From 2bb93e932969b1ba48abb1a079637fb34c8c63c2 Mon Sep 17 00:00:00 2001
From: Swami Reddy Reddy <quic_swamired@quicinc.com>
Date: Wed, 24 Jul 2024 18:53:36 +0530
Subject: [PATCH 001/290] msm: camera: sensor: TOCTOU error handling

- Proper Handling in case of invalid pinctrl index
- Removing dead code and unused variables
- Change to dereference s_ctrl only after proper
  NULL Dereference Check.

CRs-Fixed: 3875406
Change-Id: I8e2c717b22efff2a7d6503d38c048e30eff230da
Signed-off-by: Swami Reddy Reddy <quic_swamired@quicinc.com>
(cherry picked from commit 79d77de659ef7ae0727af4165c5894804ab72d60)
---
 drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c | 13 ++++++++-----
 .../cam_sensor_module/cam_sensor/cam_sensor_core.c  |  5 +++--
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c b/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c
index 5165f6b2d1c9..146967f076a9 100644
--- a/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c
+++ b/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/init.h>
@@ -379,7 +380,7 @@ static int cam_res_mgr_shared_pinctrl_select_state(
 		cam_res->pctrl_res[idx].pstatus = PINCTRL_STATUS_SUSPEND;
 	}
 
-	return 0;
+	return rc;
 }
 
 static int cam_res_mgr_add_device(struct device *dev,
@@ -577,11 +578,9 @@ static void cam_res_mgr_gpio_free(struct device *dev, uint gpio)
 	bool                   need_free = true;
 	int                    dev_num = 0;
 	struct cam_gpio_res   *gpio_res = NULL;
-	bool                   is_shared_gpio = false;
 	bool                   is_shared_pctrl_gpio = false;
 	int                    pctrl_idx = -1;
 
-	is_shared_gpio = cam_res_mgr_gpio_is_in_shared_gpio(gpio);
 	is_shared_pctrl_gpio =
 			cam_res_mgr_gpio_is_in_shared_pctrl_gpio(gpio);
 
@@ -634,8 +633,12 @@ static void cam_res_mgr_gpio_free(struct device *dev, uint gpio)
 			pctrl_idx =
 				cam_res_mgr_util_get_idx_from_shared_pctrl_gpio(
 					gpio);
-			cam_res_mgr_shared_pinctrl_select_state(
-				pctrl_idx, false);
+			if (pctrl_idx >= 0) {
+				cam_res_mgr_shared_pinctrl_select_state(
+					pctrl_idx, false);
+			} else {
+				CAM_ERR(CAM_RES, "invalid pinctrl idx: %d", pctrl_idx);
+			}
 		}
 
 		CAM_DBG(CAM_RES, "freeing gpio: %u", gpio);
diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
index 999fec038324..a31023e4101c 100644
--- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
+++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
@@ -719,13 +719,14 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl,
 {
 	int rc = 0, pkt_opcode = 0;
 	struct cam_control *cmd = (struct cam_control *)arg;
-	struct cam_sensor_power_ctrl_t *power_info =
-		&s_ctrl->sensordata->power_info;
+	struct cam_sensor_power_ctrl_t *power_info = NULL;
 	if (!s_ctrl || !arg) {
 		CAM_ERR(CAM_SENSOR, "s_ctrl is NULL");
 		return -EINVAL;
 	}
 
+	power_info = &s_ctrl->sensordata->power_info;
+
 	if (cmd->op_code != CAM_SENSOR_PROBE_CMD) {
 		if (cmd->handle_type != CAM_HANDLE_USER_POINTER) {
 			CAM_ERR(CAM_SENSOR, "Invalid handle type: %d",

From 7454ead81703738c912fd11db98bb505c8cbd571 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 17 Jul 2025 06:04:35 -0700
Subject: [PATCH 002/290] fw-api: CL 29789406 - update fw common interface
 files

Change-Id: I7e600fd9f49ab329cebc58fe9c23b30b8f601bc9
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 69eb61830fb9..8651ad5e3e95 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -37631,6 +37631,9 @@ typedef enum wmi_hw_mode_config_type {
 #define WMI_SUPPORT_11BE_GET(flags) WMI_GET_BITS(flags, 6, 1)
 #define WMI_SUPPORT_11BE_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value)
 
+#define WMI_SUPPORT_11BN_GET(flags) WMI_GET_BITS(flags, 7, 1)
+#define WMI_SUPPORT_11BN_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value)
+
 #define WMI_MAX_MUBFEE_GET(flags) WMI_GET_BITS(flags, 28, 4)
 #define WMI_MAX_MUBFEE_SET(flags, value) WMI_SET_BITS(flags, 28, 4, value)
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2c695cde4cda..10341c56ceb1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1637
+#define __WMI_REVISION_ 1638
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 20d8306516a574e32c71689d487a567423780b05 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 19 Jul 2025 06:01:34 -0700
Subject: [PATCH 003/290] fw-api: CL 29804280 - update fw common interface
 files

Change-Id: Ifbb9ea057d28fd1f4fbb7eca9a48933ef1c17c34
CRs-Fixed: 3830439
---
 fw/htt.h       |  2 ++
 fw/htt_stats.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 6e1874396d53..2c2b6cd998f7 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -866,6 +866,8 @@ typedef enum {
     HTT_STATS_TX_SELFGEN_BN_ERR_TAG                 = 220, /* htt_stats_tx_selfgen_bn_err_tlv, TOPIC=advanced */
     HTT_STATS_TX_SELFGEN_BN_TAG                     = 221, /* htt_stats_tx_selfgen_bn_tlv, TOPIC=advanced */
     HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG        = 222, /* htt_stats_tx_selfgen_bn_sched_status_tlv, TOPIC=advanced */
+    HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG      = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv, TOPIC=advanced */
+    HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG      = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv, TOPIC=advanced */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index c0730881c023..7909db9297fe 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -919,6 +919,25 @@ typedef enum {
      * TLV: htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv
      */
     HTT_UPLOAD_BE_UL_MU_OFDMA_STATS,
+
+    /*
+     * Upload BN UL MU-OFDMA + BN DL MU-OFDMA stats,
+     * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv and
+     * htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv
+     */
+    HTT_UPLOAD_BN_MU_OFDMA_STATS,
+
+    /*
+     * Upload BN DL MU-OFDMA
+     * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv
+     */
+    HTT_UPLOAD_BN_DL_MU_OFDMA_STATS,
+
+    /*
+     * Upload BN UL MU-OFDMA
+     * TLV: htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv
+     */
+    HTT_UPLOAD_BN_UL_MU_OFDMA_STATS,
 } htt_mu_stats_upload_t;
 
 /* htt_tx_rate_stats_upload_t
@@ -3135,6 +3154,7 @@ typedef enum {
 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8
 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
+#define HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS 16
 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8
 #define HTT_STATS_MAX_MUMIMO_GRP_SZ 8
 /*
@@ -4398,6 +4418,12 @@ typedef struct {
 typedef htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv
     htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /** Represents the count for 11BN DL MU OFDMA sequences */
+    A_UINT32 bn_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS];
+} htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /**
@@ -4444,6 +4470,25 @@ typedef struct {
 typedef htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv
     htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * Represents the count for 11BN UL MU OFDMA sequences with Basic Triggers
+     */
+    A_UINT32 bn_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS];
+    /**
+     * Represents the count for 11BN UL MU OFDMA sequences with BSRP Triggers
+     */
+    A_UINT32 bn_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS];
+    /**
+     * Represents the count for 11BN UL MU OFDMA sequences with BAR Triggers
+     */
+    A_UINT32 bn_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS];
+    /**
+     * TODO_BORON_OFDMA : Add array for BN_BRP number of users
+     */
+} htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /**
@@ -4530,6 +4575,7 @@ typedef htt_stats_tx_pdev_mumimo_mpdu_stats_tlv
 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */
 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE 4 /* SCHED_TX_MODE_MU_OFDMA_BE */
 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE  5 /* SCHED_TX_MODE_MU_MIMO_BE */
+#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BN 6 /* SCHED_TX_MODE_MU_OFDMA_BN */
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;

From 3586bf486b532387bdf94152064e9256b4d80a49 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 22 Jul 2025 12:01:43 -0700
Subject: [PATCH 004/290] fw-api: CL 29832217 - update fw common interface
 files

Change-Id: I46cc259ecb5de80c03492c417b8012b9e22d1c71
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 7909db9297fe..fa0740ea1e4d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -9895,6 +9895,29 @@ typedef struct {
     A_UINT32 num_terminate_seq_inefficient;
     /* Histogram of sequence inefficiency */
     A_UINT32 hist_seq_efficiency[HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM];
+    /* CTS2SELF sequences posted */
+    A_UINT32 num_cts2self_ulmumimo_seq_posted;
+    /* Number of times ULMUMIMO classification is set to high */
+    A_UINT32 num_ulmumimo_high_traffic;
+    /* Number of times ULMUMIMO classification is set to medium */
+    A_UINT32 num_ulmumimo_medium_traffic;
+    /* Number of times ULMUMIMO classification is set to low */
+    A_UINT32 num_ulmumimo_low_traffic;
+    /*
+     * Number of times ULMUMIMO sequence is terminated
+     * for high traffic classification
+     */
+    A_UINT32 num_terminate_seq_high_traffic;
+    /*
+     * Number of times ULMUMIMO sequence is terminated
+     * for medium traffic classification
+     */
+    A_UINT32 num_terminate_seq_medium_traffic;
+    /*
+     * Number of times ULMUMIMO sequence is terminated
+     * for low traffic classification
+     */
+    A_UINT32 num_terminate_seq_low_traffic;
 } htt_stats_pdev_ulmumimo_seq_term_stats_tlv;
 
 #define HTT_STATS_MAX_ULMUMIMO_TRIGGERS 6

From 6fc329eeb7b188d7ca8454cb2a65434a7b5ad79b Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 24 Jul 2025 06:01:56 -0700
Subject: [PATCH 005/290] fw-api: CL 29845167 - update fw common interface
 files

Change-Id: I05a51b5785d06c4a9aa5578b51e6ed6dbb6f0a1f
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 69 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 66 insertions(+), 3 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fa0740ea1e4d..e1a0e9ccfddc 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6163,6 +6163,19 @@ typedef struct {
         ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \
     } while (0)
 
+#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M 0x00000f00
+#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S 8
+
+#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M) >> \
+     HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S)
+
+#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S)); \
+    } while (0)
+
 #define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \
     (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \
      HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \
@@ -6230,17 +6243,33 @@ typedef enum {
 #define HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS \
     HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS
 
+typedef enum {
+    HTT_WIFI_VER_UNKNOWN = 0,
+    HTT_WIFI_VER_11N  = 4,
+    HTT_WIFI_VER_11AC = 5,
+    HTT_WIFI_VER_11AX = 6,
+    HTT_WIFI_VER_11BE = 7,
+    HTT_WIFI_VER_11BN = 8,
+} HTT_RX_TX_PDEV_STATS_WIFI_VERSION;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
     /**
      * BIT [ 7 :  0]   :- mac_id
-     * BIT [31 :  8]   :- reserved
+     * BIT [11 :  8]   :- wifi_version
+     * BIT [31 : 12]   :- reserved
      */
     union {
         struct {
-            A_UINT32 mac_id:    8,
-                     reserved: 24;
+            A_UINT32 mac_id:        8,
+                     /* wifi_version:
+                      * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value.
+                      * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET
+                      * / _SET macros for accessing this bitfield.
+                      */
+                     wifi_version:  4,
+                     reserved:     20;
         };
         A_UINT32 mac_id__word;
     };
@@ -6374,6 +6403,8 @@ typedef struct {
     A_UINT32 extra_eht_ltf_ofdma;
     /** 11AX HE UL_BA RU Size stats */
     A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS];
+    /** Number of tx 2xldpc packets */
+    A_UINT32 tx_2xldpc;
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;
@@ -6859,6 +6890,19 @@ typedef struct {
 } htt_rx_pdev_rate_stats_t;
 #endif /* ATH_TARGET */
 
+#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M 0x0000000f
+#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S 0
+
+#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M) >> \
+     HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S)
+
+#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S)); \
+    } while (0)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** units = dB above noise floor */
@@ -6888,6 +6932,25 @@ typedef struct {
     A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
     A_UINT8  rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; /* units = dB above noise floor */
     A_INT8   rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS];
+    /**
+     * BIT [ 3 :  0]   :- wifi_version
+     * BIT [31 :  4]   :- reserved
+     */
+    union {
+        struct {
+            A_UINT32
+                     /* wifi_version:
+                      * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value.
+                      * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET
+                      * / _SET macros for accessing this bitfield.
+                      */
+                     wifi_version:  4,
+                     reserved:     28;
+        };
+        A_UINT32 wifi_version__word;
+    };
+    /** Number of rx 2xldpc packets */
+    A_UINT32 rx_2xldpc;
 } htt_stats_rx_pdev_rate_ext_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv;

From cc33adea6838a09582a74fd848a6d27adca2752e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 24 Jul 2025 06:03:50 -0700
Subject: [PATCH 006/290] fw-api: CL 29858560 - update fw common interface
 files

Change-Id: I71fed562a4166c638d6ba1b5026fec3141aa8b0f
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index e1a0e9ccfddc..d412199cec52 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6405,6 +6405,7 @@ typedef struct {
     A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS];
     /** Number of tx 2xldpc packets */
     A_UINT32 tx_2xldpc;
+    A_UINT32 rc_state_probe_mismatched;
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;
@@ -8891,6 +8892,20 @@ typedef enum {
     HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2,
 } htt_stats_ru_type;
 
+typedef enum {
+    HTT_TX_PER_RATE_STATS_LOW_QUEUE_DEPTH = 0,
+    HTT_TX_PER_RATE_STATS_HIGH_QUEUE_DEPTH = 1,
+
+    HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS = 2
+} HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_TYPE;
+
+typedef enum {
+    HTT_TX_PER_RATE_STATS_MLO_RA_DD_NO_MCS_DROP = 0,
+    HTT_TX_PER_RATE_STATS_MLO_RA_DD_ONE_OR_MORE_MCS_DROP = 1,
+
+    HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS = 2
+} HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_TYPE;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -8918,6 +8933,19 @@ typedef struct {
     htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS];
 
     htt_tx_rate_stats_t per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+
+    /* mlo_ra_queue_depth_status:
+     * MLO SU Tx low/high queue depth PPDU counter,
+     *     mlo_ra_queue_depth_status[0]: lowq depth
+     *     mlo_ra_queue_depth_status[1]: high queue depth
+     */
+    A_UINT32 mlo_ra_queue_depth_status[HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS];
+    /* mlo_rate_drop_down:
+     * MLO RA MCS drop counter,
+     *     mlo_rate_drop_down[0]: No MCS drop
+     *     mlo_rate_drop_down[1]: MCS drop counter
+     */
+    A_UINT32 mlo_rate_drop_down[HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS];
 } htt_stats_per_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv;

From bcdefd35bf630886295bac6e7aac70aaac4fb5cf Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 24 Jul 2025 06:05:57 -0700
Subject: [PATCH 007/290] fw-api: CL 29858563 - update fw common interface
 files

Change-Id: I880fc389d82ecdad7737aa3d4e6d839ed7450b18
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_unified.h  | 8 ++++++++
 fw/wmi_version.h  | 2 +-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 18f2fa6085d5..0d4c95c7b34b 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -721,6 +721,7 @@ typedef  enum  {
     WMI_SERVICE_PDEV_DIV_STATES_REPORT = 460, /* FW supports reporting antenna diversity states */
     WMI_SERVICE_EAPOL_OVER_RAW = 461, /* FW supports sending EAPOL frames in raw mode even when the vdev is brought up in nwifi/ethernet mode */
     WMI_SERVICE_MLO_SAP_LINK_REMOVAL_SUPPORT = 462, /* Indicates FW supports MLO SAP link removal operation */
+    WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 180374e10227..be3a19b05664 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -8920,6 +8920,11 @@ typedef enum {
     WMI_SCHED_MODE_UL_OFDMA   = 0x00000008,
 } WMI_SCHED_MODE_FLAGS;
 
+typedef enum {
+    WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_RESET = 0,
+    WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_SET,
+} wmi_pdev_param_set_temp_tx_power_limit;
+
 typedef enum {
     /** TX chain mask */
     WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
@@ -10108,6 +10113,9 @@ typedef enum {
 
     /* configure CCE rules based on ethertype match */
     WMI_PDEV_PARAM_CONFIG_CUSTOM_CCE_RULE,
+
+    /* temporary tx power limit */
+    WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 10341c56ceb1..b22b5f74038b 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1638
+#define __WMI_REVISION_ 1639
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ec3d9208fc27e6dd40864bfde28078b5afed6913 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 25 Jul 2025 06:02:07 -0700
Subject: [PATCH 008/290] fw-api: CL 29873461 - update fw common interface
 files

Change-Id: I72ef94f77088cdc073e0da0a7cabec2e3944c87e
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 5f7bad98cb84..b81621509739 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -1940,6 +1940,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE;
         ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \
     } while (0)
 
+#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M  0x00040000
+#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S          18
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_GET(_var) \
+    (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M) >> \
+    HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S)
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_SET (_var , _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_2XLDPC, _val); \
+        ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S)); \
+    } while (0)
+
 typedef enum HTT_PPDU_STATS_RU_SIZE {
     HTT_PPDU_STATS_RU_26,
     HTT_PPDU_STATS_RU_52,
@@ -2127,11 +2140,14 @@ typedef struct {
      *                punctured.
      * BIT 16      :- flag showing whether EHT extra LTF is applied
      *                for current PPDU
+     * BIT 17      :- flag to show is_min_rate
+     * BIT 18      :- flag showing whether PPDU is transmitted with 2xLDPC
      */
     A_UINT32 punc_pattern_bitmap: 16,
              extra_eht_ltf:       1,
              is_min_rate:         1,
-             reserved4:           14;
+             is_2xldpc:           1,
+             reserved4:           13;
 } htt_ppdu_stats_user_rate_tlv;
 
 #define HTT_PPDU_STATS_USR_RATE_VALID_M     0x80000000

From 4d12925926f477071c9a049d673d748814684380 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 1 Aug 2025 06:01:46 -0700
Subject: [PATCH 009/290] fw-api: CL 29930067 - update fw common interface
 files

Change-Id: I916f1ef903c810d40cf4887e6a698731f0dea7ac
CRs-Fixed: 3830439
---
 fw/htt.h       |  3 +-
 fw/htt_stats.h | 83 ++++++++++++++++++++++++++++++++++++++------------
 2 files changed, 65 insertions(+), 21 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 2c2b6cd998f7..6e7ac5d9a6bc 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -817,7 +817,8 @@ typedef enum {
     HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG     = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */
     HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG   = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */
     HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG   = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */
-    HTT_STATS_PEER_AX_OFDMA_STATS_TAG              = 174, /* htt_peer_ax_ofdma_stats_tlv */
+    HTT_STATS_PEER_OFDMA_STATS_TAG                 = 174, /* htt_stats_peer_ofdma_stats_tlv */
+        HTT_STATS_PEER_AX_OFDMA_STATS_TAG = HTT_STATS_PEER_OFDMA_STATS_TAG, /* DEPRECATED */
     HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG     = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */
     HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG     = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */
     HTT_STATS_TX_PDEV_MLO_ABORT_TAG                = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index d412199cec52..a1e9a7d1305e 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2526,8 +2526,9 @@ typedef enum {
     HTT_RX_TID_STATS_TLV        = 5,
     HTT_MSDU_FLOW_STATS_TLV     = 6,
     HTT_PEER_SCHED_STATS_TLV    = 7,
-    HTT_PEER_AX_OFDMA_STATS_TLV = 8,
-    HTT_PEER_BE_OFDMA_STATS_TLV = 9,
+    HTT_PEER_OFDMA_STATS_TLV    = 8,
+        HTT_PEER_AX_OFDMA_STATS_TLV = HTT_PEER_OFDMA_STATS_TLV, /* DEPRECATED */
+    HTT_PEER_BE_OFDMA_STATS_TLV = 9,                            /* DEPRECATED */
 
     HTT_PEER_STATS_MAX_TLV      = 31,
 } htt_peer_stats_tlv_enum;
@@ -2550,18 +2551,46 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_peer_sched_stats_tlv htt_peer_sched_stats_tlv;
 
+/* Retaining the old structure defs for compatibility */
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 peer_id;
-    A_UINT32 ax_basic_trig_count;
-    A_UINT32 ax_basic_trig_err;
-    A_UINT32 ax_bsr_trig_count;
-    A_UINT32 ax_bsr_trig_err;
-    A_UINT32 ax_mu_bar_trig_count;
-    A_UINT32 ax_mu_bar_trig_err;
-    A_UINT32 ax_basic_trig_with_per;
-    A_UINT32 ax_bsr_trig_with_per;
-    A_UINT32 ax_mu_bar_trig_with_per;
+    union{
+        A_UINT32 ax_basic_trig_count; /* retaining the older alias */
+        A_UINT32 basic_trig_count;
+    };
+    union{
+        A_UINT32 ax_basic_trig_err; /* retaining the older alias */
+        A_UINT32 basic_trig_err;
+    };
+    union{
+        A_UINT32 ax_bsr_trig_count; /* retaining the older alias */
+        A_UINT32 bsr_trig_count;
+    };
+    union{
+        A_UINT32 ax_bsr_trig_err; /* retaining the older alias */
+        A_UINT32 bsr_trig_err;
+    };
+    union{
+        A_UINT32 ax_mu_bar_trig_count; /* retaining the older alias */
+        A_UINT32 mu_bar_trig_count;
+    };
+    union{
+        A_UINT32 ax_mu_bar_trig_err;  /* retaining the older alias */
+        A_UINT32 mu_bar_trig_err;
+    };
+    union{
+        A_UINT32 ax_basic_trig_with_per; /* retaining the older alias */
+        A_UINT32 basic_trig_with_per;
+    };
+    union{
+        A_UINT32 ax_bsr_trig_with_per;  /* retaining the older alias */
+        A_UINT32 bsr_trig_with_per;
+    };
+    union{
+        A_UINT32 ax_mu_bar_trig_with_per; /* retaining the older alias */
+        A_UINT32 mu_bar_trig_with_per;
+    };
     /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma
      * These fields contain 2 counters each.  The first element in each
      * array counts how many times the airtime is short enough to use
@@ -2573,13 +2602,22 @@ typedef struct {
     /* Last updated value of DL and UL queue depths for each peer per AC */
     A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM];
     A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM];
-    /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */
-    A_UINT32 ax_manual_ulofdma_trig_count;
-    A_UINT32 ax_manual_ulofdma_trig_err_count;
-} htt_stats_peer_ax_ofdma_stats_tlv;
-/* preserve old name alias for new name consistent with the tag name */
-typedef htt_stats_peer_ax_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv;
 
+    /* Per peer Manual UL OFDMA trigger and trigger error counts */
+    union{
+        A_UINT32 ax_manual_ulofdma_trig_count;  /* retaining the older alias */
+        A_UINT32 manual_ulofdma_trig_count;
+    };
+    union{
+        A_UINT32 ax_manual_ulofdma_trig_err_count;  /* retaining the older alias */
+        A_UINT32 manual_ulofdma_trig_err_count;
+    };
+} htt_stats_peer_ofdma_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_peer_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv;
+typedef htt_stats_peer_ofdma_stats_tlv htt_stats_peer_ax_ofdma_stats_tlv;
+
+/* DEPRECATED */
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 peer_id;
@@ -2661,7 +2699,8 @@ typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv;
  *   - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple)
  *   - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple)
  *   - HTT_STATS_PEER_SCHED_STATS_TAG
- *   - HTT_STATS_PEER_AX_OFDMA_STATS_TAG
+ *   - HTT_STATS_PEER_OFDMA_STATS_TAG / HTT_STATS_PEER_AX_OFDMA_STATS_TAG
+ *   - HTT_STATS_PEER_BE_OFDMA_STATS_TAG
  */
 /* NOTE:
  * This structure is for documentation, and cannot be safely used directly.
@@ -2680,8 +2719,12 @@ typedef struct _htt_peer_stats {
     htt_stats_peer_msdu_flowq_tlv     msdu_flowq[1];
     htt_stats_tx_tid_details_v1_tlv   tx_tid_stats_v1[1];
     htt_stats_peer_sched_stats_tlv    peer_sched_stats;
-    htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats;
-    htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats;
+    union {
+        htt_stats_peer_ofdma_stats_tlv    peer_ofdma_stats;
+        /* ax_ofdma_stats: DEPRECATED, but retained as alias */
+        htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats;
+    };
+    htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; /* DEPRECATED */
 } htt_peer_stats_t;
 #endif /* ATH_TARGET */
 

From 839e8dca93596a2ea7838b79b1f2a84f5acdc886 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 1 Aug 2025 06:04:16 -0700
Subject: [PATCH 010/290] fw-api: CL 29930068 - update fw common interface
 files

Change-Id: Iae387d912a0455ee2a4bdd88812e25b95e68162c
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 10 ++++++++--
 fw/wmi_version.h |  2 +-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index be3a19b05664..a6919ed8c20a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -51367,12 +51367,18 @@ typedef struct {
     A_UINT32 enable;
 } wmi_energy_mgmt_pcie_lpm_cmd_fixed_param;
 
+typedef enum {
+    WMI_DCVS_ENABLE,                  /* Enable Clock and Voltage Scaling */
+    WMI_DCVS_DISABLE,                 /* Disable Clock and Voltage Scaling */
+    WMI_DCVS_DISABLE_VOLTAGE_SCALING, /* Disable Only Voltage Scaling */
+} wmi_dcvs_config_e;
+
 typedef struct {
     /** TLV tag and len; tag equals
     * WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param */
     A_UINT32 tlv_header;
-    /** enable or disable DCVS config */
-    A_UINT32 enable;
+    /** DCVS config - holds a wmi_dcvs_config_e value */
+    A_UINT32 config;
 } wmi_energy_mgmt_dcvs_config_cmd_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b22b5f74038b..d80c0e214767 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1639
+#define __WMI_REVISION_ 1640
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c562f83618565b6197f877db7e461bcac75e228c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 2 Aug 2025 06:01:44 -0700
Subject: [PATCH 011/290] fw-api: CL 29948685 - update fw common interface
 files

Change-Id: I384f3e5876e3b62142ce80866e72b16366c4776b
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 129 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index a1e9a7d1305e..fbb28e151d72 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6449,6 +6449,22 @@ typedef struct {
     /** Number of tx 2xldpc packets */
     A_UINT32 tx_2xldpc;
     A_UINT32 rc_state_probe_mismatched;
+    /* npca_tx_bw: NPCA bw info
+     * element 0:  20 MHz
+     * element 1:  40 MHz
+     * element 2:  80 MHz
+     * element 3: 160 MHz
+     * element 4: 320 MHz
+     */
+    A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    /* npca_tx_su_punctured_mode: NPCA punctured mode info
+     * element 0:      no puncture
+     * element 1:  20 MHz punctured
+     * element 2:  40 MHz punctured
+     * element 3:  80 MHz punctured
+     * element 4: 120 MHz punctured
+     */
+    A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;
@@ -6995,6 +7011,8 @@ typedef struct {
     };
     /** Number of rx 2xldpc packets */
     A_UINT32 rx_2xldpc;
+    A_UINT32 npca_rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    A_UINT32 npca_rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
 } htt_stats_rx_pdev_rate_ext_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv;
@@ -8949,6 +8967,19 @@ typedef enum {
     HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS = 2
 } HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_TYPE;
 
+#define HTT_PER_RATE_STATS_WIFI_VERSION_M 0x0000000f
+#define HTT_PER_RATE_STATS_WIFI_VERSION_S 0
+
+#define HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_PER_RATE_STATS_WIFI_VERSION_M) >> \
+     HTT_PER_RATE_STATS_WIFI_VERSION_S)
+
+#define HTT_PER_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_PER_RATE_STATS_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_PER_RATE_STATS_WIFI_VERSION_S)); \
+    } while (0)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -8989,6 +9020,28 @@ typedef struct {
      *     mlo_rate_drop_down[1]: MCS drop counter
      */
     A_UINT32 mlo_rate_drop_down[HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS];
+
+    /**
+     * BIT [ 3 :  0]   :- wifi_version
+     * BIT [31 :  4]   :- reserved
+     */
+    union {
+        struct {
+            A_UINT32
+                /* wifi_version:
+                 * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value.
+                 * Refer to HTT_PER_RATE_STATS_WIFI_VERSION_GET
+                 * / _SET macros for accessing this bitfield.
+                 */
+                wifi_version:  4,
+                reserved:     28;
+        };
+        A_UINT32 wifi_version__word;
+    };
+
+    htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+
+    htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
 } htt_stats_per_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv;
@@ -13020,6 +13073,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
 #define HTT_BW_MGR_STATS_STATIC_PATTERN_M       0x00ffff00
 #define HTT_BW_MGR_STATS_STATIC_PATTERN_S       8
 
+#define HTT_BW_MGR_STATS_WIFI_VERSION_M         0x0000000f
+#define HTT_BW_MGR_STATS_WIFI_VERSION_S         0
+
 #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \
      HTT_BW_MGR_STATS_MAC_ID_S)
@@ -13034,69 +13090,103 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
 #define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \
      HTT_BW_MGR_STATS_PRI20_IDX_S)
+#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \
+     HTT_BW_MGR_STATS_PRI20_IDX_GET(_var)
 
 #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_SET(_var, _val) \
+    HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val)
 
 
 #define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \
      HTT_BW_MGR_STATS_PRI20_FREQ_S)
+#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_GET(_var) \
+    HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var)
 
 #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_SET(_var, _val) \
+    HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val)
 
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \
      HTT_BW_MGR_STATS_CENTER_FREQ1_S)
+#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_GET(_var) \
+    HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var)
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_SET(_var, _val) \
+    HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val)
 
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \
      HTT_BW_MGR_STATS_CENTER_FREQ2_S)
+#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_GET(_var) \
+    HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var)
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_SET(_var, _val) \
+    HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val)
 
 
 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \
      HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)
+#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_GET(_var) \
+    HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var)
 
 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_SET(_var, _val) \
+    HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val)
 
 
 #define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \
      HTT_BW_MGR_STATS_STATIC_PATTERN_S)
+#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \
+     HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var)
 
 #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \
     } while (0)
+#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_SET(_var, _val) \
+     HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val)
 
 
+#define HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_BW_MGR_STATS_WIFI_VERSION_M) >> \
+     HTT_BW_MGR_STATS_WIFI_VERSION_S)
+
+#define HTT_BW_MGR_STATS_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_BW_MGR_STATS_WIFI_VERSION_S)); \
+    } while (0)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -13135,6 +13225,45 @@ typedef struct {
         };
         A_UINT32 phy_mode__static_pattern;
     };
+
+    /*
+     * BIT [ 3 :  0]   :- wifi_version
+     * BIT [ 7  :  4]  :- Reserved
+     * BIT [ 15 :  8]  :- NPCA_pri20_index
+     * BIT [ 31 : 16]  :- NPCA_pri20_freq in Mhz
+     */
+    union {
+        struct {
+            A_UINT32 wifi_version        :  4;
+            A_UINT32 reserved2           :  4;
+            A_UINT32 npca_pri20_idx      :  8;
+            A_UINT32 npca_pri20_freq_mhz : 16;
+        };
+        A_UINT32 npca__wifi_version__pri20_idx__freq;
+    };
+
+    /* BIT [ 15 :  0]  :- NPCA_centre_freq1
+     * BIT [ 31 : 16]  :- NPCA_centre_freq2
+     */
+    union {
+        struct {
+            A_UINT32 npca_centre_freq1 : 16;
+            A_UINT32 npca_centre_freq2 : 16;
+        };
+        A_UINT32 npca__centre_freq1__freq2;
+    };
+
+    /* BIT [ 7 :  0]  :- NPCA_channel_phy_mode
+     * BIT [ 23 : 8]  :- NPCA_pattern
+     */
+    union {
+        struct {
+            A_UINT32 npca_phy_mode       :  8;
+            A_UINT32 npca_static_pattern : 16;
+            A_UINT32 reserved3           :  8;
+        };
+        A_UINT32 npca__phy_mode__static_pattern;
+    };
 } htt_stats_pdev_bw_mgr_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv;

From ebe06dad5dcfc3cacd58d220faa1de27a4aab638 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 9 Aug 2025 18:01:49 -0700
Subject: [PATCH 012/290] fw-api: CL 30026410 - update fw common interface
 files

Change-Id: Ia4620c9a061a985ca9e0d17a53458410f2dd7922
CRs-Fixed: 3830439
---
 fw/htt.h       |   1 +
 fw/htt_stats.h | 229 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 230 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 6e7ac5d9a6bc..2dd8162bdf83 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -869,6 +869,7 @@ typedef enum {
     HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG        = 222, /* htt_stats_tx_selfgen_bn_sched_status_tlv, TOPIC=advanced */
     HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG      = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv, TOPIC=advanced */
     HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG      = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv, TOPIC=advanced */
+    HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TAG          = 225, /* htt_stats_rx_peer_tid_reo_queue_ba_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fbb28e151d72..fc726cfdb9cf 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -186,6 +186,7 @@ enum htt_dbg_ext_stats_type {
      *           7 bit htt_peer_sched_stats_tlv
      *           8 bit htt_peer_ax_ofdma_stats_tlv
      *           9 bit htt_peer_be_ofdma_stats_tlv
+     *          10 bit htt_stats_rx_peer_tid_reo_queue_ba_tlv
      *   - config_param2: [Bit31 : Bit0] mac_addr31to0
      *   - config_param3: [Bit15 : Bit0] mac_addr47to32
      *                    [Bit 16] If this bit is set, reset per peer stats
@@ -2094,6 +2095,233 @@ typedef struct _htt_rx_tid_stats_tlv {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv;
 
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+
+    /**
+     * BIT [15: 0] : sw_peer_id
+     * BIT [31:16] : tid_num
+     */
+    union {
+        A_UINT32 sw_peer_id__tid_num;
+        struct {
+            A_UINT32 sw_peer_id : 16,
+                     tid_num    : 16;
+        };
+    };
+
+    /**
+     * BIT [11: 0] : Starting Sequence number of the session,
+     *               this changes whenever window moves
+     * BIT [21:12] : Points to last forwarded packet
+     */
+    union {
+        A_UINT32 ssn_current_index;
+        struct {
+            A_UINT32 ssn           : 12,
+                     current_index : 10,
+                     reserved_0    : 10;
+        };
+    };
+
+    /** Current PN number */
+    A_UINT32 pn_31_0;
+    A_UINT32 pn_63_32;
+    A_UINT32 pn_95_64;
+    A_UINT32 pn_127_96;
+
+    /**
+     * Timestamp of arrival of the last MPDU for this queue (in microseconds)
+     */
+    A_UINT32 last_rx_enqueue_timestamp_us;
+
+    /** Timestamp of forwarding an MPDU (in microseconds) */
+    A_UINT32 last_rx_dequeue_timestamp_us;
+
+    /** The number of MPDUs, MSDUs in the queue */
+    union {
+        A_UINT32 mpdu_msdu_cnt;
+        struct {
+            A_UINT32 current_mpdu_cnt : 16,
+                     current_msdu_cnt : 16;
+        };
+    };
+
+    /** The number of times the window moved more then 2K */
+    A_UINT32 window_jump_2k_cnt;
+
+    /**
+     * The number of times that REO started forwarding frames even though
+     * there is a hole in the bitmap.
+     * Forwarding reason is Timeout.
+     */
+    A_UINT32 timeout_cnt;
+
+    /**
+     * The number of times that REO started forwarding frames even though
+     * there is a hole in the bitmap.
+     * Forwarding reason is reception of BAR frame.
+     */
+    A_UINT32 forward_due_to_bar_cnt;
+
+    /** The number of duplicate frames that have been detected */
+    A_UINT32 duplicate_cnt;
+
+    /**
+     * The number of frames that have been received in order without a hole
+     * that prevented them from being forwarded immediately.
+     */
+    A_UINT32 frames_in_order_cnt;
+
+    /** The number of times a BAR frame is received. */
+    A_UINT32 bar_received_cnt;
+
+    /**
+     * The total number of MPDU frames that have been processed,
+     * this includes the duplicates.
+     */
+    A_UINT32 mpdu_frames_processed_cnt;
+
+    /**
+     * The total number of MSDU frames that have been processed,
+     * this includes the duplicates.
+     */
+    A_UINT32 msdu_frames_processed_cnt;
+
+    /**
+     * An approximation of the number of bytes received for
+     * this queue, in 64 byte units.
+     */
+    A_UINT32 total_processed_byte_cnt;
+
+    /** The number of MPDUs received after the window had already moved on */
+    A_UINT32 late_receive_mpdu_cnt;
+
+    /** The number of times a hole was created in the receive bitmap */
+    A_UINT32 hole_cnt;
+
+    /**
+     * The number of holes in the bitmap that moved due to aging
+     * counter expiry
+     */
+    A_UINT32 aging_drop_mpdu_cnt;
+
+    /**
+     * The number of times holes got removed from the bitmap due to
+     * aging counter expiry
+     */
+    A_UINT32 aging_drop_interval_cnt;
+
+    /** The number of ADDBA Req received */
+    A_UINT32 addba_req_cnt;
+
+    /** The number of ADDBA Resp replied for RX ADDBA Req */
+    A_UINT32 addba_resp_cnt;
+
+    /** The number of ADDBA Resp sent successfully */
+    A_UINT32 addba_rsp_success_cnt;
+
+    /** The number of ADDBA Resp sent failed */
+    A_UINT32 addba_rsp_fail_cnt;
+
+    /** The number of DELBA Req received */
+    A_UINT32 delba_req_cnt;
+
+    /** The number of DELBA Req sent successfully */
+    A_UINT32 delba_tx_success_cnt;
+
+    /** The number of DELBA Req sent failed */
+    A_UINT32 delba_tx_fail_cnt;
+
+    /** BA window size established */
+    A_UINT32 ba_win_size;
+
+    /** PN size established */
+    A_UINT32 pn_size;
+} htt_stats_rx_peer_tid_reo_queue_ba_tlv;
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_TID_DWORD_OFFSET 1
+
+/* Macros for sw_peer_id and tid_num */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_M 0x0000ffff
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S 0
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M    0xffff0000
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S    16
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S)); \
+    } while (0)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S)); \
+    } while (0)
+
+/* Macros for ssn and current_index */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M           0x00000fff
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S           0
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M 0x003ff000
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S 12
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S)); \
+    } while (0)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S)); \
+    } while (0)
+
+/* Macros for mpdu/msdu count */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M 0x0000ffff
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S 0
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M 0xffff0000
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S 16
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S)); \
+    } while (0)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) \
+    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M) >> \
+     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S)); \
+    } while (0)
+
+
 #define HTT_MAX_COUNTER_NAME 8
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -2529,6 +2757,7 @@ typedef enum {
     HTT_PEER_OFDMA_STATS_TLV    = 8,
         HTT_PEER_AX_OFDMA_STATS_TLV = HTT_PEER_OFDMA_STATS_TLV, /* DEPRECATED */
     HTT_PEER_BE_OFDMA_STATS_TLV = 9,                            /* DEPRECATED */
+    HTT_PEER_RX_REO_STATS_TLV   = 10,
 
     HTT_PEER_STATS_MAX_TLV      = 31,
 } htt_peer_stats_tlv_enum;

From f4e90ed9ad3081544c0e539c000863dc205882b9 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 10 Aug 2025 06:01:57 -0700
Subject: [PATCH 013/290] fw-api: CL 30026411 - update fw common interface
 files

Change-Id: I84fa82648b089c4e9e069720bfef3fdee38b17f9
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   1 +
 fw/wmi_tlv_defs.h |  24 ++++++++
 fw/wmi_unified.h  | 154 ++++++++++++++++++++++++++++++++++++++++++++--
 3 files changed, 175 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 0d4c95c7b34b..7d4c390a70f5 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -722,6 +722,7 @@ typedef  enum  {
     WMI_SERVICE_EAPOL_OVER_RAW = 461, /* FW supports sending EAPOL frames in raw mode even when the vdev is brought up in nwifi/ethernet mode */
     WMI_SERVICE_MLO_SAP_LINK_REMOVAL_SUPPORT = 462, /* Indicates FW supports MLO SAP link removal operation */
     WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */
+    WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 54ea736a2375..a72d22bfc0b9 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1499,6 +1499,10 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params,
     WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_co_located_chan_info,
+    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_peer_npca_cap_params,
+    WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2071,6 +2075,8 @@ typedef enum {
     OP(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID) \
     OP(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID) \
     OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \
+    OP(WMI_PDEV_NPCA_AP_CAP_CMDID) \
+    OP(WMI_PEER_NPCA_CAP_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2408,6 +2414,7 @@ typedef enum {
     OP(WMI_OPT_DP_DIAG_EVENTID) \
     OP(WMI_HW_BLACKLIST_CHAN_EVENTID) \
     OP(WMI_PDEV_SUSPEND_EVENTID) \
+    OP(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -2908,6 +2915,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_mdsuq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)
+    //WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
 
@@ -4901,6 +4909,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID);
 
+/* WMI_PDEV_NPCA_AP_CAP_CMDID */
+#define WMITLV_TABLE_WMI_PDEV_NPCA_AP_CAP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, wmi_pdev_npca_ap_cap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_NPCA_AP_CAP_CMDID);
+
 #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_update_pkt_routing_cmd_fixed_param, wmi_pdev_update_pkt_routing_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UPDATE_PKT_ROUTING_CMDID);
@@ -5128,6 +5141,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID);
 
+/* Multi Peer NPCA Capabilities command */
+#define WMITLV_TABLE_WMI_PEER_NPCA_CAP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param, wmi_peer_npca_cap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_NPCA_CAP_CMDID);
+
 /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */
 #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -7595,6 +7614,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHANNEL_ANI_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids_bitmap, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID);
 
+/* WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID */
+#define WMITLV_TABLE_WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, wmi_pdev_npca_ap_cap_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID);
+
 /* Roam scan channel list event */
 #define WMITLV_TABLE_WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_channel_list_event_fixed_param, wmi_roam_scan_channel_list_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a6919ed8c20a..b3d5f9901327 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -596,7 +596,10 @@ typedef enum {
      * for Power Boost feature
      */
     WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID,
-
+    /**
+     * WMI cmd to to Enable/Disable NPCA and its capabilities
+     */
+    WMI_PDEV_NPCA_AP_CAP_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -855,6 +858,9 @@ typedef enum {
     /** Customize MCS range for specific tid */
     WMI_PEER_TID_RATE_CUSTOM_CMDID,
 
+    /** Peer NPCA CAP Command **/
+    WMI_PEER_NPCA_CAP_CMDID,
+
     /* beacon/management specific commands */
 
     /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */
@@ -1929,6 +1935,11 @@ typedef enum {
      */
     WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID,
 
+    /*
+     * WMI_PDEV_NPCA_AP_CAP_CMDID response event
+     */
+    WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID,
+
 
     /* VDEV specific events */
     /** VDEV started event in response to VDEV_START request */
@@ -20237,6 +20248,10 @@ typedef struct {
 #define WMI_VDEV_START_RESPONSE_INCORRECT_CHANNEL_PARAMS        0x9 /** home channel params are incorrect */
 #define WMI_VDEV_START_RESPONSE_GENERIC_VDEV_START_FAILURE      0xa /** generic reason code for vdev start request reject */
 
+/** NPCA AP CAP response status code */
+#define WMI_PDEV_NPCA_AP_CAP_RESPONSE_STATUS_SUCCESS 0x0 /** NPCA Cap update Success */
+
+
 /** Beacon processing related command and event structures */
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tx_hdr */
@@ -22496,9 +22511,62 @@ typedef struct {
  *     wmi_peer_assoc_tid_to_link_map[] <-- tid to link_map info
  *     wmi_peer_assoc_operating_mode_params <-- operating mode param that
  *         host sends to AP in peer assoc req, optional TLV
+ *     wmi_peer_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA
+ *         capabilities, host sends NPCA peer capabilities as an optional TLV
  */
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_params*/
+    A_UINT32 sw_peer_id;
+    /*
+     * flags
+     * Bit0    :   NPCA Enabled/Disabled
+     *             WMI_NPCA_AP_CAP_ENABLED_GET / WMI_NPCA_AP_CAP_ENABLED_SET
+     *
+     * Bit1-3  :   NPCA Types
+     *             0:   Type1 - Two STF detectors
+     *             1:   Type2 - One STF detector
+     *             2-7: reserved for future purpose
+     *             WMI_NPCA_AP_CAP_TYPE_GET / WMI_NPCA_AP_CAP_TYPE_SET
+     *
+     * Bit4-9  :   NPCA Switch Delay
+     *             The time needed by an NPCA STA to switch from the
+     *             BSS primary channel to the NPCA primary channel,
+     *             in units of 4 us.
+     *             WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
+     *
+     * Bit10:15:   NPCA Switch Back Delay
+     *             The time needed by an NPCA STA to switch from the
+     *             NPCA primary channel to the BSS primary channel,
+     *             in units of 4 us.
+     *             WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
+     *
+     * Bit16:31:   Reserved
+    */
+    A_UINT32 npca_cap;
+} wmi_peer_npca_cap_params;
+
+#define WMI_NPCA_PEER_CAP_ENABLED_GET(_var)          WMI_GET_BITS(_var, 0, 1)
+#define WMI_NPCA_PEER_CAP_ENABLED_SET(_var, _val)    WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_NPCA_PEER_CAP_TYPE_GET(_var)             WMI_GET_BITS(_var, 1, 3)
+#define WMI_NPCA_PEER_CAP_TYPE_SET(_var, _val)       WMI_SET_BITS(_var, 1, 3, _val)
+
+#define WMI_NPCA_PEER_CAP_SWT_DELAY_GET(_var)        WMI_GET_BITS(_var, 4, 6)
+#define WMI_NPCA_PEER_CAP_SWT_DELAY_SET(_var, _val)  WMI_SET_BITS(_var, 4, 6, _val)
+
+#define WMI_NPCA_PEER_CAP_SWTB_DELAY_GET(_var)       WMI_GET_BITS(_var, 10, 6)
+#define WMI_NPCA_PEER_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 10, 6, _val)
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_params*/
+    /*
+     *  Following this structure is the TLV:
+     * struct wmi_peer_npca_cap_params peer_npca_cap_params[num_peers];
+     */
+} wmi_peer_npca_cap_cmd_fixed_param;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */
     A_UINT32 vdev_id;
@@ -47160,6 +47228,15 @@ typedef struct {
      */
 } wmi_pdev_multiple_vdev_restart_resp_event_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+    * WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 pdev_id; /* ID of the pdev this response belongs to */
+    /** Return status. As per WMI_PDEV_NPCA_AP_CAP_RESPONSE_XXXXX */
+    A_UINT32 status;
+} wmi_pdev_npca_ap_cap_resp_event_fixed_param;
+
 /** WMI event for Firmware to report soundbar audio frame statistics to Host **/
 typedef struct {
     /** TLV tag and len **/
@@ -51100,6 +51177,75 @@ typedef struct {
     A_UINT32 size;
 } wmi_pdev_power_boost_mem_addr_cmd_fixed_param;
 
+typedef struct _wmi_npca_info{
+    /* WMI Non-PrimaryChannelAccess channel
+     * Specifically, this is the "other primary" channel used if the
+     * "main primary" is occupied by low-bandwidth OBSS traffic.
+     */
+    wmi_channel npca_chan;
+    /* NPCA punctured bitmap */
+    A_UINT32 puncture_20mhz_bitmap;
+    /*
+     * flags
+     * Bit0     :  NPCA Enabled/Disabled
+     *             WMI_NPCA_AP_CAP_ENABLED_GET / WMI_NPCA_AP_CAP_ENABLED_SET
+     *
+     * Bit1-3   :  NPCA Types
+     *             0:   Type1 - Two STF detectors
+     *             1:   Type2 - One STF detector
+     *             2-7: Reserved for future purpose
+     *             WMI_NPCA_AP_CAP_TYPE_GET / WMI_NPCA_AP_CAP_TYPE_SET
+     *
+     * Bit4-9   :  NPCA Minium Threshold
+     *             The NPCA minimum duration threshold T, in units of 128
+     *             us, is T = 512 + NMDT x 128, where NMDT is the field
+     *             value, which yields a minimum of 512 us and a maximum of
+     *             2432 us. The minimum is chosen to cover at least the
+     *             transmission time of NPCA ICF and ICR exchange plus a
+     *             typical Data and Ack/BA exchange using non-HT or non-
+     *             HT duplicate PPDU format with 6 Mb/s data rate
+     *             WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET
+     *
+     * Bit10-15 :  NPCA Switch Delay
+     *             The time needed by an NPCA STA to switch from the
+     *             BSS primary channel to the NPCA primary channel,
+     *             in units of 4 us.
+     *             WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
+     *
+     * Bit16:21 :  NPCA Switch Back Delay
+     *             The time needed by an NPCA STA to switch from the
+     *             NPCA primary channel to the BSS primary channel,
+     *             in units of 4 us.
+     *             WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
+     *
+     * Bit22:31 :  Reserved
+     */
+    A_UINT32 npca_cap;
+    A_UINT32 reserved; /* reserved for future purpose */
+} wmi_npca_ap_info;
+
+typedef struct {
+    /* WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 pdev_id;
+    wmi_npca_ap_info npca_ap_info;
+} wmi_pdev_npca_ap_cap_cmd_fixed_param;
+
+#define WMI_NPCA_AP_CAP_ENABLED_GET(_var)          WMI_GET_BITS(_var, 0, 1)
+#define WMI_NPCA_AP_CAP_ENABLED_SET(_var, _val)    WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_NPCA_AP_CAP_TYPE_GET(_var)             WMI_GET_BITS(_var, 1, 3)
+#define WMI_NPCA_AP_CAP_TYPE_SET(_var, _val)       WMI_SET_BITS(_var, 1, 3, _val)
+
+#define WMI_NPCA_AP_CAP_MIN_THRES_GET(_var)        WMI_GET_BITS(_var, 4, 4)
+#define WMI_NPCA_AP_CAP_MIN_THRES_SET(_var, _val)  WMI_SET_BITS(_var, 4, 4, _val)
+
+#define WMI_NPCA_AP_CAP_SWT_DELAY_GET(_var)        WMI_GET_BITS(_var, 8, 6)
+#define WMI_NPCA_AP_CAP_SWT_DELAY_SET(_var, _val)  WMI_SET_BITS(_var, 8, 6, _val)
+
+#define WMI_NPCA_AP_CAP_SWTB_DELAY_GET(_var)       WMI_GET_BITS(_var, 14, 6)
+#define WMI_NPCA_AP_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 14, 6, _val)
+
 typedef struct {
     /* WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param */
     A_UINT32 tlv_header;
@@ -51368,9 +51514,9 @@ typedef struct {
 } wmi_energy_mgmt_pcie_lpm_cmd_fixed_param;
 
 typedef enum {
-    WMI_DCVS_ENABLE,                  /* Enable Clock and Voltage Scaling */
-    WMI_DCVS_DISABLE,                 /* Disable Clock and Voltage Scaling */
-    WMI_DCVS_DISABLE_VOLTAGE_SCALING, /* Disable Only Voltage Scaling */
+    WMI_DCVS_ENABLE,                  /* Enable clock and voltage scaling */
+    WMI_DCVS_DISABLE,                 /* Disable clock and voltage scaling */
+    WMI_DCVS_CLOCK_SCALING_ONLY,      /* Enable only clock scaling */
 } wmi_dcvs_config_e;
 
 typedef struct {

From 49edbc009ac1ca0c3673a776b9f8ec950698eb57 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 13 Aug 2025 18:01:51 -0700
Subject: [PATCH 014/290] fw-api: CL 30056543 - update fw common interface
 files

Change-Id: I623c753486cdd5996cebde6734041eddfeab277f
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 10 +++++++---
 fw/wmi_unified.h  | 12 ++++++++++++
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a72d22bfc0b9..350060dab0a5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1503,6 +1503,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_peer_npca_cap_params,
     WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_wfa_config_ml,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2915,8 +2916,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_mdsuq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)
-    //WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * No further TLVs can be added to this message;
+ * it is already at the target's WMI_MAX_NUM_TLVS limit (13).
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
 
 /* Peer Set Rate Report Condition Cmd */
@@ -5343,7 +5346,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SIMULATION_TEST_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_csa, wfa_config_csa, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ocv, wfa_config_ocv, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ml, wfa_config_ml, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_WFA_CONFIG_CMDID);
 
 /* SRG OBSS color Enable Bitmap */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b3d5f9901327..511974bea79f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -47632,6 +47632,17 @@ typedef struct {
     A_UINT32 force_he_trigger_to_eht_sta;
 } wmi_wfa_config_ofdma;
 
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_ml */
+    A_UINT32 tlv_header;
+    /* force_add_ext_mld_cap_field
+     *   Possible values from host are:
+     *   0  default behavior
+     *   1  add ext mld cap field always when connection
+     */
+    A_UINT32 force_add_ext_mld_cap_field;
+} wmi_wfa_config_ml;
+
 typedef struct {
     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_cmd_fixed_param */
     A_UINT32 tlv_header;
@@ -47643,6 +47654,7 @@ typedef struct {
      * wmi_wfa_config_ocv     wfa_config_ocv[];     (0 or 1 elements)
      * wmi_wfa_config_saquery wfa_config_saquery[]; (0 or 1 elements)
      * wmi_wfa_config_ofdma   wfa_config_ofdma[];   (0 or 1 elements)
+     * wmi_wfa_config_ml      wmi_wfa_config_ml[];  (0 or 1 elements)
      */
 } wmi_wfa_config_cmd_fixed_param;
 

From 69c4a987d7a142e0ea5e144a6892641008914d73 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 22 Aug 2025 18:01:52 -0700
Subject: [PATCH 015/290] fw-api: CL 30143205 - update fw common interface
 files

Change-Id: Ic7569cbf6aa3373643c11ccb0ef93256b2256605
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 16 ++++++++++++++++
 fw/wmi_unified.h  | 32 ++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 350060dab0a5..75c8c592e67e 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1504,6 +1504,9 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_wfa_config_ml,
+    WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_ac_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2078,6 +2081,7 @@ typedef enum {
     OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \
     OP(WMI_PDEV_NPCA_AP_CAP_CMDID) \
     OP(WMI_PEER_NPCA_CAP_CMDID) \
+    OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2416,6 +2420,7 @@ typedef enum {
     OP(WMI_HW_BLACKLIST_CHAN_EVENTID) \
     OP(WMI_PDEV_SUSPEND_EVENTID) \
     OP(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID) \
+    OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5864,6 +5869,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rate_code, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_RATE_CUSTOM_CMDID);
 
+/* pdev per-vdev queue depth report request cmd */
+#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8005,6 +8015,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_cache_info, scan_cache_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID);
 
+/* pdev per-vdev queue depth report event */
+#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_ac_info, vdev_ac_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 511974bea79f..4b0cd1ae5ad0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -600,6 +600,11 @@ typedef enum {
      * WMI cmd to to Enable/Disable NPCA and its capabilities
      */
     WMI_PDEV_NPCA_AP_CAP_CMDID,
+    /**
+     * WMI cmd to get the per-vdev, per-access-category queue pending packets
+     * for the pdev
+     */
+    WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -1940,6 +1945,9 @@ typedef enum {
      */
     WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID,
 
+    /* Event to share the per-access-category queue pending packets */
+    WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID,
+
 
     /* VDEV specific events */
     /** VDEV started event in response to VDEV_START request */
@@ -51587,6 +51595,30 @@ typedef struct {
     A_UINT32 pdev_id;
 } wmi_energy_mgmt_eco_mode_config_cmd_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param */
+    A_UINT32 pdev_id; /** pdev ID set by the command */
+} wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_ac_info */
+    A_UINT32 vdev_id;
+    /** pending_packets_per_ac:
+     *  number of MSDUs pending in MSDU and MPDU queues for the Access Category
+     *  for the specific vdev
+     */
+    A_UINT32 pending_packets_per_ac[WLAN_MAX_AC];
+} wmi_vdev_ac_info;
+
+typedef struct {
+    A_UINT32 tlv_header;     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param */
+    A_UINT32 pdev_id;        /* pdev ID set by the command */
+    /* The TLVs for the 4 AC follows with the vdev_id :
+     *     wmi_vdev_ac_info vdev_ac_info[];   wmi_vdev_ac_info for BE/BK/VI/VO
+     */
+} wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param;
+
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d80c0e214767..1ae44988418a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1640
+#define __WMI_REVISION_ 1641
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 1dd5533d7101ab28165649f3d0e56f0bfc443da4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 23 Aug 2025 18:01:41 -0700
Subject: [PATCH 016/290] fw-api: CL 30152986 - update fw common interface
 files

Change-Id: I868129f08e3dbca41ceb58c0893a34c116c1c66f
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 9 ++++++++-
 fw/wmi_version.h | 2 +-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4b0cd1ae5ad0..9fb4e8acb1f7 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19713,6 +19713,13 @@ typedef enum {
      */
     WMI_VDEV_PARAM_TWT_RESP_DISABLE,                      /* 0xC9 */
 
+    /*
+     * Enable or disable 2xLDPC in Fixed rate UHR data packet transmissions.
+     * valid values: 0 - Disable 2xLDPC, 1 - Enable 2xLDPC.
+     */
+    WMI_VDEV_PARAM_2xLDPC,                                /* 0xCA */
+
+
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
      * prone to change.
@@ -45948,7 +45955,7 @@ typedef struct {
 
 /* Bit 4~5 Group Addressed BU indication Exponent */
 #define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_GET(eht_ops) WMI_GET_BITS(eht_ops, 4, 2)
-#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_SET(eht_ops) WMI_SET_BITS(eht_ops, 4, 2, value)
+#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 4, 2, value)
 
 /* Bit 6 is for MCS15. If bit6 is 1 then we disable mcs15 */
 #define WMI_EHT_OPS_MCS15_DISABLE_GET(eht_ops) WMI_GET_BITS(eht_ops, 6, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1ae44988418a..00b462b5f47e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1641
+#define __WMI_REVISION_ 1642
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 568e1a741afbe8159e39b0643bfd2077063389a1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 29 Aug 2025 18:01:43 -0700
Subject: [PATCH 017/290] fw-api: CL 30198227 - update fw common interface
 files

Change-Id: Idb9e65de2422fa4ad0243a44d7840f62f6f1bdf5
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fc726cfdb9cf..da301df87aea 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6417,6 +6417,7 @@ typedef struct {
 #define HTT_TX_PDEV_STATS_NUM_LTF 4
 #define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6
 #define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6
+#define HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES 6
 #define HTT_TX_VDEV_STATS_NUM_SPATIAL_STREAMS 4
 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \
     (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \
@@ -6667,7 +6668,7 @@ typedef struct {
     A_UINT32 ax_su_embedded_trigger_data_ppdu;
     /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */
     A_UINT32 ax_su_embedded_trigger_data_ppdu_err;
-    /** sta side trigger stats */
+    /** STA side trigger stats */
     A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES];
     /** Stats for Extra EHT LTF */
     A_UINT32 extra_eht_ltf;
@@ -6694,6 +6695,8 @@ typedef struct {
      * element 4: 120 MHz punctured
      */
     A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+    /* STA side trigger stats */
+    A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES];
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;

From 93741ba3561262a1272dd9275d5a9dd8db060c00 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 30 Aug 2025 18:01:41 -0700
Subject: [PATCH 018/290] fw-api: CL 30201834 - update fw common interface
 files

Change-Id: I3446a6b683cfce00196eece9fac24d74e4f98d9b
CRs-Fixed: 3830439
---
 fw/htt.h       |   6 ++
 fw/htt_stats.h | 180 +++++++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 180 insertions(+), 6 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 2dd8162bdf83..e2325e3a4395 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -870,6 +870,12 @@ typedef enum {
     HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG      = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv, TOPIC=advanced */
     HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG      = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv, TOPIC=advanced */
     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TAG          = 225, /* htt_stats_rx_peer_tid_reo_queue_ba_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG                = 226, /* htt_stats_txbf_ofdma_bn_ndpa_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_NDP_TAG                 = 227, /* htt_stats_txbf_ofdma_bn_ndp_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_BRP_TAG                 = 228, /* htt_stats_txbf_ofdma_bn_brp_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_STEER_TAG               = 229, /* htt_stats_txbf_ofdma_bn_steer_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG          = 230, /* htt_stats_txbf_ofdma_bn_steer_mpdu_tlv */
+    HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG               = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index da301df87aea..a68c7236cd4f 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -694,12 +694,14 @@ enum htt_dbg_ext_stats_type {
         HTT_DBG_ODD_UL_BE_OFDMA_STATS =
             HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA,
 
-    /** HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA
+    /** HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS
      */
-    HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA = 61,
-        /* retain the deprecated name as an alias */
+    HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS = 61,
+        /* retain the deprecated names as aliases */
+        HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA =
+            HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS,
         HTT_DBG_ODD_BE_TXBF_OFDMA_STATS =
-            HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA,
+            HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS,
 
     /** HTT_DBG_EXT_STATS_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG
      * PARAMS:
@@ -1017,11 +1019,13 @@ typedef enum {
     HTT_UPLOAD_AX_TXBF_OFDMA_STATS,
 
     /*
-     * Upload 11be TXBF OFDMA stats
+     * Upload 11be and 11bn TXBF OFDMA stats
      *
      * TLV: htt_tx_pdev_be_txbf_ofdma_stats_t
      */
-    HTT_UPLOAD_BE_TXBF_OFDMA_STATS,
+    HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS,
+        /* retain previous name as alias */
+        HTT_UPLOAD_BE_TXBF_OFDMA_STATS = HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS,
 } htt_tx_pdev_txbf_ofdma_stats_upload_t;
 
 /* htt_tx_pdev_puncture_stats_upload_t
@@ -4183,6 +4187,165 @@ typedef struct {
     A_UINT32 be_ofdma_total_cv;
 } htt_stats_txbf_ofdma_be_parbw_tlv;
 
+typedef struct {
+    /** 11BN UHR OFDMA NDPA frame queued to the HW */
+    A_UINT32 bn_ofdma_ndpa_queued;
+    /** 11BN UHR OFDMA NDPA frame sent over the air */
+    A_UINT32 bn_ofdma_ndpa_tried;
+    /** 11BN UHR OFDMA NDPA frame flushed by HW */
+    A_UINT32 bn_ofdma_ndpa_flushed;
+    /** 11BN UHR OFDMA NDPA frame completed with error(s) */
+    A_UINT32 bn_ofdma_ndpa_err;
+} htt_txbf_ofdma_bn_ndpa_stats_elem_t;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * This field is populated with the num of elems in the bn_ndpa[]
+     * variable length array.
+     */
+    A_UINT32 num_elems_bn_ndpa_arr;
+    /**
+     * This field will be filled by target with value of
+     * sizeof(htt_txbf_ofdma_bn_ndpa_stats_elem_t).
+     * This is for allowing host to infer how much data target has provided,
+     * even if it using different version of the struct than what target
+     * had used.
+     */
+    A_UINT32 arr_elem_size_bn_ndpa;
+    HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndpa_stats_elem_t, bn_ndpa);
+} htt_stats_txbf_ofdma_bn_ndpa_tlv;
+
+typedef struct {
+    /** 11BN UHR OFDMA NDP frame queued to the HW */
+    A_UINT32 bn_ofdma_ndp_queued;
+    /** 11BN UHR OFDMA NDPA frame sent over the air */
+    A_UINT32 bn_ofdma_ndp_tried;
+    /** 11BN UHR OFDMA NDPA frame flushed by HW */
+    A_UINT32 bn_ofdma_ndp_flushed;
+    /** 11BN UHR OFDMA NDPA frame completed with error(s) */
+    A_UINT32 bn_ofdma_ndp_err;
+} htt_txbf_ofdma_bn_ndp_stats_elem_t;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * This field is populated with the num of elems in the bn_ndp[]
+     * variable length array.
+     */
+    A_UINT32 num_elems_bn_ndp_arr;
+    /**
+     * This field will be filled by target with value of
+     * sizeof(htt_txbf_ofdma_bn_ndp_stats_elem_t).
+     * This is for allowing host to infer how much data target has provided,
+     * even if it using different version of the struct than what target
+     * had used.
+     */
+    A_UINT32 arr_elem_size_bn_ndp;
+    HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndp_stats_elem_t, bn_ndp);
+} htt_stats_txbf_ofdma_bn_ndp_tlv;
+
+typedef struct {
+    /** 11BN UHR OFDMA MU BRPOLL frame queued to the HW */
+    A_UINT32 bn_ofdma_brpoll_queued;
+    /** 11BN UHR OFDMA MU BRPOLL frame sent over the air */
+    A_UINT32 bn_ofdma_brpoll_tried;
+    /** 11BN UHR OFDMA MU BRPOLL frame flushed by HW */
+    A_UINT32 bn_ofdma_brpoll_flushed;
+    /** 11BN UHR OFDMA MU BRPOLL frame completed with error(s) */
+    A_UINT32 bn_ofdma_brp_err;
+    /**
+     * Number of CBF(s) received when 11BN UHR OFDMA MU BRPOLL frame
+     * completed with error(s)
+     */
+    A_UINT32 bn_ofdma_brp_err_num_cbf_rcvd;
+} htt_txbf_ofdma_bn_brp_stats_elem_t;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * This field is populated with the num of elems in the bn_brp[]
+     * variable length array.
+     */
+    A_UINT32 num_elems_bn_brp_arr;
+    /**
+     * This field will be filled by target with value of
+     * sizeof(htt_txbf_ofdma_bn_brp_stats_elem_t).
+     * This is for allowing host to infer how much data target has provided,
+     * even if it using different version of the struct than what target
+     * had used
+     */
+    A_UINT32 arr_elem_size_bn_brp;
+    HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_brp_stats_elem_t, bn_brp);
+} htt_stats_txbf_ofdma_bn_brp_tlv;
+
+typedef struct {
+    /**
+     * 11BN UHR OFDMA PPDUs that were sent over the air with steering
+     * (TXBF + OFDMA)
+     */
+    A_UINT32 bn_ofdma_num_ppdu_steer;
+    /** 11BN UHR OFDMA PPDUs that were sent over the air in open loop */
+    A_UINT32 bn_ofdma_num_ppdu_ol;
+    /**
+     * 11BN UHR OFDMA number of users for which CBF prefetch was initiated
+     * to PHY HW during TX
+     */
+    A_UINT32 bn_ofdma_num_usrs_prefetch;
+    /**
+     * 11BN UHR OFDMA number of users for which sounding was initiated
+     * during TX
+     */
+    A_UINT32 bn_ofdma_num_usrs_sound;
+    /**
+     * 11BN UHR OFDMA number of users for which sounding was forced during TX
+     */
+    A_UINT32 bn_ofdma_num_usrs_force_sound;
+} htt_txbf_ofdma_bn_steer_stats_elem_t;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * This field is populated with the num of elems in the bn_steer[]
+     * variable length array.
+     */
+    A_UINT32 num_elems_bn_steer_arr;
+    /**
+     * This field will be filled by target with value of
+     * sizeof(htt_txbf_ofdma_bn_steer_stats_elem_t).
+     * This is for allowing host to infer how much data target has provided,
+     * even if it using different version of the struct than what target
+     * had used.
+     */
+    A_UINT32 arr_elem_size_bn_steer;
+    HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_steer_stats_elem_t, bn_steer);
+} htt_stats_txbf_ofdma_bn_steer_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* 11BN UHR OFDMA MPDUs tried in rbo steering */
+    A_UINT32 bn_ofdma_rbo_steer_mpdus_tried;
+    /* 11BN UHR OFDMA MPDUs failed in rbo steering */
+    A_UINT32 bn_ofdma_rbo_steer_mpdus_failed;
+    /* 11BN UHR OFDMA MPDUs tried in sifs steering */
+    A_UINT32 bn_ofdma_sifs_steer_mpdus_tried;
+    /* 11BN UHR OFDMA MPDUs failed in sifs steering */
+    A_UINT32 bn_ofdma_sifs_steer_mpdus_failed;
+} htt_stats_txbf_ofdma_bn_steer_mpdu_tlv;
+
+/* HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG stats TLV:
+ * Sent by target in response to HTT_DBG_EXT_STATS_TXBF_OFDMA stats ID request.
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* Num of UHR TxBF Partial Bandwidth soundings */
+    A_UINT32 bn_ofdma_parbw_user_snd;
+    /* Num of UHR Partial Bandwidth Sounded CVs received */
+    A_UINT32 bn_ofdma_parbw_cv;
+    /* Num of 11BN EHT Total CVs received */
+    A_UINT32 bn_ofdma_total_cv;
+} htt_stats_txbf_ofdma_bn_parbw_tlv;
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA
  * TLV_TAGS:
  *      - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG
@@ -4195,6 +4358,11 @@ typedef struct {
  *      - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG
  *      - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BN_NDP_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BN_BRP_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BN_STEER_TAG
+ *      - HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG
  */
 
 typedef struct {

From ef254fbc1898339716e89ffd659e873e57731566 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 31 Aug 2025 18:01:40 -0700
Subject: [PATCH 019/290] fw-api: CL 30201837 - update fw common interface
 files

Change-Id: Ib1f5ac9f44a2a56b6dfb2fece63dc90880da0a10
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 47 +++++++++++++++++++++++++++++++++++++++++++----
 fw/wmi_version.h |  2 +-
 2 files changed, 44 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9fb4e8acb1f7..227b0d38072d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -51459,16 +51459,40 @@ typedef struct {
     union {
         A_UINT32 peer_dyn_info2_word32;
         struct {
-            /**  1:0 pm
-             *  31:2 reserved
+            /**  0:0 pm
+             *   1:1  emlsr
+             *  17:2  padding_delay
+             *  26:18 transition_delay
+             *  30:27 transition_timeout
+             *  31    Reserved
              */
             A_UINT32
-                pm   : 1,
-                rsvd : 31;
+                pm                   :  1,
+                emlsr                :  1,
+                padding_delay_us     : 16,
+                transition_delay_us  :  9,
+                transition_timeout_us:  4,
+                rsvd1                :  1;
+        };
+    };
+    union {
+        A_UINT32 peer_dyn_info3_word32;
+        struct {
+            /** 13:0 link_bitmap
+             *  31:15 Reserved
+             */
+            A_UINT32
+                link_bitmap: 14,
+                rsvd2      : 18;
         };
     };
 } wmi_vdev_vbss_peer_dyn_info;
 
+typedef enum {
+    WMI_VBSS_UNICAST_PN_INFO         = 1,
+    WMI_VBSS_MULTICAST_PN_INFO       = 2,
+} wmi_vbss_pn_ctxt_id;
+
 typedef enum {
     WMI_VBSS_GET_PEER_CONTEXT        = 1,
     WMI_VBSS_SET_PEER_CONTEXT        = 2,
@@ -51496,6 +51520,21 @@ typedef enum {
 #define WMI_VDEV_VBSS_DYN_INFO_GET_PM(peer_dyn_info2) WMI_GET_BITS(pm, 0, 1)
 #define WMI_VDEV_VBSS_DYN_INFO_SET_PM(peer_dyn_info2, value) WMI_SET_BITS(pm, 0, 1, value)
 
+#define WMI_VDEV_VBSS_DYN_INFO_GET_EMLSR(peer_dyn_info2) WMI_GET_BITS(emlsr, 1, 1)
+#define WMI_VDEV_VBSS_DYN_INFO_SET_EMLSR(peer_dyn_info2, value) WMI_SET_BITS(emlsr, 1, 1, value)
+
+#define WMI_VDEV_VBSS_DYN_INFO_GET_PADDING_DELAY(peer_dyn_info2) WMI_GET_BITS(padding_delay, 2, 16)
+#define WMI_VDEV_VBSS_DYN_INFO_SET_PADDING_DELAY(peer_dyn_info2, value) WMI_SET_BITS(padding_delay, 2, 16, value)
+
+#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_DELAY(peer_dyn_info2) WMI_GET_BITS(transition_delay, 18, 9)
+#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_DELAY(peer_dyn_info2, value) WMI_SET_BITS(transition_delay, 18, 9, value)
+
+#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_TIMEOUT(peer_dyn_info2) WMI_GET_BITS(transition_timeout, 27, 4)
+#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_TIMEOUT(peer_dyn_info2, value) WMI_SET_BITS(transition_timeout, 27, 4, value)
+
+#define WMI_VDEV_VBSS_DYN_INFO_GET_LINK_BITMAP(peer_dyn_info3) WMI_GET_BITS(link_bitmap, 0, 14)
+#define WMI_VDEV_VBSS_DYN_INFO_SET_LINK_BITMAP(peer_dyn_info3, value) WMI_SET_BITS(link_bitmap, 0, 14, value)
+
 
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 00b462b5f47e..55a4db0dffb4 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1642
+#define __WMI_REVISION_ 1643
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f6b3356d4361857233ab147908676d7329fa5ddc Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 2 Sep 2025 18:01:42 -0700
Subject: [PATCH 020/290] fw-api: CL 30227097 - update fw common interface
 files

Change-Id: I8a4e67b9c37cd77ce59f5907ce4ca0a665df8198
CRs-Fixed: 3830439
---
 fw/wlan_defs.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h
index 823b8ec9fedf..fa31d27e763b 100755
--- a/fw/wlan_defs.h
+++ b/fw/wlan_defs.h
@@ -270,6 +270,13 @@ typedef enum {
         ((mode) == MODE_11BE_EHT320)    || \
         ((mode) == MODE_11BE_EHT20_2G)  || \
         ((mode) == MODE_11BE_EHT40_2G))
+#define IS_MODE_EHT_5G_6G(mode) (((mode) == MODE_11BE_EHT20) || \
+        ((mode) == MODE_11BE_EHT40)     || \
+        ((mode) == MODE_11BE_EHT80)     || \
+        ((mode) == MODE_11BE_EHT80_80)  || \
+        ((mode) == MODE_11BE_EHT160)    || \
+        ((mode) == MODE_11BE_EHT160_160)|| \
+        ((mode) == MODE_11BE_EHT320))
 #define IS_MODE_EHT_2G(mode) (((mode) == MODE_11BE_EHT20_2G) || \
         ((mode) == MODE_11BE_EHT40_2G))
 #endif /* SUPPORT_11BE */
@@ -284,6 +291,13 @@ typedef enum {
         ((mode) == MODE_11BN_UHR320)    || \
         ((mode) == MODE_11BN_UHR20_2G)  || \
         ((mode) == MODE_11BN_UHR40_2G))
+#define IS_MODE_UHR_5G_6G(mode) (((mode) == MODE_11BN_UHR20) || \
+        ((mode) == MODE_11BN_UHR40)     || \
+        ((mode) == MODE_11BN_UHR80)     || \
+        ((mode) == MODE_11BN_UHR80_80)  || \
+        ((mode) == MODE_11BN_UHR160)    || \
+        ((mode) == MODE_11BN_UHR160_160)|| \
+        ((mode) == MODE_11BN_UHR320))
 #define IS_MODE_UHR_2G(mode) (((mode) == MODE_11BN_UHR20_2G) || \
         ((mode) == MODE_11BN_UHR40_2G))
 #endif /* SUPPORT_11BN */

From b986f01538651beb25ff98c9a4ca9aab4c9a6159 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 3 Sep 2025 18:01:45 -0700
Subject: [PATCH 021/290] fw-api: CL 30231044 - update fw common interface
 files

Change-Id: Ib592d8c7a3a363ed0b397d1d12d64d31b70724ef
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 227b0d38072d..8689f00fc002 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -50362,6 +50362,7 @@ typedef enum _WMI_VDEV_PAUSE_TYPE
     WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1,
     WMI_VDEV_PAUSE_TYPE_TX = 2,
     WMI_VDEV_PAUSE_TYPE_TX_DATA = 3,
+    WMI_VDEV_PAUSE_TYPE_TX_RX = 4,
 } WMI_VDEV_PAUSE_TYPE;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 55a4db0dffb4..e5b46e612e9e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1643
+#define __WMI_REVISION_ 1644
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e575855950520ed576cec3c212d429146737fab3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 4 Sep 2025 18:01:42 -0700
Subject: [PATCH 022/290] fw-api: CL 30243121 - update fw common interface
 files

Change-Id: Ia29290e939824732c6fe3ddf044967674b507b23
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 14 ++++++++++++++
 fw/wmi_unified.h  | 20 ++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 75c8c592e67e..d481cdc7e3ed 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1507,6 +1507,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_ac_info,
+    WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2082,6 +2084,7 @@ typedef enum {
     OP(WMI_PDEV_NPCA_AP_CAP_CMDID) \
     OP(WMI_PEER_NPCA_CAP_CMDID) \
     OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
+    OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2421,6 +2424,7 @@ typedef enum {
     OP(WMI_PDEV_SUSPEND_EVENTID) \
     OP(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID) \
     OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \
+    OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5056,6 +5060,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RUNTIME_DPD_RECAL_CMDID);
 
 WMITLV_CREATE_PARAM_STRUC(WMI_GET_TPC_POWER_CMDID);
 
+/** Get TPC IE TX power value */
+#define WMITLV_TABLE_WMI_VDEV_GET_TPC_IE_POWER_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param, wmi_vdev_get_tpc_ie_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
+
 /* TWT enable cmd */
 #define WMITLV_TABLE_WMI_TWT_ENABLE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param, wmi_twt_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -7185,6 +7195,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tpc, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_EVENTID);
 
+#define WMITLV_TABLE_WMI_VDEV_TPC_IE_POWER_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param, wmi_vdev_tpc_ie_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TPC_IE_POWER_EVENTID);
+
 #define WMITLV_TABLE_WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, wmi_pdev_nfcal_power_all_channels_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBr, nfdbr, WMITLV_SIZE_VAR) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8689f00fc002..198ded26b376 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -732,6 +732,7 @@ typedef enum {
 
     WMI_VDEV_VBSS_CONFIG_CMDID,
 
+    WMI_VDEV_GET_TPC_IE_POWER_CMDID,
 
     /* peer specific commands */
 
@@ -2028,6 +2029,7 @@ typedef enum {
     /** Connect response */
     WMI_VDEV_OOB_CONNECTION_RESP_EVENTID,
     WMI_VDEV_VBSS_CONFIG_EVENTID,
+    WMI_VDEV_TPC_IE_POWER_EVENTID,
 
     /* peer specific events */
     /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */
@@ -10315,6 +10317,23 @@ typedef struct {
     A_UINT32 param;
 } wmi_pdev_get_tpc_config_cmd_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param */
+    /** pdev_id for identifying the MAC
+     * See macros starting with WMI_PDEV_ID_ for values.
+     */
+    A_UINT32 pdev_id;
+    A_UINT32 vdev_id;
+    A_UINT32 mgmt_rate; /* Values are sent as Ratecode */
+} wmi_vdev_get_tpc_ie_power_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param */
+    A_UINT32 pdev_id;
+    A_UINT32 vdev_id;
+    A_INT32 tx_pwr; /* return value will be in unit of 0.25 dBm */
+} wmi_vdev_tpc_ie_power_event_fixed_param;
+
 typedef struct {
     A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_pdev_div_get_rssi_antid_fixed_param */
     /** pdev_id for identifying the MAC */
@@ -39613,6 +39632,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index e5b46e612e9e..b33e4c99c96f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1644
+#define __WMI_REVISION_ 1645
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3cd625c2e2c7fd2d560212a019e11191fb2c8ea3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 5 Sep 2025 18:01:51 -0700
Subject: [PATCH 023/290] fw-api: CL 30269010 - update fw common interface
 files

Change-Id: I169ff6f34a34fc11f3f0c79df6c5cc2726a12060
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  4 ++-
 fw/wmi_unified.h  | 62 ++++++++++++++++++++++++++++++-----------------
 fw/wmi_version.h  |  2 +-
 3 files changed, 44 insertions(+), 24 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d481cdc7e3ed..6ab6a25d3aa4 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1509,6 +1509,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_ac_info,
     WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -6506,7 +6507,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWFDA_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_extd_stats, vdev_extd_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_extd_stats, pdev_extd_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_telemetry_stats, pdev_telemetry_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_recv_bcn_stats, recv_bcn_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_recv_bcn_stats, recv_bcn_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_coex_stats, coex_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID);
 
 /* Update PN response Event */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 198ded26b376..ab8da0944494 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10137,6 +10137,9 @@ typedef enum {
 
     /* temporary tx power limit */
     WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT,
+
+    /* configure pdev coex stats period (millisecond units) */
+    WMI_PDEV_PARAM_COEX_STATS_UPDATE_PERIOD,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -11269,26 +11272,27 @@ typedef struct {
 } wmi_vdev_get_twt_session_stats_info_cmd_fixed_param;
 
 typedef enum {
-    WMI_REQUEST_PEER_STAT            = 0x00001,
-    WMI_REQUEST_AP_STAT              = 0x00002,
-    WMI_REQUEST_PDEV_STAT            = 0x00004,
-    WMI_REQUEST_VDEV_STAT            = 0x00008,
-    WMI_REQUEST_BCNFLT_STAT          = 0x00010,
-    WMI_REQUEST_VDEV_RATE_STAT       = 0x00020,
-    WMI_REQUEST_INST_STAT            = 0x00040,
-    WMI_REQUEST_MIB_STAT             = 0x00080,
-    WMI_REQUEST_RSSI_PER_CHAIN_STAT  = 0x00100,
-    WMI_REQUEST_CONGESTION_STAT      = 0x00200,
-    WMI_REQUEST_PEER_EXTD_STAT       = 0x00400,
-    WMI_REQUEST_BCN_STAT             = 0x00800,
-    WMI_REQUEST_BCN_STAT_RESET       = 0x01000,
-    WMI_REQUEST_PEER_EXTD2_STAT      = 0x02000,
-    WMI_REQUEST_MIB_EXTD_STAT        = 0x04000,
-    WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x08000,
-    WMI_REQUEST_VDEV_EXTD_STAT       = 0x10000,
-    WMI_REQUEST_PDEV_EXTD_STAT       = 0x20000,
-    WMI_REQUEST_PDEV_TELEMETRY_STAT  = 0x40000,
-    WMI_REQUEST_VDEV_RECV_BCN_STAT   = 0x80000,
+    WMI_REQUEST_PEER_STAT            = 0x000001,
+    WMI_REQUEST_AP_STAT              = 0x000002,
+    WMI_REQUEST_PDEV_STAT            = 0x000004,
+    WMI_REQUEST_VDEV_STAT            = 0x000008,
+    WMI_REQUEST_BCNFLT_STAT          = 0x000010,
+    WMI_REQUEST_VDEV_RATE_STAT       = 0x000020,
+    WMI_REQUEST_INST_STAT            = 0x000040,
+    WMI_REQUEST_MIB_STAT             = 0x000080,
+    WMI_REQUEST_RSSI_PER_CHAIN_STAT  = 0x000100,
+    WMI_REQUEST_CONGESTION_STAT      = 0x000200,
+    WMI_REQUEST_PEER_EXTD_STAT       = 0x000400,
+    WMI_REQUEST_BCN_STAT             = 0x000800,
+    WMI_REQUEST_BCN_STAT_RESET       = 0x001000,
+    WMI_REQUEST_PEER_EXTD2_STAT      = 0x002000,
+    WMI_REQUEST_MIB_EXTD_STAT        = 0x004000,
+    WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x008000,
+    WMI_REQUEST_VDEV_EXTD_STAT       = 0x010000,
+    WMI_REQUEST_PDEV_EXTD_STAT       = 0x020000,
+    WMI_REQUEST_PDEV_TELEMETRY_STAT  = 0x040000,
+    WMI_REQUEST_VDEV_RECV_BCN_STAT   = 0x080000,
+    WMI_REQUEST_PDEV_COEX_STAT       = 0x100000,
 } wmi_stats_id;
 
 /*
@@ -11306,7 +11310,7 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param */
-    wmi_stats_id stats_id;
+    A_UINT32 stats_id; /* wmi_stats_id */
     /** unique id identifying the VDEV, generated by the caller */
     A_UINT32 vdev_id;
     /** peer MAC address */
@@ -12211,7 +12215,7 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */
-    wmi_stats_id stats_id;
+    A_UINT32 stats_id; /* wmi_stats_id */
     /** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */
     A_UINT32 num_pdev_stats;
     /** number of vdev stats event structures  (wmi_vdev_stats) 0 or max vdevs */
@@ -12283,6 +12287,10 @@ typedef struct {
  * wmi_recv_bcn_stats wmi_recv_bcn_stats[]
  * follows the other TLVs
  */
+/* If WMI_REQUEST_PDEV_COEX_STAT is set in stats_id, then TLV
+ * wmi_pdev_coex_stats wmi_pdev_coex_stats[]
+ * follows the other TLVs
+ */
 } wmi_stats_event_fixed_param;
 
 /* WLAN channel CCA stats bitmap  */
@@ -15711,6 +15719,16 @@ typedef struct {
     A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */
 } wmi_bcn_stats;
 
+/*
+ * pdev coex stats
+ */
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_coex_stats */
+    A_UINT32 pdev_id;
+    A_UINT32 cur_btc_mode; /* 0 - TDD; 1 - FDD; 2 - Hybrid; 3 - DBAM */
+    A_UINT32 cur_btc_policy; /* 0 - FR; */
+} wmi_pdev_coex_stats;
+
 #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0
 #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \
     (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b33e4c99c96f..d599a75debd6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1645
+#define __WMI_REVISION_ 1646
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 94cd5fcee0692640c6b82cf4965725b9365c1daa Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 6 Sep 2025 18:01:43 -0700
Subject: [PATCH 024/290] fw-api: CL 30273613 - update fw common interface
 files

Change-Id: If31776cbccc95b55d9e0c36213eeb63c19bd88f9
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index b81621509739..5fb291122195 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -1953,6 +1953,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE;
         ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S)); \
     } while (0)
 
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M  0x00080000
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S          19
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_GET(_var) \
+    (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M) >> \
+    HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S)
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_SET (_var , _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED, _val); \
+        ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S)); \
+    } while (0)
+
 typedef enum HTT_PPDU_STATS_RU_SIZE {
     HTT_PPDU_STATS_RU_26,
     HTT_PPDU_STATS_RU_52,
@@ -2142,12 +2155,14 @@ typedef struct {
      *                for current PPDU
      * BIT 17      :- flag to show is_min_rate
      * BIT 18      :- flag showing whether PPDU is transmitted with 2xLDPC
+     * BIT 19      :- flag showing whether PPDU is transmitted with NPCA enabled
      */
     A_UINT32 punc_pattern_bitmap: 16,
-             extra_eht_ltf:       1,
-             is_min_rate:         1,
-             is_2xldpc:           1,
-             reserved4:           13;
+             extra_eht_ltf:        1,
+             is_min_rate:          1,
+             is_2xldpc:            1,
+             is_npca_enabled:      1,
+             reserved4:           12;
 } htt_ppdu_stats_user_rate_tlv;
 
 #define HTT_PPDU_STATS_USR_RATE_VALID_M     0x80000000

From 82673d2ac8fe665b2a3e287d189a04eab1c469df Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 6 Sep 2025 18:03:25 -0700
Subject: [PATCH 025/290] fw-api: CL 30273614 - update fw common interface
 files

Change-Id: I8eab05f803f54f975f8366f0efcbdec9f61f43fd
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ab8da0944494..b2199a51e14b 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -42708,6 +42708,7 @@ typedef enum wmi_roam_invoke_status_error {
     WMI_ROAM_INVOKE_STATUS_INVALID_SCAN_MODE,      /* Roam scan mode is invalid */
     WMI_ROAM_INVOKE_STATUS_NO_CAND_AP,             /* No candidate AP found to roam to */
     WMI_ROAM_INVOKE_STATUS_HO_FAIL,                /* handoff failed */
+    WMI_ROAM_INVOKE_STATUS_SUSTAIN_CONN,           /* Sustain existing connection when MLD self roaming fails */
 } wmi_roam_invoke_status_error_t;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d599a75debd6..0bbafda5f88c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1646
+#define __WMI_REVISION_ 1647
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From bd1756641a23744b216fc7c6263194d966c4db5a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 8 Sep 2025 18:01:53 -0700
Subject: [PATCH 026/290] fw-api: CL 30281577 - update fw common interface
 files

Change-Id: If11381597e1ad0f68bbff9c740340afd56395ee5
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 8 ++++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b2199a51e14b..39e6ad674bfb 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -26992,6 +26992,14 @@ typedef enum
      */
     WMI_VENDOR_OUI_ACTION_DISABLE_DYNAMIC_SMPS = 18,
 
+    /*
+     * Keep sending qos null frame on P2P interface when final bmiss is
+     * detected, if specific vendor OUI matches.
+     * If an ACK is received, suppress reporting the final beacon miss
+     * to the host to avoid triggering a disconnect.
+     */
+    WMI_VENDOR_OUI_ACTION_FORCE_TX_NULL_FRAME_ON_P2P = 19,
+
 
     /* Add any action before this line */
     WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0bbafda5f88c..1096d6556d1f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1647
+#define __WMI_REVISION_ 1648
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3382f0831d5527d38eb8f86e0fa23138a0268ec9 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 9 Sep 2025 18:01:44 -0700
Subject: [PATCH 027/290] fw-api: CL 30297480 - update fw common interface
 files

Change-Id: Ibe8992f54342d37e93a38c1fc31840e3832bfccc
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 4 ++--
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 39e6ad674bfb..2b4d2ed80aaa 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10322,18 +10322,18 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param */
+    A_UINT32 vdev_id;
     /** pdev_id for identifying the MAC
      * See macros starting with WMI_PDEV_ID_ for values.
      */
     A_UINT32 pdev_id;
-    A_UINT32 vdev_id;
     A_UINT32 mgmt_rate; /* Values are sent as Ratecode */
 } wmi_vdev_get_tpc_ie_power_cmd_fixed_param;
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param */
-    A_UINT32 pdev_id;
     A_UINT32 vdev_id;
+    A_UINT32 pdev_id;
     A_INT32 tx_pwr; /* return value will be in unit of 0.25 dBm */
 } wmi_vdev_tpc_ie_power_event_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1096d6556d1f..8cfd774b4f7f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1648
+#define __WMI_REVISION_ 1649
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 273666bb99410377fd67222bfbdb963af1afd2bc Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 13 Sep 2025 18:01:29 -0700
Subject: [PATCH 028/290] fw-api: CL 30358561 - update fw common interface
 files

Change-Id: Iae2e79e0dffab1b0dc77d8f9a2a4bbc45de21d2a
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h | 28 ++++++++++++++++++++++++++++
 fw/wmi_unified.h  | 46 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 7d4c390a70f5..d418bd21b1ac 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -723,6 +723,7 @@ typedef  enum  {
     WMI_SERVICE_MLO_SAP_LINK_REMOVAL_SUPPORT = 462, /* Indicates FW supports MLO SAP link removal operation */
     WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */
     WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */
+    WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 6ab6a25d3aa4..e078c310b074 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -2086,6 +2086,7 @@ typedef enum {
     OP(WMI_PEER_NPCA_CAP_CMDID) \
     OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
+    OP(WMI_PEER_ASSOC_V2_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2929,9 +2930,36 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID);
 /* NOTE:
  * No further TLVs can be added to this message;
  * it is already at the target's WMI_MAX_NUM_TLVS limit (13).
+ *
+ * Note that the WMI_PEER_ASSOC_V2_CMDID (below) can support additional TLVs.
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
 
+/* Peer Assoc EXT Cmd
+ * This cmd message mirrors the WMI_PEER_ASSOC_CMDID message, but has the
+ * capacity for extra TLVs beyond those in the WMI_PEER_ASSOC_CMDID definition.
+ * This message can only be used if the target advertises support for
+ * WMI_MAX_NUM_EXT_TLVS (via the WMI_SERVICE_EXT_TLV_SUPPORT flag).
+ */
+#define WMITLV_TABLE_WMI_PEER_ASSOC_V2_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_legacy_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_ht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_vht_rates, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_he_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_eht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_mdsuq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
+
 /* Peer Set Rate Report Condition Cmd */
 #define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2b4d2ed80aaa..e535a515575c 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -115,6 +115,8 @@ extern "C" {
         }
 #endif
 
+#define WMI_MAX_NUM_EXT_TLVS 50
+
 #define ATH_MAC_LEN             6               /**< length of MAC in bytes */
 #define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */
 #define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */
@@ -867,6 +869,9 @@ typedef enum {
     /** Peer NPCA CAP Command **/
     WMI_PEER_NPCA_CAP_CMDID,
 
+    /* WMI_PEER_ASSOC_V2_CMDID: extended alternative for WMI_PEER_ASSOC_CMDID */
+    WMI_PEER_ASSOC_V2_CMDID,
+
     /* beacon/management specific commands */
 
     /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */
@@ -22410,13 +22415,23 @@ typedef struct {
 #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_GET(assoc_flags) WMI_GET_BITS(assoc_flags, 0, 1)
 #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_SET(assoc_flags, value) WMI_GET_BITS(assoc_flags, 0, 1, value)
 
+enum wmi_peer_new_assoc {
+    WMI_PEER_REASSOC = 0,      /* Peer Reassoc */
+    WMI_PEER_ASSOC = 1,        /* Peer Assoc */
+    WMI_PEER_CREATE_ASSOC = 2, /* Peer Create and Peer Assoc in single command,
+                                * currently used for SMD case */
+
+    /* Host <-> Target Peer New Assoc is assigned up to 127 */
+    WMI_PEER_NEW_ASSOC_MAX = 127
+};
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */
     /** peer MAC address */
     wmi_mac_addr peer_macaddr;
     /** VDEV id */
     A_UINT32 vdev_id;
-    /** assoc = 1 reassoc = 0 */
+    /* enum wmi_peer_new_assoc: create_assoc = 2, assoc = 1, reassoc = 0 */
     A_UINT32 peer_new_assoc;
     /** peer associd (16 bits) */
     A_UINT32 peer_associd;
@@ -22550,6 +22565,23 @@ typedef struct {
      */
     A_UINT32 max_downlink_nss;
 
+    /** Peer create flags */
+    union {
+        struct {
+            A_UINT32 hw_peer_id_valid : 1,
+                     peer_type_valid  : 1,
+                     reserved         :30;
+        };
+        A_UINT32 flags;
+    };
+    /** Global sw peer id, valid only if non-zero */
+    A_UINT32 sw_peer_id;
+    /** Global hardware id, valid only if hw_peer_id_valid is set */
+    A_UINT32 hw_peer_id;
+    /** peer type: see enum values above */
+    A_UINT32 peer_type;
+
+
 /* Following this struct are the TLV's:
  *     A_UINT8 peer_legacy_rates[];
  *     A_UINT8 peer_ht_rates[];
@@ -22563,11 +22595,23 @@ typedef struct {
  *     wmi_peer_assoc_tid_to_link_map[] <-- tid to link_map info
  *     wmi_peer_assoc_operating_mode_params <-- operating mode param that
  *         host sends to AP in peer assoc req, optional TLV
+ * --- the below only apply to WMI_PEER_ASSOC_V2_CMD, not WMI_PEER_ASSOC_CMDID
  *     wmi_peer_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA
  *         capabilities, host sends NPCA peer capabilities as an optional TLV
+ *     wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create
+ *         Optional TLV, only present for MLO peers.
+ *         If the peer is non-MLO, the array length should be 0.
+ *         Only mlo_enable flag required by MCC to decide MAC address
+ *         to be used.
  */
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_GET(flags) WMI_GET_BITS(flags, 0, 1)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_SET(flags, value) WMI_GET_BITS(flags, 0, 1, value)
+
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_GET(flags) WMI_GET_BITS(flags, 1, 1)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_GET_BITS(flags, 1, 1, value)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_params*/
     A_UINT32 sw_peer_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8cfd774b4f7f..60ece38126f3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1649
+#define __WMI_REVISION_ 1650
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From eae05969a4514fbedc7890d88cdb733ce6427b3d Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Sep 2025 18:04:04 -0700
Subject: [PATCH 029/290] fw-api: CL 30387120 - update fw common interface
 files

Change-Id: Ibe9228bfff8e54b8845a33540f44a87d84594b71
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  9 ++++++++-
 fw/wmi_unified.h  | 16 ++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index d418bd21b1ac..7279a9619c30 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -724,6 +724,7 @@ typedef  enum  {
     WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */
     WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */
     WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */
+    WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index e078c310b074..d05bebf83f93 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1510,6 +1510,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
+    WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2087,6 +2088,7 @@ typedef enum {
     OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
     OP(WMI_PEER_ASSOC_V2_CMDID) \
+    OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2935,7 +2937,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID);
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
 
-/* Peer Assoc EXT Cmd
+/* WMI_PEER_ASSOC_V2_CMD - version 2 of the PEER_ASSOC cmd, allowing more TLVs
  * This cmd message mirrors the WMI_PEER_ASSOC_CMDID message, but has the
  * capacity for extra TLVs beyond those in the WMI_PEER_ASSOC_CMDID definition.
  * This message can only be used if the target advertises support for
@@ -5913,6 +5915,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_RATE_CUSTOM_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID);
 
+/* vdev traffic monitoring request cmd */
+#define WMITLV_TABLE_WMI_VDEV_TRAFFIC_MONITORING_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, wmi_vdev_traffic_monitoring_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e535a515575c..8d2781c8d5df 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -736,6 +736,9 @@ typedef enum {
 
     WMI_VDEV_GET_TPC_IE_POWER_CMDID,
 
+    /** data traffic monitoring */
+    WMI_VDEV_TRAFFIC_MONITORING_CMDID,
+
     /* peer specific commands */
 
     /** create a peer */
@@ -39703,6 +39706,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -51756,6 +51760,18 @@ typedef struct {
      */
 } wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* VDEV identifier */
+    A_UINT32 vdev_id;
+    /** TX RX packet count threshold value */
+    A_UINT32 data_threshold;
+    /** duration of traffic monitoring, in unit of sec */
+    A_UINT32 traffic_monitoring_time;
+} wmi_vdev_traffic_monitoring_cmd_fixed_param;
+
 
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 60ece38126f3..8ad871d44164 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1650
+#define __WMI_REVISION_ 1651
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From fbb17f9e31baa84d420396dc97add4217dcf39d8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Sep 2025 18:05:38 -0700
Subject: [PATCH 030/290] fw-api: CL 30391907 - update fw common interface
 files

Change-Id: I456860f44057854cea82b95df635d658b92108d6
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  7 +++++++
 fw/wmi_unified.h  | 15 +++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 7279a9619c30..670a018a3abf 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -725,6 +725,7 @@ typedef  enum  {
     WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */
     WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */
     WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */
+    WMI_SERVICE_EM_DPS_ASSISTING_ROLE_SUPPORT = 467, /* Indicates support for Energy Mgmt DPS assisting role operation */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d05bebf83f93..6bba216cecbb 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1511,6 +1511,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
     WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2089,6 +2090,7 @@ typedef enum {
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
     OP(WMI_PEER_ASSOC_V2_CMDID) \
     OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \
+    OP(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -5920,6 +5922,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, wmi_vdev_traffic_monitoring_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
 
+/* WMI command to control Dynamic Power Save - AP Assisting role config */
+#define WMITLV_TABLE_WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8d2781c8d5df..f0cd6dde0634 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1767,6 +1767,8 @@ typedef enum {
     WMI_ENERGY_MGMT_PUO_CONFIG_CMDID,
     /** WMI cmd used to control ECO mode config */
     WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID,
+    /** WMI cmd used to control DPS Assisting AP role config */
+    WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID,
 } WMI_CMD_ID;
 
 typedef enum {
@@ -39707,6 +39709,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
+        WMI_RETURN_STRING(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -51772,6 +51775,18 @@ typedef struct {
     A_UINT32 traffic_monitoring_time;
 } wmi_vdev_traffic_monitoring_cmd_fixed_param;
 
+typedef enum {
+    WMI_DPS_ASSISTING_ROLE_DISABLE, /* Disable - DPS: AP Assisting role */
+    WMI_DPS_ASSISTING_ROLE_ENABLE,  /* Enable  - DPS: AP Assisting role */
+} wmi_dps_assisting_role_e;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+    * WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** holds a wmi_dps_assisting_role_e value */
+    A_UINT32 config;
+} wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param;
 
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8ad871d44164..44fad6cbdaaa 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1651
+#define __WMI_REVISION_ 1652
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 7c336edf7e6ac9ff978382751d324cf50b033c41 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 20 Sep 2025 18:01:31 -0700
Subject: [PATCH 031/290] fw-api: CL 30443155 - update fw common interface
 files

Change-Id: I9eaaaca3c45e7da16691226d93dc5cb1b82cd211
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 28 ++++++++++++++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f0cd6dde0634..2acc94aa77fb 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -15747,6 +15747,10 @@ typedef struct {
 #define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \
     (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT)
 
+#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT 2
+#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_MASK \
+    (1 << WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT)
+
 /**
  *  vdev extension statistics
  */
@@ -15769,10 +15773,34 @@ typedef struct {
      *     1: the "is link active" flag is valid
      * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE,
      *     1:link_active; 0:link_inactive
+     * bit 2: WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT,
+     *     0: new stats fields are not present.
+     *     1: new rx/tx/on/cca time stats fields present;
      * Refer to WMI_VDEV_STATS_FLAGS_ defs.
      */
     A_UINT32 flags;
     A_INT32 vdev_tx_power; /* dBm units */
+    /** rx_time:
+     * How many msecs vdev is in active receive on channel
+     * (32 bits number accruing over time)
+     */
+    A_UINT32 rx_time;
+    /** tx_time:
+     * How many msecs vdev is transmitting on channel
+     * (32 bits number accruing over time)
+     */
+    A_UINT32 tx_time;
+    /** on_time:
+     * How many msecs vdev is awake on channel
+     * (32 bits number accruing over time)
+     */
+    A_UINT32 on_time;
+    /** cca_time:
+     * How many msecs vdev is CCA busy on channel
+     * (32 bits number accruing over time)
+     * Includes rx_time but not tx_time.
+     */
+    A_UINT32 cca_time;
 } wmi_vdev_extd_stats;
 
 /**
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 44fad6cbdaaa..26bf4086cc14 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1652
+#define __WMI_REVISION_ 1653
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From b2a490622ac6e3bfbcb87b5f26f78ae1108207f6 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 25 Sep 2025 18:01:50 -0700
Subject: [PATCH 032/290] fw-api: CL 30501923 - update fw common interface
 files

Change-Id: I66cebbe5d6fc0eba5e08a7c3da8959ff619b42fa
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 9 +++++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2acc94aa77fb..6dcc229754c7 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -51698,12 +51698,21 @@ typedef struct {
     A_UINT32 pcie_lane;
 } wmi_energy_mgmt_pcie_config_cmd_fixed_param;
 
+typedef enum {
+    WMI_PCIE_LPM_CONFIG_TYPE_UNKNOWN,
+    WMI_PCIE_LPM_CONFIG_TYPE_L0S,
+    WMI_PCIE_LPM_CONFIG_TYPE_L1,
+    WMI_PCIE_LPM_CONFIG_TYPE_L0S_L1,
+} wmi_pcie_lpm_config_type_e;
+
 typedef struct {
     /** TLV tag and len; tag equals
     * WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param */
     A_UINT32 tlv_header;
     /** enable or disable PCIe LPM */
     A_UINT32 enable;
+    /** PCIe LPM config type */
+    A_UINT32 config_type; /* holds a wmi_pcie_lpm_config_type_e value */
 } wmi_energy_mgmt_pcie_lpm_cmd_fixed_param;
 
 typedef enum {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 26bf4086cc14..4138b977fa27 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1653
+#define __WMI_REVISION_ 1654
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 4649af0f53c626a722bcd4c9f5411629ce304b8e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 26 Sep 2025 18:01:48 -0700
Subject: [PATCH 033/290] fw-api: CL 30519235 - update fw common interface
 files

Change-Id: I33e25a3fd20c14a045fe3549b47f1fe4b1c43c78
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 66 ++++++++++++++++++++++++++++++--------------------
 1 file changed, 40 insertions(+), 26 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index a68c7236cd4f..ff3bed307d58 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2103,17 +2103,10 @@ typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv;
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
-    /**
-     * BIT [15: 0] : sw_peer_id
-     * BIT [31:16] : tid_num
-     */
-    union {
-        A_UINT32 sw_peer_id__tid_num;
-        struct {
-            A_UINT32 sw_peer_id : 16,
-                     tid_num    : 16;
-        };
-    };
+    /* Lower 4 bytes (bytes 0-3) of the MAC address */
+    A_UINT32 peer_mac_addr_31_0;
+    /* Upper 2 bytes (bytes 4-5) of MAC, and TID (1 byte) */
+    A_UINT32 peer_mac_addr_47_32_and_tid_num;
 
     /**
      * BIT [11: 0] : Starting Sequence number of the session,
@@ -2245,23 +2238,44 @@ typedef struct {
     A_UINT32 pn_size;
 } htt_stats_rx_peer_tid_reo_queue_ba_tlv;
 
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_TID_DWORD_OFFSET 1
-
-/* Macros for sw_peer_id and tid_num */
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_M 0x0000ffff
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S 0
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M    0xffff0000
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S    16
-
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_GET(_var) \
-    (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_M) >> \
-     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S)
-
-#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_SET(_var, _val) \
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_SET(_tlv_ptr, _mac_addr_ptr) \
     do { \
-        HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID, _val); \
-        ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SW_PEER_ID_S)); \
+        A_UINT32 __packed_mac_47_32; \
+        /* Pack MAC addr bytes [0-3] into peer_mac_addr_31_0 */ \
+        (_tlv_ptr)->peer_mac_addr_31_0 = (A_UINT32) \
+            (((_mac_addr_ptr)[0] << 0)  | \
+             ((_mac_addr_ptr)[1] << 8)  | \
+             ((_mac_addr_ptr)[2] << 16) | \
+             ((_mac_addr_ptr)[3] << 24)); \
+        /*
+         * Pack MAC addr bytes [4-5] into the LOWER 16 bits of
+         * peer_mac_addr_47_32_and_tid_num
+         */ \
+        __packed_mac_47_32 = (A_UINT32) \
+            (((_mac_addr_ptr)[4] << 0)  | \
+             ((_mac_addr_ptr)[5] << 8)); \
+        /*
+         * Set lower 16 bits of peer_mac_addr_47_32_and_tid_num,
+         * preserving upper 16 bits (which includes the TID) if already set
+          */ \
+        (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num &= ~0x0000FFFF; /* Clear existing MAC addr bits (lower 16) */ \
+        (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num |= __packed_mac_47_32; \
     } while (0)
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_GET(_tlv_ptr, _dest_mac_addr_ptr) \
+    do { \
+        A_UINT32 __mac_31_0_val = (_tlv_ptr)->peer_mac_addr_31_0; \
+        /* Extract MAC bytes [4-5] from the LOWER 16 bits of peer_mac_addr_47_32_and_tid */ \
+        A_UINT32 __mac_47_32_val = ((_tlv_ptr)->peer_mac_addr_47_32_and_tid_num) & 0xFFFF; \
+        (_dest_mac_addr_ptr)[0] = (A_UINT8)((__mac_31_0_val  >>  0) & 0xFF); \
+        (_dest_mac_addr_ptr)[1] = (A_UINT8)((__mac_31_0_val  >>  8) & 0xFF); \
+        (_dest_mac_addr_ptr)[2] = (A_UINT8)((__mac_31_0_val  >> 16) & 0xFF); \
+        (_dest_mac_addr_ptr)[3] = (A_UINT8)((__mac_31_0_val  >> 24) & 0xFF); \
+        (_dest_mac_addr_ptr)[4] = (A_UINT8)((__mac_47_32_val >>  0) & 0xFF); \
+        (_dest_mac_addr_ptr)[5] = (A_UINT8)((__mac_47_32_val >>  8) & 0xFF); \
+    } while (0)
+
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M    0x00FF0000 /* Mask for TID_NUM */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S    16         /* Shift for TID_NUM */
 
 #define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_GET(_var) \
     (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M) >> \

From 19d0fdfc7880a7847bbdd89ec965e2523d6d2c31 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 26 Sep 2025 18:03:26 -0700
Subject: [PATCH 034/290] fw-api: CL 30519258 - update fw common interface
 files

Change-Id: I5d30393252c3d2ff2dc1883c30f4679aff27779e
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |   4 +-
 fw/wmi_unified.h  | 383 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 387 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 6bba216cecbb..1f10eadade9b 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1512,6 +1512,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
     WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
+    WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -5990,7 +5991,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_POWER_BOOST_CAPABILITIES, power_boost_capabilities, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
 
 #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6dcc229754c7..6c6f1d81f346 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3055,6 +3055,9 @@ typedef struct _wmi_ppe_threshold {
 #define WMI_MAX_EHTCAP_MAC_SIZE  2
 #define WMI_MAX_EHTCAP_PHY_SIZE  3
 
+#define WMI_MAX_UHRCAP_MAC_SIZE  4
+#define WMI_MAX_UHRCAP_PHY_SIZE  3
+
 /*
  * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid)
  * 1 – index for <= 80MHz bw  (only 3 bytes are valid and other is reserved)
@@ -38294,6 +38297,386 @@ typedef struct {
     };
 } WMI_MAC_PHY_CAPABILITIES_EXT;
 
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2 */
+
+    /* hw_mode_id:
+     * Identify a particular set of HW characteristics, as specified by
+     * the subsequent fields.
+     * WMI_MAC_PHY_CAPABILITIES element must be mapped to its parent
+     * WMI_HW_MODE_CAPABILITIES element using hw_mode_id.
+     * No particular ordering of WMI_MAC_PHY_CAPABILITIES elements
+     * should be assumed, though in practice the elements will likely
+     * be ordered by hw_mode_id.
+     */
+    A_UINT32 hw_mode_id;
+
+    /*
+     * pdev_id starts with 1. pdev_id 1 => phy_id 0, pdev_id 2 => phy_id 1
+     * hw_link_id: Unique link id across SOCs, got as part of QMI handshake.
+     * For legacy chips which do not support MLO, these top bits will always
+     * be set to 0, so it won't impact the legacy chips which treat pdev_id
+     * as 32 bits.
+     */
+    union {
+        struct {
+            A_UINT32 pdev_id:16,
+                     hw_link_id:16;
+        } pdev_to_link_map;
+        A_UINT32 pdev_to_link_map_word32;
+    };
+    /* phy id. Starts with 0 */
+    A_UINT32 phy_id;
+    A_UINT32 wireless_modes_ext; /* REGDMN MODE EXT, see REGDMN_MODE_ enum */
+
+    /**************************************************************************
+     * following new params are for 802.11bn, but under development
+     **************************************************************************/
+    /* UHR capability mac info field of 802.11bn */
+    A_UINT32 uhr_cap_mac_info_2G[WMI_MAX_UHRCAP_MAC_SIZE];
+    A_UINT32 uhr_cap_mac_info_5G[WMI_MAX_UHRCAP_MAC_SIZE];
+
+    /* UHR capability phy field of 802.11bn, WMI_UHR_CAP defines */
+    A_UINT32 uhr_cap_phy_info_2G[WMI_MAX_UHRCAP_PHY_SIZE];
+    A_UINT32 uhr_cap_phy_info_5G[WMI_MAX_UHRCAP_PHY_SIZE];
+
+    union {
+        struct {
+            A_UINT32 npca_enabled:1,            /* bit 0 */
+                     npca_min_dur_threshold:4,  /* bits 4:1 */
+                     npca_switch_delay:6,       /* bits 10:5 */
+                     npca_switch_back_delay:6,  /* bits 16:11 */
+                     npca_qsrc:2,               /* bits 18:17 */
+                     npca_moplen:1,             /* bit 19 */
+                     reserved: 12;
+        };
+        A_UINT32 npca_capability;
+    };
+} WMI_MAC_PHY_CAPABILITIES_EXT2;
+
+#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \
+    WMI_GET_BITS(pdev_to_link_map_word32, 0, 16)
+#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_SET(pdev_to_link_map_word32, val) \
+    WMI_SET_BITS(pdev_to_link_map_word32, 0, 16, val)
+
+#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_GET(pdev_to_link_map_word32) \
+    WMI_GET_BITS(pdev_to_link_map_word32, 16, 16)
+#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_SET(pdev_to_link_map_word32, val) \
+    WMI_SET_BITS(pdev_to_link_map_word32, 16, 16, val)
+
+/****** 11BN UHR PHY Capabilities Information field ******/ /* { */
+
+/* Bit 0: Max Nss Rx for sounding NDP (≤ 80 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 0, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 0, 1, value)
+
+/* Bit 1: Max Nss,total Rx for DL MU-MIMO (≤ 80 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 1, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 1, 1, value)
+
+/* Bit 2: Max Nss Rx for sounding NDP (≤ 160 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 2, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 2, 1, value)
+
+/* Bit 3: Max Nss,total Rx for DL MU-MIMO (≤ 160 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 3, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 3, 1, value)
+
+/* Bit 4: Max Nss Rx for sounding NDP (≤ 320 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 4, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 4, 1, value)
+
+/* Bit 5: Max Nss,total Rx for DL MU-MIMO (≤ 320 MHz) */
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 5, 1)
+#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 5, 1, value)
+
+/* Bit 6: ELR Rx Support */
+#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 6, 1)
+#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 6, 1, value)
+
+/* Bit 7: ELR Tx Support */
+#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 7, 1)
+#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value)
+
+/****** End of 11BN UHR PHY Capabilities Information field ******/ /* } */
+
+/****** 11BN UHR MAC Capabilities Information field ******/ /* { */
+
+/* Bit 0: DPS Support */
+#define WMI_UHRCAP_MAC_DPS_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 0, 1)
+#define WMI_UHRCAP_MAC_DPS_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 0, 1, value)
+
+/* Bit 1: DPS Assisting support */
+#define WMI_UHRCAP_MAC_DPS_ASSIS_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 1, 1)
+#define WMI_UHRCAP_MAC_DPS_ASSIS_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 1, 1, value)
+
+/* Bit 2: DPS AP Static HCM Support */
+#define WMI_UHRCAP_MAC_DPS_AP_HCM_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 2, 1)
+#define WMI_UHRCAP_MAC_DPS_AP_HCM_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 2, 1, value)
+
+/* Bit 3: Multi Link Power Management support */
+#define WMI_UHRCAP_MAC_MULTI_LINK_PM_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 3, 1)
+#define WMI_UHRCAP_MAC_MULTI_LINK_PM_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 3, 1, value)
+
+/* Bit 4: NPCA support */
+#define WMI_UHRCAP_MAC_NPCA_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 4, 1)
+#define WMI_UHRCAP_MAC_NPCA_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 4, 1, value)
+
+/* Bit 5: Enhanced BSR support */
+#define WMI_UHRCAP_MAC_BSR_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 5, 1)
+#define WMI_UHRCAP_MAC_BSR_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 5, 1, value)
+
+/* Bit 6: Additional Mapped TID Support */
+#define WMI_UHRCAP_MAC_ADDITIONAL_TID_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 6, 1)
+#define WMI_UHRCAP_MAC_ADDITIONAL_TID_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 6, 1, value)
+
+/* Bit 7: EOTSP Support */
+#define WMI_UHRCAP_MAC_EOTSP_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 7, 1)
+#define WMI_UHRCAP_MAC_EOTSP_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 7, 1, value)
+
+/* Bit 8: DSO Support */
+#define WMI_UHRCAP_MAC_DSO_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 8, 1)
+#define WMI_UHRCAP_MAC_DSO_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 8, 1, value)
+
+/* Bit 9: P-EDCA Support */
+#define WMI_UHRCAP_MAC_P_EDCA_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 9, 1)
+#define WMI_UHRCAP_MAC_P_EDCA_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 9, 1, value)
+
+/* Bit 10: DBE Support */
+#define WMI_UHRCAP_MAC_DBE_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 10, 1)
+#define WMI_UHRCAP_MAC_DBE_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 10, 1, value)
+
+/* Bit 11: UL LLI Support */
+#define WMI_UHRCAP_MAC_UL_LLI_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 11, 1)
+#define WMI_UHRCAP_MAC_UL_LLI_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 11, 1, value)
+
+/* Bit 12: Peer-to-Peer LLI Support */
+#define WMI_UHRCAP_MAC_PEER_LLI_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 12, 1)
+#define WMI_UHRCAP_MAC_PEER_LLI_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 12, 1, value)
+
+/* Bit 13: PUO Support */
+#define WMI_UHRCAP_MAC_PUO_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 13, 1)
+#define WMI_UHRCAP_MAC_PUO_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 13, 1, value)
+
+/* Bit 14: AP PUO Support */
+#define WMI_UHRCAP_MAC_AP_PUO_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 14, 1)
+#define WMI_UHRCAP_MAC_AP_PUO_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 14, 1, value)
+
+/* Bit 15: DUO Support */
+#define WMI_UHRCAP_MAC_DUO_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 15, 1)
+#define WMI_UHRCAP_MAC_DUO_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 15, 1, value)
+
+/* Bit 16: OM Control UL MU Data Disable RX Support */
+#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 16, 1)
+#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 16, 1, value)
+
+/* Bit 17: AOM Support */
+#define WMI_UHRCAP_MAC_AOM_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 17, 1)
+#define WMI_UHRCAP_MAC_AOM_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 17, 1, value)
+
+/* Bit 18: IFCS Location Support */
+#define WMI_UHRCAP_MAC_IFCS_LOC_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 18, 1)
+#define WMI_UHRCAP_MAC_IFCS_LOC_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 18, 1, value)
+
+/* Bit 19: UHR TRS Support */
+#define WMI_UHRCAP_MAC_UHR_TRS_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 19, 1)
+#define WMI_UHRCAP_MAC_UHR_TRS_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 19, 1, value)
+
+/* Bit 20: TXSPG Support */
+#define WMI_UHRCAP_MAC_TXSPG_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 20, 1)
+#define WMI_UHRCAP_MAC_TXSPG_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 20, 1, value)
+
+/* Bit 21: TXOP Return Support in TXSPG */
+#define WMI_UHRCAP_MAC_TXOP_RETURN_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 21, 1)
+#define WMI_UHRCAP_MAC_TXOP_RETURN_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 21, 1, value)
+
+/* Bit 22 - 25: UHR Operating Mode And Parameters Update Timeout
+ *
+ * UHR Operating Mode And Parameters Update Timeout Lookup Table
+ *
+ * +------------------+-----------------------------+
+ * | Sub-field Value  | Timeout Duration            |
+ * +------------------+-----------------------------+
+ * |        0         | 0 TUs                       |
+ * |        1         | 128 µs                      |
+ * |        2         | 256 µs                      |
+ * |        3         | 512 µs                      |
+ * |        4         | 1 TU                        |
+ * |        5         | 2 TUs                       |
+ * |        6         | 4 TUs                       |
+ * |        7         | 8 TUs                       |
+ * |        8         | 16 TUs                      |
+ * |        9         | 32 TUs                      |
+ * |       10         | 64 TUs                      |
+ * |       11         | 128 TUs                     |
+ * |    12 - 15       | Reserved for future use     |
+ * +------------------+-----------------------------+
+ */
+#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 22, 4)
+#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 22, 4, value)
+
+/* Bit 26 - 28 : Parameter Update Adv Notification Interval */
+#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[0], 26, 3)
+#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[0], 26, 3, value)
+
+/* Bit 29-33: Update Indication In TIM Interval */
+#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_GET(uhr_cap_mac) \
+    (WMI_GET_BITS(uhr_cap_mac[0], 29, 3) | \
+     (WMI_GET_BITS(uhr_cap_mac[1], 0, 2) << 3))
+#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_SET(uhr_cap_mac, value) \
+    do { \
+        WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7) \
+        WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)) \
+    } while (0)
+
+/* Bit 34: Bounded ESS */
+#define WMI_UHRCAP_MAC_BOUNDED_ESS_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[1], 3, 1)
+#define WMI_UHRCAP_MAC_BOUNDED_ESS_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[1], 3, 1, value)
+
+/* Bit 35: BTM Assurance */
+#define WMI_UHRCAP_MAC_BTM_ASSURANCE_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[1], 4, 1)
+#define WMI_UHRCAP_MAC_BTM_ASSURANCE_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[1], 4, 1, value)
+
+/* Bits 36-63 --- Reserved */
+
+/* To be decided spec not provided clear bits */
+
+
+/* Bit 64-66: DBE Capabilities Params */
+#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[2], 0, 3)
+#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[2], 0, 3, value)
+
+
+/* Bit 67: EHT-MCS Map (BW=160 MHz) Present */
+#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[2], 3, 1)
+#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[2], 3, 1, value)
+
+/* Bit 68: EHT-MCS Map (BW=320 MHz) Present */
+#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[2], 4, 1)
+#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[2], 4, 1, value)
+
+/* Bit 69-71: Reserved */
+
+/* Bit 72 to 95: EHT-MCS Map (BW=160 MHz) */
+#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[2], 8, 24)
+#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[2], 8, 24, value)
+
+/* Bit 96 to 121: EHT-MCS Map (BW=320 MHz) */
+#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[3], 0, 24)
+#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[3], 0, 24, value)
+
+/****** End of 11BN UHR MAC Capabilities Information field ******/ /* } */
+
+#define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 0, 1)
+#define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 0, 1, value)
+
+#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 1, 4)
+#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 1, 5, value)
+
+#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 5, 6)
+#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 5, 6, value)
+
+#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 11, 6)
+#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 11, 6, value)
+
+#define WMI_CAP_EXT2_NPCA_QSRC_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 17, 2)
+#define WMI_CAP_EXT2_NPCA_QSRC_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 17, 2, value)
+
+#define WMI_CAP_EXT2_NPCA_MOPLEN_GET(npca_capability) \
+    WMI_GET_BITS(npca_capability, 19, 1)
+#define WMI_CAP_EXT2_NPCA_MOPLEN_SET(npca_capability, value) \
+    WMI_sET_BITS(npca_capability, 19, 1, value)
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES */
     /* hw_mode_id - identify a particular set of HW characteristics,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4138b977fa27..aabd5debe289 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1654
+#define __WMI_REVISION_ 1655
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 51f8f6e1f6c828a250ddd260519a71d1825ac555 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 27 Sep 2025 18:01:47 -0700
Subject: [PATCH 035/290] fw-api: CL 30538536 - update fw common interface
 files

Change-Id: I9aff5dfe6f6c8bcd86ab4859daebeeefcd9f9e19
CRs-Fixed: 3830439
---
 fw/htt.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index e2325e3a4395..53c422c93098 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -5521,6 +5521,9 @@ enum htt_srng_ring_id {
     HTT_LPASS_TO_FW_RXBUF_RING,    /* new LPASS to FW refill ring to recycle rx buffers */
     HTT_HOST3_TO_FW_RXBUF_RING,    /* used by host for EasyMesh feature */
     HTT_HOST4_TO_FW_RXBUF_RING,    /* fourth ring used by host to provide buffers for MGMT packets */
+    HTT_RXDMA_WBM_BUF0_RING,       /* used for SFE Datapath */
+    HTT_RXDMA_WBM_BUF1_RING,       /* used for PPE Datapath */
+    HTT_RXDMA_WBM_BUF2_RING,       /* used for MGMT path */
     /* Add Other SRING which can't be directly configured by host software above this line */
 };
 
@@ -6182,6 +6185,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
     A_UINT32 packet_type_enable_data_flags_3;
     A_UINT32 packet_type_enable_data_fpmo_flags0;
     A_UINT32 packet_type_enable_data_fpmo_flags1;
+
+    /* rdi_based_source_cfg:
+     * Each bit position in rdi_based_source_cfg represents RDI
+     * (REO Destination Indication).
+     *
+     * 1 in specific RDI position represents, for the given RDI position,
+     * ring id in the ring setup msg has to be configured as source buf.
+     *
+     * Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING
+     */
+    A_UINT32 rdi_based_source_cfg;
 } POSTPACK;
 
 #define HTT_RX_RING_SELECTION_CFG_SZ    (sizeof(struct htt_rx_ring_selection_cfg_t))

From abeb4175a6eb3220e697dd14c2d0823fa5774dc4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 28 Sep 2025 18:01:44 -0700
Subject: [PATCH 036/290] fw-api: CL 30538539 - update fw common interface
 files

Change-Id: I753f33e1977fb8eb351a0729cb80939e6a9d1eae
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index ff3bed307d58..730444663f3a 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6589,6 +6589,7 @@ typedef struct {
 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
 #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
 #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */
+#define HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */
 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
@@ -6879,6 +6880,8 @@ typedef struct {
     A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
     /* STA side trigger stats */
     A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES];
+    /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */
+    A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;
@@ -7068,6 +7071,7 @@ typedef struct {
 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
 #define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
 #define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */
+#define HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */
 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */
 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
@@ -7427,6 +7431,8 @@ typedef struct {
     A_UINT32 rx_2xldpc;
     A_UINT32 npca_rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS];
     A_UINT32 npca_rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+    /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */
+    A_UINT32 rx_mcs_ext_3[HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
 } htt_stats_rx_pdev_rate_ext_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv;
@@ -9456,6 +9462,9 @@ typedef struct {
     htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
 
     htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+
+    /* rate stats for iMCS 1.1, 3.1, 4.1, 7.1 */
+    htt_tx_rate_stats_t per_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
 } htt_stats_per_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv;

From e4d8b84a16d8c6da2079a25263ef19abebdab90d Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 28 Sep 2025 18:03:39 -0700
Subject: [PATCH 037/290] fw-api: CL 30538540 - update fw common interface
 files

Change-Id: Id14de308b654dbd8ee5aaea069eb2a9bff2dac98
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_unified.h  | 3 +++
 fw/wmi_version.h  | 2 +-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 670a018a3abf..c36760d0652e 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -726,6 +726,7 @@ typedef  enum  {
     WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */
     WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */
     WMI_SERVICE_EM_DPS_ASSISTING_ROLE_SUPPORT = 467, /* Indicates support for Energy Mgmt DPS assisting role operation */
+    WMI_SERVICE_XPAN_SAP_STA_PWRSAVE_SUPPORT = 468, /* Indicates support for power optimization in XPAN + STA */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6c6f1d81f346..69353edcb8a2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10153,6 +10153,9 @@ typedef enum {
 
     /* configure pdev coex stats period (millisecond units) */
     WMI_PDEV_PARAM_COEX_STATS_UPDATE_PERIOD,
+
+    /* To enable/disable XPAN SAP + STA power optimization */
+    WMI_PDEV_PARAM_XPAN_STA_PWRSAVE_ENABLE,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index aabd5debe289..c02e28498752 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1655
+#define __WMI_REVISION_ 1656
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c884450d8ff5656fe37416d28255fccb6f4200c0 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 28 Sep 2025 18:05:15 -0700
Subject: [PATCH 038/290] fw-api: CL 30541340 - update fw common interface
 files

Change-Id: I9d85dcac669281c0180d8868d2d172dd9a6b47be
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 69353edcb8a2..d27bf95a40fb 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -30774,6 +30774,9 @@ enum wmi_sar_feature_state_flags {
     WMI_SAR_FEATURE_ON_USER_DEFINED,
     WMI_SAR_FEATURE_ON_SAR_V2_0,
     WMI_SAR_FEATURE_ON_SAR_V3,
+        WMI_SAR_FEATURE_ON_SAR_V3_0 = WMI_SAR_FEATURE_ON_SAR_V3,
+    WMI_SAR_FEATURE_ON_SAR_V4_0,
+    WMI_SAR_FEATURE_ON_SAR_V5_0,
 };
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c02e28498752..2a249a209664 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1656
+#define __WMI_REVISION_ 1657
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 1215d075a25086d92f43db74e61bf468675b1f79 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 29 Sep 2025 18:01:53 -0700
Subject: [PATCH 039/290] fw-api: CL 30544126 - update fw common interface
 files

Change-Id: I0cdfc6a8d01c051575f0858769c08ae1d08a5bf7
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 730444663f3a..65b817eca362 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -5506,6 +5506,15 @@ typedef struct {
     A_UINT32 tqm_enqueue_msdu_count;
     A_UINT32 tqm_dropped_msdu_count;
     A_UINT32 tqm_dequeue_msdu_count;
+
+    A_UINT32 tqm_enqueue_msdu_count_ac[HTT_NUM_AC_WMM];
+    A_UINT32 tqm_dropped_msdu_count_ac[HTT_NUM_AC_WMM];
+    A_UINT32 tqm_dequeue_msdu_count_ac[HTT_NUM_AC_WMM];
+    A_UINT32 remove_msdu_ac[HTT_NUM_AC_WMM];
+    A_UINT32 remove_mpdu_ac[HTT_NUM_AC_WMM];
+    A_UINT32 remove_msdu_ttl_ac[HTT_NUM_AC_WMM];
+    A_UINT32 remove_mpdu_ttl_ac[HTT_NUM_AC_WMM];
+    A_UINT32 remove_mpdu_retries_ac[HTT_NUM_AC_WMM];
 } htt_stats_tx_tqm_pdev_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v;
@@ -8213,6 +8222,7 @@ typedef struct {
         /* upper 32 bits of the rx_bytes value */
         A_UINT32 high_32;
     } bytes_received;
+    A_UINT32  rx_msdu_cnt_ac[HTT_NUM_AC_WMM];
 } htt_stats_rx_pdev_fw_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv;

From c2e50fa895b0ab4d9a359ff0e450fadf6bdf5b87 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 2 Oct 2025 18:01:49 -0700
Subject: [PATCH 040/290] fw-api: CL 30580039 - update fw common interface
 files

Change-Id: I0661c4d2baaf3b7da617f8c66d771c77dbecfe0b
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 65b817eca362..960aa0f800a8 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -9473,7 +9473,7 @@ typedef struct {
 
     htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
 
-    /* rate stats for iMCS 1.1, 3.1, 4.1, 7.1 */
+    /* PER stats for iMCS 1.1, 3.1, 4.1, 7.1 */
     htt_tx_rate_stats_t per_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
 } htt_stats_per_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */

From e9f6067fcfafa1e9a153052917e366879335d574 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 2 Oct 2025 18:03:27 -0700
Subject: [PATCH 041/290] fw-api: CL 30583992 - update fw common interface
 files

Change-Id: I452e22b7a2c36ab878e1a85b6edb3bf3088cb96f
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 +-
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index d27bf95a40fb..aa1eb0fe76fb 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -52195,7 +52195,7 @@ typedef struct {
     A_UINT32 tlv_header;
     /* VDEV identifier */
     A_UINT32 vdev_id;
-    /** TX RX packet count threshold value */
+    /** TX RX byte count value, in KB units */
     A_UINT32 data_threshold;
     /** duration of traffic monitoring, in unit of sec */
     A_UINT32 traffic_monitoring_time;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2a249a209664..dce09579ba19 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1657
+#define __WMI_REVISION_ 1658
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 8a5851f97109a5cf80a8e9a16fbbe2a8fdb005ab Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 2 Oct 2025 18:04:58 -0700
Subject: [PATCH 042/290] fw-api: CL 30584319 - update fw common interface
 files

Change-Id: I0c1a4b623a518aed0f2d4e058412b5a9535ec87d
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 960aa0f800a8..9a37c333fcb0 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1290,6 +1290,8 @@ typedef struct {
         /* upper 32 bits of the tx_bytes value */
         A_UINT32 high_32;
     } bytes_sent;
+    /* increment array based on AC */
+    A_UINT32 num_ppdu_tried_ota_per_ac[HTT_NUM_AC_WMM];
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;
@@ -6891,6 +6893,11 @@ typedef struct {
     A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES];
     /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */
     A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+
+/*
+ * NOTE: THIS STRUCT HAS ONLY 4 BYTES OF SPACE LEFT
+ * WITHIN THE TARGET'S HTT_STATS_TLV_MAX_LEN SIZE LIMIT.
+ */
 } htt_stats_tx_pdev_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;

From 16f98deb43f55596494c6527338008e42b06b128 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 15 Oct 2025 12:04:21 -0700
Subject: [PATCH 043/290] fw-api: CL 30669084 - update fw common interface
 files

Change-Id: I78aca7ede872d2792be621488c5a94198b2617bc
CRs-Fixed: 3830439
---
 fw/htt.h | 77 ++++++++++++++++++++++++++++++++++++++++----------------
 1 file changed, 56 insertions(+), 21 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 53c422c93098..1242e91980aa 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -271,9 +271,10 @@
  * 3.141 Add H2T HTT_AST_INFO for RxOLE.
  * 3.142 Add T2H GLOBAL_PEER_ID_UNMAP def, update H2T MPDUQ_OR_MSDUQ_INFO def.
  * 3.143 Add T2H HAPS msg def.
+ * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 143
+#define HTT_CURRENT_VERSION_MINOR 144
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -11792,6 +11793,13 @@ typedef enum {
     HTT_H2T_MAX_TID_NUM            = 31,
 } H2T_TX_TID;
 
+typedef enum {
+    HTT_SAWF_SVC_INST_CREATE_REQ = 0,
+    HTT_SAWF_SVC_INST_DEACTIVATE_REQ,
+    HTT_SAWF_SVC_INST_REACTIVATE_REQ,
+    HTT_SAWF_SVC_INST_DELETE_REQ,
+} HTT_SAWF_SVC_INST_REQ_TYPE;
+
 /* HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */
 PREPACK struct htt_h2t_mpduq_or_msduq_info {
    A_UINT32 msg_type:          8,  /* bits  7:0  */
@@ -11801,28 +11809,33 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
 
     union {
         struct {
-            A_UINT32 mpduq_address_39_8;     /* bits 31:0  */
-            A_UINT32 mpduq_number:       24, /* bits 23:0  */
-                     pn_addr_39_32:       8; /* bits 31:24 */
-            A_UINT32 pn_addr_31_0;           /* bits 31:0  */
-            A_UINT32 reserved1a;             /* bits 31:0  */
-            A_UINT32 reserved1b;             /* bits 31:0  */
-            A_UINT32 reserved1c;             /* bits 31:0  */
-            A_UINT32 reserved1d;             /* bits 31:0  */
-            A_UINT32 reserved1e;             /* bits 31:0  */
-            A_UINT32 reserved1f;             /* bits 31:0  */
+            A_UINT32 mpduq_address_39_8;          /* bits 31:0  */
+            A_UINT32 mpduq_number:            24, /* bits 23:0  */
+                     pn_addr_39_32:            8; /* bits 31:24 */
+            A_UINT32 pn_addr_31_0;                /* bits 31:0  */
+            A_UINT32 reserved1a;                  /* bits 31:0  */
+            A_UINT32 reserved1b;                  /* bits 31:0  */
+            A_UINT32 reserved1c;                  /* bits 31:0  */
+            A_UINT32 reserved1d;                  /* bits 31:0  */
+            A_UINT32 reserved1e;                  /* bits 31:0  */
+            A_UINT32 reserved1f;                  /* bits 31:0  */
         };
         struct {
-            A_UINT32 tx_msduq_number:    24, /* bits 23:0  */
-                     svc_class_id:        8; /* bits 31:24 */
-            A_UINT32 msduq_address_39_8;     /* bits 31:0  */
-            A_UINT32 reserved2a;             /* bits 31:0  */
-            A_UINT32 reserved2b;             /* bits 31:0  */
-            A_UINT32 reserved2c;             /* bits 31:0  */
-            A_UINT32 reserved2d;             /* bits 31:0  */
-            A_UINT32 reserved2e;             /* bits 31:0  */
-            A_UINT32 reserved2f;             /* bits 31:0  */
-            A_UINT32 reserved2g;             /* bits 31:0  */
+            A_UINT32 tx_msduq_number:         24, /* bits 23:0  */
+                     svc_class_id:             8; /* bits 31:24 */
+            A_UINT32 msduq_address_39_8;          /* bits 31:0  */
+            A_UINT32 svc_inst_req_type_valid:  1, /* bit    0   */
+                     /* svc_inst_req_type:
+                      * contains a HTT_SAWF_SVC_INST_REQ_TYPE value
+                      */
+                     svc_inst_req_type:        3, /* bits  3:1  */
+                     reserved2a:              28; /* bits 31:4  */
+            A_UINT32 reserved2b;                  /* bits 31:0  */
+            A_UINT32 reserved2c;                  /* bits 31:0  */
+            A_UINT32 reserved2d;                  /* bits 31:0  */
+            A_UINT32 reserved2e;                  /* bits 31:0  */
+            A_UINT32 reserved2f;                  /* bits 31:0  */
+            A_UINT32 reserved2g;                  /* bits 31:0  */
         };
     };
 } POSTPACK;
@@ -11963,6 +11976,28 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
         ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S)); \
     } while (0)
 
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M 0x00000001
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S          0
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M       0x0000000E
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S                1
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S)); \
+    } while (0)
+
 
 /*
  * @brief  host -> target HTT_AST_INFO message

From 76b20ed6784d2f0caf61f299957ead5a117960f1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 15 Oct 2025 12:06:15 -0700
Subject: [PATCH 044/290] fw-api: CL 30669089 - update fw common interface
 files

Change-Id: Ia83dfc062e3a647bb2370b13546b06564e934783
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  2 ++
 fw/wmi_tlv_defs.h | 13 +++++++++----
 fw/wmi_unified.h  | 38 ++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 4 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index c36760d0652e..df0e01de1666 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -727,6 +727,8 @@ typedef  enum  {
     WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */
     WMI_SERVICE_EM_DPS_ASSISTING_ROLE_SUPPORT = 467, /* Indicates support for Energy Mgmt DPS assisting role operation */
     WMI_SERVICE_XPAN_SAP_STA_PWRSAVE_SUPPORT = 468, /* Indicates support for power optimization in XPAN + STA */
+    WMI_SERVICE_CFP_SUPPORT = 469, /* FW supports control frame protection */
+    WMI_SERVICE_CFP_PADDING_SUPPORT = 470, /* FW supports control frame protection padding */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 1f10eadade9b..e0de1651d7df 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1496,7 +1496,10 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_mpduq_params,
     WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_msduq_params,
-    WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params,
+    WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params,
+        /* for backwards-compatibility, maintain old name (with "mdsu" typo) */
+        WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params =
+            WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params,
     WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_co_located_chan_info,
     WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param,
@@ -1513,6 +1516,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
     WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
+    WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2931,7 +2935,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_mdsuq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)
 /* NOTE:
  * No further TLVs can be added to this message;
  * it is already at the target's WMI_MAX_NUM_TLVS limit (13).
@@ -2959,9 +2963,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_mdsuq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index aa1eb0fe76fb..1b2adf552182 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -17429,6 +17429,10 @@ typedef struct {
      * vdev_stats_id_valid field is non-zero.
      */
     A_UINT32 vdev_stats_id;
+    /** cfp_enable: indicate whether control frame protection is enabled */
+    A_UINT32 cfp_enable;
+
+
 /* This TLV is followed by another TLV of array of structures
  *   wmi_vdev_txrx_streams cfg_txrx_streams[];
  *   wmi_vdev_create_mlo_params mlo_params[0,1];
@@ -22404,7 +22408,7 @@ typedef struct {
     WMI_SET_BITS(mpduq_msduq_number,22,5,value)
 
 typedef struct {
-    A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params */
+    A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params */
 
     /**
      * A_UINT32
@@ -22444,7 +22448,37 @@ typedef struct {
 
     /* Upper 8 bits of 40 bit pn physical address */
     A_UINT32 pn_paddr_39_32;
-} wmi_peer_assoc_hol_mdsuq_params;
+} wmi_peer_assoc_hol_msduq_params;
+/*
+ * for backwards compatibility, maintain old version of the name
+ * (with "mdsu" typo)
+ */
+typedef wmi_peer_assoc_hol_msduq_params wmi_peer_assoc_hol_mdsuq_params;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params */
+
+    /* control frame protection enable/disable per peer */
+    A_UINT32 enable_cfp;
+
+    /*
+     * MIC Padding Delay Field Values:
+     *
+     * Value    Delay
+     * ----------------
+     * 0        0 us
+     * 1        4 us
+     * 2        8 us
+     * 3        12 us
+     * 4        16 us
+     * 5        20 us
+     * 6        24 us
+     * 7        28 us
+     * 8        32 us
+     * 9-15     Reserved
+     */
+    A_UINT32 cfp_padding_delay;
+} wmi_peer_assoc_cfp_params; /* cfp -> control frame protection */
 
 /*
  * PEER assoc_flags for assoc complete:
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index dce09579ba19..30e97321bd7d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1658
+#define __WMI_REVISION_ 1659
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 056ebfdf0f9ecd00d03c1cd66ae1d9bfab0781a1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 15 Oct 2025 12:07:52 -0700
Subject: [PATCH 045/290] fw-api: CL 30678803 - update fw common interface
 files

Change-Id: I86103147e2bb6d676ef1ea26b192835c60531fde
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 1b2adf552182..89fef580f848 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -28491,6 +28491,8 @@ typedef enum {
     WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5,
     /** Enable/Disable dynamic bw feature */
     WMI_STA_SMPS_PARAM_DYNAMIC_BW_SWITCH = 6,
+    /** Enable/Disable dynamic mode sw feature */
+    WMI_STA_SMPS_PARAM_DYNAMIC_MODE_SWITCH = 7,
 } wmi_sta_smps_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 30e97321bd7d..66298d626a4f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1659
+#define __WMI_REVISION_ 1660
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c4c9b42a41c817fc59bbbb1cdc2a866a090e03c5 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 16 Oct 2025 18:01:59 -0700
Subject: [PATCH 046/290] fw-api: CL 30697325 - update fw common interface
 files

Change-Id: Ie3ce1bedc1b2be7f4bff072d871e56bf43f8d1ba
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  6 ++++++
 fw/wmi_unified.h  | 47 ++++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 3 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index df0e01de1666..71ede0c766bb 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -730,6 +730,12 @@ typedef  enum  {
     WMI_SERVICE_CFP_SUPPORT = 469, /* FW supports control frame protection */
     WMI_SERVICE_CFP_PADDING_SUPPORT = 470, /* FW supports control frame protection padding */
 
+    /* Service caps related to 11BI */
+    WMI_SERVICE_11BI_EPPKE_SUPPORT = 471,
+    WMI_SERVICE_11BI_1X_OVER_AUTH_SUPPORT = 472,
+    WMI_SERVICE_11BI_PMKID_PRIVACY_SUPPORT = 473,
+    WMI_SERVICE_11BI_DS_MAC_ADDR_SUPPORT = 474,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 89fef580f848..2a3ee0937fd2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -21435,6 +21435,9 @@ typedef struct {
 #define WMI_PEER_CREATE_GET_HW_PEER_ID_VALID(flags) WMI_GET_BITS(flags,0,1)
 #define WMI_PEER_CREATE_SET_HW_PEER_ID_VALID(flags) WMI_SET_BITS(flags,0,1,value)
 
+#define WMI_PEER_CREATE_GET_IS_11BI_PEER(flags) WMI_GET_BITS(flags,1,1)
+#define WMI_PEER_CREATE_SET_IS_11BI_PEER(flags) WMI_SET_BITS(flags,1,1,value)
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
@@ -21447,7 +21450,8 @@ typedef struct {
     union {
         struct {
             A_UINT32 hw_peer_id_valid :1,
-                     reserved         :31;
+                     is_llbi_peer:     1,
+                     reserved         :30;
         };
         A_UINT32 flags;
     };
@@ -23501,6 +23505,7 @@ enum {
     WMI_AUTH_WPA3_SAE_SHA384,
     WMI_AUTH_FT_RSNA_SAE_SHA384,
     WMI_AUTH_FT_RSNA_PSK_SHA384,
+    WMI_AUTH_EPPKE, /* For 11BI */
 };
 
 typedef enum {
@@ -23884,6 +23889,8 @@ typedef struct {
      * considered for the candidates for which MCC will be formed.
      */
     A_UINT32 mcc_score_factor_pcnt;
+    /* Scoring weightage for privacy support like 11bi */
+    A_UINT32 privacy_weightage_pcnt;
 } wmi_roam_cnd_scoring_param;
 
 typedef struct {
@@ -23955,6 +23962,16 @@ typedef struct {
      * of the currently associated AP.
      */
     A_UINT32 bg_rssi_threshold;
+    /**
+     * IEEE value for auth algorithm
+     * Authentication algorithm number = 3:
+     *     Simultaneous Authentication of Equals (SAE)
+     * Authentication algorithm number = 8:
+     *     IEEE 802.1X authentication
+     * Authentication algorithm number = 9:
+     *     EPPKE authentication
+     */
+    A_UINT32 auth_algo;
 } wmi_ap_profile;
 
 typedef struct {
@@ -31016,6 +31033,16 @@ typedef struct {
     A_UINT32 mac_tsf_id;
     /** ignore mac_tsf_id unless mac_tsf_id_valid is set */
     A_UINT32 mac_tsf_id_valid;
+    /**
+     * IEEE value for auth algorithm
+     * Authentication algorithm number = 3:
+     *     Simultaneous Authentication of Equals (SAE)
+     * Authentication algorithm number = 8:
+     *     IEEE 802.1X authentication
+     * Authentication algorithm number = 9:
+     *     EPPKE authentication
+     */
+    A_UINT32 auth_algo;
     /**
      * TLV (tag length value) parameters follows roam_synch_event
      * The TLV's are:
@@ -43109,6 +43136,24 @@ typedef struct {
     wmi_mac_addr transmit_addr;
     /* AKM suite type (as defined in the IEEE 802.11 spec) */
     A_UINT32 akm_suite_type;
+    /**
+     * IEEE value for auth algorithm
+     * Authentication algorithm number = 3:
+     *     Simultaneous Authentication of Equals (SAE)
+     * Authentication algorithm number = 8:
+     *     IEEE 802.1X authentication
+     * Authentication algorithm number = 9:
+     *     EPPKE authentication
+     */
+    A_UINT32 auth_algo;
+
+    /* IEEE value for below ciphers */
+    /** unicast cipher set */
+    A_UINT32 pairwise_cipher;
+    /** mcast/group cipher set */
+    A_UINT32 group_cipher;
+    /** mcast/group management frames cipher set */
+    A_UINT32 group_mgmt_cipher;
 } wmi_roam_preauth_start_event_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 66298d626a4f..875db7d28895 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1660
+#define __WMI_REVISION_ 1661
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ec969c94751bafc374e672ead8ee79eb6dbbd2a3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 18 Oct 2025 18:01:52 -0700
Subject: [PATCH 047/290] fw-api: CL 30714212 - update fw common interface
 files

Change-Id: If53f113031dd883385687cf04b975a0cff599626
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  6 ++++++
 fw/wmi_unified.h  | 18 ++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index e0de1651d7df..8024d8896a58 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1517,6 +1517,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
     WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
     WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params,
+    WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2436,6 +2437,7 @@ typedef enum {
     OP(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID) \
     OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \
     OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \
+    OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -8086,6 +8088,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_ac_info, vdev_ac_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID);
 
+#define WMITLV_TABLE_WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, wmi_pdev_set_tx_chainmask_comp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2a3ee0937fd2..12eb730c8aa1 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -607,6 +607,8 @@ typedef enum {
      * for the pdev
      */
     WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID,
+    /* Event to indicate the status of the set tx chainmask command */
+    WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -52270,6 +52272,22 @@ typedef struct {
      */
 } wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param;
 
+typedef enum {
+    WMI_PDEV_SET_TX_CHAINMASK_SUCCESS = 0,
+    WMI_PDEV_SET_TX_CHAINMASK_FAIL_INVALID_CHAINMASK,
+} WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param */
+    /** pdev_id for identifying the MAC
+     */
+    A_UINT32 pdev_id;
+    /*
+     * status type WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE
+     */
+    A_UINT32 status;
+} wmi_pdev_set_tx_chainmask_comp_event_fixed_param;
+
 typedef struct {
     /** TLV tag and len; tag equals
      * WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 875db7d28895..00497bbe9b70 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1661
+#define __WMI_REVISION_ 1662
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 311cba522bb7d0e2a6766f174a0d115bdcc301c5 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 20 Oct 2025 18:01:51 -0700
Subject: [PATCH 048/290] fw-api: CL 30720606 - update fw common interface
 files

Change-Id: Ib4cdce1910d8c0445811ab910dcc55d866a000a3
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  3 +++
 fw/wmi_unified.h  | 34 +++++++++++++++++++++++++++++++---
 fw/wmi_version.h  |  2 +-
 3 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 71ede0c766bb..6adcdbfac4e5 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -736,6 +736,9 @@ typedef  enum  {
     WMI_SERVICE_11BI_PMKID_PRIVACY_SUPPORT = 473,
     WMI_SERVICE_11BI_DS_MAC_ADDR_SUPPORT = 474,
 
+    WMI_SERVICE_CCK_RX_SUPPORT_5GHZ = 475, /* Indicates FW supports CCK RX in 5 GHz band */
+    WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 12eb730c8aa1..128ee667f305 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19806,6 +19806,18 @@ typedef enum {
      */
     WMI_VDEV_PARAM_2xLDPC,                                /* 0xCA */
 
+    /**
+     * Self-capability support indication for CCK RX/TX in 5GHz band.
+     * Use with WMI_VDEV_SET_PARAM_CMDID, value:
+     *    BIT 0 - cck_rx_support_5ghz
+     *    BIT 1 - cck_tx_support_5ghz
+     *
+     * Host must only set this param when enabled by ini and
+     * WMI_SERVICE_CCK_RX_SUPPORT_5GHZ/WMI_SERVICE_CCK_TX_SUPPORT_5GHZ
+     * (FW capability bits) are present.
+     */
+    WMI_VDEV_PARAM_CCK_SUPPORT,                           /* 0xCB */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
@@ -22647,9 +22659,19 @@ typedef struct {
     /** Peer create flags */
     union {
         struct {
-            A_UINT32 hw_peer_id_valid : 1,
-                     peer_type_valid  : 1,
-                     reserved         :30;
+            A_UINT32 hw_peer_id_valid         : 1,
+                     peer_type_valid          : 1,
+                     /**
+                      * Host sets these peer_cck [rx,tx] support_5ghz fields
+                      * based on the intersection of AP and self-capabilities.
+                      * Example:
+                      *     On the STA, if the peer (AP) supports CCK 5GHz RX
+                      *     and the STA supports CCK 5GHz TX, then set
+                      *     peer_cck_rx_support_5ghz = 1
+                      */
+                     peer_cck_rx_support_5ghz : 1,
+                     peer_cck_tx_support_5ghz : 1,
+                     reserved                 :28;
         };
         A_UINT32 flags;
     };
@@ -22691,6 +22713,12 @@ typedef struct {
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_GET(flags) WMI_GET_BITS(flags, 1, 1)
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_GET_BITS(flags, 1, 1, value)
 
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 2, 1)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_SET(flags, value) WMI_GET_BITS(flags, 2, 1, value)
+
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 3, 1)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_GET_BITS(flags, 3, 1, value)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_params*/
     A_UINT32 sw_peer_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 00497bbe9b70..4934e713c4de 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1662
+#define __WMI_REVISION_ 1663
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 8ba588f53b3b1dda8c10a4dd4e1bf3cf2d1e37c4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 22 Oct 2025 18:01:44 -0700
Subject: [PATCH 049/290] fw-api: CL 30735748 - update fw common interface
 files

Change-Id: I427bac34f9908de1b7db30a9896bad6560447d75
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 128ee667f305..4433c3c61d57 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19818,6 +19818,12 @@ typedef enum {
      */
     WMI_VDEV_PARAM_CCK_SUPPORT,                           /* 0xCB */
 
+    /*
+     * value 0 | disable dynamic D-SMPS base on RSSI feature
+     * value 1 | enable dynamic D-SMPS base on RSSI feature
+     */
+    WMI_VDEV_PARAM_ENABLE_DYN_DSMPS_BASE_ON_RSSI,         /* 0xCC */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4934e713c4de..e1156570d2a4 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1663
+#define __WMI_REVISION_ 1664
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9c579ff7aac6d003d5b40cb689d1cd27f636ad8d Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <prakashp@qti.qualcomm.com>
Date: Mon, 13 Oct 2025 17:39:37 -0700
Subject: [PATCH 050/290] fw-api: E3.0 WCSS_VERSION 3150 fig headers

Add FIG HW headers for fig compilation support.

Change-Id: Ia1290c93d87ee321c5b9339ff8751606d392d0c1
CRs-Fixed: 4330334
---
 hw/fig/v1/HALcomdef.h                         |   38 +
 hw/fig/v1/HALhwio.h                           |  282 ++
 hw/fig/v1/ack_report.h                        |   52 +
 hw/fig/v1/boron_top_reg.h                     |   12 +
 hw/fig/v1/buffer_addr_info.h                  |   45 +
 hw/fig/v1/ce_src_desc.h                       |  122 +
 hw/fig/v1/ce_stat_desc.h                      |  115 +
 hw/fig/v1/coex_rx_status.h                    |  131 +
 hw/fig/v1/coex_tx_req.h                       |  222 ++
 hw/fig/v1/coex_tx_status.h                    |  117 +
 hw/fig/v1/com_dtypes.h                        |  167 ++
 hw/fig/v1/eht_sig_usr_mu_mimo_info.h          |   94 +
 hw/fig/v1/eht_sig_usr_ofdma_info.h            |  108 +
 hw/fig/v1/eht_sig_usr_su_info.h               |   73 +
 hw/fig/v1/expected_response.h                 |  203 ++
 hw/fig/v1/he_sig_a_mu_dl_info.h               |  171 ++
 hw/fig/v1/he_sig_a_mu_ul_info.h               |  101 +
 hw/fig/v1/he_sig_a_su_info.h                  |  206 ++
 hw/fig/v1/he_sig_b1_mu_info.h                 |   38 +
 hw/fig/v1/he_sig_b2_mu_info.h                 |   94 +
 hw/fig/v1/he_sig_b2_ofdma_info.h              |   94 +
 hw/fig/v1/ht_sig_info.h                       |  129 +
 hw/fig/v1/l_sig_a_info.h                      |   80 +
 hw/fig/v1/l_sig_b_info.h                      |   45 +
 hw/fig/v1/macrx_abort_request_info.h          |   31 +
 hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h         |   77 +
 hw/fig/v1/mactx_eht_sig_usr_ofdma.h           |   87 +
 hw/fig/v1/mactx_eht_sig_usr_su.h              |   69 +
 hw/fig/v1/mactx_he_sig_a_mu_dl.h              |  132 +
 hw/fig/v1/mactx_he_sig_a_mu_ul.h              |   82 +
 hw/fig/v1/mactx_he_sig_a_su.h                 |  157 ++
 hw/fig/v1/mactx_he_sig_b1_mu.h                |   44 +
 hw/fig/v1/mactx_he_sig_b2_mu.h                |   77 +
 hw/fig/v1/mactx_he_sig_b2_ofdma.h             |   77 +
 hw/fig/v1/mactx_ht_sig.h                      |  102 +
 hw/fig/v1/mactx_l_sig_a.h                     |   74 +
 hw/fig/v1/mactx_l_sig_b.h                     |   49 +
 hw/fig/v1/mactx_phy_desc.h                    |  348 +++
 hw/fig/v1/mactx_u_sig_eht_su_mu.h             |  122 +
 hw/fig/v1/mactx_u_sig_eht_tb.h                |   97 +
 hw/fig/v1/mactx_user_desc_common.h            |  482 ++++
 hw/fig/v1/mactx_user_desc_per_user.h          |  285 ++
 hw/fig/v1/mactx_vht_sig_a.h                   |  112 +
 hw/fig/v1/mactx_vht_sig_b_mu160.h             |  182 ++
 hw/fig/v1/mactx_vht_sig_b_mu20.h              |   54 +
 hw/fig/v1/mactx_vht_sig_b_mu40.h              |   67 +
 hw/fig/v1/mactx_vht_sig_b_mu80.h              |  102 +
 hw/fig/v1/mactx_vht_sig_b_su160.h             |  222 ++
 hw/fig/v1/mactx_vht_sig_b_su20.h              |   54 +
 hw/fig/v1/mactx_vht_sig_b_su40.h              |   72 +
 hw/fig/v1/mactx_vht_sig_b_su80.h              |  122 +
 hw/fig/v1/mlo_sta_id_details.h                |   52 +
 hw/fig/v1/mon_buffer_addr.h                   |   75 +
 hw/fig/v1/mon_destination_ring.h              |   94 +
 hw/fig/v1/mon_drop.h                          |   61 +
 hw/fig/v1/mon_ingress_ring.h                  |   54 +
 hw/fig/v1/msmhwiobase.h                       |   12 +
 hw/fig/v1/msmhwioreg.h                        |   98 +
 hw/fig/v1/no_ack_report.h                     |  108 +
 hw/fig/v1/ofdma_trigger_details.h             |  928 +++++++
 hw/fig/v1/pcu_ppdu_setup_init.h               | 2309 ++++++++++++++++
 hw/fig/v1/pdg_response.h                      |  503 ++++
 hw/fig/v1/pdg_response_rate_setting.h         |  409 +++
 hw/fig/v1/pdg_tx_req.h                        |   89 +
 hw/fig/v1/phyrx_abort_request_info.h          |   87 +
 hw/fig/v1/phyrx_common_user_info.h            |  168 ++
 hw/fig/v1/phyrx_he_sig_a_mu_dl.h              |  132 +
 hw/fig/v1/phyrx_he_sig_a_mu_ul.h              |   82 +
 hw/fig/v1/phyrx_he_sig_a_su.h                 |  157 ++
 hw/fig/v1/phyrx_he_sig_b1_mu.h                |   44 +
 hw/fig/v1/phyrx_he_sig_b2_mu.h                |   77 +
 hw/fig/v1/phyrx_he_sig_b2_ofdma.h             |   77 +
 hw/fig/v1/phyrx_ht_sig.h                      |  102 +
 hw/fig/v1/phyrx_l_sig_a.h                     |   74 +
 hw/fig/v1/phyrx_l_sig_b.h                     |   49 +
 hw/fig/v1/phyrx_location.h                    |  332 +++
 .../v1/phyrx_other_receive_info_ru_details.h  |   47 +
 hw/fig/v1/phyrx_pkt_end.h                     |  427 +++
 hw/fig/v1/phyrx_pkt_end_info.h                |  450 +++
 hw/fig/v1/phyrx_rssi_legacy.h                 |  806 ++++++
 hw/fig/v1/phyrx_user_info.h                   |  202 ++
 hw/fig/v1/phyrx_vht_sig_a.h                   |  112 +
 hw/fig/v1/phytx_abort_request_info.h          |   38 +
 hw/fig/v1/phytx_pkt_end.h                     |  243 ++
 hw/fig/v1/phytx_ppdu_header_info_request.h    |   40 +
 hw/fig/v1/receive_pkt_start_info.h            |   87 +
 hw/fig/v1/receive_rssi_info.h                 |  465 ++++
 hw/fig/v1/receive_user_info.h                 |  271 ++
 hw/fig/v1/received_response_user_15_8.h       | 1116 ++++++++
 hw/fig/v1/received_response_user_23_16.h      | 1116 ++++++++
 hw/fig/v1/received_response_user_31_24.h      | 1116 ++++++++
 hw/fig/v1/received_response_user_36_32.h      |  705 +++++
 hw/fig/v1/received_response_user_7_0.h        | 1116 ++++++++
 hw/fig/v1/received_response_user_info.h       |  206 ++
 hw/fig/v1/received_trigger_info.h             |  142 +
 hw/fig/v1/received_trigger_info_details.h     |  191 ++
 .../reo_descriptor_threshold_reached_status.h |  257 ++
 hw/fig/v1/reo_destination_ring.h              |  305 +++
 hw/fig/v1/reo_destination_ring_with_pn.h      |  277 ++
 hw/fig/v1/reo_entrance_ring.h                 |  328 +++
 hw/fig/v1/reo_flush_cache.h                   |  156 ++
 hw/fig/v1/reo_flush_cache_status.h            |  285 ++
 hw/fig/v1/reo_flush_queue.h                   |  121 +
 hw/fig/v1/reo_flush_queue_status.h            |  229 ++
 hw/fig/v1/reo_flush_timeout_list.h            |  114 +
 hw/fig/v1/reo_flush_timeout_list_status.h     |  243 ++
 hw/fig/v1/reo_get_queue_stats.h               |  114 +
 hw/fig/v1/reo_get_queue_stats_status.h        |  306 +++
 hw/fig/v1/reo_unblock_cache.h                 |  114 +
 hw/fig/v1/reo_unblock_cache_status.h          |  236 ++
 hw/fig/v1/reo_update_rx_reo_queue.h           |  422 +++
 hw/fig/v1/reo_update_rx_reo_queue_status.h    |  222 ++
 hw/fig/v1/response_end_status.h               |  256 ++
 hw/fig/v1/response_start_status.h             |   63 +
 hw/fig/v1/ru_allocation_160_info.h            |  115 +
 hw/fig/v1/rx_attention.h                      |  376 +++
 hw/fig/v1/rx_flow_search_entry.h              |  213 ++
 hw/fig/v1/rx_frame_1k_bitmap_ack.h            |  362 +++
 hw/fig/v1/rx_frame_bitmap_ack.h               |  236 ++
 hw/fig/v1/rx_frame_bitmap_req.h               |   75 +
 hw/fig/v1/rx_location_info.h                  |  453 ++++
 hw/fig/v1/rx_mpdu_desc_info.h                 |  101 +
 hw/fig/v1/rx_mpdu_details.h                   |  131 +
 hw/fig/v1/rx_mpdu_end.h                       |  175 ++
 hw/fig/v1/rx_mpdu_ext_desc_info.h             |   52 +
 hw/fig/v1/rx_mpdu_info.h                      |  958 +++++++
 hw/fig/v1/rx_mpdu_link_ptr.h                  |   40 +
 hw/fig/v1/rx_mpdu_start.h                     |  702 +++++
 hw/fig/v1/rx_msdu_desc_info.h                 |  131 +
 hw/fig/v1/rx_msdu_details.h                   |  161 ++
 hw/fig/v1/rx_msdu_end.h                       | 1087 ++++++++
 hw/fig/v1/rx_msdu_ext_desc_info.h             |   59 +
 hw/fig/v1/rx_msdu_link.h                      | 2051 ++++++++++++++
 hw/fig/v1/rx_msdu_start.h                     |  306 +++
 hw/fig/v1/rx_ppdu_ack_report.h                |   54 +
 hw/fig/v1/rx_ppdu_end_user_stats.h            |  679 +++++
 hw/fig/v1/rx_ppdu_end_user_stats_ext.h        |  133 +
 hw/fig/v1/rx_ppdu_no_ack_report.h             |   87 +
 hw/fig/v1/rx_ppdu_start.h                     |   75 +
 hw/fig/v1/rx_ppdu_start_user_info.h           |  202 ++
 hw/fig/v1/rx_preamble.h                       |   54 +
 hw/fig/v1/rx_reo_queue.h                      |  502 ++++
 hw/fig/v1/rx_reo_queue_1k.h                   |  257 ++
 hw/fig/v1/rx_reo_queue_ext.h                  |  378 +++
 hw/fig/v1/rx_response_required_info.h         |  750 +++++
 hw/fig/v1/rx_rxpcu_classification_overview.h  |   94 +
 hw/fig/v1/rx_start_param.h                    |   47 +
 hw/fig/v1/rx_timing_info.h                    |   66 +
 hw/fig/v1/rx_trig_info.h                      |   54 +
 hw/fig/v1/rxpcu_early_rx_indication.h         |   61 +
 hw/fig/v1/rxpcu_ppdu_end_info.h               |  925 +++++++
 hw/fig/v1/rxpcu_ppdu_end_layout_info.h        |  320 +++
 hw/fig/v1/rxpt_classify_info.h                |  122 +
 hw/fig/v1/seq_hwio.h                          |   41 +
 hw/fig/v1/tcl_assist_cmd.h                    |  411 +++
 hw/fig/v1/tcl_data_cmd.h                      |  278 ++
 hw/fig/v1/tcl_gse_cmd.h                       |  143 +
 hw/fig/v1/tcl_status_ring.h                   |  129 +
 hw/fig/v1/tlv_hdr.h                           |  634 +++++
 hw/fig/v1/tlv_tag_def.h                       | 1976 ++++++++++++++
 hw/fig/v1/tqm2sw_completion_ring.h            |  262 ++
 hw/fig/v1/tx_cbf_info.h                       |  454 ++++
 hw/fig/v1/tx_fes_setup.h                      |  550 ++++
 hw/fig/v1/tx_fes_status_1k_ba.h               |  313 +++
 hw/fig/v1/tx_fes_status_ack_or_ba.h           |  145 +
 hw/fig/v1/tx_fes_status_end.h                 |  581 ++++
 hw/fig/v1/tx_fes_status_prot.h                |  156 ++
 hw/fig/v1/tx_fes_status_start.h               |  117 +
 hw/fig/v1/tx_fes_status_start_ppdu.h          |  271 ++
 hw/fig/v1/tx_fes_status_start_prot.h          |  264 ++
 hw/fig/v1/tx_fes_status_user_ppdu.h           |  180 ++
 hw/fig/v1/tx_fes_status_user_response.h       |   65 +
 hw/fig/v1/tx_flush_req.h                      |   61 +
 hw/fig/v1/tx_mpdu_start.h                     |  292 ++
 hw/fig/v1/tx_msdu_extension.h                 |  318 +++
 hw/fig/v1/tx_msdu_start.h                     |  250 ++
 hw/fig/v1/tx_peer_entry.h                     |  391 +++
 hw/fig/v1/tx_queue_extension.h                |  411 +++
 hw/fig/v1/tx_rate_stats_info.h                |  108 +
 hw/fig/v1/tx_raw_or_native_frame_setup.h      |  285 ++
 hw/fig/v1/txpcu_buffer_basics.h               |   38 +
 hw/fig/v1/txpcu_buffer_status.h               |   58 +
 hw/fig/v1/txpcu_user_buffer_status.h          |   65 +
 hw/fig/v1/u_sig_eht_su_mu_info.h              |  157 ++
 hw/fig/v1/u_sig_eht_tb_info.h                 |  122 +
 hw/fig/v1/unallocated_ru_160_info.h           |   45 +
 hw/fig/v1/uniform_descriptor_header.h         |   45 +
 hw/fig/v1/uniform_reo_cmd_header.h            |   38 +
 hw/fig/v1/uniform_reo_status_header.h         |   52 +
 hw/fig/v1/vht_sig_a_info.h                    |  143 +
 hw/fig/v1/vht_sig_b_mu160_info.h              |  241 ++
 hw/fig/v1/vht_sig_b_mu20_info.h               |   52 +
 hw/fig/v1/vht_sig_b_mu40_info.h               |   80 +
 hw/fig/v1/vht_sig_b_mu80_info.h               |  129 +
 hw/fig/v1/vht_sig_b_su160_info.h              |  297 ++
 hw/fig/v1/vht_sig_b_su20_info.h               |   52 +
 hw/fig/v1/vht_sig_b_su40_info.h               |   87 +
 hw/fig/v1/vht_sig_b_su80_info.h               |  157 ++
 hw/fig/v1/wbm2sw_completion_ring_rx.h         |  289 ++
 hw/fig/v1/wbm2sw_completion_ring_tx.h         |  243 ++
 hw/fig/v1/wbm_buffer_ring.h                   |   40 +
 hw/fig/v1/wbm_link_descriptor_ring.h          |   40 +
 hw/fig/v1/wbm_release_ring.h                  |  117 +
 hw/fig/v1/wbm_release_ring_rx.h               |   75 +
 hw/fig/v1/wbm_release_ring_tx.h               |   68 +
 hw/fig/v1/wcss_seq_hwiobase.h                 |  104 +
 hw/fig/v1/wcss_seq_hwioreg_umac.h             | 2413 +++++++++++++++++
 hw/fig/v1/wcss_version.h                      |    5 +
 208 files changed, 52217 insertions(+)
 create mode 100644 hw/fig/v1/HALcomdef.h
 create mode 100644 hw/fig/v1/HALhwio.h
 create mode 100644 hw/fig/v1/ack_report.h
 create mode 100644 hw/fig/v1/boron_top_reg.h
 create mode 100644 hw/fig/v1/buffer_addr_info.h
 create mode 100644 hw/fig/v1/ce_src_desc.h
 create mode 100644 hw/fig/v1/ce_stat_desc.h
 create mode 100644 hw/fig/v1/coex_rx_status.h
 create mode 100644 hw/fig/v1/coex_tx_req.h
 create mode 100644 hw/fig/v1/coex_tx_status.h
 create mode 100644 hw/fig/v1/com_dtypes.h
 create mode 100644 hw/fig/v1/eht_sig_usr_mu_mimo_info.h
 create mode 100644 hw/fig/v1/eht_sig_usr_ofdma_info.h
 create mode 100644 hw/fig/v1/eht_sig_usr_su_info.h
 create mode 100644 hw/fig/v1/expected_response.h
 create mode 100644 hw/fig/v1/he_sig_a_mu_dl_info.h
 create mode 100644 hw/fig/v1/he_sig_a_mu_ul_info.h
 create mode 100644 hw/fig/v1/he_sig_a_su_info.h
 create mode 100644 hw/fig/v1/he_sig_b1_mu_info.h
 create mode 100644 hw/fig/v1/he_sig_b2_mu_info.h
 create mode 100644 hw/fig/v1/he_sig_b2_ofdma_info.h
 create mode 100644 hw/fig/v1/ht_sig_info.h
 create mode 100644 hw/fig/v1/l_sig_a_info.h
 create mode 100644 hw/fig/v1/l_sig_b_info.h
 create mode 100644 hw/fig/v1/macrx_abort_request_info.h
 create mode 100644 hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
 create mode 100644 hw/fig/v1/mactx_eht_sig_usr_ofdma.h
 create mode 100644 hw/fig/v1/mactx_eht_sig_usr_su.h
 create mode 100644 hw/fig/v1/mactx_he_sig_a_mu_dl.h
 create mode 100644 hw/fig/v1/mactx_he_sig_a_mu_ul.h
 create mode 100644 hw/fig/v1/mactx_he_sig_a_su.h
 create mode 100644 hw/fig/v1/mactx_he_sig_b1_mu.h
 create mode 100644 hw/fig/v1/mactx_he_sig_b2_mu.h
 create mode 100644 hw/fig/v1/mactx_he_sig_b2_ofdma.h
 create mode 100644 hw/fig/v1/mactx_ht_sig.h
 create mode 100644 hw/fig/v1/mactx_l_sig_a.h
 create mode 100644 hw/fig/v1/mactx_l_sig_b.h
 create mode 100644 hw/fig/v1/mactx_phy_desc.h
 create mode 100644 hw/fig/v1/mactx_u_sig_eht_su_mu.h
 create mode 100644 hw/fig/v1/mactx_u_sig_eht_tb.h
 create mode 100644 hw/fig/v1/mactx_user_desc_common.h
 create mode 100644 hw/fig/v1/mactx_user_desc_per_user.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_a.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_mu160.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_mu20.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_mu40.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_mu80.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_su160.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_su20.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_su40.h
 create mode 100644 hw/fig/v1/mactx_vht_sig_b_su80.h
 create mode 100644 hw/fig/v1/mlo_sta_id_details.h
 create mode 100644 hw/fig/v1/mon_buffer_addr.h
 create mode 100644 hw/fig/v1/mon_destination_ring.h
 create mode 100644 hw/fig/v1/mon_drop.h
 create mode 100644 hw/fig/v1/mon_ingress_ring.h
 create mode 100644 hw/fig/v1/msmhwiobase.h
 create mode 100644 hw/fig/v1/msmhwioreg.h
 create mode 100644 hw/fig/v1/no_ack_report.h
 create mode 100644 hw/fig/v1/ofdma_trigger_details.h
 create mode 100644 hw/fig/v1/pcu_ppdu_setup_init.h
 create mode 100644 hw/fig/v1/pdg_response.h
 create mode 100644 hw/fig/v1/pdg_response_rate_setting.h
 create mode 100644 hw/fig/v1/pdg_tx_req.h
 create mode 100644 hw/fig/v1/phyrx_abort_request_info.h
 create mode 100644 hw/fig/v1/phyrx_common_user_info.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_a_mu_dl.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_a_mu_ul.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_a_su.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_b1_mu.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_b2_mu.h
 create mode 100644 hw/fig/v1/phyrx_he_sig_b2_ofdma.h
 create mode 100644 hw/fig/v1/phyrx_ht_sig.h
 create mode 100644 hw/fig/v1/phyrx_l_sig_a.h
 create mode 100644 hw/fig/v1/phyrx_l_sig_b.h
 create mode 100644 hw/fig/v1/phyrx_location.h
 create mode 100644 hw/fig/v1/phyrx_other_receive_info_ru_details.h
 create mode 100644 hw/fig/v1/phyrx_pkt_end.h
 create mode 100644 hw/fig/v1/phyrx_pkt_end_info.h
 create mode 100644 hw/fig/v1/phyrx_rssi_legacy.h
 create mode 100644 hw/fig/v1/phyrx_user_info.h
 create mode 100644 hw/fig/v1/phyrx_vht_sig_a.h
 create mode 100644 hw/fig/v1/phytx_abort_request_info.h
 create mode 100644 hw/fig/v1/phytx_pkt_end.h
 create mode 100644 hw/fig/v1/phytx_ppdu_header_info_request.h
 create mode 100644 hw/fig/v1/receive_pkt_start_info.h
 create mode 100644 hw/fig/v1/receive_rssi_info.h
 create mode 100644 hw/fig/v1/receive_user_info.h
 create mode 100644 hw/fig/v1/received_response_user_15_8.h
 create mode 100644 hw/fig/v1/received_response_user_23_16.h
 create mode 100644 hw/fig/v1/received_response_user_31_24.h
 create mode 100644 hw/fig/v1/received_response_user_36_32.h
 create mode 100644 hw/fig/v1/received_response_user_7_0.h
 create mode 100644 hw/fig/v1/received_response_user_info.h
 create mode 100644 hw/fig/v1/received_trigger_info.h
 create mode 100644 hw/fig/v1/received_trigger_info_details.h
 create mode 100644 hw/fig/v1/reo_descriptor_threshold_reached_status.h
 create mode 100644 hw/fig/v1/reo_destination_ring.h
 create mode 100644 hw/fig/v1/reo_destination_ring_with_pn.h
 create mode 100644 hw/fig/v1/reo_entrance_ring.h
 create mode 100644 hw/fig/v1/reo_flush_cache.h
 create mode 100644 hw/fig/v1/reo_flush_cache_status.h
 create mode 100644 hw/fig/v1/reo_flush_queue.h
 create mode 100644 hw/fig/v1/reo_flush_queue_status.h
 create mode 100644 hw/fig/v1/reo_flush_timeout_list.h
 create mode 100644 hw/fig/v1/reo_flush_timeout_list_status.h
 create mode 100644 hw/fig/v1/reo_get_queue_stats.h
 create mode 100644 hw/fig/v1/reo_get_queue_stats_status.h
 create mode 100644 hw/fig/v1/reo_unblock_cache.h
 create mode 100644 hw/fig/v1/reo_unblock_cache_status.h
 create mode 100644 hw/fig/v1/reo_update_rx_reo_queue.h
 create mode 100644 hw/fig/v1/reo_update_rx_reo_queue_status.h
 create mode 100644 hw/fig/v1/response_end_status.h
 create mode 100644 hw/fig/v1/response_start_status.h
 create mode 100644 hw/fig/v1/ru_allocation_160_info.h
 create mode 100644 hw/fig/v1/rx_attention.h
 create mode 100644 hw/fig/v1/rx_flow_search_entry.h
 create mode 100644 hw/fig/v1/rx_frame_1k_bitmap_ack.h
 create mode 100644 hw/fig/v1/rx_frame_bitmap_ack.h
 create mode 100644 hw/fig/v1/rx_frame_bitmap_req.h
 create mode 100644 hw/fig/v1/rx_location_info.h
 create mode 100644 hw/fig/v1/rx_mpdu_desc_info.h
 create mode 100644 hw/fig/v1/rx_mpdu_details.h
 create mode 100644 hw/fig/v1/rx_mpdu_end.h
 create mode 100644 hw/fig/v1/rx_mpdu_ext_desc_info.h
 create mode 100644 hw/fig/v1/rx_mpdu_info.h
 create mode 100644 hw/fig/v1/rx_mpdu_link_ptr.h
 create mode 100644 hw/fig/v1/rx_mpdu_start.h
 create mode 100644 hw/fig/v1/rx_msdu_desc_info.h
 create mode 100644 hw/fig/v1/rx_msdu_details.h
 create mode 100644 hw/fig/v1/rx_msdu_end.h
 create mode 100644 hw/fig/v1/rx_msdu_ext_desc_info.h
 create mode 100644 hw/fig/v1/rx_msdu_link.h
 create mode 100644 hw/fig/v1/rx_msdu_start.h
 create mode 100644 hw/fig/v1/rx_ppdu_ack_report.h
 create mode 100644 hw/fig/v1/rx_ppdu_end_user_stats.h
 create mode 100644 hw/fig/v1/rx_ppdu_end_user_stats_ext.h
 create mode 100644 hw/fig/v1/rx_ppdu_no_ack_report.h
 create mode 100644 hw/fig/v1/rx_ppdu_start.h
 create mode 100644 hw/fig/v1/rx_ppdu_start_user_info.h
 create mode 100644 hw/fig/v1/rx_preamble.h
 create mode 100644 hw/fig/v1/rx_reo_queue.h
 create mode 100644 hw/fig/v1/rx_reo_queue_1k.h
 create mode 100644 hw/fig/v1/rx_reo_queue_ext.h
 create mode 100644 hw/fig/v1/rx_response_required_info.h
 create mode 100644 hw/fig/v1/rx_rxpcu_classification_overview.h
 create mode 100644 hw/fig/v1/rx_start_param.h
 create mode 100644 hw/fig/v1/rx_timing_info.h
 create mode 100644 hw/fig/v1/rx_trig_info.h
 create mode 100644 hw/fig/v1/rxpcu_early_rx_indication.h
 create mode 100644 hw/fig/v1/rxpcu_ppdu_end_info.h
 create mode 100644 hw/fig/v1/rxpcu_ppdu_end_layout_info.h
 create mode 100644 hw/fig/v1/rxpt_classify_info.h
 create mode 100644 hw/fig/v1/seq_hwio.h
 create mode 100644 hw/fig/v1/tcl_assist_cmd.h
 create mode 100644 hw/fig/v1/tcl_data_cmd.h
 create mode 100644 hw/fig/v1/tcl_gse_cmd.h
 create mode 100644 hw/fig/v1/tcl_status_ring.h
 create mode 100644 hw/fig/v1/tlv_hdr.h
 create mode 100644 hw/fig/v1/tlv_tag_def.h
 create mode 100644 hw/fig/v1/tqm2sw_completion_ring.h
 create mode 100644 hw/fig/v1/tx_cbf_info.h
 create mode 100644 hw/fig/v1/tx_fes_setup.h
 create mode 100644 hw/fig/v1/tx_fes_status_1k_ba.h
 create mode 100644 hw/fig/v1/tx_fes_status_ack_or_ba.h
 create mode 100644 hw/fig/v1/tx_fes_status_end.h
 create mode 100644 hw/fig/v1/tx_fes_status_prot.h
 create mode 100644 hw/fig/v1/tx_fes_status_start.h
 create mode 100644 hw/fig/v1/tx_fes_status_start_ppdu.h
 create mode 100644 hw/fig/v1/tx_fes_status_start_prot.h
 create mode 100644 hw/fig/v1/tx_fes_status_user_ppdu.h
 create mode 100644 hw/fig/v1/tx_fes_status_user_response.h
 create mode 100644 hw/fig/v1/tx_flush_req.h
 create mode 100644 hw/fig/v1/tx_mpdu_start.h
 create mode 100644 hw/fig/v1/tx_msdu_extension.h
 create mode 100644 hw/fig/v1/tx_msdu_start.h
 create mode 100644 hw/fig/v1/tx_peer_entry.h
 create mode 100644 hw/fig/v1/tx_queue_extension.h
 create mode 100644 hw/fig/v1/tx_rate_stats_info.h
 create mode 100644 hw/fig/v1/tx_raw_or_native_frame_setup.h
 create mode 100644 hw/fig/v1/txpcu_buffer_basics.h
 create mode 100644 hw/fig/v1/txpcu_buffer_status.h
 create mode 100644 hw/fig/v1/txpcu_user_buffer_status.h
 create mode 100644 hw/fig/v1/u_sig_eht_su_mu_info.h
 create mode 100644 hw/fig/v1/u_sig_eht_tb_info.h
 create mode 100644 hw/fig/v1/unallocated_ru_160_info.h
 create mode 100644 hw/fig/v1/uniform_descriptor_header.h
 create mode 100644 hw/fig/v1/uniform_reo_cmd_header.h
 create mode 100644 hw/fig/v1/uniform_reo_status_header.h
 create mode 100644 hw/fig/v1/vht_sig_a_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_mu160_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_mu20_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_mu40_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_mu80_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_su160_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_su20_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_su40_info.h
 create mode 100644 hw/fig/v1/vht_sig_b_su80_info.h
 create mode 100644 hw/fig/v1/wbm2sw_completion_ring_rx.h
 create mode 100644 hw/fig/v1/wbm2sw_completion_ring_tx.h
 create mode 100644 hw/fig/v1/wbm_buffer_ring.h
 create mode 100644 hw/fig/v1/wbm_link_descriptor_ring.h
 create mode 100644 hw/fig/v1/wbm_release_ring.h
 create mode 100644 hw/fig/v1/wbm_release_ring_rx.h
 create mode 100644 hw/fig/v1/wbm_release_ring_tx.h
 create mode 100644 hw/fig/v1/wcss_seq_hwiobase.h
 create mode 100644 hw/fig/v1/wcss_seq_hwioreg_umac.h
 create mode 100644 hw/fig/v1/wcss_version.h

diff --git a/hw/fig/v1/HALcomdef.h b/hw/fig/v1/HALcomdef.h
new file mode 100644
index 000000000000..fd5cc2f41dcb
--- /dev/null
+++ b/hw/fig/v1/HALcomdef.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/hw/fig/v1/HALhwio.h b/hw/fig/v1/HALhwio.h
new file mode 100644
index 000000000000..53f7d7ef21e5
--- /dev/null
+++ b/hw/fig/v1/HALhwio.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  {	\
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                               }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                               }
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+                                                                               }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask))
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/hw/fig/v1/ack_report.h b/hw/fig/v1/ack_report.h
new file mode 100644
index 000000000000..e78921b308fd
--- /dev/null
+++ b/hw/fig/v1/ack_report.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t selfgen_response_reason                                 :  4,
+                      ax_trigger_type                                         :  4,
+                      sr_ppdu                                                 :  1,
+                      reserved                                                :  7,
+                      frame_control                                           : 16;
+#else
+             uint32_t frame_control                                           : 16,
+                      reserved                                                :  7,
+                      sr_ppdu                                                 :  1,
+                      ax_trigger_type                                         :  4,
+                      selfgen_response_reason                                 :  4;
+#endif
+};
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0
+
+#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
+#define ACK_REPORT_SR_PPDU_LSB                                                      8
+#define ACK_REPORT_SR_PPDU_MSB                                                      8
+#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100
+
+#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
+#define ACK_REPORT_RESERVED_LSB                                                     9
+#define ACK_REPORT_RESERVED_MSB                                                     15
+#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
+#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
+#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/fig/v1/boron_top_reg.h b/hw/fig/v1/boron_top_reg.h
new file mode 100644
index 000000000000..306398284fe3
--- /dev/null
+++ b/hw/fig/v1/boron_top_reg.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef BORON_TOP_REG_H
+#define BORON_TOP_REG_H
+
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
+
+#endif
diff --git a/hw/fig/v1/buffer_addr_info.h b/hw/fig/v1/buffer_addr_info.h
new file mode 100644
index 000000000000..d65375b54715
--- /dev/null
+++ b/hw/fig/v1/buffer_addr_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t buffer_addr_39_32                                       :  8,
+                      return_buffer_manager                                   :  4,
+                      sw_buffer_cookie                                        : 20;
+#else
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      return_buffer_manager                                   :  4,
+                      buffer_addr_39_32                                       :  8;
+#endif
+};
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                                    0x00000000
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB                                       0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB                                       31
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK                                      0xffffffff
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                                   0x00000004
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB                                      0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB                                      7
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK                                     0x000000ff
+
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                               0x00000004
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                                  8
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                                  11
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                                 0x00000f00
+
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                                    0x00000004
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB                                       12
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB                                       31
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK                                      0xfffff000
+
+#endif
diff --git a/hw/fig/v1/ce_src_desc.h b/hw/fig/v1/ce_src_desc.h
new file mode 100644
index 000000000000..4ecaedcab2a7
--- /dev/null
+++ b/hw/fig/v1/ce_src_desc.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t src_buffer_high                                         :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      ce_res_0                                                :  1,
+                      barrier_read                                            :  1,
+                      ce_res_1                                                :  2,
+                      length                                                  : 16;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_2                                                : 16;
+             uint32_t ce_res_3                                                : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t length                                                  : 16,
+                      ce_res_1                                                :  2,
+                      barrier_read                                            :  1,
+                      ce_res_0                                                :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      src_buffer_high                                         :  8;
+             uint32_t ce_res_2                                                : 16,
+                      fw_metadata                                             : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_3                                                : 20;
+#endif
+};
+
+#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET                                           0x00000000
+#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB                                              0
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB                                              31
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK                                             0xffffffff
+
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET                                          0x00000004
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB                                             0
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB                                             7
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK                                            0x000000ff
+
+#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET                                              0x00000004
+#define CE_SRC_DESC_TOEPLITZ_EN_LSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MASK                                                0x00000100
+
+#define CE_SRC_DESC_SRC_SWAP_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_SRC_SWAP_LSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MASK                                                   0x00000200
+
+#define CE_SRC_DESC_DEST_SWAP_OFFSET                                                0x00000004
+#define CE_SRC_DESC_DEST_SWAP_LSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MASK                                                  0x00000400
+
+#define CE_SRC_DESC_GATHER_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_GATHER_LSB                                                      11
+#define CE_SRC_DESC_GATHER_MSB                                                      11
+#define CE_SRC_DESC_GATHER_MASK                                                     0x00000800
+
+#define CE_SRC_DESC_CE_RES_0_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_0_LSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MASK                                                   0x00001000
+
+#define CE_SRC_DESC_BARRIER_READ_OFFSET                                             0x00000004
+#define CE_SRC_DESC_BARRIER_READ_LSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MASK                                               0x00002000
+
+#define CE_SRC_DESC_CE_RES_1_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_1_LSB                                                    14
+#define CE_SRC_DESC_CE_RES_1_MSB                                                    15
+#define CE_SRC_DESC_CE_RES_1_MASK                                                   0x0000c000
+
+#define CE_SRC_DESC_LENGTH_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_LENGTH_LSB                                                      16
+#define CE_SRC_DESC_LENGTH_MSB                                                      31
+#define CE_SRC_DESC_LENGTH_MASK                                                     0xffff0000
+
+#define CE_SRC_DESC_FW_METADATA_OFFSET                                              0x00000008
+#define CE_SRC_DESC_FW_METADATA_LSB                                                 0
+#define CE_SRC_DESC_FW_METADATA_MSB                                                 15
+#define CE_SRC_DESC_FW_METADATA_MASK                                                0x0000ffff
+
+#define CE_SRC_DESC_CE_RES_2_OFFSET                                                 0x00000008
+#define CE_SRC_DESC_CE_RES_2_LSB                                                    16
+#define CE_SRC_DESC_CE_RES_2_MSB                                                    31
+#define CE_SRC_DESC_CE_RES_2_MASK                                                   0xffff0000
+
+#define CE_SRC_DESC_CE_RES_3_OFFSET                                                 0x0000000c
+#define CE_SRC_DESC_CE_RES_3_LSB                                                    0
+#define CE_SRC_DESC_CE_RES_3_MSB                                                    19
+#define CE_SRC_DESC_CE_RES_3_MASK                                                   0x000fffff
+
+#define CE_SRC_DESC_RING_ID_OFFSET                                                  0x0000000c
+#define CE_SRC_DESC_RING_ID_LSB                                                     20
+#define CE_SRC_DESC_RING_ID_MSB                                                     27
+#define CE_SRC_DESC_RING_ID_MASK                                                    0x0ff00000
+
+#define CE_SRC_DESC_LOOPING_COUNT_OFFSET                                            0x0000000c
+#define CE_SRC_DESC_LOOPING_COUNT_LSB                                               28
+#define CE_SRC_DESC_LOOPING_COUNT_MSB                                               31
+#define CE_SRC_DESC_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/fig/v1/ce_stat_desc.h b/hw/fig/v1/ce_stat_desc.h
new file mode 100644
index 000000000000..0b9f9a221215
--- /dev/null
+++ b/hw/fig/v1/ce_stat_desc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ce_res_5                                                :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      barrier_read                                            :  1,
+                      ce_res_6                                                :  3,
+                      length                                                  : 16;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_7                                                :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t length                                                  : 16,
+                      ce_res_6                                                :  3,
+                      barrier_read                                            :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      ce_res_5                                                :  8;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_7                                                :  4,
+                      fw_metadata                                             : 16;
+#endif
+};
+
+#define CE_STAT_DESC_CE_RES_5_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_5_LSB                                                   0
+#define CE_STAT_DESC_CE_RES_5_MSB                                                   7
+#define CE_STAT_DESC_CE_RES_5_MASK                                                  0x000000ff
+
+#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET                                             0x00000000
+#define CE_STAT_DESC_TOEPLITZ_EN_LSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MASK                                               0x00000100
+
+#define CE_STAT_DESC_SRC_SWAP_OFFSET                                                0x00000000
+#define CE_STAT_DESC_SRC_SWAP_LSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MASK                                                  0x00000200
+
+#define CE_STAT_DESC_DEST_SWAP_OFFSET                                               0x00000000
+#define CE_STAT_DESC_DEST_SWAP_LSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MASK                                                 0x00000400
+
+#define CE_STAT_DESC_GATHER_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_GATHER_LSB                                                     11
+#define CE_STAT_DESC_GATHER_MSB                                                     11
+#define CE_STAT_DESC_GATHER_MASK                                                    0x00000800
+
+#define CE_STAT_DESC_BARRIER_READ_OFFSET                                            0x00000000
+#define CE_STAT_DESC_BARRIER_READ_LSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MASK                                              0x00001000
+
+#define CE_STAT_DESC_CE_RES_6_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_6_LSB                                                   13
+#define CE_STAT_DESC_CE_RES_6_MSB                                                   15
+#define CE_STAT_DESC_CE_RES_6_MASK                                                  0x0000e000
+
+#define CE_STAT_DESC_LENGTH_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_LENGTH_LSB                                                     16
+#define CE_STAT_DESC_LENGTH_MSB                                                     31
+#define CE_STAT_DESC_LENGTH_MASK                                                    0xffff0000
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET                                         0x00000004
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET                                         0x00000008
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_FW_METADATA_OFFSET                                             0x0000000c
+#define CE_STAT_DESC_FW_METADATA_LSB                                                0
+#define CE_STAT_DESC_FW_METADATA_MSB                                                15
+#define CE_STAT_DESC_FW_METADATA_MASK                                               0x0000ffff
+
+#define CE_STAT_DESC_CE_RES_7_OFFSET                                                0x0000000c
+#define CE_STAT_DESC_CE_RES_7_LSB                                                   16
+#define CE_STAT_DESC_CE_RES_7_MSB                                                   19
+#define CE_STAT_DESC_CE_RES_7_MASK                                                  0x000f0000
+
+#define CE_STAT_DESC_RING_ID_OFFSET                                                 0x0000000c
+#define CE_STAT_DESC_RING_ID_LSB                                                    20
+#define CE_STAT_DESC_RING_ID_MSB                                                    27
+#define CE_STAT_DESC_RING_ID_MASK                                                   0x0ff00000
+
+#define CE_STAT_DESC_LOOPING_COUNT_OFFSET                                           0x0000000c
+#define CE_STAT_DESC_LOOPING_COUNT_LSB                                              28
+#define CE_STAT_DESC_LOOPING_COUNT_MSB                                              31
+#define CE_STAT_DESC_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/fig/v1/coex_rx_status.h b/hw/fig/v1/coex_rx_status.h
new file mode 100644
index 000000000000..7d9c6b4d2057
--- /dev/null
+++ b/hw/fig/v1/coex_rx_status.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_RX_STATUS_H_
+#define _COEX_RX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_RX_STATUS 2
+
+#define NUM_OF_QWORDS_COEX_RX_STATUS 1
+
+struct coex_rx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_mac_frame_status                                     :  2,
+                      rx_with_tx_response                                     :  1,
+                      rx_rate                                                 :  5,
+                      rx_bw                                                   :  3,
+                      single_mpdu                                             :  1,
+                      filter_status                                           :  1,
+                      ampdu                                                   :  1,
+                      directed                                                :  1,
+                      reserved_0                                              :  1,
+                      rx_nss                                                  :  3,
+                      rx_rssi                                                 :  8,
+                      rx_type                                                 :  3,
+                      retry_bit_setting                                       :  1,
+                      more_data_bit_setting                                   :  1;
+             uint32_t remain_rx_packet_time                                   : 16,
+                      rx_remaining_fes_time                                   : 16;
+#else
+             uint32_t more_data_bit_setting                                   :  1,
+                      retry_bit_setting                                       :  1,
+                      rx_type                                                 :  3,
+                      rx_rssi                                                 :  8,
+                      rx_nss                                                  :  3,
+                      reserved_0                                              :  1,
+                      directed                                                :  1,
+                      ampdu                                                   :  1,
+                      filter_status                                           :  1,
+                      single_mpdu                                             :  1,
+                      rx_bw                                                   :  3,
+                      rx_rate                                                 :  5,
+                      rx_with_tx_response                                     :  1,
+                      rx_mac_frame_status                                     :  2;
+             uint32_t rx_remaining_fes_time                                   : 16,
+                      remain_rx_packet_time                                   : 16;
+#endif
+};
+
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB                                      0
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB                                      1
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK                                     0x0000000000000003
+
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK                                     0x0000000000000004
+
+#define COEX_RX_STATUS_RX_RATE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RATE_LSB                                                  3
+#define COEX_RX_STATUS_RX_RATE_MSB                                                  7
+#define COEX_RX_STATUS_RX_RATE_MASK                                                 0x00000000000000f8
+
+#define COEX_RX_STATUS_RX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_BW_LSB                                                    8
+#define COEX_RX_STATUS_RX_BW_MSB                                                    10
+#define COEX_RX_STATUS_RX_BW_MASK                                                   0x0000000000000700
+
+#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET                                           0x0000000000000000
+#define COEX_RX_STATUS_SINGLE_MPDU_LSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MASK                                             0x0000000000000800
+
+#define COEX_RX_STATUS_FILTER_STATUS_OFFSET                                         0x0000000000000000
+#define COEX_RX_STATUS_FILTER_STATUS_LSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MASK                                           0x0000000000001000
+
+#define COEX_RX_STATUS_AMPDU_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_AMPDU_LSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MASK                                                   0x0000000000002000
+
+#define COEX_RX_STATUS_DIRECTED_OFFSET                                              0x0000000000000000
+#define COEX_RX_STATUS_DIRECTED_LSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MASK                                                0x0000000000004000
+
+#define COEX_RX_STATUS_RESERVED_0_OFFSET                                            0x0000000000000000
+#define COEX_RX_STATUS_RESERVED_0_LSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MASK                                              0x0000000000008000
+
+#define COEX_RX_STATUS_RX_NSS_OFFSET                                                0x0000000000000000
+#define COEX_RX_STATUS_RX_NSS_LSB                                                   16
+#define COEX_RX_STATUS_RX_NSS_MSB                                                   18
+#define COEX_RX_STATUS_RX_NSS_MASK                                                  0x0000000000070000
+
+#define COEX_RX_STATUS_RX_RSSI_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RSSI_LSB                                                  19
+#define COEX_RX_STATUS_RX_RSSI_MSB                                                  26
+#define COEX_RX_STATUS_RX_RSSI_MASK                                                 0x0000000007f80000
+
+#define COEX_RX_STATUS_RX_TYPE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_TYPE_LSB                                                  27
+#define COEX_RX_STATUS_RX_TYPE_MSB                                                  29
+#define COEX_RX_STATUS_RX_TYPE_MASK                                                 0x0000000038000000
+
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET                                     0x0000000000000000
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK                                       0x0000000040000000
+
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK                                   0x0000000080000000
+
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB                                    32
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB                                    47
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK                                   0x0000ffff00000000
+
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB                                    48
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB                                    63
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK                                   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/coex_tx_req.h b/hw/fig/v1/coex_tx_req.h
new file mode 100644
index 000000000000..ed5b4c57bfd8
--- /dev/null
+++ b/hw/fig/v1/coex_tx_req.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_REQ_H_
+#define _COEX_TX_REQ_H_
+
+#define NUM_OF_DWORDS_COEX_TX_REQ 6
+
+#define NUM_OF_QWORDS_COEX_TX_REQ 3
+
+struct coex_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      nss                                                     :  3,
+                      tx_chain_mask                                           :  8,
+                      bw                                                      :  3,
+                      reserved_0                                              :  2;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      reserved_1                                              :  2;
+             uint32_t tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8,
+                      wlan_request_duration                                   : 16;
+             uint32_t wlan_pkt_type                                           :  4,
+                      coex_tx_reason                                          :  2,
+                      response_frame_type                                     :  5,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_tx_priority                                        :  4,
+                      blackout_details_en                                     :  1,
+                      blackout_peek_duration                                  :  8,
+                      reserved_3a                                             :  5;
+             uint32_t frequency_channel_bonding_mask                          : 16,
+                      num_blackout_windows                                    :  8,
+                      reserved_4a                                             :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  2,
+                      bw                                                      :  3,
+                      tx_chain_mask                                           :  8,
+                      nss                                                     :  3,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8;
+             uint32_t reserved_1                                              :  2,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t wlan_request_duration                                   : 16,
+                      alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8;
+             uint32_t reserved_3a                                             :  5,
+                      blackout_peek_duration                                  :  8,
+                      blackout_details_en                                     :  1,
+                      coex_tx_priority                                        :  4,
+                      sch_tx_burst_ongoing                                    :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      response_frame_type                                     :  5,
+                      coex_tx_reason                                          :  2,
+                      wlan_pkt_type                                           :  4;
+             uint32_t reserved_4a                                             :  8,
+                      num_blackout_windows                                    :  8,
+                      frequency_channel_bonding_mask                          : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_REQ_TX_PWR_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_TX_PWR_LSB                                                      0
+#define COEX_TX_REQ_TX_PWR_MSB                                                      7
+#define COEX_TX_REQ_TX_PWR_MASK                                                     0x00000000000000ff
+
+#define COEX_TX_REQ_MIN_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_MIN_TX_PWR_LSB                                                  8
+#define COEX_TX_REQ_MIN_TX_PWR_MSB                                                  15
+#define COEX_TX_REQ_MIN_TX_PWR_MASK                                                 0x000000000000ff00
+
+#define COEX_TX_REQ_NSS_OFFSET                                                      0x0000000000000000
+#define COEX_TX_REQ_NSS_LSB                                                         16
+#define COEX_TX_REQ_NSS_MSB                                                         18
+#define COEX_TX_REQ_NSS_MASK                                                        0x0000000000070000
+
+#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET                                            0x0000000000000000
+#define COEX_TX_REQ_TX_CHAIN_MASK_LSB                                               19
+#define COEX_TX_REQ_TX_CHAIN_MASK_MSB                                               26
+#define COEX_TX_REQ_TX_CHAIN_MASK_MASK                                              0x0000000007f80000
+
+#define COEX_TX_REQ_BW_OFFSET                                                       0x0000000000000000
+#define COEX_TX_REQ_BW_LSB                                                          27
+#define COEX_TX_REQ_BW_MSB                                                          29
+#define COEX_TX_REQ_BW_MASK                                                         0x0000000038000000
+
+#define COEX_TX_REQ_RESERVED_0_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_0_LSB                                                  30
+#define COEX_TX_REQ_RESERVED_0_MSB                                                  31
+#define COEX_TX_REQ_RESERVED_0_MASK                                                 0x00000000c0000000
+
+#define COEX_TX_REQ_ALT_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_PWR_LSB                                                  32
+#define COEX_TX_REQ_ALT_TX_PWR_MSB                                                  39
+#define COEX_TX_REQ_ALT_TX_PWR_MASK                                                 0x000000ff00000000
+
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET                                           0x0000000000000000
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB                                              40
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB                                              47
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK                                             0x0000ff0000000000
+
+#define COEX_TX_REQ_ALT_NSS_OFFSET                                                  0x0000000000000000
+#define COEX_TX_REQ_ALT_NSS_LSB                                                     48
+#define COEX_TX_REQ_ALT_NSS_MSB                                                     50
+#define COEX_TX_REQ_ALT_NSS_MASK                                                    0x0007000000000000
+
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET                                        0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB                                           51
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB                                           58
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK                                          0x07f8000000000000
+
+#define COEX_TX_REQ_ALT_BW_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_ALT_BW_LSB                                                      59
+#define COEX_TX_REQ_ALT_BW_MSB                                                      61
+#define COEX_TX_REQ_ALT_BW_MASK                                                     0x3800000000000000
+
+#define COEX_TX_REQ_RESERVED_1_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_1_LSB                                                  62
+#define COEX_TX_REQ_RESERVED_1_MSB                                                  63
+#define COEX_TX_REQ_RESERVED_1_MASK                                                 0xc000000000000000
+
+#define COEX_TX_REQ_TX_PWR_1_OFFSET                                                 0x0000000000000008
+#define COEX_TX_REQ_TX_PWR_1_LSB                                                    0
+#define COEX_TX_REQ_TX_PWR_1_MSB                                                    7
+#define COEX_TX_REQ_TX_PWR_1_MASK                                                   0x00000000000000ff
+
+#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET                                             0x0000000000000008
+#define COEX_TX_REQ_ALT_TX_PWR_1_LSB                                                8
+#define COEX_TX_REQ_ALT_TX_PWR_1_MSB                                                15
+#define COEX_TX_REQ_ALT_TX_PWR_1_MASK                                               0x000000000000ff00
+
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET                                    0x0000000000000008
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB                                       16
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB                                       31
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK                                      0x00000000ffff0000
+
+#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET                                            0x0000000000000008
+#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB                                               32
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB                                               35
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK                                              0x0000000f00000000
+
+#define COEX_TX_REQ_COEX_TX_REASON_OFFSET                                           0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_REASON_LSB                                              36
+#define COEX_TX_REQ_COEX_TX_REASON_MSB                                              37
+#define COEX_TX_REQ_COEX_TX_REASON_MASK                                             0x0000003000000000
+
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB                                         38
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB                                         42
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK                                        0x000007c000000000
+
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET                        0x0000000000000008
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK                          0x0000080000000000
+
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET                       0x0000000000000008
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK                         0x0000100000000000
+
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET                                     0x0000000000000008
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK                                       0x0000200000000000
+
+#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET                                         0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB                                            46
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB                                            49
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK                                           0x0003c00000000000
+
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK                                        0x0004000000000000
+
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET                                   0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB                                      51
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB                                      58
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK                                     0x07f8000000000000
+
+#define COEX_TX_REQ_RESERVED_3A_OFFSET                                              0x0000000000000008
+#define COEX_TX_REQ_RESERVED_3A_LSB                                                 59
+#define COEX_TX_REQ_RESERVED_3A_MSB                                                 63
+#define COEX_TX_REQ_RESERVED_3A_MASK                                                0xf800000000000000
+
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET                           0x0000000000000010
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB                              0
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB                              15
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK                             0x000000000000ffff
+
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET                                     0x0000000000000010
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB                                        16
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB                                        23
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK                                       0x0000000000ff0000
+
+#define COEX_TX_REQ_RESERVED_4A_OFFSET                                              0x0000000000000010
+#define COEX_TX_REQ_RESERVED_4A_LSB                                                 24
+#define COEX_TX_REQ_RESERVED_4A_MSB                                                 31
+#define COEX_TX_REQ_RESERVED_4A_MASK                                                0x00000000ff000000
+
+#define COEX_TX_REQ_TLV64_PADDING_OFFSET                                            0x0000000000000010
+#define COEX_TX_REQ_TLV64_PADDING_LSB                                               32
+#define COEX_TX_REQ_TLV64_PADDING_MSB                                               63
+#define COEX_TX_REQ_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/coex_tx_status.h b/hw/fig/v1/coex_tx_status.h
new file mode 100644
index 000000000000..c47c29c2a5ba
--- /dev/null
+++ b/hw/fig/v1/coex_tx_status.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_STATUS_H_
+#define _COEX_TX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_TX_STATUS 4
+
+#define NUM_OF_QWORDS_COEX_TX_STATUS 2
+
+struct coex_tx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  7,
+                      tx_bw                                                   :  3,
+                      tx_status_reason                                        :  3,
+                      tx_wait_ack                                             :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      current_tx_duration                                     : 16;
+             uint32_t next_rx_active_time                                     : 16,
+                      remaining_fes_time                                      : 16;
+             uint32_t tx_antenna_mask                                         :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      reserved_2                                              :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t current_tx_duration                                     : 16,
+                      sch_tx_burst_ongoing                                    :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      tx_wait_ack                                             :  1,
+                      tx_status_reason                                        :  3,
+                      tx_bw                                                   :  3,
+                      reserved_0a                                             :  7;
+             uint32_t remaining_fes_time                                      : 16,
+                      next_rx_active_time                                     : 16;
+             uint32_t reserved_2                                              :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      tx_antenna_mask                                         :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_STATUS_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_RESERVED_0A_LSB                                              0
+#define COEX_TX_STATUS_RESERVED_0A_MSB                                              6
+#define COEX_TX_STATUS_RESERVED_0A_MASK                                             0x000000000000007f
+
+#define COEX_TX_STATUS_TX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_TX_STATUS_TX_BW_LSB                                                    7
+#define COEX_TX_STATUS_TX_BW_MSB                                                    9
+#define COEX_TX_STATUS_TX_BW_MASK                                                   0x0000000000000380
+
+#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET                                      0x0000000000000000
+#define COEX_TX_STATUS_TX_STATUS_REASON_LSB                                         10
+#define COEX_TX_STATUS_TX_STATUS_REASON_MSB                                         12
+#define COEX_TX_STATUS_TX_STATUS_REASON_MASK                                        0x0000000000001c00
+
+#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_TX_WAIT_ACK_LSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MASK                                             0x0000000000002000
+
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK                                     0x0000000000004000
+
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET                                  0x0000000000000000
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK                                    0x0000000000008000
+
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB                                      16
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB                                      31
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK                                     0x00000000ffff0000
+
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB                                      32
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB                                      47
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK                                     0x0000ffff00000000
+
+#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET                                    0x0000000000000000
+#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB                                       48
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB                                       63
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK                                      0xffff000000000000
+
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET                                       0x0000000000000008
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB                                          0
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB                                          7
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK                                         0x00000000000000ff
+
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET                                     0x0000000000000008
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB                                        8
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB                                        15
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK                                       0x000000000000ff00
+
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET                                      0x0000000000000008
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB                                         16
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB                                         23
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK                                        0x0000000000ff0000
+
+#define COEX_TX_STATUS_RESERVED_2_OFFSET                                            0x0000000000000008
+#define COEX_TX_STATUS_RESERVED_2_LSB                                               24
+#define COEX_TX_STATUS_RESERVED_2_MSB                                               31
+#define COEX_TX_STATUS_RESERVED_2_MASK                                              0x00000000ff000000
+
+#define COEX_TX_STATUS_TLV64_PADDING_OFFSET                                         0x0000000000000008
+#define COEX_TX_STATUS_TLV64_PADDING_LSB                                            32
+#define COEX_TX_STATUS_TLV64_PADDING_MSB                                            63
+#define COEX_TX_STATUS_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/com_dtypes.h b/hw/fig/v1/com_dtypes.h
new file mode 100644
index 000000000000..a122ca419081
--- /dev/null
+++ b/hw/fig/v1/com_dtypes.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE   1
+#define FALSE  0
+
+#define  ON   1
+#define  OFF  0
+
+#ifndef NULL
+  #define NULL  0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef  unsigned char      boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef  unsigned int  uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef  unsigned short     uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef  unsigned char      uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef  signed int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef  signed char        int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef  unsigned char      byte;
+#define  _BYTE_DEFINED
+#endif
+
+typedef  unsigned short     word;
+
+typedef  unsigned long      dword;
+
+typedef  unsigned char      uint1;
+
+typedef  unsigned short     uint2;
+
+typedef  unsigned long      uint4;
+
+typedef  signed char        int1;
+
+typedef  signed short       int2;
+
+typedef  long int           int4;
+
+typedef  signed long        sint31;
+
+typedef  signed short       sint15;
+
+typedef  signed char        sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+  #ifndef _INT64_DEFINED
+
+    typedef long long     int64;
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+
+    typedef  unsigned long long  uint64;
+    #define _UINT64_DEFINED
+  #endif
+#else
+
+  #if (defined __GNUC__)
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/fig/v1/eht_sig_usr_mu_mimo_info.h b/hw/fig/v1/eht_sig_usr_mu_mimo_info.h
new file mode 100644
index 000000000000..c9e20d75e648
--- /dev/null
+++ b/hw/fig/v1/eht_sig_usr_mu_mimo_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      sta_coding                                              :  1,
+                      sta_spatial_config                                      :  6,
+                      reserved_0a                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0a                                             :  1,
+                      sta_spatial_config                                      :  6,
+                      sta_coding                                              :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET                                      0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB                                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB                                         10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK                                        0x000007ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET                                     0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB                                        11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB                                        14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK                                       0x00007800
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET                                  0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK                                    0x00008000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET                          0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB                             16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB                             21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK                            0x003f0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET                                 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK                                   0x00400000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                   0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                     0x00800000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET                           0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB                              24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB                              31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK                             0xff000000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB                         7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK                        0x000000ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB                         8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB                         15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK                        0x0000ff00
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB                         16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB                         23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK                        0x00ff0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB                         24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB                         31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK                        0xff000000
+
+#endif
diff --git a/hw/fig/v1/eht_sig_usr_ofdma_info.h b/hw/fig/v1/eht_sig_usr_ofdma_info.h
new file mode 100644
index 000000000000..f2520cccfde9
--- /dev/null
+++ b/hw/fig/v1/eht_sig_usr_ofdma_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  1,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET                                        0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB                                           0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB                                           10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK                                          0x000007ff
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET                                       0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB                                          11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB                                          14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK                                         0x00007800
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK                                     0x00008000
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET                                           0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB                                              16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB                                              19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK                                             0x000f0000
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET                                          0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK                                            0x00100000
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET                                    0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK                                      0x00200000
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK                                     0x00400000
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                     0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                       0x00800000
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET                             0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB                                24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB                                31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK                               0xff000000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB                           0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB                           7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK                          0x000000ff
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB                           8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB                           15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK                          0x0000ff00
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB                           16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB                           23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK                          0x00ff0000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB                           24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB                           31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK                          0xff000000
+
+#endif
diff --git a/hw/fig/v1/eht_sig_usr_su_info.h b/hw/fig/v1/eht_sig_usr_su_info.h
new file mode 100644
index 000000000000..208cb4de0539
--- /dev/null
+++ b/hw/fig/v1/eht_sig_usr_su_info.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  9,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  9,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+#endif
+};
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET                                           0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB                                              0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB                                              10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK                                             0x000007ff
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET                                          0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB                                             11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB                                             14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK                                            0x00007800
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK                                        0x00008000
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET                                              0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB                                                 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB                                                 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK                                                0x000f0000
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET                                             0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK                                               0x00100000
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET                                       0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK                                         0x00200000
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB                                         22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB                                         30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK                                        0x7fc00000
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v1/expected_response.h b/hw/fig/v1/expected_response.h
new file mode 100644
index 000000000000..b3ec83ceccf8
--- /dev/null
+++ b/hw/fig/v1/expected_response.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EXPECTED_RESPONSE_H_
+#define _EXPECTED_RESPONSE_H_
+
+#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
+
+#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
+
+struct expected_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t tx_ad2_47_32                                            : 16,
+                      expected_response_type                                  :  5,
+                      response_to_response                                    :  3,
+                      su_ba_user_number                                       :  1,
+                      response_info_part2_required                            :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      eht___reserved_g_0022_ndp_expected                                :  1,
+                      reserved_1                                              :  4;
+             uint32_t ndp_sta_partial_aid_2_8_0                               : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid1_8_0                                : 11;
+             uint32_t ast_index                                               : 16,
+                      capture_ack_ba_sounding                                 :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_320mhz                            :  1,
+                      reserved_3a                                             :  9;
+             uint32_t fcs                                                     :  9,
+                      expect_rx_with_blackout_details                         :  1,
+                      crc                                                     :  4,
+                      scrambler_seed                                          :  7,
+                      reserved_4b                                             : 11;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t reserved_1                                              :  4,
+                      eht___reserved_g_0022_ndp_expected                                :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      response_info_part2_required                            :  1,
+                      su_ba_user_number                                       :  1,
+                      response_to_response                                    :  3,
+                      expected_response_type                                  :  5,
+                      tx_ad2_47_32                                            : 16;
+             uint32_t ndp_sta_partial_aid1_8_0                                : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid_2_8_0                               : 11;
+             uint32_t reserved_3a                                             :  9,
+                      capture_sounding_1str_320mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_ack_ba_sounding                                 :  1,
+                      ast_index                                               : 16;
+             uint32_t reserved_4b                                             : 11,
+                      scrambler_seed                                          :  7,
+                      crc                                                     :  4,
+                      expect_rx_with_blackout_details                         :  1,
+                      fcs                                                     :  9;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET                                        0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB                                           0
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB                                           31
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK                                          0x00000000ffffffff
+
+#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET                                       0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB                                          32
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB                                          47
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK                                         0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET                             0x0000000000000000
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB                                48
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB                                52
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK                               0x001f000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET                               0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB                                  53
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB                                  55
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK                                 0x00e0000000000000
+
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET                                  0x0000000000000000
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK                                    0x0100000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET                       0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK                         0x0200000000000000
+
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET                         0x0000000000000000
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK                           0x0400000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_1_OFFSET                                         0x0000000000000000
+#define EXPECTED_RESPONSE_RESERVED_1_LSB                                            60
+#define EXPECTED_RESPONSE_RESERVED_1_MSB                                            63
+#define EXPECTED_RESPONSE_RESERVED_1_MASK                                           0xf000000000000000
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET                          0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB                             0
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB                             10
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK                            0x00000000000007ff
+
+#define EXPECTED_RESPONSE_RESERVED_2_OFFSET                                         0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_2_LSB                                            11
+#define EXPECTED_RESPONSE_RESERVED_2_MSB                                            20
+#define EXPECTED_RESPONSE_RESERVED_2_MASK                                           0x00000000001ff800
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET                           0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB                              21
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB                              31
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK                             0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_AST_INDEX_OFFSET                                          0x0000000000000008
+#define EXPECTED_RESPONSE_AST_INDEX_LSB                                             32
+#define EXPECTED_RESPONSE_AST_INDEX_MSB                                             47
+#define EXPECTED_RESPONSE_AST_INDEX_MASK                                            0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET                            0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK                              0x0001000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK                          0x0002000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK                          0x0004000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK                          0x0008000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK                         0x0010000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK                         0x0020000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK                         0x0040000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET                                        0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_3A_LSB                                           55
+#define EXPECTED_RESPONSE_RESERVED_3A_MSB                                           63
+#define EXPECTED_RESPONSE_RESERVED_3A_MASK                                          0xff80000000000000
+
+#define EXPECTED_RESPONSE_FCS_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_FCS_LSB                                                   0
+#define EXPECTED_RESPONSE_FCS_MSB                                                   8
+#define EXPECTED_RESPONSE_FCS_MASK                                                  0x00000000000001ff
+
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                    0x0000000000000010
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                      0x0000000000000200
+
+#define EXPECTED_RESPONSE_CRC_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_CRC_LSB                                                   10
+#define EXPECTED_RESPONSE_CRC_MSB                                                   13
+#define EXPECTED_RESPONSE_CRC_MASK                                                  0x0000000000003c00
+
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET                                     0x0000000000000010
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB                                        14
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB                                        20
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK                                       0x00000000001fc000
+
+#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET                                        0x0000000000000010
+#define EXPECTED_RESPONSE_RESERVED_4B_LSB                                           21
+#define EXPECTED_RESPONSE_RESERVED_4B_MSB                                           31
+#define EXPECTED_RESPONSE_RESERVED_4B_MASK                                          0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET                                      0x0000000000000010
+#define EXPECTED_RESPONSE_TLV64_PADDING_LSB                                         32
+#define EXPECTED_RESPONSE_TLV64_PADDING_MSB                                         63
+#define EXPECTED_RESPONSE_TLV64_PADDING_MASK                                        0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/he_sig_a_mu_dl_info.h b/hw/fig/v1/he_sig_a_mu_dl_info.h
new file mode 100644
index 000000000000..84571eb65d3b
--- /dev/null
+++ b/hw/fig/v1/he_sig_a_mu_dl_info.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t dl_ul_flag                                              :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dcm_of_sig_b                                            :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  3,
+                      num_sig_b_symbols                                       :  4,
+                      comp_mode_sig_b                                         :  1,
+                      cp_ltf_size                                             :  2,
+                      doppler_indication                                      :  1,
+                      reserved_0a                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  1,
+                      num_ltf_symbols                                         :  3,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0a                                             :  6,
+                      doppler_indication                                      :  1,
+                      cp_ltf_size                                             :  2,
+                      comp_mode_sig_b                                         :  1,
+                      num_sig_b_symbols                                       :  4,
+                      transmit_bw                                             :  3,
+                      spatial_reuse                                           :  4,
+                      bss_color_id                                            :  6,
+                      dcm_of_sig_b                                            :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dl_ul_flag                                              :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET                                       0x00000000
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK                                         0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB                                        1
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB                                        3
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK                                       0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK                                       0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB                                        5
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB                                        10
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK                                       0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB                                       11
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB                                       14
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK                                      0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB                                         15
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB                                         17
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK                                        0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET                                0x00000000
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB                                   18
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB                                   21
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK                                  0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET                                  0x00000000
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK                                    0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB                                         23
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB                                         24
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK                                        0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET                               0x00000000
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK                                 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB                                         31
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK                                        0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET                                  0x00000004
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB                                     8
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB                                     10
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK                                    0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                0x00000004
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK                                  0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_STBC_LSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MASK                                               0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB                           13
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB                           14
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK                          0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                   0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_DL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_DL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_DL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_DL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_DL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v1/he_sig_a_mu_ul_info.h b/hw/fig/v1/he_sig_a_mu_ul_info.h
new file mode 100644
index 000000000000..e2d0ad73a66c
--- /dev/null
+++ b/hw/fig/v1/he_sig_a_mu_ul_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           : 16,
+                      reserved_0a                                             :  1,
+                      transmit_bw                                             :  2,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  9,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      transmit_bw                                             :  2,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           : 16,
+                      bss_color_id                                            :  6,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      reserved_1a                                             :  9,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v1/he_sig_a_su_info.h b/hw/fig/v1/he_sig_a_su_info.h
new file mode 100644
index 000000000000..e4be3671016e
--- /dev/null
+++ b/hw/fig/v1/he_sig_a_su_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      beam_change                                             :  1,
+                      dl_ul_flag                                              :  1,
+                      transmit_mcs                                            :  4,
+                      dcm                                                     :  1,
+                      bss_color_id                                            :  6,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  2,
+                      cp_ltf_size                                             :  2,
+                      nsts                                                    :  3,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      coding                                                  :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      txbf                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      reserved_1a                                             :  1,
+                      doppler_indication                                      :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      nsts                                                    :  3,
+                      cp_ltf_size                                             :  2,
+                      transmit_bw                                             :  2,
+                      spatial_reuse                                           :  4,
+                      reserved_0a                                             :  1,
+                      bss_color_id                                            :  6,
+                      dcm                                                     :  1,
+                      transmit_mcs                                            :  4,
+                      dl_ul_flag                                              :  1,
+                      beam_change                                             :  1,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      doppler_indication                                      :  1,
+                      reserved_1a                                             :  1,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      txbf                                                    :  1,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      coding                                                  :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET                                   0x00000000
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK                                     0x00000001
+
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK                                           0x00000002
+
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET                                          0x00000000
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK                                            0x00000004
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB                                           3
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB                                           6
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK                                          0x00000078
+
+#define HE_SIG_A_SU_INFO_DCM_OFFSET                                                 0x00000000
+#define HE_SIG_A_SU_INFO_DCM_LSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MASK                                                   0x00000080
+
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB                                           8
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB                                           13
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK                                          0x00003f00
+
+#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET                                       0x00000000
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB                                          15
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB                                          18
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK                                         0x00078000
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB                                            19
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB                                            20
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK                                           0x00180000
+
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB                                            21
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB                                            22
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK                                           0x00600000
+
+#define HE_SIG_A_SU_INFO_NSTS_OFFSET                                                0x00000000
+#define HE_SIG_A_SU_INFO_NSTS_LSB                                                   23
+#define HE_SIG_A_SU_INFO_NSTS_MSB                                                   25
+#define HE_SIG_A_SU_INFO_NSTS_MASK                                                  0x03800000
+
+#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB                                            26
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB                                            31
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK                                           0xfc000000
+
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET                                       0x00000004
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB                                          0
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB                                          6
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK                                         0x0000007f
+
+#define HE_SIG_A_SU_INFO_CODING_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_CODING_LSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MASK                                                0x00000080
+
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                   0x00000004
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK                                     0x00000100
+
+#define HE_SIG_A_SU_INFO_STBC_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_STBC_LSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MASK                                                  0x00000200
+
+#define HE_SIG_A_SU_INFO_TXBF_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TXBF_LSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MASK                                                  0x00000400
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB                              11
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB                              12
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK                             0x00001800
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                    0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                      0x00002000
+
+#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET                                         0x00000004
+#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET                                  0x00000004
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK                                    0x00008000
+
+#define HE_SIG_A_SU_INFO_CRC_OFFSET                                                 0x00000004
+#define HE_SIG_A_SU_INFO_CRC_LSB                                                    16
+#define HE_SIG_A_SU_INFO_CRC_MSB                                                    19
+#define HE_SIG_A_SU_INFO_CRC_MASK                                                   0x000f0000
+
+#define HE_SIG_A_SU_INFO_TAIL_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TAIL_LSB                                                   20
+#define HE_SIG_A_SU_INFO_TAIL_MSB                                                   25
+#define HE_SIG_A_SU_INFO_TAIL_MASK                                                  0x03f00000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK                                   0x04000000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB                                    27
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB                                    29
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK                                   0x38000000
+
+#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_RX_NDP_LSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MASK                                                0x40000000
+
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                             0x80000000
+
+#endif
diff --git a/hw/fig/v1/he_sig_b1_mu_info.h b/hw/fig/v1/he_sig_b1_mu_info.h
new file mode 100644
index 000000000000..a248c3dc67b3
--- /dev/null
+++ b/hw/fig/v1/he_sig_b1_mu_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation                                           :  8,
+                      reserved_0                                              : 23,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 23,
+                      ru_allocation                                           :  8;
+#endif
+};
+
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
+
+#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
+#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
+
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/fig/v1/he_sig_b2_mu_info.h b/hw/fig/v1/he_sig_b2_mu_info.h
new file mode 100644
index 000000000000..83d6f3bc843f
--- /dev/null
+++ b/hw/fig/v1/he_sig_b2_mu_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
+
+struct he_sig_b2_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_spatial_config                                      :  4,
+                      sta_mcs                                                 :  4,
+                      reserved_set_to_1                                       :  1,
+                      sta_coding                                              :  1,
+                      reserved_0a                                             :  7,
+                      nsts                                                    :  3,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      nsts                                                    :  3,
+                      reserved_0a                                             :  7,
+                      sta_coding                                              :  1,
+                      reserved_set_to_1                                       :  1,
+                      sta_mcs                                                 :  4,
+                      sta_spatial_config                                      :  4,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
+#define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
+#define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
+#define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
+
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
+
+#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
+#define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
+#define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
+#define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
+
+#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
+#define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
+
+#define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
+#define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
+#define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
+#define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
+
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
+#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
+
+#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
+#define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
+#define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
+#define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
+
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
+
+#endif
diff --git a/hw/fig/v1/he_sig_b2_ofdma_info.h b/hw/fig/v1/he_sig_b2_ofdma_info.h
new file mode 100644
index 000000000000..6357d216eb3a
--- /dev/null
+++ b/hw/fig/v1/he_sig_b2_ofdma_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
+
+struct he_sig_b2_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      nsts                                                    :  3,
+                      txbf                                                    :  1,
+                      sta_mcs                                                 :  4,
+                      sta_dcm                                                 :  1,
+                      sta_coding                                              :  1,
+                      reserved_0                                              : 10,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 10,
+                      sta_coding                                              :  1,
+                      sta_dcm                                                 :  1,
+                      sta_mcs                                                 :  4,
+                      txbf                                                    :  1,
+                      nsts                                                    :  3,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET                                          0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB                                             0
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB                                             10
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK                                            0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB                                               11
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB                                               13
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK                                              0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK                                              0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB                                            18
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK                                           0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK                                           0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK                                        0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB                                         21
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB                                         30
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK                                        0x7fe00000
+
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET                                      0x00000004
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB                                         0
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB                                         7
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK                                        0x000000ff
+
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET                                         0x00000004
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB                                            8
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK                                           0x0000ff00
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET                                     0x00000004
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB                                        16
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB                                        31
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/fig/v1/ht_sig_info.h b/hw/fig/v1/ht_sig_info.h
new file mode 100644
index 000000000000..d6a4a719e6e2
--- /dev/null
+++ b/hw/fig/v1/ht_sig_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mcs                                                     :  7,
+                      cbw                                                     :  1,
+                      length                                                  : 16,
+                      reserved_0                                              :  8;
+             uint32_t smoothing                                               :  1,
+                      not_sounding                                            :  1,
+                      ht_reserved                                             :  1,
+                      aggregation                                             :  1,
+                      stbc                                                    :  2,
+                      fec_coding                                              :  1,
+                      short_gi                                                :  1,
+                      num_ext_sp_str                                          :  2,
+                      crc                                                     :  8,
+                      signal_tail                                             :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      length                                                  : 16,
+                      cbw                                                     :  1,
+                      mcs                                                     :  7;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      signal_tail                                             :  6,
+                      crc                                                     :  8,
+                      num_ext_sp_str                                          :  2,
+                      short_gi                                                :  1,
+                      fec_coding                                              :  1,
+                      stbc                                                    :  2,
+                      aggregation                                             :  1,
+                      ht_reserved                                             :  1,
+                      not_sounding                                            :  1,
+                      smoothing                                               :  1;
+#endif
+};
+
+#define HT_SIG_INFO_MCS_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_MCS_LSB                                                         0
+#define HT_SIG_INFO_MCS_MSB                                                         6
+#define HT_SIG_INFO_MCS_MASK                                                        0x0000007f
+
+#define HT_SIG_INFO_CBW_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_CBW_LSB                                                         7
+#define HT_SIG_INFO_CBW_MSB                                                         7
+#define HT_SIG_INFO_CBW_MASK                                                        0x00000080
+
+#define HT_SIG_INFO_LENGTH_OFFSET                                                   0x00000000
+#define HT_SIG_INFO_LENGTH_LSB                                                      8
+#define HT_SIG_INFO_LENGTH_MSB                                                      23
+#define HT_SIG_INFO_LENGTH_MASK                                                     0x00ffff00
+
+#define HT_SIG_INFO_RESERVED_0_OFFSET                                               0x00000000
+#define HT_SIG_INFO_RESERVED_0_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_0_MSB                                                  31
+#define HT_SIG_INFO_RESERVED_0_MASK                                                 0xff000000
+
+#define HT_SIG_INFO_SMOOTHING_OFFSET                                                0x00000004
+#define HT_SIG_INFO_SMOOTHING_LSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MASK                                                  0x00000001
+
+#define HT_SIG_INFO_NOT_SOUNDING_OFFSET                                             0x00000004
+#define HT_SIG_INFO_NOT_SOUNDING_LSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MASK                                               0x00000002
+
+#define HT_SIG_INFO_HT_RESERVED_OFFSET                                              0x00000004
+#define HT_SIG_INFO_HT_RESERVED_LSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MASK                                                0x00000004
+
+#define HT_SIG_INFO_AGGREGATION_OFFSET                                              0x00000004
+#define HT_SIG_INFO_AGGREGATION_LSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MASK                                                0x00000008
+
+#define HT_SIG_INFO_STBC_OFFSET                                                     0x00000004
+#define HT_SIG_INFO_STBC_LSB                                                        4
+#define HT_SIG_INFO_STBC_MSB                                                        5
+#define HT_SIG_INFO_STBC_MASK                                                       0x00000030
+
+#define HT_SIG_INFO_FEC_CODING_OFFSET                                               0x00000004
+#define HT_SIG_INFO_FEC_CODING_LSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MASK                                                 0x00000040
+
+#define HT_SIG_INFO_SHORT_GI_OFFSET                                                 0x00000004
+#define HT_SIG_INFO_SHORT_GI_LSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MASK                                                   0x00000080
+
+#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET                                           0x00000004
+#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB                                              8
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB                                              9
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK                                             0x00000300
+
+#define HT_SIG_INFO_CRC_OFFSET                                                      0x00000004
+#define HT_SIG_INFO_CRC_LSB                                                         10
+#define HT_SIG_INFO_CRC_MSB                                                         17
+#define HT_SIG_INFO_CRC_MASK                                                        0x0003fc00
+
+#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET                                              0x00000004
+#define HT_SIG_INFO_SIGNAL_TAIL_LSB                                                 18
+#define HT_SIG_INFO_SIGNAL_TAIL_MSB                                                 23
+#define HT_SIG_INFO_SIGNAL_TAIL_MASK                                                0x00fc0000
+
+#define HT_SIG_INFO_RESERVED_1_OFFSET                                               0x00000004
+#define HT_SIG_INFO_RESERVED_1_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_1_MSB                                                  30
+#define HT_SIG_INFO_RESERVED_1_MASK                                                 0x7f000000
+
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                                0x00000004
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                  0x80000000
+
+#endif
diff --git a/hw/fig/v1/l_sig_a_info.h b/hw/fig/v1/l_sig_a_info.h
new file mode 100644
index 000000000000..6da0725dfee7
--- /dev/null
+++ b/hw/fig/v1/l_sig_a_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      lsig_reserved                                           :  1,
+                      length                                                  : 12,
+                      parity                                                  :  1,
+                      tail                                                    :  6,
+                      pkt_type                                                :  4,
+                      captured_implicit_sounding                              :  1,
+                      reserved                                                :  2,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                :  2,
+                      captured_implicit_sounding                              :  1,
+                      pkt_type                                                :  4,
+                      tail                                                    :  6,
+                      parity                                                  :  1,
+                      length                                                  : 12,
+                      lsig_reserved                                           :  1,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_A_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_RATE_LSB                                                       0
+#define L_SIG_A_INFO_RATE_MSB                                                       3
+#define L_SIG_A_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET                                           0x00000000
+#define L_SIG_A_INFO_LSIG_RESERVED_LSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MASK                                             0x00000010
+
+#define L_SIG_A_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_LENGTH_LSB                                                     5
+#define L_SIG_A_INFO_LENGTH_MSB                                                     16
+#define L_SIG_A_INFO_LENGTH_MASK                                                    0x0001ffe0
+
+#define L_SIG_A_INFO_PARITY_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_PARITY_LSB                                                     17
+#define L_SIG_A_INFO_PARITY_MSB                                                     17
+#define L_SIG_A_INFO_PARITY_MASK                                                    0x00020000
+
+#define L_SIG_A_INFO_TAIL_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_TAIL_LSB                                                       18
+#define L_SIG_A_INFO_TAIL_MSB                                                       23
+#define L_SIG_A_INFO_TAIL_MASK                                                      0x00fc0000
+
+#define L_SIG_A_INFO_PKT_TYPE_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_PKT_TYPE_LSB                                                   24
+#define L_SIG_A_INFO_PKT_TYPE_MSB                                                   27
+#define L_SIG_A_INFO_PKT_TYPE_MASK                                                  0x0f000000
+
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET                              0x00000000
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK                                0x10000000
+
+#define L_SIG_A_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_RESERVED_LSB                                                   29
+#define L_SIG_A_INFO_RESERVED_MSB                                                   30
+#define L_SIG_A_INFO_RESERVED_MASK                                                  0x60000000
+
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/fig/v1/l_sig_b_info.h b/hw/fig/v1/l_sig_b_info.h
new file mode 100644
index 000000000000..f2052702e2de
--- /dev/null
+++ b/hw/fig/v1/l_sig_b_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      length                                                  : 12,
+                      reserved                                                : 15,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                : 15,
+                      length                                                  : 12,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_B_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_B_INFO_RATE_LSB                                                       0
+#define L_SIG_B_INFO_RATE_MSB                                                       3
+#define L_SIG_B_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_B_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_B_INFO_LENGTH_LSB                                                     4
+#define L_SIG_B_INFO_LENGTH_MSB                                                     15
+#define L_SIG_B_INFO_LENGTH_MASK                                                    0x0000fff0
+
+#define L_SIG_B_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_B_INFO_RESERVED_LSB                                                   16
+#define L_SIG_B_INFO_RESERVED_MSB                                                   30
+#define L_SIG_B_INFO_RESERVED_MASK                                                  0x7fff0000
+
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/fig/v1/macrx_abort_request_info.h b/hw/fig/v1/macrx_abort_request_info.h
new file mode 100644
index 000000000000..038f4038fa59
--- /dev/null
+++ b/hw/fig/v1/macrx_abort_request_info.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t macrx_abort_reason                                      :  8,
+                      reserved_0                                              :  8;
+#else
+             uint16_t reserved_0                                              :  8,
+                      macrx_abort_reason                                      :  8;
+#endif
+};
+
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET                          0x00000000
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB                             0
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB                             7
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK                            0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     8
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x0000ff00
+
+#endif
diff --git a/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h b/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
new file mode 100644
index 000000000000..f29ca356a223
--- /dev/null
+++ b/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
+#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
+
+#include "eht_sig_usr_mu_mimo_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
+
+struct mactx_eht_sig_usr_mu_mimo {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#else
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_eht_sig_usr_ofdma.h b/hw/fig/v1/mactx_eht_sig_usr_ofdma.h
new file mode 100644
index 000000000000..24bf6691978d
--- /dev/null
+++ b/hw/fig/v1/mactx_eht_sig_usr_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
+#define _MACTX_EHT_SIG_USR_OFDMA_H_
+
+#include "eht_sig_usr_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
+
+struct mactx_eht_sig_usr_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#else
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET  0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB     0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB     10
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK    0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB    11
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB    14
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK   0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET     0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB        16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB        19
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK       0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK      0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_eht_sig_usr_su.h b/hw/fig/v1/mactx_eht_sig_usr_su.h
new file mode 100644
index 000000000000..1fb82723c1ff
--- /dev/null
+++ b/hw/fig/v1/mactx_eht_sig_usr_su.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_SU_H_
+#define _MACTX_EHT_SIG_USR_SU_H_
+
+#include "eht_sig_usr_su_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
+
+struct mactx_eht_sig_usr_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET        0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB           0
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB           10
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK          0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET       0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB          11
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB          14
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK         0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK     0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET           0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB              16
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB              19
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK             0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET          0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK            0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK      0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB      22
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB      30
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK     0x000000007fc00000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB                                      32
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB                                      63
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_a_mu_dl.h b/hw/fig/v1/mactx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..438f3af6f9e7
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_DL_H_
+#define _MACTX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
+
+struct mactx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_a_mu_ul.h b/hw/fig/v1/mactx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..96d2b912665a
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_UL_H_
+#define _MACTX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
+
+struct mactx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_a_su.h b/hw/fig/v1/mactx_he_sig_a_su.h
new file mode 100644
index 000000000000..e51241d26559
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_SU_H_
+#define _MACTX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
+
+struct mactx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_b1_mu.h b/hw/fig/v1/mactx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..700528af2048
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B1_MU_H_
+#define _MACTX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
+
+struct mactx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_b2_mu.h b/hw/fig/v1/mactx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..ccc1c593fed6
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_MU_H_
+#define _MACTX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
+
+struct mactx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_he_sig_b2_ofdma.h b/hw/fig/v1/mactx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..afc3c4b22841
--- /dev/null
+++ b/hw/fig/v1/mactx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
+#define _MACTX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
+
+struct mactx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_ht_sig.h b/hw/fig/v1/mactx_ht_sig.h
new file mode 100644
index 000000000000..ec28824c590f
--- /dev/null
+++ b/hw/fig/v1/mactx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HT_SIG_H_
+#define _MACTX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_MACTX_HT_SIG 2
+
+#define NUM_OF_QWORDS_MACTX_HT_SIG 1
+
+struct mactx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#endif
+};
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_l_sig_a.h b/hw/fig/v1/mactx_l_sig_a.h
new file mode 100644
index 000000000000..061e46e28a2c
--- /dev/null
+++ b/hw/fig/v1/mactx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_A_H_
+#define _MACTX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
+
+struct mactx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_l_sig_b.h b/hw/fig/v1/mactx_l_sig_b.h
new file mode 100644
index 000000000000..6d533acef675
--- /dev/null
+++ b/hw/fig/v1/mactx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_B_H_
+#define _MACTX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
+
+struct mactx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_phy_desc.h b/hw/fig/v1/mactx_phy_desc.h
new file mode 100644
index 000000000000..ee4ccdf65c28
--- /dev/null
+++ b/hw/fig/v1/mactx_phy_desc.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_PHY_DESC_H_
+#define _MACTX_PHY_DESC_H_
+
+#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
+
+#define NUM_OF_QWORDS_MACTX_PHY_DESC 2
+
+struct mactx_phy_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             : 16,
+                      bf_type                                                 :  2,
+                      wait_sifs                                               :  2,
+                      dot11b_preamble_type                                    :  1,
+                      pkt_type                                                :  4,
+                      su_or_mu                                                :  2,
+                      mu_type                                                 :  1,
+                      bandwidth                                               :  3,
+                      channel_capture                                         :  1;
+             uint32_t mcs                                                     :  5,
+                      global_ofdma_mimo_enable                                :  1,
+                      stbc                                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8,
+                      measure_power                                           :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      back_to_back_transmission_expected                      :  1,
+                      heavy_clip_nss                                          :  3,
+                      txbf_per_packet_no_csd_no_walsh                         :  1;
+             uint32_t ndp                                                     :  3,
+                      ul_flag                                                 :  1,
+                      triggered                                               :  1,
+                      ap_pkt_bw                                               :  3,
+                      ru_position_start                                       :  8,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      tlv_source                                              :  1,
+                      reserved_2a                                             :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_2b                                             :  2,
+                      clpc_enable                                             :  1,
+                      mu_ndp                                                  :  1,
+                      response_expected                                       :  1;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_chain_mask_valid                                     :  1,
+                      ant_sel_valid                                           :  1,
+                      ant_sel                                                 :  1,
+                      cp_setting                                              :  2,
+                      he_ppdu_subtype                                         :  2,
+                      active_channel                                          :  3,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      ltf_size                                                :  2,
+                      ru_size_updated_v2                                      :  4,
+                      reserved_3c                                             :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+#else
+             uint32_t channel_capture                                         :  1,
+                      bandwidth                                               :  3,
+                      mu_type                                                 :  1,
+                      su_or_mu                                                :  2,
+                      pkt_type                                                :  4,
+                      dot11b_preamble_type                                    :  1,
+                      wait_sifs                                               :  2,
+                      bf_type                                                 :  2,
+                      reserved_0a                                             : 16;
+             uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
+                      heavy_clip_nss                                          :  3,
+                      back_to_back_transmission_expected                      :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      measure_power                                           :  1,
+                      tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      dot11ax_su_extended                                     :  1,
+                      stbc                                                    :  1,
+                      global_ofdma_mimo_enable                                :  1,
+                      mcs                                                     :  5;
+             uint32_t response_expected                                       :  1,
+                      mu_ndp                                                  :  1,
+                      clpc_enable                                             :  1,
+                      reserved_2b                                             :  2,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  1,
+                      tlv_source                                              :  1,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      ru_position_start                                       :  8,
+                      ap_pkt_bw                                               :  3,
+                      triggered                                               :  1,
+                      ul_flag                                                 :  1,
+                      ndp                                                     :  3;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_3c                                             :  1,
+                      ru_size_updated_v2                                      :  4,
+                      ltf_size                                                :  2,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      active_channel                                          :  3,
+                      he_ppdu_subtype                                         :  2,
+                      cp_setting                                              :  2,
+                      ant_sel                                                 :  1,
+                      ant_sel_valid                                           :  1,
+                      rx_chain_mask_valid                                     :  1,
+                      rx_chain_mask                                           :  8;
+#endif
+};
+
+#define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
+#define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
+#define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x000000000000ffff
+
+#define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
+#define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
+#define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x0000000000030000
+
+#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
+#define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
+#define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x00000000000c0000
+
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x0000000000000000
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x0000000000100000
+
+#define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
+#define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
+#define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x0000000001e00000
+
+#define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
+#define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
+#define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x0000000006000000
+
+#define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x0000000008000000
+
+#define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
+#define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
+#define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x0000000070000000
+
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x0000000080000000
+
+#define MACTX_PHY_DESC_MCS_OFFSET                                                   0x0000000000000000
+#define MACTX_PHY_DESC_MCS_LSB                                                      32
+#define MACTX_PHY_DESC_MCS_MSB                                                      36
+#define MACTX_PHY_DESC_MCS_MASK                                                     0x0000001f00000000
+
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x0000000000000000
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x0000002000000000
+
+#define MACTX_PHY_DESC_STBC_OFFSET                                                  0x0000000000000000
+#define MACTX_PHY_DESC_STBC_LSB                                                     38
+#define MACTX_PHY_DESC_STBC_MSB                                                     38
+#define MACTX_PHY_DESC_STBC_MASK                                                    0x0000004000000000
+
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x0000008000000000
+
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x0000010000000000
+
+#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            41
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            48
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe0000000000
+
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          49
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          56
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe000000000000
+
+#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x0200000000000000
+
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x0000000000000000
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x0400000000000000
+
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x0000000000000000
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x0800000000000000
+
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x0000000000000000
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           60
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           62
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x7000000000000000
+
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x0000000000000000
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x8000000000000000
+
+#define MACTX_PHY_DESC_NDP_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NDP_LSB                                                      0
+#define MACTX_PHY_DESC_NDP_MSB                                                      2
+#define MACTX_PHY_DESC_NDP_MASK                                                     0x0000000000000007
+
+#define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_UL_FLAG_LSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x0000000000000008
+
+#define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_TRIGGERED_LSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x0000000000000010
+
+#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                5
+#define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                7
+#define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x00000000000000e0
+
+#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        8
+#define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        15
+#define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x000000000000ff00
+
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x0000000000000008
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              16
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              18
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x0000000000070000
+
+#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x0000000000080000
+
+#define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2A_LSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x0000000000100000
+
+#define MACTX_PHY_DESC_NSS_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NSS_LSB                                                      21
+#define MACTX_PHY_DESC_NSS_MSB                                                      23
+#define MACTX_PHY_DESC_NSS_MASK                                                     0x0000000000e00000
+
+#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
+#define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
+#define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x0000000007000000
+
+#define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
+#define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
+#define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x0000000018000000
+
+#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x0000000020000000
+
+#define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x0000000000000008
+#define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x0000000040000000
+
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x0000000080000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            32
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            39
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff00000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x0000010000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x0000020000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_LSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x0000040000000000
+
+#define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_CP_SETTING_LSB                                               43
+#define MACTX_PHY_DESC_CP_SETTING_MSB                                               44
+#define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x0000180000000000
+
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000000000008
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          45
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          46
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x0000600000000000
+
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000000000008
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           47
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           49
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x0003800000000000
+
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000000000008
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x0004000000000000
+
+#define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000000000008
+#define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 51
+#define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 52
+#define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x0018000000000000
+
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000000000008
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       53
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       56
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e0000000000000
+
+#define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_3C_LSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x0200000000000000
+
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000000000008
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          58
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          63
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc00000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_u_sig_eht_su_mu.h b/hw/fig/v1/mactx_u_sig_eht_su_mu.h
new file mode 100644
index 000000000000..f46583e4c7ee
--- /dev/null
+++ b/hw/fig/v1/mactx_u_sig_eht_su_mu.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
+#define _MACTX_U_SIG_EHT_SU_MU_H_
+
+#include "u_sig_eht_su_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
+
+struct mactx_u_sig_eht_su_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#else
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB    0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK   0x0000000000000007
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB    3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB    5
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK   0x0000000000000038
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET  0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK    0x0000000000000040
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB   7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB   12
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK  0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB  13
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB  19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB   20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB   24
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK  0x0000000001f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK   0x0000000002000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB    26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB    31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK   0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK   0x0000000400000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK   0x0000010000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET         0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB            48
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB            51
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK           0x000f000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB           52
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB           57
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK          0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB    59
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB    61
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK   0x3800000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK        0x4000000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_u_sig_eht_tb.h b/hw/fig/v1/mactx_u_sig_eht_tb.h
new file mode 100644
index 000000000000..5e57312a9da2
--- /dev/null
+++ b/hw/fig/v1/mactx_u_sig_eht_tb.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_TB_H_
+#define _MACTX_U_SIG_EHT_TB_H_
+
+#include "u_sig_eht_tb_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
+
+struct mactx_u_sig_eht_tb {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#else
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB          0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK         0x0000000000000007
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB          3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB          5
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK         0x0000000000000038
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK          0x0000000000000040
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB         7
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB         12
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK        0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB        13
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB        19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK       0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB         20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB         25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK        0x0000000003f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB          26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB          31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK         0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK         0x0000000400000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB        35
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB        42
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK       0x000007f800000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB         43
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB         47
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK        0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET               0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB                  48
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB                  51
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK                 0x000f000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET              0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB                 52
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB                 57
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK                0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB          58
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB          62
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK         0x7c00000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_user_desc_common.h b/hw/fig/v1/mactx_user_desc_common.h
new file mode 100644
index 000000000000..04124271bbc9
--- /dev/null
+++ b/hw/fig/v1/mactx_user_desc_common.h
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_COMMON_H_
+#define _MACTX_USER_DESC_COMMON_H_
+
+#include "unallocated_ru_160_info.h"
+#include "ru_allocation_160_info.h"
+#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8
+
+struct mactx_user_desc_common {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      reserved_0b                                             :  5,
+                      ltf_size                                                :  2,
+                      reserved_0c                                             :  3,
+                      he_stf_long                                             :  1,
+                      reserved_0d                                             :  7,
+                      num_users_he_sigb_band0                                 :  8;
+             uint32_t num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  5,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1b                                             : 16;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      reserved                                                :  2,
+                      he_sigb_dcm                                             :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_compression                                     :  1,
+                      reserved_2c                                             : 15;
+             uint32_t he_sigb_0_mcs                                           :  3,
+                      reserved_3a                                             : 13,
+                      num_he_sigb_sym                                         :  5,
+                      center_ru_0                                             :  1,
+                      center_ru_1                                             :  1,
+                      reserved_3b                                             :  1,
+                      ftm_en                                                  :  1,
+                      pe_nss                                                  :  3,
+                      pe_ltf_size                                             :  2,
+                      pe_content                                              :  1,
+                      pe_chain_csd_en                                         :  1;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t num_data_symbols                                        : 16,
+                      ndp_ru_tone_set_index                                   :  7,
+                      ndp_feedback_status                                     :  1,
+                      doppler_indication                                      :  1,
+                      reserved_14a                                            :  7;
+             uint32_t spatial_reuse                                           : 16,
+                      distributed_ru                                          :  1,
+                      dru_spreading_bw                                        :  2,
+                      reserved_15a                                            : 13;
+#else
+             uint32_t num_users_he_sigb_band0                                 :  8,
+                      reserved_0d                                             :  7,
+                      he_stf_long                                             :  1,
+                      reserved_0c                                             :  3,
+                      ltf_size                                                :  2,
+                      reserved_0b                                             :  5,
+                      num_users                                               :  6;
+             uint32_t reserved_1b                                             : 16,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1a                                             :  5,
+                      num_ltf_symbols                                         :  3;
+             uint32_t reserved_2c                                             : 15,
+                      he_sigb_compression                                     :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_dcm                                             :  1,
+                      reserved                                                :  2,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t pe_chain_csd_en                                         :  1,
+                      pe_content                                              :  1,
+                      pe_ltf_size                                             :  2,
+                      pe_nss                                                  :  3,
+                      ftm_en                                                  :  1,
+                      reserved_3b                                             :  1,
+                      center_ru_1                                             :  1,
+                      center_ru_0                                             :  1,
+                      num_he_sigb_sym                                         :  5,
+                      reserved_3a                                             : 13,
+                      he_sigb_0_mcs                                           :  3;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t reserved_14a                                            :  7,
+                      doppler_indication                                      :  1,
+                      ndp_feedback_status                                     :  1,
+                      ndp_ru_tone_set_index                                   :  7,
+                      num_data_symbols                                        : 16;
+             uint32_t reserved_15a                                            : 13,
+                      dru_spreading_bw                                        :  2,
+                      distributed_ru                                          :  1,
+                      spatial_reuse                                           : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB                                        0
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB                                        5
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK                                       0x000000000000003f
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB                                      6
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB                                      10
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK                                     0x00000000000007c0
+
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET                                      0x0000000000000000
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB                                         11
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB                                         12
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK                                        0x0000000000001800
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB                                      13
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK                                     0x000000000000e000
+
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK                                     0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK                                     0x0000000000fe0000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB                          24
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB                          31
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK                         0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB                                  32
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB                                  34
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK                                 0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB                                      39
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK                                     0x000000f800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB                          40
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB                          47
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK                         0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB                                      48
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB                                      63
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK                                     0xffff000000000000
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET                     0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB                        0
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB                        1
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK                       0x0000000000000003
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                0x0000000000000004
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET                              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB                                 3
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB                                 5
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK                                0x0000000000000038
+
+#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET                                      0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_LSB                                         6
+#define MACTX_USER_DESC_COMMON_RESERVED_MSB                                         7
+#define MACTX_USER_DESC_COMMON_RESERVED_MASK                                        0x00000000000000c0
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK                                     0x0000000000000100
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB                                      9
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK                                     0x000000000000fe00
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK                             0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB                                      31
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK                                     0x00000000fffe0000
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB                                    32
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB                                    34
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK                                   0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB                                      47
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK                                     0x0000fff800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB                                  48
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB                                  52
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK                                 0x001f000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK                                     0x0020000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK                                     0x0040000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK                                     0x0080000000000000
+
+#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_FTM_EN_LSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MASK                                          0x0100000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_NSS_LSB                                           57
+#define MACTX_USER_DESC_COMMON_PE_NSS_MSB                                           59
+#define MACTX_USER_DESC_COMMON_PE_NSS_MASK                                          0x0e00000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB                                      60
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB                                      61
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK                                     0x3000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK                                      0x4000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK                                 0x8000000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB      0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB      7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK     0x00000000000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB      8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB      15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK     0x000000000000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB      16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB      23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK     0x0000000000ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB      24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB      31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK     0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB      32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB      39
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK     0x000000ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB      40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB      47
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK     0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB      48
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB      55
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK     0x00ff000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB      56
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB      63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK     0xff00000000000000
+
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB                                 0
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB                                 15
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK                                0x000000000000ffff
+
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET                         0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB                            16
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB                            22
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK                           0x00000000007f0000
+
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET                           0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK                             0x0000000000800000
+
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET                            0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK                              0x0000000001000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB                                     25
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB                                     31
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK                                    0x00000000fe000000
+
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET                                 0x0000000000000038
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB                                    32
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB                                    47
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK                                   0x0000ffff00000000
+
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET                                0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK                                  0x0001000000000000
+
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB                                 49
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB                                 50
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK                                0x0006000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB                                     51
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB                                     63
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK                                    0xfff8000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_user_desc_per_user.h b/hw/fig/v1/mactx_user_desc_per_user.h
new file mode 100644
index 000000000000..a68b50d9d639
--- /dev/null
+++ b/hw/fig/v1/mactx_user_desc_per_user.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_PER_USER_H_
+#define _MACTX_USER_DESC_PER_USER_H_
+
+#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3
+
+struct mactx_user_desc_per_user {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t psdu_length                                             : 24,
+                      reserved_0a                                             :  8;
+             uint32_t ru_start_index                                          :  8,
+                      ru_size                                                 :  4,
+                      reserved_1b                                             :  4,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_1c                                             :  1,
+                      mcs                                                     :  5,
+                      dcm                                                     :  1,
+                      reserved_1d                                             :  2;
+             uint32_t fec_type                                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      user_bf_type                                            :  2,
+                      a_factor_ldpc2x                                         :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      cw_len_2x                                               :  2,
+                      reserved_2b                                             :  1,
+                      drop_user_cbf                                           :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      cw_len_1x                                               :  2,
+                      ldpc1x_used                                             :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_2x_codeword                                        :  1,
+                      reserved_2d                                             :  5;
+             uint32_t sw_peer_id                                              : 16,
+                      per_user_subband_mask                                   : 16;
+             uint32_t ldpc_num_avbits                                         : 27,
+                      reserved_4a                                             :  5;
+             uint32_t num_cw_1x                                               : 16,
+                      num_cw_2x                                               : 16;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      psdu_length                                             : 24;
+             uint32_t reserved_1d                                             :  2,
+                      dcm                                                     :  1,
+                      mcs                                                     :  5,
+                      reserved_1c                                             :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      reserved_1b                                             :  4,
+                      ru_size                                                 :  4,
+                      ru_start_index                                          :  8;
+             uint32_t reserved_2d                                             :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc1x_used                                             :  1,
+                      cw_len_1x                                               :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      drop_user_cbf                                           :  1,
+                      reserved_2b                                             :  1,
+                      cw_len_2x                                               :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      a_factor_ldpc2x                                         :  2,
+                      user_bf_type                                            :  2,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      fec_type                                                :  1;
+             uint32_t per_user_subband_mask                                   : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_4a                                             :  5,
+                      ldpc_num_avbits                                         : 27;
+             uint32_t num_cw_2x                                               : 16,
+                      num_cw_1x                                               : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB                                    0
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK                                   0x0000000000ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB                                    24
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK                                   0x00000000ff000000
+
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET                              0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB                                 32
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB                                 39
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK                                0x000000ff00000000
+
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB                                        40
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB                                        43
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK                                       0x00000f0000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB                                    44
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB                                    47
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK                                   0x0000f00000000000
+
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK                         0x0001000000000000
+
+#define MACTX_USER_DESC_PER_USER_NSS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_NSS_LSB                                            49
+#define MACTX_USER_DESC_PER_USER_NSS_MSB                                            51
+#define MACTX_USER_DESC_PER_USER_NSS_MASK                                           0x000e000000000000
+
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB                                  52
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB                                  54
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK                                 0x0070000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK                                   0x0080000000000000
+
+#define MACTX_USER_DESC_PER_USER_MCS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_MCS_LSB                                            56
+#define MACTX_USER_DESC_PER_USER_MCS_MSB                                            60
+#define MACTX_USER_DESC_PER_USER_MCS_MASK                                           0x1f00000000000000
+
+#define MACTX_USER_DESC_PER_USER_DCM_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_DCM_LSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MASK                                           0x2000000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB                                    62
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB                                    63
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK                                   0xc000000000000000
+
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK                                      0x0000000000000001
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK                                   0x0000000000000002
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB                                      2
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB                                      3
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK                                     0x000000000000000c
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB                                      4
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB                                      5
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK                                     0x0000000000000030
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB                                      6
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB                                      7
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK                                     0x00000000000000c0
+
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET                                0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB                                   8
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB                                   9
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK                                  0x0000000000000300
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB                                10
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB                                11
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK                               0x0000000000000c00
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK                              0x0000000000001000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB                                      13
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB                                      14
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK                                     0x0000000000006000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK                                   0x0000000000008000
+
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK                                 0x0000000000010000
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB                                17
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB                                18
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK                               0x0000000000060000
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK                              0x0000000000080000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB                                      20
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB                                      21
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK                                     0x0000000000300000
+
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK                                   0x0000000000400000
+
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK                                   0x0000000000800000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK                             0x0000000001000000
+
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET                          0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK                            0x0000000002000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK                              0x0000000004000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET                                  0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB                                     32
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB                                     47
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK                                    0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET                       0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB                          48
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB                          63
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK                         0xffff000000000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET                             0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB                                0
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB                                26
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK                               0x0000000007ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB                                      32
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB                                      47
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK                                     0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB                                      48
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB                                      63
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_a.h b/hw/fig/v1/mactx_vht_sig_a.h
new file mode 100644
index 000000000000..6dec145785d6
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_A_H_
+#define _MACTX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
+
+struct mactx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu160.h b/hw/fig/v1/mactx_vht_sig_b_mu160.h
new file mode 100644
index 000000000000..b66278da930b
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_mu160.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU160_H_
+#define _MACTX_VHT_SIG_B_MU160_H_
+
+#include "vht_sig_b_mu160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
+
+struct mactx_vht_sig_b_mu160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#else
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB         18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK        0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB            19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB            22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK           0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK    0xe000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu20.h b/hw/fig/v1/mactx_vht_sig_b_mu20.h
new file mode 100644
index 000000000000..95feca30eaa3
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_mu20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU20_H_
+#define _MACTX_VHT_SIG_B_MU20_H_
+
+#include "vht_sig_b_mu20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
+
+struct mactx_vht_sig_b_mu20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB           15
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK          0x000000000000ffff
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB              16
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB              19
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK             0x00000000000f0000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB   26
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB   28
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK  0x000000001c000000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu40.h b/hw/fig/v1/mactx_vht_sig_b_mu40.h
new file mode 100644
index 000000000000..c770db089203
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_mu40.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU40_H_
+#define _MACTX_VHT_SIG_B_MU40_H_
+
+#include "vht_sig_b_mu40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
+
+struct mactx_vht_sig_b_mu40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#else
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB              17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB              20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK             0x00000000001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB       27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB       28
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK      0x0000000018000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB      48
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0001ffff00000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB         49
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB         52
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK        0x001e000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB       59
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK      0xf800000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu80.h b/hw/fig/v1/mactx_vht_sig_b_mu80.h
new file mode 100644
index 000000000000..9e39d240b618
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_mu80.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU80_H_
+#define _MACTX_VHT_SIG_B_MU80_H_
+
+#include "vht_sig_b_mu80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
+
+struct mactx_vht_sig_b_mu80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#else
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB              19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB              22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK             0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK      0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK      0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK      0xe000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_su160.h b/hw/fig/v1/mactx_vht_sig_b_su160.h
new file mode 100644
index 000000000000..01bc54e5ab89
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_su160.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU160_H_
+#define _MACTX_VHT_SIG_B_SU160_H_
+
+#include "vht_sig_b_su160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
+
+struct mactx_vht_sig_b_su160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#else
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB         20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK        0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB  21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB  22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK        0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_su20.h b/hw/fig/v1/mactx_vht_sig_b_su20.h
new file mode 100644
index 000000000000..c297cc0785e3
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_su20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU20_H_
+#define _MACTX_VHT_SIG_B_SU20_H_
+
+#include "vht_sig_b_su20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
+
+struct mactx_vht_sig_b_su20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB    17
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB    19
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK   0x00000000000e0000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB         26
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK        0x000000007c000000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_su40.h b/hw/fig/v1/mactx_vht_sig_b_su40.h
new file mode 100644
index 000000000000..002d72c430ca
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_su40.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU40_H_
+#define _MACTX_VHT_SIG_B_SU40_H_
+
+#include "vht_sig_b_su40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
+
+struct mactx_vht_sig_b_su40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#else
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB    19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB    20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB         27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK        0x0000000078000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB      50
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB    59
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB    62
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK   0x7800000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK     0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mactx_vht_sig_b_su80.h b/hw/fig/v1/mactx_vht_sig_b_su80.h
new file mode 100644
index 000000000000..b15646f03f4a
--- /dev/null
+++ b/hw/fig/v1/mactx_vht_sig_b_su80.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU80_H_
+#define _MACTX_VHT_SIG_B_SU80_H_
+
+#include "vht_sig_b_su80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
+
+struct mactx_vht_sig_b_su80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#else
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB           20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK          0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB    21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB    22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK   0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK   0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK   0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mlo_sta_id_details.h b/hw/fig/v1/mlo_sta_id_details.h
new file mode 100644
index 000000000000..952056890206
--- /dev/null
+++ b/hw/fig/v1/mlo_sta_id_details.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MLO_STA_ID_DETAILS_H_
+#define _MLO_STA_ID_DETAILS_H_
+
+#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
+
+struct mlo_sta_id_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t nstr_mlo_sta_id                                         : 10,
+                      block_self_ml_sync                                      :  1,
+                      block_partner_ml_sync                                   :  1,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      reserved_0a                                             :  3;
+#else
+             uint16_t reserved_0a                                             :  3,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      block_partner_ml_sync                                   :  1,
+                      block_self_ml_sync                                      :  1,
+                      nstr_mlo_sta_id                                         : 10;
+#endif
+};
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET                                   0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB                                      0
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB                                      9
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK                                     0x000003ff
+
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET                                0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK                                  0x00000400
+
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK                               0x00000800
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK                               0x00001000
+
+#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET                                       0x00000000
+#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB                                          13
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB                                          15
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK                                         0x0000e000
+
+#endif
diff --git a/hw/fig/v1/mon_buffer_addr.h b/hw/fig/v1/mon_buffer_addr.h
new file mode 100644
index 000000000000..8cb6f5fd57b9
--- /dev/null
+++ b/hw/fig/v1/mon_buffer_addr.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_BUFFER_ADDR_H_
+#define _MON_BUFFER_ADDR_H_
+
+#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
+
+#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
+
+struct mon_buffer_addr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t dma_length                                              : 12,
+                      reserved_2a                                             :  4,
+                      msdu_continuation                                       :  1,
+                      truncated                                               :  1,
+                      reserved_2b                                             : 14;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reserved_2b                                             : 14,
+                      truncated                                               :  1,
+                      msdu_continuation                                       :  1,
+                      reserved_2a                                             :  4,
+                      dma_length                                              : 12;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET                                0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB                                   0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB                                   31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK                                  0x00000000ffffffff
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET                               0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB                                  32
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB                                  63
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK                                 0xffffffff00000000
+
+#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET                                           0x0000000000000008
+#define MON_BUFFER_ADDR_DMA_LENGTH_LSB                                              0
+#define MON_BUFFER_ADDR_DMA_LENGTH_MSB                                              11
+#define MON_BUFFER_ADDR_DMA_LENGTH_MASK                                             0x0000000000000fff
+
+#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2A_LSB                                             12
+#define MON_BUFFER_ADDR_RESERVED_2A_MSB                                             15
+#define MON_BUFFER_ADDR_RESERVED_2A_MASK                                            0x000000000000f000
+
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET                                    0x0000000000000008
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK                                      0x0000000000010000
+
+#define MON_BUFFER_ADDR_TRUNCATED_OFFSET                                            0x0000000000000008
+#define MON_BUFFER_ADDR_TRUNCATED_LSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MASK                                              0x0000000000020000
+
+#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2B_LSB                                             18
+#define MON_BUFFER_ADDR_RESERVED_2B_MSB                                             31
+#define MON_BUFFER_ADDR_RESERVED_2B_MASK                                            0x00000000fffc0000
+
+#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET                                        0x0000000000000008
+#define MON_BUFFER_ADDR_TLV64_PADDING_LSB                                           32
+#define MON_BUFFER_ADDR_TLV64_PADDING_MSB                                           63
+#define MON_BUFFER_ADDR_TLV64_PADDING_MASK                                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/mon_destination_ring.h b/hw/fig/v1/mon_destination_ring.h
new file mode 100644
index 000000000000..1f373b585fd5
--- /dev/null
+++ b/hw/fig/v1/mon_destination_ring.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DESTINATION_RING_H_
+#define _MON_DESTINATION_RING_H_
+
+#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
+
+struct mon_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t end_offset                                              : 12,
+                      reserved_3a                                             :  2,
+                      link_info                                               :  2,
+                      end_reason                                              :  2,
+                      initiator                                               :  1,
+                      empty_descriptor                                        :  1,
+                      pkt_buffer_cnt                                          :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t looping_count                                           :  4,
+                      pkt_buffer_cnt                                          :  8,
+                      empty_descriptor                                        :  1,
+                      initiator                                               :  1,
+                      end_reason                                              :  2,
+                      link_info                                               :  2,
+                      reserved_3a                                             :  2,
+                      end_offset                                              : 12;
+#endif
+};
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET                         0x00000000
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB                            0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB                            31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK                           0xffffffff
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET                        0x00000004
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB                           0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB                           31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK                          0xffffffff
+
+#define MON_DESTINATION_RING_PPDU_ID_OFFSET                                         0x00000008
+#define MON_DESTINATION_RING_PPDU_ID_LSB                                            0
+#define MON_DESTINATION_RING_PPDU_ID_MSB                                            31
+#define MON_DESTINATION_RING_PPDU_ID_MASK                                           0xffffffff
+
+#define MON_DESTINATION_RING_END_OFFSET_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_OFFSET_LSB                                         0
+#define MON_DESTINATION_RING_END_OFFSET_MSB                                         11
+#define MON_DESTINATION_RING_END_OFFSET_MASK                                        0x00000fff
+
+#define MON_DESTINATION_RING_RESERVED_3A_OFFSET                                     0x0000000c
+#define MON_DESTINATION_RING_RESERVED_3A_LSB                                        12
+#define MON_DESTINATION_RING_RESERVED_3A_MSB                                        13
+#define MON_DESTINATION_RING_RESERVED_3A_MASK                                       0x00003000
+
+#define MON_DESTINATION_RING_LINK_INFO_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_LINK_INFO_LSB                                          14
+#define MON_DESTINATION_RING_LINK_INFO_MSB                                          15
+#define MON_DESTINATION_RING_LINK_INFO_MASK                                         0x0000c000
+
+#define MON_DESTINATION_RING_END_REASON_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_REASON_LSB                                         16
+#define MON_DESTINATION_RING_END_REASON_MSB                                         17
+#define MON_DESTINATION_RING_END_REASON_MASK                                        0x00030000
+
+#define MON_DESTINATION_RING_INITIATOR_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_INITIATOR_LSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MASK                                         0x00040000
+
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET                                0x0000000c
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK                                  0x00080000
+
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET                                  0x0000000c
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB                                     20
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB                                     27
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK                                    0x0ff00000
+
+#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000000c
+#define MON_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define MON_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define MON_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/fig/v1/mon_drop.h b/hw/fig/v1/mon_drop.h
new file mode 100644
index 000000000000..d1135ecd0dc2
--- /dev/null
+++ b/hw/fig/v1/mon_drop.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DROP_H_
+#define _MON_DROP_H_
+
+#define NUM_OF_DWORDS_MON_DROP 2
+
+#define NUM_OF_QWORDS_MON_DROP 1
+
+struct mon_drop {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t ppdu_drop_cnt                                           : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      tlv_drop_cnt                                            : 10,
+                      end_of_ppdu_seen                                        :  1,
+                      reserved_1a                                             :  1;
+#else
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t reserved_1a                                             :  1,
+                      end_of_ppdu_seen                                        :  1,
+                      tlv_drop_cnt                                            : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      ppdu_drop_cnt                                           : 10;
+#endif
+};
+
+#define MON_DROP_PPDU_ID_OFFSET                                                     0x0000000000000000
+#define MON_DROP_PPDU_ID_LSB                                                        0
+#define MON_DROP_PPDU_ID_MSB                                                        31
+#define MON_DROP_PPDU_ID_MASK                                                       0x00000000ffffffff
+
+#define MON_DROP_PPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_PPDU_DROP_CNT_LSB                                                  32
+#define MON_DROP_PPDU_DROP_CNT_MSB                                                  41
+#define MON_DROP_PPDU_DROP_CNT_MASK                                                 0x000003ff00000000
+
+#define MON_DROP_MPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_MPDU_DROP_CNT_LSB                                                  42
+#define MON_DROP_MPDU_DROP_CNT_MSB                                                  51
+#define MON_DROP_MPDU_DROP_CNT_MASK                                                 0x000ffc0000000000
+
+#define MON_DROP_TLV_DROP_CNT_OFFSET                                                0x0000000000000000
+#define MON_DROP_TLV_DROP_CNT_LSB                                                   52
+#define MON_DROP_TLV_DROP_CNT_MSB                                                   61
+#define MON_DROP_TLV_DROP_CNT_MASK                                                  0x3ff0000000000000
+
+#define MON_DROP_END_OF_PPDU_SEEN_OFFSET                                            0x0000000000000000
+#define MON_DROP_END_OF_PPDU_SEEN_LSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MASK                                              0x4000000000000000
+
+#define MON_DROP_RESERVED_1A_OFFSET                                                 0x0000000000000000
+#define MON_DROP_RESERVED_1A_LSB                                                    63
+#define MON_DROP_RESERVED_1A_MSB                                                    63
+#define MON_DROP_RESERVED_1A_MASK                                                   0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/mon_ingress_ring.h b/hw/fig/v1/mon_ingress_ring.h
new file mode 100644
index 000000000000..76f4e80417e0
--- /dev/null
+++ b/hw/fig/v1/mon_ingress_ring.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_INGRESS_RING_H_
+#define _MON_INGRESS_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_MON_INGRESS_RING 4
+
+struct mon_ingress_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#endif
+};
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB              0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB             0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB             7
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB         8
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB         11
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB              12
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET                               0x00000008
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB                                  0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB                                  31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK                                 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET                              0x0000000c
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB                                 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB                                 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK                                0xffffffff
+
+#endif
diff --git a/hw/fig/v1/msmhwiobase.h b/hw/fig/v1/msmhwiobase.h
new file mode 100644
index 000000000000..f7620cef5599
--- /dev/null
+++ b/hw/fig/v1/msmhwiobase.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define SOC_WFSS_CE_REG_BASE                                        0x01b80000
+#define SOC_WFSS_CE_REG_BASE_SIZE                                   0x0001c000
+#define SOC_WFSS_CE_REG_BASE_PHYS                                   0x01b80000
+#endif
diff --git a/hw/fig/v1/msmhwioreg.h b/hw/fig/v1/msmhwioreg.h
new file mode 100644
index 000000000000..881c73e30f58
--- /dev/null
+++ b/hw/fig/v1/msmhwioreg.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef __MSMHWIOREG_H__
+#define __MSMHWIOREG_H__
+
+#include "msmhwiobase.h"
+
+#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
+#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
+
+
+#endif
diff --git a/hw/fig/v1/no_ack_report.h b/hw/fig/v1/no_ack_report.h
new file mode 100644
index 000000000000..5f9660801de6
--- /dev/null
+++ b/hw/fig/v1/no_ack_report.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_ack_transmit_reason                                  :  4,
+                      macrx_abort_reason                                      :  4,
+                      phyrx_abort_reason                                      :  8,
+                      frame_control                                           : 16;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      sr_ppdu_during_obss                                     :  1,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      reserved_1                                              :  3;
+             uint32_t pre_bt_broadcast_status_details                         : 12,
+                      first_bt_broadcast_status_details                       : 12,
+                      reserved_2                                              :  8;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_3                                              : 20;
+#else
+             uint32_t frame_control                                           : 16,
+                      phyrx_abort_reason                                      :  8,
+                      macrx_abort_reason                                      :  4,
+                      no_ack_transmit_reason                                  :  4;
+             uint32_t reserved_1                                              :  3,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      sr_ppdu_during_obss                                     :  1,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t reserved_2                                              :  8,
+                      first_bt_broadcast_status_details                       : 12,
+                      pre_bt_broadcast_status_details                         : 12;
+             uint32_t reserved_3                                              : 20,
+                      second_bt_broadcast_status_details                      : 12;
+#endif
+};
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET                                 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB                                    0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB                                    3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK                                   0x0000000f
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB                                        4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB                                        7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK                                       0x000000f0
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB                                        8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB                                        15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK                                       0x0000ff00
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET                                          0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB                                             16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB                                             31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK                                            0xffff0000
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET                                       0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB                                          0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB                                          23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK                                         0x00ffffff
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET                                    0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK                                      0x01000000
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET                     0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB                        25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB                        28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK                       0x1e000000
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET                                             0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB                                                29
+#define NO_ACK_REPORT_RESERVED_1_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_1_MASK                                               0xe0000000
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                        0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                           0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                           11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                          0x00000fff
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                      0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                         12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                         23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                        0x00fff000
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET                                             0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB                                                24
+#define NO_ACK_REPORT_RESERVED_2_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_2_MASK                                               0xff000000
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET                     0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                        0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                        11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                       0x00000fff
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET                                             0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB                                                12
+#define NO_ACK_REPORT_RESERVED_3_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_3_MASK                                               0xfffff000
+
+#endif
diff --git a/hw/fig/v1/ofdma_trigger_details.h b/hw/fig/v1/ofdma_trigger_details.h
new file mode 100644
index 000000000000..604b52e0d464
--- /dev/null
+++ b/hw/fig/v1/ofdma_trigger_details.h
@@ -0,0 +1,928 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _OFDMA_TRIGGER_DETAILS_H_
+#define _OFDMA_TRIGGER_DETAILS_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26
+
+#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13
+
+struct ofdma_trigger_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ax_trigger_source                                       :  1,
+                      rx_trigger_frame_user_source                            :  2,
+                      received_bandwidth                                      :  3,
+                      txop_duration_all_ones                                  :  1,
+                      eht_trigger_response                                    :  1,
+                      pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      rxpcu_pcie_l0_req_duration                              :  8;
+             uint32_t he_trigger_ul_ppdu_length                               :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_reserved                                     :  1,
+                      bss_color                                               :  6;
+             uint32_t trigger_type                                            :  4,
+                      lsig_response_length                                    : 12,
+                      cascade_indication                                      :  1,
+                      carrier_sense                                           :  1,
+                      bandwidth                                               :  2,
+                      cp_ltf_size                                             :  2,
+                      mu_mimo_ltf_mode                                        :  1,
+                      number_of_ltfs                                          :  3,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ap_tx_power_lsb_part                                    :  4;
+             uint32_t ap_tx_power_msb_part                                    :  2,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      spatial_reuse                                           : 16,
+                      doppler                                                 :  1,
+                      he_siga_reserved                                        :  9,
+                      reserved_3b                                             :  1;
+             uint32_t aid12                                                   : 12,
+                      ru_allocation                                           :  9,
+                      mcs                                                     :  4,
+                      dcm                                                     :  1,
+                      start_spatial_stream                                    :  3,
+                      number_of_spatial_stream                                :  3;
+             uint32_t target_rssi                                             :  7,
+                      coding_type                                             :  1,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      tid_aggregation_limit                                   :  3,
+                      reserved_5b                                             :  1,
+                      prefered_ac                                             :  2,
+                      bar_control_ack_policy                                  :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_reserved                                    :  9,
+                      bar_control_tid_info                                    :  4;
+             uint32_t nr0_per_tid_info_reserved                               : 12,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr1_per_tid_info_reserved                               : 12,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr2_per_tid_info_reserved                               : 12,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr3_per_tid_info_reserved                               : 12,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr4_per_tid_info_reserved                               : 12,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr5_per_tid_info_reserved                               : 12,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr6_per_tid_info_reserved                               : 12,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr7_per_tid_info_reserved                               : 12,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t fb_segment_retransmission_bitmap                        :  8,
+                      reserved_14a                                            :  2,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_duration_field                                       : 16,
+                      scrambler_seed                                          :  7,
+                      rx_chain_mask_type                                      :  1;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t sw_peer_id                                              : 16,
+                      response_tx_duration                                    : 16;
+             uint32_t __reserved_g_0022_trigger_subtype                                 :  4,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      reserved_18a                                            :  1,
+                      qos_null_only_response_tx                               :  1;
+             uint32_t tbr_trigger_sound_sac                                   : 16,
+                      reserved_19a                                            :  8,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19b                                            :  3;
+             uint32_t eht_special_aid12                                       : 12,
+                      phy_version                                             :  3,
+                      bandwidth_ext                                           :  2,
+                      eht_spatial_reuse                                       :  8,
+                      u_sig_reserved1                                         :  7;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t __reserved_g_0035                                                 :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      blackout_details_en                                     :  1,
+                      uhr_trig_response                                       :  1,
+                      mcs_ext                                                 :  1,
+                      dso_primary20_index_select                              :  4,
+                      dso_icf_reception                                       :  1,
+                      dru_spreading_bw                                        :  2,
+                      dru_indication_per_80mhz                                :  4,
+                      coding_type_ext                                         :  1,
+                      pad_duration                                            :  5,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_22a                                            :  6;
+             uint32_t dso_cca_puncture_pattern                                : 16,
+                      dso_freq_subband_channel_bonding_mask                   : 16;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 32;
+#else
+             uint32_t rxpcu_pcie_l0_req_duration                              :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8,
+                      eht_trigger_response                                    :  1,
+                      txop_duration_all_ones                                  :  1,
+                      received_bandwidth                                      :  3,
+                      rx_trigger_frame_user_source                            :  2,
+                      ax_trigger_source                                       :  1;
+             uint32_t bss_color                                               :  6,
+                      he_trigger_reserved                                     :  1,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_ul_ppdu_length                               :  5;
+             uint32_t ap_tx_power_lsb_part                                    :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      number_of_ltfs                                          :  3,
+                      mu_mimo_ltf_mode                                        :  1,
+                      cp_ltf_size                                             :  2,
+                      bandwidth                                               :  2,
+                      carrier_sense                                           :  1,
+                      cascade_indication                                      :  1,
+                      lsig_response_length                                    : 12,
+                      trigger_type                                            :  4;
+             uint32_t reserved_3b                                             :  1,
+                      he_siga_reserved                                        :  9,
+                      doppler                                                 :  1,
+                      spatial_reuse                                           : 16,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      ap_tx_power_msb_part                                    :  2;
+             uint32_t number_of_spatial_stream                                :  3,
+                      start_spatial_stream                                    :  3,
+                      dcm                                                     :  1,
+                      mcs                                                     :  4,
+                      ru_allocation                                           :  9,
+                      aid12                                                   : 12;
+             uint32_t bar_control_tid_info                                    :  4,
+                      bar_control_reserved                                    :  9,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_ack_policy                                  :  1,
+                      prefered_ac                                             :  2,
+                      reserved_5b                                             :  1,
+                      tid_aggregation_limit                                   :  3,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      coding_type                                             :  1,
+                      target_rssi                                             :  7;
+             uint32_t nr0_start_seq_ctrl_start_seq_number                     : 12,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_per_tid_info_reserved                               : 12;
+             uint32_t nr1_start_seq_ctrl_start_seq_number                     : 12,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_per_tid_info_reserved                               : 12;
+             uint32_t nr2_start_seq_ctrl_start_seq_number                     : 12,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_per_tid_info_reserved                               : 12;
+             uint32_t nr3_start_seq_ctrl_start_seq_number                     : 12,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_per_tid_info_reserved                               : 12;
+             uint32_t nr4_start_seq_ctrl_start_seq_number                     : 12,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_per_tid_info_reserved                               : 12;
+             uint32_t nr5_start_seq_ctrl_start_seq_number                     : 12,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_per_tid_info_reserved                               : 12;
+             uint32_t nr6_start_seq_ctrl_start_seq_number                     : 12,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_per_tid_info_reserved                               : 12;
+             uint32_t nr7_start_seq_ctrl_start_seq_number                     : 12,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_per_tid_info_reserved                               : 12;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_14a                                            :  2,
+                      fb_segment_retransmission_bitmap                        :  8;
+             uint32_t rx_chain_mask_type                                      :  1,
+                      scrambler_seed                                          :  7,
+                      rx_duration_field                                       : 16,
+                      rx_chain_mask                                           :  8;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t response_tx_duration                                    : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t qos_null_only_response_tx                               :  1,
+                      reserved_18a                                            :  1,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      __reserved_g_0022_trigger_subtype                                 :  4;
+             uint32_t reserved_19b                                            :  3,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19a                                            :  8,
+                      tbr_trigger_sound_sac                                   : 16;
+             uint32_t u_sig_reserved1                                         :  7,
+                      eht_spatial_reuse                                       :  8,
+                      bandwidth_ext                                           :  2,
+                      phy_version                                             :  3,
+                      eht_special_aid12                                       : 12;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t reserved_22a                                            :  6,
+                      ects_as_tb_ppdu                                         :  1,
+                      pad_duration                                            :  5,
+                      coding_type_ext                                         :  1,
+                      dru_indication_per_80mhz                                :  4,
+                      dru_spreading_bw                                        :  2,
+                      dso_icf_reception                                       :  1,
+                      dso_primary20_index_select                              :  4,
+                      mcs_ext                                                 :  1,
+                      uhr_trig_response                                       :  1,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      __reserved_g_0035                                                 :  1;
+             uint32_t dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_cca_puncture_pattern                                : 16;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 32;
+#endif
+};
+
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK                                0x0000000000000001
+
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET                   0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB                      1
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB                      2
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK                     0x0000000000000006
+
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET                             0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB                                3
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB                                5
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK                               0x0000000000000038
+
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK                           0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET                           0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK                             0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET                                  0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB                                     8
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB                                     15
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK                                    0x000000000000ff00
+
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB                                         16
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB                                         23
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK                                        0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET                     0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB                        24
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB                        31
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK                       0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB                         36
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK                        0x0000001f00000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET                       0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB                          37
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB                          44
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK                         0x00001fe000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB                            45
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB                            49
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK                           0x0003e00000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB                         50
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB                         54
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK                        0x007c000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB                                 55
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB                                 56
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK                                0x0180000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET                            0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK                              0x0200000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB                                         58
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB                                         63
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK                                        0xfc00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET                                   0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB                                      0
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB                                      3
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK                                     0x000000000000000f
+
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB                              4
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB                              15
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK                             0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET                             0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK                               0x0000000000010000
+
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK                                    0x0000000000020000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET                                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB                                         18
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB                                         19
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK                                        0x00000000000c0000
+
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB                                       20
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB                                       21
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK                                      0x0000000000300000
+
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK                                 0x0000000000400000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET                                 0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB                                    23
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB                                    25
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK                                   0x0000000003800000
+
+#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET                                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_STBC_LSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MASK                                             0x0000000004000000
+
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET                              0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK                                0x0000000008000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB                              28
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK                             0x00000000f0000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB                              32
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB                              33
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK                             0x0000000300000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB                         34
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB                         35
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK                        0x0000000c00000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                 0x0000001000000000
+
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB                                     37
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB                                     52
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK                                    0x001fffe000000000
+
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET                                        0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK                                          0x0020000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB                                  54
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB                                  62
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK                                 0x7fc0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK                                      0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET                                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_AID12_LSB                                             0
+#define OFDMA_TRIGGER_DETAILS_AID12_MSB                                             11
+#define OFDMA_TRIGGER_DETAILS_AID12_MASK                                            0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET                                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB                                     12
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB                                     20
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK                                    0x00000000001ff000
+
+#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MCS_LSB                                               21
+#define OFDMA_TRIGGER_DETAILS_MCS_MSB                                               24
+#define OFDMA_TRIGGER_DETAILS_MCS_MASK                                              0x0000000001e00000
+
+#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_DCM_LSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MASK                                              0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB                              26
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB                              28
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK                             0x000000001c000000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET                       0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB                          29
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB                          31
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK                         0x00000000e0000000
+
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB                                       32
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB                                       38
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK                                      0x0000007f00000000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK                                      0x0000008000000000
+
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB                            40
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB                            41
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK                           0x0000030000000000
+
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB                             42
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB                             44
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK                            0x00001c0000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK                                      0x0000200000000000
+
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB                                       46
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB                                       47
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK                                      0x0000c00000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK                           0x0001000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK                            0x0002000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK                    0x0004000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB                              51
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB                              59
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK                             0x0ff8000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB                              60
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK                             0xf000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET               0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB                  0
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB                  7
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK                 0x00000000000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET                                   0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB                                      8
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB                                      9
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK                                     0x0000000000000300
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                   10
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                   15
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                  0x000000000000fc00
+
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET                        0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB                           16
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB                           31
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK                          0x00000000ffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET                                  0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB                                     32
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB                                     39
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK                                    0x000000ff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET                              0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB                                 40
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB                                 55
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK                                0x00ffff0000000000
+
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET                                 0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB                                    56
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB                                    62
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK                                   0x7f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET                             0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK                               0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET          0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB             0
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB             9
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK            0x00000000000003ff
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK         0x0000000000000400
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK      0x0000000000000800
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK      0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET              0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB                 13
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB                 15
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK                0x000000000000e000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET                       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB                          16
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB                          23
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK                         0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB                              24
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK                             0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET                                     0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB                                        32
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB                                        47
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK                                       0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB                              48
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK                             0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET                  0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB                     4
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB                     15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK                    0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB                  16
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB                  24
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK                 0x0000000001ff0000
+
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET                                        0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB                                           25
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB                                           27
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK                                          0x000000000e000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB                  28
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB                  29
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK                 0x0000000030000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK                                     0x0000000040000000
+
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET                      0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK                        0x0000000080000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET                          0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB                             32
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB                             47
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK                            0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB                                      48
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB                                      55
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK                                     0x00ff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET                                0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB                                   56
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB                                   60
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK                                  0x1f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB                                      61
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK                                     0xe000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB                                 11
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK                                0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET                                    0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB                                       12
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB                                       14
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK                                      0x0000000000007000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET                                  0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB                                     15
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB                                     16
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK                                    0x0000000000018000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB                                 17
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB                                 24
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK                                0x0000000001fe0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET                                0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB                                   31
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK                                  0x00000000fe000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET            0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB               32
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB               63
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK              0xffffffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET                            0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK                              0x0000000000000020
+
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK                                0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET                                        0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK                                          0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET                     0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB                        8
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB                        11
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK                       0x0000000000000f00
+
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK                                0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET                               0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB                                  13
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB                                  14
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK                                 0x0000000000006000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB                          15
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB                          18
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK                         0x0000000000078000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK                                  0x0000000000080000
+
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB                                      20
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB                                      24
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK                                     0x0000000001f00000
+
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK                                  0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB                                      26
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK                                     0x00000000fc000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB                          32
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB                          47
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK                         0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET          0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB             48
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB             63
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK            0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB                                      0
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK                                     0x00000000ffffffff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB                                      32
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/pcu_ppdu_setup_init.h b/hw/fig/v1/pcu_ppdu_setup_init.h
new file mode 100644
index 000000000000..621b649df965
--- /dev/null
+++ b/hw/fig/v1/pcu_ppdu_setup_init.h
@@ -0,0 +1,2309 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PCU_PPDU_SETUP_INIT_H_
+#define _PCU_PPDU_SETUP_INIT_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58
+
+#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29
+
+struct pcu_ppdu_setup_init {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t medium_prot_type                                        :  3,
+                      response_type                                           :  5,
+                      response_info_part2_required                            :  1,
+                      response_to_response                                    :  3,
+                      mba_user_order                                          :  2,
+                      expected_mba_size                                       : 11,
+                      required_ul_mu_resp_user_count                          :  6,
+                      transmitted_bssid_check_en                              :  1;
+             uint32_t mprot_required_bw1                                      :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw320                                    :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      update_timestamp_64                                     :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_32_upper                               :  1,
+                      reserved_1a                                             : 13;
+             uint32_t insert_timestamp_offset_0                               : 16,
+                      insert_timestamp_offset_1                               : 16;
+             uint32_t max_bw40_try_count                                      :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw320_try_count                                     :  4,
+                      insert_wur_timestamp_offset                             :  6,
+                      update_wur_timestamp                                    :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      insert_wur_fcs                                          :  1,
+                      reserved_3b                                             :  3;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_hw_response_tx_duration                             : 16,
+                      r2r_rx_duration_field                                   : 16;
+             uint32_t r2r_group_id                                            :  6,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_sta_partial_aid                                     : 11,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_set_required_response_time                          :  1,
+                      reserved_29a                                            :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      r2r_bw40_active_channel                                 :  3;
+             uint32_t r2r_bw80_active_channel                                 :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw320                                               :  3,
+                      tx_with_blackout_details                                :  1,
+                      expect_rx_with_blackout_details                         :  1;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t mu_response_expected_bitmap_36_32                       :  5,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_expected_response_sta_count                          :  6,
+                      transmit_includes_multidestination                      :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      insert_current_tx_start_timing_info                     :  1,
+                      tx_start_transmit_time_byte_offset                      : 12;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad1_47_32                              : 16,
+                      protection_frame_ad2_15_0                               : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t dynamic_medium_prot_threshold                           : 24,
+                      dynamic_medium_prot_type                                :  1,
+                      reserved_54a                                            :  7;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad3_47_32                              : 16,
+                      protection_frame_ad4_15_0                               : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#else
+             uint32_t transmitted_bssid_check_en                              :  1,
+                      required_ul_mu_resp_user_count                          :  6,
+                      expected_mba_size                                       : 11,
+                      mba_user_order                                          :  2,
+                      response_to_response                                    :  3,
+                      response_info_part2_required                            :  1,
+                      response_type                                           :  5,
+                      medium_prot_type                                        :  3;
+             uint32_t reserved_1a                                             : 13,
+                      update_timestamp_32_upper                               :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_64                                     :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      mprot_required_bw320                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw1                                      :  1;
+             uint32_t insert_timestamp_offset_1                               : 16,
+                      insert_timestamp_offset_0                               : 16;
+             uint32_t reserved_3b                                             :  3,
+                      insert_wur_fcs                                          :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      update_wur_timestamp                                    :  1,
+                      insert_wur_timestamp_offset                             :  6,
+                      max_bw320_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw40_try_count                                      :  4;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_rx_duration_field                                   : 16,
+                      r2r_hw_response_tx_duration                             : 16;
+             uint32_t r2r_bw40_active_channel                                 :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      reserved_29a                                            :  3,
+                      r2r_set_required_response_time                          :  1,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_sta_partial_aid                                     : 11,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_group_id                                            :  6;
+             uint32_t expect_rx_with_blackout_details                         :  1,
+                      tx_with_blackout_details                                :  1,
+                      r2r_bw320                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw80_active_channel                                 :  3;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t tx_start_transmit_time_byte_offset                      : 12,
+                      insert_current_tx_start_timing_info                     :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      transmit_includes_multidestination                      :  1,
+                      mu_expected_response_sta_count                          :  6,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_response_expected_bitmap_36_32                       :  5;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad2_15_0                               : 16,
+                      protection_frame_ad1_47_32                              : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t reserved_54a                                            :  7,
+                      dynamic_medium_prot_type                                :  1,
+                      dynamic_medium_prot_threshold                           : 24;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad4_15_0                               : 16,
+                      protection_frame_ad3_47_32                              : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#endif
+};
+
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB                                    0
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB                                    2
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK                                   0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET                                    0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB                                       3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB                                       7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK                                      0x00000000000000f8
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK                       0x0000000000000100
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB                                9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB                                11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK                               0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB                                      12
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB                                      13
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK                                     0x0000000000003000
+
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB                                   14
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB                                   24
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK                                  0x0000000001ffc000
+
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB                      25
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB                      30
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK                     0x000000007e000000
+
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET                       0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK                         0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK                                 0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK                                0x0000000200000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK                                0x0000000400000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK                                0x0000000800000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK                               0x0000001000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK                               0x0000002000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK                               0x0000004000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK                                   0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK                                  0x0000010000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK                                  0x0000020000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK                                  0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK                                 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK                                 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK                                 0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK                                     0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK                       0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK                                0x0001000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK                          0x0002000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK                          0x0004000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB                                         51
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK                                        0xfff8000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB                           15
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK                          0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB                           16
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB                           31
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB                                  35
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK                                 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB                                  36
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB                                  39
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK                                 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB                                 40
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB                                 43
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK                                0x00000f0000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB                                 44
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB                                 47
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK                                0x0000f00000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB                                 51
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK                                0x000f000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB                         52
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB                         57
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK                        0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET                             0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK                               0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET                       0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK                         0x0800000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET                                   0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK                                     0x1000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET                                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB                                         61
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK                                        0xe000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET  0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET     0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET    0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET   0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET      0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET       0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET       0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET  0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET     0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB        57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB        60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK       0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET    0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK      0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK           0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK           0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK     0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET      0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK        0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK         0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET  0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB     35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK    0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET          0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB             36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB             38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK            0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK     0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB          40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB          47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK         0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB      48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB      55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK     0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB    4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK   0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB     5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK    0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET          0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK            0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB        14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK       0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK       0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK   0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK    0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB  50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB  52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB     59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB     63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK    0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK    0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK  0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK    0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET  0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET     0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET    0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET   0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET      0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET       0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET       0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET    0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET   0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET     0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET         0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET         0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET    0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK      0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET   0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK     0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK          0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK          0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET  0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK    0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET     0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB        50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK       0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET      0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB         59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB         61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK        0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK   0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK           0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK    0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET      0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK        0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK    0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB   32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB   36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK  0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB    37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB    39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK   0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB            40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB            41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK           0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB       42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB       46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK      0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB       48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB       55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK      0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK   0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK   0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK   0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB  43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB  45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB    52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB    57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK   0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET    0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET   0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET     0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET         0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET         0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET                      0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB                         0
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB                         15
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK                        0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET                            0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB                               16
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB                               31
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK                              0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB                                        32
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB                                        37
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK                                       0x0000003f00000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB                             38
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB                             41
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK                            0x000003c000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET                              0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB                                 42
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB                                 52
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK                                0x001ffc0000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET                0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK                  0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET                   0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK                     0x0040000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB                                        55
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB                                        57
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK                                       0x0380000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB                             58
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB                             60
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK                            0x1c00000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB                             61
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB                             63
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK                            0xe000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET                          0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB                             0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB                             2
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK                            0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB                            3
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB                            5
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK                           0x0000000000000038
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB                            6
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB                            8
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK                           0x00000000000001c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB                            9
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB                            11
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK                           0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB                                            12
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB                                            14
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK                                           0x0000000000007000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB                                            15
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB                                            17
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK                                           0x0000000000038000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB                                            18
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB                                            20
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK                                           0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB                                           21
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB                                           23
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK                                          0x0000000000e00000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB                                           24
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB                                           26
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK                                          0x0000000007000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB                                           27
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB                                           29
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK                                          0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK                           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                  0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                    0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET                 0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB                    32
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB                    63
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK                   0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET                0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB                   0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB                   4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK                  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB                      5
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB                      10
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK                     0x00000000000007e0
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB                      11
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB                      16
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK                     0x000000000001f800
+
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK                 0x0000000000020000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET                 0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK                   0x0000000000040000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET              0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK                0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB                  20
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB                  31
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK                 0x00000000fff00000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET                        0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET                        0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK                         0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET                    0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB                       0
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB                       23
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK                      0x0000000000ffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET                         0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK                           0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET                                     0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB                                        25
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB                                        31
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK                                       0x00000000fe000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET                        0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET                        0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK                         0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/pdg_response.h b/hw/fig/v1/pdg_response.h
new file mode 100644
index 000000000000..a730a445ed10
--- /dev/null
+++ b/hw/fig/v1/pdg_response.h
@@ -0,0 +1,503 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_H_
+#define _PDG_RESPONSE_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE 14
+
+#define NUM_OF_QWORDS_PDG_RESPONSE 7
+
+struct pdg_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t hw_response_tx_duration                                 : 16,
+                      rx_duration_field                                       : 16;
+             uint32_t punctured_response_transmission                         :  1,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      scrambler_seed_override                                 :  2,
+                      response_density_valid                                  :  1,
+                      response_density                                        :  5,
+                      more_data                                               :  1,
+                      duration_indication                                     :  1,
+                      blackout_details_en                                     :  1,
+                      reserved_8a                                             :  1,
+                      bandwidth                                               :  3;
+             uint32_t ack_id                                                  : 16,
+                      block_ack_bitmap                                        : 16;
+             uint32_t response_frame_type                                     :  4,
+                      ack_id_ext                                              : 10,
+                      ftm_en                                                  :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 11;
+             uint32_t ndp_ba_start_seq_ctrl                                   : 12,
+                      active_channel                                          :  3,
+                      txop_duration_all_ones                                  :  1,
+                      frame_length                                            : 16;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      reserved_12a                                            :  7;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t rx_duration_field                                       : 16,
+                      hw_response_tx_duration                                 : 16;
+             uint32_t bandwidth                                               :  3,
+                      reserved_8a                                             :  1,
+                      blackout_details_en                                     :  1,
+                      duration_indication                                     :  1,
+                      more_data                                               :  1,
+                      response_density                                        :  5,
+                      response_density_valid                                  :  1,
+                      scrambler_seed_override                                 :  2,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      punctured_response_transmission                         :  1;
+             uint32_t block_ack_bitmap                                        : 16,
+                      ack_id                                                  : 16;
+             uint32_t sta_partial_aid                                         : 11,
+                      group_id                                                :  6,
+                      ftm_en                                                  :  1,
+                      ack_id_ext                                              : 10,
+                      response_frame_type                                     :  4;
+             uint32_t frame_length                                            : 16,
+                      txop_duration_all_ones                                  :  1,
+                      active_channel                                          :  3,
+                      ndp_ba_start_seq_ctrl                                   : 12;
+             uint32_t reserved_12a                                            :  7,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET                       0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB               1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB               24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK              0x0000000001fffffe
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET                          0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB                             25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB                             28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK                            0x000000001e000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET                         0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK                           0x0000000020000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK                                0x0000000040000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK                                0x0000000080000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET                        0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB                           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB                           39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK                          0x000000ff00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET                    0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB                       40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB                       47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK                      0x0000ff0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET                           0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB                              48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB                              50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK                             0x0007000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB                    51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB                    58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK                   0x07f8000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET                            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB                               59
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB                               61
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK                              0x3800000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK                   0x4000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET                0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK                  0x8000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB                          3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK                         0x000000000000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB                                  4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB                                  6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK                                 0x0000000000000070
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK                          0x0000000000000080
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET                            0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB                               8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB                               15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK                              0x000000000000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB                           16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB                           23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK                          0x0000000000ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET                     0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB                        24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB                        31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK                       0x00000000ff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB                         32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB                         36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK                        0x0000001f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB                          37
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB                          39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK                         0x000000e000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB                                  40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB                                  41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK                                 0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB                             42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB                             46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK                            0x00007c0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET                  0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK                    0x0000800000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB                             48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB                             55
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK                            0x00ff000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB                         56
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB                         63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK                        0xff00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB                 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB                 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK                0x000000000000007e
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET             0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB                7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB                10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK               0x0000000000000780
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB                  11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB                  12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK                 0x0000000000001800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK                         0x0000000000002000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK          0x0000000000004000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK                 0x0000000000008000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET      0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB         16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB         17
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK        0x0000000000030000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET                    0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB                       18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB                       20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK                      0x00000000001c0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK                  0x0000000000200000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB                  22
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB                  23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK                 0x0000000000c00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK                0x0000000001000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET           0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK             0x0000000002000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK                  0x0000000004000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB                          27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB                          31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK                         0x00000000f8000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB           35
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK          0x0000000f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB                  36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB                  39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK                 0x000000f000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB                   40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB                   41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK                  0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK                         0x0000040000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET                     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB                        43
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB                        45
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK                       0x0000380000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET                   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB                      46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB                      50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK                     0x0007c00000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK       0x0008000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB                          52
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB                          57
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK                         0x03f0000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB      58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB      63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK     0xfc00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB    13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB    15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK   0x000000000000e000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET            0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB               16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB               27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK              0x000000000fff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET        0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB           28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB           31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK          0x00000000f0000000
+
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET                                 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB                                    32
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB                                    47
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK                                   0x0000ffff00000000
+
+#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET                                       0x0000000000000018
+#define PDG_RESPONSE_RX_DURATION_FIELD_LSB                                          48
+#define PDG_RESPONSE_RX_DURATION_FIELD_MSB                                          63
+#define PDG_RESPONSE_RX_DURATION_FIELD_MASK                                         0xffff000000000000
+
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET                         0x0000000000000020
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK                           0x0000000000000001
+
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                        0x0000000000000020
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB                           1
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB                           16
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK                          0x000000000001fffe
+
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET                                 0x0000000000000020
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB                                    17
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB                                    18
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK                                   0x0000000000060000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET                                  0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK                                    0x0000000000080000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_LSB                                           20
+#define PDG_RESPONSE_RESPONSE_DENSITY_MSB                                           24
+#define PDG_RESPONSE_RESPONSE_DENSITY_MASK                                          0x0000000001f00000
+
+#define PDG_RESPONSE_MORE_DATA_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_MORE_DATA_LSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MASK                                                 0x0000000002000000
+
+#define PDG_RESPONSE_DURATION_INDICATION_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_DURATION_INDICATION_LSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MASK                                       0x0000000004000000
+
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK                                       0x0000000008000000
+
+#define PDG_RESPONSE_RESERVED_8A_OFFSET                                             0x0000000000000020
+#define PDG_RESPONSE_RESERVED_8A_LSB                                                28
+#define PDG_RESPONSE_RESERVED_8A_MSB                                                28
+#define PDG_RESPONSE_RESERVED_8A_MASK                                               0x0000000010000000
+
+#define PDG_RESPONSE_BANDWIDTH_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_BANDWIDTH_LSB                                                  29
+#define PDG_RESPONSE_BANDWIDTH_MSB                                                  31
+#define PDG_RESPONSE_BANDWIDTH_MASK                                                 0x00000000e0000000
+
+#define PDG_RESPONSE_ACK_ID_OFFSET                                                  0x0000000000000020
+#define PDG_RESPONSE_ACK_ID_LSB                                                     32
+#define PDG_RESPONSE_ACK_ID_MSB                                                     47
+#define PDG_RESPONSE_ACK_ID_MASK                                                    0x0000ffff00000000
+
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB                                           48
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB                                           63
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK                                          0xffff000000000000
+
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET                                     0x0000000000000028
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB                                        0
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB                                        3
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK                                       0x000000000000000f
+
+#define PDG_RESPONSE_ACK_ID_EXT_OFFSET                                              0x0000000000000028
+#define PDG_RESPONSE_ACK_ID_EXT_LSB                                                 4
+#define PDG_RESPONSE_ACK_ID_EXT_MSB                                                 13
+#define PDG_RESPONSE_ACK_ID_EXT_MASK                                                0x0000000000003ff0
+
+#define PDG_RESPONSE_FTM_EN_OFFSET                                                  0x0000000000000028
+#define PDG_RESPONSE_FTM_EN_LSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MASK                                                    0x0000000000004000
+
+#define PDG_RESPONSE_GROUP_ID_OFFSET                                                0x0000000000000028
+#define PDG_RESPONSE_GROUP_ID_LSB                                                   15
+#define PDG_RESPONSE_GROUP_ID_MSB                                                   20
+#define PDG_RESPONSE_GROUP_ID_MASK                                                  0x00000000001f8000
+
+#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET                                         0x0000000000000028
+#define PDG_RESPONSE_STA_PARTIAL_AID_LSB                                            21
+#define PDG_RESPONSE_STA_PARTIAL_AID_MSB                                            31
+#define PDG_RESPONSE_STA_PARTIAL_AID_MASK                                           0x00000000ffe00000
+
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET                                   0x0000000000000028
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB                                      32
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB                                      43
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK                                     0x00000fff00000000
+
+#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET                                          0x0000000000000028
+#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB                                             44
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB                                             46
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK                                            0x0000700000000000
+
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET                                  0x0000000000000028
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK                                    0x0000800000000000
+
+#define PDG_RESPONSE_FRAME_LENGTH_OFFSET                                            0x0000000000000028
+#define PDG_RESPONSE_FRAME_LENGTH_LSB                                               48
+#define PDG_RESPONSE_FRAME_LENGTH_MSB                                               63
+#define PDG_RESPONSE_FRAME_LENGTH_MASK                                              0xffff000000000000
+
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET                              0x0000000000000030
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB                                 0
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB                                 3
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK                                0x000000000000000f
+
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                   0x0000000000000030
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB                      4
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB                      19
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK                     0x00000000000ffff0
+
+#define PDG_RESPONSE_PAD_DURATION_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_PAD_DURATION_LSB                                               20
+#define PDG_RESPONSE_PAD_DURATION_MSB                                               24
+#define PDG_RESPONSE_PAD_DURATION_MASK                                              0x0000000001f00000
+
+#define PDG_RESPONSE_RESERVED_12A_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_RESERVED_12A_LSB                                               25
+#define PDG_RESPONSE_RESERVED_12A_MSB                                               31
+#define PDG_RESPONSE_RESERVED_12A_MASK                                              0x00000000fe000000
+
+#define PDG_RESPONSE_TLV64_PADDING_OFFSET                                           0x0000000000000030
+#define PDG_RESPONSE_TLV64_PADDING_LSB                                              32
+#define PDG_RESPONSE_TLV64_PADDING_MSB                                              63
+#define PDG_RESPONSE_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/pdg_response_rate_setting.h b/hw/fig/v1/pdg_response_rate_setting.h
new file mode 100644
index 000000000000..eb123386f2bf
--- /dev/null
+++ b/hw/fig/v1/pdg_response_rate_setting.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  1,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      pkt_type                                                :  4,
+                      smoothing                                               :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      stf_ltf_3db_boost                                       :  1,
+                      force_extra_symbol                                      :  1;
+             uint32_t reserved_2a                                             :  4,
+                      nss                                                     :  3,
+                      dpd_enable                                              :  1,
+                      tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_chain_mask                                           :  8;
+             uint32_t alt_rate_mcs                                            :  5,
+                      reserved_3a                                             :  3,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8;
+             uint32_t aggregation                                             :  1,
+                      dot11ax_bss_color_id                                    :  6,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_4a                                             :  5;
+             uint32_t dot11ax_ext_ru_start_index                              :  4,
+                      dot11ax_ext_ru_size                                     :  4,
+                      eht_duplicate_mode                                      :  2,
+                      he_sigb_dcm                                             :  1,
+                      he_sigb_0_mcs                                           :  3,
+                      num_he_sigb_sym                                         :  5,
+                      required_response_time_source                           :  1,
+                      reserved_5a                                             :  6,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t required_response_time                                  : 12,
+                      dot11be_params_placeholder                              :  4;
+#else
+             uint32_t stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      smoothing                                               :  1,
+                      pkt_type                                                :  4,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      reserved_0a                                             :  1;
+             uint32_t force_extra_symbol                                      :  1,
+                      stf_ltf_3db_boost                                       :  1,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t tx_chain_mask                                           :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8,
+                      dpd_enable                                              :  1,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  4;
+             uint32_t alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8,
+                      ldpc_2x_codeword                                        :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      reserved_3a                                             :  3,
+                      alt_rate_mcs                                            :  5;
+             uint32_t reserved_4a                                             :  5,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_bss_color_id                                    :  6,
+                      aggregation                                             :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_5a                                             :  6,
+                      required_response_time_source                           :  1,
+                      num_he_sigb_sym                                         :  5,
+                      he_sigb_0_mcs                                           :  3,
+                      he_sigb_dcm                                             :  1,
+                      eht_duplicate_mode                                      :  2,
+                      dot11ax_ext_ru_size                                     :  4,
+                      dot11ax_ext_ru_start_index                              :  4;
+             uint32_t dot11be_params_placeholder                              :  4,
+                      required_response_time                                  : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET                                0x00000008
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB                                   3
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK                                  0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  4
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000001f
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   5
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000e0
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      14
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00007c00
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET                           0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK                             0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
+
+#endif
diff --git a/hw/fig/v1/pdg_tx_req.h b/hw/fig/v1/pdg_tx_req.h
new file mode 100644
index 000000000000..6baf640807da
--- /dev/null
+++ b/hw/fig/v1/pdg_tx_req.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_TX_REQ_H_
+#define _PDG_TX_REQ_H_
+
+#define NUM_OF_DWORDS_PDG_TX_REQ 2
+
+#define NUM_OF_QWORDS_PDG_TX_REQ 1
+
+struct pdg_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_reason                                               :  2,
+                      use_puncture_pattern                                    :  2,
+                      req_bw                                                  :  3,
+                      puncture_pattern_number                                 :  6,
+                      reserved_0b                                             :  1,
+                      req_paprd                                               :  1,
+                      duration_field_boundary_valid                           :  1,
+                      duration_field_boundary                                 : 16;
+             uint32_t puncture_subband_mask                                   : 16,
+                      reserved_0c                                             : 16;
+#else
+             uint32_t duration_field_boundary                                 : 16,
+                      duration_field_boundary_valid                           :  1,
+                      req_paprd                                               :  1,
+                      reserved_0b                                             :  1,
+                      puncture_pattern_number                                 :  6,
+                      req_bw                                                  :  3,
+                      use_puncture_pattern                                    :  2,
+                      tx_reason                                               :  2;
+             uint32_t reserved_0c                                             : 16,
+                      puncture_subband_mask                                   : 16;
+#endif
+};
+
+#define PDG_TX_REQ_TX_REASON_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_TX_REASON_LSB                                                    0
+#define PDG_TX_REQ_TX_REASON_MSB                                                    1
+#define PDG_TX_REQ_TX_REASON_MASK                                                   0x0000000000000003
+
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET                                      0x0000000000000000
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB                                         2
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB                                         3
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK                                        0x000000000000000c
+
+#define PDG_TX_REQ_REQ_BW_OFFSET                                                    0x0000000000000000
+#define PDG_TX_REQ_REQ_BW_LSB                                                       4
+#define PDG_TX_REQ_REQ_BW_MSB                                                       6
+#define PDG_TX_REQ_REQ_BW_MASK                                                      0x0000000000000070
+
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB                                      7
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB                                      12
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK                                     0x0000000000001f80
+
+#define PDG_TX_REQ_RESERVED_0B_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0B_LSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MASK                                                 0x0000000000002000
+
+#define PDG_TX_REQ_REQ_PAPRD_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_REQ_PAPRD_LSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MASK                                                   0x0000000000004000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET                             0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK                               0x0000000000008000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB                                      16
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB                                      31
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK                                     0x00000000ffff0000
+
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET                                     0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB                                        32
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB                                        47
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK                                       0x0000ffff00000000
+
+#define PDG_TX_REQ_RESERVED_0C_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0C_LSB                                                  48
+#define PDG_TX_REQ_RESERVED_0C_MSB                                                  63
+#define PDG_TX_REQ_RESERVED_0C_MASK                                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_abort_request_info.h b/hw/fig/v1/phyrx_abort_request_info.h
new file mode 100644
index 000000000000..1f3bf4b817b9
--- /dev/null
+++ b/hw/fig/v1/phyrx_abort_request_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phyrx_abort_reason                                      :  8,
+                      phy_enters_nap_state                                    :  1,
+                      phy_enters_defer_state                                  :  1,
+                      gain_change_by_main                                     :  1,
+                      gain_change_by_bt                                       :  1,
+                      main_tx_indication                                      :  1,
+                      bt_tx_indication                                        :  1,
+                      concurrent_mode                                         :  1,
+                      reserved_0                                              :  1,
+                      receive_duration                                        : 16;
+#else
+             uint32_t receive_duration                                        : 16,
+                      reserved_0                                              :  1,
+                      concurrent_mode                                         :  1,
+                      bt_tx_indication                                        :  1,
+                      main_tx_indication                                      :  1,
+                      gain_change_by_bt                                       :  1,
+                      gain_change_by_main                                     :  1,
+                      phy_enters_defer_state                                  :  1,
+                      phy_enters_nap_state                                    :  1,
+                      phyrx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB                             0
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB                             7
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET                        0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK                          0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET                      0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK                        0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET                         0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK                           0x00000400
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET                           0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK                             0x00000800
+
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK                            0x00001000
+
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK                              0x00002000
+
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET                             0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK                               0x00004000
+
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x00008000
+
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB                               16
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB                               31
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK                              0xffff0000
+
+#endif
diff --git a/hw/fig/v1/phyrx_common_user_info.h b/hw/fig/v1/phyrx_common_user_info.h
new file mode 100644
index 000000000000..1aac5bf9fd32
--- /dev/null
+++ b/hw/fig/v1/phyrx_common_user_info.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
+
+#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
+
+struct phyrx_common_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t receive_duration                                        : 16,
+                      reserved_0a                                             : 16;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      eht___reserved_g_0022_ndp                                         :  1,
+                      reserved_1a                                             :  8,
+                      obss_nav_update_enable                                  :  1,
+                      obss_nav_value                                          : 16;
+             uint32_t eht_or_uhr_ppdu_type                                    :  2,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      txop_duration                                           :  7,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      spatial_reuse                                           :  4,
+                      rx_ndp                                                  :  1,
+                      dot11bn_su_elr                                          :  1,
+                      reserved_2a                                             :  6;
+             uint32_t eht_duplicate                                           :  2,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      doppler_indication                                      :  1,
+                      sta_id                                                  : 11,
+                      puncture_bitmap                                         : 16;
+#else
+             uint32_t reserved_0a                                             : 16,
+                      receive_duration                                        : 16;
+             uint32_t obss_nav_value                                          : 16,
+                      obss_nav_update_enable                                  :  1,
+                      reserved_1a                                             :  8,
+                      eht___reserved_g_0022_ndp                                         :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t reserved_2a                                             :  6,
+                      dot11bn_su_elr                                          :  1,
+                      rx_ndp                                                  :  1,
+                      spatial_reuse                                           :  4,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      txop_duration                                           :  7,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      eht_or_uhr_ppdu_type                                    :  2;
+             uint32_t puncture_bitmap                                         : 16,
+                      sta_id                                                  : 11,
+                      doppler_indication                                      :  1,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      eht_duplicate                                           :  2;
+#endif
+};
+
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET                              0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB                                 0
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB                                 15
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK                                0x000000000000ffff
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB                                      16
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK                                     0x00000000ffff0000
+
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET               0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                  32
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                  37
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                 0x0000003f00000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB                                      39
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB                                      46
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK                                     0x00007f8000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET                        0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK                          0x0000800000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET                                0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB                                   48
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB                                   63
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK                                  0xffff000000000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET                          0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB                             0
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB                             1
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK                            0x0000000000000003
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET                                  0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB                                     2
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB                                     7
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK                                    0x00000000000000fc
+
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK                                      0x0000000000000100
+
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB                                    9
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB                                    15
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK                                   0x000000000000fe00
+
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB                                       16
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB                                       17
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK                                      0x0000000000030000
+
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET                                      0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB                                         18
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB                                         19
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK                                        0x00000000000c0000
+
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB                                    20
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB                                    23
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK                                   0x0000000000f00000
+
+#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK                                          0x0000000001000000
+
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET                                0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK                                  0x0000000002000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET                                   0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB                                      26
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK                                     0x00000000fc000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB                                    32
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB                                    33
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK                                   0x0000000300000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB                    34
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB                    35
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK                   0x0000000c00000000
+
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET                            0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK                              0x0000001000000000
+
+#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_STA_ID_LSB                                           37
+#define PHYRX_COMMON_USER_INFO_STA_ID_MSB                                           47
+#define PHYRX_COMMON_USER_INFO_STA_ID_MASK                                          0x0000ffe000000000
+
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET                               0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB                                  48
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB                                  63
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_a_mu_dl.h b/hw/fig/v1/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..da4f1691b9f7
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
+
+struct phyrx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_a_mu_ul.h b/hw/fig/v1/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..ff9cf72a7237
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
+
+struct phyrx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_a_su.h b/hw/fig/v1/phyrx_he_sig_a_su.h
new file mode 100644
index 000000000000..abca58673a90
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
+
+struct phyrx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_b1_mu.h b/hw/fig/v1/phyrx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..ae784469331b
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_b2_mu.h b/hw/fig/v1/phyrx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..6035ecffde5d
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_he_sig_b2_ofdma.h b/hw/fig/v1/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..126a9559e155
--- /dev/null
+++ b/hw/fig/v1/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_ht_sig.h b/hw/fig/v1/phyrx_ht_sig.h
new file mode 100644
index 000000000000..4dd90653d431
--- /dev/null
+++ b/hw/fig/v1/phyrx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
+
+struct phyrx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#endif
+};
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_l_sig_a.h b/hw/fig/v1/phyrx_l_sig_a.h
new file mode 100644
index 000000000000..2e70822f5d06
--- /dev/null
+++ b/hw/fig/v1/phyrx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_l_sig_b.h b/hw/fig/v1/phyrx_l_sig_b.h
new file mode 100644
index 000000000000..461edd24dd4e
--- /dev/null
+++ b/hw/fig/v1/phyrx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_location.h b/hw/fig/v1/phyrx_location.h
new file mode 100644
index 000000000000..15a8413e304a
--- /dev/null
+++ b/hw/fig/v1/phyrx_location.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_LOCATION_H_
+#define _PHYRX_LOCATION_H_
+
+#include "rx_location_info.h"
+#define NUM_OF_DWORDS_PHYRX_LOCATION 28
+
+#define NUM_OF_QWORDS_PHYRX_LOCATION 14
+
+struct phyrx_location {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_location_info                                          rx_location_info_details;
+#else
+             struct   rx_location_info                                          rx_location_info_details;
+#endif
+};
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET       0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK         0x0000000000000001
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET             0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK               0x0000000000000002
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET                   0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB                      4
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB                      7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK                     0x00000000000000f0
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET                  0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB                     8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK                    0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET            0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET              0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB                 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB                 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK                0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET     0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB        32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB        39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK       0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET    0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB       40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK      0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK                 0x00ff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB                  56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB                  63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK                 0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK   0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB    39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK   0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET                   0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB                      40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK                     0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB                  51
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK                 0x000f000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB                  52
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK                 0x00f0000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET                 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB                    56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK                   0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET          0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB             0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB             15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK            0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET            0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB                     24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK                    0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK                    0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET            0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB               0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB               31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK              0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET                    0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK                      0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK                    0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB                     16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK                    0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB                     47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK                    0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB                     48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK                    0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET           0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB              0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB              7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK             0x00000000000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET       0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB          8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB          15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK         0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET             0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB                16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB                31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK               0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET                 0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB                    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_other_receive_info_ru_details.h b/hw/fig/v1/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 000000000000..a6090f721e1d
--- /dev/null
+++ b/hw/fig/v1/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
+
+#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
+
+struct phyrx_other_receive_info_ru_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB                0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB                31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK               0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB                32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB                63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK               0xffffffff00000000
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET                            0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB                               0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB                               31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK                              0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET                    0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB                       32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB                       63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK                      0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_pkt_end.h b/hw/fig/v1/phyrx_pkt_end.h
new file mode 100644
index 000000000000..1d1675edc0e1
--- /dev/null
+++ b/hw/fig/v1/phyrx_pkt_end.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+
+#include "phyrx_pkt_end_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END 24
+
+#define NUM_OF_QWORDS_PHYRX_PKT_END 12
+
+struct phyrx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#else
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#endif
+};
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET                 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK                   0x0000000000000002
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET                   0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK                     0x0000000000000004
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET                     0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK                       0x0000000000000008
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK                           0x0000000000000010
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET            0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK              0x0000000000000020
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB                            6
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB                            7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK                           0x00000000000000c0
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET                           0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB                              8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB                              15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK                             0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB                            16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB                            31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK                           0x00000000ffff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET     0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB        54
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB        63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK       0xffc0000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET                  0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB                     0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB                     31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK                    0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET                 0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB                    32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB                    63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_pkt_end_info.h b/hw/fig/v1/phyrx_pkt_end_info.h
new file mode 100644
index 000000000000..a21edc94d24e
--- /dev/null
+++ b/hw/fig/v1/phyrx_pkt_end_info.h
@@ -0,0 +1,450 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+
+#include "receive_rssi_info.h"
+#include "rx_timing_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
+
+struct phyrx_pkt_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0001                                        :  1,
+                      location_info_valid                                     :  1,
+                      timing_info_valid                                       :  1,
+                      rssi_info_valid                                         :  1,
+                      reserved_0a                                             :  1,
+                      frameless_frame_received                                :  1,
+                      reserved_0b                                             :  2,
+                      rssi_comb                                               :  8,
+                      reserved_0c                                             : 16;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#else
+             uint32_t reserved_0c                                             : 16,
+                      rssi_comb                                               :  8,
+                      reserved_0b                                             :  2,
+                      frameless_frame_received                                :  1,
+                      reserved_0a                                             :  1,
+                      rssi_info_valid                                         :  1,
+                      timing_info_valid                                       :  1,
+                      location_info_valid                                     :  1,
+                      __reserved_g_0001                                        :  1;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#endif
+};
+
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET                               0x00000000
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK                                 0x00000002
+
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET                                 0x00000000
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK                                   0x00000004
+
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET                                   0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK                                     0x00000008
+
+#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK                                         0x00000010
+
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET                          0x00000000
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK                            0x00000020
+
+#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB                                          6
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB                                          7
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK                                         0x000000c0
+
+#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET                                         0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB                                            8
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB                                            15
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK                                           0x0000ff00
+
+#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB                                          16
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB                                          31
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK                                         0xffff0000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET   0x00000004
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET   0x00000008
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET   0x0000000c
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET   0x00000010
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET      0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB         0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB         11
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK        0x00000fff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET         0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB            12
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB            21
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK           0x003ff000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET                   0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB                      22
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB                      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK                     0xffc00000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET    0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET   0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET    0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET   0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET    0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET   0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET    0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET   0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET    0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET   0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET    0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET   0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET    0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET   0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET    0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET   0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET                                0x00000058
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB                                   0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB                                   31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK                                  0xffffffff
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET                               0x0000005c
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB                                  0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB                                  31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/fig/v1/phyrx_rssi_legacy.h b/hw/fig/v1/phyrx_rssi_legacy.h
new file mode 100644
index 000000000000..820ced6212ca
--- /dev/null
+++ b/hw/fig/v1/phyrx_rssi_legacy.h
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+
+#include "receive_rssi_info.h"
+#include "receive_pkt_start_info.h"
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
+
+#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21
+
+struct phyrx_rssi_legacy {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t rssi_comb_ppdu                                          :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_for_trigger_resp                                   :  8;
+#else
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8;
+             uint32_t rssi_for_trigger_resp                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_comb_ppdu                                          :  8;
+#endif
+};
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET                0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB                   0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB                   3
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK                  0x000000000000000f
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET            0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK              0x0000000000000010
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET             0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB                5
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x00000000000000e0
+
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET             PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK               PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK                   0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET                   0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB                      16
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB                      31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK                     0x00000000ffff0000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET     0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB        32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB        63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET    0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB       0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB       31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK      0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB         32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB         39
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK         0x0000010000000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET                   0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB                      41
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB                      63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK                     0xfffffe0000000000
+
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET                                   0x0000000000000010
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB                                      0
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB                                      31
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK                                     0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET                                        0x0000000000000010
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK                                          0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET                                      0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB                                         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB                                         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK                                        0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET                                          0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB                                             8
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB                                             15
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK                                            0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET                           0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB                              16
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB                              23
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK                             0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET                               0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB                                  24
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB                                  31
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK                                 0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET                                     0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB                                        32
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB                                        39
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK                                       0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB                                 40
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB                                 47
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK                                0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET                             0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB                                48
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB                                55
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK                               0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB                                 56
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB                                 63
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_user_info.h b/hw/fig/v1/phyrx_user_info.h
new file mode 100644
index 000000000000..d3dc8b6b2414
--- /dev/null
+++ b/hw/fig/v1/phyrx_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
+
+#define NUM_OF_QWORDS_PHYRX_USER_INFO 4
+
+struct phyrx_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB                   0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB                   15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK                  0x000000000000ffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET                  0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB                     16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB                     23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK                    0x0000000000ff0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB                      24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB                      27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK                     0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET                       0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                         0x0000000010000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB                29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB                31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK               0x00000000e0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB                      32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB                      36
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK                     0x0000001f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                           38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                          0x0000006000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB                40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB                47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK               0x0000ff0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET          0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB             48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB             50
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK            0x0007000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB                   51
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK                  0x00f8000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB           63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK          0xff00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET   0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK     0x0000000000000001
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK                  0x0000000000000002
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB                     2
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB                     3
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK                    0x000000000000000c
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB                     4
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB                     5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK                    0x0000000000000030
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB                     6
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB                     7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK                    0x00000000000000c0
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                           8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                           10
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                          0x0000000000000700
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET              0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB                 11
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB                 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK                0x0000000000003800
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET                    0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK                      0x0000000000004000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET                       0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                         0x0000000000008000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB                  16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB                  19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK                 0x00000000000f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB                  20
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB                  23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK                 0x0000000000f00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB                  24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB                  27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK                 0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB                  28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB                  31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK                 0x00000000f0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB           32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK          0x0000003f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB                   38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB                   39
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK                  0x000000c000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB           40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB           45
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK          0x00003f0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB                   46
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB                   47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK                  0x0000c00000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB           48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB           53
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK          0x003f000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB                   54
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK                  0x00c0000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB           61
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK          0x3f00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB                   62
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB                   63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK                  0xc000000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK            0xffffffff00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/phyrx_vht_sig_a.h b/hw/fig/v1/phyrx_vht_sig_a.h
new file mode 100644
index 000000000000..e47f0e35adeb
--- /dev/null
+++ b/hw/fig/v1/phyrx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
+
+struct phyrx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/phytx_abort_request_info.h b/hw/fig/v1/phytx_abort_request_info.h
new file mode 100644
index 000000000000..e4800f6a2d97
--- /dev/null
+++ b/hw/fig/v1/phytx_abort_request_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t phytx_abort_reason                                      :  8,
+                      user_number                                             :  6,
+                      reserved                                                :  2;
+#else
+             uint16_t reserved                                                :  2,
+                      user_number                                             :  6,
+                      phytx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB                             0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB                             7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET                                 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB                                    8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB                                    13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK                                   0x00003f00
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET                                    0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB                                       14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB                                       15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK                                      0x0000c000
+
+#endif
diff --git a/hw/fig/v1/phytx_pkt_end.h b/hw/fig/v1/phytx_pkt_end.h
new file mode 100644
index 000000000000..55911ea9edb3
--- /dev/null
+++ b/hw/fig/v1/phytx_pkt_end.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PKT_END_H_
+#define _PHYTX_PKT_END_H_
+
+#define NUM_OF_WORDS_PHYTX_PKT_END 28
+
+#define NUM_OF_DWORDS_PHYTX_PKT_END 14
+
+struct phytx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t tx_group_delay                                          : 12,
+                      timing_status                                           :  2,
+                      phyrx_entered_nap_state                                 :  1,
+                      dpdtrain_done                                           :  1;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t beamform_masked_user_bitmap_36_32                       :  5,
+                      reserved_23                                             : 11;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#else
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t dpdtrain_done                                           :  1,
+                      phyrx_entered_nap_state                                 :  1,
+                      timing_status                                           :  2,
+                      tx_group_delay                                          : 12;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t reserved_23                                             : 11,
+                      beamform_masked_user_bitmap_36_32                       :  5;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#endif
+};
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET                          0x00000000
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB                             0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB                             15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK                            0x0000ffff
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET                         0x00000002
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB                            0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB                            15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK                           0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET                            0x00000004
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB                               0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB                               15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK                              0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET                           0x00000006
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB                              0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB                              15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK                             0x0000ffff
+
+#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET                                         0x00000008
+#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB                                            11
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK                                           0x00000fff
+
+#define PHYTX_PKT_END_TIMING_STATUS_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_TIMING_STATUS_LSB                                             12
+#define PHYTX_PKT_END_TIMING_STATUS_MSB                                             13
+#define PHYTX_PKT_END_TIMING_STATUS_MASK                                            0x00003000
+
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET                                0x00000008
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK                                  0x00004000
+
+#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK                                            0x00008000
+
+#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET                                         0x0000000a
+#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB                                            15
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK                                           0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET                                  0x0000000c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB                                     0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB                                     15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK                                    0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET                                 0x0000000e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET                                 0x00000010
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET                                 0x00000012
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET                                0x00000014
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET                                0x00000016
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET                                0x00000018
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET                                0x0000001a
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET                                 0x0000001c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET                                0x0000001e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET                                0x00000020
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET                                0x00000022
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET                                0x00000024
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET                              0x00000026
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB                                 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB                                 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK                                0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET                             0x00000028
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET                             0x0000002a
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET                             0x0000002c
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                       0x0000002e
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                          0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                          15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                         0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                      0x00000030
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                         15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                        0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                      0x00000032
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                         4
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                        0x0000001f
+
+#define PHYTX_PKT_END_RESERVED_23_OFFSET                                            0x00000032
+#define PHYTX_PKT_END_RESERVED_23_LSB                                               5
+#define PHYTX_PKT_END_RESERVED_23_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_23_MASK                                              0x0000ffe0
+
+#define PHYTX_PKT_END_RESERVED_26_OFFSET                                            0x00000034
+#define PHYTX_PKT_END_RESERVED_26_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_26_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_26_MASK                                              0x0000ffff
+
+#define PHYTX_PKT_END_RESERVED_27_OFFSET                                            0x00000036
+#define PHYTX_PKT_END_RESERVED_27_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_27_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_27_MASK                                              0x0000ffff
+
+#endif
diff --git a/hw/fig/v1/phytx_ppdu_header_info_request.h b/hw/fig/v1/phytx_ppdu_header_info_request.h
new file mode 100644
index 000000000000..7fbecae41236
--- /dev/null
+++ b/hw/fig/v1/phytx_ppdu_header_info_request.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+
+#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
+
+#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
+
+struct phytx_ppdu_header_info_request {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t request_type                                            :  5,
+                      reserved                                                : 11;
+             uint16_t tlv32_padding                                           : 16;
+#else
+             uint16_t reserved                                                : 11,
+                      request_type                                            :  5;
+             uint16_t tlv32_padding                                           : 16;
+#endif
+};
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET                          0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB                             0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB                             4
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK                            0x0000001f
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET                              0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB                                 5
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB                                 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK                                0x0000ffe0
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET                         0x00000002
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB                            0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB                            15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK                           0x0000ffff
+
+#endif
diff --git a/hw/fig/v1/receive_pkt_start_info.h b/hw/fig/v1/receive_pkt_start_info.h
new file mode 100644
index 000000000000..7f7c81449a15
--- /dev/null
+++ b/hw/fig/v1/receive_pkt_start_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_PKT_START_INFO_H_
+#define _RECEIVE_PKT_START_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
+
+struct receive_pkt_start_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reception_type                                          :  4,
+                      rx_chain_mask_type                                      :  1,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask                                           :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t preamble_time_to_rxframe                                :  8,
+                      standalone_sniffer_mode                                 :  1,
+                      reserved_3a                                             : 23;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      rx_chain_mask                                           :  8,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask_type                                      :  1,
+                      reception_type                                          :  4;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t reserved_3a                                             : 23,
+                      standalone_sniffer_mode                                 :  1,
+                      preamble_time_to_rxframe                                :  8;
+#endif
+};
+
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET                                0x00000000
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB                                   0
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB                                   3
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK                                  0x0000000f
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET                            0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK                              0x00000010
+
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET                             0x00000000
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB                                5
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB                                7
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK                               0x000000e0
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET                                 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB                                    8
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB                                    15
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK                                   0x0000ff00
+
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET                                   0x00000000
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB                                      16
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB                                      31
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK                                     0xffff0000
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET                     0x00000004
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB                        0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB                        31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK                       0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET                    0x00000008
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB                       0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB                       31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK                      0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET                      0x0000000c
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB                         0
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB                         7
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK                        0x000000ff
+
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET                       0x0000000c
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK                         0x00000100
+
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB                                      9
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB                                      31
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK                                     0xfffffe00
+
+#endif
diff --git a/hw/fig/v1/receive_rssi_info.h b/hw/fig/v1/receive_rssi_info.h
new file mode 100644
index 000000000000..9aaa98217d99
--- /dev/null
+++ b/hw/fig/v1/receive_rssi_info.h
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_pri20_chain0                                       :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext40_high20_chain0                                :  8;
+             uint32_t rssi_ext80_low20_chain0                                 :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_high20_chain0                                :  8;
+             uint32_t rssi_ext160_0_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_3_chain0                                    :  8;
+             uint32_t rssi_ext160_4_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_7_chain0                                    :  8;
+             uint32_t rssi_pri20_chain1                                       :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext40_high20_chain1                                :  8;
+             uint32_t rssi_ext80_low20_chain1                                 :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_high20_chain1                                :  8;
+             uint32_t rssi_ext160_0_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_3_chain1                                    :  8;
+             uint32_t rssi_ext160_4_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_7_chain1                                    :  8;
+             uint32_t rssi_pri20_chain2                                       :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext40_high20_chain2                                :  8;
+             uint32_t rssi_ext80_low20_chain2                                 :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_high20_chain2                                :  8;
+             uint32_t rssi_ext160_0_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_3_chain2                                    :  8;
+             uint32_t rssi_ext160_4_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_7_chain2                                    :  8;
+             uint32_t rssi_pri20_chain3                                       :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext40_high20_chain3                                :  8;
+             uint32_t rssi_ext80_low20_chain3                                 :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_high20_chain3                                :  8;
+             uint32_t rssi_ext160_0_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_3_chain3                                    :  8;
+             uint32_t rssi_ext160_4_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_7_chain3                                    :  8;
+#else
+             uint32_t rssi_ext40_high20_chain0                                :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_pri20_chain0                                       :  8;
+             uint32_t rssi_ext80_high20_chain0                                :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_low20_chain0                                 :  8;
+             uint32_t rssi_ext160_3_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_0_chain0                                    :  8;
+             uint32_t rssi_ext160_7_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_4_chain0                                    :  8;
+             uint32_t rssi_ext40_high20_chain1                                :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_pri20_chain1                                       :  8;
+             uint32_t rssi_ext80_high20_chain1                                :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_low20_chain1                                 :  8;
+             uint32_t rssi_ext160_3_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_0_chain1                                    :  8;
+             uint32_t rssi_ext160_7_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_4_chain1                                    :  8;
+             uint32_t rssi_ext40_high20_chain2                                :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_pri20_chain2                                       :  8;
+             uint32_t rssi_ext80_high20_chain2                                :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_low20_chain2                                 :  8;
+             uint32_t rssi_ext160_3_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_0_chain2                                    :  8;
+             uint32_t rssi_ext160_7_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_4_chain2                                    :  8;
+             uint32_t rssi_ext40_high20_chain3                                :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_pri20_chain3                                       :  8;
+             uint32_t rssi_ext80_high20_chain3                                :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_low20_chain3                                 :  8;
+             uint32_t rssi_ext160_3_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_0_chain3                                    :  8;
+             uint32_t rssi_ext160_7_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_4_chain3                                    :  8;
+#endif
+};
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET                            0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET                           0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET                            0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET                           0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET                            0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET                           0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET                            0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET                           0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET                            0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET                           0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET                            0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET                           0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET                            0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET                           0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET                            0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET                           0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK                                 0xff000000
+
+#endif
diff --git a/hw/fig/v1/receive_user_info.h b/hw/fig/v1/receive_user_info.h
new file mode 100644
index 000000000000..23daabab5dc8
--- /dev/null
+++ b/hw/fig/v1/receive_user_info.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
+
+struct receive_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      stbc                                                    :  1,
+                      reception_type                                          :  3;
+             uint32_t rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      __reserved_g_0004                                          :  1,
+                      mimo_ss_bitmap                                          :  8,
+                      receive_bandwidth                                       :  3,
+                      reserved_1b                                             :  5,
+                      dl_ofdma_user_index                                     :  8;
+             uint32_t dl_ofdma_content_channel                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      sta_dcm                                                 :  1,
+                      ldpc                                                    :  1,
+                      ru_type_80_0                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_3                                            :  4;
+             uint32_t ru_start_index_80_0                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3d                                             :  2;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#else
+             uint32_t reception_type                                          :  3,
+                      stbc                                                    :  1,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t dl_ofdma_user_index                                     :  8,
+                      reserved_1b                                             :  5,
+                      receive_bandwidth                                       :  3,
+                      mimo_ss_bitmap                                          :  8,
+                      __reserved_g_0004                                          :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5;
+             uint32_t ru_type_80_3                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_0                                            :  4,
+                      ldpc                                                    :  1,
+                      sta_dcm                                                 :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      dl_ofdma_content_channel                                :  1;
+             uint32_t reserved_3d                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_0                                     :  6;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#endif
+};
+
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
+#define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
+#define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
+#define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
+
+#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
+#define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
+#define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
+#define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
+
+#define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
+#define RECEIVE_USER_INFO_STBC_LSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
+
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
+
+#define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
+#define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
+#define RECEIVE_USER_INFO_RATE_MCS_MSB                                              4
+#define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000001f
+
+#define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
+#define RECEIVE_USER_INFO_SGI_LSB                                                   5
+#define RECEIVE_USER_INFO_SGI_MSB                                                   6
+#define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000060
+
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
+
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
+
+#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
+#define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
+
+#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
+#define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x00000002
+
+#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF1_LSB                                             2
+#define RECEIVE_USER_INFO_QAM_DIFF1_MSB                                             3
+#define RECEIVE_USER_INFO_QAM_DIFF1_MASK                                            0x0000000c
+
+#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF2_LSB                                             4
+#define RECEIVE_USER_INFO_QAM_DIFF2_MSB                                             5
+#define RECEIVE_USER_INFO_QAM_DIFF2_MASK                                            0x00000030
+
+#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF3_LSB                                             6
+#define RECEIVE_USER_INFO_QAM_DIFF3_MSB                                             7
+#define RECEIVE_USER_INFO_QAM_DIFF3_MASK                                            0x000000c0
+
+#define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
+#define RECEIVE_USER_INFO_NSS_LSB                                                   8
+#define RECEIVE_USER_INFO_NSS_MSB                                                   10
+#define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
+
+#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
+#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
+
+#define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
+#define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
+
+#define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
+#define RECEIVE_USER_INFO_LDPC_LSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
+
+#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
+#define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
+
+#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
+#define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
+#define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
+
+#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
+#define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
+
+#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
+#define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
+#define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/fig/v1/received_response_user_15_8.h b/hw/fig/v1/received_response_user_15_8.h
new file mode 100644
index 000000000000..6cf8117ff02f
--- /dev/null
+++ b/hw/fig/v1/received_response_user_15_8.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_15_8_H_
+#define _RECEIVED_RESPONSE_USER_15_8_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32
+
+struct received_response_user_15_8 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#else
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET     0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET     0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET    0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET    0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET    0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET    0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET    0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET    0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/received_response_user_23_16.h b/hw/fig/v1/received_response_user_23_16.h
new file mode 100644
index 000000000000..ff56f4d96472
--- /dev/null
+++ b/hw/fig/v1/received_response_user_23_16.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_23_16_H_
+#define _RECEIVED_RESPONSE_USER_23_16_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32
+
+struct received_response_user_23_16 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#else
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/received_response_user_31_24.h b/hw/fig/v1/received_response_user_31_24.h
new file mode 100644
index 000000000000..aaa90838daa9
--- /dev/null
+++ b/hw/fig/v1/received_response_user_31_24.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_31_24_H_
+#define _RECEIVED_RESPONSE_USER_31_24_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32
+
+struct received_response_user_31_24 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#else
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/received_response_user_36_32.h b/hw/fig/v1/received_response_user_36_32.h
new file mode 100644
index 000000000000..3f33fdab635e
--- /dev/null
+++ b/hw/fig/v1/received_response_user_36_32.h
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
+#define _RECEIVED_RESPONSE_USER_36_32_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20
+
+struct received_response_user_36_32 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#else
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/received_response_user_7_0.h b/hw/fig/v1/received_response_user_7_0.h
new file mode 100644
index 000000000000..f785aca46840
--- /dev/null
+++ b/hw/fig/v1/received_response_user_7_0.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_7_0_H_
+#define _RECEIVED_RESPONSE_USER_7_0_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32
+
+struct received_response_user_7_0 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#else
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET      0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET      0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET      0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET      0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET      0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET      0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET      0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET      0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/received_response_user_info.h b/hw/fig/v1/received_response_user_info.h
new file mode 100644
index 000000000000..3c3faf119635
--- /dev/null
+++ b/hw/fig/v1/received_response_user_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_fcs_pass_count                                     : 12,
+                      mpdu_fcs_fail_count                                     : 12,
+                      qosnull_frame_count                                     :  4,
+                      reserved_0a                                             :  3,
+                      user_info_valid                                         :  1;
+             uint32_t null_delimiter_count                                    : 22,
+                      reserved_1a                                             :  9,
+                      ht_control_valid                                        :  1;
+             uint32_t ht_control                                              : 32;
+             uint32_t qos_control_valid                                       : 16,
+                      eosp                                                    : 16;
+             uint32_t qos_control_15_8_tid_0                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_3                                  :  8;
+             uint32_t qos_control_15_8_tid_4                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_7                                  :  8;
+             uint32_t qos_control_15_8_tid_8                                  :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_11                                 :  8;
+             uint32_t qos_control_15_8_tid_12                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_15                                 :  8;
+#else
+             uint32_t user_info_valid                                         :  1,
+                      reserved_0a                                             :  3,
+                      qosnull_frame_count                                     :  4,
+                      mpdu_fcs_fail_count                                     : 12,
+                      mpdu_fcs_pass_count                                     : 12;
+             uint32_t ht_control_valid                                        :  1,
+                      reserved_1a                                             :  9,
+                      null_delimiter_count                                    : 22;
+             uint32_t ht_control                                              : 32;
+             uint32_t eosp                                                    : 16,
+                      qos_control_valid                                       : 16;
+             uint32_t qos_control_15_8_tid_3                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_0                                  :  8;
+             uint32_t qos_control_15_8_tid_7                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_4                                  :  8;
+             uint32_t qos_control_15_8_tid_11                                 :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_8                                  :  8;
+             uint32_t qos_control_15_8_tid_15                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_12                                 :  8;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
+
+#endif
diff --git a/hw/fig/v1/received_trigger_info.h b/hw/fig/v1/received_trigger_info.h
new file mode 100644
index 000000000000..16d10249d075
--- /dev/null
+++ b/hw/fig/v1/received_trigger_info.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_H_
+#define _RECEIVED_TRIGGER_INFO_H_
+
+#include "received_trigger_info_details.h"
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
+
+#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
+
+struct received_trigger_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_trigger_info_details                             received_trigger_details;
+#else
+             struct   received_trigger_info_details                             received_trigger_details;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET          0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB             0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB             3
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK            0x000000000000000f
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK       0x0000000000000010
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB          5
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB          8
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK         0x00000000000001e0
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET   0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK     0x0000000000400000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK       0x0000000000800000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK   0x0000000001000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB        29
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB        30
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK       0x0000000060000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB              32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB              47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK             0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET  0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB     48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB     59
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK    0x0fff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK             0x2000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK         0x4000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK             0x8000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET         0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB            0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB            15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK           0x000000000000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB              16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK             0x00000000ffff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET            0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB               32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB               47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK              0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK             0xe000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET            0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB               0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB               31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK              0x00000000ffffffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET           0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB              40
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK             0xffffff0000000000
+
+#endif
diff --git a/hw/fig/v1/received_trigger_info_details.h b/hw/fig/v1/received_trigger_info_details.h
new file mode 100644
index 000000000000..ebffe439b3b2
--- /dev/null
+++ b/hw/fig/v1/received_trigger_info_details.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t trigger_type                                            :  4,
+                      ax_trigger_source                                       :  1,
+                      ax_trigger_type                                         :  4,
+                      trigger_source_sta_full_aid                             : 13,
+                      frame_control_valid                                     :  1,
+                      qos_control_valid                                       :  1,
+                      he_control_info_valid                                   :  1,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      txop_sharing_mode                                       :  2,
+                      tid_aggregation_limit_is_zero                           :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      lsig_response_length                                    : 12,
+                      __reserved_g_0035                                                 :  1,
+                      scsid_valid                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_1a                                             :  1;
+             uint32_t frame_control                                           : 16,
+                      qos_control                                             : 16;
+             uint32_t sw_peer_id                                              : 16,
+                      txop_sharing_allocation_duration                        :  9,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      reserved_3a                                             :  3;
+             uint32_t he_control                                              : 32;
+             uint32_t txop_sharing_duration_from_durid                        :  1,
+                      frame_durationid_lower_4                                :  4,
+                      frame_durationid_upper_3                                :  3,
+                      reserved_5a                                             : 24;
+#else
+             uint32_t tid_aggregation_limit_is_zero                           :  1,
+                      txop_sharing_mode                                       :  2,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      he_control_info_valid                                   :  1,
+                      qos_control_valid                                       :  1,
+                      frame_control_valid                                     :  1,
+                      trigger_source_sta_full_aid                             : 13,
+                      ax_trigger_type                                         :  4,
+                      ax_trigger_source                                       :  1,
+                      trigger_type                                            :  4;
+             uint32_t reserved_1a                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      scsid_valid                                             :  1,
+                      __reserved_g_0035                                                 :  1,
+                      lsig_response_length                                    : 12,
+                      phy_ppdu_id                                             : 16;
+             uint32_t qos_control                                             : 16,
+                      frame_control                                           : 16;
+             uint32_t reserved_3a                                             :  3,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      txop_sharing_allocation_duration                        :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t he_control                                              : 32;
+             uint32_t reserved_5a                                             : 24,
+                      frame_durationid_upper_3                                :  3,
+                      frame_durationid_lower_4                                :  4,
+                      txop_sharing_duration_from_durid                        :  1;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET                           0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB                              0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB                              3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK                             0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK                        0x00000010
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET                        0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB                           5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB                           8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK                          0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB               9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB               21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK              0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET                    0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK                      0x00400000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK                        0x00800000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET                  0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK                    0x01000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB                         29
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB                         30
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK                        0x60000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET          0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK            0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB                               0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB                               15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK                              0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                   0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB                      16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB                      27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK                     0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK                              0x20000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET                        0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK                          0x40000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK                              0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET                          0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB                             0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB                             15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK                            0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET                            0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK                              0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET                             0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB                                15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK                               0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET       0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB          16
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB          24
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK         0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET                            0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK                              0xe0000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET                             0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB                                31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK                               0xffffffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET       0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK         0x00000001
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB                  1
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB                  4
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK                 0x0000001e
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB                  5
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB                  7
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK                 0x000000e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET                            0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB                               8
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK                              0xffffff00
+
+#endif
diff --git a/hw/fig/v1/reo_descriptor_threshold_reached_status.h b/hw/fig/v1/reo_descriptor_threshold_reached_status.h
new file mode 100644
index 000000000000..4e0343e64182
--- /dev/null
+++ b/hw/fig/v1/reo_descriptor_threshold_reached_status.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
+
+#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
+
+struct reo_descriptor_threshold_reached_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t threshold_index                                         :  2,
+                      reserved_2                                              : 30;
+             uint32_t link_descriptor_counter0                                : 24,
+                      reserved_3                                              :  8;
+             uint32_t link_descriptor_counter1                                : 24,
+                      reserved_4                                              :  8;
+             uint32_t link_descriptor_counter2                                : 24,
+                      reserved_5                                              :  8;
+             uint32_t link_descriptor_counter_sum                             : 26,
+                      reserved_6                                              :  6;
+             uint32_t reserved_7                                              : 32;
+             uint32_t reserved_8                                              : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2                                              : 30,
+                      threshold_index                                         :  2;
+             uint32_t reserved_3                                              :  8,
+                      link_descriptor_counter0                                : 24;
+             uint32_t reserved_4                                              :  8,
+                      link_descriptor_counter1                                : 24;
+             uint32_t reserved_5                                              :  8,
+                      link_descriptor_counter2                                : 24;
+             uint32_t reserved_6                                              :  6,
+                      link_descriptor_counter_sum                             : 26;
+             uint32_t reserved_7                                              : 32;
+             uint32_t reserved_8                                              : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET    0x0000000000000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB       28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB       31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK      0x00000000f0000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET      0x0000000000000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB         32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB         63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET              0x0000000000000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB                 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB                 1
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK                0x0000000000000003
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET                   0x0000000000000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB                      2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK                     0x00000000fffffffc
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET     0x0000000000000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB        32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB        55
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK       0x00ffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET                   0x0000000000000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB                      56
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB                      63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK                     0xff00000000000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET     0x0000000000000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB        0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB        23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK       0x0000000000ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET                   0x0000000000000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB                      24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK                     0x00000000ff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET     0x0000000000000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB        32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB        55
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK       0x00ffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET                   0x0000000000000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB                      56
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB                      63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK                     0xff00000000000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET  0x0000000000000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB     25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK    0x0000000003ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET                   0x0000000000000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB                      26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK                     0x00000000fc000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET                   0x0000000000000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB                      32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB                      63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK                     0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET                   0x0000000000000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB                      0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK                     0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET                  0x0000000000000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB                     32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB                     63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK                    0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET                 0x0000000000000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET                 0x0000000000000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET                 0x0000000000000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET                 0x0000000000000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET                 0x0000000000000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET                 0x0000000000000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET                 0x0000000000000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET                 0x0000000000000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET                 0x0000000000000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET                 0x0000000000000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET                 0x0000000000000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET                 0x0000000000000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET                 0x0000000000000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET                 0x0000000000000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB                    63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK                   0xffffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET                 0x0000000000000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK                   0x00000000ffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET                 0x0000000000000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB                    32
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB                    59
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK                   0x0fffffff00000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET                0x0000000000000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB                   60
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB                   63
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK                  0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_destination_ring.h b/hw/fig/v1/reo_destination_ring.h
new file mode 100644
index 000000000000..5147635121c1
--- /dev/null
+++ b/hw/fig/v1/reo_destination_ring.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
+
+struct reo_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB               0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB               7
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK              0x000000ff
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET         0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK           0x00000100
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET        0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK          0x00000200
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK              0x00000400
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET             0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK               0x00000800
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                0x00002000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET    0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK      0x00004000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                 15
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                 26
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                0x07ff8000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK  0x08000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                   0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                      28
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                      31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                     0xf0000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET        0x0000000c
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB           0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB           31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK          0xffffffff
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET                           0x00000014
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB                              0
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB                              2
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK                             0x00000007
+
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK                          0x00000008
+
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET                               0x00000014
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB                                  4
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB                                  5
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK                                 0x00000030
+
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB                                   6
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB                                   10
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK                                  0x000007c0
+
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK                                  0x00000800
+
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB                                   12
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB                                   31
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK                                  0xfffff000
+
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET                            0x00000018
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB                               0
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB                               3
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK                              0x0000000f
+
+#define REO_DESTINATION_RING_RESERVED_6A_OFFSET                                     0x00000018
+#define REO_DESTINATION_RING_RESERVED_6A_LSB                                        4
+#define REO_DESTINATION_RING_RESERVED_6A_MSB                                        31
+#define REO_DESTINATION_RING_RESERVED_6A_MASK                                       0xfffffff0
+
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK                              0x00000001
+
+#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB                                    1
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB                                    2
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK                                   0x00000006
+
+#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET                                  0x0000001c
+#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB                                     3
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB                                     7
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK                                    0x000000f8
+
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB                            8
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB                            11
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK                           0x00000f00
+
+#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET                                    0x0000001c
+#define REO_DESTINATION_RING_SW_EXCEPTION_LSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MASK                                      0x00001000
+
+#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET                                     0x0000001c
+#define REO_DESTINATION_RING_SRC_LINK_ID_LSB                                        13
+#define REO_DESTINATION_RING_SRC_LINK_ID_MSB                                        15
+#define REO_DESTINATION_RING_SRC_LINK_ID_MASK                                       0x0000e000
+
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB                   16
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB                   19
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK                  0x000f0000
+
+#define REO_DESTINATION_RING_RING_ID_OFFSET                                         0x0000001c
+#define REO_DESTINATION_RING_RING_ID_LSB                                            20
+#define REO_DESTINATION_RING_RING_ID_MSB                                            27
+#define REO_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
+
+#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000001c
+#define REO_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define REO_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define REO_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/fig/v1/reo_destination_ring_with_pn.h b/hw/fig/v1/reo_destination_ring_with_pn.h
new file mode 100644
index 000000000000..b486a8658388
--- /dev/null
+++ b/hw/fig/v1/reo_destination_ring_with_pn.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_WITH_PN_H_
+#define _REO_DESTINATION_RING_WITH_PN_H_
+
+#include "rx_msdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
+
+struct reo_destination_ring_with_pn {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t msdu_count                                              :  8,
+                      prev_pn_23_0                                            : 24;
+             uint32_t prev_pn_47_24                                           : 24,
+                      prev_pn_127_48_info                                     :  2,
+                      reserved_3a                                             :  6;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t prev_pn_23_0                                            : 24,
+                      msdu_count                                              :  8;
+             uint32_t reserved_3a                                             :  6,
+                      prev_pn_127_48_info                                     :  2,
+                      prev_pn_47_24                                           : 24;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET                              0x00000008
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB                                 0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB                                 7
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK                                0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET                            0x00000008
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB                               8
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB                               31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK                              0xffffff00
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET                           0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB                              0
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB                              23
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK                             0x00ffffff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET                     0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB                        24
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB                        25
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK                       0x03000000
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET                             0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB                                26
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK                               0xfc000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB      3
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB      16
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK     0x0001fff8
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK       0x00020000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK     0x00040000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK     0x00080000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET    0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK      0x00100000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK  0x00800000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK           0x01000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK           0x02000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK       0x04000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB     27
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB     28
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK    0x18000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB     29
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB     30
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK    0x60000000
+
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET                   0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB                      0
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB                      2
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK                     0x00000007
+
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET                0x00000014
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK                  0x00000008
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET                       0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB                          4
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB                          5
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK                         0x00000030
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB                           6
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB                           10
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK                          0x000007c0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK                          0x00000800
+
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB                           12
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB                           31
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET                    0x00000018
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB                       3
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK                      0x0000000f
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET                             0x00000018
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB                                4
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK                               0xfffffff0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET                    0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK                      0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB                            1
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB                            2
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK                           0x00000006
+
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET                          0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB                             3
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB                             7
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK                            0x000000f8
+
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB                    8
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB                    11
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK                   0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK                              0x00001000
+
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET                             0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB                                13
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB                                15
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK                               0x0000e000
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET        0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB           16
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB           19
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK          0x000f0000
+
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB                                    20
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB                                    27
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK                                   0x0ff00000
+
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET                           0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB                              28
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB                              31
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif
diff --git a/hw/fig/v1/reo_entrance_ring.h b/hw/fig/v1/reo_entrance_ring.h
new file mode 100644
index 000000000000..800244f712be
--- /dev/null
+++ b/hw/fig/v1/reo_entrance_ring.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+
+#include "rx_mpdu_details.h"
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 16
+
+struct reo_entrance_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reo_destination_indication                              :  5,
+                      frameless_bar                                           :  1,
+                      reserved_7a                                             :  4;
+             uint32_t rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      mpdu_fragment_number                                    :  4,
+                      sw_exception                                            :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_destination_ring                           :  5,
+                      mpdu_sequence_number                                    : 12,
+                      no_ack                                                  :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      src_link_id                                             :  3,
+                      reserved_9a                                             : 13;
+             uint32_t receive_queue_number                                    : 16,
+                      fw_reorder_push_reason                                  :  2,
+                      fw_reorder_error_code                                   :  5,
+                      reserved_10a                                            :  9;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_7a                                             :  4,
+                      frameless_bar                                           :  1,
+                      reo_destination_indication                              :  5,
+                      rounded_mpdu_byte_count                                 : 14,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t no_ack                                                  :  1,
+                      mpdu_sequence_number                                    : 12,
+                      sw_exception_destination_ring                           :  5,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception                                            :  1,
+                      mpdu_fragment_number                                    :  4,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2;
+             uint32_t reserved_9a                                             : 13,
+                      src_link_id                                             :  3,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_10a                                            :  9,
+                      fw_reorder_error_code                                   :  5,
+                      fw_reorder_push_reason                                  :  2,
+                      receive_queue_number                                    : 16;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            : 20;
+#endif
+};
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                        0x00000018
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                           0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                           31
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                          0xffffffff
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                          0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                          7
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                         0x000000ff
+
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET                            0x0000001c
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB                               8
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB                               21
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK                              0x003fff00
+
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET                         0x0000001c
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB                            22
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB                            26
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK                           0x07c00000
+
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET                                      0x0000001c
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK                                        0x08000000
+
+#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7A_LSB                                           28
+#define REO_ENTRANCE_RING_RESERVED_7A_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_7A_MASK                                          0xf0000000
+
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET                                  0x00000020
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB                                     0
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB                                     1
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK                                    0x00000003
+
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET                                   0x00000020
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB                                      2
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB                                      6
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK                                     0x0000007c
+
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB                                  7
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB                                  10
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK                                 0x00000780
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET                                       0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK                                         0x00000800
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET                           0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK                             0x00001000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET                0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK                  0x00002000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET                      0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB                         14
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB                         18
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK                        0x0007c000
+
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB                                  19
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB                                  30
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK                                 0x7ff80000
+
+#define REO_ENTRANCE_RING_NO_ACK_OFFSET                                             0x00000020
+#define REO_ENTRANCE_RING_NO_ACK_LSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MASK                                               0x80000000
+
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB                                           0
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB                                           15
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB                                           16
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB                                           18
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK                                          0x00070000
+
+#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_RESERVED_9A_LSB                                           19
+#define REO_ENTRANCE_RING_RESERVED_9A_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_9A_MASK                                          0xfff80000
+
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET                               0x00000028
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB                                  0
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB                                  15
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK                                 0x0000ffff
+
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET                             0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB                                16
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB                                17
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK                               0x00030000
+
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET                              0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB                                 18
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB                                 22
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK                                0x007c0000
+
+#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET                                       0x00000028
+#define REO_ENTRANCE_RING_RESERVED_10A_LSB                                          23
+#define REO_ENTRANCE_RING_RESERVED_10A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_10A_MASK                                         0xff800000
+
+#define REO_ENTRANCE_RING_RESERVED_11A_OFFSET                                       0x0000002c
+#define REO_ENTRANCE_RING_RESERVED_11A_LSB                                          0
+#define REO_ENTRANCE_RING_RESERVED_11A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_11A_MASK                                         0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_12A_OFFSET                                       0x00000030
+#define REO_ENTRANCE_RING_RESERVED_12A_LSB                                          0
+#define REO_ENTRANCE_RING_RESERVED_12A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_12A_MASK                                         0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_13A_OFFSET                                       0x00000034
+#define REO_ENTRANCE_RING_RESERVED_13A_LSB                                          0
+#define REO_ENTRANCE_RING_RESERVED_13A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_13A_MASK                                         0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_14A_OFFSET                                       0x00000038
+#define REO_ENTRANCE_RING_RESERVED_14A_LSB                                          0
+#define REO_ENTRANCE_RING_RESERVED_14A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_14A_MASK                                         0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET                                       0x0000003c
+#define REO_ENTRANCE_RING_RESERVED_15A_LSB                                          0
+#define REO_ENTRANCE_RING_RESERVED_15A_MSB                                          19
+#define REO_ENTRANCE_RING_RESERVED_15A_MASK                                         0x000fffff
+
+#define REO_ENTRANCE_RING_RING_ID_OFFSET                                            0x0000003c
+#define REO_ENTRANCE_RING_RING_ID_LSB                                               20
+#define REO_ENTRANCE_RING_RING_ID_MSB                                               27
+#define REO_ENTRANCE_RING_RING_ID_MASK                                              0x0ff00000
+
+#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET                                      0x0000003c
+#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB                                         28
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB                                         31
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK                                        0xf0000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_cache.h b/hw/fig/v1/reo_flush_cache.h
new file mode 100644
index 000000000000..ef5713f527aa
--- /dev/null
+++ b/hw/fig/v1/reo_flush_cache.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
+
+#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
+
+struct reo_flush_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_addr_31_0                                         : 32;
+             uint32_t flush_addr_39_32                                        :  8,
+                      forward_all_mpdus_in_queue                              :  1,
+                      release_cache_block_index                               :  1,
+                      cache_block_resource_index                              :  2,
+                      flush_without_invalidate                                :  1,
+                      block_cache_usage_after_flush                           :  1,
+                      flush_entire_cache                                      :  1,
+                      flush_queue_1k_desc                                     :  1,
+                      reserved_2b                                             : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_addr_31_0                                         : 32;
+             uint32_t reserved_2b                                             : 16,
+                      flush_queue_1k_desc                                     :  1,
+                      flush_entire_cache                                      :  1,
+                      block_cache_usage_after_flush                           :  1,
+                      flush_without_invalidate                                :  1,
+                      cache_block_resource_index                              :  2,
+                      release_cache_block_index                               :  1,
+                      forward_all_mpdus_in_queue                              :  1,
+                      flush_addr_39_32                                        :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
+
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB                                  17
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB                                  31
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET                                      0x0000000000000000
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB                                         32
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB                                         63
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK                                        0xffffffff00000000
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET                                     0x0000000000000008
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB                                        0
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB                                        7
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK                                       0x00000000000000ff
+
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET                           0x0000000000000008
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB                              8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB                              8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK                             0x0000000000000100
+
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET                            0x0000000000000008
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB                               9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB                               9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK                              0x0000000000000200
+
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                           0x0000000000000008
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                              10
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                              11
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                             0x0000000000000c00
+
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET                             0x0000000000000008
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB                                12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB                                12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK                               0x0000000000001000
+
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET                        0x0000000000000008
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB                           13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB                           13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK                          0x0000000000002000
+
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB                                      14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB                                      14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK                                     0x0000000000004000
+
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET                                  0x0000000000000008
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB                                     15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB                                     15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK                                    0x0000000000008000
+
+#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET                                          0x0000000000000008
+#define REO_FLUSH_CACHE_RESERVED_2B_LSB                                             16
+#define REO_FLUSH_CACHE_RESERVED_2B_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_2B_MASK                                            0x00000000ffff0000
+
+#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET                                          0x0000000000000008
+#define REO_FLUSH_CACHE_RESERVED_3A_LSB                                             32
+#define REO_FLUSH_CACHE_RESERVED_3A_MSB                                             63
+#define REO_FLUSH_CACHE_RESERVED_3A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET                                          0x0000000000000010
+#define REO_FLUSH_CACHE_RESERVED_4A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_4A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_4A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET                                          0x0000000000000010
+#define REO_FLUSH_CACHE_RESERVED_5A_LSB                                             32
+#define REO_FLUSH_CACHE_RESERVED_5A_MSB                                             63
+#define REO_FLUSH_CACHE_RESERVED_5A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET                                          0x0000000000000018
+#define REO_FLUSH_CACHE_RESERVED_6A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_6A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_6A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET                                          0x0000000000000018
+#define REO_FLUSH_CACHE_RESERVED_7A_LSB                                             32
+#define REO_FLUSH_CACHE_RESERVED_7A_MSB                                             63
+#define REO_FLUSH_CACHE_RESERVED_7A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET                                          0x0000000000000020
+#define REO_FLUSH_CACHE_RESERVED_8A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_8A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_8A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET                                        0x0000000000000020
+#define REO_FLUSH_CACHE_TLV64_PADDING_LSB                                           32
+#define REO_FLUSH_CACHE_TLV64_PADDING_MSB                                           63
+#define REO_FLUSH_CACHE_TLV64_PADDING_MASK                                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_cache_status.h b/hw/fig/v1/reo_flush_cache_status.h
new file mode 100644
index 000000000000..f39e49257a30
--- /dev/null
+++ b/hw/fig/v1/reo_flush_cache_status.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
+
+#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
+
+struct reo_flush_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      block_error_details                                     :  2,
+                      reserved_2a                                             :  5,
+                      cache_controller_flush_status_hit                       :  1,
+                      cache_controller_flush_status_desc_type                 :  3,
+                      cache_controller_flush_status_client_id                 :  4,
+                      cache_controller_flush_status_error                     :  2,
+                      cache_controller_flush_count                            :  8,
+                      flush_queue_1k_desc                                     :  1,
+                      reserved_2b                                             :  5;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2b                                             :  5,
+                      flush_queue_1k_desc                                     :  1,
+                      cache_controller_flush_count                            :  8,
+                      cache_controller_flush_status_error                     :  2,
+                      cache_controller_flush_status_client_id                 :  4,
+                      cache_controller_flush_status_desc_type                 :  3,
+                      cache_controller_flush_status_hit                       :  1,
+                      reserved_2a                                             :  5,
+                      block_error_details                                     :  2,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x0000000000000000
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x000000000000ffff
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x0000000000000000
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x0000000003ff0000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x0000000000000000
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x000000000c000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x0000000000000000
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0x00000000f0000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x0000000000000000
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          32
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          63
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB                                   0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB                                   0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK                                  0x0000000000000001
+
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET                           0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB                              1
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB                              2
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK                             0x0000000000000006
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB                                      3
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB                                      7
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK                                     0x00000000000000f8
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET             0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB                8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB                8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK               0x0000000000000100
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET       0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB          9
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB          11
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK         0x0000000000000e00
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET       0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB          12
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB          15
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK         0x000000000000f000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET           0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB              16
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB              17
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK             0x0000000000030000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET                  0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB                     18
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB                     25
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK                    0x0000000003fc0000
+
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET                           0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB                              26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB                              26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK                             0x0000000004000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB                                      27
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK                                     0x00000000f8000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB                                      32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB                                      63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB                                      32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB                                      63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB                                      32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB                                      63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET                                   0x0000000000000020
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET                                   0x0000000000000020
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB                                      32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB                                      63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET                                  0x0000000000000028
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET                                  0x0000000000000028
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET                                  0x0000000000000030
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET                                  0x0000000000000030
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET                                  0x0000000000000038
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET                                  0x0000000000000038
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET                                  0x0000000000000040
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET                                  0x0000000000000040
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET                                  0x0000000000000048
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET                                  0x0000000000000048
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET                                  0x0000000000000050
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET                                  0x0000000000000050
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET                                  0x0000000000000058
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET                                  0x0000000000000058
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB                                     63
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET                                  0x0000000000000060
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET                                  0x0000000000000060
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB                                     32
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB                                     59
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK                                    0x0fffffff00000000
+
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET                                 0x0000000000000060
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB                                    60
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB                                    63
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK                                   0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_queue.h b/hw/fig/v1/reo_flush_queue.h
new file mode 100644
index 000000000000..cf6c108d2cb7
--- /dev/null
+++ b/hw/fig/v1/reo_flush_queue.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
+
+#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
+
+struct reo_flush_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_desc_addr_31_0                                    : 32;
+             uint32_t flush_desc_addr_39_32                                   :  8,
+                      block_desc_addr_usage_after_flush                       :  1,
+                      block_resource_index                                    :  2,
+                      reserved_2a                                             : 21;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_desc_addr_31_0                                    : 32;
+             uint32_t reserved_2a                                             : 21,
+                      block_resource_index                                    :  2,
+                      block_desc_addr_usage_after_flush                       :  1,
+                      flush_desc_addr_39_32                                   :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x0000000000000000
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    32
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    63
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x0000000000000008
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x00000000000000ff
+
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x0000000000000008
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x0000000000000100
+
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x0000000000000008
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x0000000000000600
+
+#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x0000000000000008
+#define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
+#define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0x00000000fffff800
+
+#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000000000008
+#define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             32
+#define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             63
+#define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x0000000000000010
+#define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x0000000000000010
+#define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             32
+#define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             63
+#define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x0000000000000018
+#define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000000000000018
+#define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             32
+#define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             63
+#define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x0000000000000020
+#define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET                                        0x0000000000000020
+#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB                                           32
+#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB                                           63
+#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK                                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_queue_status.h b/hw/fig/v1/reo_flush_queue_status.h
new file mode 100644
index 000000000000..7f41cef1aee7
--- /dev/null
+++ b/hw/fig/v1/reo_flush_queue_status.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
+
+#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
+
+struct reo_flush_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      reserved_2a                                             : 31;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 31,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x0000000000000000
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x000000000000ffff
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x0000000000000000
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x0000000003ff0000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x0000000000000000
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x000000000c000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x0000000000000000
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0x00000000f0000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x0000000000000000
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          32
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          63
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000000000008
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB                                   0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB                                   0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK                                  0x0000000000000001
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB                                      1
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK                                     0x00000000fffffffe
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB                                      32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB                                      63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB                                      32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB                                      63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB                                      32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB                                      63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET                                   0x0000000000000020
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET                                   0x0000000000000020
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB                                      32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB                                      63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET                                  0x0000000000000028
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET                                  0x0000000000000028
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET                                  0x0000000000000030
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET                                  0x0000000000000030
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET                                  0x0000000000000038
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET                                  0x0000000000000038
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET                                  0x0000000000000040
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET                                  0x0000000000000040
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET                                  0x0000000000000048
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET                                  0x0000000000000048
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET                                  0x0000000000000050
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET                                  0x0000000000000050
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET                                  0x0000000000000058
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET                                  0x0000000000000058
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB                                     63
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK                                    0xffffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET                                  0x0000000000000060
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK                                    0x00000000ffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET                                  0x0000000000000060
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB                                     32
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB                                     59
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK                                    0x0fffffff00000000
+
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET                                 0x0000000000000060
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB                                    60
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB                                    63
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK                                   0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_timeout_list.h b/hw/fig/v1/reo_flush_timeout_list.h
new file mode 100644
index 000000000000..e978152f4ca4
--- /dev/null
+++ b/hw/fig/v1/reo_flush_timeout_list.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
+
+#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
+
+struct reo_flush_timeout_list {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t ac_timout_list                                          :  2,
+                      reserved_1                                              : 30;
+             uint32_t minimum_release_desc_count                              : 16,
+                      minimum_forward_buf_count                               : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t reserved_1                                              : 30,
+                      ac_timout_list                                          :  2;
+             uint32_t minimum_forward_buf_count                               : 16,
+                      minimum_release_desc_count                              : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET                     0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB                        0
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB                        15
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK                       0x000000000000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB                   16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB                   16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK                  0x0000000000010000
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET                        0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB                           17
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB                           31
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK                          0x00000000fffe0000
+
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET                                0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB                                   32
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB                                   33
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK                                  0x0000000300000000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET                                    0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB                                       34
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB                                       63
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK                                      0xfffffffc00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET                    0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB                       0
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB                       15
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK                      0x000000000000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET                     0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB                        16
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB                        31
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK                       0x00000000ffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB                                      32
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB                                      63
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET                                   0x0000000000000010
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB                                      32
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB                                      63
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET                                   0x0000000000000018
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB                                      32
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB                                      63
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK                                     0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET                                   0x0000000000000020
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK                                     0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET                                 0x0000000000000020
+#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB                                    32
+#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB                                    63
+#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK                                   0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_flush_timeout_list_status.h b/hw/fig/v1/reo_flush_timeout_list_status.h
new file mode 100644
index 000000000000..1827d9c8cc87
--- /dev/null
+++ b/hw/fig/v1/reo_flush_timeout_list_status.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26
+
+#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13
+
+struct reo_flush_timeout_list_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      timout_list_empty                                       :  1,
+                      reserved_2a                                             : 30;
+             uint32_t release_desc_count                                      : 16,
+                      forward_buf_count                                       : 16;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 30,
+                      timout_list_empty                                       :  1,
+                      error_detected                                          :  1;
+             uint32_t forward_buf_count                                       : 16,
+                      release_desc_count                                      : 16;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET        0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB           0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB           15
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK          0x000000000000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET       0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB          16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB          25
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK         0x0000000003ff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB    26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB    27
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK   0x000000000c000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET              0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB                 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB                 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK                0x00000000f0000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                0x0000000000000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB                   32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB                   63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK                  0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET                         0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB                            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB                            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK                           0x0000000000000001
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET                      0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB                         1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB                         1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK                        0x0000000000000002
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET                            0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB                               2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK                              0x00000000fffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET                     0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB                        32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB                        47
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK                       0x0000ffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET                      0x0000000000000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB                         48
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB                         63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK                        0xffff000000000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET                            0x0000000000000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK                              0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET                            0x0000000000000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB                               32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB                               63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK                              0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET                            0x0000000000000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK                              0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET                            0x0000000000000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB                               32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB                               63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK                              0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET                            0x0000000000000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK                              0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET                            0x0000000000000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB                               32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB                               63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK                              0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET                           0x0000000000000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET                           0x0000000000000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET                           0x0000000000000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET                           0x0000000000000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET                           0x0000000000000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET                           0x0000000000000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET                           0x0000000000000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET                           0x0000000000000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET                           0x0000000000000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET                           0x0000000000000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET                           0x0000000000000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET                           0x0000000000000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET                           0x0000000000000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET                           0x0000000000000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB                              63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK                             0xffffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET                           0x0000000000000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK                             0x00000000ffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET                           0x0000000000000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB                              32
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB                              59
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK                             0x0fffffff00000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET                          0x0000000000000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB                             60
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB                             63
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK                            0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_get_queue_stats.h b/hw/fig/v1/reo_get_queue_stats.h
new file mode 100644
index 000000000000..a2dbf08defeb
--- /dev/null
+++ b/hw/fig/v1/reo_get_queue_stats.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10
+
+#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5
+
+struct reo_get_queue_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      clear_stats                                             :  1,
+                      reserved_2a                                             : 23;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             : 23,
+                      clear_stats                                             :  1,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET                        0x0000000000000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB                           0
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB                           15
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK                          0x000000000000ffff
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                   0x0000000000000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB                      16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB                      16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK                     0x0000000000010000
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET                           0x0000000000000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB                              17
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB                              31
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK                             0x00000000fffe0000
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                      0x0000000000000000
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                         32
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                         63
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                        0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                     0x0000000000000008
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                        0
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                        7
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                       0x00000000000000ff
+
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET                                      0x0000000000000008
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB                                         8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB                                         8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK                                        0x0000000000000100
+
+#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET                                      0x0000000000000008
+#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB                                         9
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK                                        0x00000000fffffe00
+
+#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET                                      0x0000000000000008
+#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB                                         32
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB                                         63
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK                                        0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET                                      0x0000000000000010
+#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK                                        0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET                                      0x0000000000000010
+#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB                                         32
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB                                         63
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK                                        0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET                                      0x0000000000000018
+#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK                                        0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET                                      0x0000000000000018
+#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB                                         32
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB                                         63
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK                                        0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET                                      0x0000000000000020
+#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK                                        0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET                                    0x0000000000000020
+#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB                                       32
+#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB                                       63
+#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK                                      0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_get_queue_stats_status.h b/hw/fig/v1/reo_get_queue_stats_status.h
new file mode 100644
index 000000000000..6f47064c717a
--- /dev/null
+++ b/hw/fig/v1/reo_get_queue_stats_status.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26
+
+#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13
+
+struct reo_get_queue_stats_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t ssn                                                     : 12,
+                      current_index                                           : 10,
+                      reserved_2                                              : 10;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_mpdu_count                                      :  7,
+                      current_msdu_count                                      : 25;
+             uint32_t window_jump_2k                                          :  4,
+                      timeout_count                                           :  6,
+                      forward_due_to_bar_count                                :  6,
+                      duplicate_count                                         : 16;
+             uint32_t frames_in_order_count                                   : 24,
+                      bar_received_count                                      :  8;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t late_receive_mpdu_count                                 : 12,
+                      hole_count                                              : 16,
+                      get_queue_1k_stats_status_to_follow                     :  1,
+                      reserved_24a                                            :  3;
+             uint32_t aging_drop_mpdu_count                                   : 16,
+                      aging_drop_interval                                     :  8,
+                      reserved_25a                                            :  4,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2                                              : 10,
+                      current_index                                           : 10,
+                      ssn                                                     : 12;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_msdu_count                                      : 25,
+                      current_mpdu_count                                      :  7;
+             uint32_t duplicate_count                                         : 16,
+                      forward_due_to_bar_count                                :  6,
+                      timeout_count                                           :  6,
+                      window_jump_2k                                          :  4;
+             uint32_t bar_received_count                                      :  8,
+                      frames_in_order_count                                   : 24;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t reserved_24a                                            :  3,
+                      get_queue_1k_stats_status_to_follow                     :  1,
+                      hole_count                                              : 16,
+                      late_receive_mpdu_count                                 : 12;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            :  4,
+                      aging_drop_interval                                     :  8,
+                      aging_drop_mpdu_count                                   : 16;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET           0x0000000000000000
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB              0
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB              15
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK             0x000000000000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET          0x0000000000000000
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB             16
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB             25
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK            0x0000000003ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET    0x0000000000000000
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB       26
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB       27
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK      0x000000000c000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                 0x0000000000000000
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB                    28
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB                    31
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK                   0x00000000f0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                   0x0000000000000000
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB                      32
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB                      63
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK                     0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET                                       0x0000000000000008
+#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB                                          0
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB                                          11
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK                                         0x0000000000000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET                             0x0000000000000008
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB                                12
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB                                21
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK                               0x00000000003ff000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET                                0x0000000000000008
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB                                   22
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB                                   31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK                                  0x00000000ffc00000
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET                                   0x0000000000000008
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB                                      32
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB                                      63
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK                                     0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET                                  0x0000000000000010
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB                                     0
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB                                     31
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK                                    0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET                                  0x0000000000000010
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB                                     32
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB                                     63
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK                                    0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET                                 0x0000000000000018
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB                                    0
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB                                    31
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK                                   0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                 0x0000000000000018
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB                    32
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB                    63
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK                   0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                 0x0000000000000020
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB                    31
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK                   0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET                            0x0000000000000020
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB                               32
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB                               63
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK                              0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET                           0x0000000000000028
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB                              0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB                              31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK                             0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET                           0x0000000000000028
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB                              32
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB                              63
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK                             0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET                          0x0000000000000030
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB                             0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB                             31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK                            0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET                         0x0000000000000030
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB                            32
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB                            63
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK                           0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET                         0x0000000000000038
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK                           0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET                         0x0000000000000038
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB                            32
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB                            63
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK                           0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET                         0x0000000000000040
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK                           0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET                         0x0000000000000040
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB                            32
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB                            63
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK                           0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET                        0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB                           0
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB                           6
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK                          0x000000000000007f
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET                        0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB                           7
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB                           31
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK                          0x00000000ffffff80
+
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET                            0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB                               32
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB                               35
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK                              0x0000000f00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET                             0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB                                36
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB                                41
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK                               0x000003f000000000
+
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET                  0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB                     42
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB                     47
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK                    0x0000fc0000000000
+
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET                           0x0000000000000048
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB                              48
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB                              63
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK                             0xffff000000000000
+
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET                     0x0000000000000050
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB                        0
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB                        23
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK                       0x0000000000ffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET                        0x0000000000000050
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB                           24
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB                           31
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK                          0x00000000ff000000
+
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET               0x0000000000000050
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB                  32
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB                  63
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK                 0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET               0x0000000000000058
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB                  0
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB                  31
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK                 0x00000000ffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                0x0000000000000058
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB                   32
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB                   63
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK                  0xffffffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET                   0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB                      0
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB                      11
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK                     0x0000000000000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET                                0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB                                   12
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB                                   27
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK                                  0x000000000ffff000
+
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET       0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB          28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB          28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK         0x0000000010000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET                              0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB                                 29
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB                                 31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK                                0x00000000e0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET                     0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB                        32
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB                        47
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK                       0x0000ffff00000000
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET                       0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB                          48
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB                          55
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK                         0x00ff000000000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET                              0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB                                 56
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB                                 59
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK                                0x0f00000000000000
+
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET                             0x0000000000000060
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB                                60
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB                                63
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK                               0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_unblock_cache.h b/hw/fig/v1/reo_unblock_cache.h
new file mode 100644
index 000000000000..99a7923b7f9a
--- /dev/null
+++ b/hw/fig/v1/reo_unblock_cache.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
+
+#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
+
+struct reo_unblock_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t unblock_type                                            :  1,
+                      cache_block_resource_index                              :  2,
+                      reserved_1a                                             : 29;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t reserved_1a                                             : 29,
+                      cache_block_resource_index                              :  2,
+                      unblock_type                                            :  1;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                          0x0000000000000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                             0
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                             15
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                            0x000000000000ffff
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                     0x0000000000000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                        16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                        16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                       0x0000000000010000
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                             0x0000000000000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB                                17
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB                                31
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK                               0x00000000fffe0000
+
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET                                       0x0000000000000000
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB                                          32
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB                                          32
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK                                         0x0000000100000000
+
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                         0x0000000000000000
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                            33
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                            34
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                           0x0000000600000000
+
+#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET                                        0x0000000000000000
+#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB                                           35
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB                                           63
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK                                          0xfffffff800000000
+
+#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET                                        0x0000000000000008
+#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK                                          0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET                                        0x0000000000000008
+#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB                                           32
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB                                           63
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK                                          0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET                                        0x0000000000000010
+#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK                                          0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET                                        0x0000000000000010
+#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB                                           32
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB                                           63
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK                                          0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET                                        0x0000000000000018
+#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK                                          0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET                                        0x0000000000000018
+#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB                                           32
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB                                           63
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK                                          0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET                                        0x0000000000000020
+#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK                                          0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET                                      0x0000000000000020
+#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB                                         32
+#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB                                         63
+#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK                                        0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_unblock_cache_status.h b/hw/fig/v1/reo_unblock_cache_status.h
new file mode 100644
index 000000000000..2e62d26729e5
--- /dev/null
+++ b/hw/fig/v1/reo_unblock_cache_status.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
+
+#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
+
+struct reo_unblock_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      unblock_type                                            :  1,
+                      reserved_2a                                             : 30;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 30,
+                      unblock_type                                            :  1,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET             0x0000000000000000
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                0
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                15
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK               0x000000000000ffff
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET            0x0000000000000000
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB               16
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB               25
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK              0x0000000003ff0000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET      0x0000000000000000
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB         26
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB         27
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK        0x000000000c000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                   0x0000000000000000
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                      28
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                      31
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                     0x00000000f0000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                     0x0000000000000000
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                        32
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                        63
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                       0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET                              0x0000000000000008
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB                                 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB                                 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK                                0x0000000000000001
+
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET                                0x0000000000000008
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB                                   1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB                                   1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK                                  0x0000000000000002
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET                                 0x0000000000000008
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB                                    2
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK                                   0x00000000fffffffc
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET                                 0x0000000000000008
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB                                    32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB                                    63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK                                   0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK                                   0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET                                 0x0000000000000010
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB                                    32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB                                    63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK                                   0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET                                 0x0000000000000018
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK                                   0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET                                 0x0000000000000018
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB                                    32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB                                    63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK                                   0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET                                 0x0000000000000020
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK                                   0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET                                 0x0000000000000020
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB                                    32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB                                    63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK                                   0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET                                0x0000000000000028
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET                                0x0000000000000028
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET                                0x0000000000000030
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET                                0x0000000000000030
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET                                0x0000000000000038
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET                                0x0000000000000038
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET                                0x0000000000000040
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET                                0x0000000000000040
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET                                0x0000000000000048
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET                                0x0000000000000048
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET                                0x0000000000000050
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET                                0x0000000000000050
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET                                0x0000000000000058
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET                                0x0000000000000058
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB                                   63
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK                                  0xffffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET                                0x0000000000000060
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK                                  0x00000000ffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET                                0x0000000000000060
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB                                   32
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB                                   59
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK                                  0x0fffffff00000000
+
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET                               0x0000000000000060
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB                                  60
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB                                  63
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK                                 0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/reo_update_rx_reo_queue.h b/hw/fig/v1/reo_update_rx_reo_queue.h
new file mode 100644
index 000000000000..4cede8ca0194
--- /dev/null
+++ b/hw/fig/v1/reo_update_rx_reo_queue.h
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
+
+#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
+
+struct reo_update_rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      update_receive_queue_number                             :  1,
+                      update_vld                                              :  1,
+                      update_associated_link_descriptor_counter               :  1,
+                      update_disable_duplicate_detection                      :  1,
+                      update_soft_reorder_enable                              :  1,
+                      update_ac                                               :  1,
+                      update_bar                                              :  1,
+                      update_rty                                              :  1,
+                      update_chk_2k_mode                                      :  1,
+                      update_oor_mode                                         :  1,
+                      update_ba_window_size                                   :  1,
+                      update_pn_check_needed                                  :  1,
+                      update_pn_shall_be_even                                 :  1,
+                      update_pn_shall_be_uneven                               :  1,
+                      update_pn_handling_enable                               :  1,
+                      update_pn_size                                          :  1,
+                      update_ignore_ampdu_flag                                :  1,
+                      update_svld                                             :  1,
+                      update_ssn                                              :  1,
+                      update_seq_2k_error_detected_flag                       :  1,
+                      update_pn_error_detected_flag                           :  1,
+                      update_pn_valid                                         :  1,
+                      update_pn                                               :  1,
+                      clear_stat_counters                                     :  1;
+             uint32_t receive_queue_number                                    : 16,
+                      vld                                                     :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      disable_duplicate_detection                             :  1,
+                      soft_reorder_enable                                     :  1,
+                      ac                                                      :  2,
+                      bar                                                     :  1,
+                      rty                                                     :  1,
+                      chk_2k_mode                                             :  1,
+                      oor_mode                                                :  1,
+                      pn_check_needed                                         :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_handling_enable                                      :  1,
+                      ignore_ampdu_flag                                       :  1;
+             uint32_t ba_window_size                                          : 10,
+                      pn_size                                                 :  2,
+                      svld                                                    :  1,
+                      ssn                                                     : 12,
+                      seq_2k_error_detected_flag                              :  1,
+                      pn_error_detected_flag                                  :  1,
+                      pn_valid                                                :  1,
+                      flush_from_cache                                        :  1,
+                      reserved_4a                                             :  3;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t clear_stat_counters                                     :  1,
+                      update_pn                                               :  1,
+                      update_pn_valid                                         :  1,
+                      update_pn_error_detected_flag                           :  1,
+                      update_seq_2k_error_detected_flag                       :  1,
+                      update_ssn                                              :  1,
+                      update_svld                                             :  1,
+                      update_ignore_ampdu_flag                                :  1,
+                      update_pn_size                                          :  1,
+                      update_pn_handling_enable                               :  1,
+                      update_pn_shall_be_uneven                               :  1,
+                      update_pn_shall_be_even                                 :  1,
+                      update_pn_check_needed                                  :  1,
+                      update_ba_window_size                                   :  1,
+                      update_oor_mode                                         :  1,
+                      update_chk_2k_mode                                      :  1,
+                      update_rty                                              :  1,
+                      update_bar                                              :  1,
+                      update_ac                                               :  1,
+                      update_soft_reorder_enable                              :  1,
+                      update_disable_duplicate_detection                      :  1,
+                      update_associated_link_descriptor_counter               :  1,
+                      update_vld                                              :  1,
+                      update_receive_queue_number                             :  1,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t ignore_ampdu_flag                                       :  1,
+                      pn_handling_enable                                      :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_check_needed                                         :  1,
+                      oor_mode                                                :  1,
+                      chk_2k_mode                                             :  1,
+                      rty                                                     :  1,
+                      bar                                                     :  1,
+                      ac                                                      :  2,
+                      soft_reorder_enable                                     :  1,
+                      disable_duplicate_detection                             :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      vld                                                     :  1,
+                      receive_queue_number                                    : 16;
+             uint32_t reserved_4a                                             :  3,
+                      flush_from_cache                                        :  1,
+                      pn_valid                                                :  1,
+                      pn_error_detected_flag                                  :  1,
+                      seq_2k_error_detected_flag                              :  1,
+                      ssn                                                     : 12,
+                      svld                                                    :  1,
+                      pn_size                                                 :  2,
+                      ba_window_size                                          : 10;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                    0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                       15
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                      0x000000000000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET               0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                  16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                  16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                 0x0000000000010000
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                       0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB                          17
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB                          31
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK                         0x00000000fffe0000
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                  0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                     32
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                     63
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                    0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                 0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                    0
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                    7
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                   0x00000000000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET                  0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB                     8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB                     8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK                    0x0000000000000100
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET                                   0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB                                      9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB                                      9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK                                     0x0000000000000200
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET    0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB       10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB       10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK      0x0000000000000400
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB              11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB              11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK             0x0000000000000800
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET                   0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB                      12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB                      12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK                     0x0000000000001000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET                                    0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB                                       13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB                                       13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK                                      0x0000000000002000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET                                   0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB                                      14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB                                      14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK                                     0x0000000000004000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET                                   0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB                                      15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB                                      15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK                                     0x0000000000008000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB                              16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB                              16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK                             0x0000000000010000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET                              0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB                                 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB                                 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK                                0x0000000000020000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET                        0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB                           18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB                           18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK                          0x0000000000040000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET                       0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB                          19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB                          19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK                         0x0000000000080000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET                      0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB                         20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB                         20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK                        0x0000000000100000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET                    0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB                       21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB                       21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK                      0x0000000000200000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET                    0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB                       22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB                       22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK                      0x0000000000400000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET                               0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB                                  23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB                                  23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK                                 0x0000000000800000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET                     0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB                        24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB                        24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK                       0x0000000001000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET                                  0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK                                    0x0000000002000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET                                   0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB                                      26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB                                      26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK                                     0x0000000004000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET            0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB               27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB               27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK              0x0000000008000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET                0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB                   28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB                   28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK                  0x0000000010000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET                              0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB                                 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB                                 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK                                0x0000000020000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET                                    0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB                                       30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB                                       30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK                                      0x0000000040000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET                          0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK                            0x0000000080000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                         0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                            32
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                            47
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                           0x0000ffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET                                          0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB                                             48
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB                                             48
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK                                            0x0001000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB              49
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB              50
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK             0x0006000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                  0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                     51
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                     51
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                    0x0008000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                          0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                             52
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                             52
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                            0x0010000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET                                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_AC_LSB                                              53
+#define REO_UPDATE_RX_REO_QUEUE_AC_MSB                                              54
+#define REO_UPDATE_RX_REO_QUEUE_AC_MASK                                             0x0060000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET                                          0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB                                             55
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB                                             55
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK                                            0x0080000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET                                          0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB                                             56
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB                                             56
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK                                            0x0100000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                  0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB                                     57
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB                                     57
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK                                    0x0200000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET                                     0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB                                        58
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB                                        58
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK                                       0x0400000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                              0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                 59
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                 59
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                0x0800000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                             0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                60
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                60
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                               0x1000000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                              61
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                              61
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                             0x2000000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                              62
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                              62
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                             0x4000000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                            0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                               63
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                               63
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                              0x8000000000000000
+
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                               0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                  0
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                  9
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                 0x00000000000003ff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET                                      0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB                                         10
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB                                         11
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK                                        0x0000000000000c00
+
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET                                         0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB                                            12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB                                            12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK                                           0x0000000000001000
+
+#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET                                          0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB                                             13
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB                                             24
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK                                            0x0000000001ffe000
+
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                   0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                      25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                      25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                     0x0000000002000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                       0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                          26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                          26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                         0x0000000004000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET                                     0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB                                        27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB                                        27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK                                       0x0000000008000000
+
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET                             0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK                               0x0000000010000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET                                  0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB                                     29
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB                                     31
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK                                    0x00000000e0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET                                      0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB                                         32
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB                                         63
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK                                        0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET                                     0x0000000000000018
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB                                        0
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB                                        31
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK                                       0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET                                     0x0000000000000018
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB                                        32
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB                                        63
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK                                       0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET                                    0x0000000000000020
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB                                       0
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB                                       31
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK                                      0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET                                0x0000000000000020
+#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB                                   32
+#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB                                   63
+#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK                                  0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/reo_update_rx_reo_queue_status.h b/hw/fig/v1/reo_update_rx_reo_queue_status.h
new file mode 100644
index 000000000000..907841095c53
--- /dev/null
+++ b/hw/fig/v1/reo_update_rx_reo_queue_status.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26
+
+#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13
+
+struct reo_update_rx_reo_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET       0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB          0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB          15
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK         0x000000000000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET      0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB         16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB         25
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK        0x0000000003ff0000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB   26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB   27
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK  0x000000000c000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET             0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK               0x00000000f0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET               0x0000000000000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                  32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                  63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                 0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK                             0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET                           0x0000000000000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB                              32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB                              63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK                             0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET                           0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK                             0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET                           0x0000000000000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB                              32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB                              63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK                             0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET                           0x0000000000000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK                             0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET                           0x0000000000000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB                              32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB                              63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK                             0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET                           0x0000000000000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK                             0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET                           0x0000000000000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB                              32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB                              63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK                             0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET                          0x0000000000000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET                          0x0000000000000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET                          0x0000000000000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET                          0x0000000000000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET                          0x0000000000000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET                          0x0000000000000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET                          0x0000000000000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET                          0x0000000000000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET                          0x0000000000000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET                          0x0000000000000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET                          0x0000000000000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET                          0x0000000000000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET                          0x0000000000000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET                          0x0000000000000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB                             63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK                            0xffffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET                          0x0000000000000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK                            0x00000000ffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET                          0x0000000000000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB                             32
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB                             59
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK                            0x0fffffff00000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET                         0x0000000000000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB                            60
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB                            63
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK                           0xf000000000000000
+
+#endif
diff --git a/hw/fig/v1/response_end_status.h b/hw/fig/v1/response_end_status.h
new file mode 100644
index 000000000000..30c6c65e043a
--- /dev/null
+++ b/hw/fig/v1/response_end_status.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_END_STATUS_H_
+#define _RESPONSE_END_STATUS_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
+
+#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5
+
+struct response_end_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0046                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      response_transmit_status                                :  4,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      generated_response                                      :  3,
+                      mba_user_count                                          :  7,
+                      mba_fake_bitmap_count                                   :  7,
+                      coex_based_tx_bw                                        :  3,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0035                                                 :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8;
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      reserved_2b                                             : 10,
+                      only_null_delim_sent                                    :  1,
+                      brp_info_valid                                          :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0056                                       :  1,
+                      __reserved_g_0039                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0063                                       :  1,
+                      __reserved_g_0061                                       :  1,
+                      __reserved_g_0059                                       :  1,
+                      __reserved_g_0057                                       :  1,
+                      __reserved_g_0042                                       :  1;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t mu_response_bitmap_36_32                                :  5,
+                      reserved_4a                                             : 27;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      __reserved_g_0022                                                 :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      reserved_20a                                            : 13;
+#else
+             uint32_t __reserved_g_0035                                                 :  1,
+                      trig_response_related                                   :  1,
+                      coex_based_tx_bw                                        :  3,
+                      mba_fake_bitmap_count                                   :  7,
+                      mba_user_count                                          :  7,
+                      generated_response                                      :  3,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      response_transmit_status                                :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0046                                       :  1;
+             uint32_t cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t __reserved_g_0042                                       :  1,
+                      __reserved_g_0057                                       :  1,
+                      __reserved_g_0059                                       :  1,
+                      __reserved_g_0061                                       :  1,
+                      __reserved_g_0063                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0039                                       :  1,
+                      __reserved_g_0056                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      brp_info_valid                                          :  1,
+                      only_null_delim_sent                                    :  1,
+                      reserved_2b                                             : 10,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t reserved_4a                                             : 27,
+                      mu_response_bitmap_36_32                                :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t reserved_20a                                            : 13,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      addr3_47_32                                             : 16;
+#endif
+};
+
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                      0x0000000000000008
+
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB                            4
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB                            7
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK                           0x00000000000000f0
+
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK                           0x0000000000000100
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000000000200
+
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET                               0x0000000000000000
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB                                  10
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB                                  12
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK                                 0x0000000000001c00
+
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET                                   0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB                                      13
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB                                      19
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK                                     0x00000000000fe000
+
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB                               20
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB                               26
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK                              0x0000000007f00000
+
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET                                 0x0000000000000000
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB                                    27
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB                                    29
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK                                   0x0000000038000000
+
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK                              0x0000000040000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET     0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB        40
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB        45
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK       0x00003f0000000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET        0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB           46
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB           47
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK          0x0000c00000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB                            48
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB                            55
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK                           0x00ff000000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB                               56
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB                               63
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK                              0xff00000000000000
+
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB                                0
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB                                8
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK                               0x00000000000001ff
+
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET                           0x0000000000000008
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB                              9
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB                              10
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK                             0x0000000000000600
+
+#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET                                      0x0000000000000008
+#define RESPONSE_END_STATUS_RESERVED_2B_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_2B_MSB                                         20
+#define RESPONSE_END_STATUS_RESERVED_2B_MASK                                        0x00000000001ff800
+
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK                               0x0000000000200000
+
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET                                   0x0000000000000008
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK                                     0x0000000000400000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET                          0x0000000000000008
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB                             32
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB                             63
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK                            0xffffffff00000000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET                         0x0000000000000010
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB                            0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB                            4
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK                           0x000000000000001f
+
+#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET                                      0x0000000000000010
+#define RESPONSE_END_STATUS_RESERVED_4A_LSB                                         5
+#define RESPONSE_END_STATUS_RESERVED_4A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_4A_MASK                                        0x00000000ffffffe0
+
+#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET                                       0x0000000000000010
+#define RESPONSE_END_STATUS_ADDR1_31_0_LSB                                          32
+#define RESPONSE_END_STATUS_ADDR1_31_0_MSB                                          63
+#define RESPONSE_END_STATUS_ADDR1_31_0_MASK                                         0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR1_47_32_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR1_47_32_MSB                                         15
+#define RESPONSE_END_STATUS_ADDR1_47_32_MASK                                        0x000000000000ffff
+
+#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET                                       0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_15_0_LSB                                          16
+#define RESPONSE_END_STATUS_ADDR2_15_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR2_15_0_MASK                                         0x00000000ffff0000
+
+#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_47_16_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR2_47_16_MSB                                         63
+#define RESPONSE_END_STATUS_ADDR2_47_16_MASK                                        0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET                                       0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_31_0_LSB                                          0
+#define RESPONSE_END_STATUS_ADDR3_31_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR3_31_0_MASK                                         0x00000000ffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET                                      0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_47_32_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR3_47_32_MSB                                         47
+#define RESPONSE_END_STATUS_ADDR3_47_32_MASK                                        0x0000ffff00000000
+
+#define RESPONSE_END_STATUS_SECURE_OFFSET                                           0x0000000000000020
+#define RESPONSE_END_STATUS_SECURE_LSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MASK                                             0x0002000000000000
+
+#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET                                     0x0000000000000020
+#define RESPONSE_END_STATUS_RESERVED_20A_LSB                                        51
+#define RESPONSE_END_STATUS_RESERVED_20A_MSB                                        63
+#define RESPONSE_END_STATUS_RESERVED_20A_MASK                                       0xfff8000000000000
+
+#endif
diff --git a/hw/fig/v1/response_start_status.h b/hw/fig/v1/response_start_status.h
new file mode 100644
index 000000000000..b8b96e8d9f3d
--- /dev/null
+++ b/hw/fig/v1/response_start_status.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_START_STATUS_H_
+#define _RESPONSE_START_STATUS_H_
+
+#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
+
+#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
+
+struct response_start_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t generated_response                                      :  3,
+                      __reserved_g_0012                                                  :  2,
+                      trig_response_related                                   :  1,
+                      response_sta_count                                      :  7,
+                      reserved                                                : 19;
+             uint32_t phy_ppdu_id                                             : 16,
+                      sw_peer_id                                              : 16;
+#else
+             uint32_t reserved                                                : 19,
+                      response_sta_count                                      :  7,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0012                                                  :  2,
+                      generated_response                                      :  3;
+             uint32_t sw_peer_id                                              : 16,
+                      phy_ppdu_id                                             : 16;
+#endif
+};
+
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB                                0
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB                                2
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK                               0x0000000000000007
+
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET                          0x0000000000000000
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK                            0x0000000000000020
+
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB                                6
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB                                12
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK                               0x0000000000001fc0
+
+#define RESPONSE_START_STATUS_RESERVED_OFFSET                                       0x0000000000000000
+#define RESPONSE_START_STATUS_RESERVED_LSB                                          13
+#define RESPONSE_START_STATUS_RESERVED_MSB                                          31
+#define RESPONSE_START_STATUS_RESERVED_MASK                                         0x00000000ffffe000
+
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET                                    0x0000000000000000
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB                                       32
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB                                       47
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK                                      0x0000ffff00000000
+
+#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET                                     0x0000000000000000
+#define RESPONSE_START_STATUS_SW_PEER_ID_LSB                                        48
+#define RESPONSE_START_STATUS_SW_PEER_ID_MSB                                        63
+#define RESPONSE_START_STATUS_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/ru_allocation_160_info.h b/hw/fig/v1/ru_allocation_160_info.h
new file mode 100644
index 000000000000..57d51dc44f8a
--- /dev/null
+++ b/hw/fig/v1/ru_allocation_160_info.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation_band0_0                                   :  9,
+                      ru_allocation_band0_1                                   :  9,
+                      reserved_0a                                             :  6,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      ru_allocations_23_subband80_mask                        :  4;
+             uint32_t ru_allocation_band0_2                                   :  9,
+                      ru_allocation_band0_3                                   :  9,
+                      reserved_1a                                             : 14;
+             uint32_t ru_allocation_band1_0                                   :  9,
+                      ru_allocation_band1_1                                   :  9,
+                      reserved_2a                                             : 14;
+             uint32_t ru_allocation_band1_2                                   :  9,
+                      ru_allocation_band1_3                                   :  9,
+                      reserved_3a                                             : 14;
+#else
+             uint32_t ru_allocations_23_subband80_mask                        :  4,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      reserved_0a                                             :  6,
+                      ru_allocation_band0_1                                   :  9,
+                      ru_allocation_band0_0                                   :  9;
+             uint32_t reserved_1a                                             : 14,
+                      ru_allocation_band0_3                                   :  9,
+                      ru_allocation_band0_2                                   :  9;
+             uint32_t reserved_2a                                             : 14,
+                      ru_allocation_band1_1                                   :  9,
+                      ru_allocation_band1_0                                   :  9;
+             uint32_t reserved_3a                                             : 14,
+                      ru_allocation_band1_3                                   :  9,
+                      ru_allocation_band1_2                                   :  9;
+#endif
+};
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
+
+#endif
diff --git a/hw/fig/v1/rx_attention.h b/hw/fig/v1/rx_attention.h
new file mode 100644
index 000000000000..cac7c2fb52c3
--- /dev/null
+++ b/hw/fig/v1/rx_attention.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+
+#define NUM_OF_DWORDS_RX_ATTENTION 4
+
+#define NUM_OF_QWORDS_RX_ATTENTION 2
+
+struct rx_attention {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_1a                                             :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      cce_match                                               :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      reserved_1b                                             :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      wifi_parser_error                                       :  1,
+                      amsdu_parser_error                                      :  1,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      msdu_limit_error                                        :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      sa_is_valid                                             :  1,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_2                                              : 17,
+                      msdu_done                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      reserved_1b                                             :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      cce_match                                               :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_1a                                             :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_2                                              : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      sa_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      msdu_limit_error                                        :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      amsdu_parser_error                                      :  1,
+                      wifi_parser_error                                       :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000000000000000
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x0000000000000003
+
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK                                         0x00000000000001fc
+
+#define RX_ATTENTION_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_RESERVED_0_LSB                                                 9
+#define RX_ATTENTION_RESERVED_0_MSB                                                 15
+#define RX_ATTENTION_RESERVED_0_MASK                                                0x000000000000fe00
+
+#define RX_ATTENTION_PHY_PPDU_ID_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_PHY_PPDU_ID_LSB                                                16
+#define RX_ATTENTION_PHY_PPDU_ID_MSB                                                31
+#define RX_ATTENTION_PHY_PPDU_ID_MASK                                               0x00000000ffff0000
+
+#define RX_ATTENTION_FIRST_MPDU_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_FIRST_MPDU_LSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MASK                                                0x0000000100000000
+
+#define RX_ATTENTION_RESERVED_1A_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1A_LSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MASK                                               0x0000000200000000
+
+#define RX_ATTENTION_MCAST_BCAST_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_MCAST_BCAST_LSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MASK                                               0x0000000400000000
+
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK                                       0x0000000800000000
+
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK                                         0x0000001000000000
+
+#define RX_ATTENTION_POWER_MGMT_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_POWER_MGMT_LSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MASK                                                0x0000002000000000
+
+#define RX_ATTENTION_NON_QOS_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_NON_QOS_LSB                                                    38
+#define RX_ATTENTION_NON_QOS_MSB                                                    38
+#define RX_ATTENTION_NON_QOS_MASK                                                   0x0000004000000000
+
+#define RX_ATTENTION_NULL_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_NULL_DATA_LSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MASK                                                 0x0000008000000000
+
+#define RX_ATTENTION_MGMT_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MGMT_TYPE_LSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MASK                                                 0x0000010000000000
+
+#define RX_ATTENTION_CTRL_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CTRL_TYPE_LSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MASK                                                 0x0000020000000000
+
+#define RX_ATTENTION_MORE_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MORE_DATA_LSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MASK                                                 0x0000040000000000
+
+#define RX_ATTENTION_EOSP_OFFSET                                                    0x0000000000000000
+#define RX_ATTENTION_EOSP_LSB                                                       43
+#define RX_ATTENTION_EOSP_MSB                                                       43
+#define RX_ATTENTION_EOSP_MASK                                                      0x0000080000000000
+
+#define RX_ATTENTION_A_MSDU_ERROR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_A_MSDU_ERROR_LSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MASK                                              0x0000100000000000
+
+#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET                                           0x0000000000000000
+#define RX_ATTENTION_FRAGMENT_FLAG_LSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MASK                                             0x0000200000000000
+
+#define RX_ATTENTION_ORDER_OFFSET                                                   0x0000000000000000
+#define RX_ATTENTION_ORDER_LSB                                                      46
+#define RX_ATTENTION_ORDER_MSB                                                      46
+#define RX_ATTENTION_ORDER_MASK                                                     0x0000400000000000
+
+#define RX_ATTENTION_CCE_MATCH_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CCE_MATCH_LSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MASK                                                 0x0000800000000000
+
+#define RX_ATTENTION_OVERFLOW_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_OVERFLOW_ERR_LSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MASK                                              0x0001000000000000
+
+#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK                                           0x0002000000000000
+
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK                                       0x0004000000000000
+
+#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK                                            0x0008000000000000
+
+#define RX_ATTENTION_SA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_SA_IDX_INVALID_LSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MASK                                            0x0010000000000000
+
+#define RX_ATTENTION_DA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_DA_IDX_INVALID_LSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MASK                                            0x0020000000000000
+
+#define RX_ATTENTION_RESERVED_1B_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1B_LSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MASK                                               0x0040000000000000
+
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET                                    0x0000000000000000
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK                                      0x0080000000000000
+
+#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET                                        0x0000000000000000
+#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK                                          0x0100000000000000
+
+#define RX_ATTENTION_DIRECTED_OFFSET                                                0x0000000000000000
+#define RX_ATTENTION_DIRECTED_LSB                                                   57
+#define RX_ATTENTION_DIRECTED_MSB                                                   57
+#define RX_ATTENTION_DIRECTED_MASK                                                  0x0200000000000000
+
+#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_BUFFER_FRAGMENT_LSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MASK                                           0x0400000000000000
+
+#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK                                           0x0800000000000000
+
+#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_TKIP_MIC_ERR_LSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MASK                                              0x1000000000000000
+
+#define RX_ATTENTION_DECRYPT_ERR_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_DECRYPT_ERR_LSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MASK                                               0x2000000000000000
+
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET                                   0x0000000000000000
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK                                     0x4000000000000000
+
+#define RX_ATTENTION_FCS_ERR_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_FCS_ERR_LSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MASK                                                   0x8000000000000000
+
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK                                          0x0000000000000001
+
+#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_INVALID_LSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MASK                                          0x0000000000000002
+
+#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET                                       0x0000000000000008
+#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK                                         0x0000000000000004
+
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET                                      0x0000000000000008
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK                                        0x0000000000000008
+
+#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK                                            0x0000000000000010
+
+#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK                                            0x0000000000000020
+
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK                                          0x0000000000000040
+
+#define RX_ATTENTION_DA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_DA_IS_VALID_LSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MASK                                               0x0000000000000080
+
+#define RX_ATTENTION_DA_IS_MCBC_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_DA_IS_MCBC_LSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MASK                                                0x0000000000000100
+
+#define RX_ATTENTION_SA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_SA_IS_VALID_LSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MASK                                               0x0000000000000200
+
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET                                     0x0000000000000008
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB                                        10
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB                                        12
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK                                       0x0000000000001c00
+
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET                                   0x0000000000000008
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK                                     0x0000000000002000
+
+#define RX_ATTENTION_RESERVED_2_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_RESERVED_2_LSB                                                 14
+#define RX_ATTENTION_RESERVED_2_MSB                                                 30
+#define RX_ATTENTION_RESERVED_2_MASK                                                0x000000007fffc000
+
+#define RX_ATTENTION_MSDU_DONE_OFFSET                                               0x0000000000000008
+#define RX_ATTENTION_MSDU_DONE_LSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MASK                                                 0x0000000080000000
+
+#define RX_ATTENTION_TLV64_PADDING_OFFSET                                           0x0000000000000008
+#define RX_ATTENTION_TLV64_PADDING_LSB                                              32
+#define RX_ATTENTION_TLV64_PADDING_MSB                                              63
+#define RX_ATTENTION_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_flow_search_entry.h b/hw/fig/v1/rx_flow_search_entry.h
new file mode 100644
index 000000000000..25f1f81c439f
--- /dev/null
+++ b/hw/fig/v1/rx_flow_search_entry.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t src_port                                                : 16,
+                      dest_port                                               : 16;
+             uint32_t l4_protocol                                             :  8,
+                      valid                                                   :  1,
+                      reserved_9                                              :  4,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      use_ppe                                                 :  1,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1,
+                      reo_destination_handler                                 :  2;
+             uint32_t metadata                                                : 32;
+             uint32_t aggregation_count                                       :  7,
+                      lro_eligible                                            :  1,
+                      msdu_count                                              : 24;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length_pmac1                              : 16,
+                      cumulative_ip_length                                    : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#else
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t dest_port                                               : 16,
+                      src_port                                                : 16;
+             uint32_t reo_destination_handler                                 :  2,
+                      msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      use_ppe                                                 :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_9                                              :  4,
+                      valid                                                   :  1,
+                      l4_protocol                                             :  8;
+             uint32_t metadata                                                : 32;
+             uint32_t msdu_count                                              : 24,
+                      lro_eligible                                            :  1,
+                      aggregation_count                                       :  7;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length                                    : 16,
+                      cumulative_ip_length_pmac1                              : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#endif
+};
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET                                   0x00000000
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET                                    0x00000004
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET                                    0x00000008
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET                                     0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB                                        31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK                                       0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET                                  0x00000010
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB                                     0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB                                     31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK                                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET                                   0x00000014
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET                                   0x00000018
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET                                    0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET                                        0x00000020
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB                                           15
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK                                          0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET                                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB                                          16
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK                                         0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET                                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB                                        7
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK                                       0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET                                           0x00000024
+#define RX_FLOW_SEARCH_ENTRY_VALID_LSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MASK                                             0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET                                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB                                         9
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB                                         12
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK                                        0x00001e00
+
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET                                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB                                       13
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB                                       21
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK                                      0x003fe000
+
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET                                  0x00000024
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK                                    0x00400000
+
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET                                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK                                           0x00800000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB                         24
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB                         28
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK                        0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET                                       0x00000024
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK                                         0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB                            30
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB                            31
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK                           0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET                                        0x00000028
+#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB                                           31
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK                                          0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET                               0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB                                  0
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB                                  6
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK                                 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET                                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK                                      0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET                                      0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB                                         8
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB                                         31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK                                        0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET                                 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB                                    0
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB                                    31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK                                   0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET                                       0x00000034
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB                                          0
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK                                         0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET                      0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB                         15
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK                        0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET                            0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB                               16
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB                               31
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK                              0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET                             0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB                                0
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB                                31
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK                               0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rx_frame_1k_bitmap_ack.h b/hw/fig/v1/rx_frame_1k_bitmap_ack.h
new file mode 100644
index 000000000000..a43548b14a07
--- /dev/null
+++ b/hw/fig/v1/rx_frame_1k_bitmap_ack.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
+#define _RX_FRAME_1K_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38
+
+#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19
+
+struct rx_frame_1k_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  5,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0b                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0c                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      reserved_1a                                             : 20;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#else
+             uint32_t reserved_0c                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0b                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0a                                             :  5;
+             uint32_t reserved_1a                                             : 20,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#endif
+};
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB                                      4
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK                                     0x000000000000001f
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                   5
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                   6
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                  0x0000000000000060
+
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                            0x0000000000000080
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB                                      8
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB                                      9
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK                                     0x0000000000000300
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET                                        0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB                                           10
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB                                           13
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK                                          0x0000000000003c00
+
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB                                     14
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB                                     26
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK                                    0x0000000007ffc000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB                                      27
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK                                     0x00000000f8000000
+
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB                                       41
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK                                      0x000003ff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                            0x0000040000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                           0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                             0x0000080000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB                                      44
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB                                      63
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK                                     0xfffff00000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB                                       0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB                                       31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK                                      0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET                                   0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB                                      32
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB                                      47
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK                                     0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB                                       48
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB                                       63
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK                                      0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET                                   0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK                                     0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET                                    0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB                                       47
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK                                      0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET                                     0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB                                        48
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB                                        63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK                                       0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                             0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                            0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                               32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                               63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                              0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                            0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                               0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                               31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                              0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                           0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                              32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                              63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                             0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET                          0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET                         0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB                            32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB                            63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_frame_bitmap_ack.h b/hw/fig/v1/rx_frame_bitmap_ack.h
new file mode 100644
index 000000000000..0b68486b038e
--- /dev/null
+++ b/hw/fig/v1/rx_frame_bitmap_ack.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_ACK_H_
+#define _RX_FRAME_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7
+
+struct rx_frame_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_bitmap_available                                     :  1,
+                      explicit_ack                                            :  1,
+                      explict_ack_type                                        :  3,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0a                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0b                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_32_allowed                                      :  1,
+                      reserved_1a                                             : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#else
+             uint32_t reserved_0b                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0a                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      explict_ack_type                                        :  3,
+                      explicit_ack                                            :  1,
+                      no_bitmap_available                                     :  1;
+             uint32_t reserved_1a                                             : 16,
+                      ba_size_32_allowed                                      :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK                                0x0000000000000001
+
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK                                       0x0000000000000002
+
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET                                 0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB                                    2
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB                                    4
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK                                   0x000000000000001c
+
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                   0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                      5
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                      6
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                     0x0000000000000060
+
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                               0x0000000000000080
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB                                         8
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB                                         9
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK                                        0x0000000000000300
+
+#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET                                           0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_TID_LSB                                              10
+#define RX_FRAME_BITMAP_ACK_BA_TID_MSB                                              13
+#define RX_FRAME_BITMAP_ACK_BA_TID_MASK                                             0x0000000000003c00
+
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB                                        14
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB                                        26
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK                                       0x0000000007ffc000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB                                         27
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK                                        0x00000000f8000000
+
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB                                          41
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK                                         0x000003ff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                               0x0000040000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                                0x0000080000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK                                0x0000100000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK                                0x0000200000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK                                 0x0000400000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK                                 0x0000800000000000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB                                         48
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB                                         63
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB                                          0
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB                                          31
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK                                         0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET                                      0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB                                         32
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB                                         47
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK                                        0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB                                          48
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB                                          63
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK                                         0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET                                      0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB                                         0
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK                                        0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET                                       0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB                                          47
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK                                         0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET                                        0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB                                           48
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB                                           63
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK                                          0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                                0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                   0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                   31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                               0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                                  32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                                  63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                                 0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                               0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                                  0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                                  31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                                 0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                              0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                                 32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                                 63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                                0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                               0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                               0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_frame_bitmap_req.h b/hw/fig/v1/rx_frame_bitmap_req.h
new file mode 100644
index 000000000000..24f8ddd1c57c
--- /dev/null
+++ b/hw/fig/v1/rx_frame_bitmap_req.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_REQ_H_
+#define _RX_FRAME_BITMAP_REQ_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1
+
+struct rx_frame_bitmap_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t explicit_user_request                                   :  1,
+                      user_request_type                                       :  1,
+                      user_number                                             :  6,
+                      sw_peer_id                                              : 16,
+                      tid_specific_request                                    :  1,
+                      requested_tid                                           :  4,
+                      reserved_0                                              :  3;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  3,
+                      requested_tid                                           :  4,
+                      tid_specific_request                                    :  1,
+                      sw_peer_id                                              : 16,
+                      user_number                                             :  6,
+                      user_request_type                                       :  1,
+                      explicit_user_request                                   :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET                            0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK                              0x0000000000000001
+
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET                                0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK                                  0x0000000000000002
+
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB                                         2
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB                                         7
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK                                        0x00000000000000fc
+
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB                                          8
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB                                          23
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK                                         0x0000000000ffff00
+
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK                               0x0000000001000000
+
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB                                       25
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB                                       28
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK                                      0x000000001e000000
+
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB                                          29
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB                                          31
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK                                         0x00000000e0000000
+
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB                                       32
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB                                       63
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK                                      0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_location_info.h b/hw/fig/v1/rx_location_info.h
new file mode 100644
index 000000000000..ee000f6d4cda
--- /dev/null
+++ b/hw/fig/v1/rx_location_info.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
+
+struct rx_location_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_location_info_valid                                  :  1,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rtt___reserved_g_0020_mode                                           :  2,
+                      reserved_0                                              :  4,
+                      rtt_num_fac                                             :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_streams                                         :  8;
+             uint32_t rtt_first_selected_chain                                :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_cir_status                                          :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_che_buffer_pointer_high8                            :  8,
+                      reserved_3                                              :  8,
+                      rtt_pkt_bw_vht                                          :  4,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_mcs_rate                                            :  8;
+             uint32_t rtt_cfo_measurement                                     : 16,
+                      rtt_preamble_type                                       :  8,
+                      rtt_gi_type                                             :  8;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain0                                             : 16,
+                      gain_chain1                                             : 16;
+             uint32_t gain_chain2                                             : 16,
+                      gain_chain3                                             : 16;
+             uint32_t gain_report_status                                      :  8,
+                      rtt_timing_backoff_sel                                  :  8,
+                      rtt_fac_combined                                        : 16;
+             uint32_t rtt_fac_0                                               : 16,
+                      rtt_fac_1                                               : 16;
+             uint32_t rtt_fac_2                                               : 16,
+                      rtt_fac_3                                               : 16;
+             uint32_t rtt_fac_4                                               : 16,
+                      rtt_fac_5                                               : 16;
+             uint32_t rtt_fac_6                                               : 16,
+                      rtt_fac_7                                               : 16;
+             uint32_t rtt_fac_8                                               : 16,
+                      rtt_fac_9                                               : 16;
+             uint32_t rtt_fac_10                                              : 16,
+                      rtt_fac_11                                              : 16;
+             uint32_t rtt_fac_12                                              : 16,
+                      rtt_fac_13                                              : 16;
+             uint32_t rtt_fac_14                                              : 16,
+                      rtt_fac_15                                              : 16;
+             uint32_t rtt_fac_16                                              : 16,
+                      rtt_fac_17                                              : 16;
+             uint32_t rtt_fac_18                                              : 16,
+                      rtt_fac_19                                              : 16;
+             uint32_t rtt_fac_20                                              : 16,
+                      rtt_fac_21                                              : 16;
+             uint32_t rtt_fac_22                                              : 16,
+                      rtt_fac_23                                              : 16;
+             uint32_t rtt_fac_24                                              : 16,
+                      rtt_fac_25                                              : 16;
+             uint32_t rtt_fac_26                                              : 16,
+                      rtt_fac_27                                              : 16;
+             uint32_t rtt_fac_28                                              : 16,
+                      rtt_fac_29                                              : 16;
+             uint32_t rtt_fac_30                                              : 16,
+                      rtt_fac_31                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#else
+             uint32_t rtt_num_streams                                         :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_fac                                             :  8,
+                      reserved_0                                              :  4,
+                      rtt___reserved_g_0020_mode                                           :  2,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rx_location_info_valid                                  :  1;
+             uint32_t rtt_cir_status                                          :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_first_selected_chain                                :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_mcs_rate                                            :  8,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_pkt_bw_vht                                          :  4,
+                      reserved_3                                              :  8,
+                      rtt_che_buffer_pointer_high8                            :  8;
+             uint32_t rtt_gi_type                                             :  8,
+                      rtt_preamble_type                                       :  8,
+                      rtt_cfo_measurement                                     : 16;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain1                                             : 16,
+                      gain_chain0                                             : 16;
+             uint32_t gain_chain3                                             : 16,
+                      gain_chain2                                             : 16;
+             uint32_t rtt_fac_combined                                        : 16,
+                      rtt_timing_backoff_sel                                  :  8,
+                      gain_report_status                                      :  8;
+             uint32_t rtt_fac_1                                               : 16,
+                      rtt_fac_0                                               : 16;
+             uint32_t rtt_fac_3                                               : 16,
+                      rtt_fac_2                                               : 16;
+             uint32_t rtt_fac_5                                               : 16,
+                      rtt_fac_4                                               : 16;
+             uint32_t rtt_fac_7                                               : 16,
+                      rtt_fac_6                                               : 16;
+             uint32_t rtt_fac_9                                               : 16,
+                      rtt_fac_8                                               : 16;
+             uint32_t rtt_fac_11                                              : 16,
+                      rtt_fac_10                                              : 16;
+             uint32_t rtt_fac_13                                              : 16,
+                      rtt_fac_12                                              : 16;
+             uint32_t rtt_fac_15                                              : 16,
+                      rtt_fac_14                                              : 16;
+             uint32_t rtt_fac_17                                              : 16,
+                      rtt_fac_16                                              : 16;
+             uint32_t rtt_fac_19                                              : 16,
+                      rtt_fac_18                                              : 16;
+             uint32_t rtt_fac_21                                              : 16,
+                      rtt_fac_20                                              : 16;
+             uint32_t rtt_fac_23                                              : 16,
+                      rtt_fac_22                                              : 16;
+             uint32_t rtt_fac_25                                              : 16,
+                      rtt_fac_24                                              : 16;
+             uint32_t rtt_fac_27                                              : 16,
+                      rtt_fac_26                                              : 16;
+             uint32_t rtt_fac_29                                              : 16,
+                      rtt_fac_28                                              : 16;
+             uint32_t rtt_fac_31                                              : 16,
+                      rtt_fac_30                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#endif
+};
+
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET                              0x00000000
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK                                0x00000001
+
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET                                    0x00000000
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK                                      0x00000002
+
+#define RX_LOCATION_INFO_RESERVED_0_OFFSET                                          0x00000000
+#define RX_LOCATION_INFO_RESERVED_0_LSB                                             4
+#define RX_LOCATION_INFO_RESERVED_0_MSB                                             7
+#define RX_LOCATION_INFO_RESERVED_0_MASK                                            0x000000f0
+
+#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET                                         0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB                                            8
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB                                            15
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK                                           0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET                                   0x00000000
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB                                      16
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB                                      23
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET                                     0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB                                        24
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB                                        31
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK                                       0xff000000
+
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET                            0x00000004
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB                               0
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB                               7
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK                              0x000000ff
+
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET                           0x00000004
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB                              8
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB                              15
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK                             0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB                                         16
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB                                         23
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK                                        0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB                                         24
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB                                         31
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK                                        0xff000000
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET                        0x00000008
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB                           31
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK                          0xffffffff
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET                        0x0000000c
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB                           7
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK                          0x000000ff
+
+#define RX_LOCATION_INFO_RESERVED_3_OFFSET                                          0x0000000c
+#define RX_LOCATION_INFO_RESERVED_3_LSB                                             8
+#define RX_LOCATION_INFO_RESERVED_3_MSB                                             15
+#define RX_LOCATION_INFO_RESERVED_3_MASK                                            0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB                                         16
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB                                         19
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK                                        0x000f0000
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB                                         20
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB                                         23
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK                                        0x00f00000
+
+#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET                                        0x0000000c
+#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB                                           24
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB                                           31
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK                                          0xff000000
+
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET                                 0x00000010
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB                                    0
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB                                    15
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK                                   0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET                                   0x00000010
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB                                      16
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB                                      23
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET                                         0x00000010
+#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB                                            24
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB                                            31
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK                                           0xff000000
+
+#define RX_LOCATION_INFO_RX_START_TS_OFFSET                                         0x00000014
+#define RX_LOCATION_INFO_RX_START_TS_LSB                                            0
+#define RX_LOCATION_INFO_RX_START_TS_MSB                                            31
+#define RX_LOCATION_INFO_RX_START_TS_MASK                                           0xffffffff
+
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET                                   0x00000018
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB                                      0
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB                                      31
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK                                     0xffffffff
+
+#define RX_LOCATION_INFO_RX_END_TS_OFFSET                                           0x0000001c
+#define RX_LOCATION_INFO_RX_END_TS_LSB                                              0
+#define RX_LOCATION_INFO_RX_END_TS_MSB                                              31
+#define RX_LOCATION_INFO_RX_END_TS_MASK                                             0xffffffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET                                  0x00000028
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB                                     0
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB                                     7
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK                                    0x000000ff
+
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET                              0x00000028
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB                                 8
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB                                 15
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK                                0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET                                    0x00000028
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB                                       16
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB                                       31
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK                                      0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_0_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_0_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_0_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_1_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_1_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_1_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_2_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_2_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_2_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_3_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_3_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_3_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_4_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_4_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_4_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_5_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_5_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_5_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_6_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_6_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_6_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_7_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_7_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_7_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_8_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_8_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_8_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_9_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_9_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_9_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_10_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_10_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_10_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_11_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_11_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_11_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_12_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_12_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_12_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_13_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_13_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_13_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_14_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_14_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_14_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_15_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_15_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_15_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_16_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_16_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_16_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_17_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_17_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_17_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_18_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_18_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_18_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_19_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_19_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_19_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_20_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_20_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_20_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_21_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_21_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_21_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_22_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_22_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_22_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_23_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_23_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_23_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_24_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_24_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_24_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_25_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_25_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_25_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_26_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_26_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_26_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_27_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_27_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_27_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_28_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_28_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_28_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_29_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_29_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_29_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_30_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_30_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_30_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_31_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_31_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_31_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RESERVED_27A_OFFSET                                        0x0000006c
+#define RX_LOCATION_INFO_RESERVED_27A_LSB                                           0
+#define RX_LOCATION_INFO_RESERVED_27A_MSB                                           31
+#define RX_LOCATION_INFO_RESERVED_27A_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_desc_info.h b/hw/fig/v1/rx_mpdu_desc_info.h
new file mode 100644
index 000000000000..30f538fb1228
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_desc_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_count                                              :  8,
+                      fragment_flag                                           :  1,
+                      mpdu_retry_bit                                          :  1,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      raw_mpdu                                                :  1,
+                      more_fragment_flag                                      :  1,
+                      src_info                                                : 12,
+                      mpdu_qos_control_valid                                  :  1,
+                      tid                                                     :  4;
+             uint32_t peer_meta_data                                          : 32;
+#else
+             uint32_t tid                                                     :  4,
+                      mpdu_qos_control_valid                                  :  1,
+                      src_info                                                : 12,
+                      more_fragment_flag                                      :  1,
+                      raw_mpdu                                                :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      mpdu_retry_bit                                          :  1,
+                      fragment_flag                                           :  1,
+                      msdu_count                                              :  8;
+             uint32_t peer_meta_data                                          : 32;
+#endif
+};
+
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
+
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
+
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
+
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
+
+#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
+#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
+
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
+
+#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
+
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
+
+#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_SRC_INFO_LSB                                              15
+#define RX_MPDU_DESC_INFO_SRC_INFO_MSB                                              26
+#define RX_MPDU_DESC_INFO_SRC_INFO_MASK                                             0x07ff8000
+
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
+
+#define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
+#define RX_MPDU_DESC_INFO_TID_LSB                                                   28
+#define RX_MPDU_DESC_INFO_TID_MSB                                                   31
+#define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
+
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_details.h b/hw/fig/v1/rx_mpdu_details.h
new file mode 100644
index 000000000000..d2d96a0a9996
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_details.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+
+#include "rx_mpdu_ext_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6
+
+struct rx_mpdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB               0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB              0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB              7
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB               12
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                    0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                    7
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK                   0x000000ff
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET              0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK                0x00000100
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET             0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK               0x00000200
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK                   0x00000400
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET                  0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                    0x00000800
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                     0x00002000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET         0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK           0x00004000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                      15
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                      26
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                     0x07ff8000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET     0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK       0x08000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                        0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                           28
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                           31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                          0xf0000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET             0x0000000c
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB                0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB                31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK               0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET                0x00000010
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB                   0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB                   31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK                  0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET               0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB                  0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB                  15
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK                 0x0000ffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET         0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB            16
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB            17
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK           0x00030000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET   0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB      18
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB      21
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK     0x003c0000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET            0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB               22
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB               31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK              0xffc00000
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_end.h b/hw/fig/v1/rx_mpdu_end.h
new file mode 100644
index 000000000000..b811f3622720
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_end.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_END 4
+
+#define NUM_OF_QWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_1a                                             : 11,
+                      unsup_ktype_short_frame                                 :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      overflow_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      fcs_err                                                 :  1,
+                      msdu_length_err                                         :  1,
+                      reserved1c                                              :  6,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_1b                                             :  1;
+             uint32_t reserved_2a                                             : 15,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      rxpcu_mgmt_sequence_nr                                  : 16;
+             uint32_t __reserved_g_0002                                       : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1b                                             :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved1c                                              :  6,
+                      msdu_length_err                                         :  1,
+                      fcs_err                                                 :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      reserved_1a                                             : 11;
+             uint32_t rxpcu_mgmt_sequence_nr                                  : 16,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      reserved_2a                                             : 15;
+             uint32_t __reserved_g_0002                                       : 32;
+#endif
+};
+
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MPDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED_0_LSB                                                  9
+#define RX_MPDU_END_RESERVED_0_MSB                                                  15
+#define RX_MPDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MPDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MPDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MPDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MPDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_RESERVED_1A_LSB                                                 32
+#define RX_MPDU_END_RESERVED_1A_MSB                                                 42
+#define RX_MPDU_END_RESERVED_1A_MASK                                                0x000007ff00000000
+
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET                                  0x0000000000000000
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK                                    0x0000080000000000
+
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000000
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000100000000000
+
+#define RX_MPDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_OVERFLOW_ERR_LSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MASK                                               0x0000200000000000
+
+#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000400000000000
+
+#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_TKIP_MIC_ERR_LSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MASK                                               0x0000800000000000
+
+#define RX_MPDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_DECRYPT_ERR_LSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MASK                                                0x0001000000000000
+
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0002000000000000
+
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                             0x0000000000000000
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK                               0x0004000000000000
+
+#define RX_MPDU_END_FCS_ERR_OFFSET                                                  0x0000000000000000
+#define RX_MPDU_END_FCS_ERR_LSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MASK                                                    0x0008000000000000
+
+#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK                                            0x0010000000000000
+
+#define RX_MPDU_END_RESERVED1C_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED1C_LSB                                                  53
+#define RX_MPDU_END_RESERVED1C_MSB                                                  58
+#define RX_MPDU_END_RESERVED1C_MASK                                                 0x07e0000000000000
+
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000000
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB                                         59
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB                                         61
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK                                        0x3800000000000000
+
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x4000000000000000
+
+#define RX_MPDU_END_RESERVED_1B_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_RESERVED_1B_LSB                                                 63
+#define RX_MPDU_END_RESERVED_1B_MSB                                                 63
+#define RX_MPDU_END_RESERVED_1B_MASK                                                0x8000000000000000
+
+#define RX_MPDU_END_RESERVED_2A_OFFSET                                              0x0000000000000008
+#define RX_MPDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MPDU_END_RESERVED_2A_MSB                                                 14
+#define RX_MPDU_END_RESERVED_2A_MASK                                                0x0000000000007fff
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK                               0x0000000000008000
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET                                   0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB                                      16
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB                                      31
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK                                     0x00000000ffff0000
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_ext_desc_info.h b/hw/fig/v1/rx_mpdu_ext_desc_info.h
new file mode 100644
index 000000000000..83f4df333c88
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_ext_desc_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_EXT_DESC_INFO_H_
+#define _RX_MPDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2
+
+struct rx_mpdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      pn_127_48_info                                          :  2,
+                      msdu_link_desc_index                                    :  4,
+                      reserved_1a                                             : 10;
+#else
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t reserved_1a                                             : 10,
+                      msdu_link_desc_index                                    :  4,
+                      pn_127_48_info                                          :  2,
+                      pn_47_32                                                : 16;
+#endif
+};
+
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET                                        0x00000000
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB                                           0
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB                                           31
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK                                          0xffffffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET                                       0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB                                          0
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB                                          15
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK                                         0x0000ffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET                                 0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB                                    16
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB                                    17
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK                                   0x00030000
+
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET                           0x00000004
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB                              18
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB                              21
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK                             0x003c0000
+
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET                                    0x00000004
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB                                       22
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB                                       31
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK                                      0xffc00000
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_info.h b/hw/fig/v1/rx_mpdu_info.h
new file mode 100644
index 000000000000..b742b6ce733b
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_info.h
@@ -0,0 +1,958 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+
+#include "rxpt_classify_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_INFO 30
+
+struct rx_mpdu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t epd_en                                                  :  1,
+                      all_frames_shall_be_encrypted                           :  1,
+                      encrypt_type                                            :  4,
+                      wep_key_width_for_variable_key                          :  2,
+                      __reserved_g_0003                                                :  2,
+                      bssid_hit                                               :  1,
+                      bssid_number                                            :  4,
+                      tid                                                     :  4,
+                      reserved_7a                                             : 13;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      receive_queue_number                                    : 16,
+                      pre_delim_err_warning                                   :  1,
+                      first_delim_err                                         :  1,
+                      reserved_2a                                             :  6;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_frame_control_valid                                :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_fragment_number                                    :  4,
+                      more_fragment_flag                                      :  1,
+                      reserved_11a                                            :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      encrypted                                               :  1,
+                      mpdu_retry                                              :  1,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t ast_index                                               : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      ndp_frame                                               :  1,
+                      phy_err                                                 :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      protocol_version_err                                    :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      __reserved_g_0035                                                 :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t key_id_octet                                            :  8,
+                      new_peer_entry                                          :  1,
+                      decrypt_needed                                          :  1,
+                      decap_type                                              :  2,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      pre_delim_count                                         : 12,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      raw_mpdu                                                :  1,
+                      reserved_12                                             :  1;
+             uint32_t mpdu_length                                             : 14,
+                      first_mpdu                                              :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      u_apsd_trigger                                          :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      amsdu_present                                           :  1,
+                      reserved_13                                             :  1;
+             uint32_t mpdu_frame_control_field                                : 16,
+                      mpdu_duration_field                                     : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad1_47_32                                      : 16,
+                      mac_addr_ad2_15_0                                       : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mac_addr_ad3_47_32                                      : 16,
+                      mpdu_sequence_control_field                             : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mac_addr_ad4_47_32                                      : 16,
+                      mpdu_qos_control_field                                  : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t vdev_id                                                 :  8,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      src_info                                                : 12,
+                      reserved_23a                                            :  1,
+                      __reserved_g_0006                                       :  1;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t authorized_to_send_wds                                  :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      rx_misc_config                                          :  3,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      multi_link_addr_fromtods_00_raw_en                      :  1,
+                      multi_link_addr_fromtods_non00_raw_en                   :  1,
+                      multi_link_addr_ad3_valid                               :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_mgmt_en                                 :  1,
+                      multi_link_addr_ctrl_en                                 :  1,
+                      reserved_27a                                            :  5;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t multi_link_addr_ad3_47_32                               : 16,
+                      reserved_29a                                            : 16;
+#else
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t reserved_7a                                             : 13,
+                      tid                                                     :  4,
+                      bssid_number                                            :  4,
+                      bssid_hit                                               :  1,
+                      __reserved_g_0003                                                :  2,
+                      wep_key_width_for_variable_key                          :  2,
+                      encrypt_type                                            :  4,
+                      all_frames_shall_be_encrypted                           :  1,
+                      epd_en                                                  :  1;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             :  6,
+                      first_delim_err                                         :  1,
+                      pre_delim_err_warning                                   :  1,
+                      receive_queue_number                                    : 16,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      mpdu_retry                                              :  1,
+                      encrypted                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      reserved_11a                                            :  1,
+                      more_fragment_flag                                      :  1,
+                      mpdu_fragment_number                                    :  4,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mpdu_frame_control_valid                                :  1;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      ast_index                                               : 16;
+             uint32_t phy_ppdu_id                                             : 16,
+                      __reserved_g_0035                                                 :  1,
+                      __reserved_g_0022                                                 :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      protocol_version_err                                    :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      phy_err                                                 :  1,
+                      ndp_frame                                               :  1,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_12                                             :  1,
+                      raw_mpdu                                                :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      pre_delim_count                                         : 12,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      decap_type                                              :  2,
+                      decrypt_needed                                          :  1,
+                      new_peer_entry                                          :  1,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_13                                             :  1,
+                      amsdu_present                                           :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      u_apsd_trigger                                          :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      first_mpdu                                              :  1,
+                      mpdu_length                                             : 14;
+             uint32_t mpdu_duration_field                                     : 16,
+                      mpdu_frame_control_field                                : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad2_15_0                                       : 16,
+                      mac_addr_ad1_47_32                                      : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mpdu_sequence_control_field                             : 16,
+                      mac_addr_ad3_47_32                                      : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mpdu_qos_control_field                                  : 16,
+                      mac_addr_ad4_47_32                                      : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t __reserved_g_0006                                       :  1,
+                      reserved_23a                                            :  1,
+                      src_info                                                : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      vdev_id                                                 :  8;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t reserved_27a                                            :  5,
+                      multi_link_addr_ctrl_en                                 :  1,
+                      multi_link_addr_mgmt_en                                 :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_ad3_valid                               :  1,
+                      multi_link_addr_fromtods_non00_raw_en                   :  1,
+                      multi_link_addr_fromtods_00_raw_en                      :  1,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      rx_misc_config                                          :  3,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      authorized_to_send_wds                                  :  1;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t reserved_29a                                            : 16,
+                      multi_link_addr_ad3_47_32                               : 16;
+#endif
+};
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET   0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB      0
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB      4
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK     0x0000001f
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET             0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB                5
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB                6
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK               0x00000060
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET    0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK      0x00000080
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK    0x00000100
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK    0x00000200
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET        0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK          0x00000400
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB    11
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB    13
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK   0x00003800
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK         0x00020000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK         0x00040000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK              0x00080000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET                      0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK                        0x00100000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET           0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK             0x00200000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK              0x00400000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET                  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB                     23
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB                     31
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK                    0xff800000
+
+#define RX_MPDU_INFO_EPD_EN_OFFSET                                                  0x00000004
+#define RX_MPDU_INFO_EPD_EN_LSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MASK                                                    0x00000001
+
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET                           0x00000004
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK                             0x00000002
+
+#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB                                               2
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB                                               5
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK                                              0x0000003c
+
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET                          0x00000004
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB                             6
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB                             7
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK                            0x000000c0
+
+#define RX_MPDU_INFO_BSSID_HIT_OFFSET                                               0x00000004
+#define RX_MPDU_INFO_BSSID_HIT_LSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MASK                                                 0x00000400
+
+#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_BSSID_NUMBER_LSB                                               11
+#define RX_MPDU_INFO_BSSID_NUMBER_MSB                                               14
+#define RX_MPDU_INFO_BSSID_NUMBER_MASK                                              0x00007800
+
+#define RX_MPDU_INFO_TID_OFFSET                                                     0x00000004
+#define RX_MPDU_INFO_TID_LSB                                                        15
+#define RX_MPDU_INFO_TID_MSB                                                        18
+#define RX_MPDU_INFO_TID_MASK                                                       0x00078000
+
+#define RX_MPDU_INFO_RESERVED_7A_OFFSET                                             0x00000004
+#define RX_MPDU_INFO_RESERVED_7A_LSB                                                19
+#define RX_MPDU_INFO_RESERVED_7A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_7A_MASK                                               0xfff80000
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                             0x00000008
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                                0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                                31
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                            0x0000000c
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                               0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                               7
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                              0x000000ff
+
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x0000000c
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB                                       8
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB                                       23
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK                                      0x00ffff00
+
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET                                   0x0000000c
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK                                     0x01000000
+
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET                                         0x0000000c
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK                                           0x02000000
+
+#define RX_MPDU_INFO_RESERVED_2A_OFFSET                                             0x0000000c
+#define RX_MPDU_INFO_RESERVED_2A_LSB                                                26
+#define RX_MPDU_INFO_RESERVED_2A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_2A_MASK                                               0xfc000000
+
+#define RX_MPDU_INFO_PN_31_0_OFFSET                                                 0x00000010
+#define RX_MPDU_INFO_PN_31_0_LSB                                                    0
+#define RX_MPDU_INFO_PN_31_0_MSB                                                    31
+#define RX_MPDU_INFO_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_MPDU_INFO_PN_63_32_OFFSET                                                0x00000014
+#define RX_MPDU_INFO_PN_63_32_LSB                                                   0
+#define RX_MPDU_INFO_PN_63_32_MSB                                                   31
+#define RX_MPDU_INFO_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_95_64_OFFSET                                                0x00000018
+#define RX_MPDU_INFO_PN_95_64_LSB                                                   0
+#define RX_MPDU_INFO_PN_95_64_MSB                                                   31
+#define RX_MPDU_INFO_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_127_96_OFFSET                                               0x0000001c
+#define RX_MPDU_INFO_PN_127_96_LSB                                                  0
+#define RX_MPDU_INFO_PN_127_96_MSB                                                  31
+#define RX_MPDU_INFO_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET                                0x00000020
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK                                  0x00000001
+
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET                                     0x00000020
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK                                       0x00000002
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK                                        0x00000004
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK                                        0x00000008
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK                                        0x00000010
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK                                        0x00000020
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK                               0x00000040
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                                  0x00000020
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK                                    0x00000080
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET                                   0x00000020
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK                                     0x00000100
+
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK                               0x00000200
+
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB                                       10
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB                                       13
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK                                      0x00003c00
+
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK                                        0x00004000
+
+#define RX_MPDU_INFO_RESERVED_11A_OFFSET                                            0x00000020
+#define RX_MPDU_INFO_RESERVED_11A_LSB                                               15
+#define RX_MPDU_INFO_RESERVED_11A_MSB                                               15
+#define RX_MPDU_INFO_RESERVED_11A_MASK                                              0x00008000
+
+#define RX_MPDU_INFO_FR_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_FR_DS_LSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MASK                                                     0x00010000
+
+#define RX_MPDU_INFO_TO_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_TO_DS_LSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MASK                                                     0x00020000
+
+#define RX_MPDU_INFO_ENCRYPTED_OFFSET                                               0x00000020
+#define RX_MPDU_INFO_ENCRYPTED_LSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MASK                                                 0x00040000
+
+#define RX_MPDU_INFO_MPDU_RETRY_OFFSET                                              0x00000020
+#define RX_MPDU_INFO_MPDU_RETRY_LSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MASK                                                0x00080000
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB                                       20
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB                                       31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK                                      0xfff00000
+
+#define RX_MPDU_INFO_PEER_META_DATA_OFFSET                                          0x00000024
+#define RX_MPDU_INFO_PEER_META_DATA_LSB                                             0
+#define RX_MPDU_INFO_PEER_META_DATA_MSB                                             31
+#define RX_MPDU_INFO_PEER_META_DATA_MASK                                            0xffffffff
+
+#define RX_MPDU_INFO_AST_INDEX_OFFSET                                               0x00000028
+#define RX_MPDU_INFO_AST_INDEX_LSB                                                  0
+#define RX_MPDU_INFO_AST_INDEX_MSB                                                  15
+#define RX_MPDU_INFO_AST_INDEX_MASK                                                 0x0000ffff
+
+#define RX_MPDU_INFO_SW_PEER_ID_OFFSET                                              0x00000028
+#define RX_MPDU_INFO_SW_PEER_ID_LSB                                                 16
+#define RX_MPDU_INFO_SW_PEER_ID_MSB                                                 31
+#define RX_MPDU_INFO_SW_PEER_ID_MASK                                                0xffff0000
+
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000002c
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x00000003
+
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET                                       0x0000002c
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK                                         0x000001fc
+
+#define RX_MPDU_INFO_NDP_FRAME_OFFSET                                               0x0000002c
+#define RX_MPDU_INFO_NDP_FRAME_LSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MASK                                                 0x00000200
+
+#define RX_MPDU_INFO_PHY_ERR_OFFSET                                                 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_LSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MASK                                                   0x00000400
+
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET                              0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK                                0x00000800
+
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET                                    0x0000002c
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK                                      0x00001000
+
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET                                  0x0000002c
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK                                    0x00002000
+
+#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET                                             0x0000002c
+#define RX_MPDU_INFO_PHY_PPDU_ID_LSB                                                16
+#define RX_MPDU_INFO_PHY_PPDU_ID_MSB                                                31
+#define RX_MPDU_INFO_PHY_PPDU_ID_MASK                                               0xffff0000
+
+#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET                                            0x00000030
+#define RX_MPDU_INFO_KEY_ID_OCTET_LSB                                               0
+#define RX_MPDU_INFO_KEY_ID_OCTET_MSB                                               7
+#define RX_MPDU_INFO_KEY_ID_OCTET_MASK                                              0x000000ff
+
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK                                            0x00000100
+
+#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK                                            0x00000200
+
+#define RX_MPDU_INFO_DECAP_TYPE_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_DECAP_TYPE_LSB                                                 10
+#define RX_MPDU_INFO_DECAP_TYPE_MSB                                                 11
+#define RX_MPDU_INFO_DECAP_TYPE_MASK                                                0x00000c00
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK                              0x00001000
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK                              0x00002000
+
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK                                    0x00004000
+
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK                                    0x00008000
+
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET                                         0x00000030
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB                                            16
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB                                            27
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK                                           0x0fff0000
+
+#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_AMPDU_FLAG_LSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MASK                                                0x10000000
+
+#define RX_MPDU_INFO_BAR_FRAME_OFFSET                                               0x00000030
+#define RX_MPDU_INFO_BAR_FRAME_LSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MASK                                                 0x20000000
+
+#define RX_MPDU_INFO_RAW_MPDU_OFFSET                                                0x00000030
+#define RX_MPDU_INFO_RAW_MPDU_LSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MASK                                                  0x40000000
+
+#define RX_MPDU_INFO_RESERVED_12_OFFSET                                             0x00000030
+#define RX_MPDU_INFO_RESERVED_12_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MPDU_LENGTH_LSB                                                0
+#define RX_MPDU_INFO_MPDU_LENGTH_MSB                                                13
+#define RX_MPDU_INFO_MPDU_LENGTH_MASK                                               0x00003fff
+
+#define RX_MPDU_INFO_FIRST_MPDU_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_FIRST_MPDU_LSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MASK                                                0x00004000
+
+#define RX_MPDU_INFO_MCAST_BCAST_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MCAST_BCAST_LSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MASK                                               0x00008000
+
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET                                     0x00000034
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK                                       0x00010000
+
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET                                       0x00000034
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK                                         0x00020000
+
+#define RX_MPDU_INFO_POWER_MGMT_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_POWER_MGMT_LSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MASK                                                0x00040000
+
+#define RX_MPDU_INFO_NON_QOS_OFFSET                                                 0x00000034
+#define RX_MPDU_INFO_NON_QOS_LSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MASK                                                   0x00080000
+
+#define RX_MPDU_INFO_NULL_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_NULL_DATA_LSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MASK                                                 0x00100000
+
+#define RX_MPDU_INFO_MGMT_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MGMT_TYPE_LSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MASK                                                 0x00200000
+
+#define RX_MPDU_INFO_CTRL_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_CTRL_TYPE_LSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MASK                                                 0x00400000
+
+#define RX_MPDU_INFO_MORE_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MORE_DATA_LSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MASK                                                 0x00800000
+
+#define RX_MPDU_INFO_EOSP_OFFSET                                                    0x00000034
+#define RX_MPDU_INFO_EOSP_LSB                                                       24
+#define RX_MPDU_INFO_EOSP_MSB                                                       24
+#define RX_MPDU_INFO_EOSP_MASK                                                      0x01000000
+
+#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK                                             0x02000000
+
+#define RX_MPDU_INFO_ORDER_OFFSET                                                   0x00000034
+#define RX_MPDU_INFO_ORDER_LSB                                                      26
+#define RX_MPDU_INFO_ORDER_MSB                                                      26
+#define RX_MPDU_INFO_ORDER_MASK                                                     0x04000000
+
+#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET                                          0x00000034
+#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK                                            0x08000000
+
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET                                        0x00000034
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK                                          0x10000000
+
+#define RX_MPDU_INFO_DIRECTED_OFFSET                                                0x00000034
+#define RX_MPDU_INFO_DIRECTED_LSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MASK                                                  0x20000000
+
+#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_AMSDU_PRESENT_LSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MASK                                             0x40000000
+
+#define RX_MPDU_INFO_RESERVED_13_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_RESERVED_13_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET                                0x00000038
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB                                   15
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK                                  0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET                                     0x00000038
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB                                        16
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB                                        31
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK                                       0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET                                       0x0000003c
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET                                      0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET                                       0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB                                          16
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK                                         0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET                                      0x00000044
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB                                         31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK                                        0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET                                       0x00000048
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET                                      0x0000004c
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET                             0x0000004c
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB                                16
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB                                31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK                               0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET                                       0x00000050
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET                                      0x00000054
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET                                  0x00000054
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB                                     16
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB                                     31
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK                                    0xffff0000
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET                                   0x00000058
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB                                      0
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB                                      31
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK                                     0xffffffff
+
+#define RX_MPDU_INFO_VDEV_ID_OFFSET                                                 0x0000005c
+#define RX_MPDU_INFO_VDEV_ID_LSB                                                    0
+#define RX_MPDU_INFO_VDEV_ID_MSB                                                    7
+#define RX_MPDU_INFO_VDEV_ID_MASK                                                   0x000000ff
+
+#define RX_MPDU_INFO_SERVICE_CODE_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_SERVICE_CODE_LSB                                               8
+#define RX_MPDU_INFO_SERVICE_CODE_MSB                                               16
+#define RX_MPDU_INFO_SERVICE_CODE_MASK                                              0x0001ff00
+
+#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET                                          0x0000005c
+#define RX_MPDU_INFO_PRIORITY_VALID_LSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_SRC_INFO_OFFSET                                                0x0000005c
+#define RX_MPDU_INFO_SRC_INFO_LSB                                                   18
+#define RX_MPDU_INFO_SRC_INFO_MSB                                                   29
+#define RX_MPDU_INFO_SRC_INFO_MASK                                                  0x3ffc0000
+
+#define RX_MPDU_INFO_RESERVED_23A_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_RESERVED_23A_LSB                                               30
+#define RX_MPDU_INFO_RESERVED_23A_MSB                                               30
+#define RX_MPDU_INFO_RESERVED_23A_MASK                                              0x40000000
+
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK                                    0x00000001
+
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET                        0x0000006c
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK                          0x00000002
+
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK                                 0x00000004
+
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK                                 0x00000008
+
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK                                 0x00000010
+
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK                                 0x00000020
+
+#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET                                          0x0000006c
+#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB                                             6
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB                                             8
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK                                            0x000001c0
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB                                     9
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB                                     10
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK                                    0x00000600
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB                                     11
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB                                     12
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK                                    0x00001800
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB                                     13
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB                                     14
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK                                    0x00006000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET                      0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB                         15
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB                         15
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK                        0x00008000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB                      16
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB                      16
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK                     0x00010000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_LSB                                  17
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MSB                                  17
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MASK                                 0x00020000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                     0x00040000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                          0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                            0x00080000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                           0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                             0x00100000
+
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB                                       21
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB                                       22
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK                                      0x00600000
+
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB                                       23
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB                                       24
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK                                      0x01800000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_OFFSET                                 0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_LSB                                    25
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MSB                                    25
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MASK                                   0x02000000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_OFFSET                                 0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_LSB                                    26
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MSB                                    26
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MASK                                   0x04000000
+
+#define RX_MPDU_INFO_RESERVED_27A_OFFSET                                            0x0000006c
+#define RX_MPDU_INFO_RESERVED_27A_LSB                                               27
+#define RX_MPDU_INFO_RESERVED_27A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_27A_MASK                                              0xf8000000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_OFFSET                                0x00000070
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_LSB                                   0
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MSB                                   31
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MASK                                  0xffffffff
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_OFFSET                               0x00000074
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_LSB                                  0
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MSB                                  15
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MASK                                 0x0000ffff
+
+#define RX_MPDU_INFO_RESERVED_29A_OFFSET                                            0x00000074
+#define RX_MPDU_INFO_RESERVED_29A_LSB                                               16
+#define RX_MPDU_INFO_RESERVED_29A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_29A_MASK                                              0xffff0000
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_link_ptr.h b/hw/fig/v1/rx_mpdu_link_ptr.h
new file mode 100644
index 000000000000..e9d7e83a92cc
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_link_ptr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#else
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#endif
+};
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB              0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB             0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB             7
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB         8
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB         11
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB              12
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#endif
diff --git a/hw/fig/v1/rx_mpdu_start.h b/hw/fig/v1/rx_mpdu_start.h
new file mode 100644
index 000000000000..3f98c5b7377d
--- /dev/null
+++ b/hw/fig/v1/rx_mpdu_start.h
@@ -0,0 +1,702 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+
+#include "rx_mpdu_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_START 30
+
+#define NUM_OF_QWORDS_RX_MPDU_START 15
+
+struct rx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#else
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#endif
+};
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK  0x0000000000100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET                            0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK                              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET     0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK       0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB                         34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB                         37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK                        0x0000003c00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET    0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB       39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK      0x000000c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET                         0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK                           0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB                         43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB                         46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK                        0x0000780000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET                               0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB                                  47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB                                  50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK                                 0x0007800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET                       0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB                          51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK                         0xfff8000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB         39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET              0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB                 40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK                0x00ffff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET             0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK               0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET                   0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK                     0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET                       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB                          58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK                         0xfc00000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET                           0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB                              0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB                              31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK                             0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET                          0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB                             32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB                             63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK                            0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET                          0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB                             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB                             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK                            0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET                         0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB                            32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB                            63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK                           0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET          0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK            0x0000000000000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET               0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK                 0x0000000000000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK                  0x0000000000000004
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK                  0x0000000000000008
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK                  0x0000000000000010
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK                  0x0000000000000020
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK         0x0000000000000040
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET            0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK              0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK               0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK         0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB                 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB                 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK                0x0000000000003c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK                  0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET                      0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB                         15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB                         15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK                        0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK                               0x0000000000010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK                               0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET                         0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK                           0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET                        0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK                          0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB                 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB                 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK                0x00000000fff00000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET                    0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB                       32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB                       63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK                      0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB                            0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB                            15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK                           0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET                        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB                           16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB                           31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK                          0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET     0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB        32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK       0x0000000300000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET                 0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB                    34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB                    40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK                   0x000001fc00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK                           0x0000020000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET                           0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK                             0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK          0x0000080000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET              0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK                0x0000100000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET            0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK              0x0000200000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET                       0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK                         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET                      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB                         7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK                        0x00000000000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK                      0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK                      0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB                           10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB                           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK                          0x0000000000000c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK        0x0000000000001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK        0x0000000000002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK              0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK              0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET                   0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB                      16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB                      27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK                     0x000000000fff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK                          0x0000000010000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK                           0x0000000020000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK                            0x0000000040000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK                         0x0000000080000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB                          32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB                          45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK                         0x00003fff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK                          0x0000400000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK                         0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET               0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK                 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET                 0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK                   0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK                          0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET                           0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK                             0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK                           0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK                           0x0020000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK                           0x0040000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK                           0x0080000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET                              0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK                                0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK                       0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET                             0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK                               0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK                      0x0800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET                  0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK                    0x1000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK                            0x2000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK                       0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK                         0x8000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET          0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB             15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK            0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET               0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB                  31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK                 0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET                 0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB                    32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB                    63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK                   0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK                  0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET                 0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB                    16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK                   0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB                   63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK                  0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET                 0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET                0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET       0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET                 0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET                0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET            0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB               48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB               63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK              0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET             0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB                0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB                31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK               0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET                           0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB                              32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB                              39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK                             0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET                      0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB                         40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB                         48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK                        0x0001ff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET                    0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK                      0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET                          0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB                             50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK                            0x3ffc000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET                      0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB                         62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB                         62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK                        0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET  0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK    0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK           0x0000000400000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK           0x0000000800000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK           0x0000001000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK           0x0000002000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET                    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB                       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB                       40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK                      0x000001c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB               41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB               42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK              0x0000060000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB               43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB               44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK              0x0000180000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB               46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK              0x0000600000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK  0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_LSB            49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MSB            49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MASK           0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK      0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET     0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK       0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB                 53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB                 54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK                0x0060000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK                0x0180000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_OFFSET           0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_LSB              57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MSB              57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MASK             0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_OFFSET           0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_LSB              58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MSB              58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MASK             0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET                      0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB                         59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK                        0xf800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_OFFSET          0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MSB             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MASK            0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_OFFSET         0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_LSB            32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MSB            47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MASK           0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET                      0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB                         48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK                        0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_desc_info.h b/hw/fig/v1/rx_msdu_desc_info.h
new file mode 100644
index 000000000000..88569b653b64
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_desc_info.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
+
+struct rx_msdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t first_msdu_in_mpdu_flag                                 :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      msdu_continuation                                       :  1,
+                      msdu_length                                             : 14,
+                      msdu_drop                                               :  1,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding_msb                                   :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      decap_format                                            :  2,
+                      __reserved_g_0015                                       :  1;
+#else
+             uint32_t __reserved_g_0015                                       :  1,
+                      decap_format                                            :  2,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      l3_header_padding_msb                                   :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      msdu_drop                                               :  1,
+                      msdu_length                                             : 14,
+                      msdu_continuation                                       :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      first_msdu_in_mpdu_flag                                 :  1;
+#endif
+};
+
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET                            0x00000000
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK                              0x00000001
+
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET                             0x00000000
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK                               0x00000002
+
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET                                  0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK                                    0x00000004
+
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB                                           3
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB                                           16
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK                                          0x0001fff8
+
+#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK                                            0x00020000
+
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK                                          0x00040000
+
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK                                          0x00080000
+
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET                                         0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK                                           0x00100000
+
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET                              0x00000000
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK                                0x00200000
+
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET                                0x00000000
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK                                  0x00400000
+
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET                                     0x00000000
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK                                       0x00800000
+
+#define RX_MSDU_DESC_INFO_FR_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_FR_DS_LSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MASK                                                0x01000000
+
+#define RX_MSDU_DESC_INFO_TO_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_TO_DS_LSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MASK                                                0x02000000
+
+#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK                                            0x04000000
+
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB                                          27
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB                                          28
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK                                         0x18000000
+
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB                                          29
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB                                          30
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK                                         0x60000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_details.h b/hw/fig/v1/rx_msdu_details.h
new file mode 100644
index 000000000000..0b763a473ce6
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_details.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_ext_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB               0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB              0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB              7
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB               12
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET    0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK      0x00000001
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET     0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK       0x00000002
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET          0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK            0x00000004
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB                   3
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB                   16
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK                  0x0001fff8
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                    0x00020000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK                  0x00040000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK                  0x00080000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET                 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK                   0x00100000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK        0x00200000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET        0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK          0x00400000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK               0x00800000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                        0x01000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                        0x02000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                    0x04000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB                  27
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB                  28
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK                 0x18000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB                   29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB                   31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK                  0xe0000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB                  29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET           0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB              5
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB              13
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK             0x00003fe0
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET         0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK           0x00004000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB               15
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB               26
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK              0x07ff8000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB               27
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB               29
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK              0x38000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB               30
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB               31
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK              0xc0000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_end.h b/hw/fig/v1/rx_msdu_end.h
new file mode 100644
index 000000000000..34753b47edc7
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_end.h
@@ -0,0 +1,1087 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_END 32
+
+#define NUM_OF_QWORDS_RX_MSDU_END 16
+
+struct rx_msdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ip_hdr_chksum                                           : 16,
+                      reported_mpdu_length                                    : 14,
+                      reserved_1a                                             :  2;
+             uint32_t reserved_2a                                             :  8,
+                      cce_super_rule                                          :  6,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cumulative_l3_checksum                                  : 16;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t da_offset                                               :  6,
+                      sa_offset                                               :  6,
+                      da_offset_valid                                         :  1,
+                      sa_offset_valid                                         :  1,
+                      reserved_5a                                             :  2,
+                      l3_type                                                 : 16;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t tcp_flag                                                :  9,
+                      lro_eligible                                            :  1,
+                      reserved_9a                                             :  6,
+                      window_size                                             : 16;
+             uint32_t sa_sw_peer_id                                           : 16,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      to_ds                                                   :  1,
+                      tid                                                     :  4,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding                                       :  2,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail_copy                                     :  1;
+             uint32_t sa_idx                                                  : 16,
+                      da_idx_or_sw_peer_id                                    : 16;
+             uint32_t msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      flow_idx                                                : 20,
+                      use_ppe                                                 :  1,
+                      __reserved_g_0003                                                :  2,
+                      vlan_ctag_stripped                                      :  1,
+                      vlan_stag_stripped                                      :  1,
+                      fragment_flag                                           :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t cce_metadata                                            : 16,
+                      tcp_udp_chksum                                          : 16;
+             uint32_t aggregation_count                                       :  8,
+                      flow_aggregation_continuation                           :  1,
+                      fisa_timeout                                            :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      msdu_limit_error                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      cce_match                                               :  1,
+                      amsdu_parser_error                                      :  1,
+                      cumulative_ip_length                                    : 16;
+             uint32_t key_id_octet                                            :  8,
+                      reserved_16a                                            : 24;
+             uint32_t reserved_17a                                            :  6,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      multicast_echo                                          :  1,
+                      wds_learning_event                                      :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      __reserved_g_0015                                       :  1,
+                      reserved_17b                                            :  8;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  6,
+                      msdu_done_copy                                          :  1;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t reserved_28a                                            : 16,
+                      sa_15_0                                                 : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_30a                                            :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      reserved_30b                                            :  1,
+                      order                                                   :  1,
+                      wifi_parser_error                                       :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t reserved_31a                                            : 10,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_31b                                            : 17,
+                      msdu_done                                               :  1;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1a                                             :  2,
+                      reported_mpdu_length                                    : 14,
+                      ip_hdr_chksum                                           : 16;
+             uint32_t cumulative_l3_checksum                                  : 16,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_super_rule                                          :  6,
+                      reserved_2a                                             :  8;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             :  2,
+                      sa_offset_valid                                         :  1,
+                      da_offset_valid                                         :  1,
+                      sa_offset                                               :  6,
+                      da_offset                                               :  6;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t window_size                                             : 16,
+                      reserved_9a                                             :  6,
+                      lro_eligible                                            :  1,
+                      tcp_flag                                                :  9;
+             uint32_t ip_chksum_fail_copy                                     :  1,
+                      fr_ds                                                   :  1,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      l3_header_padding                                       :  2,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      tid                                                     :  4,
+                      to_ds                                                   :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      sa_sw_peer_id                                           : 16;
+             uint32_t da_idx_or_sw_peer_id                                    : 16,
+                      sa_idx                                                  : 16;
+             uint32_t fragment_flag                                           :  1,
+                      vlan_stag_stripped                                      :  1,
+                      vlan_ctag_stripped                                      :  1,
+                      __reserved_g_0003                                                :  2,
+                      use_ppe                                                 :  1,
+                      flow_idx                                                : 20,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t tcp_udp_chksum                                          : 16,
+                      cce_metadata                                            : 16;
+             uint32_t cumulative_ip_length                                    : 16,
+                      amsdu_parser_error                                      :  1,
+                      cce_match                                               :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      msdu_limit_error                                        :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      fisa_timeout                                            :  1,
+                      flow_aggregation_continuation                           :  1,
+                      aggregation_count                                       :  8;
+             uint32_t reserved_16a                                            : 24,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_17b                                            :  8,
+                      __reserved_g_0015                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_learning_event                                      :  1,
+                      multicast_echo                                          :  1,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_17a                                            :  6;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t msdu_done_copy                                          :  1,
+                      mimo_ss_bitmap                                          :  6,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t sa_15_0                                                 : 16,
+                      reserved_28a                                            : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      wifi_parser_error                                       :  1,
+                      order                                                   :  1,
+                      reserved_30b                                            :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_30a                                            :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_31b                                            : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved_31a                                            : 10;
+#endif
+};
+
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MSDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MSDU_END_RESERVED_0_LSB                                                  9
+#define RX_MSDU_END_RESERVED_0_MSB                                                  15
+#define RX_MSDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MSDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MSDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MSDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET                                            0x0000000000000000
+#define RX_MSDU_END_IP_HDR_CHKSUM_LSB                                               32
+#define RX_MSDU_END_IP_HDR_CHKSUM_MSB                                               47
+#define RX_MSDU_END_IP_HDR_CHKSUM_MASK                                              0x0000ffff00000000
+
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET                                     0x0000000000000000
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB                                        48
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB                                        61
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK                                       0x3fff000000000000
+
+#define RX_MSDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_RESERVED_1A_LSB                                                 62
+#define RX_MSDU_END_RESERVED_1A_MSB                                                 63
+#define RX_MSDU_END_RESERVED_1A_MASK                                                0xc000000000000000
+
+#define RX_MSDU_END_RESERVED_2A_OFFSET                                              0x0000000000000008
+#define RX_MSDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MSDU_END_RESERVED_2A_MSB                                                 7
+#define RX_MSDU_END_RESERVED_2A_MASK                                                0x00000000000000ff
+
+#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET                                           0x0000000000000008
+#define RX_MSDU_END_CCE_SUPER_RULE_LSB                                              8
+#define RX_MSDU_END_CCE_SUPER_RULE_MSB                                              13
+#define RX_MSDU_END_CCE_SUPER_RULE_MASK                                             0x0000000000003f00
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET                           0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK                             0x0000000000004000
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET                            0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK                              0x0000000000008000
+
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET                                   0x0000000000000008
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB                                      16
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB                                      31
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK                                     0x00000000ffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET                                     0x0000000000000008
+#define RX_MSDU_END_RULE_INDICATION_31_0_LSB                                        32
+#define RX_MSDU_END_RULE_INDICATION_31_0_MSB                                        63
+#define RX_MSDU_END_RULE_INDICATION_31_0_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET                                         0x0000000000000010
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB                                            0
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB                                            31
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK                                           0x00000000ffffffff
+
+#define RX_MSDU_END_DA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_LSB                                                   32
+#define RX_MSDU_END_DA_OFFSET_MSB                                                   37
+#define RX_MSDU_END_DA_OFFSET_MASK                                                  0x0000003f00000000
+
+#define RX_MSDU_END_SA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_LSB                                                   38
+#define RX_MSDU_END_SA_OFFSET_MSB                                                   43
+#define RX_MSDU_END_SA_OFFSET_MASK                                                  0x00000fc000000000
+
+#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_VALID_LSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MASK                                            0x0000100000000000
+
+#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_VALID_LSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MASK                                            0x0000200000000000
+
+#define RX_MSDU_END_RESERVED_5A_OFFSET                                              0x0000000000000010
+#define RX_MSDU_END_RESERVED_5A_LSB                                                 46
+#define RX_MSDU_END_RESERVED_5A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_5A_MASK                                                0x0000c00000000000
+
+#define RX_MSDU_END_L3_TYPE_OFFSET                                                  0x0000000000000010
+#define RX_MSDU_END_L3_TYPE_LSB                                                     48
+#define RX_MSDU_END_L3_TYPE_MSB                                                     63
+#define RX_MSDU_END_L3_TYPE_MASK                                                    0xffff000000000000
+
+#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET                                    0x0000000000000018
+#define RX_MSDU_END_RULE_INDICATION_63_32_LSB                                       0
+#define RX_MSDU_END_RULE_INDICATION_63_32_MSB                                       31
+#define RX_MSDU_END_RULE_INDICATION_63_32_MASK                                      0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET                                           0x0000000000000018
+#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB                                              32
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB                                              63
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET                                           0x0000000000000020
+#define RX_MSDU_END_TCP_ACK_NUMBER_LSB                                              0
+#define RX_MSDU_END_TCP_ACK_NUMBER_MSB                                              31
+#define RX_MSDU_END_TCP_ACK_NUMBER_MASK                                             0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_FLAG_OFFSET                                                 0x0000000000000020
+#define RX_MSDU_END_TCP_FLAG_LSB                                                    32
+#define RX_MSDU_END_TCP_FLAG_MSB                                                    40
+#define RX_MSDU_END_TCP_FLAG_MASK                                                   0x000001ff00000000
+
+#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET                                             0x0000000000000020
+#define RX_MSDU_END_LRO_ELIGIBLE_LSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_RESERVED_9A_LSB                                                 42
+#define RX_MSDU_END_RESERVED_9A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_9A_MASK                                                0x0000fc0000000000
+
+#define RX_MSDU_END_WINDOW_SIZE_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_WINDOW_SIZE_LSB                                                 48
+#define RX_MSDU_END_WINDOW_SIZE_MSB                                                 63
+#define RX_MSDU_END_WINDOW_SIZE_MASK                                                0xffff000000000000
+
+#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET                                            0x0000000000000028
+#define RX_MSDU_END_SA_SW_PEER_ID_LSB                                               0
+#define RX_MSDU_END_SA_SW_PEER_ID_MSB                                               15
+#define RX_MSDU_END_SA_SW_PEER_ID_MASK                                              0x000000000000ffff
+
+#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK                                             0x0000000000010000
+
+#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK                                             0x0000000000020000
+
+#define RX_MSDU_END_TO_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_TO_DS_LSB                                                       18
+#define RX_MSDU_END_TO_DS_MSB                                                       18
+#define RX_MSDU_END_TO_DS_MASK                                                      0x0000000000040000
+
+#define RX_MSDU_END_TID_OFFSET                                                      0x0000000000000028
+#define RX_MSDU_END_TID_LSB                                                         19
+#define RX_MSDU_END_TID_MSB                                                         22
+#define RX_MSDU_END_TID_MASK                                                        0x0000000000780000
+
+#define RX_MSDU_END_SA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_SA_IS_VALID_LSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MASK                                                0x0000000000800000
+
+#define RX_MSDU_END_DA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_DA_IS_VALID_LSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MASK                                                0x0000000001000000
+
+#define RX_MSDU_END_DA_IS_MCBC_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_DA_IS_MCBC_LSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MASK                                                 0x0000000002000000
+
+#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET                                        0x0000000000000028
+#define RX_MSDU_END_L3_HEADER_PADDING_LSB                                           26
+#define RX_MSDU_END_L3_HEADER_PADDING_MSB                                           27
+#define RX_MSDU_END_L3_HEADER_PADDING_MASK                                          0x000000000c000000
+
+#define RX_MSDU_END_FIRST_MSDU_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_FIRST_MSDU_LSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MASK                                                 0x0000000010000000
+
+#define RX_MSDU_END_LAST_MSDU_OFFSET                                                0x0000000000000028
+#define RX_MSDU_END_LAST_MSDU_LSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MASK                                                  0x0000000020000000
+
+#define RX_MSDU_END_FR_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_FR_DS_LSB                                                       30
+#define RX_MSDU_END_FR_DS_MSB                                                       30
+#define RX_MSDU_END_FR_DS_MASK                                                      0x0000000040000000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET                                      0x0000000000000028
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK                                        0x0000000080000000
+
+#define RX_MSDU_END_SA_IDX_OFFSET                                                   0x0000000000000028
+#define RX_MSDU_END_SA_IDX_LSB                                                      32
+#define RX_MSDU_END_SA_IDX_MSB                                                      47
+#define RX_MSDU_END_SA_IDX_MASK                                                     0x0000ffff00000000
+
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET                                     0x0000000000000028
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB                                        48
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB                                        63
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_MSDU_DROP_OFFSET                                                0x0000000000000030
+#define RX_MSDU_END_MSDU_DROP_LSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MASK                                                  0x0000000000000001
+
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET                               0x0000000000000030
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB                                  1
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB                                  5
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK                                 0x000000000000003e
+
+#define RX_MSDU_END_FLOW_IDX_OFFSET                                                 0x0000000000000030
+#define RX_MSDU_END_FLOW_IDX_LSB                                                    6
+#define RX_MSDU_END_FLOW_IDX_MSB                                                    25
+#define RX_MSDU_END_FLOW_IDX_MASK                                                   0x0000000003ffffc0
+
+#define RX_MSDU_END_USE_PPE_OFFSET                                                  0x0000000000000030
+#define RX_MSDU_END_USE_PPE_LSB                                                     26
+#define RX_MSDU_END_USE_PPE_MSB                                                     26
+#define RX_MSDU_END_USE_PPE_MASK                                                    0x0000000004000000
+
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK                                         0x0000000020000000
+
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK                                         0x0000000040000000
+
+#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET                                            0x0000000000000030
+#define RX_MSDU_END_FRAGMENT_FLAG_LSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MASK                                              0x0000000080000000
+
+#define RX_MSDU_END_FSE_METADATA_OFFSET                                             0x0000000000000030
+#define RX_MSDU_END_FSE_METADATA_LSB                                                32
+#define RX_MSDU_END_FSE_METADATA_MSB                                                63
+#define RX_MSDU_END_FSE_METADATA_MASK                                               0xffffffff00000000
+
+#define RX_MSDU_END_CCE_METADATA_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_CCE_METADATA_LSB                                                0
+#define RX_MSDU_END_CCE_METADATA_MSB                                                15
+#define RX_MSDU_END_CCE_METADATA_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET                                           0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB                                              16
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB                                              31
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK                                             0x00000000ffff0000
+
+#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET                                        0x0000000000000038
+#define RX_MSDU_END_AGGREGATION_COUNT_LSB                                           32
+#define RX_MSDU_END_AGGREGATION_COUNT_MSB                                           39
+#define RX_MSDU_END_AGGREGATION_COUNT_MASK                                          0x000000ff00000000
+
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET                            0x0000000000000038
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK                              0x0000010000000000
+
+#define RX_MSDU_END_FISA_TIMEOUT_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_FISA_TIMEOUT_LSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET                                 0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK                                   0x0000040000000000
+
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK                                           0x0000080000000000
+
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK                                           0x0000100000000000
+
+#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_INVALID_LSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MASK                                           0x0000200000000000
+
+#define RX_MSDU_END_CCE_MATCH_OFFSET                                                0x0000000000000038
+#define RX_MSDU_END_CCE_MATCH_LSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MASK                                                  0x0000400000000000
+
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET                                       0x0000000000000038
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK                                         0x0000800000000000
+
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET                                     0x0000000000000038
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB                                        48
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB                                        63
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_KEY_ID_OCTET_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_KEY_ID_OCTET_LSB                                                0
+#define RX_MSDU_END_KEY_ID_OCTET_MSB                                                7
+#define RX_MSDU_END_KEY_ID_OCTET_MASK                                               0x00000000000000ff
+
+#define RX_MSDU_END_RESERVED_16A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_16A_LSB                                                8
+#define RX_MSDU_END_RESERVED_16A_MSB                                                31
+#define RX_MSDU_END_RESERVED_16A_MASK                                               0x00000000ffffff00
+
+#define RX_MSDU_END_RESERVED_17A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17A_LSB                                                32
+#define RX_MSDU_END_RESERVED_17A_MSB                                                37
+#define RX_MSDU_END_RESERVED_17A_MASK                                               0x0000003f00000000
+
+#define RX_MSDU_END_SERVICE_CODE_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_SERVICE_CODE_LSB                                                38
+#define RX_MSDU_END_SERVICE_CODE_MSB                                                46
+#define RX_MSDU_END_SERVICE_CODE_MASK                                               0x00007fc000000000
+
+#define RX_MSDU_END_PRIORITY_VALID_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_PRIORITY_VALID_LSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MASK                                             0x0000800000000000
+
+#define RX_MSDU_END_INTRA_BSS_OFFSET                                                0x0000000000000040
+#define RX_MSDU_END_INTRA_BSS_LSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MASK                                                  0x0001000000000000
+
+#define RX_MSDU_END_DEST_CHIP_ID_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_DEST_CHIP_ID_LSB                                                49
+#define RX_MSDU_END_DEST_CHIP_ID_MSB                                                50
+#define RX_MSDU_END_DEST_CHIP_ID_MASK                                               0x0006000000000000
+
+#define RX_MSDU_END_MULTICAST_ECHO_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_MULTICAST_ECHO_LSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MASK                                             0x0008000000000000
+
+#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET                                       0x0000000000000040
+#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK                                         0x0010000000000000
+
+#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET                                        0x0000000000000040
+#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK                                          0x0020000000000000
+
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET                                     0x0000000000000040
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_RESERVED_17B_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17B_LSB                                                56
+#define RX_MSDU_END_RESERVED_17B_MSB                                                63
+#define RX_MSDU_END_RESERVED_17B_MASK                                               0xff00000000000000
+
+#define RX_MSDU_END_MSDU_LENGTH_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_LENGTH_LSB                                                 0
+#define RX_MSDU_END_MSDU_LENGTH_MSB                                                 13
+#define RX_MSDU_END_MSDU_LENGTH_MASK                                                0x0000000000003fff
+
+#define RX_MSDU_END_STBC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_STBC_LSB                                                        14
+#define RX_MSDU_END_STBC_MSB                                                        14
+#define RX_MSDU_END_STBC_MASK                                                       0x0000000000004000
+
+#define RX_MSDU_END_IPSEC_ESP_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_IPSEC_ESP_LSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MASK                                                  0x0000000000008000
+
+#define RX_MSDU_END_L3_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L3_OFFSET_LSB                                                   16
+#define RX_MSDU_END_L3_OFFSET_MSB                                                   22
+#define RX_MSDU_END_L3_OFFSET_MASK                                                  0x00000000007f0000
+
+#define RX_MSDU_END_IPSEC_AH_OFFSET                                                 0x0000000000000048
+#define RX_MSDU_END_IPSEC_AH_LSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MASK                                                   0x0000000000800000
+
+#define RX_MSDU_END_L4_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L4_OFFSET_LSB                                                   24
+#define RX_MSDU_END_L4_OFFSET_MSB                                                   31
+#define RX_MSDU_END_L4_OFFSET_MASK                                                  0x00000000ff000000
+
+#define RX_MSDU_END_MSDU_NUMBER_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_NUMBER_LSB                                                 32
+#define RX_MSDU_END_MSDU_NUMBER_MSB                                                 39
+#define RX_MSDU_END_MSDU_NUMBER_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_END_DECAP_FORMAT_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_DECAP_FORMAT_LSB                                                40
+#define RX_MSDU_END_DECAP_FORMAT_MSB                                                41
+#define RX_MSDU_END_DECAP_FORMAT_MASK                                               0x0000030000000000
+
+#define RX_MSDU_END_IPV4_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV4_PROTO_LSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MASK                                                 0x0000040000000000
+
+#define RX_MSDU_END_IPV6_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV6_PROTO_LSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MASK                                                 0x0000080000000000
+
+#define RX_MSDU_END_TCP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_TCP_PROTO_LSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MASK                                                  0x0000100000000000
+
+#define RX_MSDU_END_UDP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_UDP_PROTO_LSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MASK                                                  0x0000200000000000
+
+#define RX_MSDU_END_IP_FRAG_OFFSET                                                  0x0000000000000048
+#define RX_MSDU_END_IP_FRAG_LSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MASK                                                    0x0000400000000000
+
+#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_TCP_ONLY_ACK_LSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MASK                                               0x0000800000000000
+
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK                                          0x0001000000000000
+
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB                                           49
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB                                           50
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK                                          0x0006000000000000
+
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET                                    0x0000000000000048
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK                                      0x0008000000000000
+
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK                                       0x0010000000000000
+
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK                                       0x0020000000000000
+
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_LDPC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_LDPC_LSB                                                        55
+#define RX_MSDU_END_LDPC_MSB                                                        55
+#define RX_MSDU_END_LDPC_MASK                                                       0x0080000000000000
+
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                             0x0000000000000048
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                                56
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                                63
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                               0xff00000000000000
+
+#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_CTAG_CI_LSB                                                0
+#define RX_MSDU_END_VLAN_CTAG_CI_MSB                                                15
+#define RX_MSDU_END_VLAN_CTAG_CI_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_VLAN_STAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_STAG_CI_LSB                                                16
+#define RX_MSDU_END_VLAN_STAG_CI_MSB                                                31
+#define RX_MSDU_END_VLAN_STAG_CI_MASK                                               0x00000000ffff0000
+
+#define RX_MSDU_END_PEER_META_DATA_OFFSET                                           0x0000000000000050
+#define RX_MSDU_END_PEER_META_DATA_LSB                                              32
+#define RX_MSDU_END_PEER_META_DATA_MSB                                              63
+#define RX_MSDU_END_PEER_META_DATA_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_USER_RSSI_OFFSET                                                0x0000000000000058
+#define RX_MSDU_END_USER_RSSI_LSB                                                   0
+#define RX_MSDU_END_USER_RSSI_MSB                                                   7
+#define RX_MSDU_END_USER_RSSI_MASK                                                  0x00000000000000ff
+
+#define RX_MSDU_END_PKT_TYPE_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_PKT_TYPE_LSB                                                    8
+#define RX_MSDU_END_PKT_TYPE_MSB                                                    11
+#define RX_MSDU_END_PKT_TYPE_MASK                                                   0x0000000000000f00
+
+#define RX_MSDU_END_SGI_OFFSET                                                      0x0000000000000058
+#define RX_MSDU_END_SGI_LSB                                                         12
+#define RX_MSDU_END_SGI_MSB                                                         13
+#define RX_MSDU_END_SGI_MASK                                                        0x0000000000003000
+
+#define RX_MSDU_END_RATE_MCS_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_RATE_MCS_LSB                                                    14
+#define RX_MSDU_END_RATE_MCS_MSB                                                    18
+#define RX_MSDU_END_RATE_MCS_MASK                                                   0x000000000007c000
+
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET                                        0x0000000000000058
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB                                           19
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB                                           21
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK                                          0x0000000000380000
+
+#define RX_MSDU_END_RECEPTION_TYPE_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_RECEPTION_TYPE_LSB                                              22
+#define RX_MSDU_END_RECEPTION_TYPE_MSB                                              24
+#define RX_MSDU_END_RECEPTION_TYPE_MASK                                             0x0000000001c00000
+
+#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MIMO_SS_BITMAP_LSB                                              25
+#define RX_MSDU_END_MIMO_SS_BITMAP_MSB                                              30
+#define RX_MSDU_END_MIMO_SS_BITMAP_MASK                                             0x000000007e000000
+
+#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MSDU_DONE_COPY_LSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MASK                                             0x0000000080000000
+
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET                                         0x0000000000000058
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB                                            32
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB                                            63
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET                               0x0000000000000060
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB                                  0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB                                  31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK                                 0x00000000ffffffff
+
+#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET                                         0x0000000000000060
+#define RX_MSDU_END_SW_PHY_META_DATA_LSB                                            32
+#define RX_MSDU_END_SW_PHY_META_DATA_MSB                                            63
+#define RX_MSDU_END_SW_PHY_META_DATA_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET                                0x0000000000000068
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB                                   0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB                                   31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET                                     0x0000000000000068
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB                                        32
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB                                        63
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_RESERVED_28A_OFFSET                                             0x0000000000000070
+#define RX_MSDU_END_RESERVED_28A_LSB                                                0
+#define RX_MSDU_END_RESERVED_28A_MSB                                                15
+#define RX_MSDU_END_RESERVED_28A_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_SA_15_0_OFFSET                                                  0x0000000000000070
+#define RX_MSDU_END_SA_15_0_LSB                                                     16
+#define RX_MSDU_END_SA_15_0_MSB                                                     31
+#define RX_MSDU_END_SA_15_0_MASK                                                    0x00000000ffff0000
+
+#define RX_MSDU_END_SA_47_16_OFFSET                                                 0x0000000000000070
+#define RX_MSDU_END_SA_47_16_LSB                                                    32
+#define RX_MSDU_END_SA_47_16_MSB                                                    63
+#define RX_MSDU_END_SA_47_16_MASK                                                   0xffffffff00000000
+
+#define RX_MSDU_END_FIRST_MPDU_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_FIRST_MPDU_LSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MASK                                                 0x0000000000000001
+
+#define RX_MSDU_END_RESERVED_30A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30A_LSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MASK                                               0x0000000000000002
+
+#define RX_MSDU_END_MCAST_BCAST_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_MCAST_BCAST_LSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MASK                                                0x0000000000000004
+
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK                                        0x0000000000000008
+
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK                                          0x0000000000000010
+
+#define RX_MSDU_END_POWER_MGMT_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_POWER_MGMT_LSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MASK                                                 0x0000000000000020
+
+#define RX_MSDU_END_NON_QOS_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_NON_QOS_LSB                                                     6
+#define RX_MSDU_END_NON_QOS_MSB                                                     6
+#define RX_MSDU_END_NON_QOS_MASK                                                    0x0000000000000040
+
+#define RX_MSDU_END_NULL_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_NULL_DATA_LSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MASK                                                  0x0000000000000080
+
+#define RX_MSDU_END_MGMT_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MGMT_TYPE_LSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MASK                                                  0x0000000000000100
+
+#define RX_MSDU_END_CTRL_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_CTRL_TYPE_LSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MASK                                                  0x0000000000000200
+
+#define RX_MSDU_END_MORE_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MORE_DATA_LSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MASK                                                  0x0000000000000400
+
+#define RX_MSDU_END_EOSP_OFFSET                                                     0x0000000000000078
+#define RX_MSDU_END_EOSP_LSB                                                        11
+#define RX_MSDU_END_EOSP_MSB                                                        11
+#define RX_MSDU_END_EOSP_MASK                                                       0x0000000000000800
+
+#define RX_MSDU_END_A_MSDU_ERROR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_A_MSDU_ERROR_LSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MASK                                               0x0000000000001000
+
+#define RX_MSDU_END_RESERVED_30B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30B_LSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MASK                                               0x0000000000002000
+
+#define RX_MSDU_END_ORDER_OFFSET                                                    0x0000000000000078
+#define RX_MSDU_END_ORDER_LSB                                                       14
+#define RX_MSDU_END_ORDER_MSB                                                       14
+#define RX_MSDU_END_ORDER_MASK                                                      0x0000000000004000
+
+#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK                                          0x0000000000008000
+
+#define RX_MSDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_OVERFLOW_ERR_LSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MASK                                               0x0000000000010000
+
+#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK                                            0x0000000000020000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK                                        0x0000000000040000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK                                             0x0000000000080000
+
+#define RX_MSDU_END_SA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_SA_IDX_INVALID_LSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MASK                                             0x0000000000100000
+
+#define RX_MSDU_END_DA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_DA_IDX_INVALID_LSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MASK                                             0x0000000000200000
+
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK                                        0x0000000000400000
+
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000078
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000000000800000
+
+#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET                                         0x0000000000000078
+#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK                                           0x0000000001000000
+
+#define RX_MSDU_END_DIRECTED_OFFSET                                                 0x0000000000000078
+#define RX_MSDU_END_DIRECTED_LSB                                                    25
+#define RX_MSDU_END_DIRECTED_MSB                                                    25
+#define RX_MSDU_END_DIRECTED_MASK                                                   0x0000000002000000
+
+#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_BUFFER_FRAGMENT_LSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MASK                                            0x0000000004000000
+
+#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000000008000000
+
+#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_TKIP_MIC_ERR_LSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MASK                                               0x0000000010000000
+
+#define RX_MSDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_DECRYPT_ERR_LSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MASK                                                0x0000000020000000
+
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0000000040000000
+
+#define RX_MSDU_END_FCS_ERR_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_FCS_ERR_LSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MASK                                                    0x0000000080000000
+
+#define RX_MSDU_END_RESERVED_31A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31A_LSB                                                32
+#define RX_MSDU_END_RESERVED_31A_MSB                                                41
+#define RX_MSDU_END_RESERVED_31A_MASK                                               0x000003ff00000000
+
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB                                         42
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB                                         44
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK                                        0x00001c0000000000
+
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x0000200000000000
+
+#define RX_MSDU_END_RESERVED_31B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31B_LSB                                                46
+#define RX_MSDU_END_RESERVED_31B_MSB                                                62
+#define RX_MSDU_END_RESERVED_31B_MASK                                               0x7fffc00000000000
+
+#define RX_MSDU_END_MSDU_DONE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MSDU_DONE_LSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MASK                                                  0x8000000000000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_ext_desc_info.h b/hw/fig/v1/rx_msdu_ext_desc_info.h
new file mode 100644
index 000000000000..70bda69ddfec
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_ext_desc_info.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_EXT_DESC_INFO_H_
+#define _RX_MSDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
+
+struct rx_msdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      data_offset                                             : 12,
+                      src_link_id                                             :  3,
+                      reserved_0a                                             :  2;
+#else
+             uint32_t reserved_0a                                             :  2,
+                      src_link_id                                             :  3,
+                      data_offset                                             : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET                     0x00000000
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB                        0
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB                        4
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK                       0x0000001f
+
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET                                   0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB                                      5
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB                                      13
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK                                     0x00003fe0
+
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET                                 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK                                   0x00004000
+
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB                                       15
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB                                       26
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK                                      0x07ff8000
+
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB                                       27
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB                                       29
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK                                      0x38000000
+
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB                                       30
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB                                       31
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK                                      0xc0000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_link.h b/hw/fig/v1/rx_msdu_link.h
new file mode 100644
index 000000000000..c54357dae2ef
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_link.h
@@ -0,0 +1,2051 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+#define NUM_OF_DWORDS_RX_MSDU_LINK 64
+
+struct rx_msdu_link {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#endif
+};
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET          0x00000004
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB             0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK            0xffffffff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET         0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB            0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB            7
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK           0x000000ff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET     0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB        8
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB        11
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK       0x00000f00
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET          0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB             12
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK            0xfffff000
+
+#define RX_MSDU_LINK_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_MSDU_LINK_RESERVED_3A_LSB                                                0
+#define RX_MSDU_LINK_RESERVED_3A_MSB                                                31
+#define RX_MSDU_LINK_RESERVED_3A_MASK                                               0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000010
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000020
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000030
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000040
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000050
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000060
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000070
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000080
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000090
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x000000a0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000b0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000c0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000d0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000e0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000f0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#endif
diff --git a/hw/fig/v1/rx_msdu_start.h b/hw/fig/v1/rx_msdu_start.h
new file mode 100644
index 000000000000..e1e99c027c85
--- /dev/null
+++ b/hw/fig/v1/rx_msdu_start.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_START 10
+
+#define NUM_OF_QWORDS_RX_MSDU_START 5
+
+struct rx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      rate_mcs                                                :  5,
+                      reserved_0                                              :  2,
+                      phy_ppdu_id                                             : 16;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      reserved_5a                                             :  4,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  2,
+                      rate_mcs                                                :  5,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t mimo_ss_bitmap                                          :  8,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      reserved_5a                                             :  4,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+#endif
+};
+
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x0000000000000000
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x0000000000000003
+
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x0000000000000000
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x00000000000001fc
+
+#define RX_MSDU_START_RATE_MCS_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_RATE_MCS_LSB                                                  9
+#define RX_MSDU_START_RATE_MCS_MSB                                                  13
+#define RX_MSDU_START_RATE_MCS_MASK                                                 0x0000000000003e00
+
+#define RX_MSDU_START_RESERVED_0_OFFSET                                             0x0000000000000000
+#define RX_MSDU_START_RESERVED_0_LSB                                                14
+#define RX_MSDU_START_RESERVED_0_MSB                                                15
+#define RX_MSDU_START_RESERVED_0_MASK                                               0x000000000000c000
+
+#define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
+#define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
+#define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0x00000000ffff0000
+
+#define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_MSDU_LENGTH_LSB                                               32
+#define RX_MSDU_START_MSDU_LENGTH_MSB                                               45
+#define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff00000000
+
+#define RX_MSDU_START_STBC_OFFSET                                                   0x0000000000000000
+#define RX_MSDU_START_STBC_LSB                                                      46
+#define RX_MSDU_START_STBC_MSB                                                      46
+#define RX_MSDU_START_STBC_MASK                                                     0x0000400000000000
+
+#define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_IPSEC_ESP_LSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MASK                                                0x0000800000000000
+
+#define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L3_OFFSET_LSB                                                 48
+#define RX_MSDU_START_L3_OFFSET_MSB                                                 54
+#define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f000000000000
+
+#define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_IPSEC_AH_LSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MASK                                                 0x0080000000000000
+
+#define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L4_OFFSET_LSB                                                 56
+#define RX_MSDU_START_L4_OFFSET_MSB                                                 63
+#define RX_MSDU_START_L4_OFFSET_MASK                                                0xff00000000000000
+
+#define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x0000000000000008
+#define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
+#define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
+#define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x00000000000000ff
+
+#define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
+#define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
+#define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x0000000000000300
+
+#define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV4_PROTO_LSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MASK                                               0x0000000000000400
+
+#define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV6_PROTO_LSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MASK                                               0x0000000000000800
+
+#define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_TCP_PROTO_LSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MASK                                                0x0000000000001000
+
+#define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_UDP_PROTO_LSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MASK                                                0x0000000000002000
+
+#define RX_MSDU_START_IP_FRAG_OFFSET                                                0x0000000000000008
+#define RX_MSDU_START_IP_FRAG_LSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MASK                                                  0x0000000000004000
+
+#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x0000000000008000
+
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x0000000000010000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x0000000000060000
+
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x0000000000000008
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x0000000000080000
+
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x0000000000100000
+
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x0000000000200000
+
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x0000000000400000
+
+#define RX_MSDU_START_LDPC_OFFSET                                                   0x0000000000000008
+#define RX_MSDU_START_LDPC_LSB                                                      23
+#define RX_MSDU_START_LDPC_MSB                                                      23
+#define RX_MSDU_START_LDPC_MASK                                                     0x0000000000800000
+
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x0000000000000008
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0x00000000ff000000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      32
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      63
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff00000000
+
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x0000000000000010
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_USER_RSSI_OFFSET                                              0x0000000000000010
+#define RX_MSDU_START_USER_RSSI_LSB                                                 32
+#define RX_MSDU_START_USER_RSSI_MSB                                                 39
+#define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x0000000000000010
+#define RX_MSDU_START_PKT_TYPE_LSB                                                  40
+#define RX_MSDU_START_PKT_TYPE_MSB                                                  43
+#define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f0000000000
+
+#define RX_MSDU_START_SGI_OFFSET                                                    0x0000000000000010
+#define RX_MSDU_START_SGI_LSB                                                       44
+#define RX_MSDU_START_SGI_MSB                                                       45
+#define RX_MSDU_START_SGI_MASK                                                      0x0000300000000000
+
+#define RX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define RX_MSDU_START_RESERVED_5A_LSB                                               46
+#define RX_MSDU_START_RESERVED_5A_MSB                                               49
+#define RX_MSDU_START_RESERVED_5A_MASK                                              0x0003c00000000000
+
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x0000000000000010
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         50
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         52
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c000000000000
+
+#define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_RECEPTION_TYPE_LSB                                            53
+#define RX_MSDU_START_RECEPTION_TYPE_MSB                                            55
+#define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e0000000000000
+
+#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            56
+#define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            63
+#define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff00000000000000
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000020
+#define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
+#define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
+#define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              32
+#define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              47
+#define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff00000000
+
+#define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_STAG_CI_LSB                                              48
+#define RX_MSDU_START_VLAN_STAG_CI_MSB                                              63
+#define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_ack_report.h b/hw/fig/v1/rx_ppdu_ack_report.h
new file mode 100644
index 000000000000..345b14ea4255
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_ack_report.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_ACK_REPORT_H_
+#define _RX_PPDU_ACK_REPORT_H_
+
+#include "ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2
+
+#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1
+
+struct rx_ppdu_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB           0
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB           3
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK          0x000000000000000f
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET                0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB                   4
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB                   7
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK                  0x00000000000000f0
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET                        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK                          0x0000000000000100
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET                       0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB                          9
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB                          15
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK                         0x000000000000fe00
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET                  0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB                     16
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB                     31
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK                    0x00000000ffff0000
+
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB                                        32
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB                                        63
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_end_user_stats.h b/hw/fig/v1/rx_ppdu_end_user_stats.h
new file mode 100644
index 000000000000..51db8f35a6ab
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_end_user_stats.h
@@ -0,0 +1,679 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15
+
+struct rx_ppdu_end_user_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t sta_full_aid                                            : 13,
+                      mcs                                                     :  5,
+                      nss                                                     :  3,
+                      expected_response_ack_or_ba                             :  1,
+                      reserved_1a                                             : 10;
+             uint32_t sw_peer_id                                              : 16,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      fw2rxdma1_buf_source_used                               :  1;
+             uint32_t mpdu_cnt_fcs_ok                                         : 11,
+                      frame_control_info_valid                                :  1,
+                      qos_control_info_valid                                  :  1,
+                      ht_control_info_valid                                   :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_null_valid                              :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      reserved_3a                                             :  1,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3b                                             :  7;
+             uint32_t ast_index                                               : 16,
+                      frame_control_field                                     : 16;
+             uint32_t first_data_seq_ctrl                                     : 16,
+                      qos_control_field                                       : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t udp_msdu_count                                          : 16,
+                      tcp_msdu_count                                          : 16;
+             uint32_t other_msdu_count                                        : 16,
+                      tcp_ack_msdu_count                                      : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_bitmap                            : 16,
+                      received_qos_data_tid_eosp_bitmap                       : 16;
+             uint32_t qosctrl_15_8_tid0                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid3                                       :  8;
+             uint32_t qosctrl_15_8_tid4                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid7                                       :  8;
+             uint32_t qosctrl_15_8_tid8                                       :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid11                                      :  8;
+             uint32_t qosctrl_15_8_tid12                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid15                                      :  8;
+             uint32_t mpdu_ok_byte_count                                      : 25,
+                      ampdu_delim_ok_count_6_0                                :  7;
+             uint32_t ampdu_delim_err_count                                   : 25,
+                      ampdu_delim_ok_count_13_7                               :  7;
+             uint32_t mpdu_err_byte_count                                     : 25,
+                      ampdu_delim_ok_count_20_14                              :  7;
+             uint32_t non_consecutive_delimiter_err                           : 16,
+                      retried_msdu_count                                      : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      frame_control_info_null_valid                           :  1,
+                      frame_control_field_null                                : 16,
+                      retried_mpdu_count                                      : 11,
+                      reserved_23a                                            :  3;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_24a                                            :  4,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mcast_bcast                                             :  1,
+                      frame_control_field_mgmt_ctrl                           : 16;
+             uint32_t user_ppdu_len                                           : 24,
+                      reserved_25a                                            :  8;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t mac_addr_ad2_47_32                                      : 16,
+                      amsdu_msdu_count                                        : 16;
+             uint32_t non_amsdu_msdu_count                                    : 16,
+                      ucast_msdu_count                                        : 16;
+             uint32_t bcast_msdu_count                                        : 16,
+                      mcast_bcast_msdu_count                                  : 16;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t reserved_1a                                             : 10,
+                      expected_response_ack_or_ba                             :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5,
+                      sta_full_aid                                            : 13;
+             uint32_t fw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_3b                                             :  7,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3a                                             :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      ht_control_info_null_valid                              :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_valid                                   :  1,
+                      qos_control_info_valid                                  :  1,
+                      frame_control_info_valid                                :  1,
+                      mpdu_cnt_fcs_ok                                         : 11;
+             uint32_t frame_control_field                                     : 16,
+                      ast_index                                               : 16;
+             uint32_t qos_control_field                                       : 16,
+                      first_data_seq_ctrl                                     : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t tcp_msdu_count                                          : 16,
+                      udp_msdu_count                                          : 16;
+             uint32_t tcp_ack_msdu_count                                      : 16,
+                      other_msdu_count                                        : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_eosp_bitmap                       : 16,
+                      received_qos_data_tid_bitmap                            : 16;
+             uint32_t qosctrl_15_8_tid3                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid0                                       :  8;
+             uint32_t qosctrl_15_8_tid7                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid4                                       :  8;
+             uint32_t qosctrl_15_8_tid11                                      :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid8                                       :  8;
+             uint32_t qosctrl_15_8_tid15                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid12                                      :  8;
+             uint32_t ampdu_delim_ok_count_6_0                                :  7,
+                      mpdu_ok_byte_count                                      : 25;
+             uint32_t ampdu_delim_ok_count_13_7                               :  7,
+                      ampdu_delim_err_count                                   : 25;
+             uint32_t ampdu_delim_ok_count_20_14                              :  7,
+                      mpdu_err_byte_count                                     : 25;
+             uint32_t retried_msdu_count                                      : 16,
+                      non_consecutive_delimiter_err                           : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t reserved_23a                                            :  3,
+                      retried_mpdu_count                                      : 11,
+                      frame_control_field_null                                : 16,
+                      frame_control_info_null_valid                           :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t frame_control_field_mgmt_ctrl                           : 16,
+                      mcast_bcast                                             :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      reserved_24a                                            :  4,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_25a                                            :  8,
+                      user_ppdu_len                                           : 24;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t amsdu_msdu_count                                        : 16,
+                      mac_addr_ad2_47_32                                      : 16;
+             uint32_t ucast_msdu_count                                        : 16,
+                      non_amsdu_msdu_count                                    : 16;
+             uint32_t mcast_bcast_msdu_count                                  : 16,
+                      bcast_msdu_count                                        : 16;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK  0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB          9
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB          15
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK         0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET      0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB         16
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB         31
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK        0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB                                     32
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB                                     44
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK                                    0x00001fff00000000
+
+#define RX_PPDU_END_USER_STATS_MCS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_MCS_LSB                                              45
+#define RX_PPDU_END_USER_STATS_MCS_MSB                                              49
+#define RX_PPDU_END_USER_STATS_MCS_MASK                                             0x0003e00000000000
+
+#define RX_PPDU_END_USER_STATS_NSS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_NSS_LSB                                              50
+#define RX_PPDU_END_USER_STATS_NSS_MSB                                              52
+#define RX_PPDU_END_USER_STATS_NSS_MASK                                             0x001c000000000000
+
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK                     0x0020000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB                                      54
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK                                     0xffc0000000000000
+
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET                                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB                                       0
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB                                       15
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK                                      0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET                              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB                                 16
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB                                 26
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK                                0x0000000007ff0000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000008000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000010000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000020000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK                       0x0000000040000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000080000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET                               0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB                                  32
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB                                  42
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK                                 0x000007ff00000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK                        0x0000080000000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET                        0x0000000000000008
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK                          0x0000100000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET                         0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK                           0x0000200000000000
+
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK                0x0000400000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK                      0x0000800000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK                             0x0001000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK                             0x0002000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK                         0x0004000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK                         0x0008000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK                                     0x0010000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB                        53
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB                        56
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK                       0x01e0000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB                                      57
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK                                     0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET                                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB                                        0
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB                                        15
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK                                       0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB                              16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB                              31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK                             0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB                              32
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB                              47
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK                             0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET                             0x0000000000000010
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK                               0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET                              0x0000000000000018
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB                                 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB                                 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET                            0x0000000000000018
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB                               32
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB                               63
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK                              0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET                           0x0000000000000020
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB                              0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB                              31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK                             0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB                                   32
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB                                   47
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK                                  0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB                                   48
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB                                   63
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK                                  0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET                              0x0000000000000028
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB                                 0
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB                                 15
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK                                0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET                            0x0000000000000028
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET                     0x0000000000000028
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB                        32
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB                        63
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET                  0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB                     0
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB                     15
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK                    0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB                16
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB                31
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK               0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB                                55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK                               0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB                                56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK                               0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK                               0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK                               0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB                                23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK                               0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB                                24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK                               0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB                               48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB                               55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK                              0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB                               56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB                               63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK                              0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB                               0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB                               7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK                              0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB                               8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB                               15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK                              0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB                               16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB                               23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK                              0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB                               24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB                               31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK                              0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB                               32
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB                               56
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK                              0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET                      0x0000000000000040
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB                         57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB                         63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK                        0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET                         0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB                            0
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB                            24
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK                           0x0000000001ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET                     0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB                        25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB                        31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK                       0x00000000fe000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET                           0x0000000000000048
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB                              32
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB                              56
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK                             0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET                    0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB                       57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB                       63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK                      0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET                 0x0000000000000050
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB                    0
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB                    15
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK                   0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET                            0x0000000000000050
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET                         0x0000000000000050
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB                            32
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB                            63
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK                           0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB                    0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB                    31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK                   0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                   0x0000000000000058
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                     0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK                   0x0000000200000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET                      0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB                         34
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB                         49
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK                        0x0003fffc00000000
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET                            0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB                               50
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB                               60
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK                              0x1ffc000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET                                  0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB                                     61
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK                                    0xe000000000000000
+
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                    0
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                    1
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                   0x0000000000000003
+
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET                             0x0000000000000060
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB                                2
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB                                8
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK                               0x00000000000001fc
+
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB                                     9
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB                                     12
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK                                    0x0000000000001e00
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK              0x0000000000002000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET                            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK                              0x0000000000004000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET                                   0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK                                     0x0000000000008000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB                    16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB                    31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK                   0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET                                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB                                    32
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB                                    55
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK                                   0x00ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB                                     56
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK                                    0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET                             0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB                                0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB                                31
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK                               0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET                            0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB                               32
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB                               47
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK                              0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET                              0x0000000000000068
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB                                 48
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB                                 63
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK                                0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET                          0x0000000000000070
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB                             0
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB                             15
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK                            0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB                                 16
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB                                 31
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK                                0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB                                 32
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB                                 47
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK                                0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET                        0x0000000000000070
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB                           48
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB                           63
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK                          0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_end_user_stats_ext.h b/hw/fig/v1/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 000000000000..0a11202db481
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4
+
+struct rx_ppdu_end_user_stats_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      reserved_7a                                             : 31;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t reserved_7a                                             : 31,
+                      corrupted_due_to_fifo_delay                             :  1;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB      9
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB      15
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK     0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB     16
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB     31
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK    0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET                       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB                          32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB                          63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK                         0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB                         0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB                         31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK                        0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET                     0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                 0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET                               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB                                  33
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB                                  63
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK                                 0xfffffffe00000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_no_ack_report.h b/hw/fig/v1/rx_ppdu_no_ack_report.h
new file mode 100644
index 000000000000..d9c54c04df32
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_no_ack_report.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_NO_ACK_REPORT_H_
+#define _RX_PPDU_NO_ACK_REPORT_H_
+
+#include "no_ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
+
+#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2
+
+struct rx_ppdu_no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   no_ack_report                                             no_ack_report_details;
+#else
+             struct   no_ack_report                                             no_ack_report_details;
+#endif
+};
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET   0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB      0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB      3
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK     0x000000000000000f
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB          4
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB          7
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK         0x00000000000000f0
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB          8
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB          15
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK         0x000000000000ff00
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET            0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB               16
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB               31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK              0x00000000ffff0000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET         0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB            32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB            55
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK           0x00ffffff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET      0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK        0x0100000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET               0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB                  61
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK                 0xe000000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB                  24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK                 0x00000000ff000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB                  44
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK                 0xfffff00000000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_start.h b/hw/fig/v1/rx_ppdu_start.h
new file mode 100644
index 000000000000..19765eb4409b
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_start.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+
+#define NUM_OF_DWORDS_RX_PPDU_START 6
+
+#define NUM_OF_QWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      preamble_time_to_rxframe                                :  8,
+                      reserved_0a                                             :  8;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      preamble_time_to_rxframe                                :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_PHY_PPDU_ID_LSB                                               0
+#define RX_PPDU_START_PHY_PPDU_ID_MSB                                               15
+#define RX_PPDU_START_PHY_PPDU_ID_MASK                                              0x000000000000ffff
+
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET                               0x0000000000000000
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB                                  16
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB                                  23
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK                                 0x0000000000ff0000
+
+#define RX_PPDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_RESERVED_0A_LSB                                               24
+#define RX_PPDU_START_RESERVED_0A_MSB                                               31
+#define RX_PPDU_START_RESERVED_0A_MASK                                              0x00000000ff000000
+
+#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000000
+#define RX_PPDU_START_SW_PHY_META_DATA_LSB                                          32
+#define RX_PPDU_START_SW_PHY_META_DATA_MSB                                          63
+#define RX_PPDU_START_SW_PHY_META_DATA_MASK                                         0xffffffff00000000
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET                               0x0000000000000010
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB                                  0
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB                                  31
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK                                 0x00000000ffffffff
+
+#define RX_PPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000010
+#define RX_PPDU_START_TLV64_PADDING_LSB                                             32
+#define RX_PPDU_START_TLV64_PADDING_MSB                                             63
+#define RX_PPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_ppdu_start_user_info.h b/hw/fig/v1/rx_ppdu_start_user_info.h
new file mode 100644
index 000000000000..e0caf9b2ac24
--- /dev/null
+++ b/hw/fig/v1/rx_ppdu_start_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8
+
+#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4
+
+struct rx_ppdu_start_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB           0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB           15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK          0x000000000000ffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET          0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB             16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB             23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK            0x0000000000ff0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB              24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB              27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK             0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET               0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                 0x0000000010000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB        29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB        31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK       0x00000000e0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB              32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB              36
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK             0x0000001f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                   38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                  0x0000006000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB        40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB        47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK       0x0000ff0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET  0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB     48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB     50
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK    0x0007000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB           51
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK          0x00f8000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB   63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK  0xff00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK          0x0000000000000002
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB             2
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB             3
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK            0x000000000000000c
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB             4
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB             5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK            0x0000000000000030
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB             6
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB             7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK            0x00000000000000c0
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                   8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                   10
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                  0x0000000000000700
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET      0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB         11
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB         13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK        0x0000000000003800
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET            0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK              0x0000000000004000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET               0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                 0x0000000000008000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB          16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB          19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK         0x00000000000f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB          20
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB          23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK         0x0000000000f00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB          24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB          27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK         0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB          28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB          31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK         0x00000000f0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB   32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK  0x0000003f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB           38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB           39
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK          0x000000c000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB   40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB   45
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK  0x00003f0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB           46
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB           47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK          0x0000c00000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB   48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB   53
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK  0x003f000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB           54
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK          0x00c0000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB   61
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK  0x3f00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB           62
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB           63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK          0xc000000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK    0xffffffff00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK    0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_preamble.h b/hw/fig/v1/rx_preamble.h
new file mode 100644
index 000000000000..807463753865
--- /dev/null
+++ b/hw/fig/v1/rx_preamble.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PREAMBLE_H_
+#define _RX_PREAMBLE_H_
+
+#define NUM_OF_DWORDS_RX_PREAMBLE 2
+
+#define NUM_OF_QWORDS_RX_PREAMBLE 1
+
+struct rx_preamble {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      pkt_type                                                :  4,
+                      direction                                               :  1,
+                      reserved_0a                                             : 21;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 21,
+                      direction                                               :  1,
+                      pkt_type                                                :  4,
+                      num_users                                               :  6;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PREAMBLE_NUM_USERS_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_NUM_USERS_LSB                                                   0
+#define RX_PREAMBLE_NUM_USERS_MSB                                                   5
+#define RX_PREAMBLE_NUM_USERS_MASK                                                  0x000000000000003f
+
+#define RX_PREAMBLE_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define RX_PREAMBLE_PKT_TYPE_LSB                                                    6
+#define RX_PREAMBLE_PKT_TYPE_MSB                                                    9
+#define RX_PREAMBLE_PKT_TYPE_MASK                                                   0x00000000000003c0
+
+#define RX_PREAMBLE_DIRECTION_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_DIRECTION_LSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MASK                                                  0x0000000000000400
+
+#define RX_PREAMBLE_RESERVED_0A_OFFSET                                              0x0000000000000000
+#define RX_PREAMBLE_RESERVED_0A_LSB                                                 11
+#define RX_PREAMBLE_RESERVED_0A_MSB                                                 31
+#define RX_PREAMBLE_RESERVED_0A_MASK                                                0x00000000fffff800
+
+#define RX_PREAMBLE_TLV64_PADDING_OFFSET                                            0x0000000000000000
+#define RX_PREAMBLE_TLV64_PADDING_LSB                                               32
+#define RX_PREAMBLE_TLV64_PADDING_MSB                                               63
+#define RX_PREAMBLE_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_reo_queue.h b/hw/fig/v1/rx_reo_queue.h
new file mode 100644
index 000000000000..faaae001f79e
--- /dev/null
+++ b/hw/fig/v1/rx_reo_queue.h
@@ -0,0 +1,502 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t receive_queue_number                                    : 16,
+                      reserved_1b                                             : 16;
+             uint32_t vld                                                     :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      disable_duplicate_detection                             :  1,
+                      soft_reorder_enable                                     :  1,
+                      ac                                                      :  2,
+                      bar                                                     :  1,
+                      rty                                                     :  1,
+                      chk_2k_mode                                             :  1,
+                      oor_mode                                                :  1,
+                      ba_window_size                                          : 10,
+                      pn_check_needed                                         :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_handling_enable                                      :  1,
+                      pn_size                                                 :  2,
+                      ignore_ampdu_flag                                       :  1,
+                      reserved_2b                                             :  4;
+             uint32_t svld                                                    :  1,
+                      ssn                                                     : 12,
+                      current_index                                           : 10,
+                      seq_2k_error_detected_flag                              :  1,
+                      pn_error_detected_flag                                  :  1,
+                      reserved_3a                                             :  6,
+                      pn_valid                                                :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
+             uint32_t ptr_to_next_aging_queue_39_32                           :  8,
+                      reserved_11a                                            : 24;
+             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
+             uint32_t ptr_to_previous_aging_queue_39_32                       :  8,
+                      statistics_counter_index                                :  6,
+                      reserved_13a                                            : 18;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_mpdu_count                                      :  7,
+                      current_msdu_count                                      : 25;
+             uint32_t last_sn_reg_index                                       :  4,
+                      timeout_count                                           :  6,
+                      forward_due_to_bar_count                                :  6,
+                      duplicate_count                                         : 16;
+             uint32_t frames_in_order_count                                   : 24,
+                      bar_received_count                                      :  8;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t late_receive_mpdu_count                                 : 12,
+                      window_jump_2k                                          :  4,
+                      hole_count                                              : 16;
+             uint32_t aging_drop_mpdu_count                                   : 16,
+                      aging_drop_interval                                     :  8,
+                      reserved_30                                             :  8;
+             uint32_t reserved_31                                             : 32;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1b                                             : 16,
+                      receive_queue_number                                    : 16;
+             uint32_t reserved_2b                                             :  4,
+                      ignore_ampdu_flag                                       :  1,
+                      pn_size                                                 :  2,
+                      pn_handling_enable                                      :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_check_needed                                         :  1,
+                      ba_window_size                                          : 10,
+                      oor_mode                                                :  1,
+                      chk_2k_mode                                             :  1,
+                      rty                                                     :  1,
+                      bar                                                     :  1,
+                      ac                                                      :  2,
+                      soft_reorder_enable                                     :  1,
+                      disable_duplicate_detection                             :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      vld                                                     :  1;
+             uint32_t pn_valid                                                :  1,
+                      reserved_3a                                             :  6,
+                      pn_error_detected_flag                                  :  1,
+                      seq_2k_error_detected_flag                              :  1,
+                      current_index                                           : 10,
+                      ssn                                                     : 12,
+                      svld                                                    :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
+             uint32_t reserved_11a                                            : 24,
+                      ptr_to_next_aging_queue_39_32                           :  8;
+             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
+             uint32_t reserved_13a                                            : 18,
+                      statistics_counter_index                                :  6,
+                      ptr_to_previous_aging_queue_39_32                       :  8;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_msdu_count                                      : 25,
+                      current_mpdu_count                                      :  7;
+             uint32_t duplicate_count                                         : 16,
+                      forward_due_to_bar_count                                :  6,
+                      timeout_count                                           :  6,
+                      last_sn_reg_index                                       :  4;
+             uint32_t bar_received_count                                      :  8,
+                      frames_in_order_count                                   : 24;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t hole_count                                              : 16,
+                      window_jump_2k                                          :  4,
+                      late_receive_mpdu_count                                 : 12;
+             uint32_t reserved_30                                             :  8,
+                      aging_drop_interval                                     :  8,
+                      aging_drop_mpdu_count                                   : 16;
+             uint32_t reserved_31                                             : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x00000004
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                                       0
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                                       15
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                                      0x0000ffff
+
+#define RX_REO_QUEUE_RESERVED_1B_OFFSET                                             0x00000004
+#define RX_REO_QUEUE_RESERVED_1B_LSB                                                16
+#define RX_REO_QUEUE_RESERVED_1B_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_1B_MASK                                               0xffff0000
+
+#define RX_REO_QUEUE_VLD_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_VLD_LSB                                                        0
+#define RX_REO_QUEUE_VLD_MSB                                                        0
+#define RX_REO_QUEUE_VLD_MASK                                                       0x00000001
+
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET                      0x00000008
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB                         1
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB                         2
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK                        0x00000006
+
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                             0x00000008
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                                3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                                3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                               0x00000008
+
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                                     0x00000008
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                                        4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                                        4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                                       0x00000010
+
+#define RX_REO_QUEUE_AC_OFFSET                                                      0x00000008
+#define RX_REO_QUEUE_AC_LSB                                                         5
+#define RX_REO_QUEUE_AC_MSB                                                         6
+#define RX_REO_QUEUE_AC_MASK                                                        0x00000060
+
+#define RX_REO_QUEUE_BAR_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_BAR_LSB                                                        7
+#define RX_REO_QUEUE_BAR_MSB                                                        7
+#define RX_REO_QUEUE_BAR_MASK                                                       0x00000080
+
+#define RX_REO_QUEUE_RTY_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_RTY_LSB                                                        8
+#define RX_REO_QUEUE_RTY_MSB                                                        8
+#define RX_REO_QUEUE_RTY_MASK                                                       0x00000100
+
+#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                             0x00000008
+#define RX_REO_QUEUE_CHK_2K_MODE_LSB                                                9
+#define RX_REO_QUEUE_CHK_2K_MODE_MSB                                                9
+#define RX_REO_QUEUE_CHK_2K_MODE_MASK                                               0x00000200
+
+#define RX_REO_QUEUE_OOR_MODE_OFFSET                                                0x00000008
+#define RX_REO_QUEUE_OOR_MODE_LSB                                                   10
+#define RX_REO_QUEUE_OOR_MODE_MSB                                                   10
+#define RX_REO_QUEUE_OOR_MODE_MASK                                                  0x00000400
+
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                                          0x00000008
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                             11
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                             20
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                            0x001ff800
+
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                                         0x00000008
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                            21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                            21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                           0x00200000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                                        0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                           22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                           22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                                          0x00400000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                                      0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                                         23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                                         23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                                        0x00800000
+
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                                      0x00000008
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                                         24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                                         24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                                        0x01000000
+
+#define RX_REO_QUEUE_PN_SIZE_OFFSET                                                 0x00000008
+#define RX_REO_QUEUE_PN_SIZE_LSB                                                    25
+#define RX_REO_QUEUE_PN_SIZE_MSB                                                    26
+#define RX_REO_QUEUE_PN_SIZE_MASK                                                   0x06000000
+
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                                       0x00000008
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                                          27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                                          27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                                         0x08000000
+
+#define RX_REO_QUEUE_RESERVED_2B_OFFSET                                             0x00000008
+#define RX_REO_QUEUE_RESERVED_2B_LSB                                                28
+#define RX_REO_QUEUE_RESERVED_2B_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_2B_MASK                                               0xf0000000
+
+#define RX_REO_QUEUE_SVLD_OFFSET                                                    0x0000000c
+#define RX_REO_QUEUE_SVLD_LSB                                                       0
+#define RX_REO_QUEUE_SVLD_MSB                                                       0
+#define RX_REO_QUEUE_SVLD_MASK                                                      0x00000001
+
+#define RX_REO_QUEUE_SSN_OFFSET                                                     0x0000000c
+#define RX_REO_QUEUE_SSN_LSB                                                        1
+#define RX_REO_QUEUE_SSN_MSB                                                        12
+#define RX_REO_QUEUE_SSN_MASK                                                       0x00001ffe
+
+#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET                                           0x0000000c
+#define RX_REO_QUEUE_CURRENT_INDEX_LSB                                              13
+#define RX_REO_QUEUE_CURRENT_INDEX_MSB                                              22
+#define RX_REO_QUEUE_CURRENT_INDEX_MASK                                             0x007fe000
+
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                              0x0000000c
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                                 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                                 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                                0x00800000
+
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                                  0x0000000c
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                                     24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                                     24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                                    0x01000000
+
+#define RX_REO_QUEUE_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_REO_QUEUE_RESERVED_3A_LSB                                                25
+#define RX_REO_QUEUE_RESERVED_3A_MSB                                                30
+#define RX_REO_QUEUE_RESERVED_3A_MASK                                               0x7e000000
+
+#define RX_REO_QUEUE_PN_VALID_OFFSET                                                0x0000000c
+#define RX_REO_QUEUE_PN_VALID_LSB                                                   31
+#define RX_REO_QUEUE_PN_VALID_MSB                                                   31
+#define RX_REO_QUEUE_PN_VALID_MASK                                                  0x80000000
+
+#define RX_REO_QUEUE_PN_31_0_OFFSET                                                 0x00000010
+#define RX_REO_QUEUE_PN_31_0_LSB                                                    0
+#define RX_REO_QUEUE_PN_31_0_MSB                                                    31
+#define RX_REO_QUEUE_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_REO_QUEUE_PN_63_32_OFFSET                                                0x00000014
+#define RX_REO_QUEUE_PN_63_32_LSB                                                   0
+#define RX_REO_QUEUE_PN_63_32_MSB                                                   31
+#define RX_REO_QUEUE_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_REO_QUEUE_PN_95_64_OFFSET                                                0x00000018
+#define RX_REO_QUEUE_PN_95_64_LSB                                                   0
+#define RX_REO_QUEUE_PN_95_64_MSB                                                   31
+#define RX_REO_QUEUE_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_REO_QUEUE_PN_127_96_OFFSET                                               0x0000001c
+#define RX_REO_QUEUE_PN_127_96_LSB                                                  0
+#define RX_REO_QUEUE_PN_127_96_MSB                                                  31
+#define RX_REO_QUEUE_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                               0x00000020
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB                                  0
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB                                  31
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                               0x00000024
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB                                  0
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB                                  31
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET                            0x00000028
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB                               0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB                               31
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK                              0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET                           0x0000002c
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB                              0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB                              7
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK                             0x000000ff
+
+#define RX_REO_QUEUE_RESERVED_11A_OFFSET                                            0x0000002c
+#define RX_REO_QUEUE_RESERVED_11A_LSB                                               8
+#define RX_REO_QUEUE_RESERVED_11A_MSB                                               31
+#define RX_REO_QUEUE_RESERVED_11A_MASK                                              0xffffff00
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET                        0x00000030
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB                           0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB                           31
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK                          0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET                       0x00000034
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB                          0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB                          7
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK                         0x000000ff
+
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET                                0x00000034
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB                                   8
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB                                   13
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK                                  0x00003f00
+
+#define RX_REO_QUEUE_RESERVED_13A_OFFSET                                            0x00000034
+#define RX_REO_QUEUE_RESERVED_13A_LSB                                               14
+#define RX_REO_QUEUE_RESERVED_13A_MSB                                               31
+#define RX_REO_QUEUE_RESERVED_13A_MASK                                              0xffffc000
+
+#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET                                          0x00000038
+#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB                                             0
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB                                             31
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET                                         0x0000003c
+#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB                                            0
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB                                            31
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET                                         0x00000040
+#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB                                            0
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB                                            31
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET                                        0x00000044
+#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB                                           0
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB                                           31
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK                                          0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET                                       0x00000048
+#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET                                       0x0000004c
+#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET                                       0x00000050
+#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET                                       0x00000054
+#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET                                       0x00000058
+#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET                                      0x0000005c
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB                                         0
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB                                         6
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK                                        0x0000007f
+
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET                                      0x0000005c
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB                                         7
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB                                         31
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK                                        0xffffff80
+
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET                                       0x00000060
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB                                          0
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB                                          3
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK                                         0x0000000f
+
+#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET                                           0x00000060
+#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB                                              4
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB                                              9
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK                                             0x000003f0
+
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET                                0x00000060
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB                                   10
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB                                   15
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK                                  0x0000fc00
+
+#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET                                         0x00000060
+#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB                                            16
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB                                            31
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK                                           0xffff0000
+
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET                                   0x00000064
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB                                      0
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB                                      23
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK                                     0x00ffffff
+
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET                                      0x00000064
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB                                         24
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB                                         31
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK                                        0xff000000
+
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x00000068
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB                                0
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB                                31
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
+
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x0000006c
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB                                0
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB                                31
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
+
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                              0x00000070
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB                                 0
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB                                 31
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK                                0xffffffff
+
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET                                 0x00000074
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB                                    0
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB                                    11
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK                                   0x00000fff
+
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET                                          0x00000074
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB                                             12
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB                                             15
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK                                            0x0000f000
+
+#define RX_REO_QUEUE_HOLE_COUNT_OFFSET                                              0x00000074
+#define RX_REO_QUEUE_HOLE_COUNT_LSB                                                 16
+#define RX_REO_QUEUE_HOLE_COUNT_MSB                                                 31
+#define RX_REO_QUEUE_HOLE_COUNT_MASK                                                0xffff0000
+
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET                                   0x00000078
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB                                      0
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB                                      15
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK                                     0x0000ffff
+
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET                                     0x00000078
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB                                        16
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB                                        23
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK                                       0x00ff0000
+
+#define RX_REO_QUEUE_RESERVED_30_OFFSET                                             0x00000078
+#define RX_REO_QUEUE_RESERVED_30_LSB                                                24
+#define RX_REO_QUEUE_RESERVED_30_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_30_MASK                                               0xff000000
+
+#define RX_REO_QUEUE_RESERVED_31_OFFSET                                             0x0000007c
+#define RX_REO_QUEUE_RESERVED_31_LSB                                                0
+#define RX_REO_QUEUE_RESERVED_31_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_31_MASK                                               0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rx_reo_queue_1k.h b/hw/fig/v1/rx_reo_queue_1k.h
new file mode 100644
index 000000000000..40c4dd19bcc0
--- /dev/null
+++ b/hw/fig/v1/rx_reo_queue_1k.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_REO_QUEUE_1K_H_
+#define _RX_REO_QUEUE_1K_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
+
+struct rx_reo_queue_1k {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t rx_bitmap_319_288                                       : 32;
+             uint32_t rx_bitmap_351_320                                       : 32;
+             uint32_t rx_bitmap_383_352                                       : 32;
+             uint32_t rx_bitmap_415_384                                       : 32;
+             uint32_t rx_bitmap_447_416                                       : 32;
+             uint32_t rx_bitmap_479_448                                       : 32;
+             uint32_t rx_bitmap_511_480                                       : 32;
+             uint32_t rx_bitmap_543_512                                       : 32;
+             uint32_t rx_bitmap_575_544                                       : 32;
+             uint32_t rx_bitmap_607_576                                       : 32;
+             uint32_t rx_bitmap_639_608                                       : 32;
+             uint32_t rx_bitmap_671_640                                       : 32;
+             uint32_t rx_bitmap_703_672                                       : 32;
+             uint32_t rx_bitmap_735_704                                       : 32;
+             uint32_t rx_bitmap_767_736                                       : 32;
+             uint32_t rx_bitmap_799_768                                       : 32;
+             uint32_t rx_bitmap_831_800                                       : 32;
+             uint32_t rx_bitmap_863_832                                       : 32;
+             uint32_t rx_bitmap_895_864                                       : 32;
+             uint32_t rx_bitmap_927_896                                       : 32;
+             uint32_t rx_bitmap_959_928                                       : 32;
+             uint32_t rx_bitmap_991_960                                       : 32;
+             uint32_t rx_bitmap_1023_992                                      : 32;
+             uint32_t reserved_24                                             : 32;
+             uint32_t reserved_25                                             : 32;
+             uint32_t reserved_26                                             : 32;
+             uint32_t reserved_27                                             : 32;
+             uint32_t reserved_28                                             : 32;
+             uint32_t reserved_29                                             : 32;
+             uint32_t reserved_30                                             : 32;
+             uint32_t reserved_31                                             : 32;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t rx_bitmap_319_288                                       : 32;
+             uint32_t rx_bitmap_351_320                                       : 32;
+             uint32_t rx_bitmap_383_352                                       : 32;
+             uint32_t rx_bitmap_415_384                                       : 32;
+             uint32_t rx_bitmap_447_416                                       : 32;
+             uint32_t rx_bitmap_479_448                                       : 32;
+             uint32_t rx_bitmap_511_480                                       : 32;
+             uint32_t rx_bitmap_543_512                                       : 32;
+             uint32_t rx_bitmap_575_544                                       : 32;
+             uint32_t rx_bitmap_607_576                                       : 32;
+             uint32_t rx_bitmap_639_608                                       : 32;
+             uint32_t rx_bitmap_671_640                                       : 32;
+             uint32_t rx_bitmap_703_672                                       : 32;
+             uint32_t rx_bitmap_735_704                                       : 32;
+             uint32_t rx_bitmap_767_736                                       : 32;
+             uint32_t rx_bitmap_799_768                                       : 32;
+             uint32_t rx_bitmap_831_800                                       : 32;
+             uint32_t rx_bitmap_863_832                                       : 32;
+             uint32_t rx_bitmap_895_864                                       : 32;
+             uint32_t rx_bitmap_927_896                                       : 32;
+             uint32_t rx_bitmap_959_928                                       : 32;
+             uint32_t rx_bitmap_991_960                                       : 32;
+             uint32_t rx_bitmap_1023_992                                      : 32;
+             uint32_t reserved_24                                             : 32;
+             uint32_t reserved_25                                             : 32;
+             uint32_t reserved_26                                             : 32;
+             uint32_t reserved_27                                             : 32;
+             uint32_t reserved_28                                             : 32;
+             uint32_t reserved_29                                             : 32;
+             uint32_t reserved_30                                             : 32;
+             uint32_t reserved_31                                             : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET                              0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB                                 0
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB                                 3
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK                                0x0000000f
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                        0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                           4
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                           7
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                          0x000000f0
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET               0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                  8
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                  27
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                 0x0fffff00
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                        0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB                           28
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB                           31
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK                          0xf0000000
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET                                    0x00000004
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET                                    0x0000000c
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET                                    0x00000010
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET                                    0x00000014
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET                                    0x00000018
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET                                    0x0000001c
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET                                    0x00000020
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET                                    0x00000024
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET                                    0x00000028
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET                                    0x0000002c
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET                                    0x00000030
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET                                    0x00000034
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET                                    0x00000038
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET                                    0x0000003c
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET                                    0x00000040
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET                                    0x00000044
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET                                    0x00000048
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET                                    0x0000004c
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET                                    0x00000050
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET                                    0x00000054
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET                                    0x00000058
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET                                   0x0000005c
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB                                      0
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB                                      31
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK                                     0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET                                          0x00000060
+#define RX_REO_QUEUE_1K_RESERVED_24_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_24_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_24_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET                                          0x00000064
+#define RX_REO_QUEUE_1K_RESERVED_25_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_25_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_25_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET                                          0x00000068
+#define RX_REO_QUEUE_1K_RESERVED_26_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_26_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_26_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET                                          0x0000006c
+#define RX_REO_QUEUE_1K_RESERVED_27_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_27_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_27_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET                                          0x00000070
+#define RX_REO_QUEUE_1K_RESERVED_28_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_28_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_28_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET                                          0x00000074
+#define RX_REO_QUEUE_1K_RESERVED_29_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_29_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_29_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET                                          0x00000078
+#define RX_REO_QUEUE_1K_RESERVED_30_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_30_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_30_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET                                          0x0000007c
+#define RX_REO_QUEUE_1K_RESERVED_31_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_31_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_31_MASK                                            0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rx_reo_queue_ext.h b/hw/fig/v1/rx_reo_queue_ext.h
new file mode 100644
index 000000000000..66554c7633f3
--- /dev/null
+++ b/hw/fig/v1/rx_reo_queue_ext.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+
+#include "rx_mpdu_link_ptr.h"
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1a                                             : 32;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1a                                             : 32;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
+#endif
+};
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET                             0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB                                0
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB                                3
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK                               0x0000000f
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                       0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                          4
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                          7
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                         0x000000f0
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET              0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                 8
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                 27
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                0x0fffff00
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                       0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB                          28
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB                          31
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK                         0xf0000000
+
+#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET                                         0x00000004
+#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB                                            0
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB                                            31
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/hw/fig/v1/rx_response_required_info.h b/hw/fig/v1/rx_response_required_info.h
new file mode 100644
index 000000000000..9d5364537a1c
--- /dev/null
+++ b/hw/fig/v1/rx_response_required_info.h
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
+#define _RX_RESPONSE_REQUIRED_INFO_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16
+
+#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8
+
+struct rx_response_required_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      su_or_uplink_mu_reception                               :  1,
+                      trigger_frame_received                                  :  1,
+                      __reserved_g_0012                                                  :  2,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      mac_security                                            :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2;
+             uint32_t general_frame_control                                   : 16,
+                      second_frame_control                                    : 16;
+             uint32_t duration                                                : 16,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      ampdu                                                   :  1,
+                      rts_ta_grp_bit                                          :  1;
+             uint32_t ctrl_frame_soliciting_resp                              :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      service_dynamic                                         :  1,
+                      m_pkt                                                   :  1,
+                      sta_partial_aid                                         : 12,
+                      group_id                                                :  6,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      response_indication                                     :  2,
+                      ndp_indication                                          :  1,
+                      ndp_frame_type                                          :  3,
+                      second_frame_control_valid                              :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      vht_ack                                                 :  1;
+             uint32_t sta_aid                                                 : 11,
+                      interference                                            :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_4a                                             :  3,
+                      ack_id_ext                                              : 10,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             uint32_t response_sta_count                                      :  7,
+                      __reserved_g_0035                                                 :  1,
+                      blackout_details_en                                     :  1,
+                      reserved                                                :  2,
+                      ht_vht_sig_cbw                                          :  3,
+                      cts_cbw                                                 :  3,
+                      response_ack_count                                      :  7,
+                      response_assoc_ack_count                                :  7,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t response_ba32_count                                     :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba256_count                                    :  7,
+                      multi_tid                                               :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      emlsr_main_tlv_if                                       :  1;
+             uint32_t sw_response_frame_length                                : 16,
+                      response_ba512_count                                    :  7,
+                      response_ba1024_count                                   :  7,
+                      reserved_7a                                             :  2;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      ftm_fields_valid                                        :  1,
+                      ftm_pe_nss                                              :  3,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_content                                          :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_chain_csd_en                                     :  1;
+             uint32_t dot11ax_response_rate_source                            :  8,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      sw_peer_id                                              : 16;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      force_extra_symbol                                      :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      reserved_13a                                            :  3,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t he_a_control_response_time                              : 12,
+                      reserved_after_struct16                                 :  4;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      reserved_15a                                            :  7;
+#else
+             uint32_t wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      mac_security                                            :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      __reserved_g_0012                                                  :  2,
+                      trigger_frame_received                                  :  1,
+                      su_or_uplink_mu_reception                               :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t second_frame_control                                    : 16,
+                      general_frame_control                                   : 16;
+             uint32_t rts_ta_grp_bit                                          :  1,
+                      ampdu                                                   :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      duration                                                : 16;
+             uint32_t vht_ack                                                 :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      second_frame_control_valid                              :  1,
+                      ndp_frame_type                                          :  3,
+                      ndp_indication                                          :  1,
+                      response_indication                                     :  2,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 12,
+                      m_pkt                                                   :  1,
+                      service_dynamic                                         :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      ctrl_frame_soliciting_resp                              :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      ack_id_ext                                              : 10,
+                      reserved_4a                                             :  3,
+                      ects_as_tb_ppdu                                         :  1,
+                      interference                                            :  1,
+                      sta_aid                                                 : 11;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      response_assoc_ack_count                                :  7,
+                      response_ack_count                                      :  7,
+                      cts_cbw                                                 :  3,
+                      ht_vht_sig_cbw                                          :  3,
+                      reserved                                                :  2,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0035                                                 :  1,
+                      response_sta_count                                      :  7;
+             uint32_t emlsr_main_tlv_if                                       :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      multi_tid                                               :  1,
+                      response_ba256_count                                    :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba32_count                                     :  7;
+             uint32_t reserved_7a                                             :  2,
+                      response_ba1024_count                                   :  7,
+                      response_ba512_count                                    :  7,
+                      sw_response_frame_length                                : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ftm_pe_chain_csd_en                                     :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_content                                          :  1,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_nss                                              :  3,
+                      ftm_fields_valid                                        :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t sw_peer_id                                              : 16,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      dot11ax_response_rate_source                            :  8;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_13a                                            :  3,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_after_struct16                                 :  4,
+                      he_a_control_response_time                              : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t reserved_15a                                            :  7,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+#endif
+};
+
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET                                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK                                  0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK                    0x0000000000010000
+
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK                       0x0000000000020000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET                               0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK                                 0x0000000000400000
+
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK                     0x0000000000800000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK                        0x0000000001000000
+
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK                     0x0000000002000000
+
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK                  0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK                       0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET                                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB                                     30
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB                                     31
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK                                    0x00000000c0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB                         32
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB                         47
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK                        0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET                       0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB                          63
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK                         0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB                                      0
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB                                      15
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK                                     0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB                                      16
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB                                      19
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK                                     0x00000000000f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK                          0x0000000000100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB                                      21
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB                                      25
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK                                     0x0000000003e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET                                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB                                           26
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB                                           27
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK                                          0x000000000c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK                                         0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK                                         0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK                                        0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK                               0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK                   0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET                0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK                              0x0000000400000000
+
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK                                        0x0000000800000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB                               36
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB                               47
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK                              0x0000fff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB                                      48
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB                                      53
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK                                     0x003f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET                         0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK                           0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB                           55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB                           56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK                          0x0180000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK                               0x0200000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB                                58
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB                                60
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK                               0x1c00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK                   0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK                        0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK                                      0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB                                       0
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB                                       10
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK                                      0x00000000000007ff
+
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET                               0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK                                 0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET                            0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK                              0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB                                   13
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK                                  0x000000000000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET                                 0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB                                    25
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK                                   0x0000000003ff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB                                       26
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB                                       28
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK                                      0x000000001c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB                                   29
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK                                  0x00000000e0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB                            32
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB                            38
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK                           0x0000007f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET                        0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK                          0x0000010000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET                                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB                                      41
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB                                      42
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK                                     0x0000060000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET                             0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB                                43
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB                                45
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK                               0x0000380000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB                                       46
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB                                       48
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK                                      0x0001c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB                            55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK                           0x00fe000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB                      56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB                      62
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK                     0x7f00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET                     0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK                       0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB                           0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB                           6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK                          0x000000000000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB                           7
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB                           13
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK                          0x0000000000003f80
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB                          14
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB                          20
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK                         0x00000000001fc000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB                          21
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB                          27
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK                         0x000000000fe00000
+
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET                                  0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK                                    0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                  0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET                         0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK                           0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET                          0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK                            0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                   0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                      32
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                      47
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                     0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB                          54
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK                         0x007f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET                      0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB                         55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB                         61
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK                        0x3f80000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET                                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB                                   62
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB                                   63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK                                  0xc000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB                                    0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK                                   0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET                                0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB                                   32
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB                                   47
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK                                  0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB                                    48
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB                                    63
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK                                   0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET                                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK                                  0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET         0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK           0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET              0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                 34
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                 39
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                0x000000fc00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                40
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                43
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK               0x00000f0000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                   0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                      44
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                      45
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                     0x0000300000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                  0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                     46
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                     47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                    0x0000c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET                    0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK                      0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET                       0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK                         0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK          0x0004000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  51
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  54
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0078000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK                             0x0080000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET                                 0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB                                    56
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB                                    58
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK                                   0x0700000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET                            0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB                               59
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB                               60
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK                              0x1800000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET                             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK                               0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK                             0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET                        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK                          0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB                  0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB                  7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK                 0x00000000000000ff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB              8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB              15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK             0x000000000000ff00
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET                                 0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK                                   0x00000000ffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                    0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                       32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                       47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                      0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK                             0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK                           0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB                            50
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB                            51
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK                           0x000c000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK                           0x0010000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK                             0x0020000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET                            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK                              0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET                               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB                                  55
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB                                  57
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK                                 0x0380000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               58
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               63
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x00000000000003ff
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x0000000000000400
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x000000000000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB                    16
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB                    27
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK                   0x000000000fff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET                    0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB                       28
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB                       31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK                      0x00000000f0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB                    35
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK                   0x0000000f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB         36
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB         51
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK        0x000ffff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB                                  52
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB                                  56
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK                                 0x01f0000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB                                  57
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB                                  63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK                                 0xfe00000000000000
+
+#endif
diff --git a/hw/fig/v1/rx_rxpcu_classification_overview.h b/hw/fig/v1/rx_rxpcu_classification_overview.h
new file mode 100644
index 000000000000..92489a5f5b2d
--- /dev/null
+++ b/hw/fig/v1/rx_rxpcu_classification_overview.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t filter_pass_mpdus                                       :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      phyrx_abort_received                                    :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      phyrx_abort_received                                    :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      filter_pass_mpdus                                       :  1;
+#endif
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET                   0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK                     0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET            0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK              0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK                  0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK           0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET                 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK                   0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK            0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK                  0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET      0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK        0x00000080
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET                          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB                             9
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB                             15
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK                            0x0000fe00
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET                         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB                            16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB                            31
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK                           0xffff0000
+
+#endif
diff --git a/hw/fig/v1/rx_start_param.h b/hw/fig/v1/rx_start_param.h
new file mode 100644
index 000000000000..bb2b87e3cc97
--- /dev/null
+++ b/hw/fig/v1/rx_start_param.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_START_PARAM_H_
+#define _RX_START_PARAM_H_
+
+#define NUM_OF_DWORDS_RX_START_PARAM 2
+
+#define NUM_OF_QWORDS_RX_START_PARAM 1
+
+struct rx_start_param {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      reserved_0a                                             : 12,
+                      remaining_rx_time                                       : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t remaining_rx_time                                       : 16,
+                      reserved_0a                                             : 12,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_START_PARAM_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define RX_START_PARAM_PKT_TYPE_LSB                                                 0
+#define RX_START_PARAM_PKT_TYPE_MSB                                                 3
+#define RX_START_PARAM_PKT_TYPE_MASK                                                0x000000000000000f
+
+#define RX_START_PARAM_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define RX_START_PARAM_RESERVED_0A_LSB                                              4
+#define RX_START_PARAM_RESERVED_0A_MSB                                              15
+#define RX_START_PARAM_RESERVED_0A_MASK                                             0x000000000000fff0
+
+#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET                                     0x0000000000000000
+#define RX_START_PARAM_REMAINING_RX_TIME_LSB                                        16
+#define RX_START_PARAM_REMAINING_RX_TIME_MSB                                        31
+#define RX_START_PARAM_REMAINING_RX_TIME_MASK                                       0x00000000ffff0000
+
+#define RX_START_PARAM_TLV64_PADDING_OFFSET                                         0x0000000000000000
+#define RX_START_PARAM_TLV64_PADDING_LSB                                            32
+#define RX_START_PARAM_TLV64_PADDING_MSB                                            63
+#define RX_START_PARAM_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rx_timing_info.h b/hw/fig/v1/rx_timing_info.h
new file mode 100644
index 000000000000..ea6780e25c55
--- /dev/null
+++ b/hw/fig/v1/rx_timing_info.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TIMING_INFO_H_
+#define _RX_TIMING_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TIMING_INFO 5
+
+struct rx_timing_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t residual_phase_offset                                   : 12,
+                      sub_usec_ts_rx_end                                      : 10,
+                      reserved                                                : 10;
+#else
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t reserved                                                : 10,
+                      sub_usec_ts_rx_end                                      : 10,
+                      residual_phase_offset                                   : 12;
+#endif
+};
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET                              0x00000000
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET                              0x00000004
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET                              0x00000008
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET                              0x0000000c
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                                 0x00000010
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB                                    0
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB                                    11
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK                                   0x00000fff
+
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET                                    0x00000010
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB                                       12
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB                                       21
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK                                      0x003ff000
+
+#define RX_TIMING_INFO_RESERVED_OFFSET                                              0x00000010
+#define RX_TIMING_INFO_RESERVED_LSB                                                 22
+#define RX_TIMING_INFO_RESERVED_MSB                                                 31
+#define RX_TIMING_INFO_RESERVED_MASK                                                0xffc00000
+
+#endif
diff --git a/hw/fig/v1/rx_trig_info.h b/hw/fig/v1/rx_trig_info.h
new file mode 100644
index 000000000000..b6b074118bea
--- /dev/null
+++ b/hw/fig/v1/rx_trig_info.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TRIG_INFO_H_
+#define _RX_TRIG_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TRIG_INFO 2
+
+#define NUM_OF_QWORDS_RX_TRIG_INFO 1
+
+struct rx_trig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_trigger_frame_type                                   :  2,
+                      trigger_resp_type                                       :  3,
+                      reserved_0                                              : 27;
+             uint32_t ppdu_duration                                           : 16,
+                      unique_destination_id                                   : 16;
+#else
+             uint32_t reserved_0                                              : 27,
+                      trigger_resp_type                                       :  3,
+                      rx_trigger_frame_type                                   :  2;
+             uint32_t unique_destination_id                                   : 16,
+                      ppdu_duration                                           : 16;
+#endif
+};
+
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB                                      0
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB                                      1
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK                                     0x0000000000000003
+
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET                                       0x0000000000000000
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB                                          2
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB                                          4
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK                                         0x000000000000001c
+
+#define RX_TRIG_INFO_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_TRIG_INFO_RESERVED_0_LSB                                                 5
+#define RX_TRIG_INFO_RESERVED_0_MSB                                                 31
+#define RX_TRIG_INFO_RESERVED_0_MASK                                                0x00000000ffffffe0
+
+#define RX_TRIG_INFO_PPDU_DURATION_OFFSET                                           0x0000000000000000
+#define RX_TRIG_INFO_PPDU_DURATION_LSB                                              32
+#define RX_TRIG_INFO_PPDU_DURATION_MSB                                              47
+#define RX_TRIG_INFO_PPDU_DURATION_MASK                                             0x0000ffff00000000
+
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB                                      48
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB                                      63
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/rxpcu_early_rx_indication.h b/hw/fig/v1/rxpcu_early_rx_indication.h
new file mode 100644
index 000000000000..d2dc464cf1cf
--- /dev/null
+++ b/hw/fig/v1/rxpcu_early_rx_indication.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_EARLY_RX_INDICATION_H_
+#define _RXPCU_EARLY_RX_INDICATION_H_
+
+#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2
+
+#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1
+
+struct rxpcu_early_rx_indication {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      reserved_0a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 18,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB                                      0
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB                                      3
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK                                     0x000000000000000f
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK                          0x0000000000000010
+
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB                                      5
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB                                      9
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK                                     0x00000000000003e0
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  10
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  13
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0000000000003c00
+
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET                                0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB                                   14
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB                                   31
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK                                  0x00000000ffffc000
+
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET                              0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB                                 32
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB                                 63
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK                                0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rxpcu_ppdu_end_info.h b/hw/fig/v1/rxpcu_ppdu_end_info.h
new file mode 100644
index 000000000000..2d53435fb817
--- /dev/null
+++ b/hw/fig/v1/rxpcu_ppdu_end_info.h
@@ -0,0 +1,925 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+#include "rxpcu_ppdu_end_layout_info.h"
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32
+
+#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16
+
+struct rxpcu_ppdu_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t rx_antenna                                              : 24,
+                      tx_ht_vht_ack                                           :  1,
+                      unsupported_mu_nc                                       :  1,
+                      otp_txbf_disable                                        :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      coex_wan_tx_after_start_of_rx_ratid1                    :  1;
+             uint32_t coex_bt_tx_from_start_of_rx                             :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      __reserved_g_0012                                                  :  2,
+                      dialog_token                                            :  8,
+                      follow_up_dialog_token                                  :  8,
+                      bb_captured_channel                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_timeout                                     :  1,
+                      __reserved_g_0066                                       :  1,
+                      __reserved_g_0067                                       :  1;
+             uint32_t before_mpdu_count_passing_fcs                           : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      reserved_4                                              :  2;
+             uint32_t after_mpdu_count_failing_fcs                            : 10,
+                      reserved_5                                              : 22;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t bb_length                                               : 16,
+                      bb_data                                                 :  1,
+                      reserved_8                                              :  3,
+                      first_bt_broadcast_status_details                       : 12;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      reserved_9                                              :  8;
+             uint32_t ast_index                                               : 16,
+                      ast_index_valid                                         :  1,
+                      reserved_10                                             :  3,
+                      second_bt_broadcast_status_details                      : 12;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint16_t pre_bt_broadcast_status_details                         : 12,
+                      reserved_12a                                            :  4;
+             uint32_t non_qos_sn_info_valid                                   :  1,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      rts_or_trig_prot_type                                   :  2,
+                      reserved_13a                                            :  2,
+                      non_qos_sn_highest                                      : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_lowest_retry_setting                         :  1;
+             uint32_t qos_sn_1_info_valid                                     :  1,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_tid                                            :  4,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_lowest_retry_setting                           :  1;
+             uint32_t qos_sn_2_info_valid                                     :  1,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_tid                                            :  4,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_lowest_retry_setting                           :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      qos_sn_1_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_peer_addr_15_0                         : 16;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t coex_tracker2_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      reserved_30a                                            : 22;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#else
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t coex_wan_tx_after_start_of_rx_ratid1                    :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      otp_txbf_disable                                        :  1,
+                      unsupported_mu_nc                                       :  1,
+                      tx_ht_vht_ack                                           :  1,
+                      rx_antenna                                              : 24;
+             uint32_t __reserved_g_0067                                       :  1,
+                      __reserved_g_0066                                       :  1,
+                      bb_captured_timeout                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_channel                                     :  1,
+                      follow_up_dialog_token                                  :  8,
+                      dialog_token                                            :  8,
+                      __reserved_g_0012                                                  :  2,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_bt_tx_from_start_of_rx                             :  1;
+             uint32_t reserved_4                                              :  2,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      before_mpdu_count_passing_fcs                           : 10;
+             uint32_t reserved_5                                              : 22,
+                      after_mpdu_count_failing_fcs                            : 10;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t first_bt_broadcast_status_details                       : 12,
+                      reserved_8                                              :  3,
+                      bb_data                                                 :  1,
+                      bb_length                                               : 16;
+             uint32_t reserved_9                                              :  8,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_10                                             :  3,
+                      ast_index_valid                                         :  1,
+                      ast_index                                               : 16;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             uint32_t reserved_12a                                            :  4,
+                      pre_bt_broadcast_status_details                         : 12;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint32_t non_qos_sn_lowest_retry_setting                         :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_highest                                      : 12,
+                      reserved_13a                                            :  2,
+                      rts_or_trig_prot_type                                   :  2,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      non_qos_sn_info_valid                                   :  1;
+             uint32_t qos_sn_1_lowest_retry_setting                           :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_tid                                            :  4,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_info_valid                                     :  1;
+             uint32_t qos_sn_2_lowest_retry_setting                           :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_tid                                            :  4,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_info_valid                                     :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t rts_or_trig_prot_peer_addr_15_0                         : 16,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_1_more_frag_state                                :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t reserved_30a                                            : 22,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker2_tx_from_start_of_rx                       :  1;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB                               0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB                               31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK                              0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB                               32
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB                               63
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK                              0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET                                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB                                          0
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB                                          23
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK                                         0x0000000000ffffff
+
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK                                      0x0000000001000000
+
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET                                0x0000000000000008
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK                                  0x0000000002000000
+
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET                                 0x0000000000000008
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK                                   0x0000000004000000
+
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK                             0x0000000008000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000020000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK                0x0000000040000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET             0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK               0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET                      0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK                        0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK                       0x0000000400000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK                      0x0000000800000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK                      0x0000001000000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK                     0x0000002000000000
+
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK                         0x0000004000000000
+
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET                                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB                                        41
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB                                        48
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK                                       0x0001fe0000000000
+
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB                              49
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB                              56
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK                             0x01fe000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK                                0x0200000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET                               0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB                                  58
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB                                  60
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK                                 0x1c00000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK                                0x2000000000000000
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB                       0
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB                       9
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK                      0x00000000000003ff
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB                       10
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB                       19
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK                      0x00000000000ffc00
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB                        20
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB                        29
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK                       0x000000003ff00000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB                                          30
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK                                         0x00000000c0000000
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB                        32
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB                        41
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK                       0x000003ff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB                                          42
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK                                         0xfffffc0000000000
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB                           0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB                           31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK                          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB                           32
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB                           63
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK                          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET                                        0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB                                           0
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB                                           15
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET                                          0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_DATA_LSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MASK                                            0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB                                          17
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB                                          19
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK                                         0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                0x0000000000000020
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                   20
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                   31
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                  0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET                                 0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB                                    32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB                                    55
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK                                   0x00ffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB                                          56
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK                                         0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET                                        0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB                                           0
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB                                           15
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET                                  0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK                                    0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET                                      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB                                         17
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB                                         19
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK                                        0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET               0x0000000000000028
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                  20
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                  31
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                 0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK  0x0000200000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK   0x0000400000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB   48
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB   63
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK  0xffff000000000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         8
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         15
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                     16
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                     27
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                    0x000000000fff0000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB                                        28
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK                                       0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK                              0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET                       0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK                         0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB                               34
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB                               35
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK                              0x0000000c00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB                                        36
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB                                        37
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK                                       0x0000003000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET                               0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB                                  38
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB                                  49
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK                                 0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET                 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK                   0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET                                0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB                                   51
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB                                   62
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK                                  0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK                    0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK                                0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK                                       0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB                                        2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB                                        5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK                                       0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB                                    6
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB                                    17
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK                                   0x000000000003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK                     0x0000000000040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB                                     19
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB                                     30
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK                                    0x000000007ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK                      0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK                                0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK                                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB                                        34
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB                                        37
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK                                       0x0000003c00000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB                                    38
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB                                    49
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK                                   0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK                     0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB                                     51
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB                                     62
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK                                    0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK                      0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB    0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB    1
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK   0x0000000000000003
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB        2
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB        7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK       0x00000000000000fc
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB        8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB        13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK       0x0000000000003f00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET      0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB         14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB         19
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK        0x00000000000fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET   0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB      20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB      25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK     0x0000000003f00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB    32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB    37
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK   0x0000003f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB  50
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB  55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB        56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB        62
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK       0x7f00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET        0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK          0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB           28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK          0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB           60
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK          0xf000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB   0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB   6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK  0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB   7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB   13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK  0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB           29
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK          0x00000000e0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB           57
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK          0xfe00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET   0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB      0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB      7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK     0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB  16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB  23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET    0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB       24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB       31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK      0x00000000ff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET     0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB        40
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB        47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK       0x0000ff0000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET        0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB           56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK          0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB           0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB           32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                      0x0000000000000068
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                        0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK                           0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB                             2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB                             5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK                            0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK                           0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB                             7
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB                             10
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK                            0x0000000000000780
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK                           0x0000000000000800
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET                        0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB                           12
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB                           15
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK                          0x000000000000f000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET                  0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB                     16
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB                     31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK                    0x00000000ffff0000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET                 0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB                    32
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB                    63
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK                   0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB                                0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB                                31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK                               0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB                                32
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB                                63
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK                               0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK                  0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK                 0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK                  0x0000000000000004
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK                 0x0000000000000008
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK                  0x0000000000000010
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK                 0x0000000000000020
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK                  0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK                 0x0000000000000080
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK                  0x0000000000000100
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK                 0x0000000000000200
+
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET                                     0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB                                        10
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK                                       0x00000000fffffc00
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET                               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB                                  32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB                                  63
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/rxpcu_ppdu_end_layout_info.h b/hw/fig/v1/rxpcu_ppdu_end_layout_info.h
new file mode 100644
index 000000000000..9d54e91522ec
--- /dev/null
+++ b/hw/fig/v1/rxpcu_ppdu_end_layout_info.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
+#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
+
+struct rxpcu_ppdu_end_layout_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_legacy_offset                                      :  2,
+                      l_sig_a_offset                                          :  6,
+                      l_sig_b_offset                                          :  6,
+                      ht_sig_offset                                           :  6,
+                      vht_sig_a_offset                                        :  6,
+                      repeat_l_sig_a_offset                                   :  6;
+             uint32_t he_sig_a_su_offset                                      :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      generic_u_sig_offset                                    :  6,
+                      rssi_ht_offset                                          :  7,
+                      reserved_1a                                             :  1;
+             uint32_t vht_sig_b_su20_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su160_offset                                  :  7,
+                      reserved_2a                                             :  4;
+             uint32_t vht_sig_b_mu20_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      reserved_3a                                             :  4;
+             uint32_t he_sig_b1_mu_offset                                     :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      first_generic_eht_sig_offset                            :  7,
+                      multiple_generic_eht_sig_included                       :  1,
+                      reserved_4a                                             :  3;
+             uint32_t common_user_info_offset                                 :  7,
+                      first_debug_info_offset                                 :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_other_receive_info_included                    :  1,
+                      reserved_5a                                             :  7;
+             uint32_t data_done_offset                                        :  8,
+                      generated_cbf_details_offset                            :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      location_offset                                         :  8;
+             uint32_t __reserved_g_0011                                       :  8,
+                      pkt_end_offset                                          :  8,
+                      abort_request_ack_offset                                :  8,
+                      reserved_7a                                             :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#else
+             uint32_t repeat_l_sig_a_offset                                   :  6,
+                      vht_sig_a_offset                                        :  6,
+                      ht_sig_offset                                           :  6,
+                      l_sig_b_offset                                          :  6,
+                      l_sig_a_offset                                          :  6,
+                      rssi_legacy_offset                                      :  2;
+             uint32_t reserved_1a                                             :  1,
+                      rssi_ht_offset                                          :  7,
+                      generic_u_sig_offset                                    :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_su_offset                                      :  6;
+             uint32_t reserved_2a                                             :  4,
+                      vht_sig_b_su160_offset                                  :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su20_offset                                   :  7;
+             uint32_t reserved_3a                                             :  4,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu20_offset                                   :  7;
+             uint32_t reserved_4a                                             :  3,
+                      multiple_generic_eht_sig_included                       :  1,
+                      first_generic_eht_sig_offset                            :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b1_mu_offset                                     :  7;
+             uint32_t reserved_5a                                             :  7,
+                      multiple_other_receive_info_included                    :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_debug_info_offset                                 :  8,
+                      common_user_info_offset                                 :  7;
+             uint32_t location_offset                                         :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      generated_cbf_details_offset                            :  8,
+                      data_done_offset                                        :  8;
+             uint32_t reserved_7a                                             :  8,
+                      abort_request_ack_offset                                :  8,
+                      pkt_end_offset                                          :  8,
+                      __reserved_g_0011                                       :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET                        0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB                           1
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK                          0x00000003
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB                               2
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB                               7
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK                              0x000000fc
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB                               13
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK                              0x00003f00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET                             0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB                                14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB                                19
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK                               0x000fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET                          0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB                             20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB                             25
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK                            0x03f00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET                     0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB                        26
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB                        31
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK                       0xfc000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET                        0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB                           5
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK                          0x0000003f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB                        11
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK                       0x00000fc0
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB                        12
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB                        17
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK                       0x0003f000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET                      0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB                         18
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK                        0x00fc0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET                            0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB                               24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB                               30
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK                              0x7f000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET                               0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK                                 0x80000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET                    0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET                               0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET                               0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB                          0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB                          6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK                         0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB                          7
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB                          13
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK                         0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB                       14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB                       20
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK                      0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET              0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB                 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB                 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK                0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET         0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK           0x10000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET                               0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB                                  29
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK                                 0xe0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB                      0
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB                      6
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK                     0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB                      7
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB                      14
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK                     0x00007f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET              0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK                0x00008000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET           0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB              16
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB              23
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK             0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET      0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK        0x01000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET                               0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB                                  25
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK                                 0xfe000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET                          0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB                             0
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB                             7
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK                            0x000000ff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET              0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB                 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK                0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET                      0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB                         16
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK                        0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET                           0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB                              24
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB                              31
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK                             0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET                            0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB                               15
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK                              0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET                  0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB                     16
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB                     23
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK                    0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET                               0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB                                  24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK                                 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET                               0x00000020
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK                                 0xffffffff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET                               0x00000024
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/fig/v1/rxpt_classify_info.h b/hw/fig/v1/rxpt_classify_info.h
new file mode 100644
index 000000000000..7fc572ae2474
--- /dev/null
+++ b/hw/fig/v1/rxpt_classify_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      lmac_peer_id_msb                                        :  2,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_1000                                   :  1,
+                      rxdma0_source_ring_selection                            :  3,
+                      rxdma0_destination_ring_selection                       :  3,
+                      mcast_echo_drop_enable                                  :  1,
+                      wds_learning_detect_en                                  :  1,
+                      intrabss_check_en                                       :  1,
+                      use_ppe                                                 :  1,
+                      ppe_routing_enable                                      :  1,
+                      cce_source_sel_en                                       :  1,
+                      reserved_0b                                             :  9;
+#else
+             uint32_t reserved_0b                                             :  9,
+                      cce_source_sel_en                                       :  1,
+                      ppe_routing_enable                                      :  1,
+                      use_ppe                                                 :  1,
+                      intrabss_check_en                                       :  1,
+                      wds_learning_detect_en                                  :  1,
+                      mcast_echo_drop_enable                                  :  1,
+                      rxdma0_destination_ring_selection                       :  3,
+                      rxdma0_source_ring_selection                            :  3,
+                      pkt_selection_fp_1000                                   :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      lmac_peer_id_msb                                        :  2,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET                        0x00000000
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB                           0
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB                           4
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK                          0x0000001f
+
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET                                  0x00000000
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB                                     5
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB                                     6
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK                                    0x00000060
+
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET                         0x00000000
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK                           0x00000080
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK                         0x00000100
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK                         0x00000200
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET                             0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK                               0x00000400
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB                         11
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB                         13
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK                        0x00003800
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB                    14
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB                    16
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK                   0x0001c000
+
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK                              0x00020000
+
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK                              0x00040000
+
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK                                   0x00080000
+
+#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET                                           0x00000000
+#define RXPT_CLASSIFY_INFO_USE_PPE_LSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MASK                                             0x00100000
+
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET                                0x00000000
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK                                  0x00200000
+
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK                                   0x00400000
+
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB                                          23
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB                                          31
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK                                         0xff800000
+
+#endif
diff --git a/hw/fig/v1/seq_hwio.h b/hw/fig/v1/seq_hwio.h
new file mode 100644
index 000000000000..69111d08d535
--- /dev/null
+++ b/hw/fig/v1/seq_hwio.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/hw/fig/v1/tcl_assist_cmd.h b/hw/fig/v1/tcl_assist_cmd.h
new file mode 100644
index 000000000000..f7a5bd5287cb
--- /dev/null
+++ b/hw/fig/v1/tcl_assist_cmd.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_ASSIST_CMD_H_
+#define _TCL_ASSIST_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16
+
+struct tcl_assist_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t buf_or_ext_desc_type                                    :  1,
+                      bank_id                                                 :  6,
+                      vdev_id                                                 :  8,
+                      data_length                                             : 14,
+                      to_fw_tqm                                               :  2,
+                      reserved_2a                                             :  1;
+             uint32_t reserved_3a                                             : 25,
+                      metadata_length                                         :  7;
+             uint32_t txpt_classify_info_index                                :  8,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_override                             :  1,
+                      flow_override_enable                                    :  1,
+                      flow_select                                             :  1,
+                      hlos_tid                                                :  4,
+                      hlos_tid_overwrite                                      :  1,
+                      tos_tc_value                                            :  8,
+                      reserved_4a                                             :  3;
+             uint32_t reserved_5a                                             : 16,
+                      l3_type                                                 : 16;
+             uint32_t l4_protocol                                             :  8,
+                      l4_port                                                 : 16,
+                      l4_port_type                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      da_is_bcast                                             :  1,
+                      reserved_6a                                             :  5;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t ip_da_or_sa                                             :  1,
+                      encap_length_change                                     :  6,
+                      encap_length_decrease                                   :  1,
+                      encap_length_override                                   :  1,
+                      type_or_length                                          :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      msdu_color                                              :  2,
+                      tx_notify_frame                                         :  3,
+                      tqm_no_drop                                             :  1,
+                      reserved_11a                                            : 12,
+                      l3_checksum_enable                                      :  1,
+                      l4_checksum_enable                                      :  1;
+             uint32_t buffer_timestamp                                        : 19,
+                      buffer_timestamp_valid                                  :  1,
+                      s_vlan_tag_present                                      :  1,
+                      c_vlan_tag_present                                      :  1,
+                      wmac_hdr_len                                            :  7,
+                      reserved_12a                                            :  3;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t reserved_2a                                             :  1,
+                      to_fw_tqm                                               :  2,
+                      data_length                                             : 14,
+                      vdev_id                                                 :  8,
+                      bank_id                                                 :  6,
+                      buf_or_ext_desc_type                                    :  1;
+             uint32_t metadata_length                                         :  7,
+                      reserved_3a                                             : 25;
+             uint32_t reserved_4a                                             :  3,
+                      tos_tc_value                                            :  8,
+                      hlos_tid_overwrite                                      :  1,
+                      hlos_tid                                                :  4,
+                      flow_select                                             :  1,
+                      flow_override_enable                                    :  1,
+                      txpt_classify_info_override                             :  1,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_index                                :  8;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             : 16;
+             uint32_t reserved_6a                                             :  5,
+                      da_is_bcast                                             :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      l4_port_type                                            :  1,
+                      l4_port                                                 : 16,
+                      l4_protocol                                             :  8;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t l4_checksum_enable                                      :  1,
+                      l3_checksum_enable                                      :  1,
+                      reserved_11a                                            : 12,
+                      tqm_no_drop                                             :  1,
+                      tx_notify_frame                                         :  3,
+                      msdu_color                                              :  2,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      type_or_length                                          :  1,
+                      encap_length_override                                   :  1,
+                      encap_length_decrease                                   :  1,
+                      encap_length_change                                     :  6,
+                      ip_da_or_sa                                             :  1;
+             uint32_t reserved_12a                                            :  3,
+                      wmac_hdr_len                                            :  7,
+                      c_vlan_tag_present                                      :  1,
+                      s_vlan_tag_present                                      :  1,
+                      buffer_timestamp_valid                                  :  1,
+                      buffer_timestamp                                        : 19;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            : 20;
+#endif
+};
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                        0x00000000
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                           0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                          0xffffffff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                       0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                          0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                          7
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                         0x000000ff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                   0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                      8
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                      11
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                     0x00000f00
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                        0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                           12
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                  0x00000008
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                    0x00000001
+
+#define TCL_ASSIST_CMD_BANK_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_BANK_ID_LSB                                                  1
+#define TCL_ASSIST_CMD_BANK_ID_MSB                                                  6
+#define TCL_ASSIST_CMD_BANK_ID_MASK                                                 0x0000007e
+
+#define TCL_ASSIST_CMD_VDEV_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_VDEV_ID_LSB                                                  7
+#define TCL_ASSIST_CMD_VDEV_ID_MSB                                                  14
+#define TCL_ASSIST_CMD_VDEV_ID_MASK                                                 0x00007f80
+
+#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_DATA_LENGTH_LSB                                              15
+#define TCL_ASSIST_CMD_DATA_LENGTH_MSB                                              28
+#define TCL_ASSIST_CMD_DATA_LENGTH_MASK                                             0x1fff8000
+
+#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET                                             0x00000008
+#define TCL_ASSIST_CMD_TO_FW_TQM_LSB                                                29
+#define TCL_ASSIST_CMD_TO_FW_TQM_MSB                                                30
+#define TCL_ASSIST_CMD_TO_FW_TQM_MASK                                               0x60000000
+
+#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_RESERVED_2A_LSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MASK                                             0x80000000
+
+#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET                                           0x0000000c
+#define TCL_ASSIST_CMD_RESERVED_3A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_3A_MSB                                              24
+#define TCL_ASSIST_CMD_RESERVED_3A_MASK                                             0x01ffffff
+
+#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET                                       0x0000000c
+#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB                                          25
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB                                          31
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK                                         0xfe000000
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET                              0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB                                 0
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB                                 7
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK                                0x000000ff
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET                                0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB                                   8
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB                                   12
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK                                  0x00001f00
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET                           0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK                             0x00002000
+
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                  0x00000010
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK                                    0x00004000
+
+#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_FLOW_SELECT_LSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MASK                                             0x00008000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OFFSET                                              0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_LSB                                                 16
+#define TCL_ASSIST_CMD_HLOS_TID_MSB                                                 19
+#define TCL_ASSIST_CMD_HLOS_TID_MASK                                                0x000f0000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET                                    0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET                                          0x00000010
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB                                             21
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB                                             28
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK                                            0x1fe00000
+
+#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_RESERVED_4A_LSB                                              29
+#define TCL_ASSIST_CMD_RESERVED_4A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_4A_MASK                                             0xe0000000
+
+#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET                                           0x00000014
+#define TCL_ASSIST_CMD_RESERVED_5A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_5A_MSB                                              15
+#define TCL_ASSIST_CMD_RESERVED_5A_MASK                                             0x0000ffff
+
+#define TCL_ASSIST_CMD_L3_TYPE_OFFSET                                               0x00000014
+#define TCL_ASSIST_CMD_L3_TYPE_LSB                                                  16
+#define TCL_ASSIST_CMD_L3_TYPE_MSB                                                  31
+#define TCL_ASSIST_CMD_L3_TYPE_MASK                                                 0xffff0000
+
+#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB                                              0
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB                                              7
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK                                             0x000000ff
+
+#define TCL_ASSIST_CMD_L4_PORT_OFFSET                                               0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_LSB                                                  8
+#define TCL_ASSIST_CMD_L4_PORT_MSB                                                  23
+#define TCL_ASSIST_CMD_L4_PORT_MASK                                                 0x00ffff00
+
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET                                          0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK                                            0x01000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET                                     0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK                                       0x02000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK                                             0x04000000
+
+#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_RESERVED_6A_LSB                                              27
+#define TCL_ASSIST_CMD_RESERVED_6A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_6A_MASK                                             0xf8000000
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET                                       0x0000001c
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB                                          0
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB                                          31
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK                                         0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET                                      0x00000020
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET                                      0x00000024
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET                                     0x00000028
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB                                        0
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB                                        31
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK                                       0xffffffff
+
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK                                             0x00000001
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB                                      1
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB                                      6
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK                                     0x0000007e
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK                                   0x00000080
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK                                   0x00000100
+
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET                                        0x0000002c
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK                                          0x00000200
+
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK                                     0x00000400
+
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET                          0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK                            0x00000800
+
+#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET                                            0x0000002c
+#define TCL_ASSIST_CMD_MSDU_COLOR_LSB                                               12
+#define TCL_ASSIST_CMD_MSDU_COLOR_MSB                                               13
+#define TCL_ASSIST_CMD_MSDU_COLOR_MASK                                              0x00003000
+
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET                                       0x0000002c
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB                                          14
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB                                          16
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK                                         0x0001c000
+
+#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK                                             0x00020000
+
+#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET                                          0x0000002c
+#define TCL_ASSIST_CMD_RESERVED_11A_LSB                                             18
+#define TCL_ASSIST_CMD_RESERVED_11A_MSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_11A_MASK                                            0x3ffc0000
+
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK                                      0x40000000
+
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK                                      0x80000000
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET                                      0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB                                         0
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB                                         18
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK                                        0x0007ffff
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK                                  0x00080000
+
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK                                      0x00200000
+
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB                                             22
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB                                             28
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK                                            0x1fc00000
+
+#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_RESERVED_12A_LSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_12A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_12A_MASK                                            0xe0000000
+
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET                                        0x00000034
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB                                           0
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB                                           31
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK                                          0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET                                          0x00000038
+#define TCL_ASSIST_CMD_RESERVED_14A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_14A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_14A_MASK                                            0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET                                          0x0000003c
+#define TCL_ASSIST_CMD_RESERVED_15A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_15A_MSB                                             19
+#define TCL_ASSIST_CMD_RESERVED_15A_MASK                                            0x000fffff
+
+#define TCL_ASSIST_CMD_RING_ID_OFFSET                                               0x0000003c
+#define TCL_ASSIST_CMD_RING_ID_LSB                                                  20
+#define TCL_ASSIST_CMD_RING_ID_MSB                                                  27
+#define TCL_ASSIST_CMD_RING_ID_MASK                                                 0x0ff00000
+
+#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET                                         0x0000003c
+#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB                                            28
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB                                            31
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK                                           0xf0000000
+
+#endif
diff --git a/hw/fig/v1/tcl_data_cmd.h b/hw/fig/v1/tcl_data_cmd.h
new file mode 100644
index 000000000000..dd90a2cdcb73
--- /dev/null
+++ b/hw/fig/v1/tcl_data_cmd.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_DATA_CMD 8
+
+struct tcl_data_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t tcl_cmd_type                                            :  1,
+                      buf_or_ext_desc_type                                    :  1,
+                      bank_id                                                 :  6,
+                      tx_notify_frame                                         :  3,
+                      header_length_read_sel                                  :  1,
+                      buffer_timestamp                                        : 19,
+                      buffer_timestamp_valid                                  :  1;
+             uint32_t reserved_3a                                             : 16,
+                      tcl_cmd_number                                          : 16;
+             uint32_t data_length                                             : 16,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      to_fw                                                   :  1,
+                      reserved_4a                                             :  1,
+                      packet_offset                                           :  9;
+             uint32_t hlos_tid_overwrite                                      :  1,
+                      flow_override_enable                                    :  1,
+                      who_classify_info_sel                                   :  2,
+                      hlos_tid                                                :  4,
+                      flow_override                                           :  1,
+                      pmac_id                                                 :  2,
+                      msdu_color                                              :  2,
+                      reserved_5a                                             : 11,
+                      vdev_id                                                 :  8;
+             uint32_t search_index                                            : 20,
+                      cache_set_num                                           :  4,
+                      index_lookup_override                                   :  1,
+                      reserved_6a                                             :  7;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t buffer_timestamp_valid                                  :  1,
+                      buffer_timestamp                                        : 19,
+                      header_length_read_sel                                  :  1,
+                      tx_notify_frame                                         :  3,
+                      bank_id                                                 :  6,
+                      buf_or_ext_desc_type                                    :  1,
+                      tcl_cmd_type                                            :  1;
+             uint32_t tcl_cmd_number                                          : 16,
+                      reserved_3a                                             : 16;
+             uint32_t packet_offset                                           :  9,
+                      reserved_4a                                             :  1,
+                      to_fw                                                   :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      data_length                                             : 16;
+             uint32_t vdev_id                                                 :  8,
+                      reserved_5a                                             : 11,
+                      msdu_color                                              :  2,
+                      pmac_id                                                 :  2,
+                      flow_override                                           :  1,
+                      hlos_tid                                                :  4,
+                      who_classify_info_sel                                   :  2,
+                      flow_override_enable                                    :  1,
+                      hlos_tid_overwrite                                      :  1;
+             uint32_t reserved_6a                                             :  7,
+                      index_lookup_override                                   :  1,
+                      cache_set_num                                           :  4,
+                      search_index                                            : 20;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                          0x00000000
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                             0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                             31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                            0xffffffff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                         0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                            0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                            7
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                           0x000000ff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                     0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                        8
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                        11
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                       0x00000f00
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                          0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                             12
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                             31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                            0xfffff000
+
+#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET                                            0x00000008
+#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB                                               0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB                                               0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK                                              0x00000001
+
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                    0x00000008
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                       1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                       1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                      0x00000002
+
+#define TCL_DATA_CMD_BANK_ID_OFFSET                                                 0x00000008
+#define TCL_DATA_CMD_BANK_ID_LSB                                                    2
+#define TCL_DATA_CMD_BANK_ID_MSB                                                    7
+#define TCL_DATA_CMD_BANK_ID_MASK                                                   0x000000fc
+
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET                                         0x00000008
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB                                            8
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB                                            10
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK                                           0x00000700
+
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET                                  0x00000008
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB                                     11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB                                     11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK                                    0x00000800
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET                                        0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB                                           12
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB                                           30
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK                                          0x7ffff000
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                  0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB                                     31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB                                     31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK                                    0x80000000
+
+#define TCL_DATA_CMD_RESERVED_3A_OFFSET                                             0x0000000c
+#define TCL_DATA_CMD_RESERVED_3A_LSB                                                0
+#define TCL_DATA_CMD_RESERVED_3A_MSB                                                15
+#define TCL_DATA_CMD_RESERVED_3A_MASK                                               0x0000ffff
+
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET                                          0x0000000c
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB                                             16
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB                                             31
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK                                            0xffff0000
+
+#define TCL_DATA_CMD_DATA_LENGTH_OFFSET                                             0x00000010
+#define TCL_DATA_CMD_DATA_LENGTH_LSB                                                0
+#define TCL_DATA_CMD_DATA_LENGTH_MSB                                                15
+#define TCL_DATA_CMD_DATA_LENGTH_MASK                                               0x0000ffff
+
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET                                        0x00000010
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB                                           16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB                                           16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK                                          0x00010000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                  17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                  17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00020000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                  18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                  18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00040000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                  19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                  19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00080000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                  20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                  20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00100000
+
+#define TCL_DATA_CMD_TO_FW_OFFSET                                                   0x00000010
+#define TCL_DATA_CMD_TO_FW_LSB                                                      21
+#define TCL_DATA_CMD_TO_FW_MSB                                                      21
+#define TCL_DATA_CMD_TO_FW_MASK                                                     0x00200000
+
+#define TCL_DATA_CMD_RESERVED_4A_OFFSET                                             0x00000010
+#define TCL_DATA_CMD_RESERVED_4A_LSB                                                22
+#define TCL_DATA_CMD_RESERVED_4A_MSB                                                22
+#define TCL_DATA_CMD_RESERVED_4A_MASK                                               0x00400000
+
+#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET                                           0x00000010
+#define TCL_DATA_CMD_PACKET_OFFSET_LSB                                              23
+#define TCL_DATA_CMD_PACKET_OFFSET_MSB                                              31
+#define TCL_DATA_CMD_PACKET_OFFSET_MASK                                             0xff800000
+
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET                                      0x00000014
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB                                         0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB                                         0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK                                        0x00000001
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                    0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB                                       1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB                                       1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK                                      0x00000002
+
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET                                   0x00000014
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB                                      2
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB                                      3
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK                                     0x0000000c
+
+#define TCL_DATA_CMD_HLOS_TID_OFFSET                                                0x00000014
+#define TCL_DATA_CMD_HLOS_TID_LSB                                                   4
+#define TCL_DATA_CMD_HLOS_TID_MSB                                                   7
+#define TCL_DATA_CMD_HLOS_TID_MASK                                                  0x000000f0
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET                                           0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB                                              8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB                                              8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK                                             0x00000100
+
+#define TCL_DATA_CMD_PMAC_ID_OFFSET                                                 0x00000014
+#define TCL_DATA_CMD_PMAC_ID_LSB                                                    9
+#define TCL_DATA_CMD_PMAC_ID_MSB                                                    10
+#define TCL_DATA_CMD_PMAC_ID_MASK                                                   0x00000600
+
+#define TCL_DATA_CMD_MSDU_COLOR_OFFSET                                              0x00000014
+#define TCL_DATA_CMD_MSDU_COLOR_LSB                                                 11
+#define TCL_DATA_CMD_MSDU_COLOR_MSB                                                 12
+#define TCL_DATA_CMD_MSDU_COLOR_MASK                                                0x00001800
+
+#define TCL_DATA_CMD_RESERVED_5A_OFFSET                                             0x00000014
+#define TCL_DATA_CMD_RESERVED_5A_LSB                                                13
+#define TCL_DATA_CMD_RESERVED_5A_MSB                                                23
+#define TCL_DATA_CMD_RESERVED_5A_MASK                                               0x00ffe000
+
+#define TCL_DATA_CMD_VDEV_ID_OFFSET                                                 0x00000014
+#define TCL_DATA_CMD_VDEV_ID_LSB                                                    24
+#define TCL_DATA_CMD_VDEV_ID_MSB                                                    31
+#define TCL_DATA_CMD_VDEV_ID_MASK                                                   0xff000000
+
+#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET                                            0x00000018
+#define TCL_DATA_CMD_SEARCH_INDEX_LSB                                               0
+#define TCL_DATA_CMD_SEARCH_INDEX_MSB                                               19
+#define TCL_DATA_CMD_SEARCH_INDEX_MASK                                              0x000fffff
+
+#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET                                           0x00000018
+#define TCL_DATA_CMD_CACHE_SET_NUM_LSB                                              20
+#define TCL_DATA_CMD_CACHE_SET_NUM_MSB                                              23
+#define TCL_DATA_CMD_CACHE_SET_NUM_MASK                                             0x00f00000
+
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET                                   0x00000018
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB                                      24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB                                      24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK                                     0x01000000
+
+#define TCL_DATA_CMD_RESERVED_6A_OFFSET                                             0x00000018
+#define TCL_DATA_CMD_RESERVED_6A_LSB                                                25
+#define TCL_DATA_CMD_RESERVED_6A_MSB                                                31
+#define TCL_DATA_CMD_RESERVED_6A_MASK                                               0xfe000000
+
+#define TCL_DATA_CMD_RESERVED_7A_OFFSET                                             0x0000001c
+#define TCL_DATA_CMD_RESERVED_7A_LSB                                                0
+#define TCL_DATA_CMD_RESERVED_7A_MSB                                                19
+#define TCL_DATA_CMD_RESERVED_7A_MASK                                               0x000fffff
+
+#define TCL_DATA_CMD_RING_ID_OFFSET                                                 0x0000001c
+#define TCL_DATA_CMD_RING_ID_LSB                                                    20
+#define TCL_DATA_CMD_RING_ID_MSB                                                    27
+#define TCL_DATA_CMD_RING_ID_MASK                                                   0x0ff00000
+
+#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET                                           0x0000001c
+#define TCL_DATA_CMD_LOOPING_COUNT_LSB                                              28
+#define TCL_DATA_CMD_LOOPING_COUNT_MSB                                              31
+#define TCL_DATA_CMD_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/fig/v1/tcl_gse_cmd.h b/hw/fig/v1/tcl_gse_cmd.h
new file mode 100644
index 000000000000..992368aa31a1
--- /dev/null
+++ b/hw/fig/v1/tcl_gse_cmd.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 8
+
+struct tcl_gse_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t control_buffer_addr_31_0                                : 32;
+             uint32_t control_buffer_addr_39_32                               :  8,
+                      gse_ctrl                                                :  4,
+                      gse_sel                                                 :  1,
+                      status_destination_ring_id                              :  1,
+                      swap                                                    :  1,
+                      index_search_en                                         :  1,
+                      cache_set_num                                           :  4,
+                      reserved_1a                                             : 12;
+             uint32_t tcl_cmd_type                                            :  1,
+                      reserved_2a                                             : 31;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t control_buffer_addr_31_0                                : 32;
+             uint32_t reserved_1a                                             : 12,
+                      cache_set_num                                           :  4,
+                      index_search_en                                         :  1,
+                      swap                                                    :  1,
+                      status_destination_ring_id                              :  1,
+                      gse_sel                                                 :  1,
+                      gse_ctrl                                                :  4,
+                      control_buffer_addr_39_32                               :  8;
+             uint32_t reserved_2a                                             : 31,
+                      tcl_cmd_type                                            :  1;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET                                 0x00000000
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB                                    0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB                                    31
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK                                   0xffffffff
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET                                0x00000004
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB                                   0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB                                   7
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK                                  0x000000ff
+
+#define TCL_GSE_CMD_GSE_CTRL_OFFSET                                                 0x00000004
+#define TCL_GSE_CMD_GSE_CTRL_LSB                                                    8
+#define TCL_GSE_CMD_GSE_CTRL_MSB                                                    11
+#define TCL_GSE_CMD_GSE_CTRL_MASK                                                   0x00000f00
+
+#define TCL_GSE_CMD_GSE_SEL_OFFSET                                                  0x00000004
+#define TCL_GSE_CMD_GSE_SEL_LSB                                                     12
+#define TCL_GSE_CMD_GSE_SEL_MSB                                                     12
+#define TCL_GSE_CMD_GSE_SEL_MASK                                                    0x00001000
+
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET                               0x00000004
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB                                  13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB                                  13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK                                 0x00002000
+
+#define TCL_GSE_CMD_SWAP_OFFSET                                                     0x00000004
+#define TCL_GSE_CMD_SWAP_LSB                                                        14
+#define TCL_GSE_CMD_SWAP_MSB                                                        14
+#define TCL_GSE_CMD_SWAP_MASK                                                       0x00004000
+
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET                                          0x00000004
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB                                             15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB                                             15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK                                            0x00008000
+
+#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET                                            0x00000004
+#define TCL_GSE_CMD_CACHE_SET_NUM_LSB                                               16
+#define TCL_GSE_CMD_CACHE_SET_NUM_MSB                                               19
+#define TCL_GSE_CMD_CACHE_SET_NUM_MASK                                              0x000f0000
+
+#define TCL_GSE_CMD_RESERVED_1A_OFFSET                                              0x00000004
+#define TCL_GSE_CMD_RESERVED_1A_LSB                                                 20
+#define TCL_GSE_CMD_RESERVED_1A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_1A_MASK                                                0xfff00000
+
+#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET                                             0x00000008
+#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB                                                0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB                                                0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK                                               0x00000001
+
+#define TCL_GSE_CMD_RESERVED_2A_OFFSET                                              0x00000008
+#define TCL_GSE_CMD_RESERVED_2A_LSB                                                 1
+#define TCL_GSE_CMD_RESERVED_2A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_2A_MASK                                                0xfffffffe
+
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET                                       0x0000000c
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB                                          0
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB                                          31
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK                                         0xffffffff
+
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET                                      0x00000010
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB                                         0
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB                                         31
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK                                        0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_5A_OFFSET                                              0x00000014
+#define TCL_GSE_CMD_RESERVED_5A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_5A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_5A_MASK                                                0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_6A_OFFSET                                              0x00000018
+#define TCL_GSE_CMD_RESERVED_6A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_6A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_6A_MASK                                                0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_7A_OFFSET                                              0x0000001c
+#define TCL_GSE_CMD_RESERVED_7A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_7A_MSB                                                 19
+#define TCL_GSE_CMD_RESERVED_7A_MASK                                                0x000fffff
+
+#define TCL_GSE_CMD_RING_ID_OFFSET                                                  0x0000001c
+#define TCL_GSE_CMD_RING_ID_LSB                                                     20
+#define TCL_GSE_CMD_RING_ID_MSB                                                     27
+#define TCL_GSE_CMD_RING_ID_MASK                                                    0x0ff00000
+
+#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET                                            0x0000001c
+#define TCL_GSE_CMD_LOOPING_COUNT_LSB                                               28
+#define TCL_GSE_CMD_LOOPING_COUNT_MSB                                               31
+#define TCL_GSE_CMD_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/fig/v1/tcl_status_ring.h b/hw/fig/v1/tcl_status_ring.h
new file mode 100644
index 000000000000..5a24217c95d5
--- /dev/null
+++ b/hw/fig/v1/tcl_status_ring.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t gse_ctrl                                                :  4,
+                      ase_fse_sel                                             :  1,
+                      cache_op_res                                            :  2,
+                      index_search_en                                         :  1,
+                      msdu_cnt_n                                              : 24;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t hash_indx_val                                           : 20,
+                      cache_set_num                                           :  4,
+                      reserved_5a                                             :  8;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t msdu_cnt_n                                              : 24,
+                      index_search_en                                         :  1,
+                      cache_op_res                                            :  2,
+                      ase_fse_sel                                             :  1,
+                      gse_ctrl                                                :  4;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             :  8,
+                      cache_set_num                                           :  4,
+                      hash_indx_val                                           : 20;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_STATUS_RING_GSE_CTRL_OFFSET                                             0x00000000
+#define TCL_STATUS_RING_GSE_CTRL_LSB                                                0
+#define TCL_STATUS_RING_GSE_CTRL_MSB                                                3
+#define TCL_STATUS_RING_GSE_CTRL_MASK                                               0x0000000f
+
+#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET                                          0x00000000
+#define TCL_STATUS_RING_ASE_FSE_SEL_LSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MASK                                            0x00000010
+
+#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET                                         0x00000000
+#define TCL_STATUS_RING_CACHE_OP_RES_LSB                                            5
+#define TCL_STATUS_RING_CACHE_OP_RES_MSB                                            6
+#define TCL_STATUS_RING_CACHE_OP_RES_MASK                                           0x00000060
+
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET                                      0x00000000
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK                                        0x00000080
+
+#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET                                           0x00000000
+#define TCL_STATUS_RING_MSDU_CNT_N_LSB                                              8
+#define TCL_STATUS_RING_MSDU_CNT_N_MSB                                              31
+#define TCL_STATUS_RING_MSDU_CNT_N_MASK                                             0xffffff00
+
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET                                      0x00000004
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET                                      0x00000008
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET                                   0x0000000c
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB                                      0
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB                                      31
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK                                     0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET                                  0x00000010
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB                                     0
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB                                     31
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK                                    0xffffffff
+
+#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_HASH_INDX_VAL_LSB                                           0
+#define TCL_STATUS_RING_HASH_INDX_VAL_MSB                                           19
+#define TCL_STATUS_RING_HASH_INDX_VAL_MASK                                          0x000fffff
+
+#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_CACHE_SET_NUM_LSB                                           20
+#define TCL_STATUS_RING_CACHE_SET_NUM_MSB                                           23
+#define TCL_STATUS_RING_CACHE_SET_NUM_MASK                                          0x00f00000
+
+#define TCL_STATUS_RING_RESERVED_5A_OFFSET                                          0x00000014
+#define TCL_STATUS_RING_RESERVED_5A_LSB                                             24
+#define TCL_STATUS_RING_RESERVED_5A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_5A_MASK                                            0xff000000
+
+#define TCL_STATUS_RING_RESERVED_6A_OFFSET                                          0x00000018
+#define TCL_STATUS_RING_RESERVED_6A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_6A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_6A_MASK                                            0xffffffff
+
+#define TCL_STATUS_RING_RESERVED_7A_OFFSET                                          0x0000001c
+#define TCL_STATUS_RING_RESERVED_7A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_7A_MSB                                             19
+#define TCL_STATUS_RING_RESERVED_7A_MASK                                            0x000fffff
+
+#define TCL_STATUS_RING_RING_ID_OFFSET                                              0x0000001c
+#define TCL_STATUS_RING_RING_ID_LSB                                                 20
+#define TCL_STATUS_RING_RING_ID_MSB                                                 27
+#define TCL_STATUS_RING_RING_ID_MASK                                                0x0ff00000
+
+#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET                                        0x0000001c
+#define TCL_STATUS_RING_LOOPING_COUNT_LSB                                           28
+#define TCL_STATUS_RING_LOOPING_COUNT_MSB                                           31
+#define TCL_STATUS_RING_LOOPING_COUNT_MASK                                          0xf0000000
+
+#endif
diff --git a/hw/fig/v1/tlv_hdr.h b/hw/fig/v1/tlv_hdr.h
new file mode 100644
index 000000000000..a2defe7be508
--- /dev/null
+++ b/hw/fig/v1/tlv_hdr.h
@@ -0,0 +1,634 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+
+#define _TLV_USERID_WIDTH_      6
+
+#define _TLV_MRV_EN_LEN_WIDTH_  9
+#define _TLV_MRV_DIS_LEN_WIDTH_ 12
+
+#define _TLV_DATA_WIDTH_        32
+#define _TLV_64_DATA_WIDTH_     64
+#define _TLV_CDATA_WIDTH_       32
+#define _TLV_77_DATA_WIDTH_     77
+#define _TLV_CDATA_77_WIDTH_    64
+
+#define _TLV_TAG_WIDTH_         10
+#define _TLV_CTAG_WIDTH_        6
+
+struct tlv_mlo_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6;
+#else
+           uint32_t             tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_52  :   52;
+           uint64_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint64_t             tlv_cdata_lower_52  :   52,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mlo_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_usr_c_77_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_20  :   20;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+           uint32_t             pad_96to128_bit     :   32;
+#else
+           uint32_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             pad_77to96_bit      :   20,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint32_t             pad_96to128_bit     :   32;
+#endif
+};
+
+struct tlv_usr_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_reserved        :   32;
+#else
+           uint64_t             tlv_reserved        :   32,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6,
+                                pad_32to64_bit      :   32;
+#else
+           uint64_t             pad_32to64_bit      :   32,
+                                tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to95_bit      :   19;
+#else
+           uint32_t             pad_77to95_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+#else
+           uint32_t             pad_77to96_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata           :   _TLV_CDATA_WIDTH_,
+                                pad_44to64_bit      :   20;
+#else
+           uint64_t             tlv_cdata_lower_20  :   20,
+                                pad_44to64_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+#endif
+};
+
+#endif
diff --git a/hw/fig/v1/tlv_tag_def.h b/hw/fig/v1/tlv_tag_def.h
new file mode 100644
index 000000000000..8189c6ec5601
--- /dev/null
+++ b/hw/fig/v1/tlv_tag_def.h
@@ -0,0 +1,1976 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum tlv_tag_def {
+  WIFIMACTX_CBF_START_E                                    = 0  ,
+  WIFIPHYRX_DATA_E                                         = 1  ,
+  WIFIPHYRX_CBF_DATA_RESP_E                                = 2  ,
+  WIFIPHYRX_ABORT_REQUEST_E                                = 3  ,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E                      = 4  ,
+  WIFIMACTX_DATA_RESP_E                                    = 5  ,
+  WIFIMACTX_CBF_DATA_E                                     = 6  ,
+  WIFIMACTX_CBF_DONE_E                                     = 7  ,
+  WIFIPHYRX_LMR_DATA_RESP_E                                = 8  ,
+  WIFIRXPCU_TO_UCODE_START_E                               = 9  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E             = 10  ,
+  WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E                      = 11  ,
+  WIFIRXPCU_TO_UCODE_FCS_STATUS_E                          = 12  ,
+  WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E                      = 13  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E           = 14  ,
+  WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E                    = 15  ,
+  WIFIRXPCU_TO_UCODE_END_E                                 = 16  ,
+  WIFIPHYRX_RSSI_LEGACY_20MHZ_E                            = 17  ,
+  WIFIPHYRX_NC_ABORT_REQUEST_E                             = 18  ,
+  WIFIPHYRX_PKT_END_20MHZ_E                                = 19  ,
+  WIFIPHYRX_NC_DATA_E                                      = 20  ,
+  WIFIMACRX_CBF_READ_REQUEST_E                             = 64  ,
+  WIFIMACRX_CBF_DATA_REQUEST_E                             = 65  ,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E                         = 66  ,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E                       = 67  ,
+  WIFIMACRX_NDP_TIMEOUT_E                                  = 68  ,
+  WIFIMACRX_ABORT_ACK_E                                    = 69  ,
+  WIFIMACRX_REQ_IMPLICIT_FB_E                              = 70  ,
+  WIFIMACRX_CHAIN_MASK_E                                   = 71  ,
+  WIFIMACRX_NAP_USER_E                                     = 72  ,
+  WIFIMACRX_ABORT_REQUEST_E                                = 73  ,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E                        = 74  ,
+  WIFIPHYTX_ABORT_ACK_E                                    = 75  ,
+  WIFIPHYTX_ABORT_REQUEST_E                                = 76  ,
+  WIFIPHYTX_PKT_END_E                                      = 77  ,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E                     = 78  ,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E                            = 79  ,
+  WIFIPHYTX_DATA_REQUEST_E                                 = 80  ,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E                           = 81  ,
+  WIFIPHYTX_NAP_ACK_E                                      = 82  ,
+  WIFIPHYTX_NAP_DONE_E                                     = 83  ,
+  WIFIPHYTX_OFF_ACK_E                                      = 84  ,
+  WIFIPHYTX_ON_ACK_E                                       = 85  ,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                                = 86  ,
+  WIFIPHYTX_DEBUG16_E                                      = 87  ,
+  WIFIMACTX_ABORT_REQUEST_E                                = 88  ,
+  WIFIMACTX_ABORT_ACK_E                                    = 89  ,
+  WIFIMACTX_PKT_END_E                                      = 90  ,
+  WIFIMACTX_PRE_PHY_DESC_E                                 = 91  ,
+  WIFIMACTX_BF_PARAMS_COMMON_E                             = 92  ,
+  WIFIMACTX_BF_PARAMS_PER_USER_E                           = 93  ,
+  WIFIMACTX_PREFETCH_CV_E                                  = 94  ,
+  WIFIMACTX_USER_DESC_COMMON_E                             = 95  ,
+  WIFIMACTX_USER_DESC_PER_USER_E                           = 96  ,
+  WIFIEXAMPLE_USER_TLV_16_E                                = 97  ,
+  WIFIEXAMPLE_TLV_16_E                                     = 98  ,
+  WIFIMACTX_PHY_OFF_E                                      = 99  ,
+  WIFIMACTX_PHY_ON_E                                       = 100  ,
+  WIFIMACTX_SYNTH_OFF_E                                    = 101  ,
+  WIFIMACTX_EXPECT_CBF_COMMON_E                            = 102  ,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E                          = 103  ,
+  WIFIMACTX_PHY_DESC_E                                     = 104  ,
+  WIFIMACTX_L_SIG_A_E                                      = 105  ,
+  WIFIMACTX_L_SIG_B_E                                      = 106  ,
+  WIFIMACTX_HT_SIG_E                                       = 107  ,
+  WIFIMACTX_VHT_SIG_A_E                                    = 108  ,
+  WIFIMACTX_VHT_SIG_B_SU20_E                               = 109  ,
+  WIFIMACTX_VHT_SIG_B_SU40_E                               = 110  ,
+  WIFIMACTX_VHT_SIG_B_SU80_E                               = 111  ,
+  WIFIMACTX_VHT_SIG_B_SU160_E                              = 112  ,
+  WIFIMACTX_VHT_SIG_B_MU20_E                               = 113  ,
+  WIFIMACTX_VHT_SIG_B_MU40_E                               = 114  ,
+  WIFIMACTX_VHT_SIG_B_MU80_E                               = 115  ,
+  WIFIMACTX_VHT_SIG_B_MU160_E                              = 116  ,
+  WIFIMACTX_SERVICE_E                                      = 117  ,
+  WIFIMACTX_HE_SIG_A_SU_E                                  = 118  ,
+  WIFIMACTX_HE_SIG_A_MU_DL_E                               = 119  ,
+  WIFIMACTX_HE_SIG_A_MU_UL_E                               = 120  ,
+  WIFIMACTX_HE_SIG_B1_MU_E                                 = 121  ,
+  WIFIMACTX_HE_SIG_B2_MU_E                                 = 122  ,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E                              = 123  ,
+  WIFIMACTX_DELETE_CV_E                                    = 124  ,
+  WIFIMACTX_MU_UPLINK_COMMON_E                             = 125  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E                         = 126  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E                          = 127  ,
+  WIFIMACTX_PHY_NAP_E                                      = 128  ,
+  WIFIMACTX_DEBUG_E                                        = 129  ,
+  WIFIPHYRX_ABORT_ACK_E                                    = 130  ,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E                        = 131  ,
+  WIFIPHYRX_RSSI_LEGACY_E                                  = 132  ,
+  WIFIPHYRX_RSSI_HT_E                                      = 133  ,
+  WIFIPHYRX_USER_INFO_E                                    = 134  ,
+  WIFIPHYRX_PKT_END_E                                      = 135  ,
+  WIFIPHYRX_DEBUG_E                                        = 136  ,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E                            = 137  ,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E                           = 138  ,
+  WIFIPHYRX_L_SIG_A_E                                      = 139  ,
+  WIFIPHYRX_L_SIG_B_E                                      = 140  ,
+  WIFIPHYRX_HT_SIG_E                                       = 141  ,
+  WIFIPHYRX_VHT_SIG_A_E                                    = 142  ,
+  WIFIPHYRX_VHT_SIG_B_SU20_E                               = 143  ,
+  WIFIPHYRX_VHT_SIG_B_SU40_E                               = 144  ,
+  WIFIPHYRX_VHT_SIG_B_SU80_E                               = 145  ,
+  WIFIPHYRX_VHT_SIG_B_SU160_E                              = 146  ,
+  WIFIPHYRX_VHT_SIG_B_MU20_E                               = 147  ,
+  WIFIPHYRX_VHT_SIG_B_MU40_E                               = 148  ,
+  WIFIPHYRX_VHT_SIG_B_MU80_E                               = 149  ,
+  WIFIPHYRX_VHT_SIG_B_MU160_E                              = 150  ,
+  WIFIPHYRX_HE_SIG_A_SU_E                                  = 151  ,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E                               = 152  ,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E                               = 153  ,
+  WIFIPHYRX_HE_SIG_B1_MU_E                                 = 154  ,
+  WIFIPHYRX_HE_SIG_B2_MU_E                                 = 155  ,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E                              = 156  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E                           = 157  ,
+  WIFIPHYRX_COMMON_USER_INFO_E                             = 158  ,
+  WIFIPHYRX_DATA_DONE_E                                    = 159  ,
+  WIFICOEX_TX_REQ_E                                        = 160  ,
+  WIFIDUMMY_E                                              = 161  ,
+  WIFIEXAMPLE_TLV_32_NAME_E                                = 162  ,
+  WIFIMPDU_LIMIT_E                                         = 163  ,
+  WIFINA_LENGTH_END_E                                      = 164  ,
+  WIFIOLE_BUF_STATUS_E                                     = 165  ,
+  WIFIPCU_PPDU_SETUP_DONE_E                                = 166  ,
+  WIFIPCU_PPDU_SETUP_END_E                                 = 167  ,
+  WIFIPCU_PPDU_SETUP_INIT_E                                = 168  ,
+  WIFIPCU_PPDU_SETUP_START_E                               = 169  ,
+  WIFIPDG_FES_SETUP_E                                      = 170  ,
+  WIFIPDG_RESPONSE_E                                       = 171  ,
+  WIFIPDG_TX_REQ_E                                         = 172  ,
+  WIFISCH_WAIT_INSTR_E                                     = 173  ,
+  WIFIMACTX_SWITCH_TO_MAIN_E                               = 174  ,
+  WIFIPHYTX_LINK_STATE_E                                   = 175  ,
+  WIFIAUX_PPDU_END_E                                       = 176  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E                           = 177  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E                    = 178  ,
+  WIFITQM_GEN_MPDUS_E                                      = 179  ,
+  WIFITQM_GEN_MPDUS_STATUS_E                               = 180  ,
+  WIFITQM_REMOVE_MPDU_E                                    = 181  ,
+  WIFITQM_REMOVE_MPDU_STATUS_E                             = 182  ,
+  WIFITQM_REMOVE_MSDU_E                                    = 183  ,
+  WIFITQM_REMOVE_MSDU_STATUS_E                             = 184  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E                           = 185  ,
+  WIFITQM_WRITE_CMD_E                                      = 186  ,
+  WIFIOFDMA_TRIGGER_DETAILS_E                              = 187  ,
+  WIFITX_DATA_E                                            = 188  ,
+  WIFITX_FES_SETUP_E                                       = 189  ,
+  WIFIRX_PACKET_E                                          = 190  ,
+  WIFIEXPECTED_RESPONSE_E                                  = 191  ,
+  WIFITX_MPDU_END_E                                        = 192  ,
+  WIFITX_MPDU_START_E                                      = 193  ,
+  WIFITX_MSDU_END_E                                        = 194  ,
+  WIFITX_MSDU_START_E                                      = 195  ,
+  WIFITX_SW_MODE_SETUP_E                                   = 196  ,
+  WIFITXPCU_BUFFER_STATUS_E                                = 197  ,
+  WIFITXPCU_USER_BUFFER_STATUS_E                           = 198  ,
+  WIFIDATA_TO_TIME_CONFIG_E                                = 199  ,
+  WIFIEXAMPLE_USER_TLV_32_E                                = 200  ,
+  WIFIMPDU_INFO_E                                          = 201  ,
+  WIFIPDG_USER_SETUP_E                                     = 202  ,
+  WIFITX_11AH_SETUP_E                                      = 203  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E                     = 204  ,
+  WIFITX_PEER_ENTRY_E                                      = 205  ,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E                       = 206  ,
+  WIFIEXAMPLE_USER_TLV_44_E                                = 207  ,
+  WIFITX_FLUSH_E                                           = 208  ,
+  WIFITX_FLUSH_REQ_E                                       = 209  ,
+  WIFITQM_WRITE_CMD_STATUS_E                               = 210  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E                           = 211  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_E                            = 212  ,
+  WIFIEXAMPLE_USER_CTLV_44_E                               = 213  ,
+  WIFITX_FES_STATUS_START_E                                = 214  ,
+  WIFITX_FES_STATUS_USER_PPDU_E                            = 215  ,
+  WIFITX_FES_STATUS_USER_RESPONSE_E                        = 216  ,
+  WIFITX_FES_STATUS_END_E                                  = 217  ,
+  WIFIRX_TRIG_INFO_E                                       = 218  ,
+  WIFIRXPCU_TX_SETUP_CLEAR_E                               = 219  ,
+  WIFIRX_FRAME_BITMAP_REQ_E                                = 220  ,
+  WIFIRX_FRAME_BITMAP_ACK_E                                = 221  ,
+  WIFICOEX_RX_STATUS_E                                     = 222  ,
+  WIFIRX_START_PARAM_E                                     = 223  ,
+  WIFIRX_PPDU_START_E                                      = 224  ,
+  WIFIRX_PPDU_END_E                                        = 225  ,
+  WIFIRX_MPDU_START_E                                      = 226  ,
+  WIFIRX_MPDU_END_E                                        = 227  ,
+  WIFIRX_MSDU_START_E                                      = 228  ,
+  WIFIRX_MSDU_END_E                                        = 229  ,
+  WIFIRX_ATTENTION_E                                       = 230  ,
+  WIFIRECEIVED_RESPONSE_INFO_E                             = 231  ,
+  WIFIRX_PHY_SLEEP_E                                       = 232  ,
+  WIFIRX_HEADER_E                                          = 233  ,
+  WIFIRX_PEER_ENTRY_E                                      = 234  ,
+  WIFIRX_FLUSH_E                                           = 235  ,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E                          = 236  ,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E                           = 237  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E                    = 238  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E                     = 239  ,
+  WIFITX_CBF_INFO_E                                        = 240  ,
+  WIFIPCU_PPDU_SETUP_USER_E                                = 241  ,
+  WIFIRX_MPDU_PCU_START_E                                  = 242  ,
+  WIFIRX_PM_INFO_E                                         = 243  ,
+  WIFIRX_USER_PPDU_END_E                                   = 244  ,
+  WIFIRX_PRE_PPDU_START_E                                  = 245  ,
+  WIFIRX_PREAMBLE_E                                        = 246  ,
+  WIFITX_FES_SETUP_COMPLETE_E                              = 247  ,
+  WIFITX_LAST_MPDU_FETCHED_E                               = 248  ,
+  WIFITXDMA_STOP_REQUEST_E                                 = 249  ,
+  WIFIRXPCU_SETUP_E                                        = 250  ,
+  WIFIRXPCU_USER_SETUP_E                                   = 251  ,
+  WIFITX_FES_STATUS_ACK_OR_BA_E                            = 252  ,
+  WIFITQM_ACKED_MPDU_E                                     = 253  ,
+  WIFICOEX_TX_RESP_E                                       = 254  ,
+  WIFICOEX_TX_STATUS_E                                     = 255  ,
+  WIFIMACTX_COEX_PHY_CTRL_E                                = 256  ,
+  WIFICOEX_STATUS_BROADCAST_E                              = 257  ,
+  WIFIRESPONSE_START_STATUS_E                              = 258  ,
+  WIFIRESPONSE_END_STATUS_E                                = 259  ,
+  WIFICRYPTO_STATUS_E                                      = 260  ,
+  WIFIRECEIVED_TRIGGER_INFO_E                              = 261  ,
+  WIFICOEX_TX_STOP_CTRL_E                                  = 262  ,
+  WIFIRX_PPDU_ACK_REPORT_E                                 = 263  ,
+  WIFIRX_PPDU_NO_ACK_REPORT_E                              = 264  ,
+  WIFISCH_COEX_STATUS_E                                    = 265  ,
+  WIFISCHEDULER_COMMAND_STATUS_E                           = 266  ,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E               = 267  ,
+  WIFITX_FES_STATUS_PROT_E                                 = 268  ,
+  WIFITX_FES_STATUS_START_PPDU_E                           = 269  ,
+  WIFITX_FES_STATUS_START_PROT_E                           = 270  ,
+  WIFITXPCU_PHYTX_DEBUG32_E                                = 271  ,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E                  = 272  ,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E                         = 273  ,
+  WIFIWHO_ANCHOR_OFFSET_E                                  = 274  ,
+  WIFIWHO_ANCHOR_VALUE_E                                   = 275  ,
+  WIFIWHO_CCE_INFO_E                                       = 276  ,
+  WIFIWHO_COMMIT_E                                         = 277  ,
+  WIFIWHO_COMMIT_DONE_E                                    = 278  ,
+  WIFIWHO_FLUSH_E                                          = 279  ,
+  WIFIWHO_L2_LLC_E                                         = 280  ,
+  WIFIWHO_L2_PAYLOAD_E                                     = 281  ,
+  WIFIWHO_L3_CHECKSUM_E                                    = 282  ,
+  WIFIWHO_L3_INFO_E                                        = 283  ,
+  WIFIWHO_L4_CHECKSUM_E                                    = 284  ,
+  WIFIWHO_L4_INFO_E                                        = 285  ,
+  WIFIWHO_MSDU_E                                           = 286  ,
+  WIFIWHO_MSDU_MISC_E                                      = 287  ,
+  WIFIWHO_PACKET_DATA_E                                    = 288  ,
+  WIFIWHO_PACKET_HDR_E                                     = 289  ,
+  WIFIWHO_PPDU_END_E                                       = 290  ,
+  WIFIWHO_PPDU_START_E                                     = 291  ,
+  WIFIWHO_TSO_E                                            = 292  ,
+  WIFIWHO_WMAC_HEADER_PV0_E                                = 293  ,
+  WIFIWHO_WMAC_HEADER_PV1_E                                = 294  ,
+  WIFIWHO_WMAC_IV_E                                        = 295  ,
+  WIFIMPDU_INFO_END_E                                      = 296  ,
+  WIFIMPDU_INFO_BITMAP_E                                   = 297  ,
+  WIFITX_QUEUE_EXTENSION_E                                 = 298  ,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E                  = 299  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E                    = 300  ,
+  WIFITQM_ACKED_MPDU_STATUS_E                              = 301  ,
+  WIFITQM_ADD_MSDU_STATUS_E                                = 302  ,
+  WIFITQM_LIST_GEN_DONE_E                                  = 303  ,
+  WIFIWHO_TERMINATE_E                                      = 304  ,
+  WIFITX_LAST_MPDU_END_E                                   = 305  ,
+  WIFITX_CV_DATA_E                                         = 306  ,
+  WIFIPPDU_TX_END_E                                        = 307  ,
+  WIFIPROT_TX_END_E                                        = 308  ,
+  WIFIMPDU_INFO_GLOBAL_END_E                               = 309  ,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E                           = 310  ,
+  WIFIRX_PPDU_END_USER_STATS_E                             = 311  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E                         = 312  ,
+  WIFIREO_GET_QUEUE_STATS_E                                = 313  ,
+  WIFIREO_FLUSH_QUEUE_E                                    = 314  ,
+  WIFIREO_FLUSH_CACHE_E                                    = 315  ,
+  WIFIREO_UNBLOCK_CACHE_E                                  = 316  ,
+  WIFIREO_GET_QUEUE_STATS_STATUS_E                         = 317  ,
+  WIFIREO_FLUSH_QUEUE_STATUS_E                             = 318  ,
+  WIFIREO_FLUSH_CACHE_STATUS_E                             = 319  ,
+  WIFIREO_UNBLOCK_CACHE_STATUS_E                           = 320  ,
+  WIFITQM_FLUSH_CACHE_E                                    = 321  ,
+  WIFITQM_UNBLOCK_CACHE_E                                  = 322  ,
+  WIFITQM_FLUSH_CACHE_STATUS_E                             = 323  ,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E                           = 324  ,
+  WIFIRX_PPDU_END_STATUS_DONE_E                            = 325  ,
+  WIFIRX_STATUS_BUFFER_DONE_E                              = 326  ,
+  WIFISCHEDULER_MLO_SW_MSG_STATUS_E                        = 327  ,
+  WIFISCHEDULER_TXOP_DURATION_TRIGGER_E                    = 328  ,
+  WIFITX_DATA_SYNC_E                                       = 329  ,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E                         = 330  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_E                             = 331  ,
+  WIFITQM_SYNC_CMD_E                                       = 332  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E                      = 333  ,
+  WIFITQM_SYNC_CMD_STATUS_E                                = 334  ,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E             = 335  ,
+  WIFITCC_TQM_WRAPPER_CMD_E                                = 336  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_E                             = 337  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E                      = 338  ,
+  WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E            = 339  ,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E          = 340  ,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E                           = 341  ,
+  WIFIRX_PPDU_START_USER_INFO_E                            = 342  ,
+  WIFIRX_RING_MASK_E                                       = 343  ,
+  WIFICOEX_MAC_NAP_E                                       = 344  ,
+  WIFIRXPCU_PPDU_END_INFO_E                                = 345  ,
+  WIFIWHO_MESH_CONTROL_E                                   = 346  ,
+  WIFIPDG_SW_MODE_BW_START_E                               = 347  ,
+  WIFIPDG_SW_MODE_BW_END_E                                 = 348  ,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E                           = 349  ,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E                           = 350  ,
+  WIFISCHEDULER_END_E                                      = 351  ,
+  WIFIRX_PPDU_START_DROPPED_E                              = 352  ,
+  WIFIRX_PPDU_END_DROPPED_E                                = 353  ,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E                    = 354  ,
+  WIFIRX_MPDU_START_DROPPED_E                              = 355  ,
+  WIFIRX_MSDU_START_DROPPED_E                              = 356  ,
+  WIFIRX_MSDU_END_DROPPED_E                                = 357  ,
+  WIFIRX_MPDU_END_DROPPED_E                                = 358  ,
+  WIFIRX_ATTENTION_DROPPED_E                               = 359  ,
+  WIFITXPCU_USER_SETUP_E                                   = 360  ,
+  WIFIRXPCU_USER_SETUP_EXT_E                               = 361  ,
+  WIFICMD_PART_0_END_E                                     = 362  ,
+  WIFIMACTX_SYNTH_ON_E                                     = 363  ,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E                         = 364  ,
+  WIFITQM_MPDU_GLOBAL_START_E                              = 365  ,
+  WIFIEXAMPLE_TLV_32_E                                     = 366  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E                            = 367  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E                      = 368  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E                     = 369  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E               = 370  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_E                            = 371  ,
+  WIFITQM_2_SCH_MPDU_AVAILABLE_E                           = 372  ,
+  WIFIPDG_TRIG_RESPONSE_E                                  = 373  ,
+  WIFITRIGGER_RESPONSE_TX_DONE_E                           = 374  ,
+  WIFIABORT_FROM_PHYRX_DETAILS_E                           = 375  ,
+  WIFISCH_TQM_CMD_WRAPPER_E                                = 376  ,
+  WIFIMPDUS_AVAILABLE_E                                    = 377  ,
+  WIFIRECEIVED_RESPONSE_INFO_PART2_E                       = 378  ,
+  WIFIPHYRX_TX_START_TIMING_E                              = 379  ,
+  WIFITXPCU_PREAMBLE_DONE_E                                = 380  ,
+  WIFINDP_PREAMBLE_DONE_E                                  = 381  ,
+  WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E                       = 382  ,
+  WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E                      = 383  ,
+  WIFIMACTX_CLEAR_PREV_TX_INFO_E                           = 384  ,
+  WIFITX_PUNCTURE_SETUP_E                                  = 385  ,
+  WIFIR2R_STATUS_END_E                                     = 386  ,
+  WIFIMACTX_PREFETCH_CV_COMMON_E                           = 387  ,
+  WIFIEND_OF_FLUSH_MARKER_E                                = 388  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PUNC_E                        = 389  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E                    = 390  ,
+  WIFIRECEIVED_RESPONSE_USER_7_0_E                         = 391  ,
+  WIFIRECEIVED_RESPONSE_USER_15_8_E                        = 392  ,
+  WIFIRECEIVED_RESPONSE_USER_23_16_E                       = 393  ,
+  WIFIRECEIVED_RESPONSE_USER_31_24_E                       = 394  ,
+  WIFIRECEIVED_RESPONSE_USER_36_32_E                       = 395  ,
+  WIFITX_LOOPBACK_SETUP_E                                  = 396  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E                = 397  ,
+  WIFISCH_WAIT_INSTR_TX_PATH_E                             = 398  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E                    = 399  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E             = 400  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E               = 401  ,
+  WIFITX_WUR_DATA_E                                        = 402  ,
+  WIFIRX_PPDU_END_START_E                                  = 403  ,
+  WIFIRX_PPDU_END_MIDDLE_E                                 = 404  ,
+  WIFIRX_PPDU_END_LAST_E                                   = 405  ,
+  WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E                   = 406  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E              = 407  ,
+  WIFISRP_INFO_E                                           = 408  ,
+  WIFIOBSS_SR_INFO_E                                       = 409  ,
+  WIFISCHEDULER_SW_MSG_STATUS_E                            = 410  ,
+  WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E                  = 411  ,
+  WIFIRXPCU_SETUP_COMPLETE_E                               = 412  ,
+  WIFIMACTX_MCC_SWITCH_E                                   = 413  ,
+  WIFIMACTX_MCC_SWITCH_BACK_E                              = 414  ,
+  WIFIPHYTX_MCC_SWITCH_ACK_E                               = 415  ,
+  WIFIPHYTX_MCC_SWITCH_BACK_ACK_E                          = 416  ,
+  WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E                         = 417  ,
+  WIFILMR_TX_END_E                                         = 418  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E            = 419  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E              = 420  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E              = 421  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E          = 422  ,
+  WIFISCH_TLV_WRAPPER_E                                    = 423  ,
+  WIFISCHEDULER_STATUS_WRAPPER_E                           = 424  ,
+  WIFIMPDU_INFO_6X_E                                       = 425  ,
+  WIFIMACTX___RESERVED_G_0013                              = 426  ,
+  WIFIMACTX_U_SIG_EHT_SU_MU_E                              = 427  ,
+  WIFIMACTX_U_SIG_EHT_TB_E                                 = 428  ,
+  WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E                          = 429  ,
+  WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E                          = 430  ,
+  WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E                          = 431  ,
+  WIFIPHYRX_U_SIG_EHT_SU_MU_E                              = 432  ,
+  WIFIPHYRX_U_SIG_EHT_TB_E                                 = 433  ,
+  WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E                          = 434  ,
+  WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                      = 435  ,
+  WIFITX_PUNCTURE_6PATTERNS_SETUP_E                        = 436  ,
+  WIFIMACRX_LMR_READ_REQUEST_E                             = 437  ,
+  WIFIMACRX_LMR_DATA_REQUEST_E                             = 438  ,
+  WIFIPHYRX_LMR_TRANSFER_DONE_E                            = 439  ,
+  WIFIPHYRX_LMR_TRANSFER_ABORT_E                           = 440  ,
+  WIFIPHYRX_LMR_READ_REQUEST_ACK_E                         = 441  ,
+  WIFIMACRX_SECURE_LTF_SEQ_PTR_E                           = 442  ,
+  WIFIPHYRX_USER_INFO_MU_UL_E                              = 443  ,
+  WIFIMPDU_QUEUE_OVERVIEW_E                                = 444  ,
+  WIFISCHEDULER_NAV_INFO_E                                 = 445  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E                = 446  ,
+  WIFILMR_PEER_ENTRY_E                                     = 447  ,
+  WIFILMR_MPDU_START_E                                     = 448  ,
+  WIFILMR_DATA_E                                           = 449  ,
+  WIFILMR_MPDU_END_E                                       = 450  ,
+  WIFIREO_GET_QUEUE_1K_STATS_STATUS_E                      = 451  ,
+  WIFIRX_FRAME_1K_BITMAP_ACK_E                             = 452  ,
+  WIFITX_FES_STATUS_1K_BA_E                                = 453  ,
+  WIFITQM_ACKED_1K_MPDU_E                                  = 454  ,
+  WIFIMACRX_INBSS_OBSS_IND_E                               = 455  ,
+  WIFIPHYRX_LOCATION_E                                     = 456  ,
+  WIFIMLO_TX_NOTIFICATION_SU_E                             = 457  ,
+  WIFIMLO_TX_NOTIFICATION_MU_E                             = 458  ,
+  WIFIMLO_TX_REQ_SU_E                                      = 459  ,
+  WIFIMLO_TX_REQ_MU_E                                      = 460  ,
+  WIFIMLO_TX_RESP_E                                        = 461  ,
+  WIFIMLO_RX_NOTIFICATION_E                                = 462  ,
+  WIFIMLO_BKOFF_TRUNC_REQ_E                                = 463  ,
+  WIFIMLO_TBTT_NOTIFICATION_E                              = 464  ,
+  WIFIMLO_MESSAGE_E                                        = 465  ,
+  WIFIMLO_TS_SYNC_MSG_E                                    = 466  ,
+  WIFIMLO_FES_SETUP_E                                      = 467  ,
+  WIFIMLO_PDG_FES_SETUP_SU_E                               = 468  ,
+  WIFIMLO_PDG_FES_SETUP_MU_E                               = 469  ,
+  WIFIMPDU_INFO_1K_BITMAP_E                                = 470  ,
+  WIFIMON_BUFFER_ADDR_E                                    = 471  ,
+  WIFITX_FRAG_STATE_E                                      = 472  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E             = 473  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E              = 474  ,
+  WIFIMACTX_EHT_SIG_USR_OFDMA_E                            = 475  ,
+  WIFIMACTX_U_SIG_UHR_SU_MU_E                              = 476  ,
+  WIFIMACTX_U_SIG_UHR_TB_E                                 = 477  ,
+  WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E                     = 478  ,
+  WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E                     = 479  ,
+  WIFITX_MSDU_COMPONENT_DETAILS_TLV_E                      = 480  ,
+  WIFIPHYRX_EHT_SIG_USR_OFDMA_E                            = 481  ,
+  WIFISCHEDULER_IU_TEMPLATE_ID_E                           = 482  ,
+  WIFIPHYRX_PKT_END_PART1_E                                = 483  ,
+  WIFIMACTX_EXPECT_NDP_RECEPTION_E                         = 484  ,
+  WIFIMACTX_SECURE_LTF_SEQ_PTR_E                           = 485  ,
+  WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E                    = 486  ,
+  WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E                         = 487  ,
+  WIFIPHYRX___RESERVED_G_0014                              = 488  ,
+  WIFIPHYTX_LOCATION_E                                     = 489  ,
+  WIFIPHYTX___RESERVED_G_0014                              = 490  ,
+  WIFIMPDU_LENGTH_STRUCTS_START_E                          = 491  ,
+  WIFIMACTX_EHT_SIG_USR_SU_E                               = 492  ,
+  WIFIMACTX_EHT_SIG_USR_MU_MIMO_E                          = 493  ,
+  WIFIPHYRX_EHT_SIG_USR_SU_E                               = 494  ,
+  WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E                          = 495  ,
+  WIFIPHYRX_GENERIC_U_SIG_E                                = 496  ,
+  WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E                       = 497  ,
+  WIFIOVERWRITE_RESP_START_E                               = 498  ,
+  WIFIOVERWRITE_RESP_PREAMBLE_INFO_E                       = 499  ,
+  WIFIOVERWRITE_RESP_FRAME_INFO_E                          = 500  ,
+  WIFIOVERWRITE_RESP_END_E                                 = 501  ,
+  WIFIRXPCU_EARLY_RX_INDICATION_E                          = 502  ,
+  WIFIMON_DROP_E                                           = 503  ,
+  WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E                       = 504  ,
+  WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E                   = 505  ,
+  WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E                     = 506  ,
+  WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E                   = 507  ,
+  WIFIMACTX_PREFETCH_CV_DMA_E                              = 508  ,
+  WIFIMACTX_PREFETCH_CV_PER_USER_E                         = 509  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E          = 510  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E                      = 511  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E                    = 512  ,
+  WIFIRANGING_USER_DETAILS_E                               = 513  ,
+  WIFIPHYTX_CV_CORR_STATUS_E                               = 514  ,
+  WIFIPHYTX_CV_CORR_COMMON_E                               = 515  ,
+  WIFIPHYTX_CV_CORR_USER_E                                 = 516  ,
+  WIFIMACTX_CV_CORR_COMMON_E                               = 517  ,
+  WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E                       = 518  ,
+  WIFIBW_PUNCTURE_EVAL_WRAPPER_E                           = 519  ,
+  WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E                      = 520  ,
+  WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E                      = 521  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E                      = 522  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E                  = 523  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT2_E                        = 524  ,
+  WIFIFW2SW_MON_E                                          = 525  ,
+  WIFIWSI_DIRECT_MESSAGE_E                                 = 526  ,
+  WIFIMACTX_EMLSR_PRE_SWITCH_E                             = 527  ,
+  WIFIMACTX_EMLSR_SWITCH_E                                 = 528  ,
+  WIFIMACTX_EMLSR_SWITCH_BACK_E                            = 529  ,
+  WIFIPHYTX_EMLSR_SWITCH_ACK_E                             = 530  ,
+  WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E                        = 531  ,
+  WIFIEAD_COMMAND_E                                        = 532  ,
+  WIFIEAD_LEGACY_STATUS_CONTROL_E                          = 533  ,
+  WIFIEAD_LEGACY_INTERRUPT_CONTROL_E                       = 534  ,
+  WIFITPI_TX_INITIALIZATION_CONFIG_E                       = 535  ,
+  WIFITPI_ENABLE_RESPONSE_TIMEOUT_E                        = 536  ,
+  WIFITPI_LEGACY_STATUS_CONTROL_E                          = 537  ,
+  WIFITPI_LEGACY_INTERRUPT_CONTROL_E                       = 538  ,
+  WIFITPI_MPDU_START_E                                     = 539  ,
+  WIFITPI_MPDU_CONTINUATION_E                              = 540  ,
+  WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E               = 541  ,
+  WIFITPI_SEND_TLV_TO_PHYTX_E                              = 542  ,
+  WIFITPI_TX_START_TIME_ARRIVED_E                          = 543  ,
+  WIFITPI_STATUS_E                                         = 544  ,
+  WIFITPI_ERROR_STATUS_E                                   = 545  ,
+  WIFITPI_TIMESTAMP_STATUS_E                               = 546  ,
+  WIFIRPI_SEND_TLV_TO_PHYRX_E                              = 547  ,
+  WIFIRPI_LEGACY_STATUS_CONTROL_E                          = 548  ,
+  WIFIRPI_LEGACY_INTERRUPT_CONTROL_E                       = 549  ,
+  WIFIRPI_STATUS_E                                         = 550  ,
+  WIFIRPI_ERROR_STATUS_E                                   = 551  ,
+  WIFIRPI_TIMESTAMP_STATUS_E                               = 552  ,
+  WIFIRPI_RX_FRAME_UPDATE_STATUS_E                         = 553  ,
+  WIFITCC_PUSH_TRANSMIT_COMMAND_E                          = 554  ,
+  WIFITCC_TLV_FETCH_E                                      = 555  ,
+  WIFITCC_LEGACY_STATUS_CONTROL_E                          = 556  ,
+  WIFITCC_LEGACY_INTERRUPT_CONTROL_E                       = 557  ,
+  WIFITCC_STATUS_E                                         = 558  ,
+  WIFITCC_ERROR_STATUS_E                                   = 559  ,
+  WIFITCC_TIMESTAMP_STATUS_E                               = 560  ,
+  WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E                      = 561  ,
+  WIFITCC_SCHEDULER_CMD_E                                  = 562  ,
+  WIFITCC_BURST_CMD_AVAILABLE_E                            = 563  ,
+  WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E                    = 564  ,
+  WIFIEAD_RING_AIR_TIME_REFERENCE_E                        = 565  ,
+  WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E                        = 566  ,
+  WIFIRPI_WRITE_INFO_TO_EXT_MEM_E                          = 567  ,
+  WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E                        = 568  ,
+  WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E                        = 569  ,
+  WIFITPI_SEND_CBF_DATA_TO_PHYTX_E                         = 570  ,
+  WIFITPI_SEND_CTLV_44_TO_PHYTX_E                          = 571  ,
+  WIFITCC_FES_END_MESSAGE_E                                = 572  ,
+  WIFITPI_TX_FRAME_UPDATE_STATUS_E                         = 573  ,
+  WIFITPI_DISABLE_RESPONSE_TIMEOUT_E                       = 574  ,
+  WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E                   = 575  ,
+  WIFIEAD_MSDU_STATUS_START_E                              = 576  ,
+  WIFIEAD_MSDU_STATUS_DETAILS_E                            = 577  ,
+  WIFIMACTX_UHR_SIG_USR_SU_E                               = 578  ,
+  WIFIMACTX_UHR_SIG_USR_MU_MIMO_E                          = 579  ,
+  WIFIMACTX_UHR_SIG_USR_OFDMA_E                            = 580  ,
+  WIFIMACTX_ELR_SIG_UHR_SU_E                               = 581  ,
+  WIFICOEX_BLACKOUT_DETAILS_E                              = 582  ,
+  WIFIPEER_BLACKOUT_DETAILS_E                              = 583  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E             = 584  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_E                           = 585  ,
+  WIFIHDR_CTRL_PROT_MPDU_START_E                           = 586  ,
+  WIFIHDR_CTRL_PROT_DATA_E                                 = 587  ,
+  WIFIHDR_CTRL_PROT_MPDU_END_E                             = 588  ,
+  WIFIHDR_CTRL_PROT_MIC_STATUS_E                           = 589  ,
+  WIFIHDR_CTRL_PROT_PEER_INFO_E                            = 590  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E                      = 591  ,
+  WIFIMACTX_U_SIG_UHR_ELR_SU_E                             = 592  ,
+  WIFIMACTX_U_SIG_UHR_COBF_E                               = 593  ,
+  WIFIMACTX_UHR_SIG_USR_COBF_E                             = 594  ,
+  WIFISPARE_REUSE_TAG_0_E                                  = 595  ,
+  WIFISPARE_REUSE_TAG_1_E                                  = 596  ,
+  WIFISPARE_REUSE_TAG_2_E                                  = 597  ,
+  WIFISPARE_REUSE_TAG_3_E                                  = 598  ,
+  WIFISPARE_REUSE_TAG_4_E                                  = 599  ,
+  WIFISPARE_REUSE_TAG_5_E                                  = 600  ,
+  WIFISPARE_REUSE_TAG_6_E                                  = 601  ,
+  WIFISPARE_REUSE_TAG_7_E                                  = 602  ,
+  WIFISPARE_REUSE_TAG_8_E                                  = 603  ,
+  WIFISPARE_REUSE_TAG_9_E                                  = 604  ,
+  WIFISPARE_REUSE_TAG_10_E                                 = 605  ,
+  WIFISPARE_REUSE_TAG_11_E                                 = 606  ,
+  WIFISPARE_REUSE_TAG_12_E                                 = 607  ,
+  WIFISPARE_REUSE_TAG_13_E                                 = 608  ,
+  WIFISPARE_REUSE_TAG_14_E                                 = 609  ,
+  WIFISPARE_REUSE_TAG_15_E                                 = 610  ,
+  WIFISPARE_REUSE_TAG_16_E                                 = 611  ,
+  WIFISPARE_REUSE_TAG_17_E                                 = 612  ,
+  WIFISPARE_REUSE_TAG_18_E                                 = 613  ,
+  WIFISPARE_REUSE_TAG_19_E                                 = 614  ,
+  WIFISPARE_REUSE_TAG_20_E                                 = 615  ,
+  WIFISPARE_REUSE_TAG_21_E                                 = 616  ,
+  WIFISPARE_REUSE_TAG_22_E                                 = 617  ,
+  WIFISPARE_REUSE_TAG_23_E                                 = 618  ,
+  WIFISPARE_REUSE_TAG_24_E                                 = 619  ,
+  WIFISPARE_REUSE_TAG_25_E                                 = 620  ,
+  WIFISPARE_REUSE_TAG_26_E                                 = 621  ,
+  WIFISPARE_REUSE_TAG_27_E                                 = 622  ,
+  WIFISPARE_REUSE_TAG_28_E                                 = 623  ,
+  WIFISPARE_REUSE_TAG_29_E                                 = 624  ,
+  WIFISPARE_REUSE_TAG_30_E                                 = 625  ,
+  WIFISPARE_REUSE_TAG_31_E                                 = 626  ,
+  WIFISPARE_REUSE_TAG_32_E                                 = 627  ,
+  WIFISPARE_REUSE_TAG_33_E                                 = 628  ,
+  WIFISPARE_REUSE_TAG_34_E                                 = 629  ,
+  WIFISPARE_REUSE_TAG_35_E                                 = 630  ,
+  WIFISPARE_REUSE_TAG_36_E                                 = 631  ,
+  WIFISPARE_REUSE_TAG_37_E                                 = 632  ,
+  WIFISPARE_REUSE_TAG_38_E                                 = 633  ,
+  WIFISPARE_REUSE_TAG_39_E                                 = 634  ,
+  WIFISPARE_REUSE_TAG_40_E                                 = 635  ,
+  WIFISPARE_REUSE_TAG_41_E                                 = 636  ,
+  WIFISPARE_REUSE_TAG_42_E                                 = 637  ,
+  WIFISPARE_REUSE_TAG_43_E                                 = 638  ,
+  WIFISPARE_REUSE_TAG_44_E                                 = 639  ,
+  WIFISPARE_REUSE_TAG_45_E                                 = 640  ,
+  WIFISPARE_REUSE_TAG_46_E                                 = 641  ,
+  WIFISPARE_REUSE_TAG_47_E                                 = 642  ,
+  WIFISPARE_REUSE_TAG_48_E                                 = 643  ,
+  WIFISPARE_REUSE_TAG_49_E                                 = 644  ,
+  WIFISPARE_REUSE_TAG_50_E                                 = 645  ,
+  WIFISPARE_REUSE_TAG_51_E                                 = 646  ,
+  WIFISPARE_REUSE_TAG_52_E                                 = 647  ,
+  WIFISPARE_REUSE_TAG_53_E                                 = 648  ,
+  WIFISPARE_REUSE_TAG_54_E                                 = 649  ,
+  WIFISPARE_REUSE_TAG_55_E                                 = 650  ,
+  WIFISPARE_REUSE_TAG_56_E                                 = 651  ,
+  WIFISPARE_REUSE_TAG_57_E                                 = 652  ,
+  WIFISPARE_REUSE_TAG_58_E                                 = 653  ,
+  WIFISPARE_REUSE_TAG_59_E                                 = 654  ,
+  WIFISPARE_REUSE_TAG_60_E                                 = 655  ,
+  WIFISPARE_REUSE_TAG_61_E                                 = 656  ,
+  WIFISPARE_REUSE_TAG_62_E                                 = 657  ,
+  WIFISPARE_REUSE_TAG_63_E                                 = 658  ,
+  WIFISPARE_REUSE_TAG_64_E                                 = 659  ,
+  WIFISPARE_REUSE_TAG_65_E                                 = 660  ,
+  WIFISPARE_REUSE_TAG_66_E                                 = 661  ,
+  WIFISPARE_REUSE_TAG_67_E                                 = 662  ,
+  WIFISPARE_REUSE_TAG_68_E                                 = 663  ,
+  WIFISPARE_REUSE_TAG_69_E                                 = 664  ,
+  WIFISPARE_REUSE_TAG_70_E                                 = 665  ,
+  WIFISPARE_REUSE_TAG_71_E                                 = 666  ,
+  WIFISPARE_REUSE_TAG_72_E                                 = 667  ,
+  WIFISPARE_REUSE_TAG_73_E                                 = 668  ,
+  WIFISPARE_REUSE_TAG_74_E                                 = 669  ,
+  WIFISPARE_REUSE_TAG_75_E                                 = 670  ,
+  WIFISPARE_REUSE_TAG_76_E                                 = 671  ,
+  WIFISPARE_REUSE_TAG_77_E                                 = 672  ,
+  WIFISPARE_REUSE_TAG_78_E                                 = 673  ,
+  WIFISPARE_REUSE_TAG_79_E                                 = 674  ,
+  WIFISPARE_REUSE_TAG_80_E                                 = 675  ,
+  WIFISPARE_REUSE_TAG_81_E                                 = 676  ,
+  WIFISPARE_REUSE_TAG_82_E                                 = 677  ,
+  WIFISPARE_REUSE_TAG_83_E                                 = 678  ,
+  WIFISPARE_REUSE_TAG_84_E                                 = 679  ,
+  WIFISPARE_REUSE_TAG_85_E                                 = 680  ,
+  WIFISPARE_REUSE_TAG_86_E                                 = 681  ,
+  WIFISPARE_REUSE_TAG_87_E                                 = 682  ,
+  WIFISPARE_REUSE_TAG_88_E                                 = 683  ,
+  WIFISPARE_REUSE_TAG_89_E                                 = 684  ,
+  WIFISPARE_REUSE_TAG_90_E                                 = 685  ,
+  WIFISPARE_REUSE_TAG_91_E                                 = 686  ,
+  WIFISPARE_REUSE_TAG_92_E                                 = 687  ,
+  WIFISPARE_REUSE_TAG_93_E                                 = 688  ,
+  WIFISPARE_REUSE_TAG_94_E                                 = 689  ,
+  WIFISPARE_REUSE_TAG_95_E                                 = 690  ,
+  WIFISPARE_REUSE_TAG_96_E                                 = 691  ,
+  WIFISPARE_REUSE_TAG_97_E                                 = 692  ,
+  WIFISPARE_REUSE_TAG_98_E                                 = 693  ,
+  WIFISPARE_REUSE_TAG_99_E                                 = 694  ,
+  WIFISPARE_REUSE_TAG_100_E                                = 695  ,
+  WIFISPARE_REUSE_TAG_101_E                                = 696  ,
+  WIFISPARE_REUSE_TAG_102_E                                = 697  ,
+  WIFISPARE_REUSE_TAG_103_E                                = 698  ,
+  WIFISPARE_REUSE_TAG_104_E                                = 699  ,
+  WIFISPARE_REUSE_TAG_105_E                                = 700  ,
+  WIFISPARE_REUSE_TAG_106_E                                = 701  ,
+  WIFISPARE_REUSE_TAG_107_E                                = 702  ,
+  WIFISPARE_REUSE_TAG_108_E                                = 703  ,
+  WIFISPARE_REUSE_TAG_109_E                                = 704  ,
+  WIFISPARE_REUSE_TAG_110_E                                = 705  ,
+  WIFISPARE_REUSE_TAG_111_E                                = 706  ,
+  WIFISPARE_REUSE_TAG_112_E                                = 707  ,
+  WIFISPARE_REUSE_TAG_113_E                                = 708  ,
+  WIFISPARE_REUSE_TAG_114_E                                = 709  ,
+  WIFISPARE_REUSE_TAG_115_E                                = 710  ,
+  WIFISPARE_REUSE_TAG_116_E                                = 711  ,
+  WIFISPARE_REUSE_TAG_117_E                                = 712  ,
+  WIFISPARE_REUSE_TAG_118_E                                = 713  ,
+  WIFISPARE_REUSE_TAG_119_E                                = 714  ,
+  WIFISPARE_REUSE_TAG_120_E                                = 715  ,
+  WIFISPARE_REUSE_TAG_121_E                                = 716  ,
+  WIFISPARE_REUSE_TAG_122_E                                = 717  ,
+  WIFISPARE_REUSE_TAG_123_E                                = 718  ,
+  WIFISPARE_REUSE_TAG_124_E                                = 719  ,
+  WIFISPARE_REUSE_TAG_125_E                                = 720  ,
+  WIFISPARE_REUSE_TAG_126_E                                = 721  ,
+  WIFISPARE_REUSE_TAG_127_E                                = 722  ,
+  WIFISPARE_REUSE_TAG_128_E                                = 723  ,
+  WIFISPARE_REUSE_TAG_129_E                                = 724  ,
+  WIFISPARE_REUSE_TAG_130_E                                = 725  ,
+  WIFISPARE_REUSE_TAG_131_E                                = 726  ,
+  WIFISPARE_REUSE_TAG_132_E                                = 727  ,
+  WIFISPARE_REUSE_TAG_133_E                                = 728  ,
+  WIFISPARE_REUSE_TAG_134_E                                = 729  ,
+  WIFISPARE_REUSE_TAG_135_E                                = 730  ,
+  WIFISPARE_REUSE_TAG_136_E                                = 731  ,
+  WIFISPARE_REUSE_TAG_137_E                                = 732  ,
+  WIFISPARE_REUSE_TAG_138_E                                = 733  ,
+  WIFISPARE_REUSE_TAG_139_E                                = 734  ,
+  WIFISPARE_REUSE_TAG_140_E                                = 735  ,
+  WIFISPARE_REUSE_TAG_141_E                                = 736  ,
+  WIFISPARE_REUSE_TAG_142_E                                = 737  ,
+  WIFISPARE_REUSE_TAG_143_E                                = 738  ,
+  WIFISPARE_REUSE_TAG_144_E                                = 739  ,
+  WIFISPARE_REUSE_TAG_145_E                                = 740  ,
+  WIFISPARE_REUSE_TAG_146_E                                = 741  ,
+  WIFISPARE_REUSE_TAG_147_E                                = 742  ,
+  WIFISPARE_REUSE_TAG_148_E                                = 743  ,
+  WIFISPARE_REUSE_TAG_149_E                                = 744  ,
+  WIFISPARE_REUSE_TAG_150_E                                = 745  ,
+  WIFISPARE_REUSE_TAG_151_E                                = 746  ,
+  WIFISPARE_REUSE_TAG_152_E                                = 747  ,
+  WIFISPARE_REUSE_TAG_153_E                                = 748  ,
+  WIFISPARE_REUSE_TAG_154_E                                = 749  ,
+  WIFISPARE_REUSE_TAG_155_E                                = 750  ,
+  WIFISPARE_REUSE_TAG_156_E                                = 751  ,
+  WIFISPARE_REUSE_TAG_157_E                                = 752  ,
+  WIFISPARE_REUSE_TAG_158_E                                = 753  ,
+  WIFISPARE_REUSE_TAG_159_E                                = 754  ,
+  WIFISPARE_REUSE_TAG_160_E                                = 755  ,
+  WIFISPARE_REUSE_TAG_161_E                                = 756  ,
+  WIFISPARE_REUSE_TAG_162_E                                = 757  ,
+  WIFISPARE_REUSE_TAG_163_E                                = 758  ,
+  WIFISPARE_REUSE_TAG_164_E                                = 759  ,
+  WIFISPARE_REUSE_TAG_165_E                                = 760  ,
+  WIFISPARE_REUSE_TAG_166_E                                = 761  ,
+  WIFISPARE_REUSE_TAG_167_E                                = 762  ,
+  WIFISPARE_REUSE_TAG_168_E                                = 763  ,
+  WIFISPARE_REUSE_TAG_169_E                                = 764  ,
+  WIFISPARE_REUSE_TAG_170_E                                = 765  ,
+  WIFISPARE_REUSE_TAG_171_E                                = 766  ,
+  WIFISPARE_REUSE_TAG_172_E                                = 767  ,
+  WIFISPARE_REUSE_TAG_173_E                                = 768  ,
+  WIFISPARE_REUSE_TAG_174_E                                = 769  ,
+  WIFISPARE_REUSE_TAG_175_E                                = 770  ,
+  WIFISPARE_REUSE_TAG_176_E                                = 771  ,
+  WIFISPARE_REUSE_TAG_177_E                                = 772  ,
+  WIFISPARE_REUSE_TAG_178_E                                = 773  ,
+  WIFISPARE_REUSE_TAG_179_E                                = 774  ,
+  WIFISPARE_REUSE_TAG_180_E                                = 775  ,
+  WIFISPARE_REUSE_TAG_181_E                                = 776  ,
+  WIFISPARE_REUSE_TAG_182_E                                = 777  ,
+  WIFISPARE_REUSE_TAG_183_E                                = 778  ,
+  WIFISPARE_REUSE_TAG_184_E                                = 779  ,
+  WIFISPARE_REUSE_TAG_185_E                                = 780  ,
+  WIFISPARE_REUSE_TAG_186_E                                = 781  ,
+  WIFISPARE_REUSE_TAG_187_E                                = 782  ,
+  WIFISPARE_REUSE_TAG_188_E                                = 783  ,
+  WIFISPARE_REUSE_TAG_189_E                                = 784  ,
+  WIFISPARE_REUSE_TAG_190_E                                = 785  ,
+  WIFISPARE_REUSE_TAG_191_E                                = 786  ,
+  WIFISPARE_REUSE_TAG_192_E                                = 787  ,
+  WIFISPARE_REUSE_TAG_193_E                                = 788  ,
+  WIFISPARE_REUSE_TAG_194_E                                = 789  ,
+  WIFISPARE_REUSE_TAG_195_E                                = 790  ,
+  WIFISPARE_REUSE_TAG_196_E                                = 791  ,
+  WIFISPARE_REUSE_TAG_197_E                                = 792  ,
+  WIFISPARE_REUSE_TAG_198_E                                = 793  ,
+  WIFISPARE_REUSE_TAG_199_E                                = 794  ,
+  WIFISPARE_REUSE_TAG_200_E                                = 795  ,
+  WIFISPARE_REUSE_TAG_201_E                                = 796  ,
+  WIFISPARE_REUSE_TAG_202_E                                = 797  ,
+  WIFISPARE_REUSE_TAG_203_E                                = 798  ,
+  WIFISPARE_REUSE_TAG_204_E                                = 799  ,
+  WIFISPARE_REUSE_TAG_205_E                                = 800  ,
+  WIFISPARE_REUSE_TAG_206_E                                = 801  ,
+  WIFISPARE_REUSE_TAG_207_E                                = 802  ,
+  WIFISPARE_REUSE_TAG_208_E                                = 803  ,
+  WIFISPARE_REUSE_TAG_209_E                                = 804  ,
+  WIFISPARE_REUSE_TAG_210_E                                = 805  ,
+  WIFISPARE_REUSE_TAG_211_E                                = 806  ,
+  WIFISPARE_REUSE_TAG_212_E                                = 807  ,
+  WIFISPARE_REUSE_TAG_213_E                                = 808  ,
+  WIFISPARE_REUSE_TAG_214_E                                = 809  ,
+  WIFISPARE_REUSE_TAG_215_E                                = 810  ,
+  WIFISPARE_REUSE_TAG_216_E                                = 811  ,
+  WIFISPARE_REUSE_TAG_217_E                                = 812  ,
+  WIFISPARE_REUSE_TAG_218_E                                = 813  ,
+  WIFISPARE_REUSE_TAG_219_E                                = 814  ,
+  WIFISPARE_REUSE_TAG_220_E                                = 815  ,
+  WIFISPARE_REUSE_TAG_221_E                                = 816  ,
+  WIFISPARE_REUSE_TAG_222_E                                = 817  ,
+  WIFISPARE_REUSE_TAG_223_E                                = 818  ,
+  WIFISPARE_REUSE_TAG_224_E                                = 819  ,
+  WIFISPARE_REUSE_TAG_225_E                                = 820  ,
+  WIFISPARE_REUSE_TAG_226_E                                = 821  ,
+  WIFISPARE_REUSE_TAG_227_E                                = 822  ,
+  WIFISPARE_REUSE_TAG_228_E                                = 823  ,
+  WIFISPARE_REUSE_TAG_229_E                                = 824  ,
+  WIFISPARE_REUSE_TAG_230_E                                = 825  ,
+  WIFISPARE_REUSE_TAG_231_E                                = 826  ,
+  WIFISPARE_REUSE_TAG_232_E                                = 827  ,
+  WIFISPARE_REUSE_TAG_233_E                                = 828  ,
+  WIFISPARE_REUSE_TAG_234_E                                = 829  ,
+  WIFISPARE_REUSE_TAG_235_E                                = 830  ,
+  WIFISPARE_REUSE_TAG_236_E                                = 831  ,
+  WIFISPARE_REUSE_TAG_237_E                                = 832  ,
+  WIFISPARE_REUSE_TAG_238_E                                = 833  ,
+  WIFISPARE_REUSE_TAG_239_E                                = 834  ,
+  WIFISPARE_REUSE_TAG_240_E                                = 835  ,
+  WIFISPARE_REUSE_TAG_241_E                                = 836  ,
+  WIFISPARE_REUSE_TAG_242_E                                = 837  ,
+  WIFISPARE_REUSE_TAG_243_E                                = 838  ,
+  WIFISPARE_REUSE_TAG_244_E                                = 839  ,
+  WIFISPARE_REUSE_TAG_245_E                                = 840  ,
+  WIFISPARE_REUSE_TAG_246_E                                = 841  ,
+  WIFISPARE_REUSE_TAG_247_E                                = 842  ,
+  WIFISPARE_REUSE_TAG_248_E                                = 843  ,
+  WIFISPARE_REUSE_TAG_249_E                                = 844  ,
+  WIFISPARE_REUSE_TAG_250_E                                = 845  ,
+  WIFISPARE_REUSE_TAG_251_E                                = 846  ,
+  WIFISPARE_REUSE_TAG_252_E                                = 847  ,
+  WIFISPARE_REUSE_TAG_253_E                                = 848  ,
+  WIFISPARE_REUSE_TAG_254_E                                = 849  ,
+  WIFISPARE_REUSE_TAG_255_E                                = 850  ,
+  WIFISPARE_REUSE_TAG_256_E                                = 851  ,
+  WIFISPARE_REUSE_TAG_257_E                                = 852  ,
+  WIFISPARE_REUSE_TAG_258_E                                = 853  ,
+  WIFISPARE_REUSE_TAG_259_E                                = 854  ,
+  WIFISPARE_REUSE_TAG_260_E                                = 855  ,
+  WIFISPARE_REUSE_TAG_261_E                                = 856  ,
+  WIFISPARE_REUSE_TAG_262_E                                = 857  ,
+  WIFISPARE_REUSE_TAG_263_E                                = 858  ,
+  WIFISPARE_REUSE_TAG_264_E                                = 859  ,
+  WIFISPARE_REUSE_TAG_265_E                                = 860  ,
+  WIFISPARE_REUSE_TAG_266_E                                = 861  ,
+  WIFISPARE_REUSE_TAG_267_E                                = 862  ,
+  WIFISPARE_REUSE_TAG_268_E                                = 863  ,
+  WIFISPARE_REUSE_TAG_269_E                                = 864  ,
+  WIFISPARE_REUSE_TAG_270_E                                = 865  ,
+  WIFISPARE_REUSE_TAG_271_E                                = 866  ,
+  WIFISPARE_REUSE_TAG_272_E                                = 867  ,
+  WIFISPARE_REUSE_TAG_273_E                                = 868  ,
+  WIFISPARE_REUSE_TAG_274_E                                = 869  ,
+  WIFISPARE_REUSE_TAG_275_E                                = 870  ,
+  WIFISPARE_REUSE_TAG_276_E                                = 871  ,
+  WIFISPARE_REUSE_TAG_277_E                                = 872  ,
+  WIFISPARE_REUSE_TAG_278_E                                = 873  ,
+  WIFISPARE_REUSE_TAG_279_E                                = 874  ,
+  WIFISPARE_REUSE_TAG_280_E                                = 875  ,
+  WIFISPARE_REUSE_TAG_281_E                                = 876  ,
+  WIFISPARE_REUSE_TAG_282_E                                = 877  ,
+  WIFISPARE_REUSE_TAG_283_E                                = 878  ,
+  WIFISPARE_REUSE_TAG_284_E                                = 879  ,
+  WIFISPARE_REUSE_TAG_285_E                                = 880  ,
+  WIFISPARE_REUSE_TAG_286_E                                = 881  ,
+  WIFISPARE_REUSE_TAG_287_E                                = 882  ,
+  WIFISPARE_REUSE_TAG_288_E                                = 883  ,
+  WIFISPARE_REUSE_TAG_289_E                                = 884  ,
+  WIFISPARE_REUSE_TAG_290_E                                = 885  ,
+  WIFISPARE_REUSE_TAG_291_E                                = 886  ,
+  WIFISPARE_REUSE_TAG_292_E                                = 887  ,
+  WIFISPARE_REUSE_TAG_293_E                                = 888  ,
+  WIFISPARE_REUSE_TAG_294_E                                = 889  ,
+  WIFISPARE_REUSE_TAG_295_E                                = 890  ,
+  WIFISPARE_REUSE_TAG_296_E                                = 891  ,
+  WIFISPARE_REUSE_TAG_297_E                                = 892  ,
+  WIFISPARE_REUSE_TAG_298_E                                = 893  ,
+  WIFISPARE_REUSE_TAG_299_E                                = 894  ,
+  WIFISPARE_REUSE_TAG_300_E                                = 895  ,
+  WIFISPARE_REUSE_TAG_301_E                                = 896  ,
+  WIFISPARE_REUSE_TAG_302_E                                = 897  ,
+  WIFISPARE_REUSE_TAG_303_E                                = 898  ,
+  WIFISPARE_REUSE_TAG_304_E                                = 899  ,
+  WIFISPARE_REUSE_TAG_305_E                                = 900  ,
+  WIFISPARE_REUSE_TAG_306_E                                = 901  ,
+  WIFISPARE_REUSE_TAG_307_E                                = 902  ,
+  WIFISPARE_REUSE_TAG_308_E                                = 903  ,
+  WIFISPARE_REUSE_TAG_309_E                                = 904  ,
+  WIFISPARE_REUSE_TAG_310_E                                = 905  ,
+  WIFISPARE_REUSE_TAG_311_E                                = 906  ,
+  WIFISPARE_REUSE_TAG_312_E                                = 907  ,
+  WIFISPARE_REUSE_TAG_313_E                                = 908  ,
+  WIFISPARE_REUSE_TAG_314_E                                = 909  ,
+  WIFISPARE_REUSE_TAG_315_E                                = 910  ,
+  WIFISPARE_REUSE_TAG_316_E                                = 911  ,
+  WIFISPARE_REUSE_TAG_317_E                                = 912  ,
+  WIFISPARE_REUSE_TAG_318_E                                = 913  ,
+  WIFISPARE_REUSE_TAG_319_E                                = 914  ,
+  WIFISPARE_REUSE_TAG_320_E                                = 915  ,
+  WIFISPARE_REUSE_TAG_321_E                                = 916  ,
+  WIFISPARE_REUSE_TAG_322_E                                = 917  ,
+  WIFISPARE_REUSE_TAG_323_E                                = 918  ,
+  WIFISPARE_REUSE_TAG_324_E                                = 919  ,
+  WIFISPARE_REUSE_TAG_325_E                                = 920  ,
+  WIFISPARE_REUSE_TAG_326_E                                = 921  ,
+  WIFISPARE_REUSE_TAG_327_E                                = 922  ,
+  WIFISPARE_REUSE_TAG_328_E                                = 923  ,
+  WIFISPARE_REUSE_TAG_329_E                                = 924  ,
+  WIFISPARE_REUSE_TAG_330_E                                = 925  ,
+  WIFISPARE_REUSE_TAG_331_E                                = 926  ,
+  WIFISPARE_REUSE_TAG_332_E                                = 927  ,
+  WIFISPARE_REUSE_TAG_333_E                                = 928  ,
+  WIFISPARE_REUSE_TAG_334_E                                = 929  ,
+  WIFISPARE_REUSE_TAG_335_E                                = 930  ,
+  WIFISPARE_REUSE_TAG_336_E                                = 931  ,
+  WIFISPARE_REUSE_TAG_337_E                                = 932  ,
+  WIFISPARE_REUSE_TAG_338_E                                = 933  ,
+  WIFISPARE_REUSE_TAG_339_E                                = 934  ,
+  WIFISPARE_REUSE_TAG_340_E                                = 935  ,
+  WIFISPARE_REUSE_TAG_341_E                                = 936  ,
+  WIFISPARE_REUSE_TAG_342_E                                = 937  ,
+  WIFISPARE_REUSE_TAG_343_E                                = 938  ,
+  WIFISPARE_REUSE_TAG_344_E                                = 939  ,
+  WIFISPARE_REUSE_TAG_345_E                                = 940  ,
+  WIFISPARE_REUSE_TAG_346_E                                = 941  ,
+  WIFISPARE_REUSE_TAG_347_E                                = 942  ,
+  WIFISPARE_REUSE_TAG_348_E                                = 943  ,
+  WIFISPARE_REUSE_TAG_349_E                                = 944  ,
+  WIFISPARE_REUSE_TAG_350_E                                = 945  ,
+  WIFISPARE_REUSE_TAG_351_E                                = 946  ,
+  WIFISPARE_REUSE_TAG_352_E                                = 947  ,
+  WIFISPARE_REUSE_TAG_353_E                                = 948  ,
+  WIFISPARE_REUSE_TAG_354_E                                = 949  ,
+  WIFISPARE_REUSE_TAG_355_E                                = 950  ,
+  WIFISPARE_REUSE_TAG_356_E                                = 951  ,
+  WIFISPARE_REUSE_TAG_357_E                                = 952  ,
+  WIFISPARE_REUSE_TAG_358_E                                = 953  ,
+  WIFISPARE_REUSE_TAG_359_E                                = 954  ,
+  WIFISPARE_REUSE_TAG_360_E                                = 955  ,
+  WIFISPARE_REUSE_TAG_361_E                                = 956  ,
+  WIFISPARE_REUSE_TAG_362_E                                = 957  ,
+  WIFISPARE_REUSE_TAG_363_E                                = 958  ,
+  WIFISPARE_REUSE_TAG_364_E                                = 959  ,
+  WIFISPARE_REUSE_TAG_365_E                                = 960  ,
+  WIFISPARE_REUSE_TAG_366_E                                = 961  ,
+  WIFISPARE_REUSE_TAG_367_E                                = 962  ,
+  WIFISPARE_REUSE_TAG_368_E                                = 963  ,
+  WIFISPARE_REUSE_TAG_369_E                                = 964  ,
+  WIFISPARE_REUSE_TAG_370_E                                = 965  ,
+  WIFISPARE_REUSE_TAG_371_E                                = 966  ,
+  WIFISPARE_REUSE_TAG_372_E                                = 967  ,
+  WIFISPARE_REUSE_TAG_373_E                                = 968  ,
+  WIFISPARE_REUSE_TAG_374_E                                = 969  ,
+  WIFISPARE_REUSE_TAG_375_E                                = 970  ,
+  WIFISPARE_REUSE_TAG_376_E                                = 971  ,
+  WIFISPARE_REUSE_TAG_377_E                                = 972  ,
+  WIFISPARE_REUSE_TAG_378_E                                = 973  ,
+  WIFISPARE_REUSE_TAG_379_E                                = 974  ,
+  WIFISPARE_REUSE_TAG_380_E                                = 975  ,
+  WIFISPARE_REUSE_TAG_381_E                                = 976  ,
+  WIFISPARE_REUSE_TAG_382_E                                = 977  ,
+  WIFISPARE_REUSE_TAG_383_E                                = 978  ,
+  WIFISPARE_REUSE_TAG_384_E                                = 979  ,
+  WIFISPARE_REUSE_TAG_385_E                                = 980  ,
+  WIFISPARE_REUSE_TAG_386_E                                = 981  ,
+  WIFISPARE_REUSE_TAG_387_E                                = 982  ,
+  WIFISPARE_REUSE_TAG_388_E                                = 983  ,
+  WIFISPARE_REUSE_TAG_389_E                                = 984  ,
+  WIFISPARE_REUSE_TAG_390_E                                = 985  ,
+  WIFISPARE_REUSE_TAG_391_E                                = 986  ,
+  WIFISPARE_REUSE_TAG_392_E                                = 987  ,
+  WIFISPARE_REUSE_TAG_393_E                                = 988  ,
+  WIFISPARE_REUSE_TAG_394_E                                = 989  ,
+  WIFISPARE_REUSE_TAG_395_E                                = 990  ,
+  WIFISPARE_REUSE_TAG_396_E                                = 991  ,
+  WIFISPARE_REUSE_TAG_397_E                                = 992  ,
+  WIFISPARE_REUSE_TAG_398_E                                = 993  ,
+  WIFISPARE_REUSE_TAG_399_E                                = 994  ,
+  WIFISPARE_REUSE_TAG_400_E                                = 995  ,
+  WIFISPARE_REUSE_TAG_401_E                                = 996  ,
+  WIFISPARE_REUSE_TAG_402_E                                = 997  ,
+  WIFISPARE_REUSE_TAG_403_E                                = 998  ,
+  WIFISPARE_REUSE_TAG_404_E                                = 999  ,
+  WIFISPARE_REUSE_TAG_405_E                                = 1000  ,
+  WIFISPARE_REUSE_TAG_406_E                                = 1001  ,
+  WIFISPARE_REUSE_TAG_407_E                                = 1002  ,
+  WIFISPARE_REUSE_TAG_408_E                                = 1003  ,
+  WIFISPARE_REUSE_TAG_409_E                                = 1004  ,
+  WIFISPARE_REUSE_TAG_410_E                                = 1005  ,
+  WIFISPARE_REUSE_TAG_411_E                                = 1006  ,
+  WIFISPARE_REUSE_TAG_412_E                                = 1007  ,
+  WIFISPARE_REUSE_TAG_413_E                                = 1008  ,
+  WIFISPARE_REUSE_TAG_414_E                                = 1009  ,
+  WIFISPARE_REUSE_TAG_415_E                                = 1010  ,
+  WIFISPARE_REUSE_TAG_416_E                                = 1011  ,
+  WIFISPARE_REUSE_TAG_417_E                                = 1012  ,
+  WIFISPARE_REUSE_TAG_418_E                                = 1013  ,
+  WIFISPARE_REUSE_TAG_419_E                                = 1014  ,
+  WIFISPARE_REUSE_TAG_420_E                                = 1015  ,
+  WIFISPARE_REUSE_TAG_421_E                                = 1016  ,
+  WIFISPARE_REUSE_TAG_422_E                                = 1017  ,
+  WIFISPARE_REUSE_TAG_423_E                                = 1018  ,
+  WIFISPARE_REUSE_TAG_424_E                                = 1019  ,
+  WIFISPARE_REUSE_TAG_425_E                                = 1020  ,
+  WIFISPARE_REUSE_TAG_426_E                                = 1021
+} tlv_tag_def__e;
+
+typedef enum {
+  WIFI_EXT_PHYRX_DATA_E                                    = 1  ,
+  WIFI_EXT_PHYRX_ABORT_REQUEST_E                           = 3  ,
+  WIFI_EXT_MACTX_DATA_RESP_E                               = 5  ,
+  WIFI_EXT_MACTX_CBF_DONE_E                                = 7  ,
+  WIFI_EXT_RXPCU_TO_UCODE_START_E                          = 9  ,
+  WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E                 = 11  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E                 = 13  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E               = 15  ,
+  WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E                       = 17  ,
+  WIFI_EXT_PHYRX_PKT_END_20MHZ_E                           = 19  ,
+  WIFI_EXT_MACRX_CBF_DATA_REQUEST_E                        = 65  ,
+  WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E                  = 67  ,
+  WIFI_EXT_MACRX_ABORT_ACK_E                               = 69  ,
+  WIFI_EXT_MACRX_CHAIN_MASK_E                              = 71  ,
+  WIFI_EXT_MACRX_ABORT_REQUEST_E                           = 73  ,
+  WIFI_EXT_PHYTX_ABORT_ACK_E                               = 75  ,
+  WIFI_EXT_PHYTX_PKT_END_E                                 = 77  ,
+  WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E                       = 79  ,
+  WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E                      = 81  ,
+  WIFI_EXT_PHYTX_NAP_DONE_E                                = 83  ,
+  WIFI_EXT_PHYTX_ON_ACK_E                                  = 85  ,
+  WIFI_EXT_PHYTX_DEBUG16_E                                 = 87  ,
+  WIFI_EXT_MACTX_ABORT_ACK_E                               = 89  ,
+  WIFI_EXT_MACTX_PRE_PHY_DESC_E                            = 91  ,
+  WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E                      = 93  ,
+  WIFI_EXT_MACTX_USER_DESC_COMMON_E                        = 95  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_16_E                           = 97  ,
+  WIFI_EXT_MACTX_PHY_OFF_E                                 = 99  ,
+  WIFI_EXT_MACTX_SYNTH_OFF_E                               = 101  ,
+  WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E                     = 103  ,
+  WIFI_EXT_MACTX_L_SIG_A_E                                 = 105  ,
+  WIFI_EXT_MACTX_HT_SIG_E                                  = 107  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU20_E                          = 109  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU80_E                          = 111  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU20_E                          = 113  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU80_E                          = 115  ,
+  WIFI_EXT_MACTX_SERVICE_E                                 = 117  ,
+  WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E                          = 119  ,
+  WIFI_EXT_MACTX_HE_SIG_B1_MU_E                            = 121  ,
+  WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E                         = 123  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_E                        = 125  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E                     = 127  ,
+  WIFI_EXT_MACTX_DEBUG_E                                   = 129  ,
+  WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E                   = 131  ,
+  WIFI_EXT_PHYRX_RSSI_HT_E                                 = 133  ,
+  WIFI_EXT_PHYRX_PKT_END_E                                 = 135  ,
+  WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E                       = 137  ,
+  WIFI_EXT_PHYRX_L_SIG_A_E                                 = 139  ,
+  WIFI_EXT_PHYRX_HT_SIG_E                                  = 141  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E                          = 143  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E                          = 145  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E                          = 147  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E                          = 149  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_SU_E                             = 151  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E                          = 153  ,
+  WIFI_EXT_PHYRX_HE_SIG_B2_MU_E                            = 155  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E                      = 157  ,
+  WIFI_EXT_PHYRX_DATA_DONE_E                               = 159  ,
+  WIFI_EXT_DUMMY_E                                         = 161  ,
+  WIFI_EXT_MPDU_LIMIT_E                                    = 163  ,
+  WIFI_EXT_OLE_BUF_STATUS_E                                = 165  ,
+  WIFI_EXT_PCU_PPDU_SETUP_END_E                            = 167  ,
+  WIFI_EXT_PCU_PPDU_SETUP_START_E                          = 169  ,
+  WIFI_EXT_PDG_RESPONSE_E                                  = 171  ,
+  WIFI_EXT_SCH_WAIT_INSTR_E                                = 173  ,
+  WIFI_EXT_PHYTX_LINK_STATE_E                              = 175  ,
+  WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E                      = 177  ,
+  WIFI_EXT_TQM_GEN_MPDUS_E                                 = 179  ,
+  WIFI_EXT_TQM_REMOVE_MPDU_E                               = 181  ,
+  WIFI_EXT_TQM_REMOVE_MSDU_E                               = 183  ,
+  WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E                      = 185  ,
+  WIFI_EXT_OFDMA_TRIGGER_DETAILS_E                         = 187  ,
+  WIFI_EXT_TX_FES_SETUP_E                                  = 189  ,
+  WIFI_EXT_EXPECTED_RESPONSE_E                             = 191  ,
+  WIFI_EXT_TX_MPDU_START_E                                 = 193  ,
+  WIFI_EXT_TX_MSDU_START_E                                 = 195  ,
+  WIFI_EXT_TXPCU_BUFFER_STATUS_E                           = 197  ,
+  WIFI_EXT_DATA_TO_TIME_CONFIG_E                           = 199  ,
+  WIFI_EXT_MPDU_INFO_E                                     = 201  ,
+  WIFI_EXT_TX_11AH_SETUP_E                                 = 203  ,
+  WIFI_EXT_TX_PEER_ENTRY_E                                 = 205  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_44_E                           = 207  ,
+  WIFI_EXT_TX_FLUSH_REQ_E                                  = 209  ,
+  WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E                      = 211  ,
+  WIFI_EXT_EXAMPLE_USER_CTLV_44_E                          = 213  ,
+  WIFI_EXT_TX_FES_STATUS_USER_PPDU_E                       = 215  ,
+  WIFI_EXT_TX_FES_STATUS_END_E                             = 217  ,
+  WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E                          = 219  ,
+  WIFI_EXT_RX_FRAME_BITMAP_ACK_E                           = 221  ,
+  WIFI_EXT_RX_START_PARAM_E                                = 223  ,
+  WIFI_EXT_RX_PPDU_END_E                                   = 225  ,
+  WIFI_EXT_RX_MPDU_END_E                                   = 227  ,
+  WIFI_EXT_RX_MSDU_END_E                                   = 229  ,
+  WIFI_EXT_RECEIVED_RESPONSE_INFO_E                        = 231  ,
+  WIFI_EXT_RX_HEADER_E                                     = 233  ,
+  WIFI_EXT_RX_FLUSH_E                                      = 235  ,
+  WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E                      = 237  ,
+  WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E                = 239  ,
+  WIFI_EXT_PCU_PPDU_SETUP_USER_E                           = 241  ,
+  WIFI_EXT_RX_PM_INFO_E                                    = 243  ,
+  WIFI_EXT_RX_PRE_PPDU_START_E                             = 245  ,
+  WIFI_EXT_TX_FES_SETUP_COMPLETE_E                         = 247  ,
+  WIFI_EXT_TXDMA_STOP_REQUEST_E                            = 249  ,
+  WIFI_EXT_RXPCU_USER_SETUP_E                              = 251  ,
+  WIFI_EXT_TQM_ACKED_MPDU_E                                = 253  ,
+  WIFI_EXT_COEX_TX_STATUS_E                                = 255  ,
+  WIFI_EXT_COEX_STATUS_BROADCAST_E                         = 257  ,
+  WIFI_EXT_RESPONSE_END_STATUS_E                           = 259  ,
+  WIFI_EXT_RECEIVED_TRIGGER_INFO_E                         = 261  ,
+  WIFI_EXT_RX_PPDU_ACK_REPORT_E                            = 263  ,
+  WIFI_EXT_SCH_COEX_STATUS_E                               = 265  ,
+  WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E          = 267  ,
+  WIFI_EXT_TX_FES_STATUS_START_PPDU_E                      = 269  ,
+  WIFI_EXT_TXPCU_PHYTX_DEBUG32_E                           = 271  ,
+  WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E                    = 273  ,
+  WIFI_EXT_WHO_ANCHOR_VALUE_E                              = 275  ,
+  WIFI_EXT_WHO_COMMIT_E                                    = 277  ,
+  WIFI_EXT_WHO_FLUSH_E                                     = 279  ,
+  WIFI_EXT_WHO_L2_PAYLOAD_E                                = 281  ,
+  WIFI_EXT_WHO_L3_INFO_E                                   = 283  ,
+  WIFI_EXT_WHO_L4_INFO_E                                   = 285  ,
+  WIFI_EXT_WHO_MSDU_MISC_E                                 = 287  ,
+  WIFI_EXT_WHO_PACKET_HDR_E                                = 289  ,
+  WIFI_EXT_WHO_PPDU_START_E                                = 291  ,
+  WIFI_EXT_WHO_WMAC_HEADER_PV0_E                           = 293  ,
+  WIFI_EXT_WHO_WMAC_IV_E                                   = 295  ,
+  WIFI_EXT_MPDU_INFO_BITMAP_E                              = 297  ,
+  WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E             = 299  ,
+  WIFI_EXT_TQM_ACKED_MPDU_STATUS_E                         = 301  ,
+  WIFI_EXT_TQM_LIST_GEN_DONE_E                             = 303  ,
+  WIFI_EXT_TX_LAST_MPDU_END_E                              = 305  ,
+  WIFI_EXT_PPDU_TX_END_E                                   = 307  ,
+  WIFI_EXT_MPDU_INFO_GLOBAL_END_E                          = 309  ,
+  WIFI_EXT_RX_PPDU_END_USER_STATS_E                        = 311  ,
+  WIFI_EXT_REO_GET_QUEUE_STATS_E                           = 313  ,
+  WIFI_EXT_REO_FLUSH_CACHE_E                               = 315  ,
+  WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E                    = 317  ,
+  WIFI_EXT_REO_FLUSH_CACHE_STATUS_E                        = 319  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_E                               = 321  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E                        = 323  ,
+  WIFI_EXT_RX_PPDU_END_STATUS_DONE_E                       = 325  ,
+  WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E                   = 327  ,
+  WIFI_EXT_TX_DATA_SYNC_E                                  = 329  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E                        = 331  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E                 = 333  ,
+  WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E        = 335  ,
+  WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E                        = 337  ,
+  WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E       = 339  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E                      = 341  ,
+  WIFI_EXT_RX_RING_MASK_E                                  = 343  ,
+  WIFI_EXT_RXPCU_PPDU_END_INFO_E                           = 345  ,
+  WIFI_EXT_PDG_SW_MODE_BW_START_E                          = 347  ,
+  WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E                      = 349  ,
+  WIFI_EXT_SCHEDULER_END_E                                 = 351  ,
+  WIFI_EXT_RX_PPDU_END_DROPPED_E                           = 353  ,
+  WIFI_EXT_RX_MPDU_START_DROPPED_E                         = 355  ,
+  WIFI_EXT_RX_MSDU_END_DROPPED_E                           = 357  ,
+  WIFI_EXT_RX_ATTENTION_DROPPED_E                          = 359  ,
+  WIFI_EXT_RXPCU_USER_SETUP_EXT_E                          = 361  ,
+  WIFI_EXT_MACTX_SYNTH_ON_E                                = 363  ,
+  WIFI_EXT_TQM_MPDU_GLOBAL_START_E                         = 365  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E                       = 367  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E                = 369  ,
+  WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E                       = 371  ,
+  WIFI_EXT_PDG_TRIG_RESPONSE_E                             = 373  ,
+  WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E                      = 375  ,
+  WIFI_EXT_MPDUS_AVAILABLE_E                               = 377  ,
+  WIFI_EXT_PHYRX_TX_START_TIMING_E                         = 379  ,
+  WIFI_EXT_NDP_PREAMBLE_DONE_E                             = 381  ,
+  WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E                 = 383  ,
+  WIFI_EXT_TX_PUNCTURE_SETUP_E                             = 385  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E                      = 387  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E                   = 389  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E                    = 391  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E                  = 393  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E                  = 395  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E           = 397  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E               = 399  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E          = 401  ,
+  WIFI_EXT_RX_PPDU_END_START_E                             = 403  ,
+  WIFI_EXT_RX_PPDU_END_LAST_E                              = 405  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E         = 407  ,
+  WIFI_EXT_OBSS_SR_INFO_E                                  = 409  ,
+  WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E             = 411  ,
+  WIFI_EXT_MACTX_MCC_SWITCH_E                              = 413  ,
+  WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E                          = 415  ,
+  WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E                    = 417  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E       = 419  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E         = 421  ,
+  WIFI_EXT_SCH_TLV_WRAPPER_E                               = 423  ,
+  WIFI_EXT_MPDU_INFO_6X_E                                  = 425  ,
+  WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E                         = 427  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E                     = 429  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E                     = 431  ,
+  WIFI_EXT_PHYRX_U_SIG_EHT_TB_E                            = 433  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                 = 435  ,
+  WIFI_EXT_MACRX_LMR_READ_REQUEST_E                        = 437  ,
+  WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E                       = 439  ,
+  WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E                    = 441  ,
+  WIFI_EXT_PHYRX_USER_INFO_MU_UL_E                         = 443  ,
+  WIFI_EXT_SCHEDULER_NAV_INFO_E                            = 445  ,
+  WIFI_EXT_LMR_PEER_ENTRY_E                                = 447  ,
+  WIFI_EXT_LMR_DATA_E                                      = 449  ,
+  WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E                 = 451  ,
+  WIFI_EXT_TX_FES_STATUS_1K_BA_E                           = 453  ,
+  WIFI_EXT_MACRX_INBSS_OBSS_IND_E                          = 455  ,
+  WIFI_EXT_MLO_TX_NOTIFICATION_SU_E                        = 457  ,
+  WIFI_EXT_MLO_TX_REQ_SU_E                                 = 459  ,
+  WIFI_EXT_MLO_TX_RESP_E                                   = 461  ,
+  WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E                           = 463  ,
+  WIFI_EXT_MLO_MESSAGE_E                                   = 465  ,
+  WIFI_EXT_MLO_FES_SETUP_E                                 = 467  ,
+  WIFI_EXT_MLO_PDG_FES_SETUP_MU_E                          = 469  ,
+  WIFI_EXT_MON_BUFFER_ADDR_E                               = 471  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E        = 473  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E                       = 475  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_TB_E                            = 477  ,
+  WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E                = 479  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E                       = 481  ,
+  WIFI_EXT_PHYRX_PKT_END_PART1_E                           = 483  ,
+  WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E                      = 485  ,
+  WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E                    = 487  ,
+  WIFI_EXT_PHYTX_LOCATION_E                                = 489  ,
+  WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E                     = 491  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E                     = 493  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E                     = 495  ,
+  WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E                  = 497  ,
+  WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E                  = 499  ,
+  WIFI_EXT_OVERWRITE_RESP_END_E                            = 501  ,
+  WIFI_EXT_MON_DROP_E                                      = 503  ,
+  WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E              = 505  ,
+  WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E              = 507  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E                    = 509  ,
+  WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E                 = 511  ,
+  WIFI_EXT_RANGING_USER_DETAILS_E                          = 513  ,
+  WIFI_EXT_PHYTX_CV_CORR_COMMON_E                          = 515  ,
+  WIFI_EXT_MACTX_CV_CORR_COMMON_E                          = 517  ,
+  WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E                      = 519  ,
+  WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E                 = 521  ,
+  WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E             = 523  ,
+  WIFI_EXT_FW2SW_MON_E                                     = 525  ,
+  WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E                        = 527  ,
+  WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E                       = 529  ,
+  WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E                   = 531  ,
+  WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E                     = 533  ,
+  WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E                  = 535  ,
+  WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E                     = 537  ,
+  WIFI_EXT_TPI_MPDU_START_E                                = 539  ,
+  WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E          = 541  ,
+  WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E                     = 543  ,
+  WIFI_EXT_TPI_ERROR_STATUS_E                              = 545  ,
+  WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E                         = 547  ,
+  WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E                  = 549  ,
+  WIFI_EXT_RPI_ERROR_STATUS_E                              = 551  ,
+  WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E                    = 553  ,
+  WIFI_EXT_TCC_TLV_FETCH_E                                 = 555  ,
+  WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E                  = 557  ,
+  WIFI_EXT_TCC_ERROR_STATUS_E                              = 559  ,
+  WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E                 = 561  ,
+  WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E                       = 563  ,
+  WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E                   = 565  ,
+  WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E                     = 567  ,
+  WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E                   = 569  ,
+  WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E                     = 571  ,
+  WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E                    = 573  ,
+  WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E              = 575  ,
+  WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E                       = 577  ,
+  WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E                     = 579  ,
+  WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E                          = 581  ,
+  WIFI_EXT_PEER_BLACKOUT_DETAILS_E                         = 583  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E                      = 585  ,
+  WIFI_EXT_HDR_CTRL_PROT_DATA_E                            = 587  ,
+  WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E                      = 589  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E                 = 591  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_COBF_E                          = 593  ,
+  WIFI_EXT_SPARE_REUSE_TAG_0_E                             = 595  ,
+  WIFI_EXT_SPARE_REUSE_TAG_2_E                             = 597  ,
+  WIFI_EXT_SPARE_REUSE_TAG_4_E                             = 599  ,
+  WIFI_EXT_SPARE_REUSE_TAG_6_E                             = 601  ,
+  WIFI_EXT_SPARE_REUSE_TAG_8_E                             = 603  ,
+  WIFI_EXT_SPARE_REUSE_TAG_10_E                            = 605  ,
+  WIFI_EXT_SPARE_REUSE_TAG_12_E                            = 607  ,
+  WIFI_EXT_SPARE_REUSE_TAG_14_E                            = 609  ,
+  WIFI_EXT_SPARE_REUSE_TAG_16_E                            = 611  ,
+  WIFI_EXT_SPARE_REUSE_TAG_18_E                            = 613  ,
+  WIFI_EXT_SPARE_REUSE_TAG_20_E                            = 615  ,
+  WIFI_EXT_SPARE_REUSE_TAG_22_E                            = 617  ,
+  WIFI_EXT_SPARE_REUSE_TAG_24_E                            = 619  ,
+  WIFI_EXT_SPARE_REUSE_TAG_26_E                            = 621  ,
+  WIFI_EXT_SPARE_REUSE_TAG_28_E                            = 623  ,
+  WIFI_EXT_SPARE_REUSE_TAG_30_E                            = 625  ,
+  WIFI_EXT_SPARE_REUSE_TAG_32_E                            = 627  ,
+  WIFI_EXT_SPARE_REUSE_TAG_34_E                            = 629  ,
+  WIFI_EXT_SPARE_REUSE_TAG_36_E                            = 631  ,
+  WIFI_EXT_SPARE_REUSE_TAG_38_E                            = 633  ,
+  WIFI_EXT_SPARE_REUSE_TAG_40_E                            = 635  ,
+  WIFI_EXT_SPARE_REUSE_TAG_42_E                            = 637  ,
+  WIFI_EXT_SPARE_REUSE_TAG_44_E                            = 639  ,
+  WIFI_EXT_SPARE_REUSE_TAG_46_E                            = 641  ,
+  WIFI_EXT_SPARE_REUSE_TAG_48_E                            = 643  ,
+  WIFI_EXT_SPARE_REUSE_TAG_50_E                            = 645  ,
+  WIFI_EXT_SPARE_REUSE_TAG_52_E                            = 647  ,
+  WIFI_EXT_SPARE_REUSE_TAG_54_E                            = 649  ,
+  WIFI_EXT_SPARE_REUSE_TAG_56_E                            = 651  ,
+  WIFI_EXT_SPARE_REUSE_TAG_58_E                            = 653  ,
+  WIFI_EXT_SPARE_REUSE_TAG_60_E                            = 655  ,
+  WIFI_EXT_SPARE_REUSE_TAG_62_E                            = 657  ,
+  WIFI_EXT_SPARE_REUSE_TAG_64_E                            = 659  ,
+  WIFI_EXT_SPARE_REUSE_TAG_66_E                            = 661  ,
+  WIFI_EXT_SPARE_REUSE_TAG_68_E                            = 663  ,
+  WIFI_EXT_SPARE_REUSE_TAG_70_E                            = 665  ,
+  WIFI_EXT_SPARE_REUSE_TAG_72_E                            = 667  ,
+  WIFI_EXT_SPARE_REUSE_TAG_74_E                            = 669  ,
+  WIFI_EXT_SPARE_REUSE_TAG_76_E                            = 671  ,
+  WIFI_EXT_SPARE_REUSE_TAG_78_E                            = 673  ,
+  WIFI_EXT_SPARE_REUSE_TAG_80_E                            = 675  ,
+  WIFI_EXT_SPARE_REUSE_TAG_82_E                            = 677  ,
+  WIFI_EXT_SPARE_REUSE_TAG_84_E                            = 679  ,
+  WIFI_EXT_SPARE_REUSE_TAG_86_E                            = 681  ,
+  WIFI_EXT_SPARE_REUSE_TAG_88_E                            = 683  ,
+  WIFI_EXT_SPARE_REUSE_TAG_90_E                            = 685  ,
+  WIFI_EXT_SPARE_REUSE_TAG_92_E                            = 687  ,
+  WIFI_EXT_SPARE_REUSE_TAG_94_E                            = 689  ,
+  WIFI_EXT_SPARE_REUSE_TAG_96_E                            = 691  ,
+  WIFI_EXT_SPARE_REUSE_TAG_98_E                            = 693  ,
+  WIFI_EXT_SPARE_REUSE_TAG_100_E                           = 695  ,
+  WIFI_EXT_SPARE_REUSE_TAG_102_E                           = 697  ,
+  WIFI_EXT_SPARE_REUSE_TAG_104_E                           = 699  ,
+  WIFI_EXT_SPARE_REUSE_TAG_106_E                           = 701  ,
+  WIFI_EXT_SPARE_REUSE_TAG_108_E                           = 703  ,
+  WIFI_EXT_SPARE_REUSE_TAG_110_E                           = 705  ,
+  WIFI_EXT_SPARE_REUSE_TAG_112_E                           = 707  ,
+  WIFI_EXT_SPARE_REUSE_TAG_114_E                           = 709  ,
+  WIFI_EXT_SPARE_REUSE_TAG_116_E                           = 711  ,
+  WIFI_EXT_SPARE_REUSE_TAG_118_E                           = 713  ,
+  WIFI_EXT_SPARE_REUSE_TAG_120_E                           = 715  ,
+  WIFI_EXT_SPARE_REUSE_TAG_122_E                           = 717  ,
+  WIFI_EXT_SPARE_REUSE_TAG_124_E                           = 719  ,
+  WIFI_EXT_SPARE_REUSE_TAG_126_E                           = 721  ,
+  WIFI_EXT_SPARE_REUSE_TAG_128_E                           = 723  ,
+  WIFI_EXT_SPARE_REUSE_TAG_130_E                           = 725  ,
+  WIFI_EXT_SPARE_REUSE_TAG_132_E                           = 727  ,
+  WIFI_EXT_SPARE_REUSE_TAG_134_E                           = 729  ,
+  WIFI_EXT_SPARE_REUSE_TAG_136_E                           = 731  ,
+  WIFI_EXT_SPARE_REUSE_TAG_138_E                           = 733  ,
+  WIFI_EXT_SPARE_REUSE_TAG_140_E                           = 735  ,
+  WIFI_EXT_SPARE_REUSE_TAG_142_E                           = 737  ,
+  WIFI_EXT_SPARE_REUSE_TAG_144_E                           = 739  ,
+  WIFI_EXT_SPARE_REUSE_TAG_146_E                           = 741  ,
+  WIFI_EXT_SPARE_REUSE_TAG_148_E                           = 743  ,
+  WIFI_EXT_SPARE_REUSE_TAG_150_E                           = 745  ,
+  WIFI_EXT_SPARE_REUSE_TAG_152_E                           = 747  ,
+  WIFI_EXT_SPARE_REUSE_TAG_154_E                           = 749  ,
+  WIFI_EXT_SPARE_REUSE_TAG_156_E                           = 751  ,
+  WIFI_EXT_SPARE_REUSE_TAG_158_E                           = 753  ,
+  WIFI_EXT_SPARE_REUSE_TAG_160_E                           = 755  ,
+  WIFI_EXT_SPARE_REUSE_TAG_162_E                           = 757  ,
+  WIFI_EXT_SPARE_REUSE_TAG_164_E                           = 759  ,
+  WIFI_EXT_SPARE_REUSE_TAG_166_E                           = 761  ,
+  WIFI_EXT_SPARE_REUSE_TAG_168_E                           = 763  ,
+  WIFI_EXT_SPARE_REUSE_TAG_170_E                           = 765  ,
+  WIFI_EXT_SPARE_REUSE_TAG_172_E                           = 767  ,
+  WIFI_EXT_SPARE_REUSE_TAG_174_E                           = 769  ,
+  WIFI_EXT_SPARE_REUSE_TAG_176_E                           = 771  ,
+  WIFI_EXT_SPARE_REUSE_TAG_178_E                           = 773  ,
+  WIFI_EXT_SPARE_REUSE_TAG_180_E                           = 775  ,
+  WIFI_EXT_SPARE_REUSE_TAG_182_E                           = 777  ,
+  WIFI_EXT_SPARE_REUSE_TAG_184_E                           = 779  ,
+  WIFI_EXT_SPARE_REUSE_TAG_186_E                           = 781  ,
+  WIFI_EXT_SPARE_REUSE_TAG_188_E                           = 783  ,
+  WIFI_EXT_SPARE_REUSE_TAG_190_E                           = 785  ,
+  WIFI_EXT_SPARE_REUSE_TAG_192_E                           = 787  ,
+  WIFI_EXT_SPARE_REUSE_TAG_194_E                           = 789  ,
+  WIFI_EXT_SPARE_REUSE_TAG_196_E                           = 791  ,
+  WIFI_EXT_SPARE_REUSE_TAG_198_E                           = 793  ,
+  WIFI_EXT_SPARE_REUSE_TAG_200_E                           = 795  ,
+  WIFI_EXT_SPARE_REUSE_TAG_202_E                           = 797  ,
+  WIFI_EXT_SPARE_REUSE_TAG_204_E                           = 799  ,
+  WIFI_EXT_SPARE_REUSE_TAG_206_E                           = 801  ,
+  WIFI_EXT_SPARE_REUSE_TAG_208_E                           = 803  ,
+  WIFI_EXT_SPARE_REUSE_TAG_210_E                           = 805  ,
+  WIFI_EXT_SPARE_REUSE_TAG_212_E                           = 807  ,
+  WIFI_EXT_SPARE_REUSE_TAG_214_E                           = 809  ,
+  WIFI_EXT_SPARE_REUSE_TAG_216_E                           = 811  ,
+  WIFI_EXT_SPARE_REUSE_TAG_218_E                           = 813  ,
+  WIFI_EXT_SPARE_REUSE_TAG_220_E                           = 815  ,
+  WIFI_EXT_SPARE_REUSE_TAG_222_E                           = 817  ,
+  WIFI_EXT_SPARE_REUSE_TAG_224_E                           = 819  ,
+  WIFI_EXT_SPARE_REUSE_TAG_226_E                           = 821  ,
+  WIFI_EXT_SPARE_REUSE_TAG_228_E                           = 823  ,
+  WIFI_EXT_SPARE_REUSE_TAG_230_E                           = 825  ,
+  WIFI_EXT_SPARE_REUSE_TAG_232_E                           = 827  ,
+  WIFI_EXT_SPARE_REUSE_TAG_234_E                           = 829  ,
+  WIFI_EXT_SPARE_REUSE_TAG_236_E                           = 831  ,
+  WIFI_EXT_SPARE_REUSE_TAG_238_E                           = 833  ,
+  WIFI_EXT_SPARE_REUSE_TAG_240_E                           = 835  ,
+  WIFI_EXT_SPARE_REUSE_TAG_242_E                           = 837  ,
+  WIFI_EXT_SPARE_REUSE_TAG_244_E                           = 839  ,
+  WIFI_EXT_SPARE_REUSE_TAG_246_E                           = 841  ,
+  WIFI_EXT_SPARE_REUSE_TAG_248_E                           = 843  ,
+  WIFI_EXT_SPARE_REUSE_TAG_250_E                           = 845  ,
+  WIFI_EXT_SPARE_REUSE_TAG_252_E                           = 847  ,
+  WIFI_EXT_SPARE_REUSE_TAG_254_E                           = 849  ,
+  WIFI_EXT_SPARE_REUSE_TAG_256_E                           = 851  ,
+  WIFI_EXT_SPARE_REUSE_TAG_258_E                           = 853  ,
+  WIFI_EXT_SPARE_REUSE_TAG_260_E                           = 855  ,
+  WIFI_EXT_SPARE_REUSE_TAG_262_E                           = 857  ,
+  WIFI_EXT_SPARE_REUSE_TAG_264_E                           = 859  ,
+  WIFI_EXT_SPARE_REUSE_TAG_266_E                           = 861  ,
+  WIFI_EXT_SPARE_REUSE_TAG_268_E                           = 863  ,
+  WIFI_EXT_SPARE_REUSE_TAG_270_E                           = 865  ,
+  WIFI_EXT_SPARE_REUSE_TAG_272_E                           = 867  ,
+  WIFI_EXT_SPARE_REUSE_TAG_274_E                           = 869  ,
+  WIFI_EXT_SPARE_REUSE_TAG_276_E                           = 871  ,
+  WIFI_EXT_SPARE_REUSE_TAG_278_E                           = 873  ,
+  WIFI_EXT_SPARE_REUSE_TAG_280_E                           = 875  ,
+  WIFI_EXT_SPARE_REUSE_TAG_282_E                           = 877  ,
+  WIFI_EXT_SPARE_REUSE_TAG_284_E                           = 879  ,
+  WIFI_EXT_SPARE_REUSE_TAG_286_E                           = 881  ,
+  WIFI_EXT_SPARE_REUSE_TAG_288_E                           = 883  ,
+  WIFI_EXT_SPARE_REUSE_TAG_290_E                           = 885  ,
+  WIFI_EXT_SPARE_REUSE_TAG_292_E                           = 887  ,
+  WIFI_EXT_SPARE_REUSE_TAG_294_E                           = 889  ,
+  WIFI_EXT_SPARE_REUSE_TAG_296_E                           = 891  ,
+  WIFI_EXT_SPARE_REUSE_TAG_298_E                           = 893  ,
+  WIFI_EXT_SPARE_REUSE_TAG_300_E                           = 895  ,
+  WIFI_EXT_SPARE_REUSE_TAG_302_E                           = 897  ,
+  WIFI_EXT_SPARE_REUSE_TAG_304_E                           = 899  ,
+  WIFI_EXT_SPARE_REUSE_TAG_306_E                           = 901  ,
+  WIFI_EXT_SPARE_REUSE_TAG_308_E                           = 903  ,
+  WIFI_EXT_SPARE_REUSE_TAG_310_E                           = 905  ,
+  WIFI_EXT_SPARE_REUSE_TAG_312_E                           = 907  ,
+  WIFI_EXT_SPARE_REUSE_TAG_314_E                           = 909  ,
+  WIFI_EXT_SPARE_REUSE_TAG_316_E                           = 911  ,
+  WIFI_EXT_SPARE_REUSE_TAG_318_E                           = 913  ,
+  WIFI_EXT_SPARE_REUSE_TAG_320_E                           = 915  ,
+  WIFI_EXT_SPARE_REUSE_TAG_322_E                           = 917  ,
+  WIFI_EXT_SPARE_REUSE_TAG_324_E                           = 919  ,
+  WIFI_EXT_SPARE_REUSE_TAG_326_E                           = 921  ,
+  WIFI_EXT_SPARE_REUSE_TAG_328_E                           = 923  ,
+  WIFI_EXT_SPARE_REUSE_TAG_330_E                           = 925  ,
+  WIFI_EXT_SPARE_REUSE_TAG_332_E                           = 927  ,
+  WIFI_EXT_SPARE_REUSE_TAG_334_E                           = 929  ,
+  WIFI_EXT_SPARE_REUSE_TAG_336_E                           = 931  ,
+  WIFI_EXT_SPARE_REUSE_TAG_338_E                           = 933  ,
+  WIFI_EXT_SPARE_REUSE_TAG_340_E                           = 935  ,
+  WIFI_EXT_SPARE_REUSE_TAG_342_E                           = 937  ,
+  WIFI_EXT_SPARE_REUSE_TAG_344_E                           = 939  ,
+  WIFI_EXT_SPARE_REUSE_TAG_346_E                           = 941  ,
+  WIFI_EXT_SPARE_REUSE_TAG_348_E                           = 943  ,
+  WIFI_EXT_SPARE_REUSE_TAG_350_E                           = 945  ,
+  WIFI_EXT_SPARE_REUSE_TAG_352_E                           = 947  ,
+  WIFI_EXT_SPARE_REUSE_TAG_354_E                           = 949  ,
+  WIFI_EXT_SPARE_REUSE_TAG_356_E                           = 951  ,
+  WIFI_EXT_SPARE_REUSE_TAG_358_E                           = 953  ,
+  WIFI_EXT_SPARE_REUSE_TAG_360_E                           = 955  ,
+  WIFI_EXT_SPARE_REUSE_TAG_362_E                           = 957  ,
+  WIFI_EXT_SPARE_REUSE_TAG_364_E                           = 959  ,
+  WIFI_EXT_SPARE_REUSE_TAG_366_E                           = 961  ,
+  WIFI_EXT_SPARE_REUSE_TAG_368_E                           = 963  ,
+  WIFI_EXT_SPARE_REUSE_TAG_370_E                           = 965  ,
+  WIFI_EXT_SPARE_REUSE_TAG_372_E                           = 967  ,
+  WIFI_EXT_SPARE_REUSE_TAG_374_E                           = 969  ,
+  WIFI_EXT_SPARE_REUSE_TAG_376_E                           = 971  ,
+  WIFI_EXT_SPARE_REUSE_TAG_378_E                           = 973  ,
+  WIFI_EXT_SPARE_REUSE_TAG_380_E                           = 975  ,
+  WIFI_EXT_SPARE_REUSE_TAG_382_E                           = 977  ,
+  WIFI_EXT_SPARE_REUSE_TAG_384_E                           = 979  ,
+  WIFI_EXT_SPARE_REUSE_TAG_386_E                           = 981  ,
+  WIFI_EXT_SPARE_REUSE_TAG_388_E                           = 983  ,
+  WIFI_EXT_SPARE_REUSE_TAG_390_E                           = 985  ,
+  WIFI_EXT_SPARE_REUSE_TAG_392_E                           = 987  ,
+  WIFI_EXT_SPARE_REUSE_TAG_394_E                           = 989  ,
+  WIFI_EXT_SPARE_REUSE_TAG_396_E                           = 991  ,
+  WIFI_EXT_SPARE_REUSE_TAG_398_E                           = 993  ,
+  WIFI_EXT_SPARE_REUSE_TAG_400_E                           = 995  ,
+  WIFI_EXT_SPARE_REUSE_TAG_402_E                           = 997  ,
+  WIFI_EXT_SPARE_REUSE_TAG_404_E                           = 999  ,
+  WIFI_EXT_SPARE_REUSE_TAG_406_E                           = 1001  ,
+  WIFI_EXT_SPARE_REUSE_TAG_408_E                           = 1003  ,
+  WIFI_EXT_SPARE_REUSE_TAG_410_E                           = 1005  ,
+  WIFI_EXT_SPARE_REUSE_TAG_412_E                           = 1007  ,
+  WIFI_EXT_SPARE_REUSE_TAG_414_E                           = 1009  ,
+  WIFI_EXT_SPARE_REUSE_TAG_416_E                           = 1011  ,
+  WIFI_EXT_SPARE_REUSE_TAG_418_E                           = 1013  ,
+  WIFI_EXT_SPARE_REUSE_TAG_420_E                           = 1015  ,
+  WIFI_EXT_SPARE_REUSE_TAG_422_E                           = 1017  ,
+  WIFI_EXT_SPARE_REUSE_TAG_424_E                           = 1019  ,
+  WIFI_EXT_SPARE_REUSE_TAG_426_E                           = 1021
+} ext_tlv_tag_def__e;
+
+typedef enum {
+  WIFI_N_EXT_MACTX_CBF_START_E                             = 0  ,
+  WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E                         = 2  ,
+  WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E               = 4  ,
+  WIFI_N_EXT_MACTX_CBF_DATA_E                              = 6  ,
+  WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E                         = 8  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E      = 10  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E                   = 12  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E    = 14  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_END_E                          = 16  ,
+  WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E                      = 18  ,
+  WIFI_N_EXT_PHYRX_NC_DATA_E                               = 20  ,
+  WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E                      = 64  ,
+  WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E                  = 66  ,
+  WIFI_N_EXT_MACRX_NDP_TIMEOUT_E                           = 68  ,
+  WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E                       = 70  ,
+  WIFI_N_EXT_MACRX_NAP_USER_E                              = 72  ,
+  WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E                 = 74  ,
+  WIFI_N_EXT_PHYTX_ABORT_REQUEST_E                         = 76  ,
+  WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E              = 78  ,
+  WIFI_N_EXT_PHYTX_DATA_REQUEST_E                          = 80  ,
+  WIFI_N_EXT_PHYTX_NAP_ACK_E                               = 82  ,
+  WIFI_N_EXT_PHYTX_OFF_ACK_E                               = 84  ,
+  WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E                         = 86  ,
+  WIFI_N_EXT_MACTX_ABORT_REQUEST_E                         = 88  ,
+  WIFI_N_EXT_MACTX_PKT_END_E                               = 90  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E                      = 92  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_E                           = 94  ,
+  WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E                    = 96  ,
+  WIFI_N_EXT_EXAMPLE_TLV_16_E                              = 98  ,
+  WIFI_N_EXT_MACTX_PHY_ON_E                                = 100  ,
+  WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E                     = 102  ,
+  WIFI_N_EXT_MACTX_PHY_DESC_E                              = 104  ,
+  WIFI_N_EXT_MACTX_L_SIG_B_E                               = 106  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_A_E                             = 108  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E                        = 110  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E                       = 112  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E                        = 114  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E                       = 116  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_SU_E                           = 118  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E                        = 120  ,
+  WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E                          = 122  ,
+  WIFI_N_EXT_MACTX_DELETE_CV_E                             = 124  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E                  = 126  ,
+  WIFI_N_EXT_MACTX_PHY_NAP_E                               = 128  ,
+  WIFI_N_EXT_PHYRX_ABORT_ACK_E                             = 130  ,
+  WIFI_N_EXT_PHYRX_RSSI_LEGACY_E                           = 132  ,
+  WIFI_N_EXT_PHYRX_USER_INFO_E                             = 134  ,
+  WIFI_N_EXT_PHYRX_DEBUG_E                                 = 136  ,
+  WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E                    = 138  ,
+  WIFI_N_EXT_PHYRX_L_SIG_B_E                               = 140  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_A_E                             = 142  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E                        = 144  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E                       = 146  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E                        = 148  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E                       = 150  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E                        = 152  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E                          = 154  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E                       = 156  ,
+  WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E                      = 158  ,
+  WIFI_N_EXT_COEX_TX_REQ_E                                 = 160  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E                         = 162  ,
+  WIFI_N_EXT_NA_LENGTH_END_E                               = 164  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E                         = 166  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E                         = 168  ,
+  WIFI_N_EXT_PDG_FES_SETUP_E                               = 170  ,
+  WIFI_N_EXT_PDG_TX_REQ_E                                  = 172  ,
+  WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E                        = 174  ,
+  WIFI_N_EXT_AUX_PPDU_END_E                                = 176  ,
+  WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E             = 178  ,
+  WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E                        = 180  ,
+  WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E                      = 182  ,
+  WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E                      = 184  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_E                               = 186  ,
+  WIFI_N_EXT_TX_DATA_E                                     = 188  ,
+  WIFI_N_EXT_RX_PACKET_E                                   = 190  ,
+  WIFI_N_EXT_TX_MPDU_END_E                                 = 192  ,
+  WIFI_N_EXT_TX_MSDU_END_E                                 = 194  ,
+  WIFI_N_EXT_TX_SW_MODE_SETUP_E                            = 196  ,
+  WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E                    = 198  ,
+  WIFI_N_EXT_EXAMPLE_USER_TLV_32_E                         = 200  ,
+  WIFI_N_EXT_PDG_USER_SETUP_E                              = 202  ,
+  WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E              = 204  ,
+  WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E                = 206  ,
+  WIFI_N_EXT_TX_FLUSH_E                                    = 208  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E                        = 210  ,
+  WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E                     = 212  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_E                         = 214  ,
+  WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E                 = 216  ,
+  WIFI_N_EXT_RX_TRIG_INFO_E                                = 218  ,
+  WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E                         = 220  ,
+  WIFI_N_EXT_COEX_RX_STATUS_E                              = 222  ,
+  WIFI_N_EXT_RX_PPDU_START_E                               = 224  ,
+  WIFI_N_EXT_RX_MPDU_START_E                               = 226  ,
+  WIFI_N_EXT_RX_MSDU_START_E                               = 228  ,
+  WIFI_N_EXT_RX_ATTENTION_E                                = 230  ,
+  WIFI_N_EXT_RX_PHY_SLEEP_E                                = 232  ,
+  WIFI_N_EXT_RX_PEER_ENTRY_E                               = 234  ,
+  WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E                   = 236  ,
+  WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E             = 238  ,
+  WIFI_N_EXT_TX_CBF_INFO_E                                 = 240  ,
+  WIFI_N_EXT_RX_MPDU_PCU_START_E                           = 242  ,
+  WIFI_N_EXT_RX_USER_PPDU_END_E                            = 244  ,
+  WIFI_N_EXT_RX_PREAMBLE_E                                 = 246  ,
+  WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E                        = 248  ,
+  WIFI_N_EXT_RXPCU_SETUP_E                                 = 250  ,
+  WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E                     = 252  ,
+  WIFI_N_EXT_COEX_TX_RESP_E                                = 254  ,
+  WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E                         = 256  ,
+  WIFI_N_EXT_RESPONSE_START_STATUS_E                       = 258  ,
+  WIFI_N_EXT_CRYPTO_STATUS_E                               = 260  ,
+  WIFI_N_EXT_COEX_TX_STOP_CTRL_E                           = 262  ,
+  WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E                       = 264  ,
+  WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E                    = 266  ,
+  WIFI_N_EXT_TX_FES_STATUS_PROT_E                          = 268  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_PROT_E                    = 270  ,
+  WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E           = 272  ,
+  WIFI_N_EXT_WHO_ANCHOR_OFFSET_E                           = 274  ,
+  WIFI_N_EXT_WHO_CCE_INFO_E                                = 276  ,
+  WIFI_N_EXT_WHO_COMMIT_DONE_E                             = 278  ,
+  WIFI_N_EXT_WHO_L2_LLC_E                                  = 280  ,
+  WIFI_N_EXT_WHO_L3_CHECKSUM_E                             = 282  ,
+  WIFI_N_EXT_WHO_L4_CHECKSUM_E                             = 284  ,
+  WIFI_N_EXT_WHO_MSDU_E                                    = 286  ,
+  WIFI_N_EXT_WHO_PACKET_DATA_E                             = 288  ,
+  WIFI_N_EXT_WHO_PPDU_END_E                                = 290  ,
+  WIFI_N_EXT_WHO_TSO_E                                     = 292  ,
+  WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E                         = 294  ,
+  WIFI_N_EXT_MPDU_INFO_END_E                               = 296  ,
+  WIFI_N_EXT_TX_QUEUE_EXTENSION_E                          = 298  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E             = 300  ,
+  WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E                         = 302  ,
+  WIFI_N_EXT_WHO_TERMINATE_E                               = 304  ,
+  WIFI_N_EXT_TX_CV_DATA_E                                  = 306  ,
+  WIFI_N_EXT_PROT_TX_END_E                                 = 308  ,
+  WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E                    = 310  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E                  = 312  ,
+  WIFI_N_EXT_REO_FLUSH_QUEUE_E                             = 314  ,
+  WIFI_N_EXT_REO_UNBLOCK_CACHE_E                           = 316  ,
+  WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E                      = 318  ,
+  WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E                    = 320  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_E                           = 322  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E                    = 324  ,
+  WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E                       = 326  ,
+  WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E             = 328  ,
+  WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E                  = 330  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_E                                = 332  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E                         = 334  ,
+  WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E                         = 336  ,
+  WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E               = 338  ,
+  WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E   = 340  ,
+  WIFI_N_EXT_RX_PPDU_START_USER_INFO_E                     = 342  ,
+  WIFI_N_EXT_COEX_MAC_NAP_E                                = 344  ,
+  WIFI_N_EXT_WHO_MESH_CONTROL_E                            = 346  ,
+  WIFI_N_EXT_PDG_SW_MODE_BW_END_E                          = 348  ,
+  WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E                    = 350  ,
+  WIFI_N_EXT_RX_PPDU_START_DROPPED_E                       = 352  ,
+  WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E             = 354  ,
+  WIFI_N_EXT_RX_MSDU_START_DROPPED_E                       = 356  ,
+  WIFI_N_EXT_RX_MPDU_END_DROPPED_E                         = 358  ,
+  WIFI_N_EXT_TXPCU_USER_SETUP_E                            = 360  ,
+  WIFI_N_EXT_CMD_PART_0_END_E                              = 362  ,
+  WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E                  = 364  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_E                              = 366  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E               = 368  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E        = 370  ,
+  WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E                    = 372  ,
+  WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E                    = 374  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E                         = 376  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E                = 378  ,
+  WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E                         = 380  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E                = 382  ,
+  WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E                    = 384  ,
+  WIFI_N_EXT_R2R_STATUS_END_E                              = 386  ,
+  WIFI_N_EXT_END_OF_FLUSH_MARKER_E                         = 388  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E             = 390  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E                 = 392  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E                = 394  ,
+  WIFI_N_EXT_TX_LOOPBACK_SETUP_E                           = 396  ,
+  WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E                      = 398  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E      = 400  ,
+  WIFI_N_EXT_TX_WUR_DATA_E                                 = 402  ,
+  WIFI_N_EXT_RX_PPDU_END_MIDDLE_E                          = 404  ,
+  WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E            = 406  ,
+  WIFI_N_EXT_SRP_INFO_E                                    = 408  ,
+  WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E                     = 410  ,
+  WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E                        = 412  ,
+  WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E                       = 414  ,
+  WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E                   = 416  ,
+  WIFI_N_EXT_LMR_TX_END_E                                  = 418  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E       = 420  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E   = 422  ,
+  WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E                    = 424  ,
+  WIFI_N_EXT_MACTX___RESERVED_G_0013                       = 426  ,
+  WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E                          = 428  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E                   = 430  ,
+  WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E                       = 432  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E                   = 434  ,
+  WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E                 = 436  ,
+  WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E                      = 438  ,
+  WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E                    = 440  ,
+  WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E                    = 442  ,
+  WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E                         = 444  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E         = 446  ,
+  WIFI_N_EXT_LMR_MPDU_START_E                              = 448  ,
+  WIFI_N_EXT_LMR_MPDU_END_E                                = 450  ,
+  WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E                      = 452  ,
+  WIFI_N_EXT_TQM_ACKED_1K_MPDU_E                           = 454  ,
+  WIFI_N_EXT_PHYRX_LOCATION_E                              = 456  ,
+  WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E                      = 458  ,
+  WIFI_N_EXT_MLO_TX_REQ_MU_E                               = 460  ,
+  WIFI_N_EXT_MLO_RX_NOTIFICATION_E                         = 462  ,
+  WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E                       = 464  ,
+  WIFI_N_EXT_MLO_TS_SYNC_MSG_E                             = 466  ,
+  WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E                        = 468  ,
+  WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E                         = 470  ,
+  WIFI_N_EXT_TX_FRAG_STATE_E                               = 472  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E       = 474  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E                       = 476  ,
+  WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E              = 478  ,
+  WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E               = 480  ,
+  WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E                    = 482  ,
+  WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E                  = 484  ,
+  WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E             = 486  ,
+  WIFI_N_EXT_PHYRX___RESERVED_G_0014                       = 488  ,
+  WIFI_N_EXT_PHYTX___RESERVED_G_0014                       = 490  ,
+  WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E                        = 492  ,
+  WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E                        = 494  ,
+  WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E                         = 496  ,
+  WIFI_N_EXT_OVERWRITE_RESP_START_E                        = 498  ,
+  WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E                   = 500  ,
+  WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E                   = 502  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E                = 504  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E              = 506  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E                       = 508  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E   = 510  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E             = 512  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E                        = 514  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_USER_E                          = 516  ,
+  WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E                = 518  ,
+  WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E               = 520  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E               = 522  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E                 = 524  ,
+  WIFI_N_EXT_WSI_DIRECT_MESSAGE_E                          = 526  ,
+  WIFI_N_EXT_MACTX_EMLSR_SWITCH_E                          = 528  ,
+  WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E                      = 530  ,
+  WIFI_N_EXT_EAD_COMMAND_E                                 = 532  ,
+  WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E                = 534  ,
+  WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E                 = 536  ,
+  WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E                = 538  ,
+  WIFI_N_EXT_TPI_MPDU_CONTINUATION_E                       = 540  ,
+  WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E                       = 542  ,
+  WIFI_N_EXT_TPI_STATUS_E                                  = 544  ,
+  WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E                        = 546  ,
+  WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E                   = 548  ,
+  WIFI_N_EXT_RPI_STATUS_E                                  = 550  ,
+  WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E                        = 552  ,
+  WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E                   = 554  ,
+  WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E                   = 556  ,
+  WIFI_N_EXT_TCC_STATUS_E                                  = 558  ,
+  WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E                        = 560  ,
+  WIFI_N_EXT_TCC_SCHEDULER_CMD_E                           = 562  ,
+  WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E             = 564  ,
+  WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E                 = 566  ,
+  WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E                 = 568  ,
+  WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E                  = 570  ,
+  WIFI_N_EXT_TCC_FES_END_MESSAGE_E                         = 572  ,
+  WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E                = 574  ,
+  WIFI_N_EXT_EAD_MSDU_STATUS_START_E                       = 576  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E                        = 578  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E                     = 580  ,
+  WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E                       = 582  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E      = 584  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E                    = 586  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E                      = 588  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E                     = 590  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E                      = 592  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E                      = 594  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_1_E                           = 596  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_3_E                           = 598  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_5_E                           = 600  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_7_E                           = 602  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_9_E                           = 604  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_11_E                          = 606  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_13_E                          = 608  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_15_E                          = 610  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_17_E                          = 612  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_19_E                          = 614  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_21_E                          = 616  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_23_E                          = 618  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_25_E                          = 620  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_27_E                          = 622  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_29_E                          = 624  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_31_E                          = 626  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_33_E                          = 628  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_35_E                          = 630  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_37_E                          = 632  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_39_E                          = 634  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_41_E                          = 636  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_43_E                          = 638  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_45_E                          = 640  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_47_E                          = 642  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_49_E                          = 644  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_51_E                          = 646  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_53_E                          = 648  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_55_E                          = 650  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_57_E                          = 652  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_59_E                          = 654  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_61_E                          = 656  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_63_E                          = 658  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_65_E                          = 660  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_67_E                          = 662  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_69_E                          = 664  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_71_E                          = 666  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_73_E                          = 668  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_75_E                          = 670  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_77_E                          = 672  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_79_E                          = 674  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_81_E                          = 676  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_83_E                          = 678  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_85_E                          = 680  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_87_E                          = 682  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_89_E                          = 684  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_91_E                          = 686  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_93_E                          = 688  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_95_E                          = 690  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_97_E                          = 692  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_99_E                          = 694  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_101_E                         = 696  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_103_E                         = 698  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_105_E                         = 700  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_107_E                         = 702  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_109_E                         = 704  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_111_E                         = 706  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_113_E                         = 708  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_115_E                         = 710  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_117_E                         = 712  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_119_E                         = 714  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_121_E                         = 716  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_123_E                         = 718  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_125_E                         = 720  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_127_E                         = 722  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_129_E                         = 724  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_131_E                         = 726  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_133_E                         = 728  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_135_E                         = 730  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_137_E                         = 732  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_139_E                         = 734  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_141_E                         = 736  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_143_E                         = 738  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_145_E                         = 740  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_147_E                         = 742  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_149_E                         = 744  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_151_E                         = 746  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_153_E                         = 748  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_155_E                         = 750  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_157_E                         = 752  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_159_E                         = 754  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_161_E                         = 756  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_163_E                         = 758  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_165_E                         = 760  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_167_E                         = 762  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_169_E                         = 764  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_171_E                         = 766  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_173_E                         = 768  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_175_E                         = 770  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_177_E                         = 772  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_179_E                         = 774  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_181_E                         = 776  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_183_E                         = 778  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_185_E                         = 780  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_187_E                         = 782  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_189_E                         = 784  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_191_E                         = 786  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_193_E                         = 788  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_195_E                         = 790  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_197_E                         = 792  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_199_E                         = 794  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_201_E                         = 796  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_203_E                         = 798  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_205_E                         = 800  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_207_E                         = 802  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_209_E                         = 804  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_211_E                         = 806  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_213_E                         = 808  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_215_E                         = 810  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_217_E                         = 812  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_219_E                         = 814  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_221_E                         = 816  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_223_E                         = 818  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_225_E                         = 820  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_227_E                         = 822  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_229_E                         = 824  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_231_E                         = 826  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_233_E                         = 828  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_235_E                         = 830  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_237_E                         = 832  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_239_E                         = 834  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_241_E                         = 836  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_243_E                         = 838  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_245_E                         = 840  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_247_E                         = 842  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_249_E                         = 844  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_251_E                         = 846  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_253_E                         = 848  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_255_E                         = 850  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_257_E                         = 852  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_259_E                         = 854  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_261_E                         = 856  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_263_E                         = 858  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_265_E                         = 860  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_267_E                         = 862  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_269_E                         = 864  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_271_E                         = 866  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_273_E                         = 868  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_275_E                         = 870  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_277_E                         = 872  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_279_E                         = 874  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_281_E                         = 876  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_283_E                         = 878  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_285_E                         = 880  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_287_E                         = 882  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_289_E                         = 884  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_291_E                         = 886  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_293_E                         = 888  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_295_E                         = 890  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_297_E                         = 892  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_299_E                         = 894  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_301_E                         = 896  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_303_E                         = 898  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_305_E                         = 900  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_307_E                         = 902  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_309_E                         = 904  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_311_E                         = 906  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_313_E                         = 908  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_315_E                         = 910  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_317_E                         = 912  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_319_E                         = 914  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_321_E                         = 916  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_323_E                         = 918  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_325_E                         = 920  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_327_E                         = 922  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_329_E                         = 924  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_331_E                         = 926  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_333_E                         = 928  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_335_E                         = 930  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_337_E                         = 932  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_339_E                         = 934  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_341_E                         = 936  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_343_E                         = 938  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_345_E                         = 940  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_347_E                         = 942  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_349_E                         = 944  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_351_E                         = 946  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_353_E                         = 948  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_355_E                         = 950  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_357_E                         = 952  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_359_E                         = 954  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_361_E                         = 956  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_363_E                         = 958  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_365_E                         = 960  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_367_E                         = 962  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_369_E                         = 964  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_371_E                         = 966  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_373_E                         = 968  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_375_E                         = 970  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_377_E                         = 972  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_379_E                         = 974  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_381_E                         = 976  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_383_E                         = 978  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_385_E                         = 980  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_387_E                         = 982  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_389_E                         = 984  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_391_E                         = 986  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_393_E                         = 988  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_395_E                         = 990  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_397_E                         = 992  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_399_E                         = 994  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_401_E                         = 996  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_403_E                         = 998  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_405_E                         = 1000  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_407_E                         = 1002  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_409_E                         = 1004  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_411_E                         = 1006  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_413_E                         = 1008  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_415_E                         = 1010  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_417_E                         = 1012  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_419_E                         = 1014  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_421_E                         = 1016  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_423_E                         = 1018  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_425_E                         = 1020
+} non_ext_tlv_tag_def__e;
+
+#endif
diff --git a/hw/fig/v1/tqm2sw_completion_ring.h b/hw/fig/v1/tqm2sw_completion_ring.h
new file mode 100644
index 000000000000..f67deea1f6a1
--- /dev/null
+++ b/hw/fig/v1/tqm2sw_completion_ring.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TQM2SW_COMPLETION_RING_H_
+#define _TQM2SW_COMPLETION_RING_H_
+
+#include "tx_rate_stats_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8
+
+struct tqm2sw_completion_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      cookie_conversion_status                                :  1,
+                      tqm_completion_error                                    :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t tqm_completion_error                                    :  1,
+                      cookie_conversion_status                                :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB                            0
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB                            2
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK                           0x00000007
+
+#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET                                      0x00000008
+#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK                                        0x00000008
+
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET                                   0x00000008
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB                                      4
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB                                      5
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK                                     0x00000030
+
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET                           0x00000008
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB                              6
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB                              8
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK                             0x000001c0
+
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB                            9
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB                            12
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK                           0x00001e00
+
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB                               13
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB                               16
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK                              0x0001e000
+
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK                              0x00020000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB                            18
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB                            29
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK                           0x3ffc0000
+
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET                      0x00000008
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK                        0x40000000
+
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET                          0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK                            0x80000000
+
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET                             0x0000000c
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB                                0
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB                                23
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK                               0x00ffffff
+
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET                                0x0000000c
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB                                   24
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB                                   30
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK                                  0x7f000000
+
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET                      0x0000000c
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK                        0x80000000
+
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET                                0x00000010
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB                                   0
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB                                   7
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK                                  0x000000ff
+
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET                                    0x00000010
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK                                      0x00000100
+
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET                                     0x00000010
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK                                       0x00000200
+
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET                            0x00000010
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB                               10
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB                               12
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK                              0x00001c00
+
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET                              0x00000010
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB                                 13
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB                                 31
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK                                0xffffe000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET        0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK          0x00000001
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB                        1
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB                        3
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK                       0x0000000e
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET               0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                  4
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                  7
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                 0x000000f0
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK                     0x00000100
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK                     0x00000200
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB                       10
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB                       11
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK                      0x00000c00
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB                       12
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB                       16
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK                      0x0001f000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET         0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB            17
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB            19
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK           0x000e0000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET              0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                0x00100000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB                        21
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB                        24
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK                       0x01e00000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB                        25
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB                        28
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK                       0x1e000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB                       29
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB                       31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK                      0xe0000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET           0x00000018
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB              0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB              31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK             0xffffffff
+
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET                                    0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB                                       0
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB                                       15
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK                                      0x0000ffff
+
+#define TQM2SW_COMPLETION_RING_TID_OFFSET                                           0x0000001c
+#define TQM2SW_COMPLETION_RING_TID_LSB                                              16
+#define TQM2SW_COMPLETION_RING_TID_MSB                                              19
+#define TQM2SW_COMPLETION_RING_TID_MASK                                             0x000f0000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET                        0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB                           20
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB                           27
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK                          0x0ff00000
+
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET                                 0x0000001c
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB                                    28
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB                                    31
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK                                   0xf0000000
+
+#endif
diff --git a/hw/fig/v1/tx_cbf_info.h b/hw/fig/v1/tx_cbf_info.h
new file mode 100644
index 000000000000..fed064ce95a8
--- /dev/null
+++ b/hw/fig/v1/tx_cbf_info.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_CBF_INFO_H_
+#define _TX_CBF_INFO_H_
+
+#define NUM_OF_DWORDS_TX_CBF_INFO 16
+
+#define NUM_OF_QWORDS_TX_CBF_INFO 8
+
+struct tx_cbf_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sw_peer_id                                              : 16,
+                      pre_cbf_duration                                        : 16;
+             uint32_t brpoll_info_valid                                       :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      bandwidth                                               :  3,
+                      brpoll_info                                             :  8,
+                      cbf_response_table_base_index                           :  8,
+                      peer_index                                              :  3,
+                      pkt_type                                                :  4,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t trigger_brpoll_common_info_15_0                         : 16,
+                      trigger_brpoll_common_info_31_16                        : 16;
+             uint32_t trigger_brpoll_user_info_15_0                           : 16,
+                      trigger_brpoll_user_info_31_16                          : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      sta_partial_aid                                         : 11,
+                      __reserved_g_0035                                                 :  1,
+                      reserved_8a                                             :  3,
+                      cbf_resp_pwr_mgmt                                       :  1;
+             uint32_t group_id                                                :  6,
+                      rssi_comb                                               :  8,
+                      reserved_9a                                             :  2,
+                      vht_ndpa_sta_info                                       : 16;
+             uint32_t he_eht_sta_info_15_0                                    : 16,
+                      he_eht_sta_info_31_16                                   : 16;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_11a                                            :  8;
+             uint32_t sw_response_frame_length                                : 16,
+                      sw_response_tlv_from_crypto                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2,
+                      __reserved_g_0022                                                 :  1,
+                      secure                                                  :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      emlsr_main_tlv_if                                       :  1,
+                      reserved_12a                                            :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      npda_info_11be_valid                                    :  1,
+                      eht_duplicate_mode                                      :  2,
+                      reserved_13a                                            : 11;
+             uint32_t eht_sta_info_39_32                                      :  8,
+                      unassociated___reserved_g_0022_peer                               :  1,
+                      reserved_14a                                            : 23;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t pre_cbf_duration                                        : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      pkt_type                                                :  4,
+                      peer_index                                              :  3,
+                      cbf_response_table_base_index                           :  8,
+                      brpoll_info                                             :  8,
+                      bandwidth                                               :  3,
+                      dot11ax_su_extended                                     :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      brpoll_info_valid                                       :  1;
+             uint32_t trigger_brpoll_common_info_31_16                        : 16,
+                      trigger_brpoll_common_info_15_0                         : 16;
+             uint32_t trigger_brpoll_user_info_31_16                          : 16,
+                      trigger_brpoll_user_info_15_0                           : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t cbf_resp_pwr_mgmt                                       :  1,
+                      reserved_8a                                             :  3,
+                      __reserved_g_0035                                                 :  1,
+                      sta_partial_aid                                         : 11,
+                      addr3_47_32                                             : 16;
+             uint32_t vht_ndpa_sta_info                                       : 16,
+                      reserved_9a                                             :  2,
+                      rssi_comb                                               :  8,
+                      group_id                                                :  6;
+             uint32_t he_eht_sta_info_31_16                                   : 16,
+                      he_eht_sta_info_15_0                                    : 16;
+             uint32_t reserved_11a                                            :  8,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_12a                                            :  1,
+                      emlsr_main_tlv_if                                       :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      secure                                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      sw_response_frame_length                                : 16;
+             uint32_t reserved_13a                                            : 11,
+                      eht_duplicate_mode                                      :  2,
+                      npda_info_11be_valid                                    :  1,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_14a                                            : 23,
+                      unassociated___reserved_g_0022_peer                               :  1,
+                      eht_sta_info_39_32                                      :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_CBF_INFO_SW_PEER_ID_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_SW_PEER_ID_LSB                                                  0
+#define TX_CBF_INFO_SW_PEER_ID_MSB                                                  15
+#define TX_CBF_INFO_SW_PEER_ID_MASK                                                 0x000000000000ffff
+
+#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET                                         0x0000000000000000
+#define TX_CBF_INFO_PRE_CBF_DURATION_LSB                                            16
+#define TX_CBF_INFO_PRE_CBF_DURATION_MSB                                            31
+#define TX_CBF_INFO_PRE_CBF_DURATION_MASK                                           0x00000000ffff0000
+
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET                                        0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK                                          0x0000000100000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET                                0x0000000000000000
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK                                  0x0000000200000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK                                       0x0000000400000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK                                       0x0000000800000000
+
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET                                      0x0000000000000000
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK                                        0x0000001000000000
+
+#define TX_CBF_INFO_BANDWIDTH_OFFSET                                                0x0000000000000000
+#define TX_CBF_INFO_BANDWIDTH_LSB                                                   37
+#define TX_CBF_INFO_BANDWIDTH_MSB                                                   39
+#define TX_CBF_INFO_BANDWIDTH_MASK                                                  0x000000e000000000
+
+#define TX_CBF_INFO_BRPOLL_INFO_OFFSET                                              0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_LSB                                                 40
+#define TX_CBF_INFO_BRPOLL_INFO_MSB                                                 47
+#define TX_CBF_INFO_BRPOLL_INFO_MASK                                                0x0000ff0000000000
+
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET                            0x0000000000000000
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB                               48
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB                               55
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK                              0x00ff000000000000
+
+#define TX_CBF_INFO_PEER_INDEX_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_PEER_INDEX_LSB                                                  56
+#define TX_CBF_INFO_PEER_INDEX_MSB                                                  58
+#define TX_CBF_INFO_PEER_INDEX_MASK                                                 0x0700000000000000
+
+#define TX_CBF_INFO_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_CBF_INFO_PKT_TYPE_LSB                                                    59
+#define TX_CBF_INFO_PKT_TYPE_MSB                                                    62
+#define TX_CBF_INFO_PKT_TYPE_MASK                                                   0x7800000000000000
+
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET                                   0x0000000000000000
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK                                     0x8000000000000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET                          0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB                             0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB                             15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK                            0x000000000000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET                         0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB                            16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB                            31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK                           0x00000000ffff0000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET                            0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB                               32
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB                               47
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK                              0x0000ffff00000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET                           0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB                              48
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB                              63
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK                             0xffff000000000000
+
+#define TX_CBF_INFO_ADDR1_31_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR1_31_0_LSB                                                  0
+#define TX_CBF_INFO_ADDR1_31_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR1_31_0_MASK                                                 0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR1_47_32_OFFSET                                              0x0000000000000010
+#define TX_CBF_INFO_ADDR1_47_32_LSB                                                 32
+#define TX_CBF_INFO_ADDR1_47_32_MSB                                                 47
+#define TX_CBF_INFO_ADDR1_47_32_MASK                                                0x0000ffff00000000
+
+#define TX_CBF_INFO_ADDR2_15_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR2_15_0_LSB                                                  48
+#define TX_CBF_INFO_ADDR2_15_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR2_15_0_MASK                                                 0xffff000000000000
+
+#define TX_CBF_INFO_ADDR2_47_16_OFFSET                                              0x0000000000000018
+#define TX_CBF_INFO_ADDR2_47_16_LSB                                                 0
+#define TX_CBF_INFO_ADDR2_47_16_MSB                                                 31
+#define TX_CBF_INFO_ADDR2_47_16_MASK                                                0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR3_31_0_OFFSET                                               0x0000000000000018
+#define TX_CBF_INFO_ADDR3_31_0_LSB                                                  32
+#define TX_CBF_INFO_ADDR3_31_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR3_31_0_MASK                                                 0xffffffff00000000
+
+#define TX_CBF_INFO_ADDR3_47_32_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_ADDR3_47_32_LSB                                                 0
+#define TX_CBF_INFO_ADDR3_47_32_MSB                                                 15
+#define TX_CBF_INFO_ADDR3_47_32_MASK                                                0x000000000000ffff
+
+#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET                                          0x0000000000000020
+#define TX_CBF_INFO_STA_PARTIAL_AID_LSB                                             16
+#define TX_CBF_INFO_STA_PARTIAL_AID_MSB                                             26
+#define TX_CBF_INFO_STA_PARTIAL_AID_MASK                                            0x0000000007ff0000
+
+#define TX_CBF_INFO_RESERVED_8A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_8A_LSB                                                 28
+#define TX_CBF_INFO_RESERVED_8A_MSB                                                 30
+#define TX_CBF_INFO_RESERVED_8A_MASK                                                0x0000000070000000
+
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK                                          0x0000000080000000
+
+#define TX_CBF_INFO_GROUP_ID_OFFSET                                                 0x0000000000000020
+#define TX_CBF_INFO_GROUP_ID_LSB                                                    32
+#define TX_CBF_INFO_GROUP_ID_MSB                                                    37
+#define TX_CBF_INFO_GROUP_ID_MASK                                                   0x0000003f00000000
+
+#define TX_CBF_INFO_RSSI_COMB_OFFSET                                                0x0000000000000020
+#define TX_CBF_INFO_RSSI_COMB_LSB                                                   38
+#define TX_CBF_INFO_RSSI_COMB_MSB                                                   45
+#define TX_CBF_INFO_RSSI_COMB_MASK                                                  0x00003fc000000000
+
+#define TX_CBF_INFO_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_9A_LSB                                                 46
+#define TX_CBF_INFO_RESERVED_9A_MSB                                                 47
+#define TX_CBF_INFO_RESERVED_9A_MASK                                                0x0000c00000000000
+
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB                                           48
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB                                           63
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK                                          0xffff000000000000
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB                                        0
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB                                        15
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK                                       0x000000000000ffff
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET                                    0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB                                       16
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB                                       31
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK                                      0x00000000ffff0000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK                         0x0000000100000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                              0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                                0x0000000200000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET                            0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                               34
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                               39
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                              0x000000fc00000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET                           0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                              40
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                              43
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK                             0x00000f0000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                                 0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                                    44
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                                    45
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                                   0x0000300000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                                0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                                   46
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                                   47
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                                  0x0000c00000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET                                  0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK                                    0x0001000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK                                       0x0002000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET                      0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK                        0x0004000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET                             0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                                51
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                                54
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                               0x0078000000000000
+
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET                                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK                                         0x0080000000000000
+
+#define TX_CBF_INFO_RESERVED_11A_OFFSET                                             0x0000000000000028
+#define TX_CBF_INFO_RESERVED_11A_LSB                                                56
+#define TX_CBF_INFO_RESERVED_11A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_11A_MASK                                               0xff00000000000000
+
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                                 0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                                    0
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                                    15
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                                   0x000000000000ffff
+
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                              0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                                0x0000000000010000
+
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                                   0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK                                     0x0000000000020000
+
+#define TX_CBF_INFO_WAIT_SIFS_OFFSET                                                0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_LSB                                                   18
+#define TX_CBF_INFO_WAIT_SIFS_MSB                                                   19
+#define TX_CBF_INFO_WAIT_SIFS_MASK                                                  0x00000000000c0000
+
+#define TX_CBF_INFO_SECURE_OFFSET                                                   0x0000000000000030
+#define TX_CBF_INFO_SECURE_LSB                                                      21
+#define TX_CBF_INFO_SECURE_MSB                                                      21
+#define TX_CBF_INFO_SECURE_MASK                                                     0x0000000000200000
+
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET                                        0x0000000000000030
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK                                          0x0000000001000000
+
+#define TX_CBF_INFO_RESERVED_12A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_12A_LSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MASK                                               0x0000000002000000
+
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                          0x0000000000000030
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                             26
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                             31
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                            0x00000000fc000000
+
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                                  0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                                     32
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                                     47
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                                    0x0000ffff00000000
+
+#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET                                         0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK                                           0x0001000000000000
+
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK                                         0x0002000000000000
+
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET                                     0x0000000000000030
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK                                       0x0004000000000000
+
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB                                          51
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB                                          52
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK                                         0x0018000000000000
+
+#define TX_CBF_INFO_RESERVED_13A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_13A_LSB                                                53
+#define TX_CBF_INFO_RESERVED_13A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_13A_MASK                                               0xffe0000000000000
+
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET                                       0x0000000000000038
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB                                          0
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB                                          7
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK                                         0x00000000000000ff
+
+#define TX_CBF_INFO_RESERVED_14A_OFFSET                                             0x0000000000000038
+#define TX_CBF_INFO_RESERVED_14A_LSB                                                9
+#define TX_CBF_INFO_RESERVED_14A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_14A_MASK                                               0x00000000fffffe00
+
+#define TX_CBF_INFO_TLV64_PADDING_OFFSET                                            0x0000000000000038
+#define TX_CBF_INFO_TLV64_PADDING_LSB                                               32
+#define TX_CBF_INFO_TLV64_PADDING_MSB                                               63
+#define TX_CBF_INFO_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_setup.h b/hw/fig/v1/tx_fes_setup.h
new file mode 100644
index 000000000000..24151f70fecd
--- /dev/null
+++ b/hw/fig/v1/tx_fes_setup.h
@@ -0,0 +1,550 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_SETUP_H_
+#define _TX_FES_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_FES_SETUP 10
+
+#define NUM_OF_QWORDS_TX_FES_SETUP 5
+
+struct tx_fes_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t fes_in_11ax_trigger_response_config                     :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      __reserved_g_0022                                                 :  1,
+                      expect_i2r_lmr                                          :  1,
+                      transmit_start_reason                                   :  3,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      puncture_from_all_allowed_modes                         :  1,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      number_of_users                                         :  6,
+                      mu_type                                                 :  1,
+                      ofdma_triggered_response                                :  1,
+                      response_to_response_cmd                                :  1;
+             uint32_t schedule_try                                            :  4,
+                      reserved_2a                                             :  1,
+                      subband_antenna_selection_en                            :  1,
+                      txbf                                                    :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      ignore_bw_available                                     :  1,
+                      ignore_tbtt                                             :  1,
+                      static_bandwidth                                        :  3,
+                      set_txop_duration_all_ones                              :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      bw_restricted_frames_embedded                           :  1,
+                      ast_index                                               : 16;
+             uint32_t cv_id                                                   :  8,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      rxpcu_setup_complete_present                            :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      mu_ndp                                                  :  1,
+                      bf_type                                                 :  2,
+                      cbf_nc_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nr_index                                            :  3,
+                      secure___reserved_g_0022_ista                                     :  1,
+                      ndpa                                                    :  1,
+                      wait_sifs                                               :  2,
+                      cbf_feedback_type_mask                                  :  1,
+                      cbf_feedback_type                                       :  1;
+             uint32_t cbf_sounding_token                                      :  6,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_bw_mask                                             :  1,
+                      cbf_bw                                                  :  3,
+                      use_static_bw                                           :  1,
+                      coex_nack_count                                         :  5,
+                      sch_tx_burst_ongoing                                    :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      ndp_frame                                               :  3,
+                      optimal_bw_retry_count                                  :  4,
+                      fes_continuation_ratio_threshold                        :  5;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t tb___reserved_g_0022                                              :  1,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      min_cts2self_count                                      :  4,
+                      max_cts2self_count                                      :  4,
+                      wifi_radar_enable                                       :  1,
+                      reserved_6a                                             :  1,
+                      wait_for_chksum_done                                    :  1,
+                      txrx_self_test_enable                                   :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      secure___reserved_g_0022_rsta                                     :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      last_command_in_burst                                   :  1,
+                      retain_peer_blackout_details                            :  1,
+                      enable_hw_qos_null                                      :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t monitor_override_sta_36_32                              :  5,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      __reserved_g_0035                                                 :  1,
+                      secure___reserved_g_0035_smr                                      :  1,
+                      __reserved_g_0035_type                                            :  2,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      reserved_8a                                             : 18;
+             uint32_t fw2sw_info                                              : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t response_to_response_cmd                                :  1,
+                      ofdma_triggered_response                                :  1,
+                      mu_type                                                 :  1,
+                      number_of_users                                         :  6,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      puncture_from_all_allowed_modes                         :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      transmit_start_reason                                   :  3,
+                      expect_i2r_lmr                                          :  1,
+                      __reserved_g_0022                                                 :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      fes_in_11ax_trigger_response_config                     :  1;
+             uint32_t ast_index                                               : 16,
+                      bw_restricted_frames_embedded                           :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      set_txop_duration_all_ones                              :  1,
+                      static_bandwidth                                        :  3,
+                      ignore_tbtt                                             :  1,
+                      ignore_bw_available                                     :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      txbf                                                    :  1,
+                      subband_antenna_selection_en                            :  1,
+                      reserved_2a                                             :  1,
+                      schedule_try                                            :  4;
+             uint32_t cbf_feedback_type                                       :  1,
+                      cbf_feedback_type_mask                                  :  1,
+                      wait_sifs                                               :  2,
+                      ndpa                                                    :  1,
+                      secure___reserved_g_0022_ista                                     :  1,
+                      cbf_nr_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nc_index_mask                                       :  1,
+                      bf_type                                                 :  2,
+                      mu_ndp                                                  :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      rxpcu_setup_complete_present                            :  1,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      cv_id                                                   :  8;
+             uint32_t fes_continuation_ratio_threshold                        :  5,
+                      optimal_bw_retry_count                                  :  4,
+                      ndp_frame                                               :  3,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_nack_count                                         :  5,
+                      use_static_bw                                           :  1,
+                      cbf_bw                                                  :  3,
+                      cbf_bw_mask                                             :  1,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_sounding_token                                      :  6;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t enable_hw_qos_null                                      :  1,
+                      retain_peer_blackout_details                            :  1,
+                      last_command_in_burst                                   :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      secure___reserved_g_0022_rsta                                     :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      txrx_self_test_enable                                   :  1,
+                      wait_for_chksum_done                                    :  1,
+                      reserved_6a                                             :  1,
+                      wifi_radar_enable                                       :  1,
+                      max_cts2self_count                                      :  4,
+                      min_cts2self_count                                      :  4,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      tb___reserved_g_0022                                              :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t reserved_8a                                             : 18,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      __reserved_g_0035_type                                            :  2,
+                      secure___reserved_g_0035_smr                                      :  1,
+                      __reserved_g_0035                                                 :  1,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      monitor_override_sta_36_32                              :  5;
+             uint32_t fw2sw_info                                              : 32;
+#endif
+};
+
+#define TX_FES_SETUP_SCHEDULE_ID_OFFSET                                             0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_ID_LSB                                                0
+#define TX_FES_SETUP_SCHEDULE_ID_MSB                                                31
+#define TX_FES_SETUP_SCHEDULE_ID_MASK                                               0x00000000ffffffff
+
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                     0x0000000000000000
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                       0x0000000100000000
+
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000000
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB                             33
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB                             36
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK                            0x0000001e00000000
+
+#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET                                          0x0000000000000000
+#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK                                            0x0000004000000000
+
+#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET                                   0x0000000000000000
+#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB                                      39
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB                                      41
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK                                     0x0000038000000000
+
+#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK                                          0x0000040000000000
+
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK                                  0x0000080000000000
+
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                           0x0000100000000000
+
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET                               0x0000000000000000
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK                                 0x0000200000000000
+
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                           0x0000000000000000
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                             0x0000400000000000
+
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK                           0x0000800000000000
+
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET                                    0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB                                       48
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB                                       52
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK                                      0x001f000000000000
+
+#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_FES_CONTROL_MODE_LSB                                           53
+#define TX_FES_SETUP_FES_CONTROL_MODE_MSB                                           54
+#define TX_FES_SETUP_FES_CONTROL_MODE_MASK                                          0x0060000000000000
+
+#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET                                         0x0000000000000000
+#define TX_FES_SETUP_NUMBER_OF_USERS_LSB                                            55
+#define TX_FES_SETUP_NUMBER_OF_USERS_MSB                                            60
+#define TX_FES_SETUP_NUMBER_OF_USERS_MASK                                           0x1f80000000000000
+
+#define TX_FES_SETUP_MU_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_FES_SETUP_MU_TYPE_LSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MASK                                                   0x2000000000000000
+
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK                                  0x4000000000000000
+
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK                                  0x8000000000000000
+
+#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_SCHEDULE_TRY_LSB                                               0
+#define TX_FES_SETUP_SCHEDULE_TRY_MSB                                               3
+#define TX_FES_SETUP_SCHEDULE_TRY_MASK                                              0x000000000000000f
+
+#define TX_FES_SETUP_RESERVED_2A_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_RESERVED_2A_LSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MASK                                               0x0000000000000010
+
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK                              0x0000000000000020
+
+#define TX_FES_SETUP_TXBF_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_TXBF_LSB                                                       6
+#define TX_FES_SETUP_TXBF_MSB                                                       6
+#define TX_FES_SETUP_TXBF_MASK                                                      0x0000000000000040
+
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK                              0x0000000000000080
+
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET                                     0x0000000000000008
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK                                       0x0000000000000100
+
+#define TX_FES_SETUP_IGNORE_TBTT_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_IGNORE_TBTT_LSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MASK                                               0x0000000000000200
+
+#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET                                        0x0000000000000008
+#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB                                           10
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB                                           12
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK                                          0x0000000000001c00
+
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET                              0x0000000000000008
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK                                0x0000000000002000
+
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK                              0x0000000000004000
+
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK                             0x0000000000008000
+
+#define TX_FES_SETUP_AST_INDEX_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_AST_INDEX_LSB                                                  16
+#define TX_FES_SETUP_AST_INDEX_MSB                                                  31
+#define TX_FES_SETUP_AST_INDEX_MASK                                                 0x00000000ffff0000
+
+#define TX_FES_SETUP_CV_ID_OFFSET                                                   0x0000000000000008
+#define TX_FES_SETUP_CV_ID_LSB                                                      32
+#define TX_FES_SETUP_CV_ID_MSB                                                      39
+#define TX_FES_SETUP_CV_ID_MASK                                                     0x000000ff00000000
+
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET                        0x0000000000000008
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB                           40
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB                           41
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK                          0x0000030000000000
+
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK                              0x0000040000000000
+
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB                              43
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB                              46
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK                             0x0000780000000000
+
+#define TX_FES_SETUP_MU_NDP_OFFSET                                                  0x0000000000000008
+#define TX_FES_SETUP_MU_NDP_LSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MASK                                                    0x0000800000000000
+
+#define TX_FES_SETUP_BF_TYPE_OFFSET                                                 0x0000000000000008
+#define TX_FES_SETUP_BF_TYPE_LSB                                                    48
+#define TX_FES_SETUP_BF_TYPE_MSB                                                    49
+#define TX_FES_SETUP_BF_TYPE_MASK                                                   0x0003000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK                                         0x0004000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_LSB                                               51
+#define TX_FES_SETUP_CBF_NC_INDEX_MSB                                               53
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK                                              0x0038000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK                                         0x0040000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_LSB                                               55
+#define TX_FES_SETUP_CBF_NR_INDEX_MSB                                               57
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK                                              0x0380000000000000
+
+#define TX_FES_SETUP_NDPA_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_NDPA_LSB                                                       59
+#define TX_FES_SETUP_NDPA_MSB                                                       59
+#define TX_FES_SETUP_NDPA_MASK                                                      0x0800000000000000
+
+#define TX_FES_SETUP_WAIT_SIFS_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_WAIT_SIFS_LSB                                                  60
+#define TX_FES_SETUP_WAIT_SIFS_MSB                                                  61
+#define TX_FES_SETUP_WAIT_SIFS_MASK                                                 0x3000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET                                  0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK                                    0x4000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK                                         0x8000000000000000
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET                                      0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB                                         0
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB                                         5
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK                                        0x000000000000003f
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET                                 0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK                                   0x0000000000000040
+
+#define TX_FES_SETUP_CBF_BW_MASK_OFFSET                                             0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_MASK_LSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MASK                                               0x0000000000000080
+
+#define TX_FES_SETUP_CBF_BW_OFFSET                                                  0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_LSB                                                     8
+#define TX_FES_SETUP_CBF_BW_MSB                                                     10
+#define TX_FES_SETUP_CBF_BW_MASK                                                    0x0000000000000700
+
+#define TX_FES_SETUP_USE_STATIC_BW_OFFSET                                           0x0000000000000010
+#define TX_FES_SETUP_USE_STATIC_BW_LSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MASK                                             0x0000000000000800
+
+#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET                                         0x0000000000000010
+#define TX_FES_SETUP_COEX_NACK_COUNT_LSB                                            12
+#define TX_FES_SETUP_COEX_NACK_COUNT_MSB                                            16
+#define TX_FES_SETUP_COEX_NACK_COUNT_MASK                                           0x000000000001f000
+
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET                                    0x0000000000000010
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK                                      0x0000000000020000
+
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET                           0x0000000000000010
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK                             0x0000000000040000
+
+#define TX_FES_SETUP_NDP_FRAME_OFFSET                                               0x0000000000000010
+#define TX_FES_SETUP_NDP_FRAME_LSB                                                  20
+#define TX_FES_SETUP_NDP_FRAME_MSB                                                  22
+#define TX_FES_SETUP_NDP_FRAME_MASK                                                 0x0000000000700000
+
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET                                  0x0000000000000010
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB                                     23
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB                                     26
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK                                    0x0000000007800000
+
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET                        0x0000000000000010
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB                           27
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB                           31
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK                          0x00000000f8000000
+
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET                                     0x0000000000000010
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB                                        32
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB                                        63
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK                                       0xffffffff00000000
+
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB                                         5
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB                                         8
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK                                        0x00000000000001e0
+
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB                                         9
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB                                         12
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK                                        0x0000000000001e00
+
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET                                       0x0000000000000018
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK                                         0x0000000000002000
+
+#define TX_FES_SETUP_RESERVED_6A_OFFSET                                             0x0000000000000018
+#define TX_FES_SETUP_RESERVED_6A_LSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MASK                                               0x0000000000004000
+
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK                                      0x0000000000008000
+
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK                                     0x0000000000010000
+
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET                                     0x0000000000000018
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK                                       0x0000000000020000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK                                      0x0000000000080000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET                                  0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK                                    0x0000000000100000
+
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB                               21
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB                               28
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK                              0x000000001fe00000
+
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK                                     0x0000000020000000
+
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK                              0x0000000040000000
+
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK                                        0x0000000080000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET                               0x0000000000000018
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB                                  32
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB                                  63
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK                                 0xffffffff00000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET                              0x0000000000000020
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB                                 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB                                 4
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK                                0x000000000000001f
+
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET                         0x0000000000000020
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK                           0x0000000000000020
+
+#define TX_FES_SETUP_RESERVED_8A_OFFSET                                             0x0000000000000020
+#define TX_FES_SETUP_RESERVED_8A_LSB                                                14
+#define TX_FES_SETUP_RESERVED_8A_MSB                                                31
+#define TX_FES_SETUP_RESERVED_8A_MASK                                               0x00000000ffffc000
+
+#define TX_FES_SETUP_FW2SW_INFO_OFFSET                                              0x0000000000000020
+#define TX_FES_SETUP_FW2SW_INFO_LSB                                                 32
+#define TX_FES_SETUP_FW2SW_INFO_MSB                                                 63
+#define TX_FES_SETUP_FW2SW_INFO_MASK                                                0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_1k_ba.h b/hw/fig/v1/tx_fes_status_1k_ba.h
new file mode 100644
index 000000000000..4409dc03ac03
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_1k_ba.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_1K_BA_H_
+#define _TX_FES_STATUS_1K_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17
+
+struct tx_fes_status_1k_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#endif
+};
+
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK                                 0x0000000000000001
+
+#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK                                            0x0000000000000002
+
+#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TID_LSB                                              2
+#define TX_FES_STATUS_1K_BA_BA_TID_MSB                                              5
+#define TX_FES_STATUS_1K_BA_BA_TID_MASK                                             0x000000000000003c
+
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK                               0x0000000000000040
+
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK                                   0x0000000000000080
+
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB                                      8
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB                                      15
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK                                     0x000000000000ff00
+
+#define TX_FES_STATUS_1K_BA_SSN_OFFSET                                              0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SSN_LSB                                                 16
+#define TX_FES_STATUS_1K_BA_SSN_MSB                                                 27
+#define TX_FES_STATUS_1K_BA_SSN_MASK                                                0x000000000fff0000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB                                         28
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB                                         31
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK                                        0x00000000f0000000
+
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB                                          32
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB                                          47
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK                                         0x0000ffff00000000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB                                         48
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB                                         63
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB                                      0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB                                      31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK                                     0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB                                     32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB                                     63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK                                    0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET                                  0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB                                     0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB                                     31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK                                    0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB                                    32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB                                    63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK                                   0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET                                0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET                               0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB                                  32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB                                  63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_ack_or_ba.h b/hw/fig/v1/tx_fes_status_ack_or_ba.h
new file mode 100644
index 000000000000..678c639141ba
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_ack_or_ba.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
+#define _TX_FES_STATUS_ACK_OR_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5
+
+struct tx_fes_status_ack_or_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#endif
+};
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK                             0x0000000000000001
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK                                        0x0000000000000002
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB                                          2
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB                                          5
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK                                         0x000000000000003c
+
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK                           0x0000000000000040
+
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK                               0x0000000000000080
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB                                  8
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB                                  15
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK                                 0x000000000000ff00
+
+#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB                                             16
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB                                             27
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK                                            0x000000000fff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB                                     28
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB                                     31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK                                    0x00000000f0000000
+
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB                                      32
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB                                      47
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK                                     0x0000ffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB                                     48
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB                                     63
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK                                    0xffff000000000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB                                  0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB                                  31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET                              0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB                                 32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB                                 63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK                                0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB                                 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB                                 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK                                0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET                             0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB                                32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB                                63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK                               0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK                              0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_end.h b/hw/fig/v1/tx_fes_status_end.h
new file mode 100644
index 000000000000..b1cccb06c7e1
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_end.h
@@ -0,0 +1,581 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_END_H_
+#define _TX_FES_STATUS_END_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_END 12
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_END 6
+
+struct tx_fes_status_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot___reserved_g_0046                                  :  1,
+                      prot___reserved_g_0086                                  :  1,
+                      prot___reserved_g_0043                                  :  1,
+                      prot___reserved_g_0053                                  :  1,
+                      prot___reserved_g_0041                                  :  1,
+                      __reserved_g_0082                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0086                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0083                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      global_fes_transmit_result                              :  4,
+                      cbf_bw_received_valid                                   :  1,
+                      cbf_bw_received                                         :  3,
+                      actual_received_ack_type                                :  4,
+                      sta_response_count                                      :  6,
+                      more_data_received                                      :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_after_struct16                                 :  4,
+                      brp_info_valid                                          :  1,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      reserved_1a                                             :  5,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      only_null_delim_sent                                    :  1;
+             uint32_t terminate___reserved_g_0022_sequence                              :  1,
+                      reserved_2b                                             :  5,
+                      response_type                                           :  5,
+                      r2r_end_status_to_follow                                :  1,
+                      reserved_5a                                             :  3,
+                      __reserved_g_0055                                       :  1,
+                      __reserved_g_0084                                       :  1,
+                      prot___reserved_g_0042                                  :  1,
+                      prot___reserved_g_0052                                  :  1,
+                      __reserved_g_0042                                       :  1,
+                      __reserved_g_0052                                       :  1,
+                      reserved_2c                                             : 11;
+             uint32_t beamform_masked_user_bitmap_15_0                        : 16,
+                      beamform_masked_user_bitmap_31_16                       : 16;
+             uint32_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8,
+                      highest_achieved_data_null_ratio                        :  5,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      pdg_mpdu_ready                                          :  1;
+             uint32_t pdg_mpdu_count                                          : 16,
+                      pdg_est_mpdu_tx_count                                   : 16;
+             uint32_t pdg_overview_length                                     : 24,
+                      txop_duration                                           :  7,
+                      pdg_dropped_mpdu_warning                                :  1;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      fec_type                                                :  1,
+                      stbc                                                    :  1,
+                      num_data_symbols                                        : 16,
+                      ru_size                                                 :  4,
+                      reserved_17a                                            :  4;
+             uint32_t num_ltf_symbols                                         :  3,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      reserved_18a                                            :  5,
+                      dcm                                                     :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      reserved_18b                                            :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8;
+             uint32_t __reserved_g_0022_active_user_map                                 : 16,
+                      __reserved_g_0022_sent_dummy_tx                                   :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      prot___reserved_g_0068                                  :  1,
+                      prot___reserved_g_0069                                  :  1,
+                      __reserved_g_0056                                       :  1,
+                      __reserved_g_0085                                       :  1,
+                      cv_corr_status                                          :  8;
+             uint32_t current_tx_duration                                     : 16,
+                      reserved_21a                                            :  4,
+                      hw_qos_null_bitmap                                      :  8,
+                      hw_qos_null_setup_missing                               :  1,
+                      reserved_21b                                            :  3;
+             uint32_t reserved_22b                                            :  4,
+                      prot___reserved_g_0040                                  :  1,
+                      prot___reserved_g_0080                                  :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0080                                       :  1,
+                      prot___reserved_g_0063                                  :  1,
+                      prot___reserved_g_0078                                  :  1,
+                      __reserved_g_0063                                       :  1,
+                      __reserved_g_0078                                       :  1,
+                      prot___reserved_g_0061                                  :  1,
+                      prot___reserved_g_0076                                  :  1,
+                      __reserved_g_0061                                       :  1,
+                      __reserved_g_0076                                       :  1,
+                      prot___reserved_g_0059                                  :  1,
+                      prot___reserved_g_0074                                  :  1,
+                      __reserved_g_0059                                       :  1,
+                      __reserved_g_0074                                       :  1,
+                      prot___reserved_g_0057                                  :  1,
+                      prot___reserved_g_0072                                  :  1,
+                      __reserved_g_0057                                       :  1,
+                      __reserved_g_0072                                       :  1,
+                      coex_signaling_status                                   :  8;
+#else
+             uint32_t more_data_received                                      :  1,
+                      sta_response_count                                      :  6,
+                      actual_received_ack_type                                :  4,
+                      cbf_bw_received                                         :  3,
+                      cbf_bw_received_valid                                   :  1,
+                      global_fes_transmit_result                              :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0083                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0086                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0082                                       :  1,
+                      prot___reserved_g_0041                                  :  1,
+                      prot___reserved_g_0053                                  :  1,
+                      prot___reserved_g_0043                                  :  1,
+                      prot___reserved_g_0086                                  :  1,
+                      prot___reserved_g_0046                                  :  1;
+             uint32_t only_null_delim_sent                                    :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      reserved_1a                                             :  5,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      brp_info_valid                                          :  1,
+                      reserved_after_struct16                                 :  4;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t reserved_2c                                             : 11,
+                      __reserved_g_0052                                       :  1,
+                      __reserved_g_0042                                       :  1,
+                      prot___reserved_g_0052                                  :  1,
+                      prot___reserved_g_0042                                  :  1,
+                      __reserved_g_0084                                       :  1,
+                      __reserved_g_0055                                       :  1,
+                      reserved_5a                                             :  3,
+                      r2r_end_status_to_follow                                :  1,
+                      response_type                                           :  5,
+                      reserved_2b                                             :  5,
+                      terminate___reserved_g_0022_sequence                              :  1;
+             uint32_t beamform_masked_user_bitmap_31_16                       : 16,
+                      beamform_masked_user_bitmap_15_0                        : 16;
+             uint32_t pdg_mpdu_ready                                          :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      highest_achieved_data_null_ratio                        :  5,
+                      cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             uint32_t pdg_est_mpdu_tx_count                                   : 16,
+                      pdg_mpdu_count                                          : 16;
+             uint32_t pdg_dropped_mpdu_warning                                :  1,
+                      txop_duration                                           :  7,
+                      pdg_overview_length                                     : 24;
+             uint32_t reserved_17a                                            :  4,
+                      ru_size                                                 :  4,
+                      num_data_symbols                                        : 16,
+                      stbc                                                    :  1,
+                      fec_type                                                :  1,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      reserved_18b                                            :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      dcm                                                     :  1,
+                      reserved_18a                                            :  5,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      num_ltf_symbols                                         :  3;
+             uint32_t cv_corr_status                                          :  8,
+                      __reserved_g_0085                                       :  1,
+                      __reserved_g_0056                                       :  1,
+                      prot___reserved_g_0069                                  :  1,
+                      prot___reserved_g_0068                                  :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      __reserved_g_0022_sent_dummy_tx                                   :  1,
+                      __reserved_g_0022_active_user_map                                 : 16;
+             uint32_t reserved_21b                                            :  3,
+                      hw_qos_null_setup_missing                               :  1,
+                      hw_qos_null_bitmap                                      :  8,
+                      reserved_21a                                            :  4,
+                      current_tx_duration                                     : 16;
+             uint32_t coex_signaling_status                                   :  8,
+                      __reserved_g_0072                                       :  1,
+                      __reserved_g_0057                                       :  1,
+                      prot___reserved_g_0072                                  :  1,
+                      prot___reserved_g_0057                                  :  1,
+                      __reserved_g_0074                                       :  1,
+                      __reserved_g_0059                                       :  1,
+                      prot___reserved_g_0074                                  :  1,
+                      prot___reserved_g_0059                                  :  1,
+                      __reserved_g_0076                                       :  1,
+                      __reserved_g_0061                                       :  1,
+                      prot___reserved_g_0076                                  :  1,
+                      prot___reserved_g_0061                                  :  1,
+                      __reserved_g_0078                                       :  1,
+                      __reserved_g_0063                                       :  1,
+                      prot___reserved_g_0078                                  :  1,
+                      prot___reserved_g_0063                                  :  1,
+                      __reserved_g_0080                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      prot___reserved_g_0080                                  :  1,
+                      prot___reserved_g_0040                                  :  1,
+                      reserved_22b                                            :  4;
+#endif
+};
+
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                        0x0000000000001000
+
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB                            13
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB                            16
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK                           0x000000000001e000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK                                0x0000000000020000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB                                       18
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB                                       20
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK                                      0x00000000001c0000
+
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB                              21
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB                              24
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK                             0x0000000001e00000
+
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB                                    25
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB                                    30
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK                                   0x000000007e000000
+
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB   32
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB   39
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK  0x000000ff00000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET       0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB          40
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB          45
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK         0x00003f0000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET          0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB             46
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB             47
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK            0x0000c00000000000
+
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB                               48
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB                               51
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK                              0x000f000000000000
+
+#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK                                       0x0010000000000000
+
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK                        0x0020000000000000
+
+#define TX_FES_STATUS_END_RESERVED_1A_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_1A_LSB                                           54
+#define TX_FES_STATUS_END_RESERVED_1A_MSB                                           58
+#define TX_FES_STATUS_END_RESERVED_1A_MASK                                          0x07c0000000000000
+
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK                             0x0800000000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                       0x1000000000000000
+
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                  0x2000000000000000
+
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK                                 0x8000000000000000
+
+#define TX_FES_STATUS_END_RESERVED_2B_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_RESERVED_2B_LSB                                           1
+#define TX_FES_STATUS_END_RESERVED_2B_MSB                                           5
+#define TX_FES_STATUS_END_RESERVED_2B_MASK                                          0x000000000000003e
+
+#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET                                      0x0000000000000008
+#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB                                         6
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB                                         10
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK                                        0x00000000000007c0
+
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK                             0x0000000000000800
+
+#define TX_FES_STATUS_END_RESERVED_5A_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_RESERVED_5A_LSB                                           12
+#define TX_FES_STATUS_END_RESERVED_5A_MSB                                           14
+#define TX_FES_STATUS_END_RESERVED_5A_MASK                                          0x0000000000007000
+
+#define TX_FES_STATUS_END_RESERVED_2C_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_RESERVED_2C_LSB                                           21
+#define TX_FES_STATUS_END_RESERVED_2C_MSB                                           31
+#define TX_FES_STATUS_END_RESERVED_2C_MASK                                          0x00000000ffe00000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                   0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                      32
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                      47
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                     0x0000ffff00000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                     48
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                     63
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                    0xffff000000000000
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB                              0
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB                              7
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK                             0x00000000000000ff
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB                                 8
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB                                 15
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK                                0x000000000000ff00
+
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET                   0x0000000000000010
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB                      16
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB                      20
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK                     0x00000000001f0000
+
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK                                     0x0000000000200000
+
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK                             0x0000000000400000
+
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                      0x0000000000800000
+
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET                          0x0000000000000010
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK                            0x0000000001000000
+
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                      0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                        0x0000000002000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                  0x0000000000000010
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                     26
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                     30
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                    0x000000007c000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK                                       0x0000000080000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB                                        32
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB                                        47
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK                                       0x0000ffff00000000
+
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB                                 48
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB                                 63
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK                                0xffff000000000000
+
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB                                   0
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB                                   23
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK                                  0x0000000000ffffff
+
+#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET                                      0x0000000000000018
+#define TX_FES_STATUS_END_TXOP_DURATION_LSB                                         24
+#define TX_FES_STATUS_END_TXOP_DURATION_MSB                                         30
+#define TX_FES_STATUS_END_TXOP_DURATION_MASK                                        0x000000007f000000
+
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET                           0x0000000000000018
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK                             0x0000000080000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET                          0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB                             32
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB                             33
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK                            0x0000000300000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                     0x0000000400000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB                                      35
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB                                      37
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK                                     0x0000003800000000
+
+#define TX_FES_STATUS_END_FEC_TYPE_OFFSET                                           0x0000000000000018
+#define TX_FES_STATUS_END_FEC_TYPE_LSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MASK                                             0x0000004000000000
+
+#define TX_FES_STATUS_END_STBC_OFFSET                                               0x0000000000000018
+#define TX_FES_STATUS_END_STBC_LSB                                                  39
+#define TX_FES_STATUS_END_STBC_MSB                                                  39
+#define TX_FES_STATUS_END_STBC_MASK                                                 0x0000008000000000
+
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB                                      40
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB                                      55
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK                                     0x00ffff0000000000
+
+#define TX_FES_STATUS_END_RU_SIZE_OFFSET                                            0x0000000000000018
+#define TX_FES_STATUS_END_RU_SIZE_LSB                                               56
+#define TX_FES_STATUS_END_RU_SIZE_MSB                                               59
+#define TX_FES_STATUS_END_RU_SIZE_MASK                                              0x0f00000000000000
+
+#define TX_FES_STATUS_END_RESERVED_17A_OFFSET                                       0x0000000000000018
+#define TX_FES_STATUS_END_RESERVED_17A_LSB                                          60
+#define TX_FES_STATUS_END_RESERVED_17A_MSB                                          63
+#define TX_FES_STATUS_END_RESERVED_17A_MASK                                         0xf000000000000000
+
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB                                       0
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB                                       2
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK                                      0x0000000000000007
+
+#define TX_FES_STATUS_END_LTF_SIZE_OFFSET                                           0x0000000000000020
+#define TX_FES_STATUS_END_LTF_SIZE_LSB                                              3
+#define TX_FES_STATUS_END_LTF_SIZE_MSB                                              4
+#define TX_FES_STATUS_END_LTF_SIZE_MASK                                             0x0000000000000018
+
+#define TX_FES_STATUS_END_CP_SETTING_OFFSET                                         0x0000000000000020
+#define TX_FES_STATUS_END_CP_SETTING_LSB                                            5
+#define TX_FES_STATUS_END_CP_SETTING_MSB                                            6
+#define TX_FES_STATUS_END_CP_SETTING_MASK                                           0x0000000000000060
+
+#define TX_FES_STATUS_END_RESERVED_18A_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18A_LSB                                          7
+#define TX_FES_STATUS_END_RESERVED_18A_MSB                                          11
+#define TX_FES_STATUS_END_RESERVED_18A_MASK                                         0x0000000000000f80
+
+#define TX_FES_STATUS_END_DCM_OFFSET                                                0x0000000000000020
+#define TX_FES_STATUS_END_DCM_LSB                                                   12
+#define TX_FES_STATUS_END_DCM_MSB                                                   12
+#define TX_FES_STATUS_END_DCM_MASK                                                  0x0000000000001000
+
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET                                  0x0000000000000020
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK                                    0x0000000000002000
+
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET                                 0x0000000000000020
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK                                   0x0000000000004000
+
+#define TX_FES_STATUS_END_RESERVED_18B_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18B_LSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MASK                                         0x0000000000008000
+
+#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET                                      0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB                                         16
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB                                         23
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK                                        0x0000000000ff0000
+
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB                                       24
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB                                       31
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK                                      0x00000000ff000000
+
+#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET                                     0x0000000000000020
+#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB                                        56
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB                                        63
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK                                       0xff00000000000000
+
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB                                   0
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB                                   15
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_END_RESERVED_21A_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21A_LSB                                          16
+#define TX_FES_STATUS_END_RESERVED_21A_MSB                                          19
+#define TX_FES_STATUS_END_RESERVED_21A_MASK                                         0x00000000000f0000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET                                 0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB                                    20
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB                                    27
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK                                   0x000000000ff00000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET                          0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK                            0x0000000010000000
+
+#define TX_FES_STATUS_END_RESERVED_21B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21B_LSB                                          29
+#define TX_FES_STATUS_END_RESERVED_21B_MSB                                          31
+#define TX_FES_STATUS_END_RESERVED_21B_MASK                                         0x00000000e0000000
+
+#define TX_FES_STATUS_END_RESERVED_22B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_22B_LSB                                          32
+#define TX_FES_STATUS_END_RESERVED_22B_MSB                                          35
+#define TX_FES_STATUS_END_RESERVED_22B_MASK                                         0x0000000f00000000
+
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET                              0x0000000000000028
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB                                 56
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB                                 63
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_prot.h b/hw/fig/v1/tx_fes_status_prot.h
new file mode 100644
index 000000000000..702cc1add940
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_prot.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_PROT_H_
+#define _TX_FES_STATUS_PROT_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2
+
+struct tx_fes_status_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t success                                                 :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      reserved_0                                              : 19,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5;
+             uint32_t frame_type                                              :  2,
+                      frame_subtype                                           :  4,
+                      rx_pwr_mgmt                                             :  1,
+                      status                                                  :  1,
+                      duration_field                                          : 16,
+                      reserved_1a                                             :  2,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_2a                                             : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      reserved_0                                              : 19,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      success                                                 :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      reserved_1a                                             :  2,
+                      duration_field                                          : 16,
+                      status                                                  :  1,
+                      rx_pwr_mgmt                                             :  1,
+                      frame_subtype                                           :  4,
+                      frame_type                                              :  2;
+             uint32_t reserved_2a                                             : 16;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_PROT_SUCCESS_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_SUCCESS_LSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MASK                                             0x0000000000000001
+
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK                            0x0000000000000002
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                      0x0000000000000004
+
+#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_0_LSB                                           3
+#define TX_FES_STATUS_PROT_RESERVED_0_MSB                                           21
+#define TX_FES_STATUS_PROT_RESERVED_0_MASK                                          0x00000000003ffff8
+
+#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PKT_TYPE_LSB                                             22
+#define TX_FES_STATUS_PROT_PKT_TYPE_MSB                                             25
+#define TX_FES_STATUS_PROT_PKT_TYPE_MASK                                            0x0000000003c00000
+
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK                                 0x0000000004000000
+
+#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_RATE_MCS_LSB                                             27
+#define TX_FES_STATUS_PROT_RATE_MCS_MSB                                             31
+#define TX_FES_STATUS_PROT_RATE_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB                                           32
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB                                           33
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK                                          0x0000000300000000
+
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB                                        34
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB                                        37
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK                                       0x0000003c00000000
+
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK                                         0x0000004000000000
+
+#define TX_FES_STATUS_PROT_STATUS_OFFSET                                            0x0000000000000000
+#define TX_FES_STATUS_PROT_STATUS_LSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MASK                                              0x0000008000000000
+
+#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB                                       40
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB                                       55
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK                                      0x00ffff0000000000
+
+#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_1A_LSB                                          56
+#define TX_FES_STATUS_PROT_RESERVED_1A_MSB                                          57
+#define TX_FES_STATUS_PROT_RESERVED_1A_MASK                                         0x0300000000000000
+
+#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_AGC_CBW_LSB                                              58
+#define TX_FES_STATUS_PROT_AGC_CBW_MSB                                              60
+#define TX_FES_STATUS_PROT_AGC_CBW_MASK                                             0x1c00000000000000
+
+#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB                                          61
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB                                          63
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK                                         0xe000000000000000
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB  0
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB  7
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET      0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB         8
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB         13
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK        0x0000000000003f00
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET         0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB            14
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB            15
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK           0x000000000000c000
+
+#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET                                       0x0000000000000008
+#define TX_FES_STATUS_PROT_RESERVED_2A_LSB                                          16
+#define TX_FES_STATUS_PROT_RESERVED_2A_MSB                                          31
+#define TX_FES_STATUS_PROT_RESERVED_2A_MASK                                         0x00000000ffff0000
+
+#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB                                        32
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB                                        63
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_start.h b/hw/fig/v1/tx_fes_status_start.h
new file mode 100644
index 000000000000..bc8e06ec59fb
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_start.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_H_
+#define _TX_FES_STATUS_START_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START 2
+
+struct tx_fes_status_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1a                                             :  8,
+                      transmit_start_reason                                   :  3,
+                      disabled_user_bitmap_36_32                              :  5,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      schedule_try                                            :  4,
+                      medium_prot_type                                        :  3,
+                      reserved_1b                                             :  2;
+             uint32_t optimal_bw_try_count                                    :  4,
+                      number_of_users                                         :  7,
+                      coex_nack_count                                         :  5,
+                      cca_ed0                                                 : 16;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1b                                             :  2,
+                      medium_prot_type                                        :  3,
+                      schedule_try                                            :  4,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      disabled_user_bitmap_36_32                              :  5,
+                      transmit_start_reason                                   :  3,
+                      reserved_1a                                             :  8;
+             uint32_t cca_ed0                                                 : 16,
+                      coex_nack_count                                         :  5,
+                      number_of_users                                         :  7,
+                      optimal_bw_try_count                                    :  4;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_ID_LSB                                         0
+#define TX_FES_STATUS_START_SCHEDULE_ID_MSB                                         31
+#define TX_FES_STATUS_START_SCHEDULE_ID_MASK                                        0x00000000ffffffff
+
+#define TX_FES_STATUS_START_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1A_LSB                                         32
+#define TX_FES_STATUS_START_RESERVED_1A_MSB                                         39
+#define TX_FES_STATUS_START_RESERVED_1A_MASK                                        0x000000ff00000000
+
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB                               40
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB                               42
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK                              0x0000070000000000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB                          43
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB                          47
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK                         0x0000f80000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB                                48
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB                                52
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK                               0x001f000000000000
+
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB                                    53
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB                                    54
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK                                   0x0060000000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB                                        55
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB                                        58
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK                                       0x0780000000000000
+
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB                                    59
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB                                    61
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK                                   0x3800000000000000
+
+#define TX_FES_STATUS_START_RESERVED_1B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1B_LSB                                         62
+#define TX_FES_STATUS_START_RESERVED_1B_MSB                                         63
+#define TX_FES_STATUS_START_RESERVED_1B_MASK                                        0xc000000000000000
+
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET                             0x0000000000000008
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB                                0
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB                                3
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK                               0x000000000000000f
+
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB                                     4
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB                                     10
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK                                    0x00000000000007f0
+
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB                                     11
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB                                     15
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK                                    0x000000000000f800
+
+#define TX_FES_STATUS_START_CCA_ED0_OFFSET                                          0x0000000000000008
+#define TX_FES_STATUS_START_CCA_ED0_LSB                                             16
+#define TX_FES_STATUS_START_CCA_ED0_MSB                                             31
+#define TX_FES_STATUS_START_CCA_ED0_MASK                                            0x00000000ffff0000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB                           32
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB                           63
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_start_ppdu.h b/hw/fig/v1/tx_fes_status_start_ppdu.h
new file mode 100644
index 000000000000..a87b3b0a0ccc
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_start_ppdu.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PPDU_H_
+#define _TX_FES_STATUS_START_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3
+
+struct tx_fes_status_start_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      ndp_frame                                               :  3,
+                      reserved_2b                                             :  1,
+                      coex_based_tx_bw                                        :  3,
+                      coex_based_ant_mask                                     :  8,
+                      reserved_2c                                             :  1;
+             uint32_t coex_based_tx_pwr_shared_ant                            :  8,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      concurrent_bt_tx                                        :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wan_rx                                       :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_result_alt_based                                   :  1,
+                      request_packet_bw                                       :  3,
+                      response_type                                           :  5;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t reserved_2c                                             :  1,
+                      coex_based_ant_mask                                     :  8,
+                      coex_based_tx_bw                                        :  3,
+                      reserved_2b                                             :  1,
+                      ndp_frame                                               :  3,
+                      subband_mask                                            : 16;
+             uint32_t response_type                                           :  5,
+                      request_packet_bw                                       :  3,
+                      coex_result_alt_based                                   :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      concurrent_wan_rx                                       :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_bt_tx                                        :  1,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      coex_based_tx_pwr_shared_ant                            :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB                                      16
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB                                      18
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK                                     0x0000000000070000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK                                   0x0000000000080000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB                               20
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB                               22
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK                              0x0000000000700000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET                         0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB                            23
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB                            30
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK                           0x000000007f800000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB                   32
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB                   39
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK                  0x000000ff00000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB                          40
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB                          47
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK                         0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK                              0x0001000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK                            0x0002000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK                             0x0004000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK                             0x0008000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK                         0x0010000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK                       0x0020000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK                        0x0040000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK                         0x0080000000000000
+
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB                              56
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB                              58
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK                             0x0700000000000000
+
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB                                  59
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK                                 0xf800000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_start_prot.h b/hw/fig/v1/tx_fes_status_start_prot.h
new file mode 100644
index 000000000000..aca9ac5eb28b
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_start_prot.h
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PROT_H_
+#define _TX_FES_STATUS_START_PROT_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3
+
+struct tx_fes_status_start_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      reserved_2b                                             :  4,
+                      prot_coex_based_tx_bw                                   :  3,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_result_alt_based                              :  1;
+             uint32_t prot_coex_tx_pwr_shared_ant                             :  8,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_request_packet_bw                                  :  3,
+                      response_type                                           :  5,
+                      reserved_3a                                             :  1;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t prot_coex_result_alt_based                              :  1,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_based_tx_bw                                   :  3,
+                      reserved_2b                                             :  4,
+                      subband_mask                                            : 16;
+             uint32_t reserved_3a                                             :  1,
+                      response_type                                           :  5,
+                      prot_request_packet_bw                                  :  3,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_coex_tx_pwr_shared_ant                             :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB                                    16
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK                                   0x00000000000f0000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB                          20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB                          22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK                         0x0000000000700000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET                    0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB                       23
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB                       30
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK                      0x000000007f800000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK                    0x0000000080000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB                    32
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB                    39
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK                   0x000000ff00000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB                           40
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB                           47
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK                          0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK                         0x0001000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK                       0x0002000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK                        0x0004000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK                        0x0008000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK                    0x0010000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK                  0x0020000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK                   0x0040000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB                         55
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB                         57
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK                        0x0380000000000000
+
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB                                  58
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB                                  62
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK                                 0x7c00000000000000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK                                   0x8000000000000000
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_user_ppdu.h b/hw/fig/v1/tx_fes_status_user_ppdu.h
new file mode 100644
index 000000000000..dad9a040ff46
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_user_ppdu.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_PPDU_H_
+#define _TX_FES_STATUS_USER_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3
+
+struct tx_fes_status_user_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      bw_drop_underflow_warning                               :  1,
+                      qc_eosp_setting                                         :  1,
+                      mpdu_tx_count                                           : 11,
+                      user_blocked                                            :  1,
+                      pre_trig_response_delim_count                           :  7;
+             uint32_t underflow_byte_count                                    : 16,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      coex_abort_mpdu_count                                   :  9,
+                      transmitted_tid                                         :  4,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      cv_corr_user_valid_in_phy                               :  1;
+             uint32_t duration                                                : 16,
+                      num_eof_delim_added                                     : 16;
+             uint32_t psdu_octet                                              : 24,
+                      qos_buf_state                                           :  8;
+             uint32_t num_null_delim_added                                    : 22,
+                      fc_more_data_setting                                    :  1,
+                      fc_pwr_mgt_setting                                      :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5;
+             uint32_t ht_control                                              : 32;
+#else
+             uint32_t pre_trig_response_delim_count                           :  7,
+                      user_blocked                                            :  1,
+                      mpdu_tx_count                                           : 11,
+                      qc_eosp_setting                                         :  1,
+                      bw_drop_underflow_warning                               :  1,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t cv_corr_user_valid_in_phy                               :  1,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      transmitted_tid                                         :  4,
+                      coex_abort_mpdu_count                                   :  9,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      underflow_byte_count                                    : 16;
+             uint32_t num_eof_delim_added                                     : 16,
+                      duration                                                : 16;
+             uint32_t qos_buf_state                                           :  8,
+                      psdu_octet                                              : 24;
+             uint32_t mcs                                                     :  5,
+                      nss                                                     :  3,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  1,
+                      num_null_delim_added                                    : 22;
+             uint32_t ht_control                                              : 32;
+#endif
+};
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB                            8
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK                           0x00000000000001ff
+
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB                          9
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB                          10
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK                         0x0000000000000600
+
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK                                0x0000000000001000
+
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET                                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB                                   13
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB                                   23
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK                                  0x0000000000ffe000
+
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK                                   0x0000000001000000
+
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB                   25
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB                   31
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK                  0x00000000fe000000
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB                            32
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB                            47
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK                           0x0000ffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK                    0x0001000000000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET                        0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB                           49
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB                           57
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK                          0x03fe000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB                                 58
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB                                 61
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK                                0x3c00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK                      0x8000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_DURATION_LSB                                        0
+#define TX_FES_STATUS_USER_PPDU_DURATION_MSB                                        15
+#define TX_FES_STATUS_USER_PPDU_DURATION_MASK                                       0x000000000000ffff
+
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB                             16
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB                             31
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK                            0x00000000ffff0000
+
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB                                      55
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK                                     0x00ffffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB                                   56
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB                                   63
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK                                  0xff00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB                            21
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK                           0x00000000003fffff
+
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK                           0x0000000000400000
+
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK                             0x0000000000800000
+
+#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NSS_LSB                                             24
+#define TX_FES_STATUS_USER_PPDU_NSS_MSB                                             26
+#define TX_FES_STATUS_USER_PPDU_NSS_MASK                                            0x0000000007000000
+
+#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_MCS_LSB                                             27
+#define TX_FES_STATUS_USER_PPDU_MCS_MSB                                             31
+#define TX_FES_STATUS_USER_PPDU_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB                                      63
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_fes_status_user_response.h b/hw/fig/v1/tx_fes_status_user_response.h
new file mode 100644
index 000000000000..a4562d64a9ec
--- /dev/null
+++ b/hw/fig/v1/tx_fes_status_user_response.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
+#define _TX_FES_STATUS_USER_RESPONSE_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1
+
+struct tx_fes_status_user_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fes_transmit_result                                     :  4,
+                      reserved_0                                              : 28;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t pre_padding_fcs_overwritten                             :  1,
+                      reserved_after_struct16                                 : 15;
+#else
+             uint32_t reserved_0                                              : 28,
+                      fes_transmit_result                                     :  4;
+             uint32_t reserved_after_struct16                                 : 15,
+                      pre_padding_fcs_overwritten                             :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB                         0
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB                         3
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK                        0x000000000000000f
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB                                  4
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB                                  31
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK                                 0x00000000fffffff0
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB   46
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB   47
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK  0x0000c00000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET              0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK                0x0001000000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB                     49
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB                     63
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK                    0xfffe000000000000
+
+#endif
diff --git a/hw/fig/v1/tx_flush_req.h b/hw/fig/v1/tx_flush_req.h
new file mode 100644
index 000000000000..af502ec619eb
--- /dev/null
+++ b/hw/fig/v1/tx_flush_req.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FLUSH_REQ_H_
+#define _TX_FLUSH_REQ_H_
+
+#define NUM_OF_DWORDS_TX_FLUSH_REQ 2
+
+#define NUM_OF_QWORDS_TX_FLUSH_REQ 1
+
+struct tx_flush_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t flush_req_reason                                        :  8,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_user_number_or_link_id                        :  6,
+                      mlo_abort_reason                                        :  5,
+                      reserved_0a                                             :  5;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      mlo_abort_reason                                        :  5,
+                      flush_req_user_number_or_link_id                        :  6,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_reason                                        :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB                                           0
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB                                           7
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK                                          0x00000000000000ff
+
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET                                      0x0000000000000000
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB                                         8
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB                                         15
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK                                        0x000000000000ff00
+
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB                           16
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB                           21
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK                          0x00000000003f0000
+
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB                                           22
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB                                           26
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK                                          0x0000000007c00000
+
+#define TX_FLUSH_REQ_RESERVED_0A_OFFSET                                             0x0000000000000000
+#define TX_FLUSH_REQ_RESERVED_0A_LSB                                                27
+#define TX_FLUSH_REQ_RESERVED_0A_MSB                                                31
+#define TX_FLUSH_REQ_RESERVED_0A_MASK                                               0x00000000f8000000
+
+#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET                                           0x0000000000000000
+#define TX_FLUSH_REQ_TLV64_PADDING_LSB                                              32
+#define TX_FLUSH_REQ_TLV64_PADDING_MSB                                              63
+#define TX_FLUSH_REQ_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_mpdu_start.h b/hw/fig/v1/tx_mpdu_start.h
new file mode 100644
index 000000000000..a68fab7a4f2a
--- /dev/null
+++ b/hw/fig/v1/tx_mpdu_start.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MPDU_START_H_
+#define _TX_MPDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MPDU_START 10
+
+#define NUM_OF_QWORDS_TX_MPDU_START 5
+
+struct tx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_length                                             : 14,
+                      frame_not_from_tqm                                      :  1,
+                      vht_control_present                                     :  1,
+                      mpdu_header_length                                      :  8,
+                      retry_count                                             :  7,
+                      wds                                                     :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      mpdu_sequence_number                                    : 12,
+                      raw_already_encrypted                                   :  1,
+                      frame_type                                              :  2,
+                      txdma_dropped_mpdu_warning                              :  1;
+             uint32_t iv_byte_0                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_3                                               :  8;
+             uint32_t iv_byte_4                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_7                                               :  8;
+             uint32_t iv_byte_8                                               :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_11                                              :  8;
+             uint32_t iv_byte_12                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_15                                              :  8;
+             uint32_t iv_byte_16                                              :  8,
+                      iv_byte_17                                              :  8,
+                      iv_len                                                  :  5,
+                      icv_len                                                 :  5,
+                      vht_control_offset                                      :  6;
+             uint32_t mpdu_type                                               :  1,
+                      transmit_bw_restriction                                 :  1,
+                      allowed_transmit_bw                                     :  4,
+                      tx_notify_frame                                         :  3,
+                      reserved_8a                                             : 23;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t wds                                                     :  1,
+                      retry_count                                             :  7,
+                      mpdu_header_length                                      :  8,
+                      vht_control_present                                     :  1,
+                      frame_not_from_tqm                                      :  1,
+                      mpdu_length                                             : 14;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t txdma_dropped_mpdu_warning                              :  1,
+                      frame_type                                              :  2,
+                      raw_already_encrypted                                   :  1,
+                      mpdu_sequence_number                                    : 12,
+                      pn_47_32                                                : 16;
+             uint32_t iv_byte_3                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_0                                               :  8;
+             uint32_t iv_byte_7                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_4                                               :  8;
+             uint32_t iv_byte_11                                              :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_8                                               :  8;
+             uint32_t iv_byte_15                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_12                                              :  8;
+             uint32_t vht_control_offset                                      :  6,
+                      icv_len                                                 :  5,
+                      iv_len                                                  :  5,
+                      iv_byte_17                                              :  8,
+                      iv_byte_16                                              :  8;
+             uint32_t reserved_8a                                             : 23,
+                      tx_notify_frame                                         :  3,
+                      allowed_transmit_bw                                     :  4,
+                      transmit_bw_restriction                                 :  1,
+                      mpdu_type                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MPDU_START_MPDU_LENGTH_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_MPDU_LENGTH_LSB                                               0
+#define TX_MPDU_START_MPDU_LENGTH_MSB                                               13
+#define TX_MPDU_START_MPDU_LENGTH_MASK                                              0x0000000000003fff
+
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK                                       0x0000000000004000
+
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET                                    0x0000000000000000
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK                                      0x0000000000008000
+
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB                                        16
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB                                        23
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK                                       0x0000000000ff0000
+
+#define TX_MPDU_START_RETRY_COUNT_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_RETRY_COUNT_LSB                                               24
+#define TX_MPDU_START_RETRY_COUNT_MSB                                               30
+#define TX_MPDU_START_RETRY_COUNT_MASK                                              0x000000007f000000
+
+#define TX_MPDU_START_WDS_OFFSET                                                    0x0000000000000000
+#define TX_MPDU_START_WDS_LSB                                                       31
+#define TX_MPDU_START_WDS_MSB                                                       31
+#define TX_MPDU_START_WDS_MASK                                                      0x0000000080000000
+
+#define TX_MPDU_START_PN_31_0_OFFSET                                                0x0000000000000000
+#define TX_MPDU_START_PN_31_0_LSB                                                   32
+#define TX_MPDU_START_PN_31_0_MSB                                                   63
+#define TX_MPDU_START_PN_31_0_MASK                                                  0xffffffff00000000
+
+#define TX_MPDU_START_PN_47_32_OFFSET                                               0x0000000000000008
+#define TX_MPDU_START_PN_47_32_LSB                                                  0
+#define TX_MPDU_START_PN_47_32_MSB                                                  15
+#define TX_MPDU_START_PN_47_32_MASK                                                 0x000000000000ffff
+
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET                                   0x0000000000000008
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB                                      16
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB                                      27
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK                                     0x000000000fff0000
+
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET                                  0x0000000000000008
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK                                    0x0000000010000000
+
+#define TX_MPDU_START_FRAME_TYPE_OFFSET                                             0x0000000000000008
+#define TX_MPDU_START_FRAME_TYPE_LSB                                                29
+#define TX_MPDU_START_FRAME_TYPE_MSB                                                30
+#define TX_MPDU_START_FRAME_TYPE_MASK                                               0x0000000060000000
+
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET                             0x0000000000000008
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK                               0x0000000080000000
+
+#define TX_MPDU_START_IV_BYTE_0_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_0_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_0_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_0_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_1_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_1_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_1_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_1_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_2_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_2_LSB                                                 48
+#define TX_MPDU_START_IV_BYTE_2_MSB                                                 55
+#define TX_MPDU_START_IV_BYTE_2_MASK                                                0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_3_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_3_LSB                                                 56
+#define TX_MPDU_START_IV_BYTE_3_MSB                                                 63
+#define TX_MPDU_START_IV_BYTE_3_MASK                                                0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_4_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_4_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_4_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_4_MASK                                                0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_5_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_5_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_5_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_5_MASK                                                0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_6_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_6_LSB                                                 16
+#define TX_MPDU_START_IV_BYTE_6_MSB                                                 23
+#define TX_MPDU_START_IV_BYTE_6_MASK                                                0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_7_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_7_LSB                                                 24
+#define TX_MPDU_START_IV_BYTE_7_MSB                                                 31
+#define TX_MPDU_START_IV_BYTE_7_MASK                                                0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_8_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_8_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_8_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_8_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_9_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_9_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_9_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_9_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_10_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_10_LSB                                                48
+#define TX_MPDU_START_IV_BYTE_10_MSB                                                55
+#define TX_MPDU_START_IV_BYTE_10_MASK                                               0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_11_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_11_LSB                                                56
+#define TX_MPDU_START_IV_BYTE_11_MSB                                                63
+#define TX_MPDU_START_IV_BYTE_11_MASK                                               0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_12_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_12_LSB                                                0
+#define TX_MPDU_START_IV_BYTE_12_MSB                                                7
+#define TX_MPDU_START_IV_BYTE_12_MASK                                               0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_13_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_13_LSB                                                8
+#define TX_MPDU_START_IV_BYTE_13_MSB                                                15
+#define TX_MPDU_START_IV_BYTE_13_MASK                                               0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_14_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_14_LSB                                                16
+#define TX_MPDU_START_IV_BYTE_14_MSB                                                23
+#define TX_MPDU_START_IV_BYTE_14_MASK                                               0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_15_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_15_LSB                                                24
+#define TX_MPDU_START_IV_BYTE_15_MSB                                                31
+#define TX_MPDU_START_IV_BYTE_15_MASK                                               0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_16_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_16_LSB                                                32
+#define TX_MPDU_START_IV_BYTE_16_MSB                                                39
+#define TX_MPDU_START_IV_BYTE_16_MASK                                               0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_17_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_17_LSB                                                40
+#define TX_MPDU_START_IV_BYTE_17_MSB                                                47
+#define TX_MPDU_START_IV_BYTE_17_MASK                                               0x0000ff0000000000
+
+#define TX_MPDU_START_IV_LEN_OFFSET                                                 0x0000000000000018
+#define TX_MPDU_START_IV_LEN_LSB                                                    48
+#define TX_MPDU_START_IV_LEN_MSB                                                    52
+#define TX_MPDU_START_IV_LEN_MASK                                                   0x001f000000000000
+
+#define TX_MPDU_START_ICV_LEN_OFFSET                                                0x0000000000000018
+#define TX_MPDU_START_ICV_LEN_LSB                                                   53
+#define TX_MPDU_START_ICV_LEN_MSB                                                   57
+#define TX_MPDU_START_ICV_LEN_MASK                                                  0x03e0000000000000
+
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET                                     0x0000000000000018
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB                                        58
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB                                        63
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK                                       0xfc00000000000000
+
+#define TX_MPDU_START_MPDU_TYPE_OFFSET                                              0x0000000000000020
+#define TX_MPDU_START_MPDU_TYPE_LSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MASK                                                0x0000000000000001
+
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET                                0x0000000000000020
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK                                  0x0000000000000002
+
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET                                    0x0000000000000020
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB                                       2
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB                                       5
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK                                      0x000000000000003c
+
+#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET                                        0x0000000000000020
+#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB                                           6
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB                                           8
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK                                          0x00000000000001c0
+
+#define TX_MPDU_START_RESERVED_8A_OFFSET                                            0x0000000000000020
+#define TX_MPDU_START_RESERVED_8A_LSB                                               9
+#define TX_MPDU_START_RESERVED_8A_MSB                                               31
+#define TX_MPDU_START_RESERVED_8A_MASK                                              0x00000000fffffe00
+
+#define TX_MPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000020
+#define TX_MPDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MPDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_msdu_extension.h b/hw/fig/v1/tx_msdu_extension.h
new file mode 100644
index 000000000000..f8da5593497b
--- /dev/null
+++ b/hw/fig/v1/tx_msdu_extension.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tso_enable                                              :  1,
+                      reserved_0a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      reserved_0b                                             :  7;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      udp_length                                              : 16;
+             uint32_t checksum_offset                                         : 14,
+                      partial_checksum_en                                     :  1,
+                      reserved_4a                                             :  1,
+                      payload_start_offset                                    : 14,
+                      reserved_4b                                             :  2;
+             uint32_t payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      wds                                                     :  1,
+                      reserved_5b                                             : 15;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_ptr_39_32                                          :  8,
+                      reserved_7a                                             :  8,
+                      buf0_len                                                : 16;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_ptr_39_32                                          :  8,
+                      reserved_9a                                             :  8,
+                      buf1_len                                                : 16;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_ptr_39_32                                          :  8,
+                      reserved_11a                                            :  8,
+                      buf2_len                                                : 16;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_ptr_39_32                                          :  8,
+                      reserved_13a                                            :  8,
+                      buf3_len                                                : 16;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_ptr_39_32                                          :  8,
+                      reserved_15a                                            :  8,
+                      buf4_len                                                : 16;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_ptr_39_32                                          :  8,
+                      reserved_17a                                            :  8,
+                      buf5_len                                                : 16;
+#else
+             uint32_t reserved_0b                                             :  7,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_0a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t udp_length                                              : 16,
+                      ip_identification                                       : 16;
+             uint32_t reserved_4b                                             :  2,
+                      payload_start_offset                                    : 14,
+                      reserved_4a                                             :  1,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 14;
+             uint32_t reserved_5b                                             : 15,
+                      wds                                                     :  1,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_len                                                : 16,
+                      reserved_7a                                             :  8,
+                      buf0_ptr_39_32                                          :  8;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_len                                                : 16,
+                      reserved_9a                                             :  8,
+                      buf1_ptr_39_32                                          :  8;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_len                                                : 16,
+                      reserved_11a                                            :  8,
+                      buf2_ptr_39_32                                          :  8;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_len                                                : 16,
+                      reserved_13a                                            :  8,
+                      buf3_ptr_39_32                                          :  8;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_len                                                : 16,
+                      reserved_15a                                            :  8,
+                      buf4_ptr_39_32                                          :  8;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_len                                                : 16,
+                      reserved_17a                                            :  8,
+                      buf5_ptr_39_32                                          :  8;
+#endif
+};
+
+#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
+#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
+
+#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
+#define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
+#define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
+#define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
+#define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
+
+#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
+#define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
+#define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
+
+#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
+#define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
+#define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
+
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
+
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
+
+#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
+#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
+
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
+
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
+
+#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
+#define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
+
+#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
+#define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
+
+#define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
+#define TX_MSDU_EXTENSION_WDS_LSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
+
+#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
+#define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET                                        0x0000001c
+#define TX_MSDU_EXTENSION_RESERVED_7A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_7A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_7A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
+#define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
+#define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
+#define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
+#define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
+#define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
+#define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
+#define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
+#define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
+
+#endif
diff --git a/hw/fig/v1/tx_msdu_start.h b/hw/fig/v1/tx_msdu_start.h
new file mode 100644
index 000000000000..e62a76009f3a
--- /dev/null
+++ b/hw/fig/v1/tx_msdu_start.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_START_H_
+#define _TX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_START 8
+
+#define NUM_OF_QWORDS_TX_MSDU_START 4
+
+struct tx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_len                                                : 14,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      encap_type                                              :  2,
+                      epd_en                                                  :  1,
+                      da_sa_present                                           :  2,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      dummy_msdu_delimitation                                 :  1,
+                      reserved_0a                                             :  5;
+             uint32_t tso_enable                                              :  1,
+                      reserved_1a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      mesh_enable                                             :  1,
+                      reserved_1b                                             :  6;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      checksum_offset                                         : 13,
+                      partial_checksum_en                                     :  1,
+                      reserved_4                                              :  2;
+             uint32_t payload_start_offset                                    : 14,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5b                                             :  2;
+             uint32_t udp_length                                              : 16,
+                      reserved_6                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      dummy_msdu_delimitation                                 :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      da_sa_present                                           :  2,
+                      epd_en                                                  :  1,
+                      encap_type                                              :  2,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      msdu_len                                                : 14;
+             uint32_t reserved_1b                                             :  6,
+                      mesh_enable                                             :  1,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_1a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t reserved_4                                              :  2,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 13,
+                      ip_identification                                       : 16;
+             uint32_t reserved_5b                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      payload_start_offset                                    : 14;
+             uint32_t reserved_6                                              : 16,
+                      udp_length                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MSDU_START_MSDU_LEN_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_MSDU_LEN_LSB                                                  0
+#define TX_MSDU_START_MSDU_LEN_MSB                                                  13
+#define TX_MSDU_START_MSDU_LEN_MASK                                                 0x0000000000003fff
+
+#define TX_MSDU_START_FIRST_MSDU_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_FIRST_MSDU_LSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MASK                                               0x0000000000004000
+
+#define TX_MSDU_START_LAST_MSDU_OFFSET                                              0x0000000000000000
+#define TX_MSDU_START_LAST_MSDU_LSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MASK                                                0x0000000000008000
+
+#define TX_MSDU_START_ENCAP_TYPE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_ENCAP_TYPE_LSB                                                16
+#define TX_MSDU_START_ENCAP_TYPE_MSB                                                17
+#define TX_MSDU_START_ENCAP_TYPE_MASK                                               0x0000000000030000
+
+#define TX_MSDU_START_EPD_EN_OFFSET                                                 0x0000000000000000
+#define TX_MSDU_START_EPD_EN_LSB                                                    18
+#define TX_MSDU_START_EPD_EN_MSB                                                    18
+#define TX_MSDU_START_EPD_EN_MASK                                                   0x0000000000040000
+
+#define TX_MSDU_START_DA_SA_PRESENT_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_DA_SA_PRESENT_LSB                                             19
+#define TX_MSDU_START_DA_SA_PRESENT_MSB                                             20
+#define TX_MSDU_START_DA_SA_PRESENT_MASK                                            0x0000000000180000
+
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET                                       0x0000000000000000
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK                                         0x0000000000200000
+
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000000400000
+
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000000800000
+
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000001000000
+
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000002000000
+
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET                                0x0000000000000000
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK                                  0x0000000004000000
+
+#define TX_MSDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_0A_LSB                                               27
+#define TX_MSDU_START_RESERVED_0A_MSB                                               31
+#define TX_MSDU_START_RESERVED_0A_MASK                                              0x00000000f8000000
+
+#define TX_MSDU_START_TSO_ENABLE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_TSO_ENABLE_LSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MASK                                               0x0000000100000000
+
+#define TX_MSDU_START_RESERVED_1A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1A_LSB                                               33
+#define TX_MSDU_START_RESERVED_1A_MSB                                               38
+#define TX_MSDU_START_RESERVED_1A_MASK                                              0x0000007e00000000
+
+#define TX_MSDU_START_TCP_FLAG_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_LSB                                                  39
+#define TX_MSDU_START_TCP_FLAG_MSB                                                  47
+#define TX_MSDU_START_TCP_FLAG_MASK                                                 0x0000ff8000000000
+
+#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_MASK_LSB                                             48
+#define TX_MSDU_START_TCP_FLAG_MASK_MSB                                             56
+#define TX_MSDU_START_TCP_FLAG_MASK_MASK                                            0x01ff000000000000
+
+#define TX_MSDU_START_MESH_ENABLE_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_MESH_ENABLE_LSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MASK                                              0x0200000000000000
+
+#define TX_MSDU_START_RESERVED_1B_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1B_LSB                                               58
+#define TX_MSDU_START_RESERVED_1B_MSB                                               63
+#define TX_MSDU_START_RESERVED_1B_MASK                                              0xfc00000000000000
+
+#define TX_MSDU_START_L2_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_L2_LENGTH_LSB                                                 0
+#define TX_MSDU_START_L2_LENGTH_MSB                                                 15
+#define TX_MSDU_START_L2_LENGTH_MASK                                                0x000000000000ffff
+
+#define TX_MSDU_START_IP_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_IP_LENGTH_LSB                                                 16
+#define TX_MSDU_START_IP_LENGTH_MSB                                                 31
+#define TX_MSDU_START_IP_LENGTH_MASK                                                0x00000000ffff0000
+
+#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET                                         0x0000000000000008
+#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB                                            32
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB                                            63
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK                                           0xffffffff00000000
+
+#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET                                      0x0000000000000010
+#define TX_MSDU_START_IP_IDENTIFICATION_LSB                                         0
+#define TX_MSDU_START_IP_IDENTIFICATION_MSB                                         15
+#define TX_MSDU_START_IP_IDENTIFICATION_MASK                                        0x000000000000ffff
+
+#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET                                        0x0000000000000010
+#define TX_MSDU_START_CHECKSUM_OFFSET_LSB                                           16
+#define TX_MSDU_START_CHECKSUM_OFFSET_MSB                                           28
+#define TX_MSDU_START_CHECKSUM_OFFSET_MASK                                          0x000000001fff0000
+
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET                                    0x0000000000000010
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK                                      0x0000000020000000
+
+#define TX_MSDU_START_RESERVED_4_OFFSET                                             0x0000000000000010
+#define TX_MSDU_START_RESERVED_4_LSB                                                30
+#define TX_MSDU_START_RESERVED_4_MSB                                                31
+#define TX_MSDU_START_RESERVED_4_MASK                                               0x00000000c0000000
+
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET                                   0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB                                      32
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB                                      45
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK                                     0x00003fff00000000
+
+#define TX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5A_LSB                                               46
+#define TX_MSDU_START_RESERVED_5A_MSB                                               47
+#define TX_MSDU_START_RESERVED_5A_MASK                                              0x0000c00000000000
+
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET                                     0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB                                        48
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB                                        61
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK                                       0x3fff000000000000
+
+#define TX_MSDU_START_RESERVED_5B_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5B_LSB                                               62
+#define TX_MSDU_START_RESERVED_5B_MSB                                               63
+#define TX_MSDU_START_RESERVED_5B_MASK                                              0xc000000000000000
+
+#define TX_MSDU_START_UDP_LENGTH_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_UDP_LENGTH_LSB                                                0
+#define TX_MSDU_START_UDP_LENGTH_MSB                                                15
+#define TX_MSDU_START_UDP_LENGTH_MASK                                               0x000000000000ffff
+
+#define TX_MSDU_START_RESERVED_6_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_RESERVED_6_LSB                                                16
+#define TX_MSDU_START_RESERVED_6_MSB                                                31
+#define TX_MSDU_START_RESERVED_6_MASK                                               0x00000000ffff0000
+
+#define TX_MSDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000018
+#define TX_MSDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MSDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MSDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_peer_entry.h b/hw/fig/v1/tx_peer_entry.h
new file mode 100644
index 000000000000..c26c7f6a3e05
--- /dev/null
+++ b/hw/fig/v1/tx_peer_entry.h
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_PEER_ENTRY_H_
+#define _TX_PEER_ENTRY_H_
+
+#define NUM_OF_DWORDS_TX_PEER_ENTRY 22
+
+#define NUM_OF_QWORDS_TX_PEER_ENTRY 11
+
+struct tx_peer_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_a_47_32                                        : 16,
+                      mac_addr_b_15_0                                         : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t use_ad_b                                                :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      vlan_llc_mode                                           :  1,
+                      key_type                                                :  4,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      ignore_hard_filters                                     :  1,
+                      ignore_soft_filters                                     :  1,
+                      epd_output                                              :  1,
+                      wds                                                     :  1,
+                      insert_or_strip                                         :  1,
+                      sw_filter_id                                            : 16;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t sta_partial_aid                                         : 11,
+                      transmit_vif                                            :  4,
+                      block_this_user                                         :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      use_qos_alt_mute_mask                                   :  1,
+                      dl_ul_direction                                         :  1,
+                      use_ad_c                                                :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      multi_link_addr_ad3_valid                               :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      reserved_12                                             :  1;
+             uint32_t insert_vlan_outer_tci                                   : 16,
+                      insert_vlan_inner_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t multi_link_addr_crypto_enable                           :  1,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      reserved_17a                                            :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t mac_addr_c_47_32                                        : 16,
+                      multi_link_addr_ad3_47_32                               : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_b_15_0                                         : 16,
+                      mac_addr_a_47_32                                        : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t sw_filter_id                                            : 16,
+                      insert_or_strip                                         :  1,
+                      wds                                                     :  1,
+                      epd_output                                              :  1,
+                      ignore_soft_filters                                     :  1,
+                      ignore_hard_filters                                     :  1,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      key_type                                                :  4,
+                      vlan_llc_mode                                           :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      use_ad_b                                                :  1;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t reserved_12                                             :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_ad3_valid                               :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      use_ad_c                                                :  1,
+                      dl_ul_direction                                         :  1,
+                      use_qos_alt_mute_mask                                   :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      block_this_user                                         :  1,
+                      transmit_vif                                            :  4,
+                      sta_partial_aid                                         : 11;
+             uint32_t insert_vlan_inner_tci                                   : 16,
+                      insert_vlan_outer_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_17a                                            :  9,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      multi_link_addr_crypto_enable                           :  1;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t multi_link_addr_ad3_47_32                               : 16,
+                      mac_addr_c_47_32                                        : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET                                       0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB                                           48
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB                                           63
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK                                          0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET                                       0x0000000000000008
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB                                          0
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB                                          31
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK                                         0x00000000ffffffff
+
+#define TX_PEER_ENTRY_USE_AD_B_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_USE_AD_B_LSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MASK                                                 0x0000000100000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK                                  0x0000000200000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK                                  0x0000000400000000
+
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET                                          0x0000000000000008
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK                                            0x0000000800000000
+
+#define TX_PEER_ENTRY_KEY_TYPE_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_KEY_TYPE_LSB                                                  36
+#define TX_PEER_ENTRY_KEY_TYPE_MSB                                                  39
+#define TX_PEER_ENTRY_KEY_TYPE_MASK                                                 0x000000f000000000
+
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET                                     0x0000000000000008
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB                                        40
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB                                        42
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK                                       0x0000070000000000
+
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK                                      0x0000080000000000
+
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK                                      0x0000100000000000
+
+#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET                                             0x0000000000000008
+#define TX_PEER_ENTRY_EPD_OUTPUT_LSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MASK                                               0x0000200000000000
+
+#define TX_PEER_ENTRY_WDS_OFFSET                                                    0x0000000000000008
+#define TX_PEER_ENTRY_WDS_LSB                                                       46
+#define TX_PEER_ENTRY_WDS_MSB                                                       46
+#define TX_PEER_ENTRY_WDS_MASK                                                      0x0000400000000000
+
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET                                        0x0000000000000008
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK                                          0x0000800000000000
+
+#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET                                           0x0000000000000008
+#define TX_PEER_ENTRY_SW_FILTER_ID_LSB                                              48
+#define TX_PEER_ENTRY_SW_FILTER_ID_MSB                                              63
+#define TX_PEER_ENTRY_SW_FILTER_ID_MASK                                             0xffff000000000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET                                      0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB                                         0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB                                         31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK                                        0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET                                     0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB                                        32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB                                        63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK                                       0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET                                     0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB                                        0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB                                        31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK                                       0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET                                    0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB                                       32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB                                       63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK                                      0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB                                           0
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB                                           10
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK                                          0x00000000000007ff
+
+#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET                                           0x0000000000000030
+#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB                                              11
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB                                              14
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK                                             0x0000000000007800
+
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK                                          0x0000000000008000
+
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB                                           16
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB                                           17
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK                                          0x0000000000030000
+
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK                                    0x0000000000040000
+
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK                                          0x0000000000080000
+
+#define TX_PEER_ENTRY_USE_AD_C_OFFSET                                               0x0000000000000030
+#define TX_PEER_ENTRY_USE_AD_C_LSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MASK                                                 0x0000000000100000
+
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET                             0x0000000000000030
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB                                21
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB                                22
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK                               0x0000000000600000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET                              0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK                                0x0000000000800000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                  0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                    0x0000000001000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                         0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                           0x0000000002000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                          0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                            0x0000000004000000
+
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB                                      27
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB                                      28
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK                                     0x0000000018000000
+
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB                                      29
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB                                      30
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK                                     0x0000000060000000
+
+#define TX_PEER_ENTRY_RESERVED_12_OFFSET                                            0x0000000000000030
+#define TX_PEER_ENTRY_RESERVED_12_LSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MASK                                              0x0000000080000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB                                     32
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB                                     47
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK                                    0x0000ffff00000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB                                     48
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB                                     63
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK                                    0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET                          0x0000000000000040
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK                            0x0000000100000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB                                    33
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB                                    34
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK                                   0x0000000600000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB                                    35
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB                                    36
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK                                   0x0000001800000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB                                    37
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB                                    38
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK                                   0x0000006000000000
+
+#define TX_PEER_ENTRY_RESERVED_17A_OFFSET                                           0x0000000000000040
+#define TX_PEER_ENTRY_RESERVED_17A_LSB                                              39
+#define TX_PEER_ENTRY_RESERVED_17A_MSB                                              47
+#define TX_PEER_ENTRY_RESERVED_17A_MASK                                             0x0000ff8000000000
+
+#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET                                             0x0000000000000040
+#define TX_PEER_ENTRY_SW_PEER_ID_LSB                                                48
+#define TX_PEER_ENTRY_SW_PEER_ID_MSB                                                63
+#define TX_PEER_ENTRY_SW_PEER_ID_MASK                                               0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET                                        0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET                                       0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET                              0x0000000000000048
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB                                 48
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB                                 63
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK                                0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET                               0x0000000000000050
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB                                  0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB                                  31
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET                                          0x0000000000000050
+#define TX_PEER_ENTRY_TLV64_PADDING_LSB                                             32
+#define TX_PEER_ENTRY_TLV64_PADDING_MSB                                             63
+#define TX_PEER_ENTRY_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/tx_queue_extension.h b/hw/fig/v1/tx_queue_extension.h
new file mode 100644
index 000000000000..883383a9d8f2
--- /dev/null
+++ b/hw/fig/v1/tx_queue_extension.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_QUEUE_EXTENSION_H_
+#define _TX_QUEUE_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18
+
+#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9
+
+struct tx_queue_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t frame_ctl                                               : 16,
+                      qos_ctl                                                 : 16;
+             uint32_t ampdu_flag                                              :  1,
+                      tx_notify_no_htc_override                               :  1,
+                      reserved_1a                                             :  7,
+                      checksum_tso_disable_for_frag                           :  1,
+                      key_id                                                  :  8,
+                      qos_buf_state_overwrite                                 :  1,
+                      buf_state_sta_id                                        :  1,
+                      buf_state_source                                        :  1,
+                      ht_control_overwrite_enable                             :  1,
+                      ht_control_overwrite_source                             :  4,
+                      reserved_1b                                             :  6;
+             uint32_t ul_headroom_insertion_enable                            :  1,
+                      ul_headroom_offset                                      :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      bqrp_offset                                             :  5,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqr_rsvd_9_8                                            :  2,
+                      base_pn_63_48                                           : 16;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_field_bw20                                   : 32;
+             uint32_t ht_control_field_bw40                                   : 32;
+             uint32_t ht_control_field_bw80                                   : 32;
+             uint32_t ht_control_field_bw160                                  : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t cas_control_info                                        :  8,
+                      cas_offset                                              :  5,
+                      cas_insertion_enable                                    :  1,
+                      reserved_10a                                            :  2,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      reserved_10b                                            :  5,
+                      mpdu_hdr_len_override_en                                :  1,
+                      bar_ssn_overwrite_enable                                :  1;
+             uint32_t bar_ssn_offset                                          : 12,
+                      mpdu_hdr_len_override_val                               :  9,
+                      reserved_11a                                            : 11;
+             uint32_t ht_control_field_bw320                                  : 32;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t pre_padding_fcs_overwrite_offset                        : 16,
+                      icf_blackout_info_offset                                : 16;
+             uint32_t trigger_common_info_length                              :  6,
+                      cmf_overwrite_offset                                    : 14,
+                      reserved_15a                                            : 12;
+             uint32_t hdr_ctrl_prot_key_id_byte_offset                        : 14,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      reserved_16a                                            :  2;
+             uint32_t pad_byte_offset                                         : 16,
+                      pad_byte_offset_valid                                   :  1,
+                      reserved_17a                                            : 15;
+#else
+             uint32_t qos_ctl                                                 : 16,
+                      frame_ctl                                               : 16;
+             uint32_t reserved_1b                                             :  6,
+                      ht_control_overwrite_source                             :  4,
+                      ht_control_overwrite_enable                             :  1,
+                      buf_state_source                                        :  1,
+                      buf_state_sta_id                                        :  1,
+                      qos_buf_state_overwrite                                 :  1,
+                      key_id                                                  :  8,
+                      checksum_tso_disable_for_frag                           :  1,
+                      reserved_1a                                             :  7,
+                      tx_notify_no_htc_override                               :  1,
+                      ampdu_flag                                              :  1;
+             uint32_t base_pn_63_48                                           : 16,
+                      bqr_rsvd_9_8                                            :  2,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqrp_offset                                             :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      ul_headroom_offset                                      :  5,
+                      ul_headroom_insertion_enable                            :  1;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_field_bw20                                   : 32;
+             uint32_t ht_control_field_bw40                                   : 32;
+             uint32_t ht_control_field_bw80                                   : 32;
+             uint32_t ht_control_field_bw160                                  : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t bar_ssn_overwrite_enable                                :  1,
+                      mpdu_hdr_len_override_en                                :  1,
+                      reserved_10b                                            :  5,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      reserved_10a                                            :  2,
+                      cas_insertion_enable                                    :  1,
+                      cas_offset                                              :  5,
+                      cas_control_info                                        :  8;
+             uint32_t reserved_11a                                            : 11,
+                      mpdu_hdr_len_override_val                               :  9,
+                      bar_ssn_offset                                          : 12;
+             uint32_t ht_control_field_bw320                                  : 32;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t icf_blackout_info_offset                                : 16,
+                      pre_padding_fcs_overwrite_offset                        : 16;
+             uint32_t reserved_15a                                            : 12,
+                      cmf_overwrite_offset                                    : 14,
+                      trigger_common_info_length                              :  6;
+             uint32_t reserved_16a                                            :  2,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      hdr_ctrl_prot_key_id_byte_offset                        : 14;
+             uint32_t reserved_17a                                            : 15,
+                      pad_byte_offset_valid                                   :  1,
+                      pad_byte_offset                                         : 16;
+#endif
+};
+
+#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET                                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB                                            0
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB                                            15
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK                                           0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET                                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_CTL_LSB                                              16
+#define TX_QUEUE_EXTENSION_QOS_CTL_MSB                                              31
+#define TX_QUEUE_EXTENSION_QOS_CTL_MASK                                             0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET                                        0x0000000000000000
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK                                          0x0000000100000000
+
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK                           0x0000000200000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB                                          34
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB                                          40
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK                                         0x000001fc00000000
+
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET                     0x0000000000000000
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK                       0x0000020000000000
+
+#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET                                            0x0000000000000000
+#define TX_QUEUE_EXTENSION_KEY_ID_LSB                                               42
+#define TX_QUEUE_EXTENSION_KEY_ID_MSB                                               49
+#define TX_QUEUE_EXTENSION_KEY_ID_MASK                                              0x0003fc0000000000
+
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK                             0x0004000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK                                    0x0008000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK                                    0x0010000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK                         0x0020000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB                          54
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB                          57
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK                         0x03c0000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB                                          58
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB                                          63
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK                                         0xfc00000000000000
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK                        0x0000000000000001
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET                                0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB                                   1
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB                                   5
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK                                  0x000000000000003e
+
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET                             0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK                               0x0000000000000040
+
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET                                       0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB                                          7
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB                                          11
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK                                         0x0000000000000f80
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET                              0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB                                 12
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB                                 13
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK                                0x0000000000003000
+
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET                                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB                                         14
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB                                         15
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB                                        16
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB                                        31
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK                                       0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB                                        32
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB                                        63
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK                                       0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET                                    0x0000000000000010
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB                                       0
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB                                       31
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK                                      0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET                             0x0000000000000010
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB                                32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB                                63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK                               0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET                             0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB                                0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB                                31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK                               0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET                             0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB                                32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB                                63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK                               0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET                            0x0000000000000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB                               0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB                               31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK                              0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET                         0x0000000000000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB                            32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB                            63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK                           0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET                                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB                                     0
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB                                     7
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK                                    0x00000000000000ff
+
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET                                        0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB                                           8
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB                                           12
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK                                          0x0000000000001f00
+
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET                              0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK                                0x0000000000002000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB                                         14
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB                                         15
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET               0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB                  16
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB                  19
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK                 0x00000000000f0000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET              0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB                 20
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB                 23
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK                0x0000000000f00000
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK                    0x0000000001000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB                                         25
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB                                         29
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK                                        0x000000003e000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK                            0x0000000040000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK                            0x0000000080000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET                                    0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB                                       32
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB                                       43
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK                                      0x00000fff00000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET                         0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB                            44
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB                            52
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK                           0x001ff00000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB                                         53
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK                                        0xffe0000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET                            0x0000000000000030
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB                               0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB                               31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK                              0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET                                        0x0000000000000030
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB                                           32
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB                                           63
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK                                          0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET                  0x0000000000000038
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB                     0
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB                     15
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK                    0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET                          0x0000000000000038
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB                             16
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB                             31
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK                            0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET                        0x0000000000000038
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB                           32
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB                           37
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK                          0x0000003f00000000
+
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET                              0x0000000000000038
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB                                 38
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB                                 51
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK                                0x000fffc000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET                                      0x0000000000000038
+#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB                                         52
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK                                        0xfff0000000000000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET                  0x0000000000000040
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB                     0
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB                     13
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK                    0x0000000000003fff
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET                   0x0000000000000040
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB                      14
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB                      16
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK                     0x000000000001c000
+
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET                                  0x0000000000000040
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB                                     17
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB                                     17
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK                                    0x0000000000020000
+
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET                                   0x0000000000000040
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB                                      18
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB                                      18
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK                                     0x0000000000040000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET                         0x0000000000000040
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB                            19
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB                            29
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK                           0x000000003ff80000
+
+#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET                                      0x0000000000000040
+#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB                                         30
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB                                         31
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK                                        0x00000000c0000000
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET                                   0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB                                      32
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB                                      47
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK                                     0x0000ffff00000000
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET                             0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB                                48
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB                                48
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK                               0x0001000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_17A_OFFSET                                      0x0000000000000040
+#define TX_QUEUE_EXTENSION_RESERVED_17A_LSB                                         49
+#define TX_QUEUE_EXTENSION_RESERVED_17A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_17A_MASK                                        0xfffe000000000000
+
+#endif
diff --git a/hw/fig/v1/tx_rate_stats_info.h b/hw/fig/v1/tx_rate_stats_info.h
new file mode 100644
index 000000000000..ce84032dd353
--- /dev/null
+++ b/hw/fig/v1/tx_rate_stats_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_rate_stats_info_valid                                :  1,
+                      transmit_bw                                             :  3,
+                      transmit_pkt_type                                       :  4,
+                      transmit_stbc                                           :  1,
+                      transmit_ldpc                                           :  1,
+                      transmit_sgi                                            :  2,
+                      transmit_mcs                                            :  5,
+                      unequal_modulation_info                                 :  3,
+                      ofdma_transmission                                      :  1,
+                      reserved_0a                                             :  4,
+                      tones_in_ru                                             :  4,
+                      transmit_nss                                            :  3;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#else
+             uint32_t transmit_nss                                            :  3,
+                      tones_in_ru                                             :  4,
+                      reserved_0a                                             :  4,
+                      ofdma_transmission                                      :  1,
+                      unequal_modulation_info                                 :  3,
+                      transmit_mcs                                            :  5,
+                      transmit_sgi                                            :  2,
+                      transmit_ldpc                                           :  1,
+                      transmit_stbc                                           :  1,
+                      transmit_pkt_type                                       :  4,
+                      transmit_bw                                             :  3,
+                      tx_rate_stats_info_valid                                :  1;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#endif
+};
+
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET                          0x00000000
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK                            0x00000001
+
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB                                          1
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB                                          3
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK                                         0x0000000e
+
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET                                 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB                                    4
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB                                    7
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK                                   0x000000f0
+
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK                                       0x00000100
+
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK                                       0x00000200
+
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB                                         10
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB                                         11
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK                                        0x00000c00
+
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB                                         12
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB                                         16
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK                                        0x0001f000
+
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET                           0x00000000
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB                              17
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB                              19
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK                             0x000e0000
+
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET                                0x00000000
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK                                  0x00100000
+
+#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_RESERVED_0A_LSB                                          21
+#define TX_RATE_STATS_INFO_RESERVED_0A_MSB                                          24
+#define TX_RATE_STATS_INFO_RESERVED_0A_MASK                                         0x01e00000
+
+#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB                                          25
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB                                          28
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK                                         0x1e000000
+
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB                                         29
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB                                         31
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK                                        0xe0000000
+
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET                             0x00000004
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB                                0
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB                                31
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK                               0xffffffff
+
+#endif
diff --git a/hw/fig/v1/tx_raw_or_native_frame_setup.h b/hw/fig/v1/tx_raw_or_native_frame_setup.h
new file mode 100644
index 000000000000..220a82edf96d
--- /dev/null
+++ b/hw/fig/v1/tx_raw_or_native_frame_setup.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4
+
+#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
+
+struct tx_raw_or_native_frame_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fc_to_ds_mask                                           :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_order_mask                                           :  1,
+                      duration_field_mask                                     :  1,
+                      sequence_control_mask                                   :  1,
+                      qc_tid_mask                                             :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_amsdu_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_15to8_mask                                           :  1,
+                      iv_mask                                                 :  1,
+                      fc_to_ds_setting                                        :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_more_frag_setting                                    :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  2,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_order_setting                                        :  1,
+                      qc_tid_setting                                          :  4;
+             uint32_t qc_eosp_setting                                         :  2,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_amsdu_setting                                        :  1,
+                      qc_15to8_setting                                        :  8,
+                      mlo_addr_override                                       :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      sequence_control_source                                 :  1,
+                      fragment_number                                         :  4,
+                      sequence_number                                         : 12;
+             uint32_t mlo_addr_override_for_ctrl                              :  1,
+                      reserved_2a                                             : 31;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t qc_tid_setting                                          :  4,
+                      fc_order_setting                                        :  1,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_more_data_setting                                    :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_more_frag_setting                                    :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_to_ds_setting                                        :  1,
+                      iv_mask                                                 :  1,
+                      qc_15to8_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_amsdu_mask                                           :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_tid_mask                                             :  1,
+                      sequence_control_mask                                   :  1,
+                      duration_field_mask                                     :  1,
+                      fc_order_mask                                           :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_to_ds_mask                                           :  1;
+             uint32_t sequence_number                                         : 12,
+                      fragment_number                                         :  4,
+                      sequence_control_source                                 :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      mlo_addr_override                                       :  1,
+                      qc_15to8_setting                                        :  8,
+                      qc_amsdu_setting                                        :  1,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_eosp_setting                                         :  2;
+             uint32_t reserved_2a                                             : 31,
+                      mlo_addr_override_for_ctrl                              :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK                             0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK                           0x0000000000000002
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK                         0x0000000000000004
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK                             0x0000000000000008
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK                           0x0000000000000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK                         0x0000000000000020
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK                        0x0000000000000040
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK                             0x0000000000000080
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET                     0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK                       0x0000000000000100
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK                     0x0000000000000200
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK                               0x0000000000000400
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET                            0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK                              0x0000000000000800
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK                        0x0000000000001000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK                             0x0000000000002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK                               0x0000000000004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK                             0x0000000000008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET                                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK                                   0x0000000000010000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK                          0x0000000000020000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK                        0x0000000000040000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK                      0x0000000000080000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB                           20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB                           21
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK                          0x0000000000300000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK                        0x0000000000400000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB                       23
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB                       24
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK                      0x0000000001800000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB                      25
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB                      26
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK                     0x0000000006000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK                          0x0000000008000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET                          0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB                             28
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB                             31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK                            0x00000000f0000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB                            32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB                            33
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK                           0x0000000300000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB                      34
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB                      35
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK                     0x0000000c00000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK                          0x0000001000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB                           37
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB                           44
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK                          0x00001fe000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK                         0x0000200000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET               0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK                 0x0000400000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK                   0x0000800000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB                            48
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB                            51
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK                           0x000f000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB                            52
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB                            63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK                           0xfff0000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET              0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK                0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET                             0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB                                1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB                                31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK                               0x00000000fffffffe
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET                           0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB                              32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB                              63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v1/txpcu_buffer_basics.h b/hw/fig/v1/txpcu_buffer_basics.h
new file mode 100644
index 000000000000..4032a78ad617
--- /dev/null
+++ b/hw/fig/v1/txpcu_buffer_basics.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t available_memory                                        :  8,
+                      partial_tx_data_tlv_count                               :  8,
+                      tx_data_tlv_count                                       : 16;
+#else
+             uint32_t tx_data_tlv_count                                       : 16,
+                      partial_tx_data_tlv_count                               :  8,
+                      available_memory                                        :  8;
+#endif
+};
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET                                 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB                                    0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB                                    7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK                                   0x000000ff
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET                        0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB                           8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB                           15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK                          0x0000ff00
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET                                0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB                                   16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB                                   31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK                                  0xffff0000
+
+#endif
diff --git a/hw/fig/v1/txpcu_buffer_status.h b/hw/fig/v1/txpcu_buffer_status.h
new file mode 100644
index 000000000000..847ca277267d
--- /dev/null
+++ b/hw/fig/v1/txpcu_buffer_status.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_STATUS_H_
+#define _TXPCU_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
+
+struct txpcu_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t reserved                                                : 15,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved                                                : 15;
+#endif
+};
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x00000000000000ff
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x000000000000ff00
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0x00000000ffff0000
+
+#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            32
+#define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            46
+#define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff00000000
+
+#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x0000800000000000
+
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  48
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  63
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/txpcu_user_buffer_status.h b/hw/fig/v1/txpcu_user_buffer_status.h
new file mode 100644
index 000000000000..f6ad0fd73721
--- /dev/null
+++ b/hw/fig/v1/txpcu_user_buffer_status.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_USER_BUFFER_STATUS_H_
+#define _TXPCU_USER_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1
+
+struct txpcu_user_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t stored_word_count_user                                  : 14,
+                      reserved_1a                                             :  1,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved_1a                                             :  1,
+                      stored_word_count_user                                  : 14;
+#endif
+};
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB       0
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB       7
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK      0x00000000000000ff
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET   0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB      16
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB      31
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK     0x00000000ffff0000
+
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET                      0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB                         32
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB                         45
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK                        0x00003fff00000000
+
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET                                 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK                                   0x0000400000000000
+
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET                                    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK                                      0x0000800000000000
+
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                          0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                             48
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                             63
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                            0xffff000000000000
+
+#endif
diff --git a/hw/fig/v1/u_sig_eht_su_mu_info.h b/hw/fig/v1/u_sig_eht_su_mu_info.h
new file mode 100644
index 000000000000..1a08f3ab39b2
--- /dev/null
+++ b/hw/fig/v1/u_sig_eht_su_mu_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  5,
+                      validate_0b                                             :  1,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1b                                             :  1,
+                      mcs_of_eht_sig                                          :  2,
+                      num_eht_sig_symbols                                     :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      reserved_1d                                             :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      validate_0b                                             :  1,
+                      disregard_0a                                            :  5,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      reserved_1d                                             :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      num_eht_sig_symbols                                     :  5,
+                      mcs_of_eht_sig                                          :  2,
+                      validate_1b                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB                                        0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK                                       0x00000007
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB                                        3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB                                        5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK                                       0x00000038
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET                                      0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK                                        0x00000040
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB                                       7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB                                       12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK                                      0x00001f80
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET                                   0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB                                      13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB                                      19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK                                     0x000fe000
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB                                       20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB                                       24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK                                      0x01f00000
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK                                       0x02000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB                                        26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB                                        31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK                                       0xfc000000
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                           0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                              0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                              1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                             0x00000003
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK                                       0x00000004
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET                   0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB                      3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB                      7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK                     0x000000f8
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK                                       0x00000100
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET                                  0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB                                     9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB                                     10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK                                    0x00000600
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB                                11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB                                15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK                               0x0000f800
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET                                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB                                                16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB                                                19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK                                               0x000f0000
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET                                            0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB                                               20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB                                               25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK                                              0x03f00000
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK                               0x04000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB                                        27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB                                        29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK                                       0x38000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET                                          0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK                                            0x40000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#endif
diff --git a/hw/fig/v1/u_sig_eht_tb_info.h b/hw/fig/v1/u_sig_eht_tb_info.h
new file mode 100644
index 000000000000..8e417b38d233
--- /dev/null
+++ b/hw/fig/v1/u_sig_eht_tb_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  6,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      spatial_reuse                                           :  8,
+                      disregard_1b                                            :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1c                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      disregard_0a                                            :  6,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1c                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      disregard_1b                                            :  5,
+                      spatial_reuse                                           :  8,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB                                           0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB                                           2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK                                          0x00000007
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB                                           3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB                                           5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK                                          0x00000038
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET                                         0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK                                           0x00000040
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB                                          7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB                                          12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK                                         0x00001f80
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET                                      0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB                                         13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB                                         19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK                                        0x000fe000
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB                                          20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB                                          25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK                                         0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB                                           31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK                                          0xfc000000
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                              0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                                 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                                 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                                0x00000003
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK                                          0x00000004
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET                                      0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB                                         3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB                                         10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK                                        0x000007f8
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET                                       0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB                                          11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB                                          15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK                                         0x0000f800
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET                                                0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB                                                   16
+#define U_SIG_EHT_TB_INFO_CRC_MSB                                                   19
+#define U_SIG_EHT_TB_INFO_CRC_MASK                                                  0x000f0000
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET                                               0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB                                                  20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB                                                  25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK                                                 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB                                           30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK                                          0x7c000000
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/fig/v1/unallocated_ru_160_info.h b/hw/fig/v1/unallocated_ru_160_info.h
new file mode 100644
index 000000000000..ccd4a7bab9ad
--- /dev/null
+++ b/hw/fig/v1/unallocated_ru_160_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t subband80_0_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_1_cc1                                         :  8;
+#else
+             uint32_t subband80_1_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_0_cc0                                         :  8;
+#endif
+};
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB                                 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB                                 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK                                0x000000ff
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB                                 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB                                 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK                                0x0000ff00
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB                                 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB                                 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK                                0x00ff0000
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB                                 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB                                 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK                                0xff000000
+
+#endif
diff --git a/hw/fig/v1/uniform_descriptor_header.h b/hw/fig/v1/uniform_descriptor_header.h
new file mode 100644
index 000000000000..7a2de6ccd8df
--- /dev/null
+++ b/hw/fig/v1/uniform_descriptor_header.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t owner                                                   :  4,
+                      buffer_type                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      reserved_0a                                             :  4;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      buffer_type                                             :  4,
+                      owner                                                   :  4;
+#endif
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET                                      0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB                                         0
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB                                         3
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK                                        0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                                   4
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                                   7
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
+
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#endif
diff --git a/hw/fig/v1/uniform_reo_cmd_header.h b/hw/fig/v1/uniform_reo_cmd_header.h
new file mode 100644
index 000000000000..bcf7ed58b57c
--- /dev/null
+++ b/hw/fig/v1/uniform_reo_cmd_header.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_cmd_number                                          : 16,
+                      reo_status_required                                     :  1,
+                      reserved_0a                                             : 15;
+#else
+             uint32_t reserved_0a                                             : 15,
+                      reo_status_required                                     :  1,
+                      reo_cmd_number                                          : 16;
+#endif
+};
+
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET                                0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB                                   0
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB                                   15
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK                                  0x0000ffff
+
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                           0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB                              16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB                              16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK                             0x00010000
+
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET                                   0x00000000
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB                                      17
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB                                      31
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK                                     0xfffe0000
+
+#endif
diff --git a/hw/fig/v1/uniform_reo_status_header.h b/hw/fig/v1/uniform_reo_status_header.h
new file mode 100644
index 000000000000..b016537dffff
--- /dev/null
+++ b/hw/fig/v1/uniform_reo_status_header.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_status_number                                       : 16,
+                      cmd_execution_time                                      : 10,
+                      reo_cmd_execution_status                                :  2,
+                      reserved_0a                                             :  4;
+             uint32_t timestamp                                               : 32;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      reo_cmd_execution_status                                :  2,
+                      cmd_execution_time                                      : 10,
+                      reo_status_number                                       : 16;
+             uint32_t timestamp                                               : 32;
+#endif
+};
+
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET                          0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB                             0
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB                             15
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK                            0x0000ffff
+
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET                         0x00000000
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                            16
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                            25
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                           0x03ff0000
+
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET                   0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB                      26
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB                      27
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK                     0x0c000000
+
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET                                  0x00000004
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB                                     0
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB                                     31
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/fig/v1/vht_sig_a_info.h b/hw/fig/v1/vht_sig_a_info.h
new file mode 100644
index 000000000000..acd20f43949e
--- /dev/null
+++ b/hw/fig/v1/vht_sig_a_info.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t bandwidth                                               :  2,
+                      vhta_reserved_0                                         :  1,
+                      stbc                                                    :  1,
+                      group_id                                                :  6,
+                      n_sts                                                   : 12,
+                      txop_ps_not_allowed                                     :  1,
+                      vhta_reserved_0b                                        :  1,
+                      reserved_0                                              :  8;
+             uint32_t gi_setting                                              :  2,
+                      su_mu_coding                                            :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      mcs                                                     :  4,
+                      beamformed                                              :  1,
+                      vhta_reserved_1                                         :  1,
+                      crc                                                     :  8,
+                      tail                                                    :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      vhta_reserved_0b                                        :  1,
+                      txop_ps_not_allowed                                     :  1,
+                      n_sts                                                   : 12,
+                      group_id                                                :  6,
+                      stbc                                                    :  1,
+                      vhta_reserved_0                                         :  1,
+                      bandwidth                                               :  2;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      tail                                                    :  6,
+                      crc                                                     :  8,
+                      vhta_reserved_1                                         :  1,
+                      beamformed                                              :  1,
+                      mcs                                                     :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      su_mu_coding                                            :  1,
+                      gi_setting                                              :  2;
+#endif
+};
+
+#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET                                             0x00000000
+#define VHT_SIG_A_INFO_BANDWIDTH_LSB                                                0
+#define VHT_SIG_A_INFO_BANDWIDTH_MSB                                                1
+#define VHT_SIG_A_INFO_BANDWIDTH_MASK                                               0x00000003
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK                                         0x00000004
+
+#define VHT_SIG_A_INFO_STBC_OFFSET                                                  0x00000000
+#define VHT_SIG_A_INFO_STBC_LSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MASK                                                    0x00000008
+
+#define VHT_SIG_A_INFO_GROUP_ID_OFFSET                                              0x00000000
+#define VHT_SIG_A_INFO_GROUP_ID_LSB                                                 4
+#define VHT_SIG_A_INFO_GROUP_ID_MSB                                                 9
+#define VHT_SIG_A_INFO_GROUP_ID_MASK                                                0x000003f0
+
+#define VHT_SIG_A_INFO_N_STS_OFFSET                                                 0x00000000
+#define VHT_SIG_A_INFO_N_STS_LSB                                                    10
+#define VHT_SIG_A_INFO_N_STS_MSB                                                    21
+#define VHT_SIG_A_INFO_N_STS_MASK                                                   0x003ffc00
+
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET                                   0x00000000
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK                                     0x00400000
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET                                      0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK                                        0x00800000
+
+#define VHT_SIG_A_INFO_RESERVED_0_OFFSET                                            0x00000000
+#define VHT_SIG_A_INFO_RESERVED_0_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_0_MSB                                               31
+#define VHT_SIG_A_INFO_RESERVED_0_MASK                                              0xff000000
+
+#define VHT_SIG_A_INFO_GI_SETTING_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_GI_SETTING_LSB                                               0
+#define VHT_SIG_A_INFO_GI_SETTING_MSB                                               1
+#define VHT_SIG_A_INFO_GI_SETTING_MASK                                              0x00000003
+
+#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET                                          0x00000004
+#define VHT_SIG_A_INFO_SU_MU_CODING_LSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MASK                                            0x00000004
+
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                     0x00000004
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK                                       0x00000008
+
+#define VHT_SIG_A_INFO_MCS_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_MCS_LSB                                                      4
+#define VHT_SIG_A_INFO_MCS_MSB                                                      7
+#define VHT_SIG_A_INFO_MCS_MASK                                                     0x000000f0
+
+#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_BEAMFORMED_LSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MASK                                              0x00000100
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK                                         0x00000200
+
+#define VHT_SIG_A_INFO_CRC_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_CRC_LSB                                                      10
+#define VHT_SIG_A_INFO_CRC_MSB                                                      17
+#define VHT_SIG_A_INFO_CRC_MASK                                                     0x0003fc00
+
+#define VHT_SIG_A_INFO_TAIL_OFFSET                                                  0x00000004
+#define VHT_SIG_A_INFO_TAIL_LSB                                                     18
+#define VHT_SIG_A_INFO_TAIL_MSB                                                     23
+#define VHT_SIG_A_INFO_TAIL_MASK                                                    0x00fc0000
+
+#define VHT_SIG_A_INFO_RESERVED_1_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_RESERVED_1_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_1_MSB                                               30
+#define VHT_SIG_A_INFO_RESERVED_1_MASK                                              0x7f000000
+
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                             0x00000004
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                               0x80000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_mu160_info.h b/hw/fig/v1/vht_sig_b_mu160_info.h
new file mode 100644
index 000000000000..13931c5c3556
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_mu160_info.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+             uint32_t length_copy_d                                           : 19,
+                      mcs_copy_d                                              :  4,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  3;
+             uint32_t length_copy_e                                           : 19,
+                      mcs_copy_e                                              :  4,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  3;
+             uint32_t length_copy_f                                           : 19,
+                      mcs_copy_f                                              :  4,
+                      tail_copy_f                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_g                                           : 19,
+                      mcs_copy_g                                              :  4,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t reserved_2                                              :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+             uint32_t reserved_4                                              :  3,
+                      tail_copy_d                                             :  6,
+                      mcs_copy_d                                              :  4,
+                      length_copy_d                                           : 19;
+             uint32_t reserved_5                                              :  3,
+                      tail_copy_e                                             :  6,
+                      mcs_copy_e                                              :  4,
+                      length_copy_e                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_f                                             :  6,
+                      mcs_copy_f                                              :  4,
+                      length_copy_f                                           : 19;
+             uint32_t reserved_7                                              :  3,
+                      tail_copy_g                                             :  6,
+                      mcs_copy_g                                              :  4,
+                      length_copy_g                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB                                             18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK                                            0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB                                                19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB                                                22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK                                               0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET                                      0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET                                  0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB                                     29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB                                     31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK                                    0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK                                        0xe0000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_mu20_info.h b/hw/fig/v1/vht_sig_b_mu20_info.h
new file mode 100644
index 000000000000..c51ac839a757
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_mu20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 16,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      mu_user_number                                          :  3,
+                      reserved_0                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      mu_user_number                                          :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 16;
+#endif
+};
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB                                              15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK                                             0x0000ffff
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB                                                 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB                                                 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK                                                0x000f0000
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB                                      26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB                                      28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK                                     0x1c000000
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_mu40_info.h b/hw/fig/v1/vht_sig_b_mu40_info.h
new file mode 100644
index 000000000000..0eb4c164cca1
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_mu40_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy                                             : 17,
+                      mcs_copy                                                :  4,
+                      tail_copy                                               :  6,
+                      reserved_1                                              :  5;
+#else
+             uint32_t mu_user_number                                          :  3,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 17;
+             uint32_t reserved_1                                              :  5,
+                      tail_copy                                               :  6,
+                      mcs_copy                                                :  4,
+                      length_copy                                             : 17;
+#endif
+};
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB                                                 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB                                                 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK                                                0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB                                          28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK                                         0x18000000
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB                                         16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK                                        0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET                                         0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB                                            17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB                                            20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK                                           0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK                                         0xf8000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_mu80_info.h b/hw/fig/v1/vht_sig_b_mu80_info.h
new file mode 100644
index 000000000000..33d0f1bc08fc
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_mu80_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB                                                 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB                                                 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK                                                0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET                                       0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_su160_info.h b/hw/fig/v1/vht_sig_b_su160_info.h
new file mode 100644
index 000000000000..7ba503724b56
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_su160_info.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+             uint32_t length_copy_d                                           : 21,
+                      vhtb_reserved_copy_d                                    :  2,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  2,
+                      rx_ndp_copy_d                                           :  1;
+             uint32_t length_copy_e                                           : 21,
+                      vhtb_reserved_copy_e                                    :  2,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  2,
+                      rx_ndp_copy_e                                           :  1;
+             uint32_t length_copy_f                                           : 21,
+                      vhtb_reserved_copy_f                                    :  2,
+                      tail_copy_f                                             :  6,
+                      reserved_6                                              :  2,
+                      rx_ndp_copy_f                                           :  1;
+             uint32_t length_copy_g                                           : 21,
+                      vhtb_reserved_copy_g                                    :  2,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  2,
+                      rx_ndp_copy_g                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+             uint32_t rx_ndp_copy_d                                           :  1,
+                      reserved_4                                              :  2,
+                      tail_copy_d                                             :  6,
+                      vhtb_reserved_copy_d                                    :  2,
+                      length_copy_d                                           : 21;
+             uint32_t rx_ndp_copy_e                                           :  1,
+                      reserved_5                                              :  2,
+                      tail_copy_e                                             :  6,
+                      vhtb_reserved_copy_e                                    :  2,
+                      length_copy_e                                           : 21;
+             uint32_t rx_ndp_copy_f                                           :  1,
+                      reserved_6                                              :  2,
+                      tail_copy_f                                             :  6,
+                      vhtb_reserved_copy_f                                    :  2,
+                      length_copy_f                                           : 21;
+             uint32_t rx_ndp_copy_g                                           :  1,
+                      reserved_7                                              :  2,
+                      tail_copy_g                                             :  6,
+                      vhtb_reserved_copy_g                                    :  2,
+                      length_copy_g                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB                                             20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK                                            0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET                                   0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB                                      21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB                                      22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK                                     0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK                                            0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET                            0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET                            0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET                            0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET                            0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET                            0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET                            0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET                                      0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET                            0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK                                     0x80000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_su20_info.h b/hw/fig/v1/vht_sig_b_su20_info.h
new file mode 100644
index 000000000000..2c7f11ba3c21
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_su20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      vhtb_reserved                                           :  3,
+                      tail                                                    :  6,
+                      reserved                                                :  5,
+                      rx_ndp                                                  :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  5,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  3,
+                      length                                                  : 17;
+#endif
+};
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_su40_info.h b/hw/fig/v1/vht_sig_b_su40_info.h
new file mode 100644
index 000000000000..467259003e8d
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_su40_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved                                                :  4,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy                                             : 19,
+                      vhtb_reserved_copy                                      :  2,
+                      tail_copy                                               :  6,
+                      reserved_copy                                           :  4,
+                      rx_ndp_copy                                             :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  4,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 19;
+             uint32_t rx_ndp_copy                                             :  1,
+                      reserved_copy                                           :  4,
+                      tail_copy                                               :  6,
+                      vhtb_reserved_copy                                      :  2,
+                      length_copy                                             : 19;
+#endif
+};
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB                                       19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB                                       20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK                                      0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB                                            27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK                                           0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB                                         18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK                                        0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET                               0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB                                  19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB                                  20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK                                 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB                                       27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB                                       30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK                                      0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK                                        0x80000000
+
+#endif
diff --git a/hw/fig/v1/vht_sig_b_su80_info.h b/hw/fig/v1/vht_sig_b_su80_info.h
new file mode 100644
index 000000000000..92ceeab9b476
--- /dev/null
+++ b/hw/fig/v1/vht_sig_b_su80_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB                                              20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK                                             0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB                                       21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB                                       22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK                                      0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET                             0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET                             0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET                                       0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET                             0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK                                      0x80000000
+
+#endif
diff --git a/hw/fig/v1/wbm2sw_completion_ring_rx.h b/hw/fig/v1/wbm2sw_completion_ring_rx.h
new file mode 100644
index 000000000000..e40a7e796a87
--- /dev/null
+++ b/hw/fig/v1/wbm2sw_completion_ring_rx.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM2SW_COMPLETION_RING_RX_H_
+#define _WBM2SW_COMPLETION_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8
+
+struct wbm2sw_completion_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      wbm_internal_error                                      :  1;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t buffer_phys_addr_39_32                                  :  8,
+                      sw_buffer_cookie                                        : 20,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie                                        : 20,
+                      buffer_phys_addr_39_32                                  :  8;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET                                  0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB                                     3
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB                                     5
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK                                    0x00000038
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB                                   13
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB                                   14
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK                                  0x00006000
+
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK                                     0x00008000
+
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK                     0x00010000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET                          0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB                             17
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB                             18
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK                            0x00060000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET                           0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB                              19
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB                              23
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK                             0x00f80000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET                            0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB                               24
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB                               25
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK                              0x03000000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET                             0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB                                26
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB                                30
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK                               0x7c000000
+
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB          0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB          7
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK         0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET    0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK      0x00000100
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET   0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK     0x00000200
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK         0x00000400
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET        0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK          0x00000800
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK           0x00002000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB            15
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB            26
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK           0x07ff8000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET              0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                0xf0000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000010
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB      0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB      31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK  0x00000004
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB         3
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB         16
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK        0x0001fff8
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK          0x00020000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK        0x00040000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK        0x00080000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET       0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK         0x00100000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET   0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK     0x00800000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK              0x01000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK              0x02000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK          0x04000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB        27
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB        28
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK       0x18000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB        29
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB        30
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK       0x60000000
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET                      0x00000018
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB                        7
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK                       0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET                           0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB                              8
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB                              27
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK                             0x0fffff00
+
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/fig/v1/wbm2sw_completion_ring_tx.h b/hw/fig/v1/wbm2sw_completion_ring_tx.h
new file mode 100644
index 000000000000..6031ed7e119e
--- /dev/null
+++ b/hw/fig/v1/wbm2sw_completion_ring_tx.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM2SW_COMPLETION_RING_TX_H_
+#define _WBM2SW_COMPLETION_RING_TX_H_
+
+#include "tx_rate_stats_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
+
+struct wbm2sw_completion_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      cookie_conversion_status                                :  1,
+                      wbm_internal_error                                      :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      cookie_conversion_status                                :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB                                      3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB                                      3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK                                     0x00000008
+
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB                                   4
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB                                   5
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK                                  0x00000030
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB                            13
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB                            16
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK                           0x0001e000
+
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB                            17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB                            17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK                           0x00020000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB                         18
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB                         29
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK                        0x3ffc0000
+
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB                      30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB                      30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK                     0x40000000
+
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET                          0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB                             0
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB                             23
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK                            0x00ffffff
+
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET                             0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB                                24
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB                                30
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK                               0x7f000000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                   0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                      31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                      31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                     0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET                             0x00000010
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB                                0
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB                                7
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK                               0x000000ff
+
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET                                 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB                                    8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB                                    8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK                                   0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET                                  0x00000010
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB                                     9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB                                     9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK                                    0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                         0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB                            10
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB                            12
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK                           0x00001c00
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET                           0x00000010
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB                              13
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB                              31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK                             0xffffe000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB        0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB        0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK       0x00000001
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                  0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                     1
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                     3
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                    0x0000000e
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB               4
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB               7
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK              0x000000f0
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                   8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                   8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                  0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                   9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                   9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                  0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                    10
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                    11
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                   0x00000c00
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                    12
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                    15
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                   0x0000f000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET           0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB              16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB              16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK             0x00010000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                  0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                     17
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                     28
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                    0x1ffe0000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                    29
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                    31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                   0xe0000000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET        0x00000018
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB           0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB           31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK          0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET                                 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB                                    0
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB                                    15
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK                                   0x0000ffff
+
+#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET                                        0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_TID_LSB                                           16
+#define WBM2SW_COMPLETION_RING_TX_TID_MSB                                           19
+#define WBM2SW_COMPLETION_RING_TX_TID_MASK                                          0x000f0000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB                        20
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB                        27
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK                       0x0ff00000
+
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/fig/v1/wbm_buffer_ring.h b/hw/fig/v1/wbm_buffer_ring.h
new file mode 100644
index 000000000000..b1532e15595b
--- /dev/null
+++ b/hw/fig/v1/wbm_buffer_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+#endif
+};
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                       0x00000000
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                          0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                         0xffffffff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                      0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                         0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                         7
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                        0x000000ff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                  0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                     8
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                     11
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                    0x00000f00
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                       0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                          12
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                         0xfffff000
+
+#endif
diff --git a/hw/fig/v1/wbm_link_descriptor_ring.h b/hw/fig/v1/wbm_link_descriptor_ring.h
new file mode 100644
index 000000000000..851807aa4c1c
--- /dev/null
+++ b/hw/fig/v1/wbm_link_descriptor_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          desc_addr_info;
+#else
+             struct   buffer_addr_info                                          desc_addr_info;
+#endif
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET             0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB                0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK               0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET            0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB               0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB               7
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK              0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET        0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB           8
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB           11
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK          0x00000f00
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET             0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB                12
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK               0xfffff000
+
+#endif
diff --git a/hw/fig/v1/wbm_release_ring.h b/hw/fig/v1/wbm_release_ring.h
new file mode 100644
index 000000000000..e86d52753912
--- /dev/null
+++ b/hw/fig/v1/wbm_release_ring.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      reserved_2a                                             :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2b                                             : 22,
+                      wbm_internal_error                                      :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 28,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      reserved_2b                                             : 22,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_7a                                             : 28;
+#endif
+};
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET    0x00000000
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB       0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK      0xffffffff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET   0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB      0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB      7
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK     0x000000ff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB  8
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB  11
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET    0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB       12
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK      0xfffff000
+
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB                                  0
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB                                  2
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK                                 0x00000007
+
+#define WBM_RELEASE_RING_RESERVED_2A_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2A_LSB                                            3
+#define WBM_RELEASE_RING_RESERVED_2A_MSB                                            5
+#define WBM_RELEASE_RING_RESERVED_2A_MASK                                           0x00000038
+
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB                                    6
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB                                    8
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK                                   0x000001c0
+
+#define WBM_RELEASE_RING_RESERVED_2B_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2B_LSB                                            9
+#define WBM_RELEASE_RING_RESERVED_2B_MSB                                            30
+#define WBM_RELEASE_RING_RESERVED_2B_MASK                                           0x7ffffe00
+
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET                                  0x00000008
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK                                    0x80000000
+
+#define WBM_RELEASE_RING_RESERVED_3A_OFFSET                                         0x0000000c
+#define WBM_RELEASE_RING_RESERVED_3A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_3A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_3A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_4A_OFFSET                                         0x00000010
+#define WBM_RELEASE_RING_RESERVED_4A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_4A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_4A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_5A_OFFSET                                         0x00000014
+#define WBM_RELEASE_RING_RESERVED_5A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_5A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_5A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_6A_OFFSET                                         0x00000018
+#define WBM_RELEASE_RING_RESERVED_6A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_6A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_6A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_7A_OFFSET                                         0x0000001c
+#define WBM_RELEASE_RING_RESERVED_7A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_7A_MSB                                            27
+#define WBM_RELEASE_RING_RESERVED_7A_MASK                                           0x0fffffff
+
+#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET                                       0x0000001c
+#define WBM_RELEASE_RING_LOOPING_COUNT_LSB                                          28
+#define WBM_RELEASE_RING_LOOPING_COUNT_MSB                                          31
+#define WBM_RELEASE_RING_LOOPING_COUNT_MASK                                         0xf0000000
+
+#endif
diff --git a/hw/fig/v1/wbm_release_ring_rx.h b/hw/fig/v1/wbm_release_ring_rx.h
new file mode 100644
index 000000000000..a68bc8115a82
--- /dev/null
+++ b/hw/fig/v1/wbm_release_ring_rx.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_RX_H_
+#define _WBM_RELEASE_RING_RX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4
+
+struct wbm_release_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 14,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t reserved_3a                                             : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      reserved_2a                                             : 14,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         19
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x000fffc0
+
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET                             0x00000008
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB                                20
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB                                31
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK                               0xfff00000
+
+#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET                                      0x0000000c
+#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB                                         0
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB                                         31
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK                                        0xffffffff
+
+#endif
diff --git a/hw/fig/v1/wbm_release_ring_tx.h b/hw/fig/v1/wbm_release_ring_tx.h
new file mode 100644
index 000000000000..d1412153c6ae
--- /dev/null
+++ b/hw/fig/v1/wbm_release_ring_tx.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_TX_H_
+#define _WBM_RELEASE_RING_TX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4
+
+struct wbm_release_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 26;
+             uint32_t tqm_status_number                                       : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t reserved_2a                                             : 26,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t tqm_status_number                                       : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         31
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0xffffffc0
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   31
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0xffffffff
+
+#endif
diff --git a/hw/fig/v1/wcss_seq_hwiobase.h b/hw/fig/v1/wcss_seq_hwiobase.h
new file mode 100644
index 000000000000..b96752690ea3
--- /dev/null
+++ b/hw/fig/v1/wcss_seq_hwiobase.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef WCSS_SEQ_HWIOBASE_H
+#define WCSS_SEQ_HWIOBASE_H
+
+#define UMAC_NOC_BASE                                                 0x140000
+#define UMAC_NOC_BASE_SIZE                                          0x00004480
+#define UMAC_NOC_BASE_PHYS                                          0x00140000
+
+#define PHYA0_BASE                                                    0x300000
+#define PHYA0_BASE_SIZE                                             0x00300000
+#define PHYA0_BASE_PHYS                                             0x00300000
+
+#define PHYA1_BASE                                                    0x600000
+#define PHYA1_BASE_SIZE                                             0x00300000
+#define PHYA1_BASE_PHYS                                             0x00600000
+
+#define DMAC_BASE                                                     0x900000
+#define DMAC_BASE_SIZE                                              0x00080000
+#define DMAC_BASE_PHYS                                              0x00900000
+
+#define UMAC_BASE                                                     0xa00000
+#define UMAC_BASE_SIZE                                              0x0004d000
+#define UMAC_BASE_PHYS                                              0x00a00000
+
+#define PMAC0_BASE                                                    0xa80000
+#define PMAC0_BASE_SIZE                                             0x00040000
+#define PMAC0_BASE_PHYS                                             0x00a80000
+
+#define PMAC1_BASE                                                    0xac0000
+#define PMAC1_BASE_SIZE                                             0x00040000
+#define PMAC1_BASE_PHYS                                             0x00ac0000
+
+#define WFSS_AMCSS_BASE                                               0xb00000
+#define WFSS_AMCSS_BASE_SIZE                                        0x00040000
+#define WFSS_AMCSS_BASE_PHYS                                        0x00b00000
+
+#define CXC_BASE                                                      0xb40000
+#define CXC_BASE_SIZE                                               0x00010000
+#define CXC_BASE_PHYS                                               0x00b40000
+
+#define WFSS_PMM_BASE                                                 0xb50000
+#define WFSS_PMM_BASE_SIZE                                          0x00002401
+#define WFSS_PMM_BASE_PHYS                                          0x00b50000
+
+#define WFSS_CC_BASE                                                  0xb60000
+#define WFSS_CC_BASE_SIZE                                           0x00008000
+#define WFSS_CC_BASE_PHYS                                           0x00b60000
+
+#define WCMN_CORE_BASE                                                0xb68000
+#define WCMN_CORE_BASE_SIZE                                         0x000008a9
+#define WCMN_CORE_BASE_PHYS                                         0x00b68000
+
+#define WIFI_CFGBUS_APB_TSLV_BASE                                     0xb6b000
+#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS                              0x00b6b000
+
+#define WFSS_CFGBUS_BASE                                              0xb6c000
+#define WFSS_CFGBUS_BASE_SIZE                                       0x000000a0
+#define WFSS_CFGBUS_BASE_PHYS                                       0x00b6c000
+
+#define WIFI_CFGBUS_AHB_TSLV_BASE                                     0xb6d000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS                              0x00b6d000
+
+#define UMAC_ACMT_BASE                                                0xb6e000
+#define UMAC_ACMT_BASE_SIZE                                         0x00001000
+#define UMAC_ACMT_BASE_PHYS                                         0x00b6e000
+
+#define WCSS_CC_BASE                                                  0xb80000
+#define WCSS_CC_BASE_SIZE                                           0x00010000
+#define WCSS_CC_BASE_PHYS                                           0x00b80000
+
+#define PMM_TOP_BASE                                                  0xb90000
+#define PMM_TOP_BASE_SIZE                                           0x00010000
+#define PMM_TOP_BASE_PHYS                                           0x00b90000
+
+#define WCSS_TOP_CMN_BASE                                             0xba0000
+#define WCSS_TOP_CMN_BASE_SIZE                                      0x00004000
+#define WCSS_TOP_CMN_BASE_PHYS                                      0x00ba0000
+
+#define WCSS_CFGBUS_BASE                                              0xba4000
+#define WCSS_CFGBUS_BASE_SIZE                                       0x00008000
+#define WCSS_CFGBUS_BASE_PHYS                                       0x00ba4000
+
+#define MSIP_BASE                                                     0xbb0000
+#define MSIP_BASE_SIZE                                              0x00010000
+#define MSIP_BASE_PHYS                                              0x00bb0000
+
+#define RFA_BASE                                                      0xbc0000
+#define RFA_BASE_SIZE                                               0x00040000
+#define RFA_BASE_PHYS                                               0x00bc0000
+
+#define DBG_BASE                                                     0x1000000
+#define DBG_BASE_SIZE                                               0x00100000
+#define DBG_BASE_PHYS                                               0x01000000
+
+#define Q6SS_WLAN_BASE                                               0x1100000
+#define Q6SS_WLAN_BASE_SIZE                                         0x00100000
+#define Q6SS_WLAN_BASE_PHYS                                         0x01100000
+
+#endif
diff --git a/hw/fig/v1/wcss_seq_hwioreg_umac.h b/hw/fig/v1/wcss_seq_hwioreg_umac.h
new file mode 100644
index 000000000000..8dffd65930da
--- /dev/null
+++ b/hw/fig/v1/wcss_seq_hwioreg_umac.h
@@ -0,0 +1,2413 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOREG_UMAC_H
+#include "seq_hwio.h"
+#include "wcss_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+#include "HALhwio.h"
+#else
+#include "msmhwio.h"
+#endif
+
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS                                                        (0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK                                                               0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK                                            0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT                                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS                                           (0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK                                            0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR                                            0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK                                       0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR                                                        0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK                    0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK                       0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT                            1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK                            0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK                                    0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT                                        12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK                                     0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT                                        11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK                                     0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT                                        10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK                                     0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT                                         9
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS                                                   (0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR                                                    0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR                                                                0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK                                 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT                                         24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK                                   0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT                                         16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK                                     0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK                                       0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT                                          0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n)                                            (0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK                                                    0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn                                                       31
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR                                                0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK                                           0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR                                                            0x1
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK                                   0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT                                       0
+
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS                                                       (0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK                                                              0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR                                                        0x00000000
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR                                                                    0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK                                                 0x2
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT                                                   1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK                                                  0x1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT                                                    0
+
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n)                                                      (0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn                                                                 63
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT                                                             0
+
+#define WBM_REG_REG_BASE                                                                                        (UMAC_BASE      + 0x00034000)
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x)                                                                        ((x) + 0x40)
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)                                                                   ((x) + 0x130)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK                                                       0x7fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT                                                           2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK                                                    0x2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT                                                      1
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)                                                                      ((x) + 0x134)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK                                0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT                                        16
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK                                          0xffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT                                               0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)                                                   ((x) + 0x138)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)                                                   ((x) + 0x13c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK                                    0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT                                             8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK                                         0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT                                            0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)                                               ((x) + 0x140)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)                                               ((x) + 0x144)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)                                               ((x) + 0x148)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)                                               ((x) + 0x14c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)                                                          ((x) + 0x150)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)                                                            ((x) + 0x24c)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                       0xffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                              8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x8000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                        27
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0x51c)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xfffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)                                                             ((x) + 0x52c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                            0x8000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                   27
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                       (0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                   (0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                       (0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                   (0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS                                                                            (0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK                                                                                  0x3f
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR                                                                             0x00000000
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK                                                                        0xffffffff
+#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR                                                                                         0x3
+#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK                                                         0x20
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT                                                            5
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK                                                         0x10
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT                                                            4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                    0x8
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                      3
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                    0x4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                      2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                             0x2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                               1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                         0x1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                           0
+
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS                                                                     (0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK                                                                     0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR                                                                      0x00000000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK                                                                 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR                                                                                  0x3
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK                                                          0xffe00000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT                                                                  21
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK                                                            0x1f0000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT                                                                  16
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK                                                                  0xf800
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT                                                                      11
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK                                                                   0x7c0
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT                                                                       6
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK                                                                    0x3e
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT                                                                       1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK                                                                       0x1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT                                                                         0
+
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                 (0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                      0x3ff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                  0x00000020
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                              0x1
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK                                                 0x200
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT                                                     9
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK                                                 0x100
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT                                                     8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                            0x80
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                               7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                            0x40
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                               6
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                     0x20
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                        5
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                  0x10
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                     4
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                     0x8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                       3
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                               0x7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                 0
+
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                   (0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK                                                                      0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn                                                                             255
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR                                                                       0x00000000
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                  0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                   0x1
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                          0
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)                                                                  ((x) + 0x3010)
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)                                                               ((x) + 0x3040)
+
+#define REO_REG_REG_BASE                                                                                               (UMAC_BASE      + 0x00038000)
+
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                                                                             ((x) + 0x0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT                                                        28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT                                                        24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT                                                        20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT                                                        16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT                                                        12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT                                                         8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT                                                         4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT                                                         0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)                                                                 ((x) + 0xc)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)                                                                 ((x) + 0x10)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS                                                          (0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR                                                           0x76043210
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK                            0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT                                    28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK                             0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT                                    24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK                              0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT                                    20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK                               0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT                                    16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK                                0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT                                    12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK                                 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT                                     8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS                                                          (0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x6666ba98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS                                                          (0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT                                    0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS                                                          (0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT                                    0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)                                                             ((x) + 0x38)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK                                       0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT                                               28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK                                        0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT                                               24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK                                         0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT                                               20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK                                          0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT                                               16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK                                           0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT                                               12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK                                            0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT                                                8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK                                             0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK                                              0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)                                                             ((x) + 0x3c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT                                              24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT                                              20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT                                              16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT                                              12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT                                               8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS                                                      (0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK                   0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT                           28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK                    0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT                           24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK                     0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT                           20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK                      0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT                           16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK                       0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT                           12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK                        0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT                            8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT                            0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS                                                      (0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK               0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT                       28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK                   0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT                          24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK                    0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT                          20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK                     0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT                          16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK                      0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT                          12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK                       0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT                           8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT                            0
+
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS                                                                         (0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK                                                                            0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR                                                                          0x00000000
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR                                                                                      0x3
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)            \
+                in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK                                                                   0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT                                                                         0
+
+#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)                                                                             ((x) + 0x6c)
+
+#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)                                                                             ((x) + 0x70)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK                                                  0x100000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT                                                        20
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK                                                          0x80000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT                                                               19
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                                    0x40000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                         18
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                                 0x3e000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                      13
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                                    0x1f00
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                         8
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                             0xff
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                                0
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                                                                       ((x) + 0x344)
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK                                                                  0xffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                                                                         8
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK                                                               0x400000
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     22
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x7d0)
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0x7d4)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                                                                            ((x) + 0x7d8)
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)                                                                        ((x) + 0x7dc)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                           0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                                   16
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK                                                               0xffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT                                                                    0
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                                                                          ((x) + 0x7e0)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0x7e4)
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0x7e8)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)                                                            ((x) + 0x7f4)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x818)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x81c)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x820)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x824)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x828)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x82c)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)                                                                     ((x) + 0x830)
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x844)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x848)
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0xc08)
+
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x8000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     27
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x8000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                                27
+
+#define HWIO_REO_R0_MISC_CFG_ADDR(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_PHYS(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_OFFS                                                                                      (0x1458)
+#define HWIO_REO_R0_MISC_CFG_RMSK                                                                                             0x1
+#define HWIO_REO_R0_MISC_CFG_POR                                                                                       0x00000000
+#define HWIO_REO_R0_MISC_CFG_POR_RMSK                                                                                  0xffffffff
+#define HWIO_REO_R0_MISC_CFG_ATTR                                                                                                   0x3
+#define HWIO_REO_R0_MISC_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x))
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK                                                                        0x1
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT                                                                          0
+
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS                                                                            (0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK                                                                                 0x1ff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR                                                                             0x0000002d
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR                                                                                         0x3
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK                                                             0x1fe
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT                                                                 1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK                                                                           0x1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT                                                                             0
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                                                                       ((x) + 0x1468)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                                                                       ((x) + 0x146c)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                                                                       ((x) + 0x1470)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                                                                       ((x) + 0x1474)
+
+#define HWIO_REO_R0_MISC_CTL_ADDR(x)                                                                                   ((x) + 0x14dc)
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK                                                                         0x1e00000
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT                                                                                21
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK                                                                     0x1e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT                                                                           17
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                          (0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                      (0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                          (0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                      (0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_CREDIT_ADDR(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_PHYS(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_OFFS                                                                                        (0x16d0)
+#define HWIO_REO_R0_CREDIT_RMSK                                                                                        0xffffffff
+#define HWIO_REO_R0_CREDIT_POR                                                                                         0x00000000
+#define HWIO_REO_R0_CREDIT_POR_RMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_ATTR                                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_ADDR(x))
+#define HWIO_REO_R0_CREDIT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x))
+#define HWIO_REO_R0_CREDIT_VAL_BMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_VAL_SHFT                                                                                             0
+
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS                                                                        (0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK                                                                               0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR                                                                         0x00000002
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK                                                                        0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT                                                                          0
+
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS                                                                         (0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR                                                                          0x00000000
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR                                                                                      0x1
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x))
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT                                                                              0
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK                                                 0x2000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT                                                     13
+
+#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_OFFS                                                                                   (0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_RMSK                                                                                          0x7
+#define HWIO_REO_R0_LPM_FW_CTRL_POR                                                                                    0x00000000
+#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK                                                                               0xffffffff
+#define HWIO_REO_R0_LPM_FW_CTRL_ATTR                                                                                                0x3
+#define HWIO_REO_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                           0x4
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                             2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                           0x2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                             1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                                0x1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                                  0
+
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS                                                                             (0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK                                                                                   0x3f
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR                                                                              0x00000000
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR                                                                                          0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x))
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK                                                         0x20
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT                                                            5
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK                                                                   0x10
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT                                                                      4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK                                                                0x8
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT                                                                  3
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK                                                            0x4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT                                                              2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK                                                                      0x2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT                                                                        1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK                                                                  0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT                                                                    0
+
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS                                                         (0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK                                                         0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR                                                          0x00000000
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR                                                                      0x3
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)            \
+                in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK                                                   0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT                                                            0
+
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                        (0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                              0x7f
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR                                                                         0x00000000
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                                     0x1
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                                   0x40
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                      6
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                                   0x20
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                      5
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                         0x10
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                            4
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                            0x8
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                              3
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                      0x7
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                        0
+
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                          (0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK                                                                             0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn                                                                                    255
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR                                                                              0x00000000
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR                                                                                          0x1
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                        0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                                 0
+
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                                                                             ((x) + 0x3028)
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                                                                            ((x) + 0x3070)
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                                                                            ((x) + 0x3074)
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                                                                            ((x) + 0x3078)
+
+#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)                                                                            ((x) + 0x30b8)
+
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK                                                             0x80
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT                                                                7
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK                                                    0x40
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT                                                       6
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK                                                     0x20
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT                                                        5
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK                                                           0x10
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT                                                              4
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK                                                          0x8
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT                                                            3
+
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x8000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT                                                           27
+
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                    (0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                (0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                    (0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                (0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK                                                          0x80000000
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT                                                                  31
+
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK                                                            0x8000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT                                                                15
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK                                                        0x4000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT                                                            14
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK                                                                0x2000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT                                                                    13
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK                                                            0x1000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT                                                                12
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK                                               0x800
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT                                                  11
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK                                               0x400
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT                                                  10
+
+#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS                                                                             (0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK                                                                                    0xf
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR                                                                              0x00000000
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK                                                                         0xffffffff
+#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR                                                                                          0x3
+#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                     0x8
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                       3
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                     0x4
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                       2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                              0x2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                                1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                          0x1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                            0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS                                                                          (0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK                                                                             0x1ffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR                                                                           0x00000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)            \
+                in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK                                             0x2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT                                               1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK                                                     0x1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT                                                       0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK                                                     0x20000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT                                                             29
+
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS                                                     (0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR                                                      0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR                                                                  0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT                                                        0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS                                              (0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS                                              (0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS                                                                           (0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK                                                                                0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR                                                                            0x00000710
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR                                                                                        0x3
+#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)            \
+                in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK                                                                          0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT                                                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS                                                   (0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR                                                    0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK                                               0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR                                                                0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK                                              0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT                                                 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS                                                    (0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR                                                     0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR                                                                 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT                                                   0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS                                                (0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK                                                      0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR                                                 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR                                                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK                                           0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS                                                 (0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK                                                 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR                                                  0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR                                                              0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK                                       0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT                                                0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS                                              (0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK                                              0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR                                               0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR                                                           0x3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK                                    0xffff0000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT                                            16
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK                            0xfff0
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT                                 4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK                                  0x8
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT                                    3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK                                       0x4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT                                         2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT                               1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK                                         0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT                                           0
+
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS                                                                       (0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS                                                                      (0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK                                                                         0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR                                                                       0x00000000
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR                                                                                   0x3
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK                                                             0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                   0
+
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS                                                                       (0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS                                                                 (0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK                                                                        0xf
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR                                                                  0x00000000
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR                                                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x))
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK                                                0x8
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT                                                  3
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x4
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT                                                   2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT                                                   1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT                                                0
+
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS                                                                     (0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK                                                                     0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR                                                                      0x00000000
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR                                                                                  0x1
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK                                                               0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT                                                                        0
+
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS                                                                  (0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR                                                                   0x00000000
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR                                                                               0x1
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK                                                            0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT                                                                     0
+
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                  (0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                        0xff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                   0x00000000
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                               0x1
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                             0x80
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                             0x40
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                6
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                      0x20
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                         5
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                   0x10
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                      4
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                      0x8
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                        3
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                0x7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                  0
+
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                    (0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn                                                                              127
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR                                                                        0x00000000
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                    0x1
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                           0
+
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT                                                           7
+
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK                                             0x40
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT                                                6
+
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS                                                (0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK                                                       0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR                                                 0x0000000a
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK                                                 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT                                                   0
+
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS                                                                   (0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK                                                                         0x1f
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK                                                   0x10
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT                                                      4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK                                                    0x8
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT                                                      3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK                                                    0x4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT                                                      2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK                                                    0x2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT                                                      1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_LINK_ID_ADDR(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_PHYS(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_OFFS                                                                       (0x170)
+#define HWIO_UMCMN_R0_LINK_ID_RMSK                                                                           0xffff
+#define HWIO_UMCMN_R0_LINK_ID_POR                                                                        0x000052c8
+#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_LINK_ID_ATTR                                                                                    0x3
+#define HWIO_UMCMN_R0_LINK_ID_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x))
+#define HWIO_UMCMN_R0_LINK_ID_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m)
+#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v)
+#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x))
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK                                                               0x80
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT                                                                  7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK                                                               0x40
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT                                                                  6
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK                                                               0x38
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT                                                                  3
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK                                                                0x7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK                                                    0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT                                                        14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK                                                0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT                                                    13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK                                                    0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT                                                        12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK                                                     0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT                                                        11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK                                                     0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT                                                        10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK                                                     0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT                                                         9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK                                                     0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT                                                         8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK                                                       0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT                                                          7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK                                                       0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT                                                          6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK                                                       0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT                                                          5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK                                                       0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT                                                          4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK                                                         0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT                                                           3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK                                                        0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT                                                          2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK                                                         0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT                                                           1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK                                                        0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT                                                          0
+
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS                                                             (0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK                                                                    0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR                                                              0x00000000
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK                                                         0xffffffff
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR                                                                          0x3
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS                                                (0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK                                                   0x1ffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR                                                 0x00000000
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK                   0x1fe00
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT                         9
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK                    0x1fe
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT                        1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK                         0x1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT                           0
+
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                             0x1ff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK                                           0x100
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT                                               8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK                                            0x80
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT                                               7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK                                            0x40
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT                                               6
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK                                            0x20
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT                                               5
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n)                                                 (0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn                                                             7
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR                                                     0x00000000
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR                                                                 0x3
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT                                                         0
+
+#define MAC_TCL_REG_REG_BASE                                                                           (UMAC_BASE      + 0x00044000)
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                                                     ((x) + 0x20)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK                                  0x800000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT                                        23
+
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK                                      0x200000
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT                                            21
+
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n)                                                      ((base) + 0X74 + (0x4*(n)))
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT                                                   17
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT                                                     14
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT                                                          12
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT                                                        8
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT                                                       7
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT                                                          3
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT                                                            1
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT                                                                   0
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n)                                                        ((base) + 0X174 + (0x4*(n)))
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK                                                                0xffffffff
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK                                              0x800000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT                                                    23
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK                                                        0x40
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT                                                           6
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK                                                    0x20
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT                                                       5
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS                                                              (0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK                                                                     0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR                                                               0x00000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK                                                          0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR                                                                           0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)            \
+                in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK                                                        0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT                                                          1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK                                                        0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT                                                          0
+
+#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS                                                                   (0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK                                                                          0x7
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                           0x4
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                             2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                           0x2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                             1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x8c8)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0x8cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK                                                0xfffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                                                            ((x) + 0x8d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                                                          ((x) + 0x8d8)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                                                   ((x) + 0x8e4)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                                                   ((x) + 0x8e8)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                        ((x) + 0x8f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                         16
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                       0x7fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                            0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                        ((x) + 0x8fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                 0xffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0x910)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0x914)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0x918)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x940)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                             0x8000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                    27
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                              (0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                          (0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                              (0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                          (0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                              0x7f
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                   0x40
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                      6
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                   0x20
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                      5
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                                  0x10000
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                       16
+
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                             0x10000
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                  16
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS                                                                  (0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK                                                                       0x1ff
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR                                                                   0x00000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK                                                              0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR                                                                               0x3
+#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                                  0x100
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                                      8
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK                                                           0xc0
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT                                                              6
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK                                                        0x3f
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT                                                           0
+
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                          (0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK                                                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn                                                                    511
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR                                                              0x00000000
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR                                                                          0x1
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                        0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                 0
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                                                            ((x) + 0x2000)
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                                                            ((x) + 0x2004)
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                                                            ((x) + 0x2008)
+
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                               0x1000000
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                      24
+
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS                                                                           (0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK                                                                                0x7ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR                                                                            0x000003ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR                                                                                        0x3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)            \
+                in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x))
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x))
+
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK                                                                         0x400
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT                                                                            10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK                                                                        0x200
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT                                                                            9
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK                                                                        0x100
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT                                                                            8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK                                                                         0x80
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT                                                                            7
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK                                                                         0x40
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT                                                                            6
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK                                                                         0x20
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT                                                                            5
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK                                                                         0x10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT                                                                            4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK                                                                          0x8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT                                                                            3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK                                                                          0x4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT                                                                            2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK                                                                          0x2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT                                                                            1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK                                                                          0x1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT                                                                            0
+
+#define TQM_REG_REG_BASE                                                                                         (UMAC_BASE      + 0x0003c000)
+#define TQM_REG_REG_BASE_SIZE                                                                                    0x4000
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS                                                                          (0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK                                                                          0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR                                                                           0x00000000
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT                                                           0
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS                                                                          (0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK                                                                             0x7ffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR                                                                           0x00011100
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                              0x40000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                   18
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                           0x3e000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                13
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                              0x1f00
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                   8
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                       0xff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                          0
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS                                                                   (0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK                                                                        0x1ff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR                                                                    0x000001fe
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK                                          0x100
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT                                              8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK                                            0x80
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT                                               7
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK                                            0x40
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT                                               6
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK                                            0x20
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT                                               5
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK                                            0x10
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT                                               4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK                                             0x8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT                                               3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK                                             0x4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT                                               2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK                                             0x2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT                                               1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK                                              0x1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT                                                0
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS                                                                  (0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK                                                                    0x3fefff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR                                                                   0x00080170
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR                                                                               0x3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK                                            0x200000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT                                                  21
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK                                         0x100000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT                                               20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK                                      0x80000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT                                           19
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK                                             0x40000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT                                                  18
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK                                                    0x20000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT                                                         17
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK                                                        0x10000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT                                                             16
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK                                          0x8000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT                                              15
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK                                                 0x4000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT                                                     14
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK                                                0x2000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT                                                    13
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK                                                     0x800
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT                                                        11
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK                                                      0x400
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT                                                         10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK                                                0x200
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT                                                    9
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK                                             0x100
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT                                                 8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK                                               0x80
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT                                                  7
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK                                                       0x40
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT                                                          6
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK                                                  0x20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT                                                     5
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK                                                 0x10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT                                                    4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK                                               0x8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT                                                 3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK                                                 0x4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT                                                   2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK                                               0x2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT                                                 1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK                                             0x1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT                                               0
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS                                                           (0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS                                                                 (0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS                                                           (0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS                                                                 (0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#endif /* WCSS_SEQ_HWIOREG_UMAC_H */
diff --git a/hw/fig/v1/wcss_version.h b/hw/fig/v1/wcss_version.h
new file mode 100644
index 000000000000..76c77489574d
--- /dev/null
+++ b/hw/fig/v1/wcss_version.h
@@ -0,0 +1,5 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#define WCSS_VERSION 3150

From e45e64c61d072e51dcb56b4eafcfce71db9eef7d Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 24 Oct 2025 06:04:18 -0700
Subject: [PATCH 051/290] fw-api: CL 30757804 - update fw common interface
 files

Change-Id: Ifb26156474046b2082cff96207f24ef1b2378c42
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4433c3c61d57..fc5cf6f504bb 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -22714,16 +22714,16 @@ typedef struct {
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_GET(flags) WMI_GET_BITS(flags, 0, 1)
-#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_SET(flags, value) WMI_GET_BITS(flags, 0, 1, value)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
 
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_GET(flags) WMI_GET_BITS(flags, 1, 1)
-#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_GET_BITS(flags, 1, 1, value)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value)
 
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 2, 1)
-#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_SET(flags, value) WMI_GET_BITS(flags, 2, 1, value)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value)
 
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 3, 1)
-#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_GET_BITS(flags, 3, 1, value)
+#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_params*/

From 087c11ed7baca507711952450934915ee87e8530 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 25 Oct 2025 18:01:43 -0700
Subject: [PATCH 052/290] fw-api: CL 30768407 - update fw common interface
 files

Change-Id: I853386b65af99a4ae6f531132155d65031e74efc
CRs-Fixed: 3830439
---
 fw/htt.h | 45 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 1242e91980aa..62c8e5c32107 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -272,9 +272,10 @@
  * 3.142 Add T2H GLOBAL_PEER_ID_UNMAP def, update H2T MPDUQ_OR_MSDUQ_INFO def.
  * 3.143 Add T2H HAPS msg def.
  * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info.
+ * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 144
+#define HTT_CURRENT_VERSION_MINOR 145
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -5867,7 +5868,7 @@ enum htt_srng_ring_id {
  *    |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------|
  *    |rsvd1|ED|DT|OV|PS|SS|      ring_id    |     pdev_id    |    msg_type   |
  *    |--------------------------+-----+-----+--------------------------------|
- *    | rsvd2  |RX|RXHDL|   CLD  | CLC | CLM |           ring_buffer_size     |
+ *    |rsvd2|HE|RX|RXHDL|   CLD  | CLC | CLM |           ring_buffer_size     |
  *    |-----------------------------------------------------------------------|
  *    |                           packet_type_enable_flags_0                  |
  *    |-----------------------------------------------------------------------|
@@ -5901,6 +5902,7 @@ enum htt_srng_ring_id {
  *     CLD = config_length_data
  *     RXHDL = rx_hdr_len
  *     RX = rxpcu_filter_enable_flag
+ *     HE = rx_hdr_len extension
  * The message is interpreted as follows:
  * dword0 - b'0:7   - msg_type: This will be set to
  *                    0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG)
@@ -5966,7 +5968,18 @@ enum htt_srng_ring_id {
  *                    be zero which means allow all frames for MD at RxOLE
  *                    host wil fiter out frames.
  *                    RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out)
- *          b'28:31 - rsvd2: Reserved for future use
+ *          b'28    - rx_hdr_len_ext:
+ *                    Extend rx_hdr_len to 3 bits with b'28 as MSb.
+ *                    Valid combined values:
+ *                    001 - 64bytes
+ *                    010 - 128bytes
+ *                    011 - 256bytes
+ *                    100 - 512bytes
+ *                    101 - 1024bytes
+ *                    110 - 2048bytes
+ *                    111 - max bytes supported by HW
+ *                    default - 128 bytes
+ *          b'29:31 - rsvd2: Reserved for future use
  * dword2 - b'0:31  - packet_type_enable_flags_0:
  *                    Enable MGMT packet from 0b0000 to 0b1001
  *                    bits from low to high: FP, MD, MO - 3 bits
@@ -6133,7 +6146,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
              config_length_data:3,
              rx_hdr_len:        2,
              rxpcu_filter_enable_flag:1,
-             rsvd2:             4;
+             rx_hdr_len_ext:    1,
+             rsvd2:             3;
     A_UINT32 packet_type_enable_flags_0;
     A_UINT32 packet_type_enable_flags_1;
     A_UINT32 packet_type_enable_flags_2;
@@ -6335,14 +6349,25 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
 
 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M                 0x06000000
 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S                 25
+#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M             0x10000000
+#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S             28
+#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_M             0x7
+#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_S             0
 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \
-                (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \
-                                      HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S)
+    ((((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M) >> \
+                (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) | \
+     (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \
+                HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S))
 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \
-            do { \
-                HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \
-                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\
-            } while(0)
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK, _val); \
+        ((_var) |= (((_val) << \
+            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) & \
+            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M); \
+        ((_var) |= (((_val) << \
+            (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) & \
+            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M); \
+    } while(0)
 
 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M               0x08000000
 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S               27

From bf5cdf0750ad963070d9b616511f41716b263a4c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 25 Oct 2025 18:04:33 -0700
Subject: [PATCH 053/290] fw-api: CL 30768408 - update fw common interface
 files

Change-Id: I9579a79aba4eff17c08222c7216d4ca8b0f5530b
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 9a37c333fcb0..33cef71f72cd 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6599,6 +6599,7 @@ typedef struct {
 
 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */
 #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */
+#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */
 #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */
 #define HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */
 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4

From d83d27f4e99694fd9dcc7bc53d729b3fbfa965e4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 28 Oct 2025 03:06:13 -0700
Subject: [PATCH 054/290] fw-api: CL 30786115 - update fw common interface
 files

Change-Id: Icbd97fffd99e341def40e46e5c32d86470dc468b
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 10 +++++-----
 fw/wmi_unified.h  | 13 ++++++++-----
 fw/wmi_version.h  |  2 +-
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 8024d8896a58..8400b6e72d96 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1514,7 +1514,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_coex_stats,
     WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param,
-    WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param,
     WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
     WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params,
     WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param,
@@ -2096,7 +2096,7 @@ typedef enum {
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
     OP(WMI_PEER_ASSOC_V2_CMDID) \
     OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \
-    OP(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \
+    OP(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -5931,9 +5931,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID);
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
 
 /* WMI command to control Dynamic Power Save - AP Assisting role config */
-#define WMITLV_TABLE_WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
-WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
+#define WMITLV_TABLE_WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
 
 
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index fc5cf6f504bb..986f250f1d07 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -741,6 +741,9 @@ typedef enum {
     /** data traffic monitoring */
     WMI_VDEV_TRAFFIC_MONITORING_CMDID,
 
+    /** WMI cmd used to control DPS Assisting AP role config */
+    WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID,
+
     /* peer specific commands */
 
     /** create a peer */
@@ -1769,8 +1772,6 @@ typedef enum {
     WMI_ENERGY_MGMT_PUO_CONFIG_CMDID,
     /** WMI cmd used to control ECO mode config */
     WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID,
-    /** WMI cmd used to control DPS Assisting AP role config */
-    WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID,
 } WMI_CMD_ID;
 
 typedef enum {
@@ -40225,7 +40226,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
-        WMI_RETURN_STRING(WMI_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -52341,11 +52342,13 @@ typedef enum {
 
 typedef struct {
     /** TLV tag and len; tag equals
-    * WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param */
+    * WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param */
     A_UINT32 tlv_header;
+    /* VDEV identifier */
+    A_UINT32 vdev_id;
     /** holds a wmi_dps_assisting_role_e value */
     A_UINT32 config;
-} wmi_energy_mgmt_dps_assisting_role_config_cmd_fixed_param;
+} wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param;
 
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index e1156570d2a4..27dd950af897 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1664
+#define __WMI_REVISION_ 1665
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 86accef058b6c748f87d3ca6868b45525c20a789 Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <prakashp@qti.qualcomm.com>
Date: Tue, 28 Oct 2025 10:04:56 -0700
Subject: [PATCH 055/290] fw-api: fig: Update config macros for
 REO_R0_RBM_DESTINATION_RING_CTRL

Update fig config macros for REO_R0_RBM_DESTINATION_RING_CTR config.

Change-Id: I708b7953b6f950196838d367517ec81afb4cabd6
CRs-Fixed: 4335486
---
 hw/fig/v1/wcss_seq_hwioreg_umac.h | 62 +++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/hw/fig/v1/wcss_seq_hwioreg_umac.h b/hw/fig/v1/wcss_seq_hwioreg_umac.h
index 8dffd65930da..4fb391d29729 100644
--- a/hw/fig/v1/wcss_seq_hwioreg_umac.h
+++ b/hw/fig/v1/wcss_seq_hwioreg_umac.h
@@ -2409,5 +2409,67 @@
 #define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
 #define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
 #define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS                                                                (0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK                                             0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT                                                     28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK                                              0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT                                                     24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK                                               0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT                                                     20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK                                                0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT                                                     16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK                                                 0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT                                                     12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK                                                  0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT                                                      8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT                                                      0
 
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS                                                                (0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK                                            0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT                                                    28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK                                             0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT                                                    24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK                                              0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT                                                    20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK                                               0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT                                                    16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK                                                0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT                                                    12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK                                                 0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT                                                     8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT                                                      0
 #endif /* WCSS_SEQ_HWIOREG_UMAC_H */

From 1e71b980ce61c7ca9444560e135ffe4de2490d83 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 29 Oct 2025 18:01:58 -0700
Subject: [PATCH 056/290] fw-api: CL 30797342 - update fw common interface
 files

Change-Id: I6d56b728032003ccbe2de1675b398f78fcbddf15
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 5 ++++-
 fw/wmi_version.h | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 986f250f1d07..898d49d8cff1 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19996,7 +19996,10 @@ typedef enum {
          *      0 - Disable RTT Bandwidth downgrade
          *      1 - Enable RTT Bandwidth downgrade
          */
-        WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_BW_DOWNGRADE,    /* 0x8014 */
+        WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_BW_DOWNGRADE,/* 0x8014 */
+
+        /* customized txop for vendor configuration in unit of us */
+        WMI_VDEV_PARAM_SU_TXOP_BURST_LIMIT_US,         /* 0x8015 */
 
     /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/
 } WMI_VDEV_PARAM;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 27dd950af897..7212e31676a9 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1665
+#define __WMI_REVISION_ 1666
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 695cac28c269e980fb2ffeb807a018256f57de30 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 30 Oct 2025 18:02:04 -0700
Subject: [PATCH 057/290] fw-api: CL 30811728 - update fw common interface
 files

Change-Id: Ie3be7ba138884d1b7b37c7cc6a0190e5fb6c771f
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 11 ++++++++---
 fw/wmi_version.h |  2 +-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 898d49d8cff1..796c346a970f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19820,10 +19820,15 @@ typedef enum {
     WMI_VDEV_PARAM_CCK_SUPPORT,                           /* 0xCB */
 
     /*
-     * value 0 | disable dynamic D-SMPS base on RSSI feature
-     * value 1 | enable dynamic D-SMPS base on RSSI feature
+     * BIT 0:
+     *     value 0 | disable D-SMPS
+     *     value 1 | enable D-SMPS
+     * BIT 1:
+     *     value 0 | disable dynamic D-SMPS base on RSSI feature
+     *     value 1 | enable dynamic D-SMPS base on RSSI feature
      */
-    WMI_VDEV_PARAM_ENABLE_DYN_DSMPS_BASE_ON_RSSI,         /* 0xCC */
+    WMI_VDEV_PARAM_DSMPS_CONTROL,                         /* 0xCC */
+
 
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7212e31676a9..908e0d60c7ac 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1666
+#define __WMI_REVISION_ 1667
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9afaa54389032cef6aeceb00828831a0f0fdfb6a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 31 Oct 2025 18:01:45 -0700
Subject: [PATCH 058/290] fw-api: CL 30825844 - update fw common interface
 files

Change-Id: Ia2dbfe8758675e22e5a83f7b372446658efb394a
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 796c346a970f..cec5f724d7cf 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -21978,6 +21978,8 @@ typedef struct {
  */
 #define WMI_PEER_PARAM_UNSOL_PROBE_RESP_INTVL          0x2C
 
+#define WMI_PEER_PARAM_SET_MESH_NODE                   0x2D
+#define WMI_PEER_PARAM_SET_QUALCOMM_NODE               0x2E
 
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 908e0d60c7ac..813ee2fa93d7 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1667
+#define __WMI_REVISION_ 1668
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 944d10b79af8636c9c832ccf1d91d02bba716198 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 1 Nov 2025 18:01:39 -0700
Subject: [PATCH 059/290] fw-api: CL 30839650 - update fw common interface
 files

Change-Id: I1cf616cf0b2c617232adc0f8ac291bd5162e1320
CRs-Fixed: 3830439
---
 fw/htt.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 62c8e5c32107..58459e69d820 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -6363,10 +6363,10 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
         HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK, _val); \
         ((_var) |= (((_val) << \
             HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) & \
-            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M); \
+            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M)); \
         ((_var) |= (((_val) << \
             (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) & \
-            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M); \
+            HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M)); \
     } while(0)
 
 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M               0x08000000

From acacaa33efc0aa79d58f00bbacc9db6b8c2da676 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 2 Nov 2025 12:01:42 -0800
Subject: [PATCH 060/290] fw-api: CL 30839654 - update fw common interface
 files

Change-Id: If37f224e01f36acd050db62a3a80df9d15cc3684
CRs-Fixed: 3830439
---
 fw/enet.h | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/fw/enet.h b/fw/enet.h
index 54a561eb1db8..d8f84c595287 100644
--- a/fw/enet.h
+++ b/fw/enet.h
@@ -92,8 +92,8 @@ typedef PREPACK struct {
 } POSTPACK vlan_hdr_t;
 
 #define ETHERTYPE_IS_EAPOL_WAPI(typeorlen)           \
-			((typeorlen) == ETHERTYPE_PAE ||  \
-			(typeorlen) == ETHERTYPE_WAI)
+    ((typeorlen) == ETHERTYPE_PAE ||  \
+     (typeorlen) == ETHERTYPE_WAI)
 
 #define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
 
@@ -102,11 +102,11 @@ typedef PREPACK struct {
 #endif
 
 #ifndef ETHERTYPE_AARP
-#define	ETHERTYPE_AARP	0x80f3		/* Internal QCA AARP protocol */
+#define ETHERTYPE_AARP  0x80f3 /* Internal QCA AARP protocol */
 #endif
 
 #ifndef ETHERTYPE_IPX
-#define ETHERTYPE_IPX    0x8137    /* IPX over DIX protocol */
+#define ETHERTYPE_IPX   0x8137 /* IPX over DIX protocol */
 #endif
 
 #ifndef ETHERTYPE_ARP
@@ -133,6 +133,18 @@ typedef PREPACK struct {
 #define ETHERTYPE_PAE   0x888E /* EAP over LAN (EAPOL) */
 #endif
 
+  #ifndef EAPOL_KEY_TYPE
+  #define EAPOL_KEY_TYPE 0x3 /* EAP over LAN (EAPOL) */
+  #endif
+
+  #ifndef EAPOL_PAIRKEY
+  #define EAPOL_PAIRKEY 0x008
+  #endif
+
+  #ifndef EAPOL_GRPKEY
+  #define EAPOL_GRPKEY 0x00
+  #endif
+
 #ifndef ETHERTYPE_WAI
 #define ETHERTYPE_WAI   0x88B4 /* WAPI */
 #endif

From 94549d98c8bc6b3d2fe77bd898f35fa8fe1c419e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 4 Nov 2025 02:34:06 -0800
Subject: [PATCH 061/290] fw-api: CL 30855102 - update fw common interface
 files

Change-Id: I2f228a3a620ba41f7c487038b6708063a3404d1c
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 33cef71f72cd..aa24e860103d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6892,11 +6892,19 @@ typedef struct {
     A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
     /* STA side trigger stats */
     A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES];
+#if 0
+    /* NOTE:
+     * The tx_mcs_ext_3 field is being reverted at least temporarily,
+     * to work around message size limits in certain targets.
+     * If/when this revert becomes permanent, this "#if 0" block will
+     * be removed altogether.
+     */
     /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */
     A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+#endif
 
 /*
- * NOTE: THIS STRUCT HAS ONLY 4 BYTES OF SPACE LEFT
+ * NOTE: THIS STRUCT HAS ONLY 20 BYTES OF SPACE LEFT
  * WITHIN THE TARGET'S HTT_STATS_TLV_MAX_LEN SIZE LIMIT.
  */
 } htt_stats_tx_pdev_rate_stats_tlv;

From beec9a1e3885bb68c9b0bbb1e5796b15cea73446 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 4 Nov 2025 02:35:39 -0800
Subject: [PATCH 062/290] fw-api: CL 30855107 - update fw common interface
 files

Change-Id: I1a17054d7942208a440a26ed2dfecb2e593bd3fe
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 22 +++++++++++++
 fw/wmi_unified.h  | 83 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 106 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 8400b6e72d96..ae59bcbbd347 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1518,6 +1518,9 @@ typedef enum {
     WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2,
     WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params,
     WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2097,6 +2100,7 @@ typedef enum {
     OP(WMI_PEER_ASSOC_V2_CMDID) \
     OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \
     OP(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \
+    OP(WMI_WLAN_MODE_REQ_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2438,6 +2442,8 @@ typedef enum {
     OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \
     OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \
     OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \
+    OP(WMI_FW_READY_IND_EVENTID) \
+    OP(WMI_WLAN_MODE_RESP_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5935,6 +5941,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
 
+/* WMI cmd to specify the driver's mode of operation */
+#define WMITLV_TABLE_WMI_WLAN_MODE_REQ_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param, wmi_wlan_mode_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8092,6 +8103,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, wmi_pdev_set_tx_chainmask_comp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID);
 
+/* WMI Event to indicate Firmware is ready for mode configuration by host */
+#define WMITLV_TABLE_WMI_FW_READY_IND_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param, wmi_fw_ready_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_FW_READY_IND_EVENTID);
+
+/* WMI Event to acknowledge the driver mode sent by host */
+#define WMITLV_TABLE_WMI_WLAN_MODE_RESP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, wmi_wlan_mode_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_RESP_EVENTID);
+
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index cec5f724d7cf..66e421fe9c2e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -385,6 +385,9 @@ typedef enum {
     /** initialize the wlan sub system */
     WMI_INIT_CMDID = 0x1,
 
+    /** WMI command to specify the driver's mode of operation */
+    WMI_WLAN_MODE_REQ_CMDID,
+
     /* Scan specific commands */
 
     /** start scan request to FW  */
@@ -1790,6 +1793,23 @@ typedef enum {
      */
     WMI_IFACE_COMBINATION_IND_EVENTID,
 
+    /** WMI evt that indicates FW basic initializations are done, and FW
+     *  is ready to receive the WLAN mode specification from the host.
+     *
+     * mode selection handshake:
+     *     host <-- WMI_FW_READY_IND_EVENTID <---- target
+     *     host --> WMI_WLAN_MODE_REQ_CMDID -----> target
+     *     host <-- WMI_WLAN_MODE_RESP_EVENTID <-- target
+     * precedes the WLAN initialization handshake:
+     *     host <-- WMI_SERVICE_READY_EVENTID <--- target
+     *     host --> WMI_INIT_CMDID --------------> target
+     *     host <-- WMI_READY_EVENTID <----------- target
+     */
+    WMI_FW_READY_IND_EVENTID,
+    /* WMI evt to acknowledge the driver mode specified by host */
+    WMI_WLAN_MODE_RESP_EVENTID,
+
+
     /** Scan specific events */
     WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
 
@@ -40237,6 +40257,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
+        WMI_RETURN_STRING(WMI_WLAN_MODE_REQ_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -52361,6 +52382,68 @@ typedef struct {
 } wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param;
 
 
+/* WMI evt to indicate FW is ready */
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param */
+    A_UINT32 tlv_header;
+} wmi_fw_ready_ind_event_fixed_param;
+
+typedef enum {
+    WMI_DRIVER_MODE_MISSION,
+    WMI_DRIVER_MODE_FTM,
+    WMI_DRIVER_MODE_OFF,
+} WMI_DRIVER_MODE;
+
+/** WMI command to indicate the driver mode of operation */
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* This indicates driver mode of operation from host */
+    A_UINT32 mode; /* refer to WMI_DRIVER_MODE enum */
+} wmi_wlan_mode_req_cmd_fixed_param;
+
+typedef enum {
+    WMI_DRIVER_MODE_RESP_SUCCESS,
+    WMI_DRIVER_MODE_RESP_FAILURE,
+} WMI_WLAN_DRIVER_MODE_RESP_STATUS;
+
+typedef enum {
+    WMI_DRIVER_FAIL_REASON_UNKNOWN_MODE,
+    /* In FTM mode, initiate PHY error */
+    WMI_DRIVER_FAIL_REASON_FTM_PHY_INIT_ERR,
+    /* For both MISSION and FTM mode, set power error */
+    WMI_DRIVER_FAIL_REASON_POWER_INIT_ERR,
+    WMI_DRIVER_FAIL_REASON_MODE_OFF_ERR,
+} WMI_WLAN_MODE_FAILURE_REASON;
+
+/* Host/Firmware can get/set the status bits using below macros */
+#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_GET(status) WMI_GET_BITS(status, 0, 16)
+#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_SET(status, value) WMI_SET_BITS(status, 0, 16, value)
+
+#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_GET(mode) WMI_GET_BITS(mode, 16, 16)
+#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_SET(mode, value) WMI_GET_BITS(mode, 16, 16, value)
+
+/* WMI evt to acknowledge the driver mode sent by host */
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param */
+    A_UINT32 tlv_header;
+    /* The status word contains the following bitfields:
+     * bits 15:0  - Indicates whether the FW has accepted
+     *              (WMI_DRIVER_MODE_RESP_SUCCESS) or rejected
+     *              (WMI_DRIVER_MODE_RESP_FAILURE) the driver mode
+     *              specified by the host.
+     * bits 31:16 - Indicates the reason if the FW has rejected
+     *              the driver mode.
+     *              This field is only relevant if the status is
+     *              WMI_DRIVER_MODE_RESP_FAILURE.
+     */
+    A_UINT32 status;
+} wmi_wlan_mode_resp_event_fixed_param;
+
+
 
 /* ADD NEW DEFS HERE */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 813ee2fa93d7..b3270921e3c5 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1668
+#define __WMI_REVISION_ 1669
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 6971130183dcb8c12148d2ca1651fb82d1c5b8f1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 7 Nov 2025 18:01:55 -0800
Subject: [PATCH 063/290] fw-api: CL 30894242 - update fw common interface
 files

Change-Id: I421ec14ad5a2f6ab81760f32498c8d31c5eceb5f
CRs-Fixed: 3830439
---
 fw/htt.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index 58459e69d820..73198698a3fc 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -273,9 +273,10 @@
  * 3.143 Add T2H HAPS msg def.
  * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info.
  * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG
+ * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 145
+#define HTT_CURRENT_VERSION_MINOR 146
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -5526,6 +5527,7 @@ enum htt_srng_ring_id {
     HTT_RXDMA_WBM_BUF0_RING,       /* used for SFE Datapath */
     HTT_RXDMA_WBM_BUF1_RING,       /* used for PPE Datapath */
     HTT_RXDMA_WBM_BUF2_RING,       /* used for MGMT path */
+    HTT_RXOLE_ASE_STATUS_RING,     /* RxOLE2SW ASE Status ring */
     /* Add Other SRING which can't be directly configured by host software above this line */
 };
 

From e05c61d0f770df1e9b9b5947ed46bab01192ef40 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 8 Nov 2025 12:02:07 -0800
Subject: [PATCH 064/290] fw-api: CL 30905405 - update fw common interface
 files

Change-Id: Ie96a5d6f003e9d7be022324e8a0b1a8fa00c8a31
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 16 ++++++++--------
 fw/wmi_version.h |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 66e421fe9c2e..333da66baef9 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -38726,8 +38726,8 @@ typedef struct {
      (WMI_GET_BITS(uhr_cap_mac[1], 0, 2) << 3))
 #define WMI_UHRCAP_MAC_UPDATE_IND_TIM_SET(uhr_cap_mac, value) \
     do { \
-        WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7) \
-        WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)) \
+        WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7); \
+        WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)); \
     } while (0)
 
 /* Bit 34: Bounded ESS */
@@ -38785,32 +38785,32 @@ typedef struct {
 #define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 0, 1)
 #define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 0, 1, value)
+    WMI_SET_BITS(npca_capability, 0, 1, value)
 
 #define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 1, 4)
 #define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 1, 5, value)
+    WMI_SET_BITS(npca_capability, 1, 5, value)
 
 #define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 5, 6)
 #define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 5, 6, value)
+    WMI_SET_BITS(npca_capability, 5, 6, value)
 
 #define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 11, 6)
 #define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 11, 6, value)
+    WMI_SET_BITS(npca_capability, 11, 6, value)
 
 #define WMI_CAP_EXT2_NPCA_QSRC_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 17, 2)
 #define WMI_CAP_EXT2_NPCA_QSRC_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 17, 2, value)
+    WMI_SET_BITS(npca_capability, 17, 2, value)
 
 #define WMI_CAP_EXT2_NPCA_MOPLEN_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 19, 1)
 #define WMI_CAP_EXT2_NPCA_MOPLEN_SET(npca_capability, value) \
-    WMI_sET_BITS(npca_capability, 19, 1, value)
+    WMI_SET_BITS(npca_capability, 19, 1, value)
 
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b3270921e3c5..c04994234144 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1669
+#define __WMI_REVISION_ 1670
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From b78f944843fd82cbeef07a9edbdb778855b76098 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 8 Nov 2025 12:03:45 -0800
Subject: [PATCH 065/290] fw-api: CL 30906519 - update fw common interface
 files

Change-Id: Ic58937d5996d1dbd5d1a28efa3834f7aafeb3327
CRs-Fixed: 3830439
---
 fw/htt.h          | 27 +++++++++++++++++++++++++--
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  | 16 +++++++++++++++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 73198698a3fc..8c6472c5cc46 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -274,9 +274,10 @@
  * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info.
  * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG
  * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def.
+ * 3.147 Add direct_refill flag in SRING_SETUP msg.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 146
+#define HTT_CURRENT_VERSION_MINOR 147
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -5494,7 +5495,8 @@ PREPACK struct htt_sring_setup_t {
              prefetch_timer_cfg:  3,
              response_required:   1,
              ipa_drop_flag:      1,
-             reserved1:          11;
+             direct_refill:      1,
+             reserved1:          10;
     A_UINT32 ipa_drop_low_threshold:    8,
              ipa_drop_high_threshold:   8,
              reserved:                  16;
@@ -5852,6 +5854,27 @@ enum htt_srng_ring_id {
             ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \
         } while (0)
 
+#define HTT_SRING_SETUP_IPA_DROP_FLAG_M        0x00100000
+#define HTT_SRING_SETUP_IPA_DROP_FLAG_S        20
+#define HTT_SRING_SETUP_IPA_DROP_FLAG_GET(_var) \
+        (((_var) & HTT_SRING_SETUP_IPA_DROP_FLAG_M) >> \
+                HTT_SRING_SETUP_IPA_DROP_FLAG_S)
+#define HTT_SRING_SETUP_IPA_DROP_FLAG_SET(_var, _val) \
+        do { \
+            HTT_CHECK_SET_VAL(HTT_SRING_SETUP_IPA_DROP_FLAG, _val); \
+            ((_var) |= ((_val) << HTT_SRING_SETUP_IPA_DROP_FLAG_S)); \
+        } while (0)
+
+#define HTT_SRING_SETUP_DIRECT_REFILL_M        0x00200000
+#define HTT_SRING_SETUP_DIRECT_REFILL_S        21
+#define HTT_SRING_SETUP_DIRECT_REFILL_GET(_var) \
+        (((_var) & HTT_SRING_SETUP_DIRECT_REFILL_M) >> \
+                HTT_SRING_SETUP_DIRECT_REFILL_S)
+#define HTT_SRING_SETUP_DIRECT_REFILL_SET(_var, _val) \
+        do { \
+            HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DIRECT_REFILL, _val); \
+            ((_var) |= ((_val) << HTT_SRING_SETUP_DIRECT_REFILL_S)); \
+        } while (0)
 
 /**
  * @brief host -> target RX ring selection config message
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 6adcdbfac4e5..4a53da1202d4 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -738,6 +738,7 @@ typedef  enum  {
 
     WMI_SERVICE_CCK_RX_SUPPORT_5GHZ = 475, /* Indicates FW supports CCK RX in 5 GHz band */
     WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */
+    WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 333da66baef9..03c69db4bb15 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5106,8 +5106,16 @@ typedef struct {
      *      country supports SP regulatory rules.
      *      Refer to the below defintions of WMI_RSRC_CFG_HOST_SERVICE_FLAG
      *      AFC_TRIGGER_ON_DEFAULT_CC_EVENT_GET and _SET macros.
+     *  Bit 23
+     *      This bit will set by host to inform FW that direct refill to
+     *      SW2RxDMA ring is supported by the host and the ring which is
+     *      directly refilled by HOST will be indicated in the
+     *      HTT_H2T_MSG_TYPE_SRING_SETUP and FW should refill the Rx buffers
+     *      to the secondary refill ring.
+     *      Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG
+     *      DIRECT_REFILL_SUPPORT_GET and _SET macros.
      *
-     *  Bits 31:23 - Reserved
+     *  Bits 31:24 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -5686,6 +5694,12 @@ typedef struct {
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_AFC_TRIGGER_ON_DEFAULT_CC_EVENT_SET(host_service_flags, val) \
         WMI_SET_BITS(host_service_flags, 22, 1, val)
 
+/* This bit is used to inform FW that HOST supports direct Rx buffers refill to the SW2RxDMA ring*/
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_GET(host_service_flags) \
+         WMI_GET_BITS(host_service_flags, 23, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_SET(host_service_flags, val) \
+         WMI_SET_BITS(host_service_flags, 23, 1, val)
+
 
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c04994234144..744f2302c459 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1670
+#define __WMI_REVISION_ 1671
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 555fdda348a9abd8f283045dcab43539b5b070ac Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 11 Nov 2025 12:02:01 -0800
Subject: [PATCH 066/290] fw-api: CL 30924456 - update fw common interface
 files

Change-Id: Idd3d384b1e572f65742d7e21c20b288740e14ae9
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   1 +
 fw/wmi_tlv_defs.h |  55 +++++++++
 fw/wmi_unified.h  | 295 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 4 files changed, 350 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 4a53da1202d4..b0ea65d4cce8 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -739,6 +739,7 @@ typedef  enum  {
     WMI_SERVICE_CCK_RX_SUPPORT_5GHZ = 475, /* Indicates FW supports CCK RX in 5 GHz band */
     WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */
     WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */
+    WMI_SERVICE_NAN_STANDARD_MODE_SUPPORT = 478, /* Indicates FW supports NAN in standard mode (supplicant-based NAN architecture model) */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index ae59bcbbd347..a7c39df3bde0 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1521,6 +1521,15 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_ctrl_config_param,
+    WMITLV_TAG_STRUC_wmi_nan_disc_band_config_param,
+    WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2101,6 +2110,9 @@ typedef enum {
     OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \
     OP(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \
     OP(WMI_WLAN_MODE_REQ_CMDID) \
+    OP(WMI_NAN_ENABLE_CMDID) \
+    OP(WMI_NAN_CONFIG_CMDID) \
+    OP(WMI_NAN_DISABLE_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2444,6 +2456,10 @@ typedef enum {
     OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \
     OP(WMI_FW_READY_IND_EVENTID) \
     OP(WMI_WLAN_MODE_RESP_EVENTID) \
+    OP(WMI_NAN_ENABLE_RSP_EVENTID) \
+    OP(WMI_NAN_NEXT_DW_INFO_EVENTID) \
+    OP(WMI_NAN_DISABLE_CNF_EVENTID) \
+    OP(WMI_NAN_DISABLE_IND_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -4144,6 +4160,25 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_CMDID);
 
+/* NAN Enable Command */
+#define WMITLV_TABLE_WMI_NAN_ENABLE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param, wmi_nan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_CMDID);
+
+/* NAN Config Command */
+#define WMITLV_TABLE_WMI_NAN_CONFIG_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, wmi_nan_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CONFIG_CMDID);
+
+/* NAN Disable Command */
+#define WMITLV_TABLE_WMI_NAN_DISABLE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, wmi_nan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CMDID);
+
 /* NAN Data Get Capabilities Cmd */
 #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX)
@@ -6822,6 +6857,26 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_STARTED_CLUSTER_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_JOINED_CLUSTER_EVENTID);
 
+/* NAN Enable Response Event */
+#define WMITLV_TABLE_WMI_NAN_ENABLE_RSP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, wmi_nan_enable_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_RSP_EVENTID);
+
+/* NAN Next DW Info Event */
+#define WMITLV_TABLE_WMI_NAN_NEXT_DW_INFO_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, wmi_nan_next_dw_info_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_NEXT_DW_INFO_EVENTID);
+
+/* NAN Disable Confirm Event */
+#define WMITLV_TABLE_WMI_NAN_DISABLE_CNF_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param, wmi_nan_disable_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CNF_EVENTID);
+
+/* NAN Disable Indication Event */
+#define WMITLV_TABLE_WMI_NAN_DISABLE_IND_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, wmi_nan_disable_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_IND_EVENTID);
+
 /* Coex report antenna isolation event */
 #define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 03c69db4bb15..577576be46f9 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1503,6 +1503,13 @@ typedef enum {
     WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN),
     /** Command to handle OEM's NAN specific opaque data */
     WMI_NAN_OEM_DATA_CMDID,
+    /** Command to enable NAN mode */
+    WMI_NAN_ENABLE_CMDID,
+    /** Command to update NAN configuration */
+    WMI_NAN_CONFIG_CMDID,
+    /** Command to disable NAN mode */
+    WMI_NAN_DISABLE_CMDID,
+
 
     /** Modem power state command */
     WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX),
@@ -2543,6 +2550,14 @@ typedef enum {
     WMI_NAN_DMESG_EVENTID,
     /** Event to deliver OEM's NAN specific opaque data */
     WMI_NAN_OEM_DATA_EVENTID,
+    /** Event response to NAN enable command */
+    WMI_NAN_ENABLE_RSP_EVENTID,
+    /** Event indicating information about next Discovery Window (DW) */
+    WMI_NAN_NEXT_DW_INFO_EVENTID,
+    /** Event confirmation to NAN disable command */
+    WMI_NAN_DISABLE_CNF_EVENTID,
+    /** Event notifying FW triggered NAN disable indication */
+    WMI_NAN_DISABLE_IND_EVENTID,
 
     /* Coex Event */
     WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
@@ -5256,12 +5271,34 @@ typedef struct {
      * BIT 2-31: Reserved
      */
     A_UINT32 dp_haps_config;
+
+    /**
+     * @brief nan_config_word
+     * BIT 0 : 7 -> Minimum lead time (in milliseconds) that firmware
+     *              must ensure before sending WMI_NAN_NEXT_DW_INFO_EVENTID,
+     *              as configured via host INI settings.
+     * BIT 8 : 31 -> Reserved
+     */
+    union {
+        A_UINT32 nan_config_word;
+        struct {
+            A_UINT32
+                dw_notif_lead_time: 8,
+                reserved2: 24;
+        };
+    };
 } wmi_resource_config;
+
 #define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_GET(word32) \
     WMI_GET_BITS(word32, 0, 1)
 #define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_SET(word32, value) \
     WMI_SET_BITS(word32, 0, 1, value)
 
+#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_GET(word32) \
+        WMI_GET_BITS(word32, 0, 8)
+#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_SET(word32, value) \
+        WMI_SET_BITS(word32, 0, 8, value)
+
 #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
     (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1))))
 #define WMI_MSDU_FLOW_AST_ENABLE_SET(msdu_flow_config0, ast_x, enable) \
@@ -30106,6 +30143,155 @@ typedef struct {
      */
 } wmi_nan_oem_data_cmd_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_param */
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+/*
+* TLVs following this structure:
+*     wmi_nan_ctrl_config_param nan_ctrl_config[];
+*     wmi_nan_disc_band_config_param nan_disc_band_config[];
+*/
+} wmi_nan_enable_cmd_fixed_param;
+
+typedef enum {
+    WMI_NAN_DISC_BAND_PRI_2GHZ = 0x01,
+    WMI_NAN_DISC_BAND_SEC_5GHZ = 0x02,
+} WMI_NAN_DISC_BANDS;
+
+/* Macros for parsing nan_ctrl_flags field */
+#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_RANGING(param) \
+        WMI_GET_BITS(param, 0, 1)
+#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_RANGING(param, val) \
+        WMI_SET_BITS(param, 0, 1, val)
+#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_EARLY_DW_TERMINATION(param) \
+        WMI_GET_BITS(param, 1, 1)
+#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_EARLY_DW_TERMINATION(param, val) \
+        WMI_SET_BITS(param, 1, 1, val)
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param */
+    A_UINT32 master_pref; /* Master preference value for cluster formation */
+   /* Cluster ID used for synchronization.
+    * The value (lower 4 bytes) is sent in network byte order (big-endian).
+    * If set to 0, the firmware will generate a randomized cluster ID.
+    */
+    A_UINT32 cluster_id;
+    /* Service ID value for publish beacon */
+    A_UINT32 service_id_bcn_val;
+    /* Max hop count allowed for cluster joining */
+    A_UINT32 hop_count_limit_val;
+    /* Service ID value for subscribe beacon */
+    A_UINT32 subscribe_sid_beacon_val;
+    A_UINT32 config_tx_rx_chains; /* TX/RX chain configuration */
+    /* Bitfield for NAN control options,
+     * use WMI_NAN_CTRL_FLAGS_SET_* and WMI_NAN_CTRL_FLAGS_GET_* macros
+     * for access
+     */
+    union {
+        struct {
+            A_UINT32
+                /* Enable ranging capability */
+                enable_ranging: 1,
+
+                /* Enable early termination of Discovery Window */
+                enable_early_dw_termination:1,
+
+                reserved: 30; /* reserved for future use */
+        };
+        A_UINT32 nan_ctrl_flags; /* 32-bit control flags word */
+    };
+    A_UINT32 supp_disc_bands; /* Possible values are enum WMI_NAN_DISC_BANDS */
+/*
+* TLVs following this structure:
+*     wmi_nan_disc_band_config_param nan_disc_band_config[];
+*/
+} wmi_nan_ctrl_config_param;
+
+/* Macros for parsing scan_params field */
+#define WMI_NAN_DISC_SCAN_PARAMS_GET_DWELL_MS(param) \
+        WMI_GET_BITS(param, 0, 16)
+#define WMI_NAN_DISC_SCAN_PARAMS_SET_DWELL_MS(param, val) \
+        WMI_SET_BITS(param, 0, 16, val)
+
+#define WMI_NAN_DISC_SCAN_PARAMS_GET_INTERVAL_SEC(param) \
+        WMI_GET_BITS(param, 16, 16)
+#define WMI_NAN_DISC_SCAN_PARAMS_SET_INTERVAL_SEC(param, val) \
+        WMI_SET_BITS(param, 16, 16, val)
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_band_config_param */
+    /* Channel frequency (in MHz) for discovery */
+    A_UINT32 chan_freq;
+    /* Encoded scan parameters (use WMI_NAN_DISC_SCAN_PARAMS_GET/SET macros) */
+    union {
+        struct {
+            A_UINT32
+                dwell_ms:     16,
+                interval_sec: 16;
+        };
+        A_UINT32 scan_params_word;
+    };
+    /*
+     * Committed/Awake DW interval. Valid values range: 0-5.
+     * 0 indicates no wakeup for DW and can't be used on 2.4GHz band,
+     * otherwise 2^(n-1).
+     */
+    A_UINT32 awake_dw_intval;
+    /*
+     * RSSI threshold (in dBm) indicating close proximity; used to determine
+     * if a received Synchronization Beacon from a peer within the
+     * same NAN cluster should trigger a role change from Master to Non-Master
+     * Sync when the peer has a higher Master Rank.
+     */
+    A_INT32 rssi_close_val;
+    /*
+     * RSSI threshold (in dBm) indicating medium proximity; used to evaluate
+     * if three or more Synchronization Beacons from peers within the
+     * same NAN cluster justify a role change from Master to Non-Master Sync
+     * when those peers have higher Master Ranks.
+     */
+    A_INT32 rssi_middle_val;
+    /*
+     * RSSI threshold (in dBm) used to determine if a peer is within proximity
+     * during a match event
+     */
+    A_INT32 rssi_proximity_val;
+    /* Window size for RSSI averaging (based on number of beacons received) */
+    A_UINT32 rssi_avg_window_size;
+} wmi_nan_disc_band_config_param;
+
+typedef enum {
+    WMI_NAN_CONF_CHANGE_MASTER_PREF           = 0x00000001,
+    WMI_NAN_CONF_CHANGE_CLUSTER_ID            = 0x00000002,
+    WMI_NAN_CONF_CHANGE_SERVICE_ID_BCN_VAL    = 0x00000004,
+    WMI_NAN_CONF_CHANGE_HOP_COUNT_LIMIT_VAL   = 0x00000008,
+    WMI_NAN_CONF_CHANGE_SUBSCRIBE_SID_BCN_VAL = 0x00000010,
+    WMI_NAN_CONF_CHANGE_CONFIG_TX_RX_CHAINS   = 0x00000020,
+    WMI_NAN_CONF_CHANGE_ENABLE_RANGING        = 0x00000040,
+    WMI_NAN_CONF_CHANGE_ENABLE_EARLY_DW_TERM  = 0x00000080,
+    WMI_NAN_CONF_CHANGE_SUPP_DISC_BANDS       = 0x00000100,
+} WMI_NAN_CONFIG_CHANGE_PARAM;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param */
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+    /* Bitmap indicating which NAN configuration parameters have changed and
+     * need to be updated by the target firmware. Each bit corresponds to a
+     * specific parameter defined in WMI_NAN_CONFIG_CHANGE_PARAM.
+     */
+    A_UINT32 nan_conf_change_bitmap;
+/*
+ * TLVs following this structure:
+ *     wmi_nan_ctrl_config_param nan_ctrl_config[];
+ *     wmi_nan_disc_band_config_param nan_disc_band_config[];
+ */
+} wmi_nan_config_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param */
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+} wmi_nan_disable_cmd_fixed_param;
+
 #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag)      WMI_GET_BITS(flag, 0, 1)
 #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val)
 #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag)      WMI_GET_BITS(flag, 1, 1)
@@ -30195,7 +30381,7 @@ typedef struct {
     A_UINT32 tlv_header;
     /** Unique id identifying the VDEV */
     A_UINT32 vdev_id;
-    /** NAN Cluster ID */
+    /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */
     A_UINT32 nan_cluster_id;
 } wmi_nan_started_cluster_event_fixed_param_PROTOTYPE;
 
@@ -30209,7 +30395,7 @@ typedef struct {
     A_UINT32 tlv_header;
     /** Unique id identifying the VDEV */
     A_UINT32 vdev_id;
-    /** NAN Cluster ID */
+    /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */
     A_UINT32 nan_cluster_id;
 } wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE;
 
@@ -30226,6 +30412,82 @@ typedef struct {
      */
 } wmi_nan_dmesg_event_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+    A_UINT32 status; /* Status code; 0 indicates NAN enable is success */
+    A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel */
+} wmi_nan_enable_rsp_event_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+    A_UINT32 dw_chan_freq; /* DW channel freq in MHz */
+} wmi_nan_next_dw_info_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+    A_UINT32 status; /* Status code; 0 indicates NAN enable is success */
+} wmi_nan_disable_cnf_event_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
+} wmi_nan_disable_ind_event_fixed_param;
+
+typedef enum {
+    WMI_NDP_BAND_CAP_2GHZ = 0x01,
+    WMI_NDP_BAND_CAP_5GHZ = 0x02,
+    WMI_NDP_BAND_CAP_6GHZ = 0x04,
+} WMI_NDP_BAND_CAP;
+
+/* Macros for parsing NAN device_caps fields */
+#define WMI_DEVICE_CAPS_GET_VHT_PHY_MODE(word32) \
+        WMI_GET_BITS(word32, 0, 1)
+#define WMI_DEVICE_CAPS_SET_VHT_PHY_MODE(word32, val) \
+        WMI_SET_BITS(word32, 0, 1, val)
+#define WMI_DEVICE_CAPS_GET_HE_PHY_MODE(word32) \
+        WMI_GET_BITS(word32, 1, 1)
+#define WMI_DEVICE_CAPS_SET_HE_PHY_MODE(word32, val) \
+        WMI_SET_BITS(word32, 1, 1, val)
+#define WMI_DEVICE_CAPS_GET_HE_VHT_80_80(word32) \
+        WMI_GET_BITS(word32, 2, 1)
+#define WMI_DEVICE_CAPS_SET_HE_VHT_80_80(word32, val) \
+        WMI_SET_BITS(word32, 2, 1, val)
+#define WMI_DEVICE_CAPS_GET_HE_VHT_160(word32) \
+        WMI_GET_BITS(word32, 3, 1)
+#define WMI_DEVICE_CAPS_SET_HE_VHT_160(word32, val) \
+        WMI_SET_BITS(word32, 3, 1, val)
+#define WMI_DEVICE_CAPS_GET_NUM_TX_ANT(word32) \
+        WMI_GET_BITS(word32, 4, 4)
+#define WMI_DEVICE_CAPS_SET_NUM_TX_ANT(word32, val) \
+        WMI_SET_BITS(word32, 4, 4, val)
+#define WMI_DEVICE_CAPS_GET_NUM_RX_ANT(word32) \
+        WMI_GET_BITS(word32, 8, 4)
+#define WMI_DEVICE_CAPS_SET_NUM_RX_ANT(word32, val) \
+        WMI_SET_BITS(word32, 8, 4, val)
+#define WMI_DEVICE_CAPS_GET_S3_SUPPORT(word32) \
+        WMI_GET_BITS(word32, 12, 1)
+#define WMI_DEVICE_CAPS_SET_S3_SUPPORT(word32, val) \
+        WMI_SET_BITS(word32, 12, 1, val)
+#define WMI_DEVICE_CAPS_GET_MAX_NDI_INTERFACES(word32) \
+        WMI_GET_BITS(word32, 13, 3)
+#define WMI_DEVICE_CAPS_SET_MAX_NDI_INTERFACES(word32, val) \
+        WMI_SET_BITS(word32, 13, 3, val)
+#define WMI_DEVICE_CAPS_GET_NDP_SUPPORTED_BAND(word32) \
+        WMI_GET_BITS(word32, 16, 8)
+#define WMI_DEVICE_CAPS_SET_NDP_SUPPORTED_BAND(word32, val) \
+        WMI_SET_BITS(word32, 16, 8, val)
+#define WMI_DEVICE_CAPS_GET_MAX_CHAN_SWITCH_TIME(word32) \
+        WMI_GET_BITS(word32, 0, 16)
+#define WMI_DEVICE_CAPS_SET_MAX_CHAN_SWITCH_TIME(word32, val) \
+        WMI_SET_BITS(word32, 0, 16, val)
+
 typedef struct {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_nan_capabilities */
     A_UINT32 tlv_header;
@@ -30233,6 +30495,32 @@ typedef struct {
     A_UINT32 max_ndp_sessions;
     /** Maximum number of nan pairing sessions supported by the Firmware */
     A_UINT32 max_pairing_sessions;
+    union {
+        /* First 32-bit word of device capabilities */
+        A_UINT32 device_caps_word0;
+        struct {
+            A_UINT32 vht_phy_mode:      1, /* Support for VHT PHY mode */
+                     he_phy_mode:       1, /* Support for HE PHY mode */
+                     he_vht_80_80:      1, /* Support for 80+80 MHz HE/VHT */
+                     he_vht_160:        1, /* Support for 160 MHz HE/VHT */
+                     num_tx_ant:        4, /* Number of TX antennas */
+                     num_rx_ant:        4, /* Number of RX antennas */
+                     s3_support:        1, /* Support for S3 power save */
+                     max_ndi_interfaces:3, /* Max number of NDI interfaces */
+                     ndp_supported_band:8, /* Supported bands for NDP
+                                            * (see WMI_NDP_BAND_CAP) */
+                     reserved:8;           /* Reserved bits */
+        };
+    };
+    union {
+        /* Second 32-bit word of device capabilities */
+        A_UINT32 device_caps_word1;
+        struct {
+            A_UINT32 max_chan_switch_time:16, /* Max channel switch time,
+                                               * in microseconds */
+                     reserved2:           16; /* Reserved bits */
+        };
+    };
 } wmi_nan_capabilities;
 
 /** NAN DATA CMD's */
@@ -40272,6 +40560,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_WLAN_MODE_REQ_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_ENABLE_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_CONFIG_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_DISABLE_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 744f2302c459..00d17076d0e2 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1671
+#define __WMI_REVISION_ 1672
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 2947b78e2430b086833f3b61ca85a2234cd2b161 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 12 Nov 2025 12:02:06 -0800
Subject: [PATCH 067/290] fw-api: CL 30933603 - update fw common interface
 files

Change-Id: I764382f3ebdf7f51946c27b67d671d5f9d11a46b
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 5fb291122195..be9e8f863c29 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -971,7 +971,8 @@ typedef struct {
                      is_combined_ul_basic_trigger: 1,
                      is_manual_ulofdma_trigger: 1,
                      is_combined_ul_bsrp_trigger: 1,
-                     reserved3:     28;
+                     is_sta_dps_seq: 1,
+                     reserved3:     27;
         };
     };
     /* Flag to indicate if the channel chosen is 320_1 / 320_2 */

From d60e79099e62371736c0916db51fdcacc2157f07 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 12 Nov 2025 12:03:46 -0800
Subject: [PATCH 068/290] fw-api: CL 30939043 - update fw common interface
 files

Change-Id: Iee985c55dfff68c1b7f8d40d385c6c3b1b7cfbbd
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  | 34 ++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 3 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index b0ea65d4cce8..1bd84737785d 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -740,6 +740,7 @@ typedef  enum  {
     WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */
     WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */
     WMI_SERVICE_NAN_STANDARD_MODE_SUPPORT = 478, /* Indicates FW supports NAN in standard mode (supplicant-based NAN architecture model) */
+    WMI_SERVICE_CONC_2VDEV_DCS_STATS_SUPPORT = 479, /* Indicate FW support for collecting DCS stats for more than 1 vdev (max 2 concurrent vdevs) */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 577576be46f9..e44f024185d8 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5129,8 +5129,12 @@ typedef struct {
      *      to the secondary refill ring.
      *      Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG
      *      DIRECT_REFILL_SUPPORT_GET and _SET macros.
+     *  Bit 24
+     *      This bit will be set by host to inform FW that HOST will be
+     *      expecting and will be able to handle DCS stats event sent
+     *      by FW for concurrent vdevs (event can support max 2 vdevs data).
      *
-     *  Bits 31:24 - Reserved
+     *  Bits 31:25 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -5737,6 +5741,11 @@ typedef struct {
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_SET(host_service_flags, val) \
          WMI_SET_BITS(host_service_flags, 23, 1, val)
 
+/* This bit will be used to inform FW that HOST will be handling DCS stats for multiple vdevs (max 2) */
+#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_GET(host_service_flags) \
+    WMI_GET_BITS(host_service_flags, 24, 1)
+#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_SET(host_service_flags, value) \
+    WMI_SET_BITS(host_service_flags, 24, 1, value)
 
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
@@ -23163,6 +23172,24 @@ typedef struct _wlan_dcs_im_tgt_stats {
 
     /** BSS rx cycle count */
     A_UINT32 my_bss_rx_cycle_count;
+
+    /*------*/
+    /* vdev id and pdev id will be added accordingly in each TLV,
+     * when combined event for 2 vdevs in case of concurrency.
+     */
+
+    /* vdev_id_and_pdev_id_valid:
+     * If set, then the below vdev_id and pdev_id fields have valid values.
+     * If not set, then the below vdev_id and pdev_id fields must be ignored.
+     */
+    A_UINT32 vdev_id_and_pdev_id_valid;
+
+    /** vdev id **/
+    A_UINT32 vdev_id;  /* unique vdev id for DCS stats info */
+
+    /** pdev id **/
+    A_UINT32 pdev_id;  /* unique pdev id for DCS stats info */
+    /*------*/
 } wlan_dcs_im_tgt_stats_t;
 
 typedef struct wlan_dcs_awgn_info {
@@ -23252,7 +23279,10 @@ typedef struct {
  * elements (not arrays).     union { wlan_dcs_cw_int cw_int; wlan_dcs_im_tgt_stats_t   wlan_stat; } int_event;
  *
  *       wlan_dcs_cw_int            cw_int[];   <-- cw_interference event
- *       wlan_dcs_im_tgt_stats_t   wlan_stat[]; <-- wlan im interference stats
+ *       wlan_dcs_im_tgt_stats_t   wlan_stat[]; <-- wlan im interference stats,
+ *                                                  Contains vdev_id + pdev_id
+ *                                                  to specify who the stats
+ *                                                  are for.
  *       wmi_dcs_awgn_int_t        awgn_int[];  <-- Additive white Gaussian noise (AWGN) interference
  *       wmi_dcs_obss_int_t        obss_int[];  <-- Overlapping Basic Service Set (OBSS) interference
  */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 00d17076d0e2..e6d0c658800c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1672
+#define __WMI_REVISION_ 1673
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From cacdad0cf193730a111c2907352f39a63bca95d9 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 13 Nov 2025 12:01:49 -0800
Subject: [PATCH 069/290] fw-api: CL 30949206 - update fw common interface
 files

Change-Id: I6ec2ac68098839e39722975fa243c94fbbc3c480
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e44f024185d8..7b50bfa5058f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10239,6 +10239,9 @@ typedef enum {
 
     /* To enable/disable XPAN SAP + STA power optimization */
     WMI_PDEV_PARAM_XPAN_STA_PWRSAVE_ENABLE,
+
+    /** Beacon antenna for smart antenna */
+    WMI_PDEV_PARAM_SMART_ANTENNA_BEACON_ANTENNA,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index e6d0c658800c..c96e554a36bf 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1673
+#define __WMI_REVISION_ 1674
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 801c1c29c60c48586f4339cd4c88bb7323edd182 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 14 Nov 2025 01:51:38 -0800
Subject: [PATCH 070/290] fw-api: CL 30960339 - update fw common interface
 files

Change-Id: Id2c8e416e1179d373a40851b07075406760ff844
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   2 +
 fw/wmi_tlv_defs.h |   7 +++
 fw/wmi_unified.h  | 118 ++++++++++++++++++++++++++++++++++++++++++----
 fw/wmi_version.h  |   2 +-
 4 files changed, 118 insertions(+), 11 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 1bd84737785d..c510d1c0e2ec 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -741,6 +741,8 @@ typedef  enum  {
     WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */
     WMI_SERVICE_NAN_STANDARD_MODE_SUPPORT = 478, /* Indicates FW supports NAN in standard mode (supplicant-based NAN architecture model) */
     WMI_SERVICE_CONC_2VDEV_DCS_STATS_SUPPORT = 479, /* Indicate FW support for collecting DCS stats for more than 1 vdev (max 2 concurrent vdevs) */
+    WMI_SERVICE_CFR_UNASSOC_RX_CAPTURE_SUPPORT = 480, /* Indicates FW supports RX-based unassociated CFR capture */
+    WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a7c39df3bde0..a0cbcd887f9c 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1530,6 +1530,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param,
+    WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2460,6 +2461,7 @@ typedef enum {
     OP(WMI_NAN_NEXT_DW_INFO_EVENTID) \
     OP(WMI_NAN_DISABLE_CNF_EVENTID) \
     OP(WMI_NAN_DISABLE_IND_EVENTID) \
+    OP(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -8168,6 +8170,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FW_READY_IND_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, wmi_wlan_mode_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_RESP_EVENTID);
 
+/* CFR capture filter response event */
+#define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_RESP_EVENTID(id,op,buf,len) \
+WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, wmi_cfr_capture_filter_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID);
+
 
 
 #ifdef __cplusplus
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 7b50bfa5058f..ff3cbbbb8ff2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2663,6 +2663,9 @@ typedef enum {
     WMI_AUDIO_AGGR_REPORT_STATISTICS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_AUDIO),
     WMI_AUDIO_AGGR_SCHED_METHOD_EVENTID,
 
+    /** WMI events related to CFR capture response event */
+    WMI_CFR_CAPTURE_FILTER_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CFR_CAPTURE),
+
     /** Vendor defined WMI events **/
     WMI_VENDOR_PDEV_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VENDOR),
     WMI_VENDOR_VDEV_EVENTID,
@@ -47001,7 +47004,12 @@ typedef struct {
     A_UINT32 correlation_info_2;
     /* Bits 1:0:    TX status (if any); values defined in enum
     *               WMI_FRAME_TX_STATUS
-     * Bits 30:2:   reserved (set to 0x0)
+     * Bits 28:2:   reserved (set to 0x0)
+     * Bit  29:     frame sequence control valid flag:
+     *              The frame_seq_ctrl word / bitfields in
+     *              wmi_peer_cfr_capture_event_fixed_param must be ignored
+     *              unless this flag is set.
+     * Bit  30:     PS failed flag
      * Bit  31:     Status of the CFR capture of the peer
      *              1 (True) - Successful; 0 (False) - Not successful
      */
@@ -47079,8 +47087,41 @@ typedef struct {
      * Bits 16:31      reserved
      */
     A_UINT32 mcs_gi_info;
+
+    /*
+     * 802.11 Sequence Control field from the transmitted frame.
+     * Added for enhanced CFR correlation.
+     *
+     * Bits 0:3    Fragment number
+     * Bits 4:15   Sequence number
+     * Bits 16:31  Reserved (set to 0)
+     *
+     * Value is 0 if not available.
+     *
+     * NOTE: This field is appended for backward compatibility.
+     * Older hosts will ignore this field as they parse based on
+     * their known structure size.
+     */
+    A_UINT32 frame_seq_ctrl;
 } wmi_peer_cfr_capture_event_fixed_param;
 
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX      0x00000003
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S    0
+
+/* bits 28:2 are reserved */
+
+/* frame_seq_ctrl field is valid */
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID   0x20000000
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID_S 29
+
+/* Failed to capture CFR as peer is in power save mode */
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED         0x40000000
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S       30
+
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK                0x80000000
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S              31
+
+
 #define WMI_CFR_MCS_GET(mcs_gi_info) \
         WMI_GET_BITS(mcs_gi_info, 0, 8)
 
@@ -47093,6 +47134,57 @@ typedef struct {
 #define WMI_CFR_GI_TYPE_SET(mcs_gi_info, value) \
         WMI_SET_BITS(mcs_gi_info, 8, 8, value)
 
+/* Macros to get/set fragment number from frame_seq_ctrl field */
+#define WMI_CFR_FRAME_FRAG_NUM_GET(frame_seq_ctrl) \
+        WMI_GET_BITS(frame_seq_ctrl, 0, 4)
+#define WMI_CFR_FRAME_FRAG_NUM_SET(frame_seq_ctrl, value) \
+        WMI_SET_BITS(frame_seq_ctrl, 0, 4, value)
+
+/* Macros to get/set sequence number from frame_seq_ctrl field */
+#define WMI_CFR_FRAME_SEQ_NUM_GET(frame_seq_ctrl) \
+        WMI_GET_BITS(frame_seq_ctrl, 4, 12)
+#define WMI_CFR_FRAME_SEQ_NUM_SET(frame_seq_ctrl, value) \
+        WMI_SET_BITS(frame_seq_ctrl, 4, 12, value)
+
+/**
+ * CFR capture filter command response status codes
+ * These values are sent to host in wmi_cfr_capture_filter_resp_event
+ */
+typedef enum {
+    /** Configuration successful */
+    WMI_CFR_CAPTURE_FILTER_STATUS_SUCCESS        = 0,
+
+    /** Channel not specified for unassoc mode */
+    WMI_CFR_CAPTURE_FILTER_STATUS_NO_CHANNEL     = 1,
+
+    /** Invalid MAC ID */
+    WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_MAC_ID = 2,
+
+    /** OCS channel request failed */
+    WMI_CFR_CAPTURE_FILTER_STATUS_OCS_FAILED     = 3,
+
+    /** vdev not found */
+    WMI_CFR_CAPTURE_FILTER_STATUS_NO_VDEV        = 4,
+
+    /** Invalid param */
+    WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_PARAM  = 5,
+} wmi_cfr_capture_filter_status_t;
+
+typedef struct {
+    A_UINT32 tlv_header;
+    /* Status of the CFR capture filter configuration based on wmi_cfr_capture_filter_status_t */
+    A_UINT32 status; /* wmi_cfr_capture_filter_status_t */
+    A_UINT32 pdev_id;
+    /*
+     * Fields for peer CFR capture support -
+     * These fields are ONLY populated for peer capture responses.
+     * For filter capture responses, these remain 0.
+     */
+    A_UINT32 vdev_id;           /* VDEV ID (0 for filter capture) */
+    wmi_mac_addr mac_addr;      /* Peer MAC address (all zeros for filter capture) */
+    A_UINT32 request;           /* WMI_PEER_CFR_CAPTURE_ENABLE/DISABLE (0 for filter capture) */
+} wmi_cfr_capture_filter_resp_event_fixed_param;
+
 
 #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff
 #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \
@@ -47170,15 +47262,6 @@ typedef struct {
     A_UINT32 agc_gain_tbl_index[WMI_MAX_CHAINS/WMI_CFR_AGC_GAIN_CHAINS_PER_U32];
 } wmi_peer_cfr_capture_event_phase_fixed_param;
 
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK      0x80000000
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S    31
-
-/* Failed to capture CFR as peer is in power save mode */
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED      0x40000000
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S    30
-
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX      0x00000003
-#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S    0
 
 /**
  *  wmi_cold_boot_cal_data config flags
@@ -48051,6 +48134,17 @@ typedef struct {
      */
     A_UINT32 capture_count;
 
+    /* unassoc_capture_config:
+     * Bit 0:    Enable unassociated capture mode
+     * Bits 31:1 Reserved
+     */
+    A_UINT32 unassoc_capture_config;
+
+    /* Target channel frequency in MHz */
+    A_UINT32 unassoc_channel_mhz;
+
+    /* Target channel phy_mode */
+    A_UINT32 unassoc_phy_mode; /* WLAN_PHY_MODE */
 /*
  * A variable-length TLV array of wmi_cfr_filter_group_config will
  * follow this fixed_param TLV
@@ -48058,6 +48152,10 @@ typedef struct {
  */
 } wmi_cfr_capture_filter_cmd_fixed_param;
 
+/* CFR Capture macros to get/set the unassociated capture mode enable flag */
+#define WMI_CFR_UNASSOC_CAPTURE_EN_GET(x)        WMI_GET_BITS(x, 0, 1)
+#define WMI_CFR_UNASSOC_CAPTURE_EN_SET(x, value) WMI_SET_BITS(x, 0, 1, value)
+
 enum wmi_oem_data_evt_cause {
     WMI_OEM_DATA_EVT_CAUSE_UNSPECIFIED = 0,
     WMI_OEM_DATA_EVT_CAUSE_CMD_REQ = 1,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c96e554a36bf..1e9c9ed9fbac 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1674
+#define __WMI_REVISION_ 1675
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ed981aa515535bd046edb1ec77d74ecc98c05867 Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <prakashp@qti.qualcomm.com>
Date: Thu, 30 Oct 2025 01:15:24 -0700
Subject: [PATCH 071/290] fw-api: fig: v1 remove unused reo hw data structure
 files

Remove REO hw data structures not used on fig.

Change-Id: I3c11ee11f2d69f4873dae60b0534898931556364
CRs-Fixed: 4344733
---
 .../reo_descriptor_threshold_reached_status.h | 257 ---------
 hw/fig/v1/reo_flush_cache.h                   | 156 ------
 hw/fig/v1/reo_flush_cache_status.h            | 285 ----------
 hw/fig/v1/reo_flush_queue.h                   | 121 -----
 hw/fig/v1/reo_flush_queue_status.h            | 229 --------
 hw/fig/v1/reo_flush_timeout_list.h            | 114 ----
 hw/fig/v1/reo_flush_timeout_list_status.h     | 243 ---------
 hw/fig/v1/reo_get_queue_stats.h               | 114 ----
 hw/fig/v1/reo_get_queue_stats_status.h        | 306 -----------
 hw/fig/v1/reo_unblock_cache.h                 | 114 ----
 hw/fig/v1/reo_unblock_cache_status.h          | 236 --------
 hw/fig/v1/reo_update_rx_reo_queue.h           | 422 ---------------
 hw/fig/v1/reo_update_rx_reo_queue_status.h    | 222 --------
 hw/fig/v1/rx_reo_queue.h                      | 502 ------------------
 hw/fig/v1/rx_reo_queue_1k.h                   | 257 ---------
 hw/fig/v1/rx_reo_queue_ext.h                  | 378 -------------
 hw/fig/v1/tcl_data_cmd.h                      | 278 ----------
 hw/fig/v1/tcl_gse_cmd.h                       | 143 -----
 hw/fig/v1/uniform_reo_cmd_header.h            |  38 --
 hw/fig/v1/uniform_reo_status_header.h         |  52 --
 hw/fig/v1/wbm2sw_completion_ring_tx.h         | 243 ---------
 21 files changed, 4710 deletions(-)
 delete mode 100644 hw/fig/v1/reo_descriptor_threshold_reached_status.h
 delete mode 100644 hw/fig/v1/reo_flush_cache.h
 delete mode 100644 hw/fig/v1/reo_flush_cache_status.h
 delete mode 100644 hw/fig/v1/reo_flush_queue.h
 delete mode 100644 hw/fig/v1/reo_flush_queue_status.h
 delete mode 100644 hw/fig/v1/reo_flush_timeout_list.h
 delete mode 100644 hw/fig/v1/reo_flush_timeout_list_status.h
 delete mode 100644 hw/fig/v1/reo_get_queue_stats.h
 delete mode 100644 hw/fig/v1/reo_get_queue_stats_status.h
 delete mode 100644 hw/fig/v1/reo_unblock_cache.h
 delete mode 100644 hw/fig/v1/reo_unblock_cache_status.h
 delete mode 100644 hw/fig/v1/reo_update_rx_reo_queue.h
 delete mode 100644 hw/fig/v1/reo_update_rx_reo_queue_status.h
 delete mode 100644 hw/fig/v1/rx_reo_queue.h
 delete mode 100644 hw/fig/v1/rx_reo_queue_1k.h
 delete mode 100644 hw/fig/v1/rx_reo_queue_ext.h
 delete mode 100644 hw/fig/v1/tcl_data_cmd.h
 delete mode 100644 hw/fig/v1/tcl_gse_cmd.h
 delete mode 100644 hw/fig/v1/uniform_reo_cmd_header.h
 delete mode 100644 hw/fig/v1/uniform_reo_status_header.h
 delete mode 100644 hw/fig/v1/wbm2sw_completion_ring_tx.h

diff --git a/hw/fig/v1/reo_descriptor_threshold_reached_status.h b/hw/fig/v1/reo_descriptor_threshold_reached_status.h
deleted file mode 100644
index 4e0343e64182..000000000000
--- a/hw/fig/v1/reo_descriptor_threshold_reached_status.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
-#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
-
-#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
-
-struct reo_descriptor_threshold_reached_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t threshold_index                                         :  2,
-                      reserved_2                                              : 30;
-             uint32_t link_descriptor_counter0                                : 24,
-                      reserved_3                                              :  8;
-             uint32_t link_descriptor_counter1                                : 24,
-                      reserved_4                                              :  8;
-             uint32_t link_descriptor_counter2                                : 24,
-                      reserved_5                                              :  8;
-             uint32_t link_descriptor_counter_sum                             : 26,
-                      reserved_6                                              :  6;
-             uint32_t reserved_7                                              : 32;
-             uint32_t reserved_8                                              : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2                                              : 30,
-                      threshold_index                                         :  2;
-             uint32_t reserved_3                                              :  8,
-                      link_descriptor_counter0                                : 24;
-             uint32_t reserved_4                                              :  8,
-                      link_descriptor_counter1                                : 24;
-             uint32_t reserved_5                                              :  8,
-                      link_descriptor_counter2                                : 24;
-             uint32_t reserved_6                                              :  6,
-                      link_descriptor_counter_sum                             : 26;
-             uint32_t reserved_7                                              : 32;
-             uint32_t reserved_8                                              : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET    0x0000000000000000
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB       28
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB       31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK      0x00000000f0000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET      0x0000000000000000
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB         32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB         63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET              0x0000000000000008
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB                 0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB                 1
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK                0x0000000000000003
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET                   0x0000000000000008
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB                      2
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB                      31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK                     0x00000000fffffffc
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET     0x0000000000000008
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB        32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB        55
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK       0x00ffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET                   0x0000000000000008
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB                      56
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB                      63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK                     0xff00000000000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET     0x0000000000000010
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB        0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB        23
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK       0x0000000000ffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET                   0x0000000000000010
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB                      24
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB                      31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK                     0x00000000ff000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET     0x0000000000000010
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB        32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB        55
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK       0x00ffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET                   0x0000000000000010
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB                      56
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB                      63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK                     0xff00000000000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET  0x0000000000000018
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB     0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB     25
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK    0x0000000003ffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET                   0x0000000000000018
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB                      26
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB                      31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK                     0x00000000fc000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET                   0x0000000000000018
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB                      32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB                      63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK                     0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET                   0x0000000000000020
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB                      0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB                      31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK                     0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET                  0x0000000000000020
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB                     32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB                     63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK                    0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET                 0x0000000000000028
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET                 0x0000000000000028
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET                 0x0000000000000030
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET                 0x0000000000000030
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET                 0x0000000000000038
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET                 0x0000000000000038
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET                 0x0000000000000040
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET                 0x0000000000000040
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET                 0x0000000000000048
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET                 0x0000000000000048
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET                 0x0000000000000050
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET                 0x0000000000000050
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET                 0x0000000000000058
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET                 0x0000000000000058
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB                    63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK                   0xffffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET                 0x0000000000000060
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB                    0
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB                    31
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK                   0x00000000ffffffff
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET                 0x0000000000000060
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB                    32
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB                    59
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK                   0x0fffffff00000000
-
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET                0x0000000000000060
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB                   60
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB                   63
-#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK                  0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_cache.h b/hw/fig/v1/reo_flush_cache.h
deleted file mode 100644
index ef5713f527aa..000000000000
--- a/hw/fig/v1/reo_flush_cache.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_CACHE_H_
-#define _REO_FLUSH_CACHE_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
-
-#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
-
-struct reo_flush_cache {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t flush_addr_31_0                                         : 32;
-             uint32_t flush_addr_39_32                                        :  8,
-                      forward_all_mpdus_in_queue                              :  1,
-                      release_cache_block_index                               :  1,
-                      cache_block_resource_index                              :  2,
-                      flush_without_invalidate                                :  1,
-                      block_cache_usage_after_flush                           :  1,
-                      flush_entire_cache                                      :  1,
-                      flush_queue_1k_desc                                     :  1,
-                      reserved_2b                                             : 16;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t flush_addr_31_0                                         : 32;
-             uint32_t reserved_2b                                             : 16,
-                      flush_queue_1k_desc                                     :  1,
-                      flush_entire_cache                                      :  1,
-                      block_cache_usage_after_flush                           :  1,
-                      flush_without_invalidate                                :  1,
-                      cache_block_resource_index                              :  2,
-                      release_cache_block_index                               :  1,
-                      forward_all_mpdus_in_queue                              :  1,
-                      flush_addr_39_32                                        :  8;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
-
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
-#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
-
-#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
-#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB                                  17
-#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB                                  31
-#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
-
-#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET                                      0x0000000000000000
-#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB                                         32
-#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB                                         63
-#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK                                        0xffffffff00000000
-
-#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET                                     0x0000000000000008
-#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB                                        0
-#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB                                        7
-#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK                                       0x00000000000000ff
-
-#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET                           0x0000000000000008
-#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB                              8
-#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB                              8
-#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK                             0x0000000000000100
-
-#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET                            0x0000000000000008
-#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB                               9
-#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB                               9
-#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK                              0x0000000000000200
-
-#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                           0x0000000000000008
-#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                              10
-#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                              11
-#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                             0x0000000000000c00
-
-#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET                             0x0000000000000008
-#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB                                12
-#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB                                12
-#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK                               0x0000000000001000
-
-#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET                        0x0000000000000008
-#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB                           13
-#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB                           13
-#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK                          0x0000000000002000
-
-#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB                                      14
-#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB                                      14
-#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK                                     0x0000000000004000
-
-#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET                                  0x0000000000000008
-#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB                                     15
-#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB                                     15
-#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK                                    0x0000000000008000
-
-#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET                                          0x0000000000000008
-#define REO_FLUSH_CACHE_RESERVED_2B_LSB                                             16
-#define REO_FLUSH_CACHE_RESERVED_2B_MSB                                             31
-#define REO_FLUSH_CACHE_RESERVED_2B_MASK                                            0x00000000ffff0000
-
-#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET                                          0x0000000000000008
-#define REO_FLUSH_CACHE_RESERVED_3A_LSB                                             32
-#define REO_FLUSH_CACHE_RESERVED_3A_MSB                                             63
-#define REO_FLUSH_CACHE_RESERVED_3A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET                                          0x0000000000000010
-#define REO_FLUSH_CACHE_RESERVED_4A_LSB                                             0
-#define REO_FLUSH_CACHE_RESERVED_4A_MSB                                             31
-#define REO_FLUSH_CACHE_RESERVED_4A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET                                          0x0000000000000010
-#define REO_FLUSH_CACHE_RESERVED_5A_LSB                                             32
-#define REO_FLUSH_CACHE_RESERVED_5A_MSB                                             63
-#define REO_FLUSH_CACHE_RESERVED_5A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET                                          0x0000000000000018
-#define REO_FLUSH_CACHE_RESERVED_6A_LSB                                             0
-#define REO_FLUSH_CACHE_RESERVED_6A_MSB                                             31
-#define REO_FLUSH_CACHE_RESERVED_6A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET                                          0x0000000000000018
-#define REO_FLUSH_CACHE_RESERVED_7A_LSB                                             32
-#define REO_FLUSH_CACHE_RESERVED_7A_MSB                                             63
-#define REO_FLUSH_CACHE_RESERVED_7A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET                                          0x0000000000000020
-#define REO_FLUSH_CACHE_RESERVED_8A_LSB                                             0
-#define REO_FLUSH_CACHE_RESERVED_8A_MSB                                             31
-#define REO_FLUSH_CACHE_RESERVED_8A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET                                        0x0000000000000020
-#define REO_FLUSH_CACHE_TLV64_PADDING_LSB                                           32
-#define REO_FLUSH_CACHE_TLV64_PADDING_MSB                                           63
-#define REO_FLUSH_CACHE_TLV64_PADDING_MASK                                          0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_cache_status.h b/hw/fig/v1/reo_flush_cache_status.h
deleted file mode 100644
index f39e49257a30..000000000000
--- a/hw/fig/v1/reo_flush_cache_status.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_CACHE_STATUS_H_
-#define _REO_FLUSH_CACHE_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
-
-#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
-
-struct reo_flush_cache_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t error_detected                                          :  1,
-                      block_error_details                                     :  2,
-                      reserved_2a                                             :  5,
-                      cache_controller_flush_status_hit                       :  1,
-                      cache_controller_flush_status_desc_type                 :  3,
-                      cache_controller_flush_status_client_id                 :  4,
-                      cache_controller_flush_status_error                     :  2,
-                      cache_controller_flush_count                            :  8,
-                      flush_queue_1k_desc                                     :  1,
-                      reserved_2b                                             :  5;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2b                                             :  5,
-                      flush_queue_1k_desc                                     :  1,
-                      cache_controller_flush_count                            :  8,
-                      cache_controller_flush_status_error                     :  2,
-                      cache_controller_flush_status_client_id                 :  4,
-                      cache_controller_flush_status_desc_type                 :  3,
-                      cache_controller_flush_status_hit                       :  1,
-                      reserved_2a                                             :  5,
-                      block_error_details                                     :  2,
-                      error_detected                                          :  1;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x0000000000000000
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x000000000000ffff
-
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x0000000000000000
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x0000000003ff0000
-
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x0000000000000000
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x000000000c000000
-
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x0000000000000000
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0x00000000f0000000
-
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x0000000000000000
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          32
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          63
-#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB                                   0
-#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB                                   0
-#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK                                  0x0000000000000001
-
-#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET                           0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB                              1
-#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB                              2
-#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK                             0x0000000000000006
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB                                      3
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB                                      7
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK                                     0x00000000000000f8
-
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET             0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB                8
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB                8
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK               0x0000000000000100
-
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET       0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB          9
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB          11
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK         0x0000000000000e00
-
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET       0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB          12
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB          15
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK         0x000000000000f000
-
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET           0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB              16
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB              17
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK             0x0000000000030000
-
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET                  0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB                     18
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB                     25
-#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK                    0x0000000003fc0000
-
-#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET                           0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB                              26
-#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB                              26
-#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK                             0x0000000004000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB                                      27
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB                                      31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK                                     0x00000000f8000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB                                      32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB                                      63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB                                      0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB                                      31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB                                      32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB                                      63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB                                      0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB                                      31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB                                      32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB                                      63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET                                   0x0000000000000020
-#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB                                      0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB                                      31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET                                   0x0000000000000020
-#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB                                      32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB                                      63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET                                  0x0000000000000028
-#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET                                  0x0000000000000028
-#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET                                  0x0000000000000030
-#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET                                  0x0000000000000030
-#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET                                  0x0000000000000038
-#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET                                  0x0000000000000038
-#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET                                  0x0000000000000040
-#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET                                  0x0000000000000040
-#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET                                  0x0000000000000048
-#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET                                  0x0000000000000048
-#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET                                  0x0000000000000050
-#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET                                  0x0000000000000050
-#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET                                  0x0000000000000058
-#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET                                  0x0000000000000058
-#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB                                     63
-#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET                                  0x0000000000000060
-#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB                                     0
-#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB                                     31
-#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET                                  0x0000000000000060
-#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB                                     32
-#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB                                     59
-#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK                                    0x0fffffff00000000
-
-#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET                                 0x0000000000000060
-#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB                                    60
-#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB                                    63
-#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK                                   0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_queue.h b/hw/fig/v1/reo_flush_queue.h
deleted file mode 100644
index cf6c108d2cb7..000000000000
--- a/hw/fig/v1/reo_flush_queue.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_QUEUE_H_
-#define _REO_FLUSH_QUEUE_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
-
-#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
-
-struct reo_flush_queue {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t flush_desc_addr_31_0                                    : 32;
-             uint32_t flush_desc_addr_39_32                                   :  8,
-                      block_desc_addr_usage_after_flush                       :  1,
-                      block_resource_index                                    :  2,
-                      reserved_2a                                             : 21;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t flush_desc_addr_31_0                                    : 32;
-             uint32_t reserved_2a                                             : 21,
-                      block_resource_index                                    :  2,
-                      block_desc_addr_usage_after_flush                       :  1,
-                      flush_desc_addr_39_32                                   :  8;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
-
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
-#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
-
-#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
-#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
-#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
-#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
-
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x0000000000000000
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    32
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    63
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x0000000000000008
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
-#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x00000000000000ff
-
-#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x0000000000000008
-#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
-#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
-#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x0000000000000100
-
-#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x0000000000000008
-#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
-#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
-#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x0000000000000600
-
-#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x0000000000000008
-#define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
-#define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
-#define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0x00000000fffff800
-
-#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000000000008
-#define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             32
-#define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             63
-#define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x0000000000000010
-#define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
-#define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
-#define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x0000000000000010
-#define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             32
-#define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             63
-#define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x0000000000000018
-#define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
-#define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
-#define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000000000000018
-#define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             32
-#define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             63
-#define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x0000000000000020
-#define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
-#define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
-#define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET                                        0x0000000000000020
-#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB                                           32
-#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB                                           63
-#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK                                          0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_queue_status.h b/hw/fig/v1/reo_flush_queue_status.h
deleted file mode 100644
index 7f41cef1aee7..000000000000
--- a/hw/fig/v1/reo_flush_queue_status.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_QUEUE_STATUS_H_
-#define _REO_FLUSH_QUEUE_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
-
-#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
-
-struct reo_flush_queue_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t error_detected                                          :  1,
-                      reserved_2a                                             : 31;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2a                                             : 31,
-                      error_detected                                          :  1;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x0000000000000000
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x000000000000ffff
-
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x0000000000000000
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x0000000003ff0000
-
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x0000000000000000
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x000000000c000000
-
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x0000000000000000
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0x00000000f0000000
-
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x0000000000000000
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          32
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          63
-#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000000000008
-#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB                                   0
-#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB                                   0
-#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK                                  0x0000000000000001
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB                                      1
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB                                      31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK                                     0x00000000fffffffe
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB                                      32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB                                      63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB                                      0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB                                      31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB                                      32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB                                      63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB                                      0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB                                      31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB                                      32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB                                      63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET                                   0x0000000000000020
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB                                      0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB                                      31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET                                   0x0000000000000020
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB                                      32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB                                      63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET                                  0x0000000000000028
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET                                  0x0000000000000028
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET                                  0x0000000000000030
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET                                  0x0000000000000030
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET                                  0x0000000000000038
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET                                  0x0000000000000038
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET                                  0x0000000000000040
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET                                  0x0000000000000040
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET                                  0x0000000000000048
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET                                  0x0000000000000048
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET                                  0x0000000000000050
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET                                  0x0000000000000050
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET                                  0x0000000000000058
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET                                  0x0000000000000058
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB                                     63
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK                                    0xffffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET                                  0x0000000000000060
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB                                     0
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB                                     31
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK                                    0x00000000ffffffff
-
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET                                  0x0000000000000060
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB                                     32
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB                                     59
-#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK                                    0x0fffffff00000000
-
-#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET                                 0x0000000000000060
-#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB                                    60
-#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB                                    63
-#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK                                   0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_timeout_list.h b/hw/fig/v1/reo_flush_timeout_list.h
deleted file mode 100644
index e978152f4ca4..000000000000
--- a/hw/fig/v1/reo_flush_timeout_list.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
-#define _REO_FLUSH_TIMEOUT_LIST_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
-
-#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
-
-struct reo_flush_timeout_list {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t ac_timout_list                                          :  2,
-                      reserved_1                                              : 30;
-             uint32_t minimum_release_desc_count                              : 16,
-                      minimum_forward_buf_count                               : 16;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t reserved_1                                              : 30,
-                      ac_timout_list                                          :  2;
-             uint32_t minimum_forward_buf_count                               : 16,
-                      minimum_release_desc_count                              : 16;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET                     0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB                        0
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB                        15
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK                       0x000000000000ffff
-
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB                   16
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB                   16
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK                  0x0000000000010000
-
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET                        0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB                           17
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB                           31
-#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK                          0x00000000fffe0000
-
-#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET                                0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB                                   32
-#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB                                   33
-#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK                                  0x0000000300000000
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET                                    0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB                                       34
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB                                       63
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK                                      0xfffffffc00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET                    0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB                       0
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB                       15
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK                      0x000000000000ffff
-
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET                     0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB                        16
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB                        31
-#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK                       0x00000000ffff0000
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET                                   0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB                                      32
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB                                      63
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB                                      0
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB                                      31
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET                                   0x0000000000000010
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB                                      32
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB                                      63
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB                                      0
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB                                      31
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET                                   0x0000000000000018
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB                                      32
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB                                      63
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK                                     0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET                                   0x0000000000000020
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB                                      0
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB                                      31
-#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK                                     0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET                                 0x0000000000000020
-#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB                                    32
-#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB                                    63
-#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK                                   0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_flush_timeout_list_status.h b/hw/fig/v1/reo_flush_timeout_list_status.h
deleted file mode 100644
index 1827d9c8cc87..000000000000
--- a/hw/fig/v1/reo_flush_timeout_list_status.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
-#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26
-
-#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13
-
-struct reo_flush_timeout_list_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t error_detected                                          :  1,
-                      timout_list_empty                                       :  1,
-                      reserved_2a                                             : 30;
-             uint32_t release_desc_count                                      : 16,
-                      forward_buf_count                                       : 16;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2a                                             : 30,
-                      timout_list_empty                                       :  1,
-                      error_detected                                          :  1;
-             uint32_t forward_buf_count                                       : 16,
-                      release_desc_count                                      : 16;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET        0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB           0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB           15
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK          0x000000000000ffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET       0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB          16
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB          25
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK         0x0000000003ff0000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB    26
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB    27
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK   0x000000000c000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET              0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB                 28
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB                 31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK                0x00000000f0000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                0x0000000000000000
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB                   32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB                   63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK                  0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET                         0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB                            0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB                            0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK                           0x0000000000000001
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET                      0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB                         1
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB                         1
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK                        0x0000000000000002
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET                            0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB                               2
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB                               31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK                              0x00000000fffffffc
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET                     0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB                        32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB                        47
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK                       0x0000ffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET                      0x0000000000000008
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB                         48
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB                         63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK                        0xffff000000000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET                            0x0000000000000010
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB                               0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB                               31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK                              0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET                            0x0000000000000010
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB                               32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB                               63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK                              0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET                            0x0000000000000018
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB                               0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB                               31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK                              0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET                            0x0000000000000018
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB                               32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB                               63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK                              0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET                            0x0000000000000020
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB                               0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB                               31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK                              0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET                            0x0000000000000020
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB                               32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB                               63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK                              0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET                           0x0000000000000028
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET                           0x0000000000000028
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET                           0x0000000000000030
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET                           0x0000000000000030
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET                           0x0000000000000038
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET                           0x0000000000000038
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET                           0x0000000000000040
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET                           0x0000000000000040
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET                           0x0000000000000048
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET                           0x0000000000000048
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET                           0x0000000000000050
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET                           0x0000000000000050
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET                           0x0000000000000058
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET                           0x0000000000000058
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB                              63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK                             0xffffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET                           0x0000000000000060
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB                              0
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB                              31
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK                             0x00000000ffffffff
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET                           0x0000000000000060
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB                              32
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB                              59
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK                             0x0fffffff00000000
-
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET                          0x0000000000000060
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB                             60
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB                             63
-#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK                            0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_get_queue_stats.h b/hw/fig/v1/reo_get_queue_stats.h
deleted file mode 100644
index a2dbf08defeb..000000000000
--- a/hw/fig/v1/reo_get_queue_stats.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_GET_QUEUE_STATS_H_
-#define _REO_GET_QUEUE_STATS_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10
-
-#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5
-
-struct reo_get_queue_stats {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
-             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
-                      clear_stats                                             :  1,
-                      reserved_2a                                             : 23;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
-             uint32_t reserved_2a                                             : 23,
-                      clear_stats                                             :  1,
-                      rx_reo_queue_desc_addr_39_32                            :  8;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET                        0x0000000000000000
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB                           0
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB                           15
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK                          0x000000000000ffff
-
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                   0x0000000000000000
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB                      16
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB                      16
-#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK                     0x0000000000010000
-
-#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET                           0x0000000000000000
-#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB                              17
-#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB                              31
-#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK                             0x00000000fffe0000
-
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                      0x0000000000000000
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                         32
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                         63
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                        0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                     0x0000000000000008
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                        0
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                        7
-#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                       0x00000000000000ff
-
-#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET                                      0x0000000000000008
-#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB                                         8
-#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB                                         8
-#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK                                        0x0000000000000100
-
-#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET                                      0x0000000000000008
-#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB                                         9
-#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB                                         31
-#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK                                        0x00000000fffffe00
-
-#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET                                      0x0000000000000008
-#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB                                         32
-#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB                                         63
-#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK                                        0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET                                      0x0000000000000010
-#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB                                         0
-#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB                                         31
-#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK                                        0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET                                      0x0000000000000010
-#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB                                         32
-#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB                                         63
-#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK                                        0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET                                      0x0000000000000018
-#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB                                         0
-#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB                                         31
-#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK                                        0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET                                      0x0000000000000018
-#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB                                         32
-#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB                                         63
-#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK                                        0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET                                      0x0000000000000020
-#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB                                         0
-#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB                                         31
-#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK                                        0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET                                    0x0000000000000020
-#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB                                       32
-#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB                                       63
-#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK                                      0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_get_queue_stats_status.h b/hw/fig/v1/reo_get_queue_stats_status.h
deleted file mode 100644
index 6f47064c717a..000000000000
--- a/hw/fig/v1/reo_get_queue_stats_status.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
-#define _REO_GET_QUEUE_STATS_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26
-
-#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13
-
-struct reo_get_queue_stats_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t ssn                                                     : 12,
-                      current_index                                           : 10,
-                      reserved_2                                              : 10;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t last_rx_enqueue_timestamp                               : 32;
-             uint32_t last_rx_dequeue_timestamp                               : 32;
-             uint32_t rx_bitmap_31_0                                          : 32;
-             uint32_t rx_bitmap_63_32                                         : 32;
-             uint32_t rx_bitmap_95_64                                         : 32;
-             uint32_t rx_bitmap_127_96                                        : 32;
-             uint32_t rx_bitmap_159_128                                       : 32;
-             uint32_t rx_bitmap_191_160                                       : 32;
-             uint32_t rx_bitmap_223_192                                       : 32;
-             uint32_t rx_bitmap_255_224                                       : 32;
-             uint32_t rx_bitmap_287_256                                       : 32;
-             uint32_t current_mpdu_count                                      :  7,
-                      current_msdu_count                                      : 25;
-             uint32_t window_jump_2k                                          :  4,
-                      timeout_count                                           :  6,
-                      forward_due_to_bar_count                                :  6,
-                      duplicate_count                                         : 16;
-             uint32_t frames_in_order_count                                   : 24,
-                      bar_received_count                                      :  8;
-             uint32_t mpdu_frames_processed_count                             : 32;
-             uint32_t msdu_frames_processed_count                             : 32;
-             uint32_t total_processed_byte_count                              : 32;
-             uint32_t late_receive_mpdu_count                                 : 12,
-                      hole_count                                              : 16,
-                      get_queue_1k_stats_status_to_follow                     :  1,
-                      reserved_24a                                            :  3;
-             uint32_t aging_drop_mpdu_count                                   : 16,
-                      aging_drop_interval                                     :  8,
-                      reserved_25a                                            :  4,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2                                              : 10,
-                      current_index                                           : 10,
-                      ssn                                                     : 12;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t last_rx_enqueue_timestamp                               : 32;
-             uint32_t last_rx_dequeue_timestamp                               : 32;
-             uint32_t rx_bitmap_31_0                                          : 32;
-             uint32_t rx_bitmap_63_32                                         : 32;
-             uint32_t rx_bitmap_95_64                                         : 32;
-             uint32_t rx_bitmap_127_96                                        : 32;
-             uint32_t rx_bitmap_159_128                                       : 32;
-             uint32_t rx_bitmap_191_160                                       : 32;
-             uint32_t rx_bitmap_223_192                                       : 32;
-             uint32_t rx_bitmap_255_224                                       : 32;
-             uint32_t rx_bitmap_287_256                                       : 32;
-             uint32_t current_msdu_count                                      : 25,
-                      current_mpdu_count                                      :  7;
-             uint32_t duplicate_count                                         : 16,
-                      forward_due_to_bar_count                                :  6,
-                      timeout_count                                           :  6,
-                      window_jump_2k                                          :  4;
-             uint32_t bar_received_count                                      :  8,
-                      frames_in_order_count                                   : 24;
-             uint32_t mpdu_frames_processed_count                             : 32;
-             uint32_t msdu_frames_processed_count                             : 32;
-             uint32_t total_processed_byte_count                              : 32;
-             uint32_t reserved_24a                                            :  3,
-                      get_queue_1k_stats_status_to_follow                     :  1,
-                      hole_count                                              : 16,
-                      late_receive_mpdu_count                                 : 12;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            :  4,
-                      aging_drop_interval                                     :  8,
-                      aging_drop_mpdu_count                                   : 16;
-#endif
-};
-
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET           0x0000000000000000
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB              0
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB              15
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK             0x000000000000ffff
-
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET          0x0000000000000000
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB             16
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB             25
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK            0x0000000003ff0000
-
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET    0x0000000000000000
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB       26
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB       27
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK      0x000000000c000000
-
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                 0x0000000000000000
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB                    28
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB                    31
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK                   0x00000000f0000000
-
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                   0x0000000000000000
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB                      32
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB                      63
-#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK                     0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET                                       0x0000000000000008
-#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB                                          0
-#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB                                          11
-#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK                                         0x0000000000000fff
-
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET                             0x0000000000000008
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB                                12
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB                                21
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK                               0x00000000003ff000
-
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET                                0x0000000000000008
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB                                   22
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB                                   31
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK                                  0x00000000ffc00000
-
-#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET                                   0x0000000000000008
-#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB                                      32
-#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB                                      63
-#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK                                     0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET                                  0x0000000000000010
-#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB                                     0
-#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB                                     31
-#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK                                    0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET                                  0x0000000000000010
-#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB                                     32
-#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB                                     63
-#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK                                    0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET                                 0x0000000000000018
-#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB                                    0
-#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB                                    31
-#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK                                   0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                 0x0000000000000018
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB                    32
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB                    63
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK                   0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                 0x0000000000000020
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB                    0
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB                    31
-#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK                   0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET                            0x0000000000000020
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB                               32
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB                               63
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK                              0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET                           0x0000000000000028
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB                              0
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB                              31
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK                             0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET                           0x0000000000000028
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB                              32
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB                              63
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK                             0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET                          0x0000000000000030
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB                             0
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB                             31
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK                            0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET                         0x0000000000000030
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB                            32
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB                            63
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK                           0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET                         0x0000000000000038
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB                            0
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB                            31
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK                           0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET                         0x0000000000000038
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB                            32
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB                            63
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK                           0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET                         0x0000000000000040
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB                            0
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB                            31
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK                           0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET                         0x0000000000000040
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB                            32
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB                            63
-#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK                           0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET                        0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB                           0
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB                           6
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK                          0x000000000000007f
-
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET                        0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB                           7
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB                           31
-#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK                          0x00000000ffffff80
-
-#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET                            0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB                               32
-#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB                               35
-#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK                              0x0000000f00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET                             0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB                                36
-#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB                                41
-#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK                               0x000003f000000000
-
-#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET                  0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB                     42
-#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB                     47
-#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK                    0x0000fc0000000000
-
-#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET                           0x0000000000000048
-#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB                              48
-#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB                              63
-#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK                             0xffff000000000000
-
-#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET                     0x0000000000000050
-#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB                        0
-#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB                        23
-#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK                       0x0000000000ffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET                        0x0000000000000050
-#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB                           24
-#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB                           31
-#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK                          0x00000000ff000000
-
-#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET               0x0000000000000050
-#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB                  32
-#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB                  63
-#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK                 0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET               0x0000000000000058
-#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB                  0
-#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB                  31
-#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK                 0x00000000ffffffff
-
-#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                0x0000000000000058
-#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB                   32
-#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB                   63
-#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK                  0xffffffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET                   0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB                      0
-#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB                      11
-#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK                     0x0000000000000fff
-
-#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET                                0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB                                   12
-#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB                                   27
-#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK                                  0x000000000ffff000
-
-#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET       0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB          28
-#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB          28
-#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK         0x0000000010000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET                              0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB                                 29
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB                                 31
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK                                0x00000000e0000000
-
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET                     0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB                        32
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB                        47
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK                       0x0000ffff00000000
-
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET                       0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB                          48
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB                          55
-#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK                         0x00ff000000000000
-
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET                              0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB                                 56
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB                                 59
-#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK                                0x0f00000000000000
-
-#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET                             0x0000000000000060
-#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB                                60
-#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB                                63
-#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK                               0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_unblock_cache.h b/hw/fig/v1/reo_unblock_cache.h
deleted file mode 100644
index 99a7923b7f9a..000000000000
--- a/hw/fig/v1/reo_unblock_cache.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_UNBLOCK_CACHE_H_
-#define _REO_UNBLOCK_CACHE_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
-
-#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
-
-struct reo_unblock_cache {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t unblock_type                                            :  1,
-                      cache_block_resource_index                              :  2,
-                      reserved_1a                                             : 29;
-             uint32_t reserved_2a                                             : 32;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t reserved_1a                                             : 29,
-                      cache_block_resource_index                              :  2,
-                      unblock_type                                            :  1;
-             uint32_t reserved_2a                                             : 32;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                          0x0000000000000000
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                             0
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                             15
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                            0x000000000000ffff
-
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                     0x0000000000000000
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                        16
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                        16
-#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                       0x0000000000010000
-
-#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                             0x0000000000000000
-#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB                                17
-#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB                                31
-#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK                               0x00000000fffe0000
-
-#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET                                       0x0000000000000000
-#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB                                          32
-#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB                                          32
-#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK                                         0x0000000100000000
-
-#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                         0x0000000000000000
-#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                            33
-#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                            34
-#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                           0x0000000600000000
-
-#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET                                        0x0000000000000000
-#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB                                           35
-#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB                                           63
-#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK                                          0xfffffff800000000
-
-#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET                                        0x0000000000000008
-#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB                                           0
-#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB                                           31
-#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK                                          0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET                                        0x0000000000000008
-#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB                                           32
-#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB                                           63
-#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK                                          0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET                                        0x0000000000000010
-#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB                                           0
-#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB                                           31
-#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK                                          0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET                                        0x0000000000000010
-#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB                                           32
-#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB                                           63
-#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK                                          0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET                                        0x0000000000000018
-#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB                                           0
-#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB                                           31
-#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK                                          0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET                                        0x0000000000000018
-#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB                                           32
-#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB                                           63
-#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK                                          0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET                                        0x0000000000000020
-#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB                                           0
-#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB                                           31
-#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK                                          0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET                                      0x0000000000000020
-#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB                                         32
-#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB                                         63
-#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK                                        0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_unblock_cache_status.h b/hw/fig/v1/reo_unblock_cache_status.h
deleted file mode 100644
index 2e62d26729e5..000000000000
--- a/hw/fig/v1/reo_unblock_cache_status.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
-#define _REO_UNBLOCK_CACHE_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
-
-#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
-
-struct reo_unblock_cache_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t error_detected                                          :  1,
-                      unblock_type                                            :  1,
-                      reserved_2a                                             : 30;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2a                                             : 30,
-                      unblock_type                                            :  1,
-                      error_detected                                          :  1;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET             0x0000000000000000
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                0
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                15
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK               0x000000000000ffff
-
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET            0x0000000000000000
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB               16
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB               25
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK              0x0000000003ff0000
-
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET      0x0000000000000000
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB         26
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB         27
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK        0x000000000c000000
-
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                   0x0000000000000000
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                      28
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                      31
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                     0x00000000f0000000
-
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                     0x0000000000000000
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                        32
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                        63
-#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                       0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET                              0x0000000000000008
-#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB                                 0
-#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB                                 0
-#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK                                0x0000000000000001
-
-#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET                                0x0000000000000008
-#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB                                   1
-#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB                                   1
-#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK                                  0x0000000000000002
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET                                 0x0000000000000008
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB                                    2
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB                                    31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK                                   0x00000000fffffffc
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET                                 0x0000000000000008
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB                                    32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB                                    63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK                                   0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET                                 0x0000000000000010
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB                                    0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB                                    31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK                                   0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET                                 0x0000000000000010
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB                                    32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB                                    63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK                                   0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET                                 0x0000000000000018
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB                                    0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB                                    31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK                                   0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET                                 0x0000000000000018
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB                                    32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB                                    63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK                                   0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET                                 0x0000000000000020
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB                                    0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB                                    31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK                                   0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET                                 0x0000000000000020
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB                                    32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB                                    63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK                                   0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET                                0x0000000000000028
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET                                0x0000000000000028
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET                                0x0000000000000030
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET                                0x0000000000000030
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET                                0x0000000000000038
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET                                0x0000000000000038
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET                                0x0000000000000040
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET                                0x0000000000000040
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET                                0x0000000000000048
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET                                0x0000000000000048
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET                                0x0000000000000050
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET                                0x0000000000000050
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET                                0x0000000000000058
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET                                0x0000000000000058
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB                                   63
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK                                  0xffffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET                                0x0000000000000060
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB                                   0
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB                                   31
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK                                  0x00000000ffffffff
-
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET                                0x0000000000000060
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB                                   32
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB                                   59
-#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK                                  0x0fffffff00000000
-
-#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET                               0x0000000000000060
-#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB                                  60
-#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB                                  63
-#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK                                 0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/reo_update_rx_reo_queue.h b/hw/fig/v1/reo_update_rx_reo_queue.h
deleted file mode 100644
index 4cede8ca0194..000000000000
--- a/hw/fig/v1/reo_update_rx_reo_queue.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
-#define _REO_UPDATE_RX_REO_QUEUE_H_
-
-#include "uniform_reo_cmd_header.h"
-#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
-
-#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
-
-struct reo_update_rx_reo_queue {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
-             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
-                      update_receive_queue_number                             :  1,
-                      update_vld                                              :  1,
-                      update_associated_link_descriptor_counter               :  1,
-                      update_disable_duplicate_detection                      :  1,
-                      update_soft_reorder_enable                              :  1,
-                      update_ac                                               :  1,
-                      update_bar                                              :  1,
-                      update_rty                                              :  1,
-                      update_chk_2k_mode                                      :  1,
-                      update_oor_mode                                         :  1,
-                      update_ba_window_size                                   :  1,
-                      update_pn_check_needed                                  :  1,
-                      update_pn_shall_be_even                                 :  1,
-                      update_pn_shall_be_uneven                               :  1,
-                      update_pn_handling_enable                               :  1,
-                      update_pn_size                                          :  1,
-                      update_ignore_ampdu_flag                                :  1,
-                      update_svld                                             :  1,
-                      update_ssn                                              :  1,
-                      update_seq_2k_error_detected_flag                       :  1,
-                      update_pn_error_detected_flag                           :  1,
-                      update_pn_valid                                         :  1,
-                      update_pn                                               :  1,
-                      clear_stat_counters                                     :  1;
-             uint32_t receive_queue_number                                    : 16,
-                      vld                                                     :  1,
-                      associated_link_descriptor_counter                      :  2,
-                      disable_duplicate_detection                             :  1,
-                      soft_reorder_enable                                     :  1,
-                      ac                                                      :  2,
-                      bar                                                     :  1,
-                      rty                                                     :  1,
-                      chk_2k_mode                                             :  1,
-                      oor_mode                                                :  1,
-                      pn_check_needed                                         :  1,
-                      pn_shall_be_even                                        :  1,
-                      pn_shall_be_uneven                                      :  1,
-                      pn_handling_enable                                      :  1,
-                      ignore_ampdu_flag                                       :  1;
-             uint32_t ba_window_size                                          : 10,
-                      pn_size                                                 :  2,
-                      svld                                                    :  1,
-                      ssn                                                     : 12,
-                      seq_2k_error_detected_flag                              :  1,
-                      pn_error_detected_flag                                  :  1,
-                      pn_valid                                                :  1,
-                      flush_from_cache                                        :  1,
-                      reserved_4a                                             :  3;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t tlv64_padding                                           : 32;
-#else
-             struct   uniform_reo_cmd_header                                    cmd_header;
-             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
-             uint32_t clear_stat_counters                                     :  1,
-                      update_pn                                               :  1,
-                      update_pn_valid                                         :  1,
-                      update_pn_error_detected_flag                           :  1,
-                      update_seq_2k_error_detected_flag                       :  1,
-                      update_ssn                                              :  1,
-                      update_svld                                             :  1,
-                      update_ignore_ampdu_flag                                :  1,
-                      update_pn_size                                          :  1,
-                      update_pn_handling_enable                               :  1,
-                      update_pn_shall_be_uneven                               :  1,
-                      update_pn_shall_be_even                                 :  1,
-                      update_pn_check_needed                                  :  1,
-                      update_ba_window_size                                   :  1,
-                      update_oor_mode                                         :  1,
-                      update_chk_2k_mode                                      :  1,
-                      update_rty                                              :  1,
-                      update_bar                                              :  1,
-                      update_ac                                               :  1,
-                      update_soft_reorder_enable                              :  1,
-                      update_disable_duplicate_detection                      :  1,
-                      update_associated_link_descriptor_counter               :  1,
-                      update_vld                                              :  1,
-                      update_receive_queue_number                             :  1,
-                      rx_reo_queue_desc_addr_39_32                            :  8;
-             uint32_t ignore_ampdu_flag                                       :  1,
-                      pn_handling_enable                                      :  1,
-                      pn_shall_be_uneven                                      :  1,
-                      pn_shall_be_even                                        :  1,
-                      pn_check_needed                                         :  1,
-                      oor_mode                                                :  1,
-                      chk_2k_mode                                             :  1,
-                      rty                                                     :  1,
-                      bar                                                     :  1,
-                      ac                                                      :  2,
-                      soft_reorder_enable                                     :  1,
-                      disable_duplicate_detection                             :  1,
-                      associated_link_descriptor_counter                      :  2,
-                      vld                                                     :  1,
-                      receive_queue_number                                    : 16;
-             uint32_t reserved_4a                                             :  3,
-                      flush_from_cache                                        :  1,
-                      pn_valid                                                :  1,
-                      pn_error_detected_flag                                  :  1,
-                      seq_2k_error_detected_flag                              :  1,
-                      ssn                                                     : 12,
-                      svld                                                    :  1,
-                      pn_size                                                 :  2,
-                      ba_window_size                                          : 10;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t tlv64_padding                                           : 32;
-#endif
-};
-
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                    0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                       0
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                       15
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                      0x000000000000ffff
-
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET               0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                  16
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                  16
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                 0x0000000000010000
-
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                       0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB                          17
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB                          31
-#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK                         0x00000000fffe0000
-
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                  0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                     32
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                     63
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                    0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                 0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                    0
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                    7
-#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                   0x00000000000000ff
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET                  0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB                     8
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB                     8
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK                    0x0000000000000100
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET                                   0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB                                      9
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB                                      9
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK                                     0x0000000000000200
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET    0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB       10
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB       10
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK      0x0000000000000400
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB              11
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB              11
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK             0x0000000000000800
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET                   0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB                      12
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB                      12
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK                     0x0000000000001000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET                                    0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB                                       13
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB                                       13
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK                                      0x0000000000002000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET                                   0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB                                      14
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB                                      14
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK                                     0x0000000000004000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET                                   0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB                                      15
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB                                      15
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK                                     0x0000000000008000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB                              16
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB                              16
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK                             0x0000000000010000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET                              0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB                                 17
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB                                 17
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK                                0x0000000000020000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET                        0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB                           18
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB                           18
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK                          0x0000000000040000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET                       0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB                          19
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB                          19
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK                         0x0000000000080000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET                      0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB                         20
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB                         20
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK                        0x0000000000100000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET                    0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB                       21
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB                       21
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK                      0x0000000000200000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET                    0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB                       22
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB                       22
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK                      0x0000000000400000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET                               0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB                                  23
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB                                  23
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK                                 0x0000000000800000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET                     0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB                        24
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB                        24
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK                       0x0000000001000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET                                  0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB                                     25
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB                                     25
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK                                    0x0000000002000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET                                   0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB                                      26
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB                                      26
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK                                     0x0000000004000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET            0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB               27
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB               27
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK              0x0000000008000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET                0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB                   28
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB                   28
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK                  0x0000000010000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET                              0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB                                 29
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB                                 29
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK                                0x0000000020000000
-
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET                                    0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB                                       30
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB                                       30
-#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK                                      0x0000000040000000
-
-#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET                          0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK                            0x0000000080000000
-
-#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                         0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                            32
-#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                            47
-#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                           0x0000ffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET                                          0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB                                             48
-#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB                                             48
-#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK                                            0x0001000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB              49
-#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB              50
-#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK             0x0006000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                  0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                     51
-#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                     51
-#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                    0x0008000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                          0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                             52
-#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                             52
-#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                            0x0010000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET                                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_AC_LSB                                              53
-#define REO_UPDATE_RX_REO_QUEUE_AC_MSB                                              54
-#define REO_UPDATE_RX_REO_QUEUE_AC_MASK                                             0x0060000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET                                          0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB                                             55
-#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB                                             55
-#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK                                            0x0080000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET                                          0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB                                             56
-#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB                                             56
-#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK                                            0x0100000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                  0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB                                     57
-#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB                                     57
-#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK                                    0x0200000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET                                     0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB                                        58
-#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB                                        58
-#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK                                       0x0400000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                              0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                 59
-#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                 59
-#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                0x0800000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                             0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                60
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                60
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                               0x1000000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                              61
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                              61
-#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                             0x2000000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                              62
-#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                              62
-#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                             0x4000000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                            0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                               63
-#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                               63
-#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                              0x8000000000000000
-
-#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                               0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                  0
-#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                  9
-#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                 0x00000000000003ff
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET                                      0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB                                         10
-#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB                                         11
-#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK                                        0x0000000000000c00
-
-#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET                                         0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB                                            12
-#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB                                            12
-#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK                                           0x0000000000001000
-
-#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET                                          0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB                                             13
-#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB                                             24
-#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK                                            0x0000000001ffe000
-
-#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                   0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                      25
-#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                      25
-#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                     0x0000000002000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                       0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                          26
-#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                          26
-#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                         0x0000000004000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET                                     0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB                                        27
-#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB                                        27
-#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK                                       0x0000000008000000
-
-#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET                             0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB                                28
-#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB                                28
-#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK                               0x0000000010000000
-
-#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET                                  0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB                                     29
-#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB                                     31
-#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK                                    0x00000000e0000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET                                      0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB                                         32
-#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB                                         63
-#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK                                        0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET                                     0x0000000000000018
-#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB                                        0
-#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB                                        31
-#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK                                       0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET                                     0x0000000000000018
-#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB                                        32
-#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB                                        63
-#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK                                       0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET                                    0x0000000000000020
-#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB                                       0
-#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB                                       31
-#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK                                      0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET                                0x0000000000000020
-#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB                                   32
-#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB                                   63
-#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK                                  0xffffffff00000000
-
-#endif
diff --git a/hw/fig/v1/reo_update_rx_reo_queue_status.h b/hw/fig/v1/reo_update_rx_reo_queue_status.h
deleted file mode 100644
index 907841095c53..000000000000
--- a/hw/fig/v1/reo_update_rx_reo_queue_status.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
-#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
-
-#include "uniform_reo_status_header.h"
-#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26
-
-#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13
-
-struct reo_update_rx_reo_queue_status {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2a                                             : 32;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t reserved_25a                                            : 28,
-                      looping_count                                           :  4;
-#else
-             struct   uniform_reo_status_header                                 status_header;
-             uint32_t reserved_2a                                             : 32;
-             uint32_t reserved_3a                                             : 32;
-             uint32_t reserved_4a                                             : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 32;
-             uint32_t reserved_8a                                             : 32;
-             uint32_t reserved_9a                                             : 32;
-             uint32_t reserved_10a                                            : 32;
-             uint32_t reserved_11a                                            : 32;
-             uint32_t reserved_12a                                            : 32;
-             uint32_t reserved_13a                                            : 32;
-             uint32_t reserved_14a                                            : 32;
-             uint32_t reserved_15a                                            : 32;
-             uint32_t reserved_16a                                            : 32;
-             uint32_t reserved_17a                                            : 32;
-             uint32_t reserved_18a                                            : 32;
-             uint32_t reserved_19a                                            : 32;
-             uint32_t reserved_20a                                            : 32;
-             uint32_t reserved_21a                                            : 32;
-             uint32_t reserved_22a                                            : 32;
-             uint32_t reserved_23a                                            : 32;
-             uint32_t reserved_24a                                            : 32;
-             uint32_t looping_count                                           :  4,
-                      reserved_25a                                            : 28;
-#endif
-};
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET       0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB          0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB          15
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK         0x000000000000ffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET      0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB         16
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB         25
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK        0x0000000003ff0000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB   26
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB   27
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK  0x000000000c000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET             0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                28
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK               0x00000000f0000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET               0x0000000000000000
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                  32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                  63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                 0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB                              0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB                              31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK                             0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET                           0x0000000000000008
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB                              32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB                              63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK                             0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET                           0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB                              0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB                              31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK                             0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET                           0x0000000000000010
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB                              32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB                              63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK                             0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET                           0x0000000000000018
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB                              0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB                              31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK                             0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET                           0x0000000000000018
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB                              32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB                              63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK                             0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET                           0x0000000000000020
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB                              0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB                              31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK                             0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET                           0x0000000000000020
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB                              32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB                              63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK                             0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET                          0x0000000000000028
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET                          0x0000000000000028
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET                          0x0000000000000030
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET                          0x0000000000000030
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET                          0x0000000000000038
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET                          0x0000000000000038
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET                          0x0000000000000040
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET                          0x0000000000000040
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET                          0x0000000000000048
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET                          0x0000000000000048
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET                          0x0000000000000050
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET                          0x0000000000000050
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET                          0x0000000000000058
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET                          0x0000000000000058
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB                             63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK                            0xffffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET                          0x0000000000000060
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB                             0
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB                             31
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK                            0x00000000ffffffff
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET                          0x0000000000000060
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB                             32
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB                             59
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK                            0x0fffffff00000000
-
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET                         0x0000000000000060
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB                            60
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB                            63
-#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK                           0xf000000000000000
-
-#endif
diff --git a/hw/fig/v1/rx_reo_queue.h b/hw/fig/v1/rx_reo_queue.h
deleted file mode 100644
index faaae001f79e..000000000000
--- a/hw/fig/v1/rx_reo_queue.h
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _RX_REO_QUEUE_H_
-#define _RX_REO_QUEUE_H_
-
-#include "uniform_descriptor_header.h"
-#define NUM_OF_DWORDS_RX_REO_QUEUE 32
-
-struct rx_reo_queue {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t receive_queue_number                                    : 16,
-                      reserved_1b                                             : 16;
-             uint32_t vld                                                     :  1,
-                      associated_link_descriptor_counter                      :  2,
-                      disable_duplicate_detection                             :  1,
-                      soft_reorder_enable                                     :  1,
-                      ac                                                      :  2,
-                      bar                                                     :  1,
-                      rty                                                     :  1,
-                      chk_2k_mode                                             :  1,
-                      oor_mode                                                :  1,
-                      ba_window_size                                          : 10,
-                      pn_check_needed                                         :  1,
-                      pn_shall_be_even                                        :  1,
-                      pn_shall_be_uneven                                      :  1,
-                      pn_handling_enable                                      :  1,
-                      pn_size                                                 :  2,
-                      ignore_ampdu_flag                                       :  1,
-                      reserved_2b                                             :  4;
-             uint32_t svld                                                    :  1,
-                      ssn                                                     : 12,
-                      current_index                                           : 10,
-                      seq_2k_error_detected_flag                              :  1,
-                      pn_error_detected_flag                                  :  1,
-                      reserved_3a                                             :  6,
-                      pn_valid                                                :  1;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t last_rx_enqueue_timestamp                               : 32;
-             uint32_t last_rx_dequeue_timestamp                               : 32;
-             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
-             uint32_t ptr_to_next_aging_queue_39_32                           :  8,
-                      reserved_11a                                            : 24;
-             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
-             uint32_t ptr_to_previous_aging_queue_39_32                       :  8,
-                      statistics_counter_index                                :  6,
-                      reserved_13a                                            : 18;
-             uint32_t rx_bitmap_31_0                                          : 32;
-             uint32_t rx_bitmap_63_32                                         : 32;
-             uint32_t rx_bitmap_95_64                                         : 32;
-             uint32_t rx_bitmap_127_96                                        : 32;
-             uint32_t rx_bitmap_159_128                                       : 32;
-             uint32_t rx_bitmap_191_160                                       : 32;
-             uint32_t rx_bitmap_223_192                                       : 32;
-             uint32_t rx_bitmap_255_224                                       : 32;
-             uint32_t rx_bitmap_287_256                                       : 32;
-             uint32_t current_mpdu_count                                      :  7,
-                      current_msdu_count                                      : 25;
-             uint32_t last_sn_reg_index                                       :  4,
-                      timeout_count                                           :  6,
-                      forward_due_to_bar_count                                :  6,
-                      duplicate_count                                         : 16;
-             uint32_t frames_in_order_count                                   : 24,
-                      bar_received_count                                      :  8;
-             uint32_t mpdu_frames_processed_count                             : 32;
-             uint32_t msdu_frames_processed_count                             : 32;
-             uint32_t total_processed_byte_count                              : 32;
-             uint32_t late_receive_mpdu_count                                 : 12,
-                      window_jump_2k                                          :  4,
-                      hole_count                                              : 16;
-             uint32_t aging_drop_mpdu_count                                   : 16,
-                      aging_drop_interval                                     :  8,
-                      reserved_30                                             :  8;
-             uint32_t reserved_31                                             : 32;
-#else
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t reserved_1b                                             : 16,
-                      receive_queue_number                                    : 16;
-             uint32_t reserved_2b                                             :  4,
-                      ignore_ampdu_flag                                       :  1,
-                      pn_size                                                 :  2,
-                      pn_handling_enable                                      :  1,
-                      pn_shall_be_uneven                                      :  1,
-                      pn_shall_be_even                                        :  1,
-                      pn_check_needed                                         :  1,
-                      ba_window_size                                          : 10,
-                      oor_mode                                                :  1,
-                      chk_2k_mode                                             :  1,
-                      rty                                                     :  1,
-                      bar                                                     :  1,
-                      ac                                                      :  2,
-                      soft_reorder_enable                                     :  1,
-                      disable_duplicate_detection                             :  1,
-                      associated_link_descriptor_counter                      :  2,
-                      vld                                                     :  1;
-             uint32_t pn_valid                                                :  1,
-                      reserved_3a                                             :  6,
-                      pn_error_detected_flag                                  :  1,
-                      seq_2k_error_detected_flag                              :  1,
-                      current_index                                           : 10,
-                      ssn                                                     : 12,
-                      svld                                                    :  1;
-             uint32_t pn_31_0                                                 : 32;
-             uint32_t pn_63_32                                                : 32;
-             uint32_t pn_95_64                                                : 32;
-             uint32_t pn_127_96                                               : 32;
-             uint32_t last_rx_enqueue_timestamp                               : 32;
-             uint32_t last_rx_dequeue_timestamp                               : 32;
-             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
-             uint32_t reserved_11a                                            : 24,
-                      ptr_to_next_aging_queue_39_32                           :  8;
-             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
-             uint32_t reserved_13a                                            : 18,
-                      statistics_counter_index                                :  6,
-                      ptr_to_previous_aging_queue_39_32                       :  8;
-             uint32_t rx_bitmap_31_0                                          : 32;
-             uint32_t rx_bitmap_63_32                                         : 32;
-             uint32_t rx_bitmap_95_64                                         : 32;
-             uint32_t rx_bitmap_127_96                                        : 32;
-             uint32_t rx_bitmap_159_128                                       : 32;
-             uint32_t rx_bitmap_191_160                                       : 32;
-             uint32_t rx_bitmap_223_192                                       : 32;
-             uint32_t rx_bitmap_255_224                                       : 32;
-             uint32_t rx_bitmap_287_256                                       : 32;
-             uint32_t current_msdu_count                                      : 25,
-                      current_mpdu_count                                      :  7;
-             uint32_t duplicate_count                                         : 16,
-                      forward_due_to_bar_count                                :  6,
-                      timeout_count                                           :  6,
-                      last_sn_reg_index                                       :  4;
-             uint32_t bar_received_count                                      :  8,
-                      frames_in_order_count                                   : 24;
-             uint32_t mpdu_frames_processed_count                             : 32;
-             uint32_t msdu_frames_processed_count                             : 32;
-             uint32_t total_processed_byte_count                              : 32;
-             uint32_t hole_count                                              : 16,
-                      window_jump_2k                                          :  4,
-                      late_receive_mpdu_count                                 : 12;
-             uint32_t reserved_30                                             :  8,
-                      aging_drop_interval                                     :  8,
-                      aging_drop_mpdu_count                                   : 16;
-             uint32_t reserved_31                                             : 32;
-#endif
-};
-
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB                                    0
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB                                    3
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
-
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
-
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
-
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
-#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
-
-#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x00000004
-#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                                       0
-#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                                       15
-#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                                      0x0000ffff
-
-#define RX_REO_QUEUE_RESERVED_1B_OFFSET                                             0x00000004
-#define RX_REO_QUEUE_RESERVED_1B_LSB                                                16
-#define RX_REO_QUEUE_RESERVED_1B_MSB                                                31
-#define RX_REO_QUEUE_RESERVED_1B_MASK                                               0xffff0000
-
-#define RX_REO_QUEUE_VLD_OFFSET                                                     0x00000008
-#define RX_REO_QUEUE_VLD_LSB                                                        0
-#define RX_REO_QUEUE_VLD_MSB                                                        0
-#define RX_REO_QUEUE_VLD_MASK                                                       0x00000001
-
-#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET                      0x00000008
-#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB                         1
-#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB                         2
-#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK                        0x00000006
-
-#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                             0x00000008
-#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                                3
-#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                                3
-#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                               0x00000008
-
-#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                                     0x00000008
-#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                                        4
-#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                                        4
-#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                                       0x00000010
-
-#define RX_REO_QUEUE_AC_OFFSET                                                      0x00000008
-#define RX_REO_QUEUE_AC_LSB                                                         5
-#define RX_REO_QUEUE_AC_MSB                                                         6
-#define RX_REO_QUEUE_AC_MASK                                                        0x00000060
-
-#define RX_REO_QUEUE_BAR_OFFSET                                                     0x00000008
-#define RX_REO_QUEUE_BAR_LSB                                                        7
-#define RX_REO_QUEUE_BAR_MSB                                                        7
-#define RX_REO_QUEUE_BAR_MASK                                                       0x00000080
-
-#define RX_REO_QUEUE_RTY_OFFSET                                                     0x00000008
-#define RX_REO_QUEUE_RTY_LSB                                                        8
-#define RX_REO_QUEUE_RTY_MSB                                                        8
-#define RX_REO_QUEUE_RTY_MASK                                                       0x00000100
-
-#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                             0x00000008
-#define RX_REO_QUEUE_CHK_2K_MODE_LSB                                                9
-#define RX_REO_QUEUE_CHK_2K_MODE_MSB                                                9
-#define RX_REO_QUEUE_CHK_2K_MODE_MASK                                               0x00000200
-
-#define RX_REO_QUEUE_OOR_MODE_OFFSET                                                0x00000008
-#define RX_REO_QUEUE_OOR_MODE_LSB                                                   10
-#define RX_REO_QUEUE_OOR_MODE_MSB                                                   10
-#define RX_REO_QUEUE_OOR_MODE_MASK                                                  0x00000400
-
-#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                                          0x00000008
-#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                             11
-#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                             20
-#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                            0x001ff800
-
-#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                                         0x00000008
-#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                            21
-#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                            21
-#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                           0x00200000
-
-#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                                        0x00000008
-#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                           22
-#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                           22
-#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                                          0x00400000
-
-#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                                      0x00000008
-#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                                         23
-#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                                         23
-#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                                        0x00800000
-
-#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                                      0x00000008
-#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                                         24
-#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                                         24
-#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                                        0x01000000
-
-#define RX_REO_QUEUE_PN_SIZE_OFFSET                                                 0x00000008
-#define RX_REO_QUEUE_PN_SIZE_LSB                                                    25
-#define RX_REO_QUEUE_PN_SIZE_MSB                                                    26
-#define RX_REO_QUEUE_PN_SIZE_MASK                                                   0x06000000
-
-#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                                       0x00000008
-#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                                          27
-#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                                          27
-#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                                         0x08000000
-
-#define RX_REO_QUEUE_RESERVED_2B_OFFSET                                             0x00000008
-#define RX_REO_QUEUE_RESERVED_2B_LSB                                                28
-#define RX_REO_QUEUE_RESERVED_2B_MSB                                                31
-#define RX_REO_QUEUE_RESERVED_2B_MASK                                               0xf0000000
-
-#define RX_REO_QUEUE_SVLD_OFFSET                                                    0x0000000c
-#define RX_REO_QUEUE_SVLD_LSB                                                       0
-#define RX_REO_QUEUE_SVLD_MSB                                                       0
-#define RX_REO_QUEUE_SVLD_MASK                                                      0x00000001
-
-#define RX_REO_QUEUE_SSN_OFFSET                                                     0x0000000c
-#define RX_REO_QUEUE_SSN_LSB                                                        1
-#define RX_REO_QUEUE_SSN_MSB                                                        12
-#define RX_REO_QUEUE_SSN_MASK                                                       0x00001ffe
-
-#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET                                           0x0000000c
-#define RX_REO_QUEUE_CURRENT_INDEX_LSB                                              13
-#define RX_REO_QUEUE_CURRENT_INDEX_MSB                                              22
-#define RX_REO_QUEUE_CURRENT_INDEX_MASK                                             0x007fe000
-
-#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                              0x0000000c
-#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                                 23
-#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                                 23
-#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                                0x00800000
-
-#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                                  0x0000000c
-#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                                     24
-#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                                     24
-#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                                    0x01000000
-
-#define RX_REO_QUEUE_RESERVED_3A_OFFSET                                             0x0000000c
-#define RX_REO_QUEUE_RESERVED_3A_LSB                                                25
-#define RX_REO_QUEUE_RESERVED_3A_MSB                                                30
-#define RX_REO_QUEUE_RESERVED_3A_MASK                                               0x7e000000
-
-#define RX_REO_QUEUE_PN_VALID_OFFSET                                                0x0000000c
-#define RX_REO_QUEUE_PN_VALID_LSB                                                   31
-#define RX_REO_QUEUE_PN_VALID_MSB                                                   31
-#define RX_REO_QUEUE_PN_VALID_MASK                                                  0x80000000
-
-#define RX_REO_QUEUE_PN_31_0_OFFSET                                                 0x00000010
-#define RX_REO_QUEUE_PN_31_0_LSB                                                    0
-#define RX_REO_QUEUE_PN_31_0_MSB                                                    31
-#define RX_REO_QUEUE_PN_31_0_MASK                                                   0xffffffff
-
-#define RX_REO_QUEUE_PN_63_32_OFFSET                                                0x00000014
-#define RX_REO_QUEUE_PN_63_32_LSB                                                   0
-#define RX_REO_QUEUE_PN_63_32_MSB                                                   31
-#define RX_REO_QUEUE_PN_63_32_MASK                                                  0xffffffff
-
-#define RX_REO_QUEUE_PN_95_64_OFFSET                                                0x00000018
-#define RX_REO_QUEUE_PN_95_64_LSB                                                   0
-#define RX_REO_QUEUE_PN_95_64_MSB                                                   31
-#define RX_REO_QUEUE_PN_95_64_MASK                                                  0xffffffff
-
-#define RX_REO_QUEUE_PN_127_96_OFFSET                                               0x0000001c
-#define RX_REO_QUEUE_PN_127_96_LSB                                                  0
-#define RX_REO_QUEUE_PN_127_96_MSB                                                  31
-#define RX_REO_QUEUE_PN_127_96_MASK                                                 0xffffffff
-
-#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                               0x00000020
-#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB                                  0
-#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB                                  31
-#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK                                 0xffffffff
-
-#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                               0x00000024
-#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB                                  0
-#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB                                  31
-#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK                                 0xffffffff
-
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET                            0x00000028
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB                               0
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB                               31
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK                              0xffffffff
-
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET                           0x0000002c
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB                              0
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB                              7
-#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK                             0x000000ff
-
-#define RX_REO_QUEUE_RESERVED_11A_OFFSET                                            0x0000002c
-#define RX_REO_QUEUE_RESERVED_11A_LSB                                               8
-#define RX_REO_QUEUE_RESERVED_11A_MSB                                               31
-#define RX_REO_QUEUE_RESERVED_11A_MASK                                              0xffffff00
-
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET                        0x00000030
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB                           0
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB                           31
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK                          0xffffffff
-
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET                       0x00000034
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB                          0
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB                          7
-#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK                         0x000000ff
-
-#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET                                0x00000034
-#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB                                   8
-#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB                                   13
-#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK                                  0x00003f00
-
-#define RX_REO_QUEUE_RESERVED_13A_OFFSET                                            0x00000034
-#define RX_REO_QUEUE_RESERVED_13A_LSB                                               14
-#define RX_REO_QUEUE_RESERVED_13A_MSB                                               31
-#define RX_REO_QUEUE_RESERVED_13A_MASK                                              0xffffc000
-
-#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET                                          0x00000038
-#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB                                             0
-#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB                                             31
-#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET                                         0x0000003c
-#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB                                            0
-#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB                                            31
-#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK                                           0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET                                         0x00000040
-#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB                                            0
-#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB                                            31
-#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK                                           0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET                                        0x00000044
-#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB                                           0
-#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB                                           31
-#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK                                          0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET                                       0x00000048
-#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB                                          0
-#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB                                          31
-#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK                                         0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET                                       0x0000004c
-#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB                                          0
-#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB                                          31
-#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK                                         0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET                                       0x00000050
-#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB                                          0
-#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB                                          31
-#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK                                         0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET                                       0x00000054
-#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB                                          0
-#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB                                          31
-#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK                                         0xffffffff
-
-#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET                                       0x00000058
-#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB                                          0
-#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB                                          31
-#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK                                         0xffffffff
-
-#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET                                      0x0000005c
-#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB                                         0
-#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB                                         6
-#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK                                        0x0000007f
-
-#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET                                      0x0000005c
-#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB                                         7
-#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB                                         31
-#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK                                        0xffffff80
-
-#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET                                       0x00000060
-#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB                                          0
-#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB                                          3
-#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK                                         0x0000000f
-
-#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET                                           0x00000060
-#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB                                              4
-#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB                                              9
-#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK                                             0x000003f0
-
-#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET                                0x00000060
-#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB                                   10
-#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB                                   15
-#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK                                  0x0000fc00
-
-#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET                                         0x00000060
-#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB                                            16
-#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB                                            31
-#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK                                           0xffff0000
-
-#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET                                   0x00000064
-#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB                                      0
-#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB                                      23
-#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK                                     0x00ffffff
-
-#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET                                      0x00000064
-#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB                                         24
-#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB                                         31
-#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK                                        0xff000000
-
-#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x00000068
-#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB                                0
-#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB                                31
-#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
-
-#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x0000006c
-#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB                                0
-#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB                                31
-#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
-
-#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                              0x00000070
-#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB                                 0
-#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB                                 31
-#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK                                0xffffffff
-
-#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET                                 0x00000074
-#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB                                    0
-#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB                                    11
-#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK                                   0x00000fff
-
-#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET                                          0x00000074
-#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB                                             12
-#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB                                             15
-#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK                                            0x0000f000
-
-#define RX_REO_QUEUE_HOLE_COUNT_OFFSET                                              0x00000074
-#define RX_REO_QUEUE_HOLE_COUNT_LSB                                                 16
-#define RX_REO_QUEUE_HOLE_COUNT_MSB                                                 31
-#define RX_REO_QUEUE_HOLE_COUNT_MASK                                                0xffff0000
-
-#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET                                   0x00000078
-#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB                                      0
-#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB                                      15
-#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK                                     0x0000ffff
-
-#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET                                     0x00000078
-#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB                                        16
-#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB                                        23
-#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK                                       0x00ff0000
-
-#define RX_REO_QUEUE_RESERVED_30_OFFSET                                             0x00000078
-#define RX_REO_QUEUE_RESERVED_30_LSB                                                24
-#define RX_REO_QUEUE_RESERVED_30_MSB                                                31
-#define RX_REO_QUEUE_RESERVED_30_MASK                                               0xff000000
-
-#define RX_REO_QUEUE_RESERVED_31_OFFSET                                             0x0000007c
-#define RX_REO_QUEUE_RESERVED_31_LSB                                                0
-#define RX_REO_QUEUE_RESERVED_31_MSB                                                31
-#define RX_REO_QUEUE_RESERVED_31_MASK                                               0xffffffff
-
-#endif
diff --git a/hw/fig/v1/rx_reo_queue_1k.h b/hw/fig/v1/rx_reo_queue_1k.h
deleted file mode 100644
index 40c4dd19bcc0..000000000000
--- a/hw/fig/v1/rx_reo_queue_1k.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _RX_REO_QUEUE_1K_H_
-#define _RX_REO_QUEUE_1K_H_
-
-#include "uniform_descriptor_header.h"
-#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
-
-struct rx_reo_queue_1k {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t rx_bitmap_319_288                                       : 32;
-             uint32_t rx_bitmap_351_320                                       : 32;
-             uint32_t rx_bitmap_383_352                                       : 32;
-             uint32_t rx_bitmap_415_384                                       : 32;
-             uint32_t rx_bitmap_447_416                                       : 32;
-             uint32_t rx_bitmap_479_448                                       : 32;
-             uint32_t rx_bitmap_511_480                                       : 32;
-             uint32_t rx_bitmap_543_512                                       : 32;
-             uint32_t rx_bitmap_575_544                                       : 32;
-             uint32_t rx_bitmap_607_576                                       : 32;
-             uint32_t rx_bitmap_639_608                                       : 32;
-             uint32_t rx_bitmap_671_640                                       : 32;
-             uint32_t rx_bitmap_703_672                                       : 32;
-             uint32_t rx_bitmap_735_704                                       : 32;
-             uint32_t rx_bitmap_767_736                                       : 32;
-             uint32_t rx_bitmap_799_768                                       : 32;
-             uint32_t rx_bitmap_831_800                                       : 32;
-             uint32_t rx_bitmap_863_832                                       : 32;
-             uint32_t rx_bitmap_895_864                                       : 32;
-             uint32_t rx_bitmap_927_896                                       : 32;
-             uint32_t rx_bitmap_959_928                                       : 32;
-             uint32_t rx_bitmap_991_960                                       : 32;
-             uint32_t rx_bitmap_1023_992                                      : 32;
-             uint32_t reserved_24                                             : 32;
-             uint32_t reserved_25                                             : 32;
-             uint32_t reserved_26                                             : 32;
-             uint32_t reserved_27                                             : 32;
-             uint32_t reserved_28                                             : 32;
-             uint32_t reserved_29                                             : 32;
-             uint32_t reserved_30                                             : 32;
-             uint32_t reserved_31                                             : 32;
-#else
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t rx_bitmap_319_288                                       : 32;
-             uint32_t rx_bitmap_351_320                                       : 32;
-             uint32_t rx_bitmap_383_352                                       : 32;
-             uint32_t rx_bitmap_415_384                                       : 32;
-             uint32_t rx_bitmap_447_416                                       : 32;
-             uint32_t rx_bitmap_479_448                                       : 32;
-             uint32_t rx_bitmap_511_480                                       : 32;
-             uint32_t rx_bitmap_543_512                                       : 32;
-             uint32_t rx_bitmap_575_544                                       : 32;
-             uint32_t rx_bitmap_607_576                                       : 32;
-             uint32_t rx_bitmap_639_608                                       : 32;
-             uint32_t rx_bitmap_671_640                                       : 32;
-             uint32_t rx_bitmap_703_672                                       : 32;
-             uint32_t rx_bitmap_735_704                                       : 32;
-             uint32_t rx_bitmap_767_736                                       : 32;
-             uint32_t rx_bitmap_799_768                                       : 32;
-             uint32_t rx_bitmap_831_800                                       : 32;
-             uint32_t rx_bitmap_863_832                                       : 32;
-             uint32_t rx_bitmap_895_864                                       : 32;
-             uint32_t rx_bitmap_927_896                                       : 32;
-             uint32_t rx_bitmap_959_928                                       : 32;
-             uint32_t rx_bitmap_991_960                                       : 32;
-             uint32_t rx_bitmap_1023_992                                      : 32;
-             uint32_t reserved_24                                             : 32;
-             uint32_t reserved_25                                             : 32;
-             uint32_t reserved_26                                             : 32;
-             uint32_t reserved_27                                             : 32;
-             uint32_t reserved_28                                             : 32;
-             uint32_t reserved_29                                             : 32;
-             uint32_t reserved_30                                             : 32;
-             uint32_t reserved_31                                             : 32;
-#endif
-};
-
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET                              0x00000000
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB                                 0
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB                                 3
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK                                0x0000000f
-
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                        0x00000000
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                           4
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                           7
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                          0x000000f0
-
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET               0x00000000
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                  8
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                  27
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                 0x0fffff00
-
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                        0x00000000
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB                           28
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB                           31
-#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK                          0xf0000000
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET                                    0x00000004
-#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET                                    0x00000008
-#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET                                    0x0000000c
-#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET                                    0x00000010
-#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET                                    0x00000014
-#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET                                    0x00000018
-#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET                                    0x0000001c
-#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET                                    0x00000020
-#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET                                    0x00000024
-#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET                                    0x00000028
-#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET                                    0x0000002c
-#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET                                    0x00000030
-#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET                                    0x00000034
-#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET                                    0x00000038
-#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET                                    0x0000003c
-#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET                                    0x00000040
-#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET                                    0x00000044
-#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET                                    0x00000048
-#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET                                    0x0000004c
-#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET                                    0x00000050
-#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET                                    0x00000054
-#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET                                    0x00000058
-#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB                                       0
-#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB                                       31
-#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK                                      0xffffffff
-
-#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET                                   0x0000005c
-#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB                                      0
-#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB                                      31
-#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK                                     0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET                                          0x00000060
-#define RX_REO_QUEUE_1K_RESERVED_24_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_24_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_24_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET                                          0x00000064
-#define RX_REO_QUEUE_1K_RESERVED_25_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_25_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_25_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET                                          0x00000068
-#define RX_REO_QUEUE_1K_RESERVED_26_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_26_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_26_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET                                          0x0000006c
-#define RX_REO_QUEUE_1K_RESERVED_27_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_27_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_27_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET                                          0x00000070
-#define RX_REO_QUEUE_1K_RESERVED_28_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_28_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_28_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET                                          0x00000074
-#define RX_REO_QUEUE_1K_RESERVED_29_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_29_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_29_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET                                          0x00000078
-#define RX_REO_QUEUE_1K_RESERVED_30_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_30_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_30_MASK                                            0xffffffff
-
-#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET                                          0x0000007c
-#define RX_REO_QUEUE_1K_RESERVED_31_LSB                                             0
-#define RX_REO_QUEUE_1K_RESERVED_31_MSB                                             31
-#define RX_REO_QUEUE_1K_RESERVED_31_MASK                                            0xffffffff
-
-#endif
diff --git a/hw/fig/v1/rx_reo_queue_ext.h b/hw/fig/v1/rx_reo_queue_ext.h
deleted file mode 100644
index 66554c7633f3..000000000000
--- a/hw/fig/v1/rx_reo_queue_ext.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _RX_REO_QUEUE_EXT_H_
-#define _RX_REO_QUEUE_EXT_H_
-
-#include "rx_mpdu_link_ptr.h"
-#include "uniform_descriptor_header.h"
-#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
-
-struct rx_reo_queue_ext {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t reserved_1a                                             : 32;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
-#else
-             struct   uniform_descriptor_header                                 descriptor_header;
-             uint32_t reserved_1a                                             : 32;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
-             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
-#endif
-};
-
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET                             0x00000000
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB                                0
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB                                3
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK                               0x0000000f
-
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                       0x00000000
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                          4
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                          7
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                         0x000000f0
-
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET              0x00000000
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                 8
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                 27
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                0x0fffff00
-
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                       0x00000000
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB                          28
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB                          31
-#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK                         0xf0000000
-
-#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET                                         0x00000004
-#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB                                            0
-#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB                                            31
-#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK                                           0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
-
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
-#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
-
-#endif
diff --git a/hw/fig/v1/tcl_data_cmd.h b/hw/fig/v1/tcl_data_cmd.h
deleted file mode 100644
index dd90a2cdcb73..000000000000
--- a/hw/fig/v1/tcl_data_cmd.h
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _TCL_DATA_CMD_H_
-#define _TCL_DATA_CMD_H_
-
-#include "buffer_addr_info.h"
-#define NUM_OF_DWORDS_TCL_DATA_CMD 8
-
-struct tcl_data_cmd {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             struct   buffer_addr_info                                          buf_addr_info;
-             uint32_t tcl_cmd_type                                            :  1,
-                      buf_or_ext_desc_type                                    :  1,
-                      bank_id                                                 :  6,
-                      tx_notify_frame                                         :  3,
-                      header_length_read_sel                                  :  1,
-                      buffer_timestamp                                        : 19,
-                      buffer_timestamp_valid                                  :  1;
-             uint32_t reserved_3a                                             : 16,
-                      tcl_cmd_number                                          : 16;
-             uint32_t data_length                                             : 16,
-                      ipv4_checksum_en                                        :  1,
-                      udp_over_ipv4_checksum_en                               :  1,
-                      udp_over_ipv6_checksum_en                               :  1,
-                      tcp_over_ipv4_checksum_en                               :  1,
-                      tcp_over_ipv6_checksum_en                               :  1,
-                      to_fw                                                   :  1,
-                      reserved_4a                                             :  1,
-                      packet_offset                                           :  9;
-             uint32_t hlos_tid_overwrite                                      :  1,
-                      flow_override_enable                                    :  1,
-                      who_classify_info_sel                                   :  2,
-                      hlos_tid                                                :  4,
-                      flow_override                                           :  1,
-                      pmac_id                                                 :  2,
-                      msdu_color                                              :  2,
-                      reserved_5a                                             : 11,
-                      vdev_id                                                 :  8;
-             uint32_t search_index                                            : 20,
-                      cache_set_num                                           :  4,
-                      index_lookup_override                                   :  1,
-                      reserved_6a                                             :  7;
-             uint32_t reserved_7a                                             : 20,
-                      ring_id                                                 :  8,
-                      looping_count                                           :  4;
-#else
-             struct   buffer_addr_info                                          buf_addr_info;
-             uint32_t buffer_timestamp_valid                                  :  1,
-                      buffer_timestamp                                        : 19,
-                      header_length_read_sel                                  :  1,
-                      tx_notify_frame                                         :  3,
-                      bank_id                                                 :  6,
-                      buf_or_ext_desc_type                                    :  1,
-                      tcl_cmd_type                                            :  1;
-             uint32_t tcl_cmd_number                                          : 16,
-                      reserved_3a                                             : 16;
-             uint32_t packet_offset                                           :  9,
-                      reserved_4a                                             :  1,
-                      to_fw                                                   :  1,
-                      tcp_over_ipv6_checksum_en                               :  1,
-                      tcp_over_ipv4_checksum_en                               :  1,
-                      udp_over_ipv6_checksum_en                               :  1,
-                      udp_over_ipv4_checksum_en                               :  1,
-                      ipv4_checksum_en                                        :  1,
-                      data_length                                             : 16;
-             uint32_t vdev_id                                                 :  8,
-                      reserved_5a                                             : 11,
-                      msdu_color                                              :  2,
-                      pmac_id                                                 :  2,
-                      flow_override                                           :  1,
-                      hlos_tid                                                :  4,
-                      who_classify_info_sel                                   :  2,
-                      flow_override_enable                                    :  1,
-                      hlos_tid_overwrite                                      :  1;
-             uint32_t reserved_6a                                             :  7,
-                      index_lookup_override                                   :  1,
-                      cache_set_num                                           :  4,
-                      search_index                                            : 20;
-             uint32_t looping_count                                           :  4,
-                      ring_id                                                 :  8,
-                      reserved_7a                                             : 20;
-#endif
-};
-
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                          0x00000000
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                             0
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                             31
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                            0xffffffff
-
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                         0x00000004
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                            0
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                            7
-#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                           0x000000ff
-
-#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                     0x00000004
-#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                        8
-#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                        11
-#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                       0x00000f00
-
-#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                          0x00000004
-#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                             12
-#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                             31
-#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                            0xfffff000
-
-#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET                                            0x00000008
-#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB                                               0
-#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB                                               0
-#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK                                              0x00000001
-
-#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                    0x00000008
-#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                       1
-#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                       1
-#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                      0x00000002
-
-#define TCL_DATA_CMD_BANK_ID_OFFSET                                                 0x00000008
-#define TCL_DATA_CMD_BANK_ID_LSB                                                    2
-#define TCL_DATA_CMD_BANK_ID_MSB                                                    7
-#define TCL_DATA_CMD_BANK_ID_MASK                                                   0x000000fc
-
-#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET                                         0x00000008
-#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB                                            8
-#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB                                            10
-#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK                                           0x00000700
-
-#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET                                  0x00000008
-#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB                                     11
-#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB                                     11
-#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK                                    0x00000800
-
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET                                        0x00000008
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB                                           12
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB                                           30
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK                                          0x7ffff000
-
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                  0x00000008
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB                                     31
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB                                     31
-#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK                                    0x80000000
-
-#define TCL_DATA_CMD_RESERVED_3A_OFFSET                                             0x0000000c
-#define TCL_DATA_CMD_RESERVED_3A_LSB                                                0
-#define TCL_DATA_CMD_RESERVED_3A_MSB                                                15
-#define TCL_DATA_CMD_RESERVED_3A_MASK                                               0x0000ffff
-
-#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET                                          0x0000000c
-#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB                                             16
-#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB                                             31
-#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK                                            0xffff0000
-
-#define TCL_DATA_CMD_DATA_LENGTH_OFFSET                                             0x00000010
-#define TCL_DATA_CMD_DATA_LENGTH_LSB                                                0
-#define TCL_DATA_CMD_DATA_LENGTH_MSB                                                15
-#define TCL_DATA_CMD_DATA_LENGTH_MASK                                               0x0000ffff
-
-#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET                                        0x00000010
-#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB                                           16
-#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB                                           16
-#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK                                          0x00010000
-
-#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
-#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                  17
-#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                  17
-#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00020000
-
-#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
-#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                  18
-#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                  18
-#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00040000
-
-#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
-#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                  19
-#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                  19
-#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00080000
-
-#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
-#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                  20
-#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                  20
-#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00100000
-
-#define TCL_DATA_CMD_TO_FW_OFFSET                                                   0x00000010
-#define TCL_DATA_CMD_TO_FW_LSB                                                      21
-#define TCL_DATA_CMD_TO_FW_MSB                                                      21
-#define TCL_DATA_CMD_TO_FW_MASK                                                     0x00200000
-
-#define TCL_DATA_CMD_RESERVED_4A_OFFSET                                             0x00000010
-#define TCL_DATA_CMD_RESERVED_4A_LSB                                                22
-#define TCL_DATA_CMD_RESERVED_4A_MSB                                                22
-#define TCL_DATA_CMD_RESERVED_4A_MASK                                               0x00400000
-
-#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET                                           0x00000010
-#define TCL_DATA_CMD_PACKET_OFFSET_LSB                                              23
-#define TCL_DATA_CMD_PACKET_OFFSET_MSB                                              31
-#define TCL_DATA_CMD_PACKET_OFFSET_MASK                                             0xff800000
-
-#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET                                      0x00000014
-#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB                                         0
-#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB                                         0
-#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK                                        0x00000001
-
-#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                    0x00000014
-#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB                                       1
-#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB                                       1
-#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK                                      0x00000002
-
-#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET                                   0x00000014
-#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB                                      2
-#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB                                      3
-#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK                                     0x0000000c
-
-#define TCL_DATA_CMD_HLOS_TID_OFFSET                                                0x00000014
-#define TCL_DATA_CMD_HLOS_TID_LSB                                                   4
-#define TCL_DATA_CMD_HLOS_TID_MSB                                                   7
-#define TCL_DATA_CMD_HLOS_TID_MASK                                                  0x000000f0
-
-#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET                                           0x00000014
-#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB                                              8
-#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB                                              8
-#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK                                             0x00000100
-
-#define TCL_DATA_CMD_PMAC_ID_OFFSET                                                 0x00000014
-#define TCL_DATA_CMD_PMAC_ID_LSB                                                    9
-#define TCL_DATA_CMD_PMAC_ID_MSB                                                    10
-#define TCL_DATA_CMD_PMAC_ID_MASK                                                   0x00000600
-
-#define TCL_DATA_CMD_MSDU_COLOR_OFFSET                                              0x00000014
-#define TCL_DATA_CMD_MSDU_COLOR_LSB                                                 11
-#define TCL_DATA_CMD_MSDU_COLOR_MSB                                                 12
-#define TCL_DATA_CMD_MSDU_COLOR_MASK                                                0x00001800
-
-#define TCL_DATA_CMD_RESERVED_5A_OFFSET                                             0x00000014
-#define TCL_DATA_CMD_RESERVED_5A_LSB                                                13
-#define TCL_DATA_CMD_RESERVED_5A_MSB                                                23
-#define TCL_DATA_CMD_RESERVED_5A_MASK                                               0x00ffe000
-
-#define TCL_DATA_CMD_VDEV_ID_OFFSET                                                 0x00000014
-#define TCL_DATA_CMD_VDEV_ID_LSB                                                    24
-#define TCL_DATA_CMD_VDEV_ID_MSB                                                    31
-#define TCL_DATA_CMD_VDEV_ID_MASK                                                   0xff000000
-
-#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET                                            0x00000018
-#define TCL_DATA_CMD_SEARCH_INDEX_LSB                                               0
-#define TCL_DATA_CMD_SEARCH_INDEX_MSB                                               19
-#define TCL_DATA_CMD_SEARCH_INDEX_MASK                                              0x000fffff
-
-#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET                                           0x00000018
-#define TCL_DATA_CMD_CACHE_SET_NUM_LSB                                              20
-#define TCL_DATA_CMD_CACHE_SET_NUM_MSB                                              23
-#define TCL_DATA_CMD_CACHE_SET_NUM_MASK                                             0x00f00000
-
-#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET                                   0x00000018
-#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB                                      24
-#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB                                      24
-#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK                                     0x01000000
-
-#define TCL_DATA_CMD_RESERVED_6A_OFFSET                                             0x00000018
-#define TCL_DATA_CMD_RESERVED_6A_LSB                                                25
-#define TCL_DATA_CMD_RESERVED_6A_MSB                                                31
-#define TCL_DATA_CMD_RESERVED_6A_MASK                                               0xfe000000
-
-#define TCL_DATA_CMD_RESERVED_7A_OFFSET                                             0x0000001c
-#define TCL_DATA_CMD_RESERVED_7A_LSB                                                0
-#define TCL_DATA_CMD_RESERVED_7A_MSB                                                19
-#define TCL_DATA_CMD_RESERVED_7A_MASK                                               0x000fffff
-
-#define TCL_DATA_CMD_RING_ID_OFFSET                                                 0x0000001c
-#define TCL_DATA_CMD_RING_ID_LSB                                                    20
-#define TCL_DATA_CMD_RING_ID_MSB                                                    27
-#define TCL_DATA_CMD_RING_ID_MASK                                                   0x0ff00000
-
-#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET                                           0x0000001c
-#define TCL_DATA_CMD_LOOPING_COUNT_LSB                                              28
-#define TCL_DATA_CMD_LOOPING_COUNT_MSB                                              31
-#define TCL_DATA_CMD_LOOPING_COUNT_MASK                                             0xf0000000
-
-#endif
diff --git a/hw/fig/v1/tcl_gse_cmd.h b/hw/fig/v1/tcl_gse_cmd.h
deleted file mode 100644
index 992368aa31a1..000000000000
--- a/hw/fig/v1/tcl_gse_cmd.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _TCL_GSE_CMD_H_
-#define _TCL_GSE_CMD_H_
-
-#define NUM_OF_DWORDS_TCL_GSE_CMD 8
-
-struct tcl_gse_cmd {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             uint32_t control_buffer_addr_31_0                                : 32;
-             uint32_t control_buffer_addr_39_32                               :  8,
-                      gse_ctrl                                                :  4,
-                      gse_sel                                                 :  1,
-                      status_destination_ring_id                              :  1,
-                      swap                                                    :  1,
-                      index_search_en                                         :  1,
-                      cache_set_num                                           :  4,
-                      reserved_1a                                             : 12;
-             uint32_t tcl_cmd_type                                            :  1,
-                      reserved_2a                                             : 31;
-             uint32_t cmd_meta_data_31_0                                      : 32;
-             uint32_t cmd_meta_data_63_32                                     : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t reserved_7a                                             : 20,
-                      ring_id                                                 :  8,
-                      looping_count                                           :  4;
-#else
-             uint32_t control_buffer_addr_31_0                                : 32;
-             uint32_t reserved_1a                                             : 12,
-                      cache_set_num                                           :  4,
-                      index_search_en                                         :  1,
-                      swap                                                    :  1,
-                      status_destination_ring_id                              :  1,
-                      gse_sel                                                 :  1,
-                      gse_ctrl                                                :  4,
-                      control_buffer_addr_39_32                               :  8;
-             uint32_t reserved_2a                                             : 31,
-                      tcl_cmd_type                                            :  1;
-             uint32_t cmd_meta_data_31_0                                      : 32;
-             uint32_t cmd_meta_data_63_32                                     : 32;
-             uint32_t reserved_5a                                             : 32;
-             uint32_t reserved_6a                                             : 32;
-             uint32_t looping_count                                           :  4,
-                      ring_id                                                 :  8,
-                      reserved_7a                                             : 20;
-#endif
-};
-
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET                                 0x00000000
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB                                    0
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB                                    31
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK                                   0xffffffff
-
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET                                0x00000004
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB                                   0
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB                                   7
-#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK                                  0x000000ff
-
-#define TCL_GSE_CMD_GSE_CTRL_OFFSET                                                 0x00000004
-#define TCL_GSE_CMD_GSE_CTRL_LSB                                                    8
-#define TCL_GSE_CMD_GSE_CTRL_MSB                                                    11
-#define TCL_GSE_CMD_GSE_CTRL_MASK                                                   0x00000f00
-
-#define TCL_GSE_CMD_GSE_SEL_OFFSET                                                  0x00000004
-#define TCL_GSE_CMD_GSE_SEL_LSB                                                     12
-#define TCL_GSE_CMD_GSE_SEL_MSB                                                     12
-#define TCL_GSE_CMD_GSE_SEL_MASK                                                    0x00001000
-
-#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET                               0x00000004
-#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB                                  13
-#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB                                  13
-#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK                                 0x00002000
-
-#define TCL_GSE_CMD_SWAP_OFFSET                                                     0x00000004
-#define TCL_GSE_CMD_SWAP_LSB                                                        14
-#define TCL_GSE_CMD_SWAP_MSB                                                        14
-#define TCL_GSE_CMD_SWAP_MASK                                                       0x00004000
-
-#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET                                          0x00000004
-#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB                                             15
-#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB                                             15
-#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK                                            0x00008000
-
-#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET                                            0x00000004
-#define TCL_GSE_CMD_CACHE_SET_NUM_LSB                                               16
-#define TCL_GSE_CMD_CACHE_SET_NUM_MSB                                               19
-#define TCL_GSE_CMD_CACHE_SET_NUM_MASK                                              0x000f0000
-
-#define TCL_GSE_CMD_RESERVED_1A_OFFSET                                              0x00000004
-#define TCL_GSE_CMD_RESERVED_1A_LSB                                                 20
-#define TCL_GSE_CMD_RESERVED_1A_MSB                                                 31
-#define TCL_GSE_CMD_RESERVED_1A_MASK                                                0xfff00000
-
-#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET                                             0x00000008
-#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB                                                0
-#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB                                                0
-#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK                                               0x00000001
-
-#define TCL_GSE_CMD_RESERVED_2A_OFFSET                                              0x00000008
-#define TCL_GSE_CMD_RESERVED_2A_LSB                                                 1
-#define TCL_GSE_CMD_RESERVED_2A_MSB                                                 31
-#define TCL_GSE_CMD_RESERVED_2A_MASK                                                0xfffffffe
-
-#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET                                       0x0000000c
-#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB                                          0
-#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB                                          31
-#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK                                         0xffffffff
-
-#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET                                      0x00000010
-#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB                                         0
-#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB                                         31
-#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK                                        0xffffffff
-
-#define TCL_GSE_CMD_RESERVED_5A_OFFSET                                              0x00000014
-#define TCL_GSE_CMD_RESERVED_5A_LSB                                                 0
-#define TCL_GSE_CMD_RESERVED_5A_MSB                                                 31
-#define TCL_GSE_CMD_RESERVED_5A_MASK                                                0xffffffff
-
-#define TCL_GSE_CMD_RESERVED_6A_OFFSET                                              0x00000018
-#define TCL_GSE_CMD_RESERVED_6A_LSB                                                 0
-#define TCL_GSE_CMD_RESERVED_6A_MSB                                                 31
-#define TCL_GSE_CMD_RESERVED_6A_MASK                                                0xffffffff
-
-#define TCL_GSE_CMD_RESERVED_7A_OFFSET                                              0x0000001c
-#define TCL_GSE_CMD_RESERVED_7A_LSB                                                 0
-#define TCL_GSE_CMD_RESERVED_7A_MSB                                                 19
-#define TCL_GSE_CMD_RESERVED_7A_MASK                                                0x000fffff
-
-#define TCL_GSE_CMD_RING_ID_OFFSET                                                  0x0000001c
-#define TCL_GSE_CMD_RING_ID_LSB                                                     20
-#define TCL_GSE_CMD_RING_ID_MSB                                                     27
-#define TCL_GSE_CMD_RING_ID_MASK                                                    0x0ff00000
-
-#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET                                            0x0000001c
-#define TCL_GSE_CMD_LOOPING_COUNT_LSB                                               28
-#define TCL_GSE_CMD_LOOPING_COUNT_MSB                                               31
-#define TCL_GSE_CMD_LOOPING_COUNT_MASK                                              0xf0000000
-
-#endif
diff --git a/hw/fig/v1/uniform_reo_cmd_header.h b/hw/fig/v1/uniform_reo_cmd_header.h
deleted file mode 100644
index bcf7ed58b57c..000000000000
--- a/hw/fig/v1/uniform_reo_cmd_header.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _UNIFORM_REO_CMD_HEADER_H_
-#define _UNIFORM_REO_CMD_HEADER_H_
-
-#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
-
-struct uniform_reo_cmd_header {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             uint32_t reo_cmd_number                                          : 16,
-                      reo_status_required                                     :  1,
-                      reserved_0a                                             : 15;
-#else
-             uint32_t reserved_0a                                             : 15,
-                      reo_status_required                                     :  1,
-                      reo_cmd_number                                          : 16;
-#endif
-};
-
-#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET                                0x00000000
-#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB                                   0
-#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB                                   15
-#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK                                  0x0000ffff
-
-#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                           0x00000000
-#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB                              16
-#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB                              16
-#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK                             0x00010000
-
-#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET                                   0x00000000
-#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB                                      17
-#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB                                      31
-#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK                                     0xfffe0000
-
-#endif
diff --git a/hw/fig/v1/uniform_reo_status_header.h b/hw/fig/v1/uniform_reo_status_header.h
deleted file mode 100644
index b016537dffff..000000000000
--- a/hw/fig/v1/uniform_reo_status_header.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _UNIFORM_REO_STATUS_HEADER_H_
-#define _UNIFORM_REO_STATUS_HEADER_H_
-
-#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
-
-struct uniform_reo_status_header {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             uint32_t reo_status_number                                       : 16,
-                      cmd_execution_time                                      : 10,
-                      reo_cmd_execution_status                                :  2,
-                      reserved_0a                                             :  4;
-             uint32_t timestamp                                               : 32;
-#else
-             uint32_t reserved_0a                                             :  4,
-                      reo_cmd_execution_status                                :  2,
-                      cmd_execution_time                                      : 10,
-                      reo_status_number                                       : 16;
-             uint32_t timestamp                                               : 32;
-#endif
-};
-
-#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET                          0x00000000
-#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB                             0
-#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB                             15
-#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK                            0x0000ffff
-
-#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET                         0x00000000
-#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                            16
-#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                            25
-#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                           0x03ff0000
-
-#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET                   0x00000000
-#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB                      26
-#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB                      27
-#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK                     0x0c000000
-
-#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET                                0x00000000
-#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB                                   28
-#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB                                   31
-#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK                                  0xf0000000
-
-#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET                                  0x00000004
-#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB                                     0
-#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB                                     31
-#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK                                    0xffffffff
-
-#endif
diff --git a/hw/fig/v1/wbm2sw_completion_ring_tx.h b/hw/fig/v1/wbm2sw_completion_ring_tx.h
deleted file mode 100644
index 6031ed7e119e..000000000000
--- a/hw/fig/v1/wbm2sw_completion_ring_tx.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
- * SPDX-License-Identifier: ISC
- */
-
-#ifndef _WBM2SW_COMPLETION_RING_TX_H_
-#define _WBM2SW_COMPLETION_RING_TX_H_
-
-#include "tx_rate_stats_info.h"
-#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
-
-struct wbm2sw_completion_ring_tx {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
-             uint32_t buffer_virt_addr_31_0                                   : 32;
-             uint32_t buffer_virt_addr_63_32                                  : 32;
-             uint32_t release_source_module                                   :  3,
-                      cache_id                                                :  1,
-                      reserved_2a                                             :  2,
-                      buffer_or_desc_type                                     :  3,
-                      return_buffer_manager                                   :  4,
-                      tqm_release_reason                                      :  4,
-                      rbm_override_valid                                      :  1,
-                      sw_buffer_cookie_11_0                                   : 12,
-                      cookie_conversion_status                                :  1,
-                      wbm_internal_error                                      :  1;
-             uint32_t tqm_status_number                                       : 24,
-                      transmit_count                                          :  7,
-                      sw_release_details_valid                                :  1;
-             uint32_t ack_frame_rssi                                          :  8,
-                      first_msdu                                              :  1,
-                      last_msdu                                               :  1,
-                      fw_tx_notify_frame                                      :  3,
-                      buffer_timestamp                                        : 19;
-             struct   tx_rate_stats_info                                        tx_rate_stats;
-             uint32_t sw_peer_id                                              : 16,
-                      tid                                                     :  4,
-                      sw_buffer_cookie_19_12                                  :  8,
-                      looping_count                                           :  4;
-#else
-             uint32_t buffer_virt_addr_31_0                                   : 32;
-             uint32_t buffer_virt_addr_63_32                                  : 32;
-             uint32_t wbm_internal_error                                      :  1,
-                      cookie_conversion_status                                :  1,
-                      sw_buffer_cookie_11_0                                   : 12,
-                      rbm_override_valid                                      :  1,
-                      tqm_release_reason                                      :  4,
-                      return_buffer_manager                                   :  4,
-                      buffer_or_desc_type                                     :  3,
-                      reserved_2a                                             :  2,
-                      cache_id                                                :  1,
-                      release_source_module                                   :  3;
-             uint32_t sw_release_details_valid                                :  1,
-                      transmit_count                                          :  7,
-                      tqm_status_number                                       : 24;
-             uint32_t buffer_timestamp                                        : 19,
-                      fw_tx_notify_frame                                      :  3,
-                      last_msdu                                               :  1,
-                      first_msdu                                              :  1,
-                      ack_frame_rssi                                          :  8;
-             struct   tx_rate_stats_info                                        tx_rate_stats;
-             uint32_t looping_count                                           :  4,
-                      sw_buffer_cookie_19_12                                  :  8,
-                      tid                                                     :  4,
-                      sw_peer_id                                              : 16;
-#endif
-};
-
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB                         0
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB                         31
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
-
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB                        0
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB                        31
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
-
-#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
-#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB                         0
-#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB                         2
-#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
-
-#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET                                   0x00000008
-#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB                                      3
-#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB                                      3
-#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK                                     0x00000008
-
-#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET                                0x00000008
-#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB                                   4
-#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB                                   5
-#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK                                  0x00000030
-
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB                           6
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB                           8
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
-
-#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
-#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB                         9
-#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB                         12
-#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
-
-#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET                         0x00000008
-#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB                            13
-#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB                            16
-#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK                           0x0001e000
-
-#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET                         0x00000008
-#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB                            17
-#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB                            17
-#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK                           0x00020000
-
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET                      0x00000008
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB                         18
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB                         29
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK                        0x3ffc0000
-
-#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
-#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB                      30
-#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB                      30
-#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK                     0x40000000
-
-#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
-#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB                            31
-#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB                            31
-#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK                           0x80000000
-
-#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET                          0x0000000c
-#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB                             0
-#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB                             23
-#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK                            0x00ffffff
-
-#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET                             0x0000000c
-#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB                                24
-#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB                                30
-#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK                               0x7f000000
-
-#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                   0x0000000c
-#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                      31
-#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                      31
-#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                     0x80000000
-
-#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET                             0x00000010
-#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB                                0
-#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB                                7
-#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK                               0x000000ff
-
-#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET                                 0x00000010
-#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB                                    8
-#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB                                    8
-#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK                                   0x00000100
-
-#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET                                  0x00000010
-#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB                                     9
-#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB                                     9
-#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK                                    0x00000200
-
-#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                         0x00000010
-#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB                            10
-#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB                            12
-#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK                           0x00001c00
-
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET                           0x00000010
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB                              13
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB                              31
-#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK                             0xffffe000
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET     0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB        0
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB        0
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK       0x00000001
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                  0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                     1
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                     3
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                    0x0000000e
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET            0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB               4
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB               7
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK              0x000000f0
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                   8
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                   8
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                  0x00000100
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                   9
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                   9
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                  0x00000200
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                 0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                    10
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                    11
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                   0x00000c00
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                 0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                    12
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                    15
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                   0x0000f000
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET           0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB              16
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB              16
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK             0x00010000
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                  0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                     17
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                     28
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                    0x1ffe0000
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                 0x00000014
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                    29
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                    31
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                   0xe0000000
-
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET        0x00000018
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB           0
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB           31
-#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK          0xffffffff
-
-#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET                                 0x0000001c
-#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB                                    0
-#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB                                    15
-#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK                                   0x0000ffff
-
-#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET                                        0x0000001c
-#define WBM2SW_COMPLETION_RING_TX_TID_LSB                                           16
-#define WBM2SW_COMPLETION_RING_TX_TID_MSB                                           19
-#define WBM2SW_COMPLETION_RING_TX_TID_MASK                                          0x000f0000
-
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET                     0x0000001c
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB                        20
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB                        27
-#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK                       0x0ff00000
-
-#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET                              0x0000001c
-#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB                                 28
-#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB                                 31
-#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK                                0xf0000000
-
-#endif

From 594c30b7ec92a37e4178bf3cbfd3504cb343ce18 Mon Sep 17 00:00:00 2001
From: Krupali Dhanvijay <kdhanvij@qti.qualcomm.com>
Date: Mon, 13 Oct 2025 10:57:26 +0530
Subject: [PATCH 072/290] qcacld-3.0: Consider intersected AKM for association
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Currently host overwrites crypto AKM with candidate AP’s AKM.
To choose the most secure AKM, host do sort of AKMs properly
based on security to use for association and can choose the
AKM which station do not advertise and results in Assoc failure.

To fix this, consider intersection of crypto and candidate AP’s
AKM for association instead of AKMs directly from AP config.

CRs-Fixed: 4320132
Change-Id: Id1813fc9f7fe76ff5ae9daf4da051067bddfdce1
---
 core/sme/src/csr/csr_util.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/core/sme/src/csr/csr_util.c b/core/sme/src/csr/csr_util.c
index f8c2f48b711c..ecd857bcd604 100644
--- a/core/sme/src/csr/csr_util.c
+++ b/core/sme/src/csr/csr_util.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -2451,6 +2451,7 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev,
 {
 	int32_t key_mgmt = 0;
 	int32_t neg_akm;
+	int32_t ap_akm = 0;
 	uint8_t i;
 
 	neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_KEY_MGMT);
@@ -2460,9 +2461,16 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev,
 	}
 
 	for (i = 0; i < ap_rsn.akm_suite_cnt; i++)
-		SET_PARAM(neg_akm,
+		SET_PARAM(ap_akm,
 			  wlan_crypto_rsn_suite_to_keymgmt(ap_rsn.akm_suite[i]));
 
+	/* Intersect crypto AKM and candidate AP's AKM */
+	neg_akm &= ap_akm;
+	if (neg_akm <= 0) {
+		sme_err("Invalid AKM suite");
+		return;
+	}
+
 	/*
 	 * As there can be multiple AKM present select the most secured AKM
 	 * present
@@ -2531,6 +2539,7 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev,
 {
 	int32_t ucastcipherset = 0;
 	int32_t neg_ucastcipher;
+	int32_t ap_ucastcipher = 0;
 	uint8_t i;
 
 	neg_ucastcipher = wlan_crypto_get_param(vdev,
@@ -2541,9 +2550,16 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev,
 	}
 
 	for (i = 0; i < ap_rsn.pwise_cipher_suite_count; i++)
-		SET_PARAM(neg_ucastcipher,
+		SET_PARAM(ap_ucastcipher,
 			  wlan_crypto_rsn_suite_to_cipher(ap_rsn.pwise_cipher_suites[i]));
 
+	/* Intersect crypto cipherset and candidate AP's cipherset */
+	neg_ucastcipher &= ap_ucastcipher;
+	if (neg_ucastcipher <= 0) {
+		sme_err("Invalid unicast cipherset");
+		return;
+	}
+
 	/*
 	 * As there can be multiple ucastcipher present select the most secured
 	 * ucastcipher present.

From 4f24c30f87fe396d393f092a1bcd2e1349a079de Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 19 Nov 2025 18:02:41 -0800
Subject: [PATCH 073/290] fw-api: CL 30998406 - update fw common interface
 files

Change-Id: Ie5d52121aa21a8d1b812380c87ec1279c681127c
CRs-Fixed: 3830439
---
 fw/htt.h         | 4 +++-
 fw/wmi_unified.h | 3 ++-
 fw/wmi_version.h | 2 +-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 8c6472c5cc46..3c949416f709 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -275,9 +275,10 @@
  * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG
  * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def.
  * 3.147 Add direct_refill flag in SRING_SETUP msg.
+ * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 147
+#define HTT_CURRENT_VERSION_MINOR 148
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -20074,6 +20075,7 @@ typedef enum {
     HTT_PEER_CFR_CAPTURE_BW_80MHZ    = 2,
     HTT_PEER_CFR_CAPTURE_BW_160MHZ   = 3,
     HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4,
+    HTT_PEER_CFR_CAPTURE_BW_320MHZ   = 5,
     HTT_PEER_CFR_CAPTURE_BW_MAX,
 } HTT_PEER_CFR_CAPTURE_BW;
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ff3cbbbb8ff2..61cc62260cab 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -21565,7 +21565,7 @@ typedef struct {
     union {
         struct {
             A_UINT32 hw_peer_id_valid :1,
-                     is_llbi_peer:     1,
+                     is_11bi_peer     :1,
                      reserved         :30;
         };
         A_UINT32 flags;
@@ -29443,6 +29443,7 @@ typedef enum {
     WMI_PEER_CFR_CAPTURE_BW_80MHZ    = 2,
     WMI_PEER_CFR_CAPTURE_BW_160MHZ   = 3,
     WMI_PEER_CFR_CAPTURE_BW_80_80MHZ = 4,
+    WMI_PEER_CFR_CAPTURE_BW_320MHZ   = 5,
     WMI_PEER_CFR_CAPTURE_BW_MAX,
 } WMI_PEER_CFR_CAPTURE_BW;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1e9c9ed9fbac..a9c471950e30 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1675
+#define __WMI_REVISION_ 1676
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ffdfc3e6264fce2ab85ad70de0f2caa5980032ad Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 19 Nov 2025 23:23:12 -0800
Subject: [PATCH 074/290] fw-api: CL 31012511 - update fw common interface
 files

Change-Id: Idee4d32565a665f57279254bd98e0cf20559bb94
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   1 +
 fw/wmi_tlv_defs.h | 213 ++++++++++++++++++++++++++++++++++++++++++++--
 fw/wmi_unified.h  |  37 ++++++++
 fw/wmi_version.h  |   2 +-
 4 files changed, 246 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index c510d1c0e2ec..705dcff7ec06 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -743,6 +743,7 @@ typedef  enum  {
     WMI_SERVICE_CONC_2VDEV_DCS_STATS_SUPPORT = 479, /* Indicate FW support for collecting DCS stats for more than 1 vdev (max 2 concurrent vdevs) */
     WMI_SERVICE_CFR_UNASSOC_RX_CAPTURE_SUPPORT = 480, /* Indicates FW supports RX-based unassociated CFR capture */
     WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */
+    WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a0cbcd887f9c..d8d8183cc5e7 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1531,6 +1531,10 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param,
     WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2114,6 +2118,8 @@ typedef enum {
     OP(WMI_NAN_ENABLE_CMDID) \
     OP(WMI_NAN_CONFIG_CMDID) \
     OP(WMI_NAN_DISABLE_CMDID) \
+    OP(WMI_VDEV_UNIFIED_CONNECT_CMDID) \
+    OP(WMI_VDEV_UNIFIED_DISCONNECT_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2462,6 +2468,8 @@ typedef enum {
     OP(WMI_NAN_DISABLE_CNF_EVENTID) \
     OP(WMI_NAN_DISABLE_IND_EVENTID) \
     OP(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID) \
+    OP(WMI_VDEV_UNIFIED_CONNECT_EVENTID) \
+    OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -2482,14 +2490,33 @@ WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID);
 #define WMITLV_TABLE_WMI_PEER_CREATE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, mlo_params, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_CREATE_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_VDEV_START_REQUEST_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_UP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID);
 
 /* Peer delete Cmd */
 #define WMITLV_TABLE_WMI_PEER_DELETE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, mlo_params, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_DELETE_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 2 disconnection related
+ * cmds:
+ *     WMI_PEER_DELETE_CMDID,
+ *     WMI_VDEV_STOP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID);
 
 /* Delete all peer Cmd */
@@ -2848,7 +2875,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_VDEV_START_REQUEST_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_UP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_REQUEST_CMDID);
 
 /* Vdev restart request cmd */
@@ -2993,7 +3031,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX)
-
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_ASSOC_V2_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_VDEV_START_REQUEST_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_UP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
 
 /* Peer Set Rate Report Condition Cmd */
@@ -3738,14 +3787,33 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_CMDID);
 #define WMITLV_TABLE_WMI_VDEV_UP_CMDID(id,op,buf,len)   \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, co_located_chan_info, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_UP_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_VDEV_START_REQUEST_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_UP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UP_CMDID);
 
 /* Vdev stop cmd */
 #define WMITLV_TABLE_WMI_VDEV_STOP_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, mlo_params, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 2 disconnection related
+ * cmds:
+ *     WMI_PEER_DELETE_CMDID,
+ *     WMI_VDEV_STOP_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOP_CMDID);
 
 /* Vdev down Cmd */
@@ -5984,6 +6052,70 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID);
 WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
 
 
+/* WMI command for unified connect cmd */
+#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param, wmi_vdev_unified_connect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, vdev_start_chan, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, vdev_start_noa_descriptors, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, vdev_start_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, vdev_start_partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, vdev_start_dbw_chan, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, vdev_start_dbw_chan_info, WMITLV_SIZE_VAR) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
+
+/* WMI command for unified disconnect cmd */
+#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param, wmi_vdev_unified_disconnect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, peer_delete_mlo_params, WMITLV_SIZE_VAR) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, vdev_stop_mlo_params, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
+
+
 
 /************************** TLV definitions of WMI events *******************************/
 
@@ -6231,11 +6363,30 @@ WMITLV_CREATE_PARAM_STRUC(WMI_QOS_NULL_FRAME_TX_COMPLETION_EVENTID);
 /* VDEV Start response Event */
 #define WMITLV_TABLE_WMI_VDEV_START_RESP_EVENTID(id,op,buf,len)                                                         \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_START_RESP_EVENTID needs to be included
+ * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related
+ * events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_VDEV_START_RESP_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_RESP_EVENTID);
 
 /* VDEV Stopped Event */
 #define WMITLV_TABLE_WMI_VDEV_STOPPED_EVENTID(id,op,buf,len)                                                         \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_STOPPED_EVENTID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related
+ * events:
+ *     WMI_PEER_DELETE_RESP_EVENTID,
+ *     WMI_VDEV_STOPPED_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOPPED_EVENTID);
 
 /* VDEV delete response Event */
@@ -7021,6 +7172,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATE_EVENTID);
 /* peer delete response Event */
 #define WMITLV_TABLE_WMI_PEER_DELETE_RESP_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_DELETE_RESP_EVENTID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related
+ * events:
+ *     WMI_PEER_DELETE_RESP_EVENTID,
+ *     WMI_VDEV_STOPPED_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_RESP_EVENTID);
 
 /* delete all peer response Event */
@@ -7031,11 +7191,31 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID);
 /* peer assoc conf Event */
 #define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_ASSOC_CONF_EVENTID needs to be included
+ * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related
+ * events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_VDEV_START_RESP_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID);
 
 /* peer create conf Event */
 #define WMITLV_TABLE_WMI_PEER_CREATE_CONF_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * Any new TLV addition in WMI_PEER_CREATE_CONF_EVENTID needs to be included
+ * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related
+ * events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_VDEV_START_RESP_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CONF_EVENTID);
 
 /* D0-WOW Disable Ack event */
@@ -8176,6 +8356,27 @@ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fi
 WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID);
 
 
+/* WMI command for unified connect event */
+#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param, wmi_vdev_unified_connect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_EVENTID);
+
+/* WMI command for unified disconnect event */
+#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param, wmi_vdev_unified_disconnect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \
+ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID);
+
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 61cc62260cab..3c148d3ba5d3 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -747,6 +747,13 @@ typedef enum {
     /** WMI cmd used to control DPS Assisting AP role config */
     WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID,
 
+    /** WMI cmd for unified connect */
+    WMI_VDEV_UNIFIED_CONNECT_CMDID,
+
+    /** WMI cmd for unified disconnect */
+    WMI_VDEV_UNIFIED_DISCONNECT_CMDID,
+
+
     /* peer specific commands */
 
     /** create a peer */
@@ -2070,6 +2077,10 @@ typedef enum {
     WMI_VDEV_OOB_CONNECTION_RESP_EVENTID,
     WMI_VDEV_VBSS_CONFIG_EVENTID,
     WMI_VDEV_TPC_IE_POWER_EVENTID,
+    /** WMI event for unified connect */
+    WMI_VDEV_UNIFIED_CONNECT_EVENTID,
+    /** WMI event for unified disconnect */
+    WMI_VDEV_UNIFIED_DISCONNECT_EVENTID,
 
     /* peer specific events */
     /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */
@@ -33435,6 +33446,32 @@ typedef enum {
     WMI_USD_SERVICE_PROTOCOL_TYPE_CSA_MATTER = 3,
 } WMI_USD_SERVICE_PROTOCOL_TYPE;
 
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param */
+    /** unique id identifying the VDEV, generated by the caller */
+    A_UINT32 vdev_id;
+} wmi_vdev_unified_connect_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param */
+    /** unique id identifying the VDEV, generated by the caller */
+    A_UINT32 vdev_id;
+} wmi_vdev_unified_disconnect_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param */
+    /** unique id identifying the VDEV, generated by the caller */
+    A_UINT32 vdev_id;
+} wmi_vdev_unified_connect_event_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param */
+    /** unique id identifying the VDEV, generated by the caller */
+    A_UINT32 vdev_id;
+} wmi_vdev_unified_disconnect_event_fixed_param;
+
+
 #define EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET     0
 #define EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK       1
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a9c471950e30..b70d34142501 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1676
+#define __WMI_REVISION_ 1677
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From beb514eec232f988675be85feb9231c330178fdd Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 21 Nov 2025 12:02:06 -0800
Subject: [PATCH 075/290] fw-api: CL 31021605 - update fw common interface
 files

Change-Id: Ib4e42d837b9746ce12b65e3697359615f044ee9a
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  8 ++++++-
 fw/wmi_unified.h  | 54 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 705dcff7ec06..6ba4f4c06cd7 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -744,6 +744,7 @@ typedef  enum  {
     WMI_SERVICE_CFR_UNASSOC_RX_CAPTURE_SUPPORT = 480, /* Indicates FW supports RX-based unassociated CFR capture */
     WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */
     WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */
+    WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d8d8183cc5e7..871590bb4e78 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1535,6 +1535,9 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_beacon_stats,
+    WMITLV_TAG_STRUC_wmi_vdev_congestion_stats,
+    WMITLV_TAG_STRUC_wmi_vdev_data_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -7719,7 +7722,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_bcn_tx_stats_struct,  ctrl_path_pdev_bcn_tx_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_conn_stats_struct,  ctrl_path_pdev_conn_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_beacon_stats, vdev_beacon_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_congestion_stats, vdev_congestion_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
 
 /*
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 3c148d3ba5d3..33572d9c2615 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -37975,6 +37975,7 @@ typedef enum {
     WMI_REQUEST_CTRL_PATH_PDEV_CONN_STAT    = 21,
     WMI_REQUEST_CTRL_PATH_ML_RECONFIG_STAT  = 22,
     WMI_REQUEST_CTRL_PATH_STA_DAR_STAT      = 23,
+    WMI_REQUEST_ENHANCED_STAT               = 24,
 } wmi_ctrl_path_stats_id;
 
 typedef enum {
@@ -47224,6 +47225,59 @@ typedef struct {
 } wmi_cfr_capture_filter_resp_event_fixed_param;
 
 
+/* max beacon bmiss bitmask array size, in 32-bit words */
+#define WMI_MAX_BCN_BMISS_HISTORY_LENGTH 8
+
+/* max MCS counters supported for enhance stats */
+#define WMI_ENHANCE_STATS_MAX_MCS_COUNTERS 16
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_beacon_stats */
+    A_UINT32 vdev_id; /* ID of the vdev these beacon stats are from */
+    /* length:
+     * Number of A_UINT32 elements within the bmiss_bitmask array which
+     * contain valid data.
+     * Array elements beyond this limit should be ignored.
+     */
+    A_UINT32 length;
+    /* bmiss_bitmask:
+     * Beacon miss bitmask indicating which beacons got missed from up to
+     * the last 255 expected beacons (32*8 bits).
+     * Only bmiss_bitmask[0] through bmiss_bitmask[length-1] (inclusive)
+     * contain valid data.
+     */
+    A_UINT32 bmiss_bitmask[WMI_MAX_BCN_BMISS_HISTORY_LENGTH];
+} wmi_vdev_beacon_stats;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_qdata_congestion_stats */
+    A_UINT32 vdev_id; /* ID of the vdev these congestion stats are from */
+    /* cca_busy_time:
+     * Number of milliseconds during which CCA is busy,
+     * out of total time spent on the channel
+     */
+    A_UINT32 cca_busy_time;
+    /* on_time:
+     * Total time in milliseconds for which we were on the channel
+     * and monitored
+     */
+    A_UINT32 on_time;
+} wmi_vdev_congestion_stats;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_data_stats */
+    A_UINT32 vdev_id; /* ID of the vdev these data stats are from */
+    /* Set of TX MCS counters for data PPDUs */
+    A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS];
+    /* Set of TX BW counters for data PPDUs */
+    A_UINT32 tx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX];
+    /* Set of RX MCS counters for data PPDUs */
+    A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS];
+    /* Set of RX BW counters for data PPDUs */
+    A_UINT32 rx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX];
+} wmi_vdev_data_stats;
+
+
 #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff
 #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \
     ((A_UINT16) ((tlv)->chain_phase[chain_idx] & WMI_UNIFIED_CHAIN_PHASE_MASK))
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b70d34142501..2a631cbb504a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1677
+#define __WMI_REVISION_ 1678
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ff3a4c7cfc676c517bc1d544b03ee80630729774 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 21 Nov 2025 12:03:51 -0800
Subject: [PATCH 076/290] fw-api: CL 31023126 - update fw common interface
 files

Change-Id: I4e423ca0877e6de241073062579b6af312157b07
CRs-Fixed: 3830439
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 3c949416f709..41d66f06944f 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -881,6 +881,7 @@ typedef enum {
     HTT_STATS_TXBF_OFDMA_BN_STEER_TAG               = 229, /* htt_stats_txbf_ofdma_bn_steer_tlv */
     HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG          = 230, /* htt_stats_txbf_ofdma_bn_steer_mpdu_tlv */
     HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG               = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */
+    HTT_STATS_OPTIONAL_CONFIGS_TAG                  = 232, /* htt_stats_optional_configs_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index aa24e860103d..50fac11c59af 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -850,6 +850,14 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_HDS_PROF = 76,
 
+    /** HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_optional_configs_tlv
+     */
+    HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS = 77,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -11960,6 +11968,84 @@ typedef struct {
     ((word) |= (((value) << 24) & 0xff000000))
 
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    union {
+        A_UINT32 flags;
+        struct {
+             /*
+              * bit 0: Dynamic ED CCA status flag
+              * bit 1: LPI status flag
+              * bit 2: Green Tx status flag
+              * bit 3: ANI status flag
+              * bit 4: Static ANI status flag
+              * bit 5: ANN Powerboost status flag
+              * bit 6: EANI status flag
+              * bit 7: Spur Mitigation status flag
+              * bit 8: Multigain RSSI status flag
+              */
+             A_UINT32
+                 is_dyn_cca_enabled:        1, /* bit 0 */
+                 is_lpi_enabled:            1, /* bit 1 */
+                 is_gtx_enabled:            1, /* bit 2 */
+                 is_ani_enabled:            1, /* bit 3 */
+                 is_static_ani_enabled:     1, /* bit 4 */
+                 is_ann_pbt_enabled:        1, /* bit 5 */
+                 is_e_ani_enabled:          1, /* bit 6 */
+                 is_spur_mit_enabled:       1, /* bit 7 */
+                 is_multigain_rssi_enabled: 1, /* bit 8 */
+
+                 reserved: 23; /* bits 31:9 */
+        };
+    };
+} htt_stats_optional_configs_tlv;
+
+#define HTT_STATS_OPT_CONF_GET_DYN_CCA(word) \
+    (((word) & 0x1) >> 0)
+#define HTT_STATS_OPT_CONF_SET_DYN_CCA(word, value) \
+    ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0))
+
+#define HTT_STATS_OPT_CONF_GET_LPI(word) \
+    (((word) & 0x2) >> 1)
+#define HTT_STATS_OPT_CONF_SET_LPI(word, value) \
+    ((word) = ((word) & ~0x2) | (((value) & 0x1) << 1))
+
+#define HTT_STATS_OPT_CONF_GET_GTX(word) \
+    (((word) & 0x4) >> 2)
+#define HTT_STATS_OPT_CONF_SET_GTX(word, value) \
+    ((word) = ((word) & ~0x4) | (((value) & 0x1) << 2))
+
+#define HTT_STATS_OPT_CONF_GET_ANI(word) \
+    (((word) & 0x8) >> 3)
+#define HTT_STATS_OPT_CONF_SET_ANI(word, value) \
+    ((word) = ((word) & ~0x8) | (((value) & 0x1) << 3))
+
+#define HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) \
+    (((word) & 0x10) >> 4)
+#define HTT_STATS_OPT_CONF_SET_STATIC_ANI(word, value) \
+    ((word) = ((word) & ~0x10) | (((value) & 0x1) << 4))
+
+#define HTT_STATS_OPT_CONF_GET_ANN_PBT(word) \
+    (((word) & 0x20) >> 5)
+#define HTT_STATS_OPT_CONF_SET_ANN_PBT(word, value) \
+    ((word) = ((word) & ~0x20) | (((value) & 0x1) << 5))
+
+#define HTT_STATS_OPT_CONF_GET_EANI(word) \
+    (((word) & 0x40) >> 6)
+#define HTT_STATS_OPT_CONF_SET_EANI(word, value) \
+    ((word) = ((word) & ~0x40) | (((value) & 0x1) << 6))
+
+#define HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) \
+    (((word) & 0x80) >> 7)
+#define HTT_STATS_OPT_CONF_SET_SPUR_MIT(word, value) \
+    ((word) = ((word) & ~0x80) | (((value) & 0x1) << 7))
+
+#define HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) \
+    (((word) & 0x100) >> 8)
+#define HTT_STATS_OPT_CONF_SET_MULTIGAIN_RSSI(word, value) \
+    ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8))
+
+
 typedef struct {
     union {
         A_UINT32 word32;

From c855bef342d6d82769ec1b8488c83a7f8e4bcc74 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 26 Nov 2025 12:02:25 -0800
Subject: [PATCH 077/290] fw-api: CL 31059684 - update fw common interface
 files

Change-Id: Id28f987ea29f8738f8a9668ed51f1c0a27da16c7
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 33572d9c2615..710942403bce 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19926,6 +19926,12 @@ typedef enum {
      */
     WMI_VDEV_PARAM_DSMPS_CONTROL,                         /* 0xCC */
 
+    /*
+     * Support P2P GO cancel long duration one-shot NOA
+     *      0 - Disable P2P GO cancel NOA feature - default value
+     *      1 - Enable P2P GO cancel NOA feature
+     */
+    WMI_VDEV_PARAM_SET_GO_CANCEL_NOA,                     /* 0xCD */
 
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2a631cbb504a..f2da8aa2443d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1678
+#define __WMI_REVISION_ 1679
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f84197a42bedc370387cc3a46a4a018def5981e2 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 26 Nov 2025 12:04:17 -0800
Subject: [PATCH 078/290] fw-api: CL 31060090 - update fw common interface
 files

Change-Id: Iafc0e765038680e5d80ba2b2a7cf72916107d882
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 50fac11c59af..1b39949985f5 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -3557,6 +3557,9 @@ typedef struct {
      */
     A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR];
     A_UINT32 ru_alloc_mode_cnt[HTT_RU_ALLOC_NUM_MODES];
+    A_UINT32 mu_bar_pipeline_seq_cnt;
+    A_UINT32 mu_bar_pipeline_resume_cnt;
+    A_UINT32 mu_bar_pipeline_resume_fail_cnt;
 } htt_stats_tx_selfgen_cmn_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv;

From cd2d7092b382db3f0d9d77cd02cdba2d7a4008dc Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 3 Dec 2025 12:05:56 -0800
Subject: [PATCH 079/290] fw-api: CL 31100347 - update fw common interface
 files

Change-Id: I1e75e339e4904a4cd7a26850f29bd97462715a03
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  | 44 +++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 3 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 6ba4f4c06cd7..e54f8faf6483 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -745,6 +745,7 @@ typedef  enum  {
     WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */
     WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */
     WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */
+    WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 710942403bce..c5482a0564c0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -27932,7 +27932,24 @@ typedef struct {
      *     0 - need check sub channel marking
      *     1 - full bandwidth need put to NOL
      *     Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros
-     * [1:31] reserved
+     *
+     * Bits 1-7:
+     *     RADAR TYPE field (currently reserved for future use)
+     *     When implemented, this field will indicate the type of
+     *     radar detected.
+     *     The meaning of the different values of this radar type field
+     *     will be specified in the future.
+     *     Refer to WMI_RADAR_FLAGS_RADAR_TYPE_GET and _SET macros.
+     *
+     * Bits 8-15:
+     *     RADAR RSSI in dBm in the range of -128 to +127.
+     *     This 8-bit value is interpreted as a twos-complement signed number
+     *     (so for example, 0x80 = -128, 0x0 = 0, and 0x7f = 127).
+     *     This bit field is valid only if the
+     *     WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT
+     *     wmi service flag is set.
+     *
+     * [16:31] reserved
      */
     A_UINT32 flags;
 }  WMI_RADAR_FLAGS;
@@ -27940,6 +27957,12 @@ typedef struct {
 #define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS    0
 #define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS  1
 
+#define WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS     1
+#define WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS   7
+
+#define WMI_RADAR_FLAGS_RSSI_DBM_BITPOS       8
+#define WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS     8
+
 #define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \
     WMI_GET_BITS(flag, \
         WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
@@ -27949,6 +27972,25 @@ typedef struct {
         WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
         WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val)
 
+#define WMI_RADAR_FLAGS_RADAR_TYPE_GET(flag) \
+    WMI_GET_BITS(flag, \
+        WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \
+        WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS)
+#define WMI_RADAR_FLAGS_RADAR_TYPE_SET(flag, val) \
+    WMI_SET_BITS(flag, \
+        WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \
+        WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS, val)
+
+#define WMI_RADAR_FLAGS_RSSI_DBM_GET(flag) \
+    ((A_INT8)WMI_GET_BITS(flag, \
+        WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \
+        WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS))
+#define WMI_RADAR_FLAGS_RSSI_DBM_SET(flag, val) \
+    WMI_SET_BITS(flag, \
+        WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \
+        WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS, val)
+
+
 typedef enum {
     OCAC_COMPLETE = 0,
     OCAC_ABORT,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f2da8aa2443d..42c69a73769f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1679
+#define __WMI_REVISION_ 1680
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 8381f552cfc303469a2505a2128322af6c37f6bb Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 3 Dec 2025 12:07:45 -0800
Subject: [PATCH 080/290] fw-api: CL 31108122 - update fw common interface
 files

Change-Id: I574bd0d62f8936016292806144d99593697dce74
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c5482a0564c0..0f01a53b7f93 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10256,6 +10256,12 @@ typedef enum {
 
     /** Beacon antenna for smart antenna */
     WMI_PDEV_PARAM_SMART_ANTENNA_BEACON_ANTENNA,
+
+    /*
+     * The extra early rx duration (in usec units) when
+     * adaptive early rx is disabled
+     */
+    WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_EXTRA_SLEEP_SLOP,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 42c69a73769f..f7a628f81926 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1680
+#define __WMI_REVISION_ 1681
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 8ea452fa6a23e4e14b96f336a9eb0d91929ea88f Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 5 Dec 2025 12:04:12 -0800
Subject: [PATCH 081/290] fw-api: CL 31127648 - update fw common interface
 files

Change-Id: I666893fdea2a5bd4485fc78c3d68643f13148c2c
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 1b39949985f5..51c6756f8613 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1300,6 +1300,9 @@ typedef struct {
     } bytes_sent;
     /* increment array based on AC */
     A_UINT32 num_ppdu_tried_ota_per_ac[HTT_NUM_AC_WMM];
+    A_UINT32 hw_reaped_lpi;
+    A_UINT32 hw_reaped_sp;
+    A_UINT32 hw_reaped_vlp;
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;

From ae28631e9863644ac74443b99d67402fdd044774 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 5 Dec 2025 12:06:00 -0800
Subject: [PATCH 082/290] fw-api: CL 31129784 - update fw common interface
 files

Change-Id: Ie59c1a2de240fb1d2812323a3a03885c77147729
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 18 ++++++++++--------
 fw/wmi_version.h |  2 +-
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 0f01a53b7f93..3c420f4cbc15 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -17752,10 +17752,10 @@ typedef enum {
 } wmi_vdev_update_mac_addr_conf_status;
 
 /** values for vdev_type */
-#define WMI_VDEV_TYPE_AP         0x1
-#define WMI_VDEV_TYPE_STA        0x2
-#define WMI_VDEV_TYPE_IBSS       0x3
-#define WMI_VDEV_TYPE_MONITOR    0x4
+#define WMI_VDEV_TYPE_AP            0x1
+#define WMI_VDEV_TYPE_STA           0x2
+#define WMI_VDEV_TYPE_IBSS          0x3
+#define WMI_VDEV_TYPE_MONITOR       0x4
 
 /** VDEV type is for social wifi interface.This VDEV is Currently mainly needed
 * by FW to execute the NAN specific WMI commands and also implement NAN specific
@@ -17764,14 +17764,16 @@ typedef enum {
 * WMI command to create this VDEV once during initialization and host is not
 * expected to use any VDEV specific WMI commands on this VDEV.
 **/
-#define WMI_VDEV_TYPE_NAN        0x5
+#define WMI_VDEV_TYPE_NAN           0x5
 
-#define WMI_VDEV_TYPE_OCB        0x6
+#define WMI_VDEV_TYPE_OCB           0x6
 
 /* NAN Data Interface */
-#define WMI_VDEV_TYPE_NDI        0x7
+#define WMI_VDEV_TYPE_NDI           0x7
 
-#define WMI_VDEV_TYPE_MESH_POINT 0x8
+#define WMI_VDEV_TYPE_MESH_POINT    0x8
+
+#define WMI_VDEV_TYPE_WIFI_PASSTHRU 0x9
 
 /*
  * Param values to be sent for WMI_VDEV_PARAM_SGI command
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f7a628f81926..d7752da43adc 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1681
+#define __WMI_REVISION_ 1682
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 519f618893306e9dfb970fadfb010fdecb9a0dd5 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 6 Dec 2025 12:07:45 -0800
Subject: [PATCH 083/290] fw-api: CL 31139082 - update fw common interface
 files

Change-Id: I93bc84fdef8907aca1e57127b53af0f36b4f0815
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 51c6756f8613..c7614f430112 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1300,8 +1300,11 @@ typedef struct {
     } bytes_sent;
     /* increment array based on AC */
     A_UINT32 num_ppdu_tried_ota_per_ac[HTT_NUM_AC_WMM];
+    /** Number of hardware reaped (Tx completed) packets in LPI mode */
     A_UINT32 hw_reaped_lpi;
+    /** Number of hardware reaped (Tx completed) packets in SP mode */
     A_UINT32 hw_reaped_sp;
+    /** Number of hardware reaped (Tx completed) packets in VLP mode */
     A_UINT32 hw_reaped_vlp;
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
@@ -5365,6 +5368,8 @@ typedef struct {
     A_UINT32 num_subcycles_with_sort;
     /** Num of subcycles without sort for this Txq */
     A_UINT32 num_subcycles_no_sort;
+    /** num of times DPS client is scheduled */
+    A_UINT32 num_dps_client_scheduled;
 } htt_stats_tx_pdev_scheduler_txq_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv

From ba1680c57a9863e26b465db8791b1031aef25b4e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 6 Dec 2025 12:09:30 -0800
Subject: [PATCH 084/290] fw-api: CL 31139090 - update fw common interface
 files

Change-Id: Ie363e4a7da114702009c303e15795b1b58af26e0
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_unified.h  | 9 +++++++++
 fw/wmi_version.h  | 2 +-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index e54f8faf6483..e156876d0d78 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -746,6 +746,7 @@ typedef  enum  {
     WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */
     WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */
     WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */
+    WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485,  /* Indicates FW support for WOW timeline optimization feature */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 3c420f4cbc15..cbf8aca631ef 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -21057,6 +21057,15 @@ enum wmi_sta_powersave_param {
      *  Value determines the ITO level to apply
      */
     WMI_STA_PS_PARAM_ITO_LEVEL = 13,
+
+    /**
+     * TX/RX inactivity time in msec before going to sleep in wow.
+     *
+     * The power save SM will monitor tx/rx activity on the VDEV, if no
+     * activity for the specified msec of the parameter the Power save SM will
+     * go to sleep.
+     */
+    WMI_STA_PS_PARAM_INACTIVITY_TIME_WOW = 14,
 };
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d7752da43adc..9396537c897a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1682
+#define __WMI_REVISION_ 1683
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f7b7e311c4e47e93c292c5b846c450c62234d71a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 9 Dec 2025 18:01:38 -0800
Subject: [PATCH 085/290] fw-api: CL 31152020 - update fw common interface
 files

Change-Id: I6627c1350dbb2ed4434541d626c95f34e448b063
CRs-Fixed: 3830439
---
 fw/htt.h       |  2 ++
 fw/htt_stats.h | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 41d66f06944f..dd992e5a4e0f 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -882,6 +882,8 @@ typedef enum {
     HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG          = 230, /* htt_stats_txbf_ofdma_bn_steer_mpdu_tlv */
     HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG               = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */
     HTT_STATS_OPTIONAL_CONFIGS_TAG                  = 232, /* htt_stats_optional_configs_tlv */
+    HTT_STATS_PDEV_SAM_TAG                          = 233, /* htt_stats_pdev_sam_tlv */
+
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index c7614f430112..4ccf44f631ec 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -858,6 +858,14 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS = 77,
 
+    /** HTT_DBG_EXT_STATS_PDEV_SAM
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_pdev_sam_tlv
+     */
+    HTT_DBG_EXT_STATS_PDEV_SAM = 78,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -14783,4 +14791,51 @@ typedef struct {
 } htt_stats_gtx_tlv;
 /*===================== End GTX stats ====================*/
 
+
+#define HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE 16
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 pdev_id;
+    /*
+     * Number of commands posted on the FW -> SAM Command Ring. The index has
+     * an internal firmware meaning (this stat is primarily provided for
+     * internal debug), but is related to the type of command that has been
+     * posted.
+     */
+    A_UINT32 cmd_posted[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE];
+    /*
+     * Number of statuses reaped on the SAM -> FW Status Ring. The index has an
+     * internal firmware meaning (this stat is primarily provided for internal
+     * debug), but is related to the type of status that is being processed.
+     */
+    A_UINT32 status_reaped[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE];
+    /*
+     * Incremented each time a first_summary_bitmap_change_seen TLV is
+     * processed on the SAM -> FW Status ring.
+     */
+    A_UINT32 first_seen_tlv_reaped;
+    /*
+     * Number of MSDUQ Empty -> Not Empty transitions observed through SAM
+     * Queue Bitmaps.
+     */
+    A_UINT32 msduq_to_not_empty_cnt;
+    /*
+     * Number of MSDUQ Not Empty -> Empty transitions observed through SAM
+     * Queue Bitmaps.
+     */
+    A_UINT32 msduq_to_empty_cnt;
+    /*
+     * Number of MPDUQ Empty -> Not Empty transitions observed through SAM
+     * Queue Bitmaps.
+     */
+    A_UINT32 mpduq_to_not_empty_cnt;
+    /*
+     * Number of MPDUQ Not Empty -> Empty transitions observed through SAM
+     * Queue Bitmaps.
+     */
+    A_UINT32 mpduq_to_empty_cnt;
+} htt_stats_pdev_sam_tlv;
+
+
 #endif /* __HTT_STATS_H__ */

From 580d979a42903c6b5ee0daa59611db694dc5d56a Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <prakashp@qti.qualcomm.com>
Date: Mon, 3 Nov 2025 16:14:56 -0800
Subject: [PATCH 086/290] fw-api: hw_headers: Add v2 3175 hw headers for fig

Add v2 hw headers version 3175 for fig.

Change-Id: Idb357bbbf0be3a26405e073618f8c0c667b2b4ac
CRs-Fixed: 4344711
---
 hw/fig/v2/HALcomdef.h                         |   39 +
 hw/fig/v2/HALhwio.h                           |  283 ++
 hw/fig/v2/ack_report.h                        |   52 +
 hw/fig/v2/boron_top_reg.h                     |   12 +
 hw/fig/v2/buffer_addr_info.h                  |   45 +
 hw/fig/v2/ce_src_desc.h                       |  122 +
 hw/fig/v2/ce_stat_desc.h                      |  115 +
 hw/fig/v2/coex_rx_status.h                    |  131 +
 hw/fig/v2/coex_tx_req.h                       |  222 ++
 hw/fig/v2/coex_tx_status.h                    |  117 +
 hw/fig/v2/com_dtypes.h                        |  168 ++
 hw/fig/v2/eht_sig_usr_mu_mimo_info.h          |   94 +
 hw/fig/v2/eht_sig_usr_ofdma_info.h            |  108 +
 hw/fig/v2/eht_sig_usr_su_info.h               |   73 +
 hw/fig/v2/expected_response.h                 |  203 ++
 hw/fig/v2/he_sig_a_mu_dl_info.h               |  171 ++
 hw/fig/v2/he_sig_a_mu_ul_info.h               |  101 +
 hw/fig/v2/he_sig_a_su_info.h                  |  206 ++
 hw/fig/v2/he_sig_b1_mu_info.h                 |   38 +
 hw/fig/v2/he_sig_b2_mu_info.h                 |   94 +
 hw/fig/v2/he_sig_b2_ofdma_info.h              |   94 +
 hw/fig/v2/ht_sig_info.h                       |  129 +
 hw/fig/v2/l_sig_a_info.h                      |   80 +
 hw/fig/v2/l_sig_b_info.h                      |   45 +
 hw/fig/v2/macrx_abort_request_info.h          |   31 +
 hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h         |   77 +
 hw/fig/v2/mactx_eht_sig_usr_ofdma.h           |   87 +
 hw/fig/v2/mactx_eht_sig_usr_su.h              |   69 +
 hw/fig/v2/mactx_he_sig_a_mu_dl.h              |  132 +
 hw/fig/v2/mactx_he_sig_a_mu_ul.h              |   82 +
 hw/fig/v2/mactx_he_sig_a_su.h                 |  157 ++
 hw/fig/v2/mactx_he_sig_b1_mu.h                |   44 +
 hw/fig/v2/mactx_he_sig_b2_mu.h                |   77 +
 hw/fig/v2/mactx_he_sig_b2_ofdma.h             |   77 +
 hw/fig/v2/mactx_ht_sig.h                      |  102 +
 hw/fig/v2/mactx_l_sig_a.h                     |   74 +
 hw/fig/v2/mactx_l_sig_b.h                     |   49 +
 hw/fig/v2/mactx_phy_desc.h                    |  348 +++
 hw/fig/v2/mactx_u_sig_eht_su_mu.h             |  122 +
 hw/fig/v2/mactx_u_sig_eht_tb.h                |   97 +
 hw/fig/v2/mactx_user_desc_common.h            |  482 ++++
 hw/fig/v2/mactx_user_desc_per_user.h          |  285 ++
 hw/fig/v2/mactx_vht_sig_a.h                   |  112 +
 hw/fig/v2/mactx_vht_sig_b_mu160.h             |  182 ++
 hw/fig/v2/mactx_vht_sig_b_mu20.h              |   54 +
 hw/fig/v2/mactx_vht_sig_b_mu40.h              |   67 +
 hw/fig/v2/mactx_vht_sig_b_mu80.h              |  102 +
 hw/fig/v2/mactx_vht_sig_b_su160.h             |  222 ++
 hw/fig/v2/mactx_vht_sig_b_su20.h              |   54 +
 hw/fig/v2/mactx_vht_sig_b_su40.h              |   72 +
 hw/fig/v2/mactx_vht_sig_b_su80.h              |  122 +
 hw/fig/v2/mlo_sta_id_details.h                |   52 +
 hw/fig/v2/mon_buffer_addr.h                   |   75 +
 hw/fig/v2/mon_destination_ring.h              |   94 +
 hw/fig/v2/mon_drop.h                          |   61 +
 hw/fig/v2/mon_ingress_ring.h                  |   54 +
 hw/fig/v2/msmhwiobase.h                       |   12 +
 hw/fig/v2/msmhwioreg.h                        |   98 +
 hw/fig/v2/no_ack_report.h                     |  108 +
 hw/fig/v2/ofdma_trigger_details.h             |  944 +++++++
 hw/fig/v2/pcu_ppdu_setup_init.h               | 2316 +++++++++++++++
 hw/fig/v2/pdg_response.h                      |  510 ++++
 hw/fig/v2/pdg_response_rate_setting.h         |  409 +++
 hw/fig/v2/pdg_tx_req.h                        |   89 +
 hw/fig/v2/phyrx_abort_request_info.h          |   87 +
 hw/fig/v2/phyrx_common_user_info.h            |  196 ++
 hw/fig/v2/phyrx_he_sig_a_mu_dl.h              |  132 +
 hw/fig/v2/phyrx_he_sig_a_mu_ul.h              |   82 +
 hw/fig/v2/phyrx_he_sig_a_su.h                 |  157 ++
 hw/fig/v2/phyrx_he_sig_b1_mu.h                |   44 +
 hw/fig/v2/phyrx_he_sig_b2_mu.h                |   77 +
 hw/fig/v2/phyrx_he_sig_b2_ofdma.h             |   77 +
 hw/fig/v2/phyrx_ht_sig.h                      |  102 +
 hw/fig/v2/phyrx_l_sig_a.h                     |   74 +
 hw/fig/v2/phyrx_l_sig_b.h                     |   49 +
 hw/fig/v2/phyrx_location.h                    |  332 +++
 .../v2/phyrx_other_receive_info_ru_details.h  |   47 +
 hw/fig/v2/phyrx_pkt_end.h                     |  427 +++
 hw/fig/v2/phyrx_pkt_end_info.h                |  450 +++
 hw/fig/v2/phyrx_rssi_legacy.h                 |  806 ++++++
 hw/fig/v2/phyrx_user_info.h                   |  207 ++
 hw/fig/v2/phyrx_vht_sig_a.h                   |  112 +
 hw/fig/v2/phytx_abort_request_info.h          |   38 +
 hw/fig/v2/phytx_pkt_end.h                     |  243 ++
 hw/fig/v2/phytx_ppdu_header_info_request.h    |   40 +
 hw/fig/v2/receive_pkt_start_info.h            |   87 +
 hw/fig/v2/receive_rssi_info.h                 |  465 +++
 hw/fig/v2/receive_user_info.h                 |  278 ++
 hw/fig/v2/received_response_user_15_8.h       | 1116 ++++++++
 hw/fig/v2/received_response_user_23_16.h      | 1116 ++++++++
 hw/fig/v2/received_response_user_31_24.h      | 1116 ++++++++
 hw/fig/v2/received_response_user_36_32.h      |  705 +++++
 hw/fig/v2/received_response_user_7_0.h        | 1116 ++++++++
 hw/fig/v2/received_response_user_info.h       |  206 ++
 hw/fig/v2/received_trigger_info.h             |  142 +
 hw/fig/v2/received_trigger_info_details.h     |  193 ++
 hw/fig/v2/reo_destination_ring.h              |  305 ++
 hw/fig/v2/reo_destination_ring_with_pn.h      |  277 ++
 hw/fig/v2/reo_entrance_ring.h                 |  321 +++
 hw/fig/v2/response_end_status.h               |  277 ++
 hw/fig/v2/response_start_status.h             |  112 +
 hw/fig/v2/ru_allocation_160_info.h            |  115 +
 hw/fig/v2/rx_attention.h                      |  376 +++
 hw/fig/v2/rx_flow_search_entry.h              |  213 ++
 hw/fig/v2/rx_frame_1k_bitmap_ack.h            |  362 +++
 hw/fig/v2/rx_frame_bitmap_ack.h               |  236 ++
 hw/fig/v2/rx_frame_bitmap_req.h               |   75 +
 hw/fig/v2/rx_location_info.h                  |  453 +++
 hw/fig/v2/rx_mpdu_desc_info.h                 |  101 +
 hw/fig/v2/rx_mpdu_details.h                   |  131 +
 hw/fig/v2/rx_mpdu_end.h                       |  196 ++
 hw/fig/v2/rx_mpdu_ext_desc_info.h             |   52 +
 hw/fig/v2/rx_mpdu_info.h                      |  972 +++++++
 hw/fig/v2/rx_mpdu_link_ptr.h                  |   40 +
 hw/fig/v2/rx_mpdu_start.h                     |  712 +++++
 hw/fig/v2/rx_msdu_desc_info.h                 |  131 +
 hw/fig/v2/rx_msdu_details.h                   |  161 ++
 hw/fig/v2/rx_msdu_end.h                       | 1094 ++++++++
 hw/fig/v2/rx_msdu_ext_desc_info.h             |   59 +
 hw/fig/v2/rx_msdu_link.h                      | 2051 ++++++++++++++
 hw/fig/v2/rx_msdu_start.h                     |  306 ++
 hw/fig/v2/rx_ppdu_ack_report.h                |   54 +
 hw/fig/v2/rx_ppdu_end_user_stats.h            |  679 +++++
 hw/fig/v2/rx_ppdu_end_user_stats_ext.h        |  133 +
 hw/fig/v2/rx_ppdu_no_ack_report.h             |   87 +
 hw/fig/v2/rx_ppdu_start.h                     |   75 +
 hw/fig/v2/rx_ppdu_start_user_info.h           |  207 ++
 hw/fig/v2/rx_preamble.h                       |   54 +
 hw/fig/v2/rx_response_required_info.h         |  764 +++++
 hw/fig/v2/rx_rxpcu_classification_overview.h  |   94 +
 hw/fig/v2/rx_start_param.h                    |   47 +
 hw/fig/v2/rx_timing_info.h                    |   66 +
 hw/fig/v2/rx_trig_info.h                      |   54 +
 hw/fig/v2/rxpcu_early_rx_indication.h         |   61 +
 hw/fig/v2/rxpcu_ppdu_end_info.h               |  925 ++++++
 hw/fig/v2/rxpcu_ppdu_end_layout_info.h        |  320 +++
 hw/fig/v2/rxpt_classify_info.h                |  122 +
 hw/fig/v2/seq_hwio.h                          |   41 +
 hw/fig/v2/tcl_assist_cmd.h                    |  411 +++
 hw/fig/v2/tcl_status_ring.h                   |  129 +
 hw/fig/v2/tlv_hdr.h                           |  634 +++++
 hw/fig/v2/tlv_tag_def.h                       | 1948 +++++++++++++
 hw/fig/v2/tqm2sw_completion_ring.h            |  262 ++
 hw/fig/v2/tx_cbf_info.h                       |  454 +++
 hw/fig/v2/tx_fes_setup.h                      |  585 ++++
 hw/fig/v2/tx_fes_status_1k_ba.h               |  313 +++
 hw/fig/v2/tx_fes_status_ack_or_ba.h           |  145 +
 hw/fig/v2/tx_fes_status_end.h                 |  602 ++++
 hw/fig/v2/tx_fes_status_prot.h                |  156 ++
 hw/fig/v2/tx_fes_status_start.h               |  117 +
 hw/fig/v2/tx_fes_status_start_ppdu.h          |  271 ++
 hw/fig/v2/tx_fes_status_start_prot.h          |  264 ++
 hw/fig/v2/tx_fes_status_user_ppdu.h           |  180 ++
 hw/fig/v2/tx_fes_status_user_response.h       |   79 +
 hw/fig/v2/tx_flush_req.h                      |   61 +
 hw/fig/v2/tx_mpdu_start.h                     |  299 ++
 hw/fig/v2/tx_msdu_extension.h                 |  318 +++
 hw/fig/v2/tx_msdu_start.h                     |  250 ++
 hw/fig/v2/tx_peer_entry.h                     |  391 +++
 hw/fig/v2/tx_queue_extension.h                |  432 +++
 hw/fig/v2/tx_rate_stats_info.h                |  108 +
 hw/fig/v2/tx_raw_or_native_frame_setup.h      |  285 ++
 hw/fig/v2/txpcu_buffer_basics.h               |   38 +
 hw/fig/v2/txpcu_buffer_status.h               |   58 +
 hw/fig/v2/txpcu_user_buffer_status.h          |   65 +
 hw/fig/v2/u_sig_eht_su_mu_info.h              |  157 ++
 hw/fig/v2/u_sig_eht_tb_info.h                 |  122 +
 hw/fig/v2/unallocated_ru_160_info.h           |   45 +
 hw/fig/v2/uniform_descriptor_header.h         |   45 +
 hw/fig/v2/vht_sig_a_info.h                    |  143 +
 hw/fig/v2/vht_sig_b_mu160_info.h              |  241 ++
 hw/fig/v2/vht_sig_b_mu20_info.h               |   52 +
 hw/fig/v2/vht_sig_b_mu40_info.h               |   80 +
 hw/fig/v2/vht_sig_b_mu80_info.h               |  129 +
 hw/fig/v2/vht_sig_b_su160_info.h              |  297 ++
 hw/fig/v2/vht_sig_b_su20_info.h               |   52 +
 hw/fig/v2/vht_sig_b_su40_info.h               |   87 +
 hw/fig/v2/vht_sig_b_su80_info.h               |  157 ++
 hw/fig/v2/wbm2sw_completion_ring_rx.h         |  289 ++
 hw/fig/v2/wbm_buffer_ring.h                   |   40 +
 hw/fig/v2/wbm_link_descriptor_ring.h          |   40 +
 hw/fig/v2/wbm_release_ring.h                  |  117 +
 hw/fig/v2/wbm_release_ring_rx.h               |   75 +
 hw/fig/v2/wbm_release_ring_tx.h               |   68 +
 hw/fig/v2/wcss_seq_hwiobase.h                 |  105 +
 hw/fig/v2/wcss_seq_hwioreg_umac.h             | 2481 +++++++++++++++++
 hw/fig/v2/wcss_version.h                      |    6 +
 187 files changed, 47856 insertions(+)
 create mode 100644 hw/fig/v2/HALcomdef.h
 create mode 100644 hw/fig/v2/HALhwio.h
 create mode 100644 hw/fig/v2/ack_report.h
 create mode 100644 hw/fig/v2/boron_top_reg.h
 create mode 100644 hw/fig/v2/buffer_addr_info.h
 create mode 100644 hw/fig/v2/ce_src_desc.h
 create mode 100644 hw/fig/v2/ce_stat_desc.h
 create mode 100644 hw/fig/v2/coex_rx_status.h
 create mode 100644 hw/fig/v2/coex_tx_req.h
 create mode 100644 hw/fig/v2/coex_tx_status.h
 create mode 100644 hw/fig/v2/com_dtypes.h
 create mode 100644 hw/fig/v2/eht_sig_usr_mu_mimo_info.h
 create mode 100644 hw/fig/v2/eht_sig_usr_ofdma_info.h
 create mode 100644 hw/fig/v2/eht_sig_usr_su_info.h
 create mode 100644 hw/fig/v2/expected_response.h
 create mode 100644 hw/fig/v2/he_sig_a_mu_dl_info.h
 create mode 100644 hw/fig/v2/he_sig_a_mu_ul_info.h
 create mode 100644 hw/fig/v2/he_sig_a_su_info.h
 create mode 100644 hw/fig/v2/he_sig_b1_mu_info.h
 create mode 100644 hw/fig/v2/he_sig_b2_mu_info.h
 create mode 100644 hw/fig/v2/he_sig_b2_ofdma_info.h
 create mode 100644 hw/fig/v2/ht_sig_info.h
 create mode 100644 hw/fig/v2/l_sig_a_info.h
 create mode 100644 hw/fig/v2/l_sig_b_info.h
 create mode 100644 hw/fig/v2/macrx_abort_request_info.h
 create mode 100644 hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
 create mode 100644 hw/fig/v2/mactx_eht_sig_usr_ofdma.h
 create mode 100644 hw/fig/v2/mactx_eht_sig_usr_su.h
 create mode 100644 hw/fig/v2/mactx_he_sig_a_mu_dl.h
 create mode 100644 hw/fig/v2/mactx_he_sig_a_mu_ul.h
 create mode 100644 hw/fig/v2/mactx_he_sig_a_su.h
 create mode 100644 hw/fig/v2/mactx_he_sig_b1_mu.h
 create mode 100644 hw/fig/v2/mactx_he_sig_b2_mu.h
 create mode 100644 hw/fig/v2/mactx_he_sig_b2_ofdma.h
 create mode 100644 hw/fig/v2/mactx_ht_sig.h
 create mode 100644 hw/fig/v2/mactx_l_sig_a.h
 create mode 100644 hw/fig/v2/mactx_l_sig_b.h
 create mode 100644 hw/fig/v2/mactx_phy_desc.h
 create mode 100644 hw/fig/v2/mactx_u_sig_eht_su_mu.h
 create mode 100644 hw/fig/v2/mactx_u_sig_eht_tb.h
 create mode 100644 hw/fig/v2/mactx_user_desc_common.h
 create mode 100644 hw/fig/v2/mactx_user_desc_per_user.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_a.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_mu160.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_mu20.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_mu40.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_mu80.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_su160.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_su20.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_su40.h
 create mode 100644 hw/fig/v2/mactx_vht_sig_b_su80.h
 create mode 100644 hw/fig/v2/mlo_sta_id_details.h
 create mode 100644 hw/fig/v2/mon_buffer_addr.h
 create mode 100644 hw/fig/v2/mon_destination_ring.h
 create mode 100644 hw/fig/v2/mon_drop.h
 create mode 100644 hw/fig/v2/mon_ingress_ring.h
 create mode 100644 hw/fig/v2/msmhwiobase.h
 create mode 100644 hw/fig/v2/msmhwioreg.h
 create mode 100644 hw/fig/v2/no_ack_report.h
 create mode 100644 hw/fig/v2/ofdma_trigger_details.h
 create mode 100644 hw/fig/v2/pcu_ppdu_setup_init.h
 create mode 100644 hw/fig/v2/pdg_response.h
 create mode 100644 hw/fig/v2/pdg_response_rate_setting.h
 create mode 100644 hw/fig/v2/pdg_tx_req.h
 create mode 100644 hw/fig/v2/phyrx_abort_request_info.h
 create mode 100644 hw/fig/v2/phyrx_common_user_info.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_a_mu_dl.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_a_mu_ul.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_a_su.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_b1_mu.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_b2_mu.h
 create mode 100644 hw/fig/v2/phyrx_he_sig_b2_ofdma.h
 create mode 100644 hw/fig/v2/phyrx_ht_sig.h
 create mode 100644 hw/fig/v2/phyrx_l_sig_a.h
 create mode 100644 hw/fig/v2/phyrx_l_sig_b.h
 create mode 100644 hw/fig/v2/phyrx_location.h
 create mode 100644 hw/fig/v2/phyrx_other_receive_info_ru_details.h
 create mode 100644 hw/fig/v2/phyrx_pkt_end.h
 create mode 100644 hw/fig/v2/phyrx_pkt_end_info.h
 create mode 100644 hw/fig/v2/phyrx_rssi_legacy.h
 create mode 100644 hw/fig/v2/phyrx_user_info.h
 create mode 100644 hw/fig/v2/phyrx_vht_sig_a.h
 create mode 100644 hw/fig/v2/phytx_abort_request_info.h
 create mode 100644 hw/fig/v2/phytx_pkt_end.h
 create mode 100644 hw/fig/v2/phytx_ppdu_header_info_request.h
 create mode 100644 hw/fig/v2/receive_pkt_start_info.h
 create mode 100644 hw/fig/v2/receive_rssi_info.h
 create mode 100644 hw/fig/v2/receive_user_info.h
 create mode 100644 hw/fig/v2/received_response_user_15_8.h
 create mode 100644 hw/fig/v2/received_response_user_23_16.h
 create mode 100644 hw/fig/v2/received_response_user_31_24.h
 create mode 100644 hw/fig/v2/received_response_user_36_32.h
 create mode 100644 hw/fig/v2/received_response_user_7_0.h
 create mode 100644 hw/fig/v2/received_response_user_info.h
 create mode 100644 hw/fig/v2/received_trigger_info.h
 create mode 100644 hw/fig/v2/received_trigger_info_details.h
 create mode 100644 hw/fig/v2/reo_destination_ring.h
 create mode 100644 hw/fig/v2/reo_destination_ring_with_pn.h
 create mode 100644 hw/fig/v2/reo_entrance_ring.h
 create mode 100644 hw/fig/v2/response_end_status.h
 create mode 100644 hw/fig/v2/response_start_status.h
 create mode 100644 hw/fig/v2/ru_allocation_160_info.h
 create mode 100644 hw/fig/v2/rx_attention.h
 create mode 100644 hw/fig/v2/rx_flow_search_entry.h
 create mode 100644 hw/fig/v2/rx_frame_1k_bitmap_ack.h
 create mode 100644 hw/fig/v2/rx_frame_bitmap_ack.h
 create mode 100644 hw/fig/v2/rx_frame_bitmap_req.h
 create mode 100644 hw/fig/v2/rx_location_info.h
 create mode 100644 hw/fig/v2/rx_mpdu_desc_info.h
 create mode 100644 hw/fig/v2/rx_mpdu_details.h
 create mode 100644 hw/fig/v2/rx_mpdu_end.h
 create mode 100644 hw/fig/v2/rx_mpdu_ext_desc_info.h
 create mode 100644 hw/fig/v2/rx_mpdu_info.h
 create mode 100644 hw/fig/v2/rx_mpdu_link_ptr.h
 create mode 100644 hw/fig/v2/rx_mpdu_start.h
 create mode 100644 hw/fig/v2/rx_msdu_desc_info.h
 create mode 100644 hw/fig/v2/rx_msdu_details.h
 create mode 100644 hw/fig/v2/rx_msdu_end.h
 create mode 100644 hw/fig/v2/rx_msdu_ext_desc_info.h
 create mode 100644 hw/fig/v2/rx_msdu_link.h
 create mode 100644 hw/fig/v2/rx_msdu_start.h
 create mode 100644 hw/fig/v2/rx_ppdu_ack_report.h
 create mode 100644 hw/fig/v2/rx_ppdu_end_user_stats.h
 create mode 100644 hw/fig/v2/rx_ppdu_end_user_stats_ext.h
 create mode 100644 hw/fig/v2/rx_ppdu_no_ack_report.h
 create mode 100644 hw/fig/v2/rx_ppdu_start.h
 create mode 100644 hw/fig/v2/rx_ppdu_start_user_info.h
 create mode 100644 hw/fig/v2/rx_preamble.h
 create mode 100644 hw/fig/v2/rx_response_required_info.h
 create mode 100644 hw/fig/v2/rx_rxpcu_classification_overview.h
 create mode 100644 hw/fig/v2/rx_start_param.h
 create mode 100644 hw/fig/v2/rx_timing_info.h
 create mode 100644 hw/fig/v2/rx_trig_info.h
 create mode 100644 hw/fig/v2/rxpcu_early_rx_indication.h
 create mode 100644 hw/fig/v2/rxpcu_ppdu_end_info.h
 create mode 100644 hw/fig/v2/rxpcu_ppdu_end_layout_info.h
 create mode 100644 hw/fig/v2/rxpt_classify_info.h
 create mode 100644 hw/fig/v2/seq_hwio.h
 create mode 100644 hw/fig/v2/tcl_assist_cmd.h
 create mode 100644 hw/fig/v2/tcl_status_ring.h
 create mode 100644 hw/fig/v2/tlv_hdr.h
 create mode 100644 hw/fig/v2/tlv_tag_def.h
 create mode 100644 hw/fig/v2/tqm2sw_completion_ring.h
 create mode 100644 hw/fig/v2/tx_cbf_info.h
 create mode 100644 hw/fig/v2/tx_fes_setup.h
 create mode 100644 hw/fig/v2/tx_fes_status_1k_ba.h
 create mode 100644 hw/fig/v2/tx_fes_status_ack_or_ba.h
 create mode 100644 hw/fig/v2/tx_fes_status_end.h
 create mode 100644 hw/fig/v2/tx_fes_status_prot.h
 create mode 100644 hw/fig/v2/tx_fes_status_start.h
 create mode 100644 hw/fig/v2/tx_fes_status_start_ppdu.h
 create mode 100644 hw/fig/v2/tx_fes_status_start_prot.h
 create mode 100644 hw/fig/v2/tx_fes_status_user_ppdu.h
 create mode 100644 hw/fig/v2/tx_fes_status_user_response.h
 create mode 100644 hw/fig/v2/tx_flush_req.h
 create mode 100644 hw/fig/v2/tx_mpdu_start.h
 create mode 100644 hw/fig/v2/tx_msdu_extension.h
 create mode 100644 hw/fig/v2/tx_msdu_start.h
 create mode 100644 hw/fig/v2/tx_peer_entry.h
 create mode 100644 hw/fig/v2/tx_queue_extension.h
 create mode 100644 hw/fig/v2/tx_rate_stats_info.h
 create mode 100644 hw/fig/v2/tx_raw_or_native_frame_setup.h
 create mode 100644 hw/fig/v2/txpcu_buffer_basics.h
 create mode 100644 hw/fig/v2/txpcu_buffer_status.h
 create mode 100644 hw/fig/v2/txpcu_user_buffer_status.h
 create mode 100644 hw/fig/v2/u_sig_eht_su_mu_info.h
 create mode 100644 hw/fig/v2/u_sig_eht_tb_info.h
 create mode 100644 hw/fig/v2/unallocated_ru_160_info.h
 create mode 100644 hw/fig/v2/uniform_descriptor_header.h
 create mode 100644 hw/fig/v2/vht_sig_a_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_mu160_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_mu20_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_mu40_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_mu80_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_su160_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_su20_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_su40_info.h
 create mode 100644 hw/fig/v2/vht_sig_b_su80_info.h
 create mode 100644 hw/fig/v2/wbm2sw_completion_ring_rx.h
 create mode 100644 hw/fig/v2/wbm_buffer_ring.h
 create mode 100644 hw/fig/v2/wbm_link_descriptor_ring.h
 create mode 100644 hw/fig/v2/wbm_release_ring.h
 create mode 100644 hw/fig/v2/wbm_release_ring_rx.h
 create mode 100644 hw/fig/v2/wbm_release_ring_tx.h
 create mode 100644 hw/fig/v2/wcss_seq_hwiobase.h
 create mode 100644 hw/fig/v2/wcss_seq_hwioreg_umac.h
 create mode 100644 hw/fig/v2/wcss_version.h

diff --git a/hw/fig/v2/HALcomdef.h b/hw/fig/v2/HALcomdef.h
new file mode 100644
index 000000000000..60ee92e6cd2e
--- /dev/null
+++ b/hw/fig/v2/HALcomdef.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/hw/fig/v2/HALhwio.h b/hw/fig/v2/HALhwio.h
new file mode 100644
index 000000000000..94dd4185e173
--- /dev/null
+++ b/hw/fig/v2/HALhwio.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  {	\
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                               }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                               }
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+                                                                               }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask))
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/hw/fig/v2/ack_report.h b/hw/fig/v2/ack_report.h
new file mode 100644
index 000000000000..e78921b308fd
--- /dev/null
+++ b/hw/fig/v2/ack_report.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t selfgen_response_reason                                 :  4,
+                      ax_trigger_type                                         :  4,
+                      sr_ppdu                                                 :  1,
+                      reserved                                                :  7,
+                      frame_control                                           : 16;
+#else
+             uint32_t frame_control                                           : 16,
+                      reserved                                                :  7,
+                      sr_ppdu                                                 :  1,
+                      ax_trigger_type                                         :  4,
+                      selfgen_response_reason                                 :  4;
+#endif
+};
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0
+
+#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
+#define ACK_REPORT_SR_PPDU_LSB                                                      8
+#define ACK_REPORT_SR_PPDU_MSB                                                      8
+#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100
+
+#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
+#define ACK_REPORT_RESERVED_LSB                                                     9
+#define ACK_REPORT_RESERVED_MSB                                                     15
+#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
+#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
+#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/fig/v2/boron_top_reg.h b/hw/fig/v2/boron_top_reg.h
new file mode 100644
index 000000000000..306398284fe3
--- /dev/null
+++ b/hw/fig/v2/boron_top_reg.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef BORON_TOP_REG_H
+#define BORON_TOP_REG_H
+
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
+
+#endif
diff --git a/hw/fig/v2/buffer_addr_info.h b/hw/fig/v2/buffer_addr_info.h
new file mode 100644
index 000000000000..d65375b54715
--- /dev/null
+++ b/hw/fig/v2/buffer_addr_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t buffer_addr_39_32                                       :  8,
+                      return_buffer_manager                                   :  4,
+                      sw_buffer_cookie                                        : 20;
+#else
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      return_buffer_manager                                   :  4,
+                      buffer_addr_39_32                                       :  8;
+#endif
+};
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                                    0x00000000
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB                                       0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB                                       31
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK                                      0xffffffff
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                                   0x00000004
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB                                      0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB                                      7
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK                                     0x000000ff
+
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                               0x00000004
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                                  8
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                                  11
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                                 0x00000f00
+
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                                    0x00000004
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB                                       12
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB                                       31
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK                                      0xfffff000
+
+#endif
diff --git a/hw/fig/v2/ce_src_desc.h b/hw/fig/v2/ce_src_desc.h
new file mode 100644
index 000000000000..4ecaedcab2a7
--- /dev/null
+++ b/hw/fig/v2/ce_src_desc.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t src_buffer_high                                         :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      ce_res_0                                                :  1,
+                      barrier_read                                            :  1,
+                      ce_res_1                                                :  2,
+                      length                                                  : 16;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_2                                                : 16;
+             uint32_t ce_res_3                                                : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t length                                                  : 16,
+                      ce_res_1                                                :  2,
+                      barrier_read                                            :  1,
+                      ce_res_0                                                :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      src_buffer_high                                         :  8;
+             uint32_t ce_res_2                                                : 16,
+                      fw_metadata                                             : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_3                                                : 20;
+#endif
+};
+
+#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET                                           0x00000000
+#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB                                              0
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB                                              31
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK                                             0xffffffff
+
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET                                          0x00000004
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB                                             0
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB                                             7
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK                                            0x000000ff
+
+#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET                                              0x00000004
+#define CE_SRC_DESC_TOEPLITZ_EN_LSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MASK                                                0x00000100
+
+#define CE_SRC_DESC_SRC_SWAP_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_SRC_SWAP_LSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MASK                                                   0x00000200
+
+#define CE_SRC_DESC_DEST_SWAP_OFFSET                                                0x00000004
+#define CE_SRC_DESC_DEST_SWAP_LSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MASK                                                  0x00000400
+
+#define CE_SRC_DESC_GATHER_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_GATHER_LSB                                                      11
+#define CE_SRC_DESC_GATHER_MSB                                                      11
+#define CE_SRC_DESC_GATHER_MASK                                                     0x00000800
+
+#define CE_SRC_DESC_CE_RES_0_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_0_LSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MASK                                                   0x00001000
+
+#define CE_SRC_DESC_BARRIER_READ_OFFSET                                             0x00000004
+#define CE_SRC_DESC_BARRIER_READ_LSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MASK                                               0x00002000
+
+#define CE_SRC_DESC_CE_RES_1_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_1_LSB                                                    14
+#define CE_SRC_DESC_CE_RES_1_MSB                                                    15
+#define CE_SRC_DESC_CE_RES_1_MASK                                                   0x0000c000
+
+#define CE_SRC_DESC_LENGTH_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_LENGTH_LSB                                                      16
+#define CE_SRC_DESC_LENGTH_MSB                                                      31
+#define CE_SRC_DESC_LENGTH_MASK                                                     0xffff0000
+
+#define CE_SRC_DESC_FW_METADATA_OFFSET                                              0x00000008
+#define CE_SRC_DESC_FW_METADATA_LSB                                                 0
+#define CE_SRC_DESC_FW_METADATA_MSB                                                 15
+#define CE_SRC_DESC_FW_METADATA_MASK                                                0x0000ffff
+
+#define CE_SRC_DESC_CE_RES_2_OFFSET                                                 0x00000008
+#define CE_SRC_DESC_CE_RES_2_LSB                                                    16
+#define CE_SRC_DESC_CE_RES_2_MSB                                                    31
+#define CE_SRC_DESC_CE_RES_2_MASK                                                   0xffff0000
+
+#define CE_SRC_DESC_CE_RES_3_OFFSET                                                 0x0000000c
+#define CE_SRC_DESC_CE_RES_3_LSB                                                    0
+#define CE_SRC_DESC_CE_RES_3_MSB                                                    19
+#define CE_SRC_DESC_CE_RES_3_MASK                                                   0x000fffff
+
+#define CE_SRC_DESC_RING_ID_OFFSET                                                  0x0000000c
+#define CE_SRC_DESC_RING_ID_LSB                                                     20
+#define CE_SRC_DESC_RING_ID_MSB                                                     27
+#define CE_SRC_DESC_RING_ID_MASK                                                    0x0ff00000
+
+#define CE_SRC_DESC_LOOPING_COUNT_OFFSET                                            0x0000000c
+#define CE_SRC_DESC_LOOPING_COUNT_LSB                                               28
+#define CE_SRC_DESC_LOOPING_COUNT_MSB                                               31
+#define CE_SRC_DESC_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/fig/v2/ce_stat_desc.h b/hw/fig/v2/ce_stat_desc.h
new file mode 100644
index 000000000000..0b9f9a221215
--- /dev/null
+++ b/hw/fig/v2/ce_stat_desc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ce_res_5                                                :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      barrier_read                                            :  1,
+                      ce_res_6                                                :  3,
+                      length                                                  : 16;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_7                                                :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t length                                                  : 16,
+                      ce_res_6                                                :  3,
+                      barrier_read                                            :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      ce_res_5                                                :  8;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_7                                                :  4,
+                      fw_metadata                                             : 16;
+#endif
+};
+
+#define CE_STAT_DESC_CE_RES_5_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_5_LSB                                                   0
+#define CE_STAT_DESC_CE_RES_5_MSB                                                   7
+#define CE_STAT_DESC_CE_RES_5_MASK                                                  0x000000ff
+
+#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET                                             0x00000000
+#define CE_STAT_DESC_TOEPLITZ_EN_LSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MASK                                               0x00000100
+
+#define CE_STAT_DESC_SRC_SWAP_OFFSET                                                0x00000000
+#define CE_STAT_DESC_SRC_SWAP_LSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MASK                                                  0x00000200
+
+#define CE_STAT_DESC_DEST_SWAP_OFFSET                                               0x00000000
+#define CE_STAT_DESC_DEST_SWAP_LSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MASK                                                 0x00000400
+
+#define CE_STAT_DESC_GATHER_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_GATHER_LSB                                                     11
+#define CE_STAT_DESC_GATHER_MSB                                                     11
+#define CE_STAT_DESC_GATHER_MASK                                                    0x00000800
+
+#define CE_STAT_DESC_BARRIER_READ_OFFSET                                            0x00000000
+#define CE_STAT_DESC_BARRIER_READ_LSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MASK                                              0x00001000
+
+#define CE_STAT_DESC_CE_RES_6_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_6_LSB                                                   13
+#define CE_STAT_DESC_CE_RES_6_MSB                                                   15
+#define CE_STAT_DESC_CE_RES_6_MASK                                                  0x0000e000
+
+#define CE_STAT_DESC_LENGTH_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_LENGTH_LSB                                                     16
+#define CE_STAT_DESC_LENGTH_MSB                                                     31
+#define CE_STAT_DESC_LENGTH_MASK                                                    0xffff0000
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET                                         0x00000004
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET                                         0x00000008
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_FW_METADATA_OFFSET                                             0x0000000c
+#define CE_STAT_DESC_FW_METADATA_LSB                                                0
+#define CE_STAT_DESC_FW_METADATA_MSB                                                15
+#define CE_STAT_DESC_FW_METADATA_MASK                                               0x0000ffff
+
+#define CE_STAT_DESC_CE_RES_7_OFFSET                                                0x0000000c
+#define CE_STAT_DESC_CE_RES_7_LSB                                                   16
+#define CE_STAT_DESC_CE_RES_7_MSB                                                   19
+#define CE_STAT_DESC_CE_RES_7_MASK                                                  0x000f0000
+
+#define CE_STAT_DESC_RING_ID_OFFSET                                                 0x0000000c
+#define CE_STAT_DESC_RING_ID_LSB                                                    20
+#define CE_STAT_DESC_RING_ID_MSB                                                    27
+#define CE_STAT_DESC_RING_ID_MASK                                                   0x0ff00000
+
+#define CE_STAT_DESC_LOOPING_COUNT_OFFSET                                           0x0000000c
+#define CE_STAT_DESC_LOOPING_COUNT_LSB                                              28
+#define CE_STAT_DESC_LOOPING_COUNT_MSB                                              31
+#define CE_STAT_DESC_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/fig/v2/coex_rx_status.h b/hw/fig/v2/coex_rx_status.h
new file mode 100644
index 000000000000..7d9c6b4d2057
--- /dev/null
+++ b/hw/fig/v2/coex_rx_status.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_RX_STATUS_H_
+#define _COEX_RX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_RX_STATUS 2
+
+#define NUM_OF_QWORDS_COEX_RX_STATUS 1
+
+struct coex_rx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_mac_frame_status                                     :  2,
+                      rx_with_tx_response                                     :  1,
+                      rx_rate                                                 :  5,
+                      rx_bw                                                   :  3,
+                      single_mpdu                                             :  1,
+                      filter_status                                           :  1,
+                      ampdu                                                   :  1,
+                      directed                                                :  1,
+                      reserved_0                                              :  1,
+                      rx_nss                                                  :  3,
+                      rx_rssi                                                 :  8,
+                      rx_type                                                 :  3,
+                      retry_bit_setting                                       :  1,
+                      more_data_bit_setting                                   :  1;
+             uint32_t remain_rx_packet_time                                   : 16,
+                      rx_remaining_fes_time                                   : 16;
+#else
+             uint32_t more_data_bit_setting                                   :  1,
+                      retry_bit_setting                                       :  1,
+                      rx_type                                                 :  3,
+                      rx_rssi                                                 :  8,
+                      rx_nss                                                  :  3,
+                      reserved_0                                              :  1,
+                      directed                                                :  1,
+                      ampdu                                                   :  1,
+                      filter_status                                           :  1,
+                      single_mpdu                                             :  1,
+                      rx_bw                                                   :  3,
+                      rx_rate                                                 :  5,
+                      rx_with_tx_response                                     :  1,
+                      rx_mac_frame_status                                     :  2;
+             uint32_t rx_remaining_fes_time                                   : 16,
+                      remain_rx_packet_time                                   : 16;
+#endif
+};
+
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB                                      0
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB                                      1
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK                                     0x0000000000000003
+
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK                                     0x0000000000000004
+
+#define COEX_RX_STATUS_RX_RATE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RATE_LSB                                                  3
+#define COEX_RX_STATUS_RX_RATE_MSB                                                  7
+#define COEX_RX_STATUS_RX_RATE_MASK                                                 0x00000000000000f8
+
+#define COEX_RX_STATUS_RX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_BW_LSB                                                    8
+#define COEX_RX_STATUS_RX_BW_MSB                                                    10
+#define COEX_RX_STATUS_RX_BW_MASK                                                   0x0000000000000700
+
+#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET                                           0x0000000000000000
+#define COEX_RX_STATUS_SINGLE_MPDU_LSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MASK                                             0x0000000000000800
+
+#define COEX_RX_STATUS_FILTER_STATUS_OFFSET                                         0x0000000000000000
+#define COEX_RX_STATUS_FILTER_STATUS_LSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MASK                                           0x0000000000001000
+
+#define COEX_RX_STATUS_AMPDU_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_AMPDU_LSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MASK                                                   0x0000000000002000
+
+#define COEX_RX_STATUS_DIRECTED_OFFSET                                              0x0000000000000000
+#define COEX_RX_STATUS_DIRECTED_LSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MASK                                                0x0000000000004000
+
+#define COEX_RX_STATUS_RESERVED_0_OFFSET                                            0x0000000000000000
+#define COEX_RX_STATUS_RESERVED_0_LSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MASK                                              0x0000000000008000
+
+#define COEX_RX_STATUS_RX_NSS_OFFSET                                                0x0000000000000000
+#define COEX_RX_STATUS_RX_NSS_LSB                                                   16
+#define COEX_RX_STATUS_RX_NSS_MSB                                                   18
+#define COEX_RX_STATUS_RX_NSS_MASK                                                  0x0000000000070000
+
+#define COEX_RX_STATUS_RX_RSSI_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RSSI_LSB                                                  19
+#define COEX_RX_STATUS_RX_RSSI_MSB                                                  26
+#define COEX_RX_STATUS_RX_RSSI_MASK                                                 0x0000000007f80000
+
+#define COEX_RX_STATUS_RX_TYPE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_TYPE_LSB                                                  27
+#define COEX_RX_STATUS_RX_TYPE_MSB                                                  29
+#define COEX_RX_STATUS_RX_TYPE_MASK                                                 0x0000000038000000
+
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET                                     0x0000000000000000
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK                                       0x0000000040000000
+
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK                                   0x0000000080000000
+
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB                                    32
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB                                    47
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK                                   0x0000ffff00000000
+
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB                                    48
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB                                    63
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK                                   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/coex_tx_req.h b/hw/fig/v2/coex_tx_req.h
new file mode 100644
index 000000000000..ed5b4c57bfd8
--- /dev/null
+++ b/hw/fig/v2/coex_tx_req.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_REQ_H_
+#define _COEX_TX_REQ_H_
+
+#define NUM_OF_DWORDS_COEX_TX_REQ 6
+
+#define NUM_OF_QWORDS_COEX_TX_REQ 3
+
+struct coex_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      nss                                                     :  3,
+                      tx_chain_mask                                           :  8,
+                      bw                                                      :  3,
+                      reserved_0                                              :  2;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      reserved_1                                              :  2;
+             uint32_t tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8,
+                      wlan_request_duration                                   : 16;
+             uint32_t wlan_pkt_type                                           :  4,
+                      coex_tx_reason                                          :  2,
+                      response_frame_type                                     :  5,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_tx_priority                                        :  4,
+                      blackout_details_en                                     :  1,
+                      blackout_peek_duration                                  :  8,
+                      reserved_3a                                             :  5;
+             uint32_t frequency_channel_bonding_mask                          : 16,
+                      num_blackout_windows                                    :  8,
+                      reserved_4a                                             :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  2,
+                      bw                                                      :  3,
+                      tx_chain_mask                                           :  8,
+                      nss                                                     :  3,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8;
+             uint32_t reserved_1                                              :  2,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t wlan_request_duration                                   : 16,
+                      alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8;
+             uint32_t reserved_3a                                             :  5,
+                      blackout_peek_duration                                  :  8,
+                      blackout_details_en                                     :  1,
+                      coex_tx_priority                                        :  4,
+                      sch_tx_burst_ongoing                                    :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      response_frame_type                                     :  5,
+                      coex_tx_reason                                          :  2,
+                      wlan_pkt_type                                           :  4;
+             uint32_t reserved_4a                                             :  8,
+                      num_blackout_windows                                    :  8,
+                      frequency_channel_bonding_mask                          : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_REQ_TX_PWR_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_TX_PWR_LSB                                                      0
+#define COEX_TX_REQ_TX_PWR_MSB                                                      7
+#define COEX_TX_REQ_TX_PWR_MASK                                                     0x00000000000000ff
+
+#define COEX_TX_REQ_MIN_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_MIN_TX_PWR_LSB                                                  8
+#define COEX_TX_REQ_MIN_TX_PWR_MSB                                                  15
+#define COEX_TX_REQ_MIN_TX_PWR_MASK                                                 0x000000000000ff00
+
+#define COEX_TX_REQ_NSS_OFFSET                                                      0x0000000000000000
+#define COEX_TX_REQ_NSS_LSB                                                         16
+#define COEX_TX_REQ_NSS_MSB                                                         18
+#define COEX_TX_REQ_NSS_MASK                                                        0x0000000000070000
+
+#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET                                            0x0000000000000000
+#define COEX_TX_REQ_TX_CHAIN_MASK_LSB                                               19
+#define COEX_TX_REQ_TX_CHAIN_MASK_MSB                                               26
+#define COEX_TX_REQ_TX_CHAIN_MASK_MASK                                              0x0000000007f80000
+
+#define COEX_TX_REQ_BW_OFFSET                                                       0x0000000000000000
+#define COEX_TX_REQ_BW_LSB                                                          27
+#define COEX_TX_REQ_BW_MSB                                                          29
+#define COEX_TX_REQ_BW_MASK                                                         0x0000000038000000
+
+#define COEX_TX_REQ_RESERVED_0_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_0_LSB                                                  30
+#define COEX_TX_REQ_RESERVED_0_MSB                                                  31
+#define COEX_TX_REQ_RESERVED_0_MASK                                                 0x00000000c0000000
+
+#define COEX_TX_REQ_ALT_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_PWR_LSB                                                  32
+#define COEX_TX_REQ_ALT_TX_PWR_MSB                                                  39
+#define COEX_TX_REQ_ALT_TX_PWR_MASK                                                 0x000000ff00000000
+
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET                                           0x0000000000000000
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB                                              40
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB                                              47
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK                                             0x0000ff0000000000
+
+#define COEX_TX_REQ_ALT_NSS_OFFSET                                                  0x0000000000000000
+#define COEX_TX_REQ_ALT_NSS_LSB                                                     48
+#define COEX_TX_REQ_ALT_NSS_MSB                                                     50
+#define COEX_TX_REQ_ALT_NSS_MASK                                                    0x0007000000000000
+
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET                                        0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB                                           51
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB                                           58
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK                                          0x07f8000000000000
+
+#define COEX_TX_REQ_ALT_BW_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_ALT_BW_LSB                                                      59
+#define COEX_TX_REQ_ALT_BW_MSB                                                      61
+#define COEX_TX_REQ_ALT_BW_MASK                                                     0x3800000000000000
+
+#define COEX_TX_REQ_RESERVED_1_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_1_LSB                                                  62
+#define COEX_TX_REQ_RESERVED_1_MSB                                                  63
+#define COEX_TX_REQ_RESERVED_1_MASK                                                 0xc000000000000000
+
+#define COEX_TX_REQ_TX_PWR_1_OFFSET                                                 0x0000000000000008
+#define COEX_TX_REQ_TX_PWR_1_LSB                                                    0
+#define COEX_TX_REQ_TX_PWR_1_MSB                                                    7
+#define COEX_TX_REQ_TX_PWR_1_MASK                                                   0x00000000000000ff
+
+#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET                                             0x0000000000000008
+#define COEX_TX_REQ_ALT_TX_PWR_1_LSB                                                8
+#define COEX_TX_REQ_ALT_TX_PWR_1_MSB                                                15
+#define COEX_TX_REQ_ALT_TX_PWR_1_MASK                                               0x000000000000ff00
+
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET                                    0x0000000000000008
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB                                       16
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB                                       31
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK                                      0x00000000ffff0000
+
+#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET                                            0x0000000000000008
+#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB                                               32
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB                                               35
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK                                              0x0000000f00000000
+
+#define COEX_TX_REQ_COEX_TX_REASON_OFFSET                                           0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_REASON_LSB                                              36
+#define COEX_TX_REQ_COEX_TX_REASON_MSB                                              37
+#define COEX_TX_REQ_COEX_TX_REASON_MASK                                             0x0000003000000000
+
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB                                         38
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB                                         42
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK                                        0x000007c000000000
+
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET                        0x0000000000000008
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK                          0x0000080000000000
+
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET                       0x0000000000000008
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK                         0x0000100000000000
+
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET                                     0x0000000000000008
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK                                       0x0000200000000000
+
+#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET                                         0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB                                            46
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB                                            49
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK                                           0x0003c00000000000
+
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK                                        0x0004000000000000
+
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET                                   0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB                                      51
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB                                      58
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK                                     0x07f8000000000000
+
+#define COEX_TX_REQ_RESERVED_3A_OFFSET                                              0x0000000000000008
+#define COEX_TX_REQ_RESERVED_3A_LSB                                                 59
+#define COEX_TX_REQ_RESERVED_3A_MSB                                                 63
+#define COEX_TX_REQ_RESERVED_3A_MASK                                                0xf800000000000000
+
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET                           0x0000000000000010
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB                              0
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB                              15
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK                             0x000000000000ffff
+
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET                                     0x0000000000000010
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB                                        16
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB                                        23
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK                                       0x0000000000ff0000
+
+#define COEX_TX_REQ_RESERVED_4A_OFFSET                                              0x0000000000000010
+#define COEX_TX_REQ_RESERVED_4A_LSB                                                 24
+#define COEX_TX_REQ_RESERVED_4A_MSB                                                 31
+#define COEX_TX_REQ_RESERVED_4A_MASK                                                0x00000000ff000000
+
+#define COEX_TX_REQ_TLV64_PADDING_OFFSET                                            0x0000000000000010
+#define COEX_TX_REQ_TLV64_PADDING_LSB                                               32
+#define COEX_TX_REQ_TLV64_PADDING_MSB                                               63
+#define COEX_TX_REQ_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/coex_tx_status.h b/hw/fig/v2/coex_tx_status.h
new file mode 100644
index 000000000000..c47c29c2a5ba
--- /dev/null
+++ b/hw/fig/v2/coex_tx_status.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_STATUS_H_
+#define _COEX_TX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_TX_STATUS 4
+
+#define NUM_OF_QWORDS_COEX_TX_STATUS 2
+
+struct coex_tx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  7,
+                      tx_bw                                                   :  3,
+                      tx_status_reason                                        :  3,
+                      tx_wait_ack                                             :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      current_tx_duration                                     : 16;
+             uint32_t next_rx_active_time                                     : 16,
+                      remaining_fes_time                                      : 16;
+             uint32_t tx_antenna_mask                                         :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      reserved_2                                              :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t current_tx_duration                                     : 16,
+                      sch_tx_burst_ongoing                                    :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      tx_wait_ack                                             :  1,
+                      tx_status_reason                                        :  3,
+                      tx_bw                                                   :  3,
+                      reserved_0a                                             :  7;
+             uint32_t remaining_fes_time                                      : 16,
+                      next_rx_active_time                                     : 16;
+             uint32_t reserved_2                                              :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      tx_antenna_mask                                         :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_STATUS_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_RESERVED_0A_LSB                                              0
+#define COEX_TX_STATUS_RESERVED_0A_MSB                                              6
+#define COEX_TX_STATUS_RESERVED_0A_MASK                                             0x000000000000007f
+
+#define COEX_TX_STATUS_TX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_TX_STATUS_TX_BW_LSB                                                    7
+#define COEX_TX_STATUS_TX_BW_MSB                                                    9
+#define COEX_TX_STATUS_TX_BW_MASK                                                   0x0000000000000380
+
+#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET                                      0x0000000000000000
+#define COEX_TX_STATUS_TX_STATUS_REASON_LSB                                         10
+#define COEX_TX_STATUS_TX_STATUS_REASON_MSB                                         12
+#define COEX_TX_STATUS_TX_STATUS_REASON_MASK                                        0x0000000000001c00
+
+#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_TX_WAIT_ACK_LSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MASK                                             0x0000000000002000
+
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK                                     0x0000000000004000
+
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET                                  0x0000000000000000
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK                                    0x0000000000008000
+
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB                                      16
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB                                      31
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK                                     0x00000000ffff0000
+
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB                                      32
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB                                      47
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK                                     0x0000ffff00000000
+
+#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET                                    0x0000000000000000
+#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB                                       48
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB                                       63
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK                                      0xffff000000000000
+
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET                                       0x0000000000000008
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB                                          0
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB                                          7
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK                                         0x00000000000000ff
+
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET                                     0x0000000000000008
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB                                        8
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB                                        15
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK                                       0x000000000000ff00
+
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET                                      0x0000000000000008
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB                                         16
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB                                         23
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK                                        0x0000000000ff0000
+
+#define COEX_TX_STATUS_RESERVED_2_OFFSET                                            0x0000000000000008
+#define COEX_TX_STATUS_RESERVED_2_LSB                                               24
+#define COEX_TX_STATUS_RESERVED_2_MSB                                               31
+#define COEX_TX_STATUS_RESERVED_2_MASK                                              0x00000000ff000000
+
+#define COEX_TX_STATUS_TLV64_PADDING_OFFSET                                         0x0000000000000008
+#define COEX_TX_STATUS_TLV64_PADDING_LSB                                            32
+#define COEX_TX_STATUS_TLV64_PADDING_MSB                                            63
+#define COEX_TX_STATUS_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/com_dtypes.h b/hw/fig/v2/com_dtypes.h
new file mode 100644
index 000000000000..aa7bf7a51845
--- /dev/null
+++ b/hw/fig/v2/com_dtypes.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE   1
+#define FALSE  0
+
+#define  ON   1
+#define  OFF  0
+
+#ifndef NULL
+  #define NULL  0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef  unsigned char      boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef  unsigned int  uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef  unsigned short     uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef  unsigned char      uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef  signed int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef  signed char        int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef  unsigned char      byte;
+#define  _BYTE_DEFINED
+#endif
+
+typedef  unsigned short     word;
+
+typedef  unsigned long      dword;
+
+typedef  unsigned char      uint1;
+
+typedef  unsigned short     uint2;
+
+typedef  unsigned long      uint4;
+
+typedef  signed char        int1;
+
+typedef  signed short       int2;
+
+typedef  long int           int4;
+
+typedef  signed long        sint31;
+
+typedef  signed short       sint15;
+
+typedef  signed char        sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+  #ifndef _INT64_DEFINED
+
+    typedef long long     int64;
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+
+    typedef  unsigned long long  uint64;
+    #define _UINT64_DEFINED
+  #endif
+#else
+
+  #if (defined __GNUC__)
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/fig/v2/eht_sig_usr_mu_mimo_info.h b/hw/fig/v2/eht_sig_usr_mu_mimo_info.h
new file mode 100644
index 000000000000..c9e20d75e648
--- /dev/null
+++ b/hw/fig/v2/eht_sig_usr_mu_mimo_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      sta_coding                                              :  1,
+                      sta_spatial_config                                      :  6,
+                      reserved_0a                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0a                                             :  1,
+                      sta_spatial_config                                      :  6,
+                      sta_coding                                              :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET                                      0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB                                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB                                         10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK                                        0x000007ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET                                     0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB                                        11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB                                        14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK                                       0x00007800
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET                                  0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK                                    0x00008000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET                          0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB                             16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB                             21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK                            0x003f0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET                                 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK                                   0x00400000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                   0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                     0x00800000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET                           0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB                              24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB                              31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK                             0xff000000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB                         7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK                        0x000000ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB                         8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB                         15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK                        0x0000ff00
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB                         16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB                         23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK                        0x00ff0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB                         24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB                         31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK                        0xff000000
+
+#endif
diff --git a/hw/fig/v2/eht_sig_usr_ofdma_info.h b/hw/fig/v2/eht_sig_usr_ofdma_info.h
new file mode 100644
index 000000000000..f2520cccfde9
--- /dev/null
+++ b/hw/fig/v2/eht_sig_usr_ofdma_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  1,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET                                        0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB                                           0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB                                           10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK                                          0x000007ff
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET                                       0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB                                          11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB                                          14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK                                         0x00007800
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK                                     0x00008000
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET                                           0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB                                              16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB                                              19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK                                             0x000f0000
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET                                          0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK                                            0x00100000
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET                                    0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK                                      0x00200000
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK                                     0x00400000
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                     0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                       0x00800000
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET                             0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB                                24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB                                31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK                               0xff000000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB                           0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB                           7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK                          0x000000ff
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB                           8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB                           15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK                          0x0000ff00
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB                           16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB                           23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK                          0x00ff0000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB                           24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB                           31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK                          0xff000000
+
+#endif
diff --git a/hw/fig/v2/eht_sig_usr_su_info.h b/hw/fig/v2/eht_sig_usr_su_info.h
new file mode 100644
index 000000000000..208cb4de0539
--- /dev/null
+++ b/hw/fig/v2/eht_sig_usr_su_info.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  9,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  9,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+#endif
+};
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET                                           0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB                                              0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB                                              10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK                                             0x000007ff
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET                                          0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB                                             11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB                                             14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK                                            0x00007800
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK                                        0x00008000
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET                                              0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB                                                 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB                                                 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK                                                0x000f0000
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET                                             0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK                                               0x00100000
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET                                       0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK                                         0x00200000
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB                                         22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB                                         30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK                                        0x7fc00000
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v2/expected_response.h b/hw/fig/v2/expected_response.h
new file mode 100644
index 000000000000..b3ec83ceccf8
--- /dev/null
+++ b/hw/fig/v2/expected_response.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EXPECTED_RESPONSE_H_
+#define _EXPECTED_RESPONSE_H_
+
+#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
+
+#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
+
+struct expected_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t tx_ad2_47_32                                            : 16,
+                      expected_response_type                                  :  5,
+                      response_to_response                                    :  3,
+                      su_ba_user_number                                       :  1,
+                      response_info_part2_required                            :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      eht___reserved_g_0022_ndp_expected                                :  1,
+                      reserved_1                                              :  4;
+             uint32_t ndp_sta_partial_aid_2_8_0                               : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid1_8_0                                : 11;
+             uint32_t ast_index                                               : 16,
+                      capture_ack_ba_sounding                                 :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_320mhz                            :  1,
+                      reserved_3a                                             :  9;
+             uint32_t fcs                                                     :  9,
+                      expect_rx_with_blackout_details                         :  1,
+                      crc                                                     :  4,
+                      scrambler_seed                                          :  7,
+                      reserved_4b                                             : 11;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t reserved_1                                              :  4,
+                      eht___reserved_g_0022_ndp_expected                                :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      response_info_part2_required                            :  1,
+                      su_ba_user_number                                       :  1,
+                      response_to_response                                    :  3,
+                      expected_response_type                                  :  5,
+                      tx_ad2_47_32                                            : 16;
+             uint32_t ndp_sta_partial_aid1_8_0                                : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid_2_8_0                               : 11;
+             uint32_t reserved_3a                                             :  9,
+                      capture_sounding_1str_320mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_ack_ba_sounding                                 :  1,
+                      ast_index                                               : 16;
+             uint32_t reserved_4b                                             : 11,
+                      scrambler_seed                                          :  7,
+                      crc                                                     :  4,
+                      expect_rx_with_blackout_details                         :  1,
+                      fcs                                                     :  9;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET                                        0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB                                           0
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB                                           31
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK                                          0x00000000ffffffff
+
+#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET                                       0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB                                          32
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB                                          47
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK                                         0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET                             0x0000000000000000
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB                                48
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB                                52
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK                               0x001f000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET                               0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB                                  53
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB                                  55
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK                                 0x00e0000000000000
+
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET                                  0x0000000000000000
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK                                    0x0100000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET                       0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK                         0x0200000000000000
+
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET                         0x0000000000000000
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK                           0x0400000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_1_OFFSET                                         0x0000000000000000
+#define EXPECTED_RESPONSE_RESERVED_1_LSB                                            60
+#define EXPECTED_RESPONSE_RESERVED_1_MSB                                            63
+#define EXPECTED_RESPONSE_RESERVED_1_MASK                                           0xf000000000000000
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET                          0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB                             0
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB                             10
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK                            0x00000000000007ff
+
+#define EXPECTED_RESPONSE_RESERVED_2_OFFSET                                         0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_2_LSB                                            11
+#define EXPECTED_RESPONSE_RESERVED_2_MSB                                            20
+#define EXPECTED_RESPONSE_RESERVED_2_MASK                                           0x00000000001ff800
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET                           0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB                              21
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB                              31
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK                             0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_AST_INDEX_OFFSET                                          0x0000000000000008
+#define EXPECTED_RESPONSE_AST_INDEX_LSB                                             32
+#define EXPECTED_RESPONSE_AST_INDEX_MSB                                             47
+#define EXPECTED_RESPONSE_AST_INDEX_MASK                                            0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET                            0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK                              0x0001000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK                          0x0002000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK                          0x0004000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK                          0x0008000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK                         0x0010000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK                         0x0020000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK                         0x0040000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET                                        0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_3A_LSB                                           55
+#define EXPECTED_RESPONSE_RESERVED_3A_MSB                                           63
+#define EXPECTED_RESPONSE_RESERVED_3A_MASK                                          0xff80000000000000
+
+#define EXPECTED_RESPONSE_FCS_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_FCS_LSB                                                   0
+#define EXPECTED_RESPONSE_FCS_MSB                                                   8
+#define EXPECTED_RESPONSE_FCS_MASK                                                  0x00000000000001ff
+
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                    0x0000000000000010
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                      0x0000000000000200
+
+#define EXPECTED_RESPONSE_CRC_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_CRC_LSB                                                   10
+#define EXPECTED_RESPONSE_CRC_MSB                                                   13
+#define EXPECTED_RESPONSE_CRC_MASK                                                  0x0000000000003c00
+
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET                                     0x0000000000000010
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB                                        14
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB                                        20
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK                                       0x00000000001fc000
+
+#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET                                        0x0000000000000010
+#define EXPECTED_RESPONSE_RESERVED_4B_LSB                                           21
+#define EXPECTED_RESPONSE_RESERVED_4B_MSB                                           31
+#define EXPECTED_RESPONSE_RESERVED_4B_MASK                                          0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET                                      0x0000000000000010
+#define EXPECTED_RESPONSE_TLV64_PADDING_LSB                                         32
+#define EXPECTED_RESPONSE_TLV64_PADDING_MSB                                         63
+#define EXPECTED_RESPONSE_TLV64_PADDING_MASK                                        0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/he_sig_a_mu_dl_info.h b/hw/fig/v2/he_sig_a_mu_dl_info.h
new file mode 100644
index 000000000000..84571eb65d3b
--- /dev/null
+++ b/hw/fig/v2/he_sig_a_mu_dl_info.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t dl_ul_flag                                              :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dcm_of_sig_b                                            :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  3,
+                      num_sig_b_symbols                                       :  4,
+                      comp_mode_sig_b                                         :  1,
+                      cp_ltf_size                                             :  2,
+                      doppler_indication                                      :  1,
+                      reserved_0a                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  1,
+                      num_ltf_symbols                                         :  3,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0a                                             :  6,
+                      doppler_indication                                      :  1,
+                      cp_ltf_size                                             :  2,
+                      comp_mode_sig_b                                         :  1,
+                      num_sig_b_symbols                                       :  4,
+                      transmit_bw                                             :  3,
+                      spatial_reuse                                           :  4,
+                      bss_color_id                                            :  6,
+                      dcm_of_sig_b                                            :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dl_ul_flag                                              :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET                                       0x00000000
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK                                         0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB                                        1
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB                                        3
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK                                       0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK                                       0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB                                        5
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB                                        10
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK                                       0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB                                       11
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB                                       14
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK                                      0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB                                         15
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB                                         17
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK                                        0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET                                0x00000000
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB                                   18
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB                                   21
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK                                  0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET                                  0x00000000
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK                                    0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB                                         23
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB                                         24
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK                                        0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET                               0x00000000
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK                                 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB                                         31
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK                                        0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET                                  0x00000004
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB                                     8
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB                                     10
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK                                    0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                0x00000004
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK                                  0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_STBC_LSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MASK                                               0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB                           13
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB                           14
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK                          0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                   0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_DL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_DL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_DL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_DL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_DL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v2/he_sig_a_mu_ul_info.h b/hw/fig/v2/he_sig_a_mu_ul_info.h
new file mode 100644
index 000000000000..e2d0ad73a66c
--- /dev/null
+++ b/hw/fig/v2/he_sig_a_mu_ul_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           : 16,
+                      reserved_0a                                             :  1,
+                      transmit_bw                                             :  2,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  9,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      transmit_bw                                             :  2,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           : 16,
+                      bss_color_id                                            :  6,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      reserved_1a                                             :  9,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/fig/v2/he_sig_a_su_info.h b/hw/fig/v2/he_sig_a_su_info.h
new file mode 100644
index 000000000000..e4be3671016e
--- /dev/null
+++ b/hw/fig/v2/he_sig_a_su_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      beam_change                                             :  1,
+                      dl_ul_flag                                              :  1,
+                      transmit_mcs                                            :  4,
+                      dcm                                                     :  1,
+                      bss_color_id                                            :  6,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  2,
+                      cp_ltf_size                                             :  2,
+                      nsts                                                    :  3,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      coding                                                  :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      txbf                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      reserved_1a                                             :  1,
+                      doppler_indication                                      :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      nsts                                                    :  3,
+                      cp_ltf_size                                             :  2,
+                      transmit_bw                                             :  2,
+                      spatial_reuse                                           :  4,
+                      reserved_0a                                             :  1,
+                      bss_color_id                                            :  6,
+                      dcm                                                     :  1,
+                      transmit_mcs                                            :  4,
+                      dl_ul_flag                                              :  1,
+                      beam_change                                             :  1,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      doppler_indication                                      :  1,
+                      reserved_1a                                             :  1,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      txbf                                                    :  1,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      coding                                                  :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET                                   0x00000000
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK                                     0x00000001
+
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK                                           0x00000002
+
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET                                          0x00000000
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK                                            0x00000004
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB                                           3
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB                                           6
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK                                          0x00000078
+
+#define HE_SIG_A_SU_INFO_DCM_OFFSET                                                 0x00000000
+#define HE_SIG_A_SU_INFO_DCM_LSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MASK                                                   0x00000080
+
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB                                           8
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB                                           13
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK                                          0x00003f00
+
+#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET                                       0x00000000
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB                                          15
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB                                          18
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK                                         0x00078000
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB                                            19
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB                                            20
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK                                           0x00180000
+
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB                                            21
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB                                            22
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK                                           0x00600000
+
+#define HE_SIG_A_SU_INFO_NSTS_OFFSET                                                0x00000000
+#define HE_SIG_A_SU_INFO_NSTS_LSB                                                   23
+#define HE_SIG_A_SU_INFO_NSTS_MSB                                                   25
+#define HE_SIG_A_SU_INFO_NSTS_MASK                                                  0x03800000
+
+#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB                                            26
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB                                            31
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK                                           0xfc000000
+
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET                                       0x00000004
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB                                          0
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB                                          6
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK                                         0x0000007f
+
+#define HE_SIG_A_SU_INFO_CODING_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_CODING_LSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MASK                                                0x00000080
+
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                   0x00000004
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK                                     0x00000100
+
+#define HE_SIG_A_SU_INFO_STBC_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_STBC_LSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MASK                                                  0x00000200
+
+#define HE_SIG_A_SU_INFO_TXBF_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TXBF_LSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MASK                                                  0x00000400
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB                              11
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB                              12
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK                             0x00001800
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                    0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                      0x00002000
+
+#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET                                         0x00000004
+#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET                                  0x00000004
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK                                    0x00008000
+
+#define HE_SIG_A_SU_INFO_CRC_OFFSET                                                 0x00000004
+#define HE_SIG_A_SU_INFO_CRC_LSB                                                    16
+#define HE_SIG_A_SU_INFO_CRC_MSB                                                    19
+#define HE_SIG_A_SU_INFO_CRC_MASK                                                   0x000f0000
+
+#define HE_SIG_A_SU_INFO_TAIL_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TAIL_LSB                                                   20
+#define HE_SIG_A_SU_INFO_TAIL_MSB                                                   25
+#define HE_SIG_A_SU_INFO_TAIL_MASK                                                  0x03f00000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK                                   0x04000000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB                                    27
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB                                    29
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK                                   0x38000000
+
+#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_RX_NDP_LSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MASK                                                0x40000000
+
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                             0x80000000
+
+#endif
diff --git a/hw/fig/v2/he_sig_b1_mu_info.h b/hw/fig/v2/he_sig_b1_mu_info.h
new file mode 100644
index 000000000000..a248c3dc67b3
--- /dev/null
+++ b/hw/fig/v2/he_sig_b1_mu_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation                                           :  8,
+                      reserved_0                                              : 23,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 23,
+                      ru_allocation                                           :  8;
+#endif
+};
+
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
+
+#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
+#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
+
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/fig/v2/he_sig_b2_mu_info.h b/hw/fig/v2/he_sig_b2_mu_info.h
new file mode 100644
index 000000000000..83d6f3bc843f
--- /dev/null
+++ b/hw/fig/v2/he_sig_b2_mu_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
+
+struct he_sig_b2_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_spatial_config                                      :  4,
+                      sta_mcs                                                 :  4,
+                      reserved_set_to_1                                       :  1,
+                      sta_coding                                              :  1,
+                      reserved_0a                                             :  7,
+                      nsts                                                    :  3,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      nsts                                                    :  3,
+                      reserved_0a                                             :  7,
+                      sta_coding                                              :  1,
+                      reserved_set_to_1                                       :  1,
+                      sta_mcs                                                 :  4,
+                      sta_spatial_config                                      :  4,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
+#define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
+#define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
+#define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
+
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
+
+#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
+#define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
+#define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
+#define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
+
+#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
+#define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
+
+#define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
+#define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
+#define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
+#define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
+
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
+#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
+
+#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
+#define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
+#define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
+#define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
+
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
+
+#endif
diff --git a/hw/fig/v2/he_sig_b2_ofdma_info.h b/hw/fig/v2/he_sig_b2_ofdma_info.h
new file mode 100644
index 000000000000..6357d216eb3a
--- /dev/null
+++ b/hw/fig/v2/he_sig_b2_ofdma_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
+
+struct he_sig_b2_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      nsts                                                    :  3,
+                      txbf                                                    :  1,
+                      sta_mcs                                                 :  4,
+                      sta_dcm                                                 :  1,
+                      sta_coding                                              :  1,
+                      reserved_0                                              : 10,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 10,
+                      sta_coding                                              :  1,
+                      sta_dcm                                                 :  1,
+                      sta_mcs                                                 :  4,
+                      txbf                                                    :  1,
+                      nsts                                                    :  3,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET                                          0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB                                             0
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB                                             10
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK                                            0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB                                               11
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB                                               13
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK                                              0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK                                              0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB                                            18
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK                                           0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK                                           0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK                                        0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB                                         21
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB                                         30
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK                                        0x7fe00000
+
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET                                      0x00000004
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB                                         0
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB                                         7
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK                                        0x000000ff
+
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET                                         0x00000004
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB                                            8
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK                                           0x0000ff00
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET                                     0x00000004
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB                                        16
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB                                        31
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/fig/v2/ht_sig_info.h b/hw/fig/v2/ht_sig_info.h
new file mode 100644
index 000000000000..d6a4a719e6e2
--- /dev/null
+++ b/hw/fig/v2/ht_sig_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mcs                                                     :  7,
+                      cbw                                                     :  1,
+                      length                                                  : 16,
+                      reserved_0                                              :  8;
+             uint32_t smoothing                                               :  1,
+                      not_sounding                                            :  1,
+                      ht_reserved                                             :  1,
+                      aggregation                                             :  1,
+                      stbc                                                    :  2,
+                      fec_coding                                              :  1,
+                      short_gi                                                :  1,
+                      num_ext_sp_str                                          :  2,
+                      crc                                                     :  8,
+                      signal_tail                                             :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      length                                                  : 16,
+                      cbw                                                     :  1,
+                      mcs                                                     :  7;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      signal_tail                                             :  6,
+                      crc                                                     :  8,
+                      num_ext_sp_str                                          :  2,
+                      short_gi                                                :  1,
+                      fec_coding                                              :  1,
+                      stbc                                                    :  2,
+                      aggregation                                             :  1,
+                      ht_reserved                                             :  1,
+                      not_sounding                                            :  1,
+                      smoothing                                               :  1;
+#endif
+};
+
+#define HT_SIG_INFO_MCS_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_MCS_LSB                                                         0
+#define HT_SIG_INFO_MCS_MSB                                                         6
+#define HT_SIG_INFO_MCS_MASK                                                        0x0000007f
+
+#define HT_SIG_INFO_CBW_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_CBW_LSB                                                         7
+#define HT_SIG_INFO_CBW_MSB                                                         7
+#define HT_SIG_INFO_CBW_MASK                                                        0x00000080
+
+#define HT_SIG_INFO_LENGTH_OFFSET                                                   0x00000000
+#define HT_SIG_INFO_LENGTH_LSB                                                      8
+#define HT_SIG_INFO_LENGTH_MSB                                                      23
+#define HT_SIG_INFO_LENGTH_MASK                                                     0x00ffff00
+
+#define HT_SIG_INFO_RESERVED_0_OFFSET                                               0x00000000
+#define HT_SIG_INFO_RESERVED_0_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_0_MSB                                                  31
+#define HT_SIG_INFO_RESERVED_0_MASK                                                 0xff000000
+
+#define HT_SIG_INFO_SMOOTHING_OFFSET                                                0x00000004
+#define HT_SIG_INFO_SMOOTHING_LSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MASK                                                  0x00000001
+
+#define HT_SIG_INFO_NOT_SOUNDING_OFFSET                                             0x00000004
+#define HT_SIG_INFO_NOT_SOUNDING_LSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MASK                                               0x00000002
+
+#define HT_SIG_INFO_HT_RESERVED_OFFSET                                              0x00000004
+#define HT_SIG_INFO_HT_RESERVED_LSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MASK                                                0x00000004
+
+#define HT_SIG_INFO_AGGREGATION_OFFSET                                              0x00000004
+#define HT_SIG_INFO_AGGREGATION_LSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MASK                                                0x00000008
+
+#define HT_SIG_INFO_STBC_OFFSET                                                     0x00000004
+#define HT_SIG_INFO_STBC_LSB                                                        4
+#define HT_SIG_INFO_STBC_MSB                                                        5
+#define HT_SIG_INFO_STBC_MASK                                                       0x00000030
+
+#define HT_SIG_INFO_FEC_CODING_OFFSET                                               0x00000004
+#define HT_SIG_INFO_FEC_CODING_LSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MASK                                                 0x00000040
+
+#define HT_SIG_INFO_SHORT_GI_OFFSET                                                 0x00000004
+#define HT_SIG_INFO_SHORT_GI_LSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MASK                                                   0x00000080
+
+#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET                                           0x00000004
+#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB                                              8
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB                                              9
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK                                             0x00000300
+
+#define HT_SIG_INFO_CRC_OFFSET                                                      0x00000004
+#define HT_SIG_INFO_CRC_LSB                                                         10
+#define HT_SIG_INFO_CRC_MSB                                                         17
+#define HT_SIG_INFO_CRC_MASK                                                        0x0003fc00
+
+#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET                                              0x00000004
+#define HT_SIG_INFO_SIGNAL_TAIL_LSB                                                 18
+#define HT_SIG_INFO_SIGNAL_TAIL_MSB                                                 23
+#define HT_SIG_INFO_SIGNAL_TAIL_MASK                                                0x00fc0000
+
+#define HT_SIG_INFO_RESERVED_1_OFFSET                                               0x00000004
+#define HT_SIG_INFO_RESERVED_1_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_1_MSB                                                  30
+#define HT_SIG_INFO_RESERVED_1_MASK                                                 0x7f000000
+
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                                0x00000004
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                  0x80000000
+
+#endif
diff --git a/hw/fig/v2/l_sig_a_info.h b/hw/fig/v2/l_sig_a_info.h
new file mode 100644
index 000000000000..6da0725dfee7
--- /dev/null
+++ b/hw/fig/v2/l_sig_a_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      lsig_reserved                                           :  1,
+                      length                                                  : 12,
+                      parity                                                  :  1,
+                      tail                                                    :  6,
+                      pkt_type                                                :  4,
+                      captured_implicit_sounding                              :  1,
+                      reserved                                                :  2,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                :  2,
+                      captured_implicit_sounding                              :  1,
+                      pkt_type                                                :  4,
+                      tail                                                    :  6,
+                      parity                                                  :  1,
+                      length                                                  : 12,
+                      lsig_reserved                                           :  1,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_A_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_RATE_LSB                                                       0
+#define L_SIG_A_INFO_RATE_MSB                                                       3
+#define L_SIG_A_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET                                           0x00000000
+#define L_SIG_A_INFO_LSIG_RESERVED_LSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MASK                                             0x00000010
+
+#define L_SIG_A_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_LENGTH_LSB                                                     5
+#define L_SIG_A_INFO_LENGTH_MSB                                                     16
+#define L_SIG_A_INFO_LENGTH_MASK                                                    0x0001ffe0
+
+#define L_SIG_A_INFO_PARITY_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_PARITY_LSB                                                     17
+#define L_SIG_A_INFO_PARITY_MSB                                                     17
+#define L_SIG_A_INFO_PARITY_MASK                                                    0x00020000
+
+#define L_SIG_A_INFO_TAIL_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_TAIL_LSB                                                       18
+#define L_SIG_A_INFO_TAIL_MSB                                                       23
+#define L_SIG_A_INFO_TAIL_MASK                                                      0x00fc0000
+
+#define L_SIG_A_INFO_PKT_TYPE_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_PKT_TYPE_LSB                                                   24
+#define L_SIG_A_INFO_PKT_TYPE_MSB                                                   27
+#define L_SIG_A_INFO_PKT_TYPE_MASK                                                  0x0f000000
+
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET                              0x00000000
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK                                0x10000000
+
+#define L_SIG_A_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_RESERVED_LSB                                                   29
+#define L_SIG_A_INFO_RESERVED_MSB                                                   30
+#define L_SIG_A_INFO_RESERVED_MASK                                                  0x60000000
+
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/fig/v2/l_sig_b_info.h b/hw/fig/v2/l_sig_b_info.h
new file mode 100644
index 000000000000..f2052702e2de
--- /dev/null
+++ b/hw/fig/v2/l_sig_b_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      length                                                  : 12,
+                      reserved                                                : 15,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                : 15,
+                      length                                                  : 12,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_B_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_B_INFO_RATE_LSB                                                       0
+#define L_SIG_B_INFO_RATE_MSB                                                       3
+#define L_SIG_B_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_B_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_B_INFO_LENGTH_LSB                                                     4
+#define L_SIG_B_INFO_LENGTH_MSB                                                     15
+#define L_SIG_B_INFO_LENGTH_MASK                                                    0x0000fff0
+
+#define L_SIG_B_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_B_INFO_RESERVED_LSB                                                   16
+#define L_SIG_B_INFO_RESERVED_MSB                                                   30
+#define L_SIG_B_INFO_RESERVED_MASK                                                  0x7fff0000
+
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/fig/v2/macrx_abort_request_info.h b/hw/fig/v2/macrx_abort_request_info.h
new file mode 100644
index 000000000000..038f4038fa59
--- /dev/null
+++ b/hw/fig/v2/macrx_abort_request_info.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t macrx_abort_reason                                      :  8,
+                      reserved_0                                              :  8;
+#else
+             uint16_t reserved_0                                              :  8,
+                      macrx_abort_reason                                      :  8;
+#endif
+};
+
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET                          0x00000000
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB                             0
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB                             7
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK                            0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     8
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x0000ff00
+
+#endif
diff --git a/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h b/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
new file mode 100644
index 000000000000..f29ca356a223
--- /dev/null
+++ b/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
+#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
+
+#include "eht_sig_usr_mu_mimo_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
+
+struct mactx_eht_sig_usr_mu_mimo {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#else
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_eht_sig_usr_ofdma.h b/hw/fig/v2/mactx_eht_sig_usr_ofdma.h
new file mode 100644
index 000000000000..24bf6691978d
--- /dev/null
+++ b/hw/fig/v2/mactx_eht_sig_usr_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
+#define _MACTX_EHT_SIG_USR_OFDMA_H_
+
+#include "eht_sig_usr_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
+
+struct mactx_eht_sig_usr_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#else
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET  0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB     0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB     10
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK    0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB    11
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB    14
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK   0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET     0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB        16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB        19
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK       0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK      0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_eht_sig_usr_su.h b/hw/fig/v2/mactx_eht_sig_usr_su.h
new file mode 100644
index 000000000000..1fb82723c1ff
--- /dev/null
+++ b/hw/fig/v2/mactx_eht_sig_usr_su.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_SU_H_
+#define _MACTX_EHT_SIG_USR_SU_H_
+
+#include "eht_sig_usr_su_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
+
+struct mactx_eht_sig_usr_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET        0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB           0
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB           10
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK          0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET       0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB          11
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB          14
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK         0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK     0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET           0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB              16
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB              19
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK             0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET          0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK            0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK      0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB      22
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB      30
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK     0x000000007fc00000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB                                      32
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB                                      63
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_a_mu_dl.h b/hw/fig/v2/mactx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..438f3af6f9e7
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_DL_H_
+#define _MACTX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
+
+struct mactx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_a_mu_ul.h b/hw/fig/v2/mactx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..96d2b912665a
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_UL_H_
+#define _MACTX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
+
+struct mactx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_a_su.h b/hw/fig/v2/mactx_he_sig_a_su.h
new file mode 100644
index 000000000000..e51241d26559
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_SU_H_
+#define _MACTX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
+
+struct mactx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_b1_mu.h b/hw/fig/v2/mactx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..700528af2048
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B1_MU_H_
+#define _MACTX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
+
+struct mactx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_b2_mu.h b/hw/fig/v2/mactx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..ccc1c593fed6
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_MU_H_
+#define _MACTX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
+
+struct mactx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_he_sig_b2_ofdma.h b/hw/fig/v2/mactx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..afc3c4b22841
--- /dev/null
+++ b/hw/fig/v2/mactx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
+#define _MACTX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
+
+struct mactx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_ht_sig.h b/hw/fig/v2/mactx_ht_sig.h
new file mode 100644
index 000000000000..ec28824c590f
--- /dev/null
+++ b/hw/fig/v2/mactx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HT_SIG_H_
+#define _MACTX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_MACTX_HT_SIG 2
+
+#define NUM_OF_QWORDS_MACTX_HT_SIG 1
+
+struct mactx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#endif
+};
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_l_sig_a.h b/hw/fig/v2/mactx_l_sig_a.h
new file mode 100644
index 000000000000..061e46e28a2c
--- /dev/null
+++ b/hw/fig/v2/mactx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_A_H_
+#define _MACTX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
+
+struct mactx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_l_sig_b.h b/hw/fig/v2/mactx_l_sig_b.h
new file mode 100644
index 000000000000..6d533acef675
--- /dev/null
+++ b/hw/fig/v2/mactx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_B_H_
+#define _MACTX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
+
+struct mactx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_phy_desc.h b/hw/fig/v2/mactx_phy_desc.h
new file mode 100644
index 000000000000..ee4ccdf65c28
--- /dev/null
+++ b/hw/fig/v2/mactx_phy_desc.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_PHY_DESC_H_
+#define _MACTX_PHY_DESC_H_
+
+#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
+
+#define NUM_OF_QWORDS_MACTX_PHY_DESC 2
+
+struct mactx_phy_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             : 16,
+                      bf_type                                                 :  2,
+                      wait_sifs                                               :  2,
+                      dot11b_preamble_type                                    :  1,
+                      pkt_type                                                :  4,
+                      su_or_mu                                                :  2,
+                      mu_type                                                 :  1,
+                      bandwidth                                               :  3,
+                      channel_capture                                         :  1;
+             uint32_t mcs                                                     :  5,
+                      global_ofdma_mimo_enable                                :  1,
+                      stbc                                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8,
+                      measure_power                                           :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      back_to_back_transmission_expected                      :  1,
+                      heavy_clip_nss                                          :  3,
+                      txbf_per_packet_no_csd_no_walsh                         :  1;
+             uint32_t ndp                                                     :  3,
+                      ul_flag                                                 :  1,
+                      triggered                                               :  1,
+                      ap_pkt_bw                                               :  3,
+                      ru_position_start                                       :  8,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      tlv_source                                              :  1,
+                      reserved_2a                                             :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_2b                                             :  2,
+                      clpc_enable                                             :  1,
+                      mu_ndp                                                  :  1,
+                      response_expected                                       :  1;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_chain_mask_valid                                     :  1,
+                      ant_sel_valid                                           :  1,
+                      ant_sel                                                 :  1,
+                      cp_setting                                              :  2,
+                      he_ppdu_subtype                                         :  2,
+                      active_channel                                          :  3,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      ltf_size                                                :  2,
+                      ru_size_updated_v2                                      :  4,
+                      reserved_3c                                             :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+#else
+             uint32_t channel_capture                                         :  1,
+                      bandwidth                                               :  3,
+                      mu_type                                                 :  1,
+                      su_or_mu                                                :  2,
+                      pkt_type                                                :  4,
+                      dot11b_preamble_type                                    :  1,
+                      wait_sifs                                               :  2,
+                      bf_type                                                 :  2,
+                      reserved_0a                                             : 16;
+             uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
+                      heavy_clip_nss                                          :  3,
+                      back_to_back_transmission_expected                      :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      measure_power                                           :  1,
+                      tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      dot11ax_su_extended                                     :  1,
+                      stbc                                                    :  1,
+                      global_ofdma_mimo_enable                                :  1,
+                      mcs                                                     :  5;
+             uint32_t response_expected                                       :  1,
+                      mu_ndp                                                  :  1,
+                      clpc_enable                                             :  1,
+                      reserved_2b                                             :  2,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  1,
+                      tlv_source                                              :  1,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      ru_position_start                                       :  8,
+                      ap_pkt_bw                                               :  3,
+                      triggered                                               :  1,
+                      ul_flag                                                 :  1,
+                      ndp                                                     :  3;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_3c                                             :  1,
+                      ru_size_updated_v2                                      :  4,
+                      ltf_size                                                :  2,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      active_channel                                          :  3,
+                      he_ppdu_subtype                                         :  2,
+                      cp_setting                                              :  2,
+                      ant_sel                                                 :  1,
+                      ant_sel_valid                                           :  1,
+                      rx_chain_mask_valid                                     :  1,
+                      rx_chain_mask                                           :  8;
+#endif
+};
+
+#define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
+#define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
+#define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x000000000000ffff
+
+#define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
+#define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
+#define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x0000000000030000
+
+#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
+#define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
+#define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x00000000000c0000
+
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x0000000000000000
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x0000000000100000
+
+#define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
+#define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
+#define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x0000000001e00000
+
+#define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
+#define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
+#define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x0000000006000000
+
+#define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x0000000008000000
+
+#define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
+#define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
+#define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x0000000070000000
+
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x0000000080000000
+
+#define MACTX_PHY_DESC_MCS_OFFSET                                                   0x0000000000000000
+#define MACTX_PHY_DESC_MCS_LSB                                                      32
+#define MACTX_PHY_DESC_MCS_MSB                                                      36
+#define MACTX_PHY_DESC_MCS_MASK                                                     0x0000001f00000000
+
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x0000000000000000
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x0000002000000000
+
+#define MACTX_PHY_DESC_STBC_OFFSET                                                  0x0000000000000000
+#define MACTX_PHY_DESC_STBC_LSB                                                     38
+#define MACTX_PHY_DESC_STBC_MSB                                                     38
+#define MACTX_PHY_DESC_STBC_MASK                                                    0x0000004000000000
+
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x0000008000000000
+
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x0000010000000000
+
+#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            41
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            48
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe0000000000
+
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          49
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          56
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe000000000000
+
+#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x0200000000000000
+
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x0000000000000000
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x0400000000000000
+
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x0000000000000000
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x0800000000000000
+
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x0000000000000000
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           60
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           62
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x7000000000000000
+
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x0000000000000000
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x8000000000000000
+
+#define MACTX_PHY_DESC_NDP_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NDP_LSB                                                      0
+#define MACTX_PHY_DESC_NDP_MSB                                                      2
+#define MACTX_PHY_DESC_NDP_MASK                                                     0x0000000000000007
+
+#define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_UL_FLAG_LSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x0000000000000008
+
+#define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_TRIGGERED_LSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x0000000000000010
+
+#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                5
+#define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                7
+#define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x00000000000000e0
+
+#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        8
+#define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        15
+#define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x000000000000ff00
+
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x0000000000000008
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              16
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              18
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x0000000000070000
+
+#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x0000000000080000
+
+#define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2A_LSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x0000000000100000
+
+#define MACTX_PHY_DESC_NSS_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NSS_LSB                                                      21
+#define MACTX_PHY_DESC_NSS_MSB                                                      23
+#define MACTX_PHY_DESC_NSS_MASK                                                     0x0000000000e00000
+
+#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
+#define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
+#define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x0000000007000000
+
+#define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
+#define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
+#define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x0000000018000000
+
+#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x0000000020000000
+
+#define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x0000000000000008
+#define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x0000000040000000
+
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x0000000080000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            32
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            39
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff00000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x0000010000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x0000020000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_LSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x0000040000000000
+
+#define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_CP_SETTING_LSB                                               43
+#define MACTX_PHY_DESC_CP_SETTING_MSB                                               44
+#define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x0000180000000000
+
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000000000008
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          45
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          46
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x0000600000000000
+
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000000000008
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           47
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           49
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x0003800000000000
+
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000000000008
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x0004000000000000
+
+#define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000000000008
+#define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 51
+#define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 52
+#define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x0018000000000000
+
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000000000008
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       53
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       56
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e0000000000000
+
+#define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_3C_LSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x0200000000000000
+
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000000000008
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          58
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          63
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc00000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_u_sig_eht_su_mu.h b/hw/fig/v2/mactx_u_sig_eht_su_mu.h
new file mode 100644
index 000000000000..f46583e4c7ee
--- /dev/null
+++ b/hw/fig/v2/mactx_u_sig_eht_su_mu.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
+#define _MACTX_U_SIG_EHT_SU_MU_H_
+
+#include "u_sig_eht_su_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
+
+struct mactx_u_sig_eht_su_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#else
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB    0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK   0x0000000000000007
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB    3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB    5
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK   0x0000000000000038
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET  0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK    0x0000000000000040
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB   7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB   12
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK  0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB  13
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB  19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB   20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB   24
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK  0x0000000001f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK   0x0000000002000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB    26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB    31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK   0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK   0x0000000400000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK   0x0000010000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET         0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB            48
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB            51
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK           0x000f000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB           52
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB           57
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK          0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB    59
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB    61
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK   0x3800000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK        0x4000000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_u_sig_eht_tb.h b/hw/fig/v2/mactx_u_sig_eht_tb.h
new file mode 100644
index 000000000000..5e57312a9da2
--- /dev/null
+++ b/hw/fig/v2/mactx_u_sig_eht_tb.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_TB_H_
+#define _MACTX_U_SIG_EHT_TB_H_
+
+#include "u_sig_eht_tb_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
+
+struct mactx_u_sig_eht_tb {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#else
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB          0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK         0x0000000000000007
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB          3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB          5
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK         0x0000000000000038
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK          0x0000000000000040
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB         7
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB         12
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK        0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB        13
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB        19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK       0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB         20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB         25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK        0x0000000003f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB          26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB          31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK         0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK         0x0000000400000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB        35
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB        42
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK       0x000007f800000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB         43
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB         47
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK        0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET               0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB                  48
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB                  51
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK                 0x000f000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET              0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB                 52
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB                 57
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK                0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB          58
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB          62
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK         0x7c00000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_user_desc_common.h b/hw/fig/v2/mactx_user_desc_common.h
new file mode 100644
index 000000000000..04124271bbc9
--- /dev/null
+++ b/hw/fig/v2/mactx_user_desc_common.h
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_COMMON_H_
+#define _MACTX_USER_DESC_COMMON_H_
+
+#include "unallocated_ru_160_info.h"
+#include "ru_allocation_160_info.h"
+#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8
+
+struct mactx_user_desc_common {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      reserved_0b                                             :  5,
+                      ltf_size                                                :  2,
+                      reserved_0c                                             :  3,
+                      he_stf_long                                             :  1,
+                      reserved_0d                                             :  7,
+                      num_users_he_sigb_band0                                 :  8;
+             uint32_t num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  5,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1b                                             : 16;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      reserved                                                :  2,
+                      he_sigb_dcm                                             :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_compression                                     :  1,
+                      reserved_2c                                             : 15;
+             uint32_t he_sigb_0_mcs                                           :  3,
+                      reserved_3a                                             : 13,
+                      num_he_sigb_sym                                         :  5,
+                      center_ru_0                                             :  1,
+                      center_ru_1                                             :  1,
+                      reserved_3b                                             :  1,
+                      ftm_en                                                  :  1,
+                      pe_nss                                                  :  3,
+                      pe_ltf_size                                             :  2,
+                      pe_content                                              :  1,
+                      pe_chain_csd_en                                         :  1;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t num_data_symbols                                        : 16,
+                      ndp_ru_tone_set_index                                   :  7,
+                      ndp_feedback_status                                     :  1,
+                      doppler_indication                                      :  1,
+                      reserved_14a                                            :  7;
+             uint32_t spatial_reuse                                           : 16,
+                      distributed_ru                                          :  1,
+                      dru_spreading_bw                                        :  2,
+                      reserved_15a                                            : 13;
+#else
+             uint32_t num_users_he_sigb_band0                                 :  8,
+                      reserved_0d                                             :  7,
+                      he_stf_long                                             :  1,
+                      reserved_0c                                             :  3,
+                      ltf_size                                                :  2,
+                      reserved_0b                                             :  5,
+                      num_users                                               :  6;
+             uint32_t reserved_1b                                             : 16,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1a                                             :  5,
+                      num_ltf_symbols                                         :  3;
+             uint32_t reserved_2c                                             : 15,
+                      he_sigb_compression                                     :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_dcm                                             :  1,
+                      reserved                                                :  2,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t pe_chain_csd_en                                         :  1,
+                      pe_content                                              :  1,
+                      pe_ltf_size                                             :  2,
+                      pe_nss                                                  :  3,
+                      ftm_en                                                  :  1,
+                      reserved_3b                                             :  1,
+                      center_ru_1                                             :  1,
+                      center_ru_0                                             :  1,
+                      num_he_sigb_sym                                         :  5,
+                      reserved_3a                                             : 13,
+                      he_sigb_0_mcs                                           :  3;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t reserved_14a                                            :  7,
+                      doppler_indication                                      :  1,
+                      ndp_feedback_status                                     :  1,
+                      ndp_ru_tone_set_index                                   :  7,
+                      num_data_symbols                                        : 16;
+             uint32_t reserved_15a                                            : 13,
+                      dru_spreading_bw                                        :  2,
+                      distributed_ru                                          :  1,
+                      spatial_reuse                                           : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB                                        0
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB                                        5
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK                                       0x000000000000003f
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB                                      6
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB                                      10
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK                                     0x00000000000007c0
+
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET                                      0x0000000000000000
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB                                         11
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB                                         12
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK                                        0x0000000000001800
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB                                      13
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK                                     0x000000000000e000
+
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK                                     0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK                                     0x0000000000fe0000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB                          24
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB                          31
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK                         0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB                                  32
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB                                  34
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK                                 0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB                                      39
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK                                     0x000000f800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB                          40
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB                          47
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK                         0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB                                      48
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB                                      63
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK                                     0xffff000000000000
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET                     0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB                        0
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB                        1
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK                       0x0000000000000003
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                0x0000000000000004
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET                              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB                                 3
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB                                 5
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK                                0x0000000000000038
+
+#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET                                      0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_LSB                                         6
+#define MACTX_USER_DESC_COMMON_RESERVED_MSB                                         7
+#define MACTX_USER_DESC_COMMON_RESERVED_MASK                                        0x00000000000000c0
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK                                     0x0000000000000100
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB                                      9
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK                                     0x000000000000fe00
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK                             0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB                                      31
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK                                     0x00000000fffe0000
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB                                    32
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB                                    34
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK                                   0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB                                      47
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK                                     0x0000fff800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB                                  48
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB                                  52
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK                                 0x001f000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK                                     0x0020000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK                                     0x0040000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK                                     0x0080000000000000
+
+#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_FTM_EN_LSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MASK                                          0x0100000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_NSS_LSB                                           57
+#define MACTX_USER_DESC_COMMON_PE_NSS_MSB                                           59
+#define MACTX_USER_DESC_COMMON_PE_NSS_MASK                                          0x0e00000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB                                      60
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB                                      61
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK                                     0x3000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK                                      0x4000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK                                 0x8000000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB      0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB      7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK     0x00000000000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB      8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB      15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK     0x000000000000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB      16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB      23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK     0x0000000000ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB      24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB      31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK     0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB      32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB      39
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK     0x000000ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB      40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB      47
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK     0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB      48
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB      55
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK     0x00ff000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB      56
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB      63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK     0xff00000000000000
+
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB                                 0
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB                                 15
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK                                0x000000000000ffff
+
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET                         0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB                            16
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB                            22
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK                           0x00000000007f0000
+
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET                           0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK                             0x0000000000800000
+
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET                            0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK                              0x0000000001000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB                                     25
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB                                     31
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK                                    0x00000000fe000000
+
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET                                 0x0000000000000038
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB                                    32
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB                                    47
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK                                   0x0000ffff00000000
+
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET                                0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK                                  0x0001000000000000
+
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB                                 49
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB                                 50
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK                                0x0006000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB                                     51
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB                                     63
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK                                    0xfff8000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_user_desc_per_user.h b/hw/fig/v2/mactx_user_desc_per_user.h
new file mode 100644
index 000000000000..a68b50d9d639
--- /dev/null
+++ b/hw/fig/v2/mactx_user_desc_per_user.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_PER_USER_H_
+#define _MACTX_USER_DESC_PER_USER_H_
+
+#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3
+
+struct mactx_user_desc_per_user {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t psdu_length                                             : 24,
+                      reserved_0a                                             :  8;
+             uint32_t ru_start_index                                          :  8,
+                      ru_size                                                 :  4,
+                      reserved_1b                                             :  4,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_1c                                             :  1,
+                      mcs                                                     :  5,
+                      dcm                                                     :  1,
+                      reserved_1d                                             :  2;
+             uint32_t fec_type                                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      user_bf_type                                            :  2,
+                      a_factor_ldpc2x                                         :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      cw_len_2x                                               :  2,
+                      reserved_2b                                             :  1,
+                      drop_user_cbf                                           :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      cw_len_1x                                               :  2,
+                      ldpc1x_used                                             :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_2x_codeword                                        :  1,
+                      reserved_2d                                             :  5;
+             uint32_t sw_peer_id                                              : 16,
+                      per_user_subband_mask                                   : 16;
+             uint32_t ldpc_num_avbits                                         : 27,
+                      reserved_4a                                             :  5;
+             uint32_t num_cw_1x                                               : 16,
+                      num_cw_2x                                               : 16;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      psdu_length                                             : 24;
+             uint32_t reserved_1d                                             :  2,
+                      dcm                                                     :  1,
+                      mcs                                                     :  5,
+                      reserved_1c                                             :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      reserved_1b                                             :  4,
+                      ru_size                                                 :  4,
+                      ru_start_index                                          :  8;
+             uint32_t reserved_2d                                             :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc1x_used                                             :  1,
+                      cw_len_1x                                               :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      drop_user_cbf                                           :  1,
+                      reserved_2b                                             :  1,
+                      cw_len_2x                                               :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      a_factor_ldpc2x                                         :  2,
+                      user_bf_type                                            :  2,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      fec_type                                                :  1;
+             uint32_t per_user_subband_mask                                   : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_4a                                             :  5,
+                      ldpc_num_avbits                                         : 27;
+             uint32_t num_cw_2x                                               : 16,
+                      num_cw_1x                                               : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB                                    0
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK                                   0x0000000000ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB                                    24
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK                                   0x00000000ff000000
+
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET                              0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB                                 32
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB                                 39
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK                                0x000000ff00000000
+
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB                                        40
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB                                        43
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK                                       0x00000f0000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB                                    44
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB                                    47
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK                                   0x0000f00000000000
+
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK                         0x0001000000000000
+
+#define MACTX_USER_DESC_PER_USER_NSS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_NSS_LSB                                            49
+#define MACTX_USER_DESC_PER_USER_NSS_MSB                                            51
+#define MACTX_USER_DESC_PER_USER_NSS_MASK                                           0x000e000000000000
+
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB                                  52
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB                                  54
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK                                 0x0070000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK                                   0x0080000000000000
+
+#define MACTX_USER_DESC_PER_USER_MCS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_MCS_LSB                                            56
+#define MACTX_USER_DESC_PER_USER_MCS_MSB                                            60
+#define MACTX_USER_DESC_PER_USER_MCS_MASK                                           0x1f00000000000000
+
+#define MACTX_USER_DESC_PER_USER_DCM_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_DCM_LSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MASK                                           0x2000000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB                                    62
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB                                    63
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK                                   0xc000000000000000
+
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK                                      0x0000000000000001
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK                                   0x0000000000000002
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB                                      2
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB                                      3
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK                                     0x000000000000000c
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB                                      4
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB                                      5
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK                                     0x0000000000000030
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB                                      6
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB                                      7
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK                                     0x00000000000000c0
+
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET                                0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB                                   8
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB                                   9
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK                                  0x0000000000000300
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB                                10
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB                                11
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK                               0x0000000000000c00
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK                              0x0000000000001000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB                                      13
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB                                      14
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK                                     0x0000000000006000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK                                   0x0000000000008000
+
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK                                 0x0000000000010000
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB                                17
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB                                18
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK                               0x0000000000060000
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK                              0x0000000000080000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB                                      20
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB                                      21
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK                                     0x0000000000300000
+
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK                                   0x0000000000400000
+
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK                                   0x0000000000800000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK                             0x0000000001000000
+
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET                          0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK                            0x0000000002000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK                              0x0000000004000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET                                  0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB                                     32
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB                                     47
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK                                    0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET                       0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB                          48
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB                          63
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK                         0xffff000000000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET                             0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB                                0
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB                                26
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK                               0x0000000007ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB                                      32
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB                                      47
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK                                     0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB                                      48
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB                                      63
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_a.h b/hw/fig/v2/mactx_vht_sig_a.h
new file mode 100644
index 000000000000..6dec145785d6
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_A_H_
+#define _MACTX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
+
+struct mactx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_mu160.h b/hw/fig/v2/mactx_vht_sig_b_mu160.h
new file mode 100644
index 000000000000..b66278da930b
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_mu160.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU160_H_
+#define _MACTX_VHT_SIG_B_MU160_H_
+
+#include "vht_sig_b_mu160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
+
+struct mactx_vht_sig_b_mu160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#else
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB         18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK        0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB            19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB            22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK           0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK    0xe000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_mu20.h b/hw/fig/v2/mactx_vht_sig_b_mu20.h
new file mode 100644
index 000000000000..95feca30eaa3
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_mu20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU20_H_
+#define _MACTX_VHT_SIG_B_MU20_H_
+
+#include "vht_sig_b_mu20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
+
+struct mactx_vht_sig_b_mu20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB           15
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK          0x000000000000ffff
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB              16
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB              19
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK             0x00000000000f0000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB   26
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB   28
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK  0x000000001c000000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_mu40.h b/hw/fig/v2/mactx_vht_sig_b_mu40.h
new file mode 100644
index 000000000000..c770db089203
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_mu40.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU40_H_
+#define _MACTX_VHT_SIG_B_MU40_H_
+
+#include "vht_sig_b_mu40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
+
+struct mactx_vht_sig_b_mu40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#else
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB              17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB              20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK             0x00000000001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB       27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB       28
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK      0x0000000018000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB      48
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0001ffff00000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB         49
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB         52
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK        0x001e000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB       59
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK      0xf800000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_mu80.h b/hw/fig/v2/mactx_vht_sig_b_mu80.h
new file mode 100644
index 000000000000..9e39d240b618
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_mu80.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU80_H_
+#define _MACTX_VHT_SIG_B_MU80_H_
+
+#include "vht_sig_b_mu80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
+
+struct mactx_vht_sig_b_mu80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#else
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB              19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB              22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK             0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK      0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK      0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK      0xe000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_su160.h b/hw/fig/v2/mactx_vht_sig_b_su160.h
new file mode 100644
index 000000000000..01bc54e5ab89
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_su160.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU160_H_
+#define _MACTX_VHT_SIG_B_SU160_H_
+
+#include "vht_sig_b_su160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
+
+struct mactx_vht_sig_b_su160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#else
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB         20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK        0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB  21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB  22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK        0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_su20.h b/hw/fig/v2/mactx_vht_sig_b_su20.h
new file mode 100644
index 000000000000..c297cc0785e3
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_su20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU20_H_
+#define _MACTX_VHT_SIG_B_SU20_H_
+
+#include "vht_sig_b_su20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
+
+struct mactx_vht_sig_b_su20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB    17
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB    19
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK   0x00000000000e0000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB         26
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK        0x000000007c000000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_su40.h b/hw/fig/v2/mactx_vht_sig_b_su40.h
new file mode 100644
index 000000000000..002d72c430ca
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_su40.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU40_H_
+#define _MACTX_VHT_SIG_B_SU40_H_
+
+#include "vht_sig_b_su40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
+
+struct mactx_vht_sig_b_su40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#else
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB    19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB    20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB         27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK        0x0000000078000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB      50
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB    59
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB    62
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK   0x7800000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK     0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mactx_vht_sig_b_su80.h b/hw/fig/v2/mactx_vht_sig_b_su80.h
new file mode 100644
index 000000000000..b15646f03f4a
--- /dev/null
+++ b/hw/fig/v2/mactx_vht_sig_b_su80.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU80_H_
+#define _MACTX_VHT_SIG_B_SU80_H_
+
+#include "vht_sig_b_su80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
+
+struct mactx_vht_sig_b_su80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#else
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB           20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK          0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB    21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB    22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK   0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK   0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK   0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mlo_sta_id_details.h b/hw/fig/v2/mlo_sta_id_details.h
new file mode 100644
index 000000000000..952056890206
--- /dev/null
+++ b/hw/fig/v2/mlo_sta_id_details.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MLO_STA_ID_DETAILS_H_
+#define _MLO_STA_ID_DETAILS_H_
+
+#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
+
+struct mlo_sta_id_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t nstr_mlo_sta_id                                         : 10,
+                      block_self_ml_sync                                      :  1,
+                      block_partner_ml_sync                                   :  1,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      reserved_0a                                             :  3;
+#else
+             uint16_t reserved_0a                                             :  3,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      block_partner_ml_sync                                   :  1,
+                      block_self_ml_sync                                      :  1,
+                      nstr_mlo_sta_id                                         : 10;
+#endif
+};
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET                                   0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB                                      0
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB                                      9
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK                                     0x000003ff
+
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET                                0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK                                  0x00000400
+
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK                               0x00000800
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK                               0x00001000
+
+#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET                                       0x00000000
+#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB                                          13
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB                                          15
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK                                         0x0000e000
+
+#endif
diff --git a/hw/fig/v2/mon_buffer_addr.h b/hw/fig/v2/mon_buffer_addr.h
new file mode 100644
index 000000000000..8cb6f5fd57b9
--- /dev/null
+++ b/hw/fig/v2/mon_buffer_addr.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_BUFFER_ADDR_H_
+#define _MON_BUFFER_ADDR_H_
+
+#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
+
+#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
+
+struct mon_buffer_addr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t dma_length                                              : 12,
+                      reserved_2a                                             :  4,
+                      msdu_continuation                                       :  1,
+                      truncated                                               :  1,
+                      reserved_2b                                             : 14;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reserved_2b                                             : 14,
+                      truncated                                               :  1,
+                      msdu_continuation                                       :  1,
+                      reserved_2a                                             :  4,
+                      dma_length                                              : 12;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET                                0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB                                   0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB                                   31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK                                  0x00000000ffffffff
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET                               0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB                                  32
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB                                  63
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK                                 0xffffffff00000000
+
+#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET                                           0x0000000000000008
+#define MON_BUFFER_ADDR_DMA_LENGTH_LSB                                              0
+#define MON_BUFFER_ADDR_DMA_LENGTH_MSB                                              11
+#define MON_BUFFER_ADDR_DMA_LENGTH_MASK                                             0x0000000000000fff
+
+#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2A_LSB                                             12
+#define MON_BUFFER_ADDR_RESERVED_2A_MSB                                             15
+#define MON_BUFFER_ADDR_RESERVED_2A_MASK                                            0x000000000000f000
+
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET                                    0x0000000000000008
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK                                      0x0000000000010000
+
+#define MON_BUFFER_ADDR_TRUNCATED_OFFSET                                            0x0000000000000008
+#define MON_BUFFER_ADDR_TRUNCATED_LSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MASK                                              0x0000000000020000
+
+#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2B_LSB                                             18
+#define MON_BUFFER_ADDR_RESERVED_2B_MSB                                             31
+#define MON_BUFFER_ADDR_RESERVED_2B_MASK                                            0x00000000fffc0000
+
+#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET                                        0x0000000000000008
+#define MON_BUFFER_ADDR_TLV64_PADDING_LSB                                           32
+#define MON_BUFFER_ADDR_TLV64_PADDING_MSB                                           63
+#define MON_BUFFER_ADDR_TLV64_PADDING_MASK                                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/mon_destination_ring.h b/hw/fig/v2/mon_destination_ring.h
new file mode 100644
index 000000000000..1f373b585fd5
--- /dev/null
+++ b/hw/fig/v2/mon_destination_ring.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DESTINATION_RING_H_
+#define _MON_DESTINATION_RING_H_
+
+#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
+
+struct mon_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t end_offset                                              : 12,
+                      reserved_3a                                             :  2,
+                      link_info                                               :  2,
+                      end_reason                                              :  2,
+                      initiator                                               :  1,
+                      empty_descriptor                                        :  1,
+                      pkt_buffer_cnt                                          :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t looping_count                                           :  4,
+                      pkt_buffer_cnt                                          :  8,
+                      empty_descriptor                                        :  1,
+                      initiator                                               :  1,
+                      end_reason                                              :  2,
+                      link_info                                               :  2,
+                      reserved_3a                                             :  2,
+                      end_offset                                              : 12;
+#endif
+};
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET                         0x00000000
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB                            0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB                            31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK                           0xffffffff
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET                        0x00000004
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB                           0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB                           31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK                          0xffffffff
+
+#define MON_DESTINATION_RING_PPDU_ID_OFFSET                                         0x00000008
+#define MON_DESTINATION_RING_PPDU_ID_LSB                                            0
+#define MON_DESTINATION_RING_PPDU_ID_MSB                                            31
+#define MON_DESTINATION_RING_PPDU_ID_MASK                                           0xffffffff
+
+#define MON_DESTINATION_RING_END_OFFSET_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_OFFSET_LSB                                         0
+#define MON_DESTINATION_RING_END_OFFSET_MSB                                         11
+#define MON_DESTINATION_RING_END_OFFSET_MASK                                        0x00000fff
+
+#define MON_DESTINATION_RING_RESERVED_3A_OFFSET                                     0x0000000c
+#define MON_DESTINATION_RING_RESERVED_3A_LSB                                        12
+#define MON_DESTINATION_RING_RESERVED_3A_MSB                                        13
+#define MON_DESTINATION_RING_RESERVED_3A_MASK                                       0x00003000
+
+#define MON_DESTINATION_RING_LINK_INFO_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_LINK_INFO_LSB                                          14
+#define MON_DESTINATION_RING_LINK_INFO_MSB                                          15
+#define MON_DESTINATION_RING_LINK_INFO_MASK                                         0x0000c000
+
+#define MON_DESTINATION_RING_END_REASON_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_REASON_LSB                                         16
+#define MON_DESTINATION_RING_END_REASON_MSB                                         17
+#define MON_DESTINATION_RING_END_REASON_MASK                                        0x00030000
+
+#define MON_DESTINATION_RING_INITIATOR_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_INITIATOR_LSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MASK                                         0x00040000
+
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET                                0x0000000c
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK                                  0x00080000
+
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET                                  0x0000000c
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB                                     20
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB                                     27
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK                                    0x0ff00000
+
+#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000000c
+#define MON_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define MON_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define MON_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/fig/v2/mon_drop.h b/hw/fig/v2/mon_drop.h
new file mode 100644
index 000000000000..d1135ecd0dc2
--- /dev/null
+++ b/hw/fig/v2/mon_drop.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DROP_H_
+#define _MON_DROP_H_
+
+#define NUM_OF_DWORDS_MON_DROP 2
+
+#define NUM_OF_QWORDS_MON_DROP 1
+
+struct mon_drop {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t ppdu_drop_cnt                                           : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      tlv_drop_cnt                                            : 10,
+                      end_of_ppdu_seen                                        :  1,
+                      reserved_1a                                             :  1;
+#else
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t reserved_1a                                             :  1,
+                      end_of_ppdu_seen                                        :  1,
+                      tlv_drop_cnt                                            : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      ppdu_drop_cnt                                           : 10;
+#endif
+};
+
+#define MON_DROP_PPDU_ID_OFFSET                                                     0x0000000000000000
+#define MON_DROP_PPDU_ID_LSB                                                        0
+#define MON_DROP_PPDU_ID_MSB                                                        31
+#define MON_DROP_PPDU_ID_MASK                                                       0x00000000ffffffff
+
+#define MON_DROP_PPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_PPDU_DROP_CNT_LSB                                                  32
+#define MON_DROP_PPDU_DROP_CNT_MSB                                                  41
+#define MON_DROP_PPDU_DROP_CNT_MASK                                                 0x000003ff00000000
+
+#define MON_DROP_MPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_MPDU_DROP_CNT_LSB                                                  42
+#define MON_DROP_MPDU_DROP_CNT_MSB                                                  51
+#define MON_DROP_MPDU_DROP_CNT_MASK                                                 0x000ffc0000000000
+
+#define MON_DROP_TLV_DROP_CNT_OFFSET                                                0x0000000000000000
+#define MON_DROP_TLV_DROP_CNT_LSB                                                   52
+#define MON_DROP_TLV_DROP_CNT_MSB                                                   61
+#define MON_DROP_TLV_DROP_CNT_MASK                                                  0x3ff0000000000000
+
+#define MON_DROP_END_OF_PPDU_SEEN_OFFSET                                            0x0000000000000000
+#define MON_DROP_END_OF_PPDU_SEEN_LSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MASK                                              0x4000000000000000
+
+#define MON_DROP_RESERVED_1A_OFFSET                                                 0x0000000000000000
+#define MON_DROP_RESERVED_1A_LSB                                                    63
+#define MON_DROP_RESERVED_1A_MSB                                                    63
+#define MON_DROP_RESERVED_1A_MASK                                                   0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/mon_ingress_ring.h b/hw/fig/v2/mon_ingress_ring.h
new file mode 100644
index 000000000000..76f4e80417e0
--- /dev/null
+++ b/hw/fig/v2/mon_ingress_ring.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_INGRESS_RING_H_
+#define _MON_INGRESS_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_MON_INGRESS_RING 4
+
+struct mon_ingress_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#endif
+};
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB              0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB             0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB             7
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB         8
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB         11
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB              12
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET                               0x00000008
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB                                  0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB                                  31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK                                 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET                              0x0000000c
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB                                 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB                                 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK                                0xffffffff
+
+#endif
diff --git a/hw/fig/v2/msmhwiobase.h b/hw/fig/v2/msmhwiobase.h
new file mode 100644
index 000000000000..f7620cef5599
--- /dev/null
+++ b/hw/fig/v2/msmhwiobase.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define SOC_WFSS_CE_REG_BASE                                        0x01b80000
+#define SOC_WFSS_CE_REG_BASE_SIZE                                   0x0001c000
+#define SOC_WFSS_CE_REG_BASE_PHYS                                   0x01b80000
+#endif
diff --git a/hw/fig/v2/msmhwioreg.h b/hw/fig/v2/msmhwioreg.h
new file mode 100644
index 000000000000..881c73e30f58
--- /dev/null
+++ b/hw/fig/v2/msmhwioreg.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef __MSMHWIOREG_H__
+#define __MSMHWIOREG_H__
+
+#include "msmhwiobase.h"
+
+#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
+#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
+
+
+#endif
diff --git a/hw/fig/v2/no_ack_report.h b/hw/fig/v2/no_ack_report.h
new file mode 100644
index 000000000000..5f9660801de6
--- /dev/null
+++ b/hw/fig/v2/no_ack_report.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_ack_transmit_reason                                  :  4,
+                      macrx_abort_reason                                      :  4,
+                      phyrx_abort_reason                                      :  8,
+                      frame_control                                           : 16;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      sr_ppdu_during_obss                                     :  1,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      reserved_1                                              :  3;
+             uint32_t pre_bt_broadcast_status_details                         : 12,
+                      first_bt_broadcast_status_details                       : 12,
+                      reserved_2                                              :  8;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_3                                              : 20;
+#else
+             uint32_t frame_control                                           : 16,
+                      phyrx_abort_reason                                      :  8,
+                      macrx_abort_reason                                      :  4,
+                      no_ack_transmit_reason                                  :  4;
+             uint32_t reserved_1                                              :  3,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      sr_ppdu_during_obss                                     :  1,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t reserved_2                                              :  8,
+                      first_bt_broadcast_status_details                       : 12,
+                      pre_bt_broadcast_status_details                         : 12;
+             uint32_t reserved_3                                              : 20,
+                      second_bt_broadcast_status_details                      : 12;
+#endif
+};
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET                                 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB                                    0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB                                    3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK                                   0x0000000f
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB                                        4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB                                        7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK                                       0x000000f0
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB                                        8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB                                        15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK                                       0x0000ff00
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET                                          0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB                                             16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB                                             31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK                                            0xffff0000
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET                                       0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB                                          0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB                                          23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK                                         0x00ffffff
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET                                    0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK                                      0x01000000
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET                     0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB                        25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB                        28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK                       0x1e000000
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET                                             0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB                                                29
+#define NO_ACK_REPORT_RESERVED_1_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_1_MASK                                               0xe0000000
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                        0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                           0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                           11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                          0x00000fff
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                      0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                         12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                         23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                        0x00fff000
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET                                             0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB                                                24
+#define NO_ACK_REPORT_RESERVED_2_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_2_MASK                                               0xff000000
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET                     0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                        0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                        11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                       0x00000fff
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET                                             0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB                                                12
+#define NO_ACK_REPORT_RESERVED_3_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_3_MASK                                               0xfffff000
+
+#endif
diff --git a/hw/fig/v2/ofdma_trigger_details.h b/hw/fig/v2/ofdma_trigger_details.h
new file mode 100644
index 000000000000..d1e667c885d4
--- /dev/null
+++ b/hw/fig/v2/ofdma_trigger_details.h
@@ -0,0 +1,944 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _OFDMA_TRIGGER_DETAILS_H_
+#define _OFDMA_TRIGGER_DETAILS_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26
+
+#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13
+
+struct ofdma_trigger_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ax_trigger_source                                       :  1,
+                      rx_trigger_frame_user_source                            :  2,
+                      received_bandwidth                                      :  3,
+                      txop_duration_all_ones                                  :  1,
+                      eht_trigger_response                                    :  1,
+                      pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      rxpcu_pcie_l0_req_duration                              :  8;
+             uint32_t he_trigger_ul_ppdu_length                               :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_reserved                                     :  1,
+                      bss_color                                               :  6;
+             uint32_t trigger_type                                            :  4,
+                      lsig_response_length                                    : 12,
+                      cascade_indication                                      :  1,
+                      carrier_sense                                           :  1,
+                      bandwidth                                               :  2,
+                      cp_ltf_size                                             :  2,
+                      mu_mimo_ltf_mode                                        :  1,
+                      number_of_ltfs                                          :  3,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ap_tx_power_lsb_part                                    :  4;
+             uint32_t ap_tx_power_msb_part                                    :  2,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      spatial_reuse                                           : 16,
+                      doppler                                                 :  1,
+                      he_siga_reserved                                        :  9,
+                      reserved_3b                                             :  1;
+             uint32_t aid12                                                   : 12,
+                      ru_allocation                                           :  9,
+                      mcs                                                     :  4,
+                      dcm                                                     :  1,
+                      start_spatial_stream                                    :  3,
+                      number_of_spatial_stream                                :  3;
+             uint32_t target_rssi                                             :  7,
+                      coding_type                                             :  1,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      tid_aggregation_limit                                   :  3,
+                      reserved_5b                                             :  1,
+                      prefered_ac                                             :  2,
+                      bar_control_ack_policy                                  :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_reserved                                    :  9,
+                      bar_control_tid_info                                    :  4;
+             uint32_t nr0_per_tid_info_reserved                               : 12,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr1_per_tid_info_reserved                               : 12,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr2_per_tid_info_reserved                               : 12,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr3_per_tid_info_reserved                               : 12,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr4_per_tid_info_reserved                               : 12,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr5_per_tid_info_reserved                               : 12,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr6_per_tid_info_reserved                               : 12,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr7_per_tid_info_reserved                               : 12,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t fb_segment_retransmission_bitmap                        :  8,
+                      reserved_14a                                            :  2,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_duration_field                                       : 16,
+                      scrambler_seed                                          :  7,
+                      rx_chain_mask_type                                      :  1;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t sw_peer_id                                              : 16,
+                      response_tx_duration                                    : 16;
+             uint32_t __reserved_g_0022_trigger_subtype                                 :  4,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      reserved_18a                                            :  1,
+                      qos_null_only_response_tx                               :  1;
+             uint32_t tbr_trigger_sound_sac                                   : 16,
+                      reserved_19a                                            :  8,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19b                                            :  3;
+             uint32_t eht_special_aid12                                       : 12,
+                      phy_version                                             :  3,
+                      bandwidth_ext                                           :  2,
+                      eht_spatial_reuse                                       :  8,
+                      u_sig_reserved1                                         :  7;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t __reserved_g_0035                                                 :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      blackout_details_en                                     :  1,
+                      uhr_trig_response                                       :  1,
+                      mcs_ext                                                 :  1,
+                      dso_primary20_index_select                              :  4,
+                      dso_icf_reception                                       :  1,
+                      dru_spreading_bw                                        :  2,
+                      dru_indication_per_80mhz                                :  4,
+                      coding_type_ext                                         :  1,
+                      pad_duration                                            :  5,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_22a                                            :  6;
+             uint32_t dso_cca_puncture_pattern                                : 16,
+                      dso_freq_subband_channel_bonding_mask                   : 16;
+             uint32_t __reserved_g_0017                                       :  1,
+                      enable_steering                                         :  1,
+                      q2q_mba                                                 :  1,
+                      reserved_24a                                            : 29;
+             uint32_t reserved_25a                                            : 32;
+#else
+             uint32_t rxpcu_pcie_l0_req_duration                              :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8,
+                      eht_trigger_response                                    :  1,
+                      txop_duration_all_ones                                  :  1,
+                      received_bandwidth                                      :  3,
+                      rx_trigger_frame_user_source                            :  2,
+                      ax_trigger_source                                       :  1;
+             uint32_t bss_color                                               :  6,
+                      he_trigger_reserved                                     :  1,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_ul_ppdu_length                               :  5;
+             uint32_t ap_tx_power_lsb_part                                    :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      number_of_ltfs                                          :  3,
+                      mu_mimo_ltf_mode                                        :  1,
+                      cp_ltf_size                                             :  2,
+                      bandwidth                                               :  2,
+                      carrier_sense                                           :  1,
+                      cascade_indication                                      :  1,
+                      lsig_response_length                                    : 12,
+                      trigger_type                                            :  4;
+             uint32_t reserved_3b                                             :  1,
+                      he_siga_reserved                                        :  9,
+                      doppler                                                 :  1,
+                      spatial_reuse                                           : 16,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      ap_tx_power_msb_part                                    :  2;
+             uint32_t number_of_spatial_stream                                :  3,
+                      start_spatial_stream                                    :  3,
+                      dcm                                                     :  1,
+                      mcs                                                     :  4,
+                      ru_allocation                                           :  9,
+                      aid12                                                   : 12;
+             uint32_t bar_control_tid_info                                    :  4,
+                      bar_control_reserved                                    :  9,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_ack_policy                                  :  1,
+                      prefered_ac                                             :  2,
+                      reserved_5b                                             :  1,
+                      tid_aggregation_limit                                   :  3,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      coding_type                                             :  1,
+                      target_rssi                                             :  7;
+             uint32_t nr0_start_seq_ctrl_start_seq_number                     : 12,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_per_tid_info_reserved                               : 12;
+             uint32_t nr1_start_seq_ctrl_start_seq_number                     : 12,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_per_tid_info_reserved                               : 12;
+             uint32_t nr2_start_seq_ctrl_start_seq_number                     : 12,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_per_tid_info_reserved                               : 12;
+             uint32_t nr3_start_seq_ctrl_start_seq_number                     : 12,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_per_tid_info_reserved                               : 12;
+             uint32_t nr4_start_seq_ctrl_start_seq_number                     : 12,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_per_tid_info_reserved                               : 12;
+             uint32_t nr5_start_seq_ctrl_start_seq_number                     : 12,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_per_tid_info_reserved                               : 12;
+             uint32_t nr6_start_seq_ctrl_start_seq_number                     : 12,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_per_tid_info_reserved                               : 12;
+             uint32_t nr7_start_seq_ctrl_start_seq_number                     : 12,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_per_tid_info_reserved                               : 12;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_14a                                            :  2,
+                      fb_segment_retransmission_bitmap                        :  8;
+             uint32_t rx_chain_mask_type                                      :  1,
+                      scrambler_seed                                          :  7,
+                      rx_duration_field                                       : 16,
+                      rx_chain_mask                                           :  8;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t response_tx_duration                                    : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t qos_null_only_response_tx                               :  1,
+                      reserved_18a                                            :  1,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      __reserved_g_0022_trigger_subtype                                 :  4;
+             uint32_t reserved_19b                                            :  3,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19a                                            :  8,
+                      tbr_trigger_sound_sac                                   : 16;
+             uint32_t u_sig_reserved1                                         :  7,
+                      eht_spatial_reuse                                       :  8,
+                      bandwidth_ext                                           :  2,
+                      phy_version                                             :  3,
+                      eht_special_aid12                                       : 12;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t reserved_22a                                            :  6,
+                      ects_as_tb_ppdu                                         :  1,
+                      pad_duration                                            :  5,
+                      coding_type_ext                                         :  1,
+                      dru_indication_per_80mhz                                :  4,
+                      dru_spreading_bw                                        :  2,
+                      dso_icf_reception                                       :  1,
+                      dso_primary20_index_select                              :  4,
+                      mcs_ext                                                 :  1,
+                      uhr_trig_response                                       :  1,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      __reserved_g_0035                                                 :  1;
+             uint32_t dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_cca_puncture_pattern                                : 16;
+             uint32_t reserved_24a                                            : 29,
+                      q2q_mba                                                 :  1,
+                      enable_steering                                         :  1,
+                      __reserved_g_0017                                       :  1;
+             uint32_t reserved_25a                                            : 32;
+#endif
+};
+
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK                                0x0000000000000001
+
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET                   0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB                      1
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB                      2
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK                     0x0000000000000006
+
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET                             0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB                                3
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB                                5
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK                               0x0000000000000038
+
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK                           0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET                           0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK                             0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET                                  0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB                                     8
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB                                     15
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK                                    0x000000000000ff00
+
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB                                         16
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB                                         23
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK                                        0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET                     0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB                        24
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB                        31
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK                       0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB                         36
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK                        0x0000001f00000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET                       0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB                          37
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB                          44
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK                         0x00001fe000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB                            45
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB                            49
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK                           0x0003e00000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB                         50
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB                         54
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK                        0x007c000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB                                 55
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB                                 56
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK                                0x0180000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET                            0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK                              0x0200000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB                                         58
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB                                         63
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK                                        0xfc00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET                                   0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB                                      0
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB                                      3
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK                                     0x000000000000000f
+
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB                              4
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB                              15
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK                             0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET                             0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK                               0x0000000000010000
+
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK                                    0x0000000000020000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET                                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB                                         18
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB                                         19
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK                                        0x00000000000c0000
+
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB                                       20
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB                                       21
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK                                      0x0000000000300000
+
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK                                 0x0000000000400000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET                                 0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB                                    23
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB                                    25
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK                                   0x0000000003800000
+
+#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET                                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_STBC_LSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MASK                                             0x0000000004000000
+
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET                              0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK                                0x0000000008000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB                              28
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK                             0x00000000f0000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB                              32
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB                              33
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK                             0x0000000300000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB                         34
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB                         35
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK                        0x0000000c00000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                 0x0000001000000000
+
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB                                     37
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB                                     52
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK                                    0x001fffe000000000
+
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET                                        0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK                                          0x0020000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB                                  54
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB                                  62
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK                                 0x7fc0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK                                      0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET                                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_AID12_LSB                                             0
+#define OFDMA_TRIGGER_DETAILS_AID12_MSB                                             11
+#define OFDMA_TRIGGER_DETAILS_AID12_MASK                                            0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET                                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB                                     12
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB                                     20
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK                                    0x00000000001ff000
+
+#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MCS_LSB                                               21
+#define OFDMA_TRIGGER_DETAILS_MCS_MSB                                               24
+#define OFDMA_TRIGGER_DETAILS_MCS_MASK                                              0x0000000001e00000
+
+#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_DCM_LSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MASK                                              0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB                              26
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB                              28
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK                             0x000000001c000000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET                       0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB                          29
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB                          31
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK                         0x00000000e0000000
+
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB                                       32
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB                                       38
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK                                      0x0000007f00000000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK                                      0x0000008000000000
+
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB                            40
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB                            41
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK                           0x0000030000000000
+
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB                             42
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB                             44
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK                            0x00001c0000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK                                      0x0000200000000000
+
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB                                       46
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB                                       47
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK                                      0x0000c00000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK                           0x0001000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK                            0x0002000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK                    0x0004000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB                              51
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB                              59
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK                             0x0ff8000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB                              60
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK                             0xf000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET               0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB                  0
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB                  7
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK                 0x00000000000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET                                   0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB                                      8
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB                                      9
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK                                     0x0000000000000300
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                   10
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                   15
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                  0x000000000000fc00
+
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET                        0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB                           16
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB                           31
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK                          0x00000000ffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET                                  0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB                                     32
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB                                     39
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK                                    0x000000ff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET                              0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB                                 40
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB                                 55
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK                                0x00ffff0000000000
+
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET                                 0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB                                    56
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB                                    62
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK                                   0x7f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET                             0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK                               0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET          0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB             0
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB             9
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK            0x00000000000003ff
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK         0x0000000000000400
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK      0x0000000000000800
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK      0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET              0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB                 13
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB                 15
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK                0x000000000000e000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET                       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB                          16
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB                          23
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK                         0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB                              24
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK                             0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET                                     0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB                                        32
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB                                        47
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK                                       0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB                              48
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK                             0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET                  0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB                     4
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB                     15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK                    0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB                  16
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB                  24
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK                 0x0000000001ff0000
+
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET                                        0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB                                           25
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB                                           27
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK                                          0x000000000e000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB                  28
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB                  29
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK                 0x0000000030000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK                                     0x0000000040000000
+
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET                      0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK                        0x0000000080000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET                          0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB                             32
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB                             47
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK                            0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB                                      48
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB                                      55
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK                                     0x00ff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET                                0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB                                   56
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB                                   60
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK                                  0x1f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB                                      61
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK                                     0xe000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB                                 11
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK                                0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET                                    0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB                                       12
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB                                       14
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK                                      0x0000000000007000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET                                  0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB                                     15
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB                                     16
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK                                    0x0000000000018000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB                                 17
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB                                 24
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK                                0x0000000001fe0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET                                0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB                                   31
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK                                  0x00000000fe000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET            0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB               32
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB               63
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK              0xffffffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET                            0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK                              0x0000000000000020
+
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK                                0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET                                        0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK                                          0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET                     0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB                        8
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB                        11
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK                       0x0000000000000f00
+
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK                                0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET                               0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB                                  13
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB                                  14
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK                                 0x0000000000006000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB                          15
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB                          18
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK                         0x0000000000078000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK                                  0x0000000000080000
+
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB                                      20
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB                                      24
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK                                     0x0000000001f00000
+
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK                                  0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB                                      26
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK                                     0x00000000fc000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB                          32
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB                          47
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK                         0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET          0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB             48
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB             63
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK            0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET                                0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB                                   1
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB                                   1
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK                                  0x0000000000000002
+
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET                                        0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB                                           2
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB                                           2
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK                                          0x0000000000000004
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB                                      3
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK                                     0x00000000fffffff8
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB                                      32
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/pcu_ppdu_setup_init.h b/hw/fig/v2/pcu_ppdu_setup_init.h
new file mode 100644
index 000000000000..f623a25ba4d4
--- /dev/null
+++ b/hw/fig/v2/pcu_ppdu_setup_init.h
@@ -0,0 +1,2316 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PCU_PPDU_SETUP_INIT_H_
+#define _PCU_PPDU_SETUP_INIT_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58
+
+#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29
+
+struct pcu_ppdu_setup_init {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t medium_prot_type                                        :  3,
+                      response_type                                           :  5,
+                      response_info_part2_required                            :  1,
+                      response_to_response                                    :  3,
+                      mba_user_order                                          :  2,
+                      expected_mba_size                                       : 11,
+                      required_ul_mu_resp_user_count                          :  6,
+                      transmitted_bssid_check_en                              :  1;
+             uint32_t mprot_required_bw1                                      :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw320                                    :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      update_timestamp_64                                     :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_32_upper                               :  1,
+                      reserved_1a                                             : 13;
+             uint32_t insert_timestamp_offset_0                               : 16,
+                      insert_timestamp_offset_1                               : 16;
+             uint32_t max_bw40_try_count                                      :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw320_try_count                                     :  4,
+                      insert_wur_timestamp_offset                             :  6,
+                      update_wur_timestamp                                    :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      insert_wur_fcs                                          :  1,
+                      q2q_trigger                                             :  1,
+                      reserved_3b                                             :  2;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_hw_response_tx_duration                             : 16,
+                      r2r_rx_duration_field                                   : 16;
+             uint32_t r2r_group_id                                            :  6,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_sta_partial_aid                                     : 11,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_set_required_response_time                          :  1,
+                      reserved_29a                                            :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      r2r_bw40_active_channel                                 :  3;
+             uint32_t r2r_bw80_active_channel                                 :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw320                                               :  3,
+                      tx_with_blackout_details                                :  1,
+                      expect_rx_with_blackout_details                         :  1;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t mu_response_expected_bitmap_36_32                       :  5,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_expected_response_sta_count                          :  6,
+                      transmit_includes_multidestination                      :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      insert_current_tx_start_timing_info                     :  1,
+                      tx_start_transmit_time_byte_offset                      : 12;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad1_47_32                              : 16,
+                      protection_frame_ad2_15_0                               : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t dynamic_medium_prot_threshold                           : 24,
+                      dynamic_medium_prot_type                                :  1,
+                      reserved_54a                                            :  7;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad3_47_32                              : 16,
+                      protection_frame_ad4_15_0                               : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#else
+             uint32_t transmitted_bssid_check_en                              :  1,
+                      required_ul_mu_resp_user_count                          :  6,
+                      expected_mba_size                                       : 11,
+                      mba_user_order                                          :  2,
+                      response_to_response                                    :  3,
+                      response_info_part2_required                            :  1,
+                      response_type                                           :  5,
+                      medium_prot_type                                        :  3;
+             uint32_t reserved_1a                                             : 13,
+                      update_timestamp_32_upper                               :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_64                                     :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      mprot_required_bw320                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw1                                      :  1;
+             uint32_t insert_timestamp_offset_1                               : 16,
+                      insert_timestamp_offset_0                               : 16;
+             uint32_t reserved_3b                                             :  2,
+                      q2q_trigger                                             :  1,
+                      insert_wur_fcs                                          :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      update_wur_timestamp                                    :  1,
+                      insert_wur_timestamp_offset                             :  6,
+                      max_bw320_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw40_try_count                                      :  4;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_rx_duration_field                                   : 16,
+                      r2r_hw_response_tx_duration                             : 16;
+             uint32_t r2r_bw40_active_channel                                 :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      reserved_29a                                            :  3,
+                      r2r_set_required_response_time                          :  1,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_sta_partial_aid                                     : 11,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_group_id                                            :  6;
+             uint32_t expect_rx_with_blackout_details                         :  1,
+                      tx_with_blackout_details                                :  1,
+                      r2r_bw320                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw80_active_channel                                 :  3;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t tx_start_transmit_time_byte_offset                      : 12,
+                      insert_current_tx_start_timing_info                     :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      transmit_includes_multidestination                      :  1,
+                      mu_expected_response_sta_count                          :  6,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_response_expected_bitmap_36_32                       :  5;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad2_15_0                               : 16,
+                      protection_frame_ad1_47_32                              : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t reserved_54a                                            :  7,
+                      dynamic_medium_prot_type                                :  1,
+                      dynamic_medium_prot_threshold                           : 24;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad4_15_0                               : 16,
+                      protection_frame_ad3_47_32                              : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#endif
+};
+
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB                                    0
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB                                    2
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK                                   0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET                                    0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB                                       3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB                                       7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK                                      0x00000000000000f8
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK                       0x0000000000000100
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB                                9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB                                11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK                               0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB                                      12
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB                                      13
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK                                     0x0000000000003000
+
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB                                   14
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB                                   24
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK                                  0x0000000001ffc000
+
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB                      25
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB                      30
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK                     0x000000007e000000
+
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET                       0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK                         0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK                                 0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK                                0x0000000200000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK                                0x0000000400000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK                                0x0000000800000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK                               0x0000001000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK                               0x0000002000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK                               0x0000004000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK                                   0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK                                  0x0000010000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK                                  0x0000020000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK                                  0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK                                 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK                                 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK                                 0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK                                     0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK                       0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK                                0x0001000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK                          0x0002000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK                          0x0004000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB                                         51
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK                                        0xfff8000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB                           15
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK                          0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB                           16
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB                           31
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB                                  35
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK                                 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB                                  36
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB                                  39
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK                                 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB                                 40
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB                                 43
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK                                0x00000f0000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB                                 44
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB                                 47
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK                                0x0000f00000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB                                 51
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK                                0x000f000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB                         52
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB                         57
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK                        0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET                             0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK                               0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET                       0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK                         0x0800000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET                                   0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK                                     0x1000000000000000
+
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET                                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB                                         61
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB                                         61
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK                                        0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET                                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB                                         62
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK                                        0xc000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET  0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET     0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET    0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET   0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET      0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET       0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET       0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET  0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET     0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB        57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB        60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK       0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET    0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK      0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK           0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK           0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK     0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET      0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK        0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK         0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET  0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB     35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK    0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET          0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB             36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB             38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK            0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK     0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB          40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB          47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK         0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB      48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB      55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK     0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB    4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK   0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB     5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK    0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET          0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK            0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB        14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK       0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK       0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK   0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK    0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB  50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB  52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB     59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB     63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK    0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK    0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK  0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK    0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET  0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET     0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET    0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET   0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET      0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET       0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET       0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET    0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET   0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET     0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET         0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET         0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET    0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK      0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET   0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK     0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK          0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK          0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET  0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK    0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET     0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB        50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK       0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET      0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB         59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB         61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK        0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK   0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK           0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK    0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET      0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK        0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK    0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB   32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB   36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK  0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB    37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB    39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK   0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB            40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB            41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK           0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB       42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB       46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK      0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB       48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB       55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK      0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK   0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK   0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK   0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB  43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB  45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB    52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB    57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK   0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET    0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET   0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET     0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET         0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET         0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET                      0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB                         0
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB                         15
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK                        0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET                            0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB                               16
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB                               31
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK                              0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB                                        32
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB                                        37
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK                                       0x0000003f00000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB                             38
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB                             41
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK                            0x000003c000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET                              0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB                                 42
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB                                 52
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK                                0x001ffc0000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET                0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK                  0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET                   0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK                     0x0040000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB                                        55
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB                                        57
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK                                       0x0380000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB                             58
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB                             60
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK                            0x1c00000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB                             61
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB                             63
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK                            0xe000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET                          0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB                             0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB                             2
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK                            0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB                            3
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB                            5
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK                           0x0000000000000038
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB                            6
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB                            8
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK                           0x00000000000001c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB                            9
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB                            11
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK                           0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB                                            12
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB                                            14
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK                                           0x0000000000007000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB                                            15
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB                                            17
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK                                           0x0000000000038000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB                                            18
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB                                            20
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK                                           0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB                                           21
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB                                           23
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK                                          0x0000000000e00000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB                                           24
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB                                           26
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK                                          0x0000000007000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB                                           27
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB                                           29
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK                                          0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK                           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                  0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                    0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET                 0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB                    32
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB                    63
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK                   0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET                0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB                   0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB                   4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK                  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB                      5
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB                      10
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK                     0x00000000000007e0
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB                      11
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB                      16
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK                     0x000000000001f800
+
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK                 0x0000000000020000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET                 0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK                   0x0000000000040000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET              0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK                0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB                  20
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB                  31
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK                 0x00000000fff00000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET                        0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET                        0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK                         0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET                    0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB                       0
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB                       23
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK                      0x0000000000ffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET                         0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK                           0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET                                     0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB                                        25
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB                                        31
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK                                       0x00000000fe000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET                        0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET                        0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK                         0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/pdg_response.h b/hw/fig/v2/pdg_response.h
new file mode 100644
index 000000000000..d94c69ff2645
--- /dev/null
+++ b/hw/fig/v2/pdg_response.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_H_
+#define _PDG_RESPONSE_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE 14
+
+#define NUM_OF_QWORDS_PDG_RESPONSE 7
+
+struct pdg_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t hw_response_tx_duration                                 : 16,
+                      rx_duration_field                                       : 16;
+             uint32_t punctured_response_transmission                         :  1,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      scrambler_seed_override                                 :  2,
+                      response_density_valid                                  :  1,
+                      response_density                                        :  5,
+                      more_data                                               :  1,
+                      duration_indication                                     :  1,
+                      blackout_details_en                                     :  1,
+                      cfp_protected_resp                                      :  1,
+                      bandwidth                                               :  3;
+             uint32_t ack_id                                                  : 16,
+                      block_ack_bitmap                                        : 16;
+             uint32_t response_frame_type                                     :  4,
+                      ack_id_ext                                              : 10,
+                      ftm_en                                                  :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 11;
+             uint32_t ndp_ba_start_seq_ctrl                                   : 12,
+                      active_channel                                          :  3,
+                      txop_duration_all_ones                                  :  1,
+                      frame_length                                            : 16;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      q2q_mba                                                 :  1,
+                      reserved_12a                                            :  6;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t rx_duration_field                                       : 16,
+                      hw_response_tx_duration                                 : 16;
+             uint32_t bandwidth                                               :  3,
+                      cfp_protected_resp                                      :  1,
+                      blackout_details_en                                     :  1,
+                      duration_indication                                     :  1,
+                      more_data                                               :  1,
+                      response_density                                        :  5,
+                      response_density_valid                                  :  1,
+                      scrambler_seed_override                                 :  2,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      punctured_response_transmission                         :  1;
+             uint32_t block_ack_bitmap                                        : 16,
+                      ack_id                                                  : 16;
+             uint32_t sta_partial_aid                                         : 11,
+                      group_id                                                :  6,
+                      ftm_en                                                  :  1,
+                      ack_id_ext                                              : 10,
+                      response_frame_type                                     :  4;
+             uint32_t frame_length                                            : 16,
+                      txop_duration_all_ones                                  :  1,
+                      active_channel                                          :  3,
+                      ndp_ba_start_seq_ctrl                                   : 12;
+             uint32_t reserved_12a                                            :  6,
+                      q2q_mba                                                 :  1,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET                       0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB               1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB               24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK              0x0000000001fffffe
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET                          0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB                             25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB                             28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK                            0x000000001e000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET                         0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK                           0x0000000020000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK                                0x0000000040000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK                                0x0000000080000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET                        0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB                           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB                           39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK                          0x000000ff00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET                    0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB                       40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB                       47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK                      0x0000ff0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET                           0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB                              48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB                              50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK                             0x0007000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB                    51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB                    58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK                   0x07f8000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET                            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB                               59
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB                               61
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK                              0x3800000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK                   0x4000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET                0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK                  0x8000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB                          3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK                         0x000000000000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB                                  4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB                                  6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK                                 0x0000000000000070
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK                          0x0000000000000080
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET                            0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB                               8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB                               15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK                              0x000000000000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB                           16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB                           23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK                          0x0000000000ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET                     0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB                        24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB                        31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK                       0x00000000ff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB                         32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB                         36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK                        0x0000001f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB                          37
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB                          39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK                         0x000000e000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB                                  40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB                                  41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK                                 0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB                             42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB                             46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK                            0x00007c0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET                  0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK                    0x0000800000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB                             48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB                             55
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK                            0x00ff000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB                         56
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB                         63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK                        0xff00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB                 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB                 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK                0x000000000000007e
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET             0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB                7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB                10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK               0x0000000000000780
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB                  11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB                  12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK                 0x0000000000001800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK                         0x0000000000002000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK          0x0000000000004000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK                 0x0000000000008000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET      0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB         16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB         17
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK        0x0000000000030000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET                    0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB                       18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB                       20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK                      0x00000000001c0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK                  0x0000000000200000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB                  22
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB                  23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK                 0x0000000000c00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK                0x0000000001000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET           0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK             0x0000000002000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK                  0x0000000004000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB                          27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB                          31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK                         0x00000000f8000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB           35
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK          0x0000000f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB                  36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB                  39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK                 0x000000f000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB                   40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB                   41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK                  0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK                         0x0000040000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET                     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB                        43
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB                        45
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK                       0x0000380000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET                   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB                      46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB                      50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK                     0x0007c00000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK       0x0008000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB                          52
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB                          57
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK                         0x03f0000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB      58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB      63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK     0xfc00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB    13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB    15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK   0x000000000000e000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET            0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB               16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB               27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK              0x000000000fff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET        0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB           28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB           31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK          0x00000000f0000000
+
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET                                 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB                                    32
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB                                    47
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK                                   0x0000ffff00000000
+
+#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET                                       0x0000000000000018
+#define PDG_RESPONSE_RX_DURATION_FIELD_LSB                                          48
+#define PDG_RESPONSE_RX_DURATION_FIELD_MSB                                          63
+#define PDG_RESPONSE_RX_DURATION_FIELD_MASK                                         0xffff000000000000
+
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET                         0x0000000000000020
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK                           0x0000000000000001
+
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                        0x0000000000000020
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB                           1
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB                           16
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK                          0x000000000001fffe
+
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET                                 0x0000000000000020
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB                                    17
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB                                    18
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK                                   0x0000000000060000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET                                  0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK                                    0x0000000000080000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_LSB                                           20
+#define PDG_RESPONSE_RESPONSE_DENSITY_MSB                                           24
+#define PDG_RESPONSE_RESPONSE_DENSITY_MASK                                          0x0000000001f00000
+
+#define PDG_RESPONSE_MORE_DATA_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_MORE_DATA_LSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MASK                                                 0x0000000002000000
+
+#define PDG_RESPONSE_DURATION_INDICATION_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_DURATION_INDICATION_LSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MASK                                       0x0000000004000000
+
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK                                       0x0000000008000000
+
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET                                      0x0000000000000020
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB                                         28
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB                                         28
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK                                        0x0000000010000000
+
+#define PDG_RESPONSE_BANDWIDTH_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_BANDWIDTH_LSB                                                  29
+#define PDG_RESPONSE_BANDWIDTH_MSB                                                  31
+#define PDG_RESPONSE_BANDWIDTH_MASK                                                 0x00000000e0000000
+
+#define PDG_RESPONSE_ACK_ID_OFFSET                                                  0x0000000000000020
+#define PDG_RESPONSE_ACK_ID_LSB                                                     32
+#define PDG_RESPONSE_ACK_ID_MSB                                                     47
+#define PDG_RESPONSE_ACK_ID_MASK                                                    0x0000ffff00000000
+
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB                                           48
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB                                           63
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK                                          0xffff000000000000
+
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET                                     0x0000000000000028
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB                                        0
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB                                        3
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK                                       0x000000000000000f
+
+#define PDG_RESPONSE_ACK_ID_EXT_OFFSET                                              0x0000000000000028
+#define PDG_RESPONSE_ACK_ID_EXT_LSB                                                 4
+#define PDG_RESPONSE_ACK_ID_EXT_MSB                                                 13
+#define PDG_RESPONSE_ACK_ID_EXT_MASK                                                0x0000000000003ff0
+
+#define PDG_RESPONSE_FTM_EN_OFFSET                                                  0x0000000000000028
+#define PDG_RESPONSE_FTM_EN_LSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MASK                                                    0x0000000000004000
+
+#define PDG_RESPONSE_GROUP_ID_OFFSET                                                0x0000000000000028
+#define PDG_RESPONSE_GROUP_ID_LSB                                                   15
+#define PDG_RESPONSE_GROUP_ID_MSB                                                   20
+#define PDG_RESPONSE_GROUP_ID_MASK                                                  0x00000000001f8000
+
+#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET                                         0x0000000000000028
+#define PDG_RESPONSE_STA_PARTIAL_AID_LSB                                            21
+#define PDG_RESPONSE_STA_PARTIAL_AID_MSB                                            31
+#define PDG_RESPONSE_STA_PARTIAL_AID_MASK                                           0x00000000ffe00000
+
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET                                   0x0000000000000028
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB                                      32
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB                                      43
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK                                     0x00000fff00000000
+
+#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET                                          0x0000000000000028
+#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB                                             44
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB                                             46
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK                                            0x0000700000000000
+
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET                                  0x0000000000000028
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK                                    0x0000800000000000
+
+#define PDG_RESPONSE_FRAME_LENGTH_OFFSET                                            0x0000000000000028
+#define PDG_RESPONSE_FRAME_LENGTH_LSB                                               48
+#define PDG_RESPONSE_FRAME_LENGTH_MSB                                               63
+#define PDG_RESPONSE_FRAME_LENGTH_MASK                                              0xffff000000000000
+
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET                              0x0000000000000030
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB                                 0
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB                                 3
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK                                0x000000000000000f
+
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                   0x0000000000000030
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB                      4
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB                      19
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK                     0x00000000000ffff0
+
+#define PDG_RESPONSE_PAD_DURATION_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_PAD_DURATION_LSB                                               20
+#define PDG_RESPONSE_PAD_DURATION_MSB                                               24
+#define PDG_RESPONSE_PAD_DURATION_MASK                                              0x0000000001f00000
+
+#define PDG_RESPONSE_Q2Q_MBA_OFFSET                                                 0x0000000000000030
+#define PDG_RESPONSE_Q2Q_MBA_LSB                                                    25
+#define PDG_RESPONSE_Q2Q_MBA_MSB                                                    25
+#define PDG_RESPONSE_Q2Q_MBA_MASK                                                   0x0000000002000000
+
+#define PDG_RESPONSE_RESERVED_12A_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_RESERVED_12A_LSB                                               26
+#define PDG_RESPONSE_RESERVED_12A_MSB                                               31
+#define PDG_RESPONSE_RESERVED_12A_MASK                                              0x00000000fc000000
+
+#define PDG_RESPONSE_TLV64_PADDING_OFFSET                                           0x0000000000000030
+#define PDG_RESPONSE_TLV64_PADDING_LSB                                              32
+#define PDG_RESPONSE_TLV64_PADDING_MSB                                              63
+#define PDG_RESPONSE_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/pdg_response_rate_setting.h b/hw/fig/v2/pdg_response_rate_setting.h
new file mode 100644
index 000000000000..eb123386f2bf
--- /dev/null
+++ b/hw/fig/v2/pdg_response_rate_setting.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  1,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      pkt_type                                                :  4,
+                      smoothing                                               :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      stf_ltf_3db_boost                                       :  1,
+                      force_extra_symbol                                      :  1;
+             uint32_t reserved_2a                                             :  4,
+                      nss                                                     :  3,
+                      dpd_enable                                              :  1,
+                      tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_chain_mask                                           :  8;
+             uint32_t alt_rate_mcs                                            :  5,
+                      reserved_3a                                             :  3,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8;
+             uint32_t aggregation                                             :  1,
+                      dot11ax_bss_color_id                                    :  6,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_4a                                             :  5;
+             uint32_t dot11ax_ext_ru_start_index                              :  4,
+                      dot11ax_ext_ru_size                                     :  4,
+                      eht_duplicate_mode                                      :  2,
+                      he_sigb_dcm                                             :  1,
+                      he_sigb_0_mcs                                           :  3,
+                      num_he_sigb_sym                                         :  5,
+                      required_response_time_source                           :  1,
+                      reserved_5a                                             :  6,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t required_response_time                                  : 12,
+                      dot11be_params_placeholder                              :  4;
+#else
+             uint32_t stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      smoothing                                               :  1,
+                      pkt_type                                                :  4,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      reserved_0a                                             :  1;
+             uint32_t force_extra_symbol                                      :  1,
+                      stf_ltf_3db_boost                                       :  1,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t tx_chain_mask                                           :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8,
+                      dpd_enable                                              :  1,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  4;
+             uint32_t alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8,
+                      ldpc_2x_codeword                                        :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      reserved_3a                                             :  3,
+                      alt_rate_mcs                                            :  5;
+             uint32_t reserved_4a                                             :  5,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_bss_color_id                                    :  6,
+                      aggregation                                             :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_5a                                             :  6,
+                      required_response_time_source                           :  1,
+                      num_he_sigb_sym                                         :  5,
+                      he_sigb_0_mcs                                           :  3,
+                      he_sigb_dcm                                             :  1,
+                      eht_duplicate_mode                                      :  2,
+                      dot11ax_ext_ru_size                                     :  4,
+                      dot11ax_ext_ru_start_index                              :  4;
+             uint32_t dot11be_params_placeholder                              :  4,
+                      required_response_time                                  : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET                                0x00000008
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB                                   3
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK                                  0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  4
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000001f
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   5
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000e0
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      14
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00007c00
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET                           0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK                             0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
+
+#endif
diff --git a/hw/fig/v2/pdg_tx_req.h b/hw/fig/v2/pdg_tx_req.h
new file mode 100644
index 000000000000..6baf640807da
--- /dev/null
+++ b/hw/fig/v2/pdg_tx_req.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_TX_REQ_H_
+#define _PDG_TX_REQ_H_
+
+#define NUM_OF_DWORDS_PDG_TX_REQ 2
+
+#define NUM_OF_QWORDS_PDG_TX_REQ 1
+
+struct pdg_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_reason                                               :  2,
+                      use_puncture_pattern                                    :  2,
+                      req_bw                                                  :  3,
+                      puncture_pattern_number                                 :  6,
+                      reserved_0b                                             :  1,
+                      req_paprd                                               :  1,
+                      duration_field_boundary_valid                           :  1,
+                      duration_field_boundary                                 : 16;
+             uint32_t puncture_subband_mask                                   : 16,
+                      reserved_0c                                             : 16;
+#else
+             uint32_t duration_field_boundary                                 : 16,
+                      duration_field_boundary_valid                           :  1,
+                      req_paprd                                               :  1,
+                      reserved_0b                                             :  1,
+                      puncture_pattern_number                                 :  6,
+                      req_bw                                                  :  3,
+                      use_puncture_pattern                                    :  2,
+                      tx_reason                                               :  2;
+             uint32_t reserved_0c                                             : 16,
+                      puncture_subband_mask                                   : 16;
+#endif
+};
+
+#define PDG_TX_REQ_TX_REASON_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_TX_REASON_LSB                                                    0
+#define PDG_TX_REQ_TX_REASON_MSB                                                    1
+#define PDG_TX_REQ_TX_REASON_MASK                                                   0x0000000000000003
+
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET                                      0x0000000000000000
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB                                         2
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB                                         3
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK                                        0x000000000000000c
+
+#define PDG_TX_REQ_REQ_BW_OFFSET                                                    0x0000000000000000
+#define PDG_TX_REQ_REQ_BW_LSB                                                       4
+#define PDG_TX_REQ_REQ_BW_MSB                                                       6
+#define PDG_TX_REQ_REQ_BW_MASK                                                      0x0000000000000070
+
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB                                      7
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB                                      12
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK                                     0x0000000000001f80
+
+#define PDG_TX_REQ_RESERVED_0B_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0B_LSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MASK                                                 0x0000000000002000
+
+#define PDG_TX_REQ_REQ_PAPRD_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_REQ_PAPRD_LSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MASK                                                   0x0000000000004000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET                             0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK                               0x0000000000008000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB                                      16
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB                                      31
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK                                     0x00000000ffff0000
+
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET                                     0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB                                        32
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB                                        47
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK                                       0x0000ffff00000000
+
+#define PDG_TX_REQ_RESERVED_0C_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0C_LSB                                                  48
+#define PDG_TX_REQ_RESERVED_0C_MSB                                                  63
+#define PDG_TX_REQ_RESERVED_0C_MASK                                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_abort_request_info.h b/hw/fig/v2/phyrx_abort_request_info.h
new file mode 100644
index 000000000000..1f3bf4b817b9
--- /dev/null
+++ b/hw/fig/v2/phyrx_abort_request_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phyrx_abort_reason                                      :  8,
+                      phy_enters_nap_state                                    :  1,
+                      phy_enters_defer_state                                  :  1,
+                      gain_change_by_main                                     :  1,
+                      gain_change_by_bt                                       :  1,
+                      main_tx_indication                                      :  1,
+                      bt_tx_indication                                        :  1,
+                      concurrent_mode                                         :  1,
+                      reserved_0                                              :  1,
+                      receive_duration                                        : 16;
+#else
+             uint32_t receive_duration                                        : 16,
+                      reserved_0                                              :  1,
+                      concurrent_mode                                         :  1,
+                      bt_tx_indication                                        :  1,
+                      main_tx_indication                                      :  1,
+                      gain_change_by_bt                                       :  1,
+                      gain_change_by_main                                     :  1,
+                      phy_enters_defer_state                                  :  1,
+                      phy_enters_nap_state                                    :  1,
+                      phyrx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB                             0
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB                             7
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET                        0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK                          0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET                      0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK                        0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET                         0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK                           0x00000400
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET                           0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK                             0x00000800
+
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK                            0x00001000
+
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK                              0x00002000
+
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET                             0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK                               0x00004000
+
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x00008000
+
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB                               16
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB                               31
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK                              0xffff0000
+
+#endif
diff --git a/hw/fig/v2/phyrx_common_user_info.h b/hw/fig/v2/phyrx_common_user_info.h
new file mode 100644
index 000000000000..b0817f33c169
--- /dev/null
+++ b/hw/fig/v2/phyrx_common_user_info.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
+
+#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
+
+struct phyrx_common_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t receive_duration                                        : 16,
+                      reserved_0a                                             : 16;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      eht___reserved_g_0022_ndp                                         :  1,
+                      bss_color_id_2                                          :  6,
+                      reserved_1a                                             :  2,
+                      obss_nav_update_enable                                  :  1,
+                      obss_nav_value                                          : 16;
+             uint32_t eht_or_uhr_ppdu_type                                    :  2,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      txop_duration                                           :  7,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      spatial_reuse                                           :  4,
+                      rx_ndp                                                  :  1,
+                      dot11bn_su_elr                                          :  1,
+                      combining_bandwidth                                     :  3,
+                      bss_flag                                                :  1,
+                      cobf_transmission                                       :  1,
+                      cosr_transmission                                       :  1;
+             uint32_t eht_duplicate                                           :  2,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      doppler_indication                                      :  1,
+                      sta_id                                                  : 11,
+                      puncture_bitmap                                         : 16;
+#else
+             uint32_t reserved_0a                                             : 16,
+                      receive_duration                                        : 16;
+             uint32_t obss_nav_value                                          : 16,
+                      obss_nav_update_enable                                  :  1,
+                      reserved_1a                                             :  2,
+                      bss_color_id_2                                          :  6,
+                      eht___reserved_g_0022_ndp                                         :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t cosr_transmission                                       :  1,
+                      cobf_transmission                                       :  1,
+                      bss_flag                                                :  1,
+                      combining_bandwidth                                     :  3,
+                      dot11bn_su_elr                                          :  1,
+                      rx_ndp                                                  :  1,
+                      spatial_reuse                                           :  4,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      txop_duration                                           :  7,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      eht_or_uhr_ppdu_type                                    :  2;
+             uint32_t puncture_bitmap                                         : 16,
+                      sta_id                                                  : 11,
+                      doppler_indication                                      :  1,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      eht_duplicate                                           :  2;
+#endif
+};
+
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET                              0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB                                 0
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB                                 15
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK                                0x000000000000ffff
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB                                      16
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK                                     0x00000000ffff0000
+
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET               0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                  32
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                  37
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                 0x0000003f00000000
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_OFFSET                                0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_LSB                                   39
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MSB                                   44
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MASK                                  0x00001f8000000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB                                      45
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB                                      46
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK                                     0x0000600000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET                        0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK                          0x0000800000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET                                0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB                                   48
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB                                   63
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK                                  0xffff000000000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET                          0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB                             0
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB                             1
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK                            0x0000000000000003
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET                                  0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB                                     2
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB                                     7
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK                                    0x00000000000000fc
+
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK                                      0x0000000000000100
+
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB                                    9
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB                                    15
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK                                   0x000000000000fe00
+
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB                                       16
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB                                       17
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK                                      0x0000000000030000
+
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET                                      0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB                                         18
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB                                         19
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK                                        0x00000000000c0000
+
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB                                    20
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB                                    23
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK                                   0x0000000000f00000
+
+#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK                                          0x0000000001000000
+
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET                                0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK                                  0x0000000002000000
+
+#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_OFFSET                           0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_LSB                              26
+#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MSB                              28
+#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MASK                             0x000000001c000000
+
+#define PHYRX_COMMON_USER_INFO_BSS_FLAG_OFFSET                                      0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_BSS_FLAG_LSB                                         29
+#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MSB                                         29
+#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MASK                                        0x0000000020000000
+
+#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_OFFSET                             0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_LSB                                30
+#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MSB                                30
+#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MASK                               0x0000000040000000
+
+#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_OFFSET                             0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_LSB                                31
+#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MSB                                31
+#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MASK                               0x0000000080000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB                                    32
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB                                    33
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK                                   0x0000000300000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB                    34
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB                    35
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK                   0x0000000c00000000
+
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET                            0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK                              0x0000001000000000
+
+#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_STA_ID_LSB                                           37
+#define PHYRX_COMMON_USER_INFO_STA_ID_MSB                                           47
+#define PHYRX_COMMON_USER_INFO_STA_ID_MASK                                          0x0000ffe000000000
+
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET                               0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB                                  48
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB                                  63
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_a_mu_dl.h b/hw/fig/v2/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..da4f1691b9f7
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
+
+struct phyrx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_a_mu_ul.h b/hw/fig/v2/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..ff9cf72a7237
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
+
+struct phyrx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_a_su.h b/hw/fig/v2/phyrx_he_sig_a_su.h
new file mode 100644
index 000000000000..abca58673a90
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
+
+struct phyrx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_b1_mu.h b/hw/fig/v2/phyrx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..ae784469331b
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_b2_mu.h b/hw/fig/v2/phyrx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..6035ecffde5d
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_he_sig_b2_ofdma.h b/hw/fig/v2/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..126a9559e155
--- /dev/null
+++ b/hw/fig/v2/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_ht_sig.h b/hw/fig/v2/phyrx_ht_sig.h
new file mode 100644
index 000000000000..4dd90653d431
--- /dev/null
+++ b/hw/fig/v2/phyrx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
+
+struct phyrx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#endif
+};
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_l_sig_a.h b/hw/fig/v2/phyrx_l_sig_a.h
new file mode 100644
index 000000000000..2e70822f5d06
--- /dev/null
+++ b/hw/fig/v2/phyrx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_l_sig_b.h b/hw/fig/v2/phyrx_l_sig_b.h
new file mode 100644
index 000000000000..461edd24dd4e
--- /dev/null
+++ b/hw/fig/v2/phyrx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_location.h b/hw/fig/v2/phyrx_location.h
new file mode 100644
index 000000000000..15a8413e304a
--- /dev/null
+++ b/hw/fig/v2/phyrx_location.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_LOCATION_H_
+#define _PHYRX_LOCATION_H_
+
+#include "rx_location_info.h"
+#define NUM_OF_DWORDS_PHYRX_LOCATION 28
+
+#define NUM_OF_QWORDS_PHYRX_LOCATION 14
+
+struct phyrx_location {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_location_info                                          rx_location_info_details;
+#else
+             struct   rx_location_info                                          rx_location_info_details;
+#endif
+};
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET       0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK         0x0000000000000001
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET             0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK               0x0000000000000002
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET                   0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB                      4
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB                      7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK                     0x00000000000000f0
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET                  0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB                     8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK                    0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET            0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET              0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB                 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB                 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK                0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET     0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB        32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB        39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK       0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET    0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB       40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK      0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK                 0x00ff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB                  56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB                  63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK                 0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK   0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB    39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK   0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET                   0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB                      40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK                     0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB                  51
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK                 0x000f000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB                  52
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK                 0x00f0000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET                 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB                    56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK                   0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET          0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB             0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB             15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK            0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET            0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB                     24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK                    0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK                    0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET            0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB               0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB               31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK              0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET                    0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK                      0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK                    0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB                     16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK                    0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB                     47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK                    0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB                     48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK                    0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET           0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB              0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB              7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK             0x00000000000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET       0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB          8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB          15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK         0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET             0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB                16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB                31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK               0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET                 0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB                    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_other_receive_info_ru_details.h b/hw/fig/v2/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 000000000000..a6090f721e1d
--- /dev/null
+++ b/hw/fig/v2/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
+
+#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
+
+struct phyrx_other_receive_info_ru_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB                0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB                31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK               0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB                32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB                63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK               0xffffffff00000000
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET                            0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB                               0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB                               31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK                              0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET                    0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB                       32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB                       63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK                      0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_pkt_end.h b/hw/fig/v2/phyrx_pkt_end.h
new file mode 100644
index 000000000000..1d1675edc0e1
--- /dev/null
+++ b/hw/fig/v2/phyrx_pkt_end.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+
+#include "phyrx_pkt_end_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END 24
+
+#define NUM_OF_QWORDS_PHYRX_PKT_END 12
+
+struct phyrx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#else
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#endif
+};
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET                 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK                   0x0000000000000002
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET                   0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK                     0x0000000000000004
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET                     0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK                       0x0000000000000008
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK                           0x0000000000000010
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET            0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK              0x0000000000000020
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB                            6
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB                            7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK                           0x00000000000000c0
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET                           0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB                              8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB                              15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK                             0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB                            16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB                            31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK                           0x00000000ffff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET     0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB        54
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB        63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK       0xffc0000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET                  0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB                     0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB                     31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK                    0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET                 0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB                    32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB                    63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_pkt_end_info.h b/hw/fig/v2/phyrx_pkt_end_info.h
new file mode 100644
index 000000000000..a21edc94d24e
--- /dev/null
+++ b/hw/fig/v2/phyrx_pkt_end_info.h
@@ -0,0 +1,450 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+
+#include "receive_rssi_info.h"
+#include "rx_timing_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
+
+struct phyrx_pkt_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0001                                        :  1,
+                      location_info_valid                                     :  1,
+                      timing_info_valid                                       :  1,
+                      rssi_info_valid                                         :  1,
+                      reserved_0a                                             :  1,
+                      frameless_frame_received                                :  1,
+                      reserved_0b                                             :  2,
+                      rssi_comb                                               :  8,
+                      reserved_0c                                             : 16;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#else
+             uint32_t reserved_0c                                             : 16,
+                      rssi_comb                                               :  8,
+                      reserved_0b                                             :  2,
+                      frameless_frame_received                                :  1,
+                      reserved_0a                                             :  1,
+                      rssi_info_valid                                         :  1,
+                      timing_info_valid                                       :  1,
+                      location_info_valid                                     :  1,
+                      __reserved_g_0001                                        :  1;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#endif
+};
+
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET                               0x00000000
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK                                 0x00000002
+
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET                                 0x00000000
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK                                   0x00000004
+
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET                                   0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK                                     0x00000008
+
+#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK                                         0x00000010
+
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET                          0x00000000
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK                            0x00000020
+
+#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB                                          6
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB                                          7
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK                                         0x000000c0
+
+#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET                                         0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB                                            8
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB                                            15
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK                                           0x0000ff00
+
+#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB                                          16
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB                                          31
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK                                         0xffff0000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET   0x00000004
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET   0x00000008
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET   0x0000000c
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET   0x00000010
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET      0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB         0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB         11
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK        0x00000fff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET         0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB            12
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB            21
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK           0x003ff000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET                   0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB                      22
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB                      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK                     0xffc00000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET    0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET   0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET    0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET   0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET    0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET   0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET    0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET   0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET    0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET   0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET    0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET   0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET    0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET   0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET    0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET   0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET                                0x00000058
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB                                   0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB                                   31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK                                  0xffffffff
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET                               0x0000005c
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB                                  0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB                                  31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/fig/v2/phyrx_rssi_legacy.h b/hw/fig/v2/phyrx_rssi_legacy.h
new file mode 100644
index 000000000000..820ced6212ca
--- /dev/null
+++ b/hw/fig/v2/phyrx_rssi_legacy.h
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+
+#include "receive_rssi_info.h"
+#include "receive_pkt_start_info.h"
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
+
+#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21
+
+struct phyrx_rssi_legacy {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t rssi_comb_ppdu                                          :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_for_trigger_resp                                   :  8;
+#else
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8;
+             uint32_t rssi_for_trigger_resp                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_comb_ppdu                                          :  8;
+#endif
+};
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET                0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB                   0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB                   3
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK                  0x000000000000000f
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET            0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK              0x0000000000000010
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET             0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB                5
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x00000000000000e0
+
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET             PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK               PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK                   0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET                   0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB                      16
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB                      31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK                     0x00000000ffff0000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET     0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB        32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB        63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET    0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB       0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB       31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK      0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB         32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB         39
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK         0x0000010000000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET                   0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB                      41
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB                      63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK                     0xfffffe0000000000
+
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET                                   0x0000000000000010
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB                                      0
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB                                      31
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK                                     0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET                                        0x0000000000000010
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK                                          0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET                                      0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB                                         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB                                         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK                                        0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET                                          0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB                                             8
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB                                             15
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK                                            0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET                           0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB                              16
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB                              23
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK                             0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET                               0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB                                  24
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB                                  31
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK                                 0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET                                     0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB                                        32
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB                                        39
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK                                       0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB                                 40
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB                                 47
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK                                0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET                             0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB                                48
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB                                55
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK                               0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB                                 56
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB                                 63
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_user_info.h b/hw/fig/v2/phyrx_user_info.h
new file mode 100644
index 000000000000..784904450033
--- /dev/null
+++ b/hw/fig/v2/phyrx_user_info.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
+
+#define NUM_OF_QWORDS_PHYRX_USER_INFO 4
+
+struct phyrx_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB                   0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB                   15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK                  0x000000000000ffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET                  0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB                     16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB                     23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK                    0x0000000000ff0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB                      24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB                      27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK                     0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET                       0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                         0x0000000010000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB                29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB                31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK               0x00000000e0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB                      32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB                      36
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK                     0x0000001f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                           38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                          0x0000006000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB                40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB                47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK               0x0000ff0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET          0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB             48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB             50
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK            0x0007000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB                   51
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK                  0x00f8000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB           63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK          0xff00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET   0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK     0x0000000000000001
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK                  0x0000000000000002
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB                     2
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB                     3
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK                    0x000000000000000c
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB                     4
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB                     5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK                    0x0000000000000030
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB                     6
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB                     7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK                    0x00000000000000c0
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                           8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                           10
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                          0x0000000000000700
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET              0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB                 11
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB                 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK                0x0000000000003800
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET                    0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK                      0x0000000000004000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET                       0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                         0x0000000000008000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB                  16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB                  19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK                 0x00000000000f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB                  20
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB                  23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK                 0x0000000000f00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB                  24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB                  27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK                 0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB                  28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB                  31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK                 0x00000000f0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB           32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK          0x0000003f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB                   38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB                   39
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK                  0x000000c000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB           40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB           45
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK          0x00003f0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB                   46
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB                   47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK                  0x0000c00000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB           48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB           53
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK          0x003f000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB                   54
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK                  0x00c0000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB           61
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK          0x3f00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET           0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB              62
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB              62
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK             0x4000000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB                   63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB                   63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK                  0x8000000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK            0xffffffff00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/phyrx_vht_sig_a.h b/hw/fig/v2/phyrx_vht_sig_a.h
new file mode 100644
index 000000000000..e47f0e35adeb
--- /dev/null
+++ b/hw/fig/v2/phyrx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
+
+struct phyrx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/phytx_abort_request_info.h b/hw/fig/v2/phytx_abort_request_info.h
new file mode 100644
index 000000000000..e4800f6a2d97
--- /dev/null
+++ b/hw/fig/v2/phytx_abort_request_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t phytx_abort_reason                                      :  8,
+                      user_number                                             :  6,
+                      reserved                                                :  2;
+#else
+             uint16_t reserved                                                :  2,
+                      user_number                                             :  6,
+                      phytx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB                             0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB                             7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET                                 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB                                    8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB                                    13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK                                   0x00003f00
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET                                    0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB                                       14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB                                       15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK                                      0x0000c000
+
+#endif
diff --git a/hw/fig/v2/phytx_pkt_end.h b/hw/fig/v2/phytx_pkt_end.h
new file mode 100644
index 000000000000..55911ea9edb3
--- /dev/null
+++ b/hw/fig/v2/phytx_pkt_end.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PKT_END_H_
+#define _PHYTX_PKT_END_H_
+
+#define NUM_OF_WORDS_PHYTX_PKT_END 28
+
+#define NUM_OF_DWORDS_PHYTX_PKT_END 14
+
+struct phytx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t tx_group_delay                                          : 12,
+                      timing_status                                           :  2,
+                      phyrx_entered_nap_state                                 :  1,
+                      dpdtrain_done                                           :  1;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t beamform_masked_user_bitmap_36_32                       :  5,
+                      reserved_23                                             : 11;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#else
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t dpdtrain_done                                           :  1,
+                      phyrx_entered_nap_state                                 :  1,
+                      timing_status                                           :  2,
+                      tx_group_delay                                          : 12;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t reserved_23                                             : 11,
+                      beamform_masked_user_bitmap_36_32                       :  5;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#endif
+};
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET                          0x00000000
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB                             0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB                             15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK                            0x0000ffff
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET                         0x00000002
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB                            0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB                            15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK                           0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET                            0x00000004
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB                               0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB                               15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK                              0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET                           0x00000006
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB                              0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB                              15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK                             0x0000ffff
+
+#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET                                         0x00000008
+#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB                                            11
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK                                           0x00000fff
+
+#define PHYTX_PKT_END_TIMING_STATUS_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_TIMING_STATUS_LSB                                             12
+#define PHYTX_PKT_END_TIMING_STATUS_MSB                                             13
+#define PHYTX_PKT_END_TIMING_STATUS_MASK                                            0x00003000
+
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET                                0x00000008
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK                                  0x00004000
+
+#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK                                            0x00008000
+
+#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET                                         0x0000000a
+#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB                                            15
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK                                           0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET                                  0x0000000c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB                                     0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB                                     15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK                                    0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET                                 0x0000000e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET                                 0x00000010
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET                                 0x00000012
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET                                0x00000014
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET                                0x00000016
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET                                0x00000018
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET                                0x0000001a
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET                                 0x0000001c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET                                0x0000001e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET                                0x00000020
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET                                0x00000022
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET                                0x00000024
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET                              0x00000026
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB                                 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB                                 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK                                0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET                             0x00000028
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET                             0x0000002a
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET                             0x0000002c
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                       0x0000002e
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                          0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                          15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                         0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                      0x00000030
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                         15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                        0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                      0x00000032
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                         4
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                        0x0000001f
+
+#define PHYTX_PKT_END_RESERVED_23_OFFSET                                            0x00000032
+#define PHYTX_PKT_END_RESERVED_23_LSB                                               5
+#define PHYTX_PKT_END_RESERVED_23_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_23_MASK                                              0x0000ffe0
+
+#define PHYTX_PKT_END_RESERVED_26_OFFSET                                            0x00000034
+#define PHYTX_PKT_END_RESERVED_26_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_26_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_26_MASK                                              0x0000ffff
+
+#define PHYTX_PKT_END_RESERVED_27_OFFSET                                            0x00000036
+#define PHYTX_PKT_END_RESERVED_27_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_27_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_27_MASK                                              0x0000ffff
+
+#endif
diff --git a/hw/fig/v2/phytx_ppdu_header_info_request.h b/hw/fig/v2/phytx_ppdu_header_info_request.h
new file mode 100644
index 000000000000..7fbecae41236
--- /dev/null
+++ b/hw/fig/v2/phytx_ppdu_header_info_request.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+
+#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
+
+#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
+
+struct phytx_ppdu_header_info_request {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t request_type                                            :  5,
+                      reserved                                                : 11;
+             uint16_t tlv32_padding                                           : 16;
+#else
+             uint16_t reserved                                                : 11,
+                      request_type                                            :  5;
+             uint16_t tlv32_padding                                           : 16;
+#endif
+};
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET                          0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB                             0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB                             4
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK                            0x0000001f
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET                              0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB                                 5
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB                                 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK                                0x0000ffe0
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET                         0x00000002
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB                            0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB                            15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK                           0x0000ffff
+
+#endif
diff --git a/hw/fig/v2/receive_pkt_start_info.h b/hw/fig/v2/receive_pkt_start_info.h
new file mode 100644
index 000000000000..7f7c81449a15
--- /dev/null
+++ b/hw/fig/v2/receive_pkt_start_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_PKT_START_INFO_H_
+#define _RECEIVE_PKT_START_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
+
+struct receive_pkt_start_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reception_type                                          :  4,
+                      rx_chain_mask_type                                      :  1,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask                                           :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t preamble_time_to_rxframe                                :  8,
+                      standalone_sniffer_mode                                 :  1,
+                      reserved_3a                                             : 23;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      rx_chain_mask                                           :  8,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask_type                                      :  1,
+                      reception_type                                          :  4;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t reserved_3a                                             : 23,
+                      standalone_sniffer_mode                                 :  1,
+                      preamble_time_to_rxframe                                :  8;
+#endif
+};
+
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET                                0x00000000
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB                                   0
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB                                   3
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK                                  0x0000000f
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET                            0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK                              0x00000010
+
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET                             0x00000000
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB                                5
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB                                7
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK                               0x000000e0
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET                                 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB                                    8
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB                                    15
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK                                   0x0000ff00
+
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET                                   0x00000000
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB                                      16
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB                                      31
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK                                     0xffff0000
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET                     0x00000004
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB                        0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB                        31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK                       0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET                    0x00000008
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB                       0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB                       31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK                      0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET                      0x0000000c
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB                         0
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB                         7
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK                        0x000000ff
+
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET                       0x0000000c
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK                         0x00000100
+
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB                                      9
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB                                      31
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK                                     0xfffffe00
+
+#endif
diff --git a/hw/fig/v2/receive_rssi_info.h b/hw/fig/v2/receive_rssi_info.h
new file mode 100644
index 000000000000..9aaa98217d99
--- /dev/null
+++ b/hw/fig/v2/receive_rssi_info.h
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_pri20_chain0                                       :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext40_high20_chain0                                :  8;
+             uint32_t rssi_ext80_low20_chain0                                 :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_high20_chain0                                :  8;
+             uint32_t rssi_ext160_0_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_3_chain0                                    :  8;
+             uint32_t rssi_ext160_4_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_7_chain0                                    :  8;
+             uint32_t rssi_pri20_chain1                                       :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext40_high20_chain1                                :  8;
+             uint32_t rssi_ext80_low20_chain1                                 :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_high20_chain1                                :  8;
+             uint32_t rssi_ext160_0_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_3_chain1                                    :  8;
+             uint32_t rssi_ext160_4_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_7_chain1                                    :  8;
+             uint32_t rssi_pri20_chain2                                       :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext40_high20_chain2                                :  8;
+             uint32_t rssi_ext80_low20_chain2                                 :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_high20_chain2                                :  8;
+             uint32_t rssi_ext160_0_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_3_chain2                                    :  8;
+             uint32_t rssi_ext160_4_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_7_chain2                                    :  8;
+             uint32_t rssi_pri20_chain3                                       :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext40_high20_chain3                                :  8;
+             uint32_t rssi_ext80_low20_chain3                                 :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_high20_chain3                                :  8;
+             uint32_t rssi_ext160_0_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_3_chain3                                    :  8;
+             uint32_t rssi_ext160_4_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_7_chain3                                    :  8;
+#else
+             uint32_t rssi_ext40_high20_chain0                                :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_pri20_chain0                                       :  8;
+             uint32_t rssi_ext80_high20_chain0                                :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_low20_chain0                                 :  8;
+             uint32_t rssi_ext160_3_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_0_chain0                                    :  8;
+             uint32_t rssi_ext160_7_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_4_chain0                                    :  8;
+             uint32_t rssi_ext40_high20_chain1                                :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_pri20_chain1                                       :  8;
+             uint32_t rssi_ext80_high20_chain1                                :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_low20_chain1                                 :  8;
+             uint32_t rssi_ext160_3_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_0_chain1                                    :  8;
+             uint32_t rssi_ext160_7_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_4_chain1                                    :  8;
+             uint32_t rssi_ext40_high20_chain2                                :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_pri20_chain2                                       :  8;
+             uint32_t rssi_ext80_high20_chain2                                :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_low20_chain2                                 :  8;
+             uint32_t rssi_ext160_3_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_0_chain2                                    :  8;
+             uint32_t rssi_ext160_7_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_4_chain2                                    :  8;
+             uint32_t rssi_ext40_high20_chain3                                :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_pri20_chain3                                       :  8;
+             uint32_t rssi_ext80_high20_chain3                                :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_low20_chain3                                 :  8;
+             uint32_t rssi_ext160_3_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_0_chain3                                    :  8;
+             uint32_t rssi_ext160_7_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_4_chain3                                    :  8;
+#endif
+};
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET                            0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET                           0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET                            0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET                           0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET                            0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET                           0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET                            0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET                           0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET                            0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET                           0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET                            0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET                           0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET                            0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET                           0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET                            0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET                           0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK                                 0xff000000
+
+#endif
diff --git a/hw/fig/v2/receive_user_info.h b/hw/fig/v2/receive_user_info.h
new file mode 100644
index 000000000000..51617cc781c0
--- /dev/null
+++ b/hw/fig/v2/receive_user_info.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
+
+struct receive_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      stbc                                                    :  1,
+                      reception_type                                          :  3;
+             uint32_t rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      __reserved_g_0004                                          :  1,
+                      mimo_ss_bitmap                                          :  8,
+                      receive_bandwidth                                       :  3,
+                      reserved_1b                                             :  5,
+                      dl_ofdma_user_index                                     :  8;
+             uint32_t dl_ofdma_content_channel                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      sta_dcm                                                 :  1,
+                      ldpc                                                    :  1,
+                      ru_type_80_0                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_3                                            :  4;
+             uint32_t ru_start_index_80_0                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      ldpc_2x_codeword                                        :  1,
+                      reserved_3d                                             :  1;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#else
+             uint32_t reception_type                                          :  3,
+                      stbc                                                    :  1,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t dl_ofdma_user_index                                     :  8,
+                      reserved_1b                                             :  5,
+                      receive_bandwidth                                       :  3,
+                      mimo_ss_bitmap                                          :  8,
+                      __reserved_g_0004                                          :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5;
+             uint32_t ru_type_80_3                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_0                                            :  4,
+                      ldpc                                                    :  1,
+                      sta_dcm                                                 :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      dl_ofdma_content_channel                                :  1;
+             uint32_t reserved_3d                                             :  1,
+                      ldpc_2x_codeword                                        :  1,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_0                                     :  6;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#endif
+};
+
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
+#define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
+#define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
+#define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
+
+#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
+#define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
+#define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
+#define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
+
+#define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
+#define RECEIVE_USER_INFO_STBC_LSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
+
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
+
+#define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
+#define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
+#define RECEIVE_USER_INFO_RATE_MCS_MSB                                              4
+#define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000001f
+
+#define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
+#define RECEIVE_USER_INFO_SGI_LSB                                                   5
+#define RECEIVE_USER_INFO_SGI_MSB                                                   6
+#define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000060
+
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
+
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
+
+#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
+#define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
+
+#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
+#define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x00000002
+
+#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF1_LSB                                             2
+#define RECEIVE_USER_INFO_QAM_DIFF1_MSB                                             3
+#define RECEIVE_USER_INFO_QAM_DIFF1_MASK                                            0x0000000c
+
+#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF2_LSB                                             4
+#define RECEIVE_USER_INFO_QAM_DIFF2_MSB                                             5
+#define RECEIVE_USER_INFO_QAM_DIFF2_MASK                                            0x00000030
+
+#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF3_LSB                                             6
+#define RECEIVE_USER_INFO_QAM_DIFF3_MSB                                             7
+#define RECEIVE_USER_INFO_QAM_DIFF3_MASK                                            0x000000c0
+
+#define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
+#define RECEIVE_USER_INFO_NSS_LSB                                                   8
+#define RECEIVE_USER_INFO_NSS_MSB                                                   10
+#define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
+
+#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
+#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
+
+#define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
+#define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
+
+#define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
+#define RECEIVE_USER_INFO_LDPC_LSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
+
+#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
+#define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
+
+#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
+#define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
+#define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
+
+#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
+#define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
+
+#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_OFFSET                                   0x0000000c
+#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_LSB                                      30
+#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MSB                                      30
+#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MASK                                     0x40000000
+
+#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           31
+#define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
+#define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0x80000000
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/fig/v2/received_response_user_15_8.h b/hw/fig/v2/received_response_user_15_8.h
new file mode 100644
index 000000000000..6cf8117ff02f
--- /dev/null
+++ b/hw/fig/v2/received_response_user_15_8.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_15_8_H_
+#define _RECEIVED_RESPONSE_USER_15_8_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32
+
+struct received_response_user_15_8 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#else
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET     0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET     0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET    0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET    0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET    0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET    0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET    0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET    0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/received_response_user_23_16.h b/hw/fig/v2/received_response_user_23_16.h
new file mode 100644
index 000000000000..ff56f4d96472
--- /dev/null
+++ b/hw/fig/v2/received_response_user_23_16.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_23_16_H_
+#define _RECEIVED_RESPONSE_USER_23_16_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32
+
+struct received_response_user_23_16 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#else
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/received_response_user_31_24.h b/hw/fig/v2/received_response_user_31_24.h
new file mode 100644
index 000000000000..aaa90838daa9
--- /dev/null
+++ b/hw/fig/v2/received_response_user_31_24.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_31_24_H_
+#define _RECEIVED_RESPONSE_USER_31_24_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32
+
+struct received_response_user_31_24 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#else
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/received_response_user_36_32.h b/hw/fig/v2/received_response_user_36_32.h
new file mode 100644
index 000000000000..3f33fdab635e
--- /dev/null
+++ b/hw/fig/v2/received_response_user_36_32.h
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
+#define _RECEIVED_RESPONSE_USER_36_32_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20
+
+struct received_response_user_36_32 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#else
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/received_response_user_7_0.h b/hw/fig/v2/received_response_user_7_0.h
new file mode 100644
index 000000000000..f785aca46840
--- /dev/null
+++ b/hw/fig/v2/received_response_user_7_0.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_7_0_H_
+#define _RECEIVED_RESPONSE_USER_7_0_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32
+
+struct received_response_user_7_0 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#else
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET      0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET      0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET      0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET      0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET      0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET      0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET      0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET      0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/received_response_user_info.h b/hw/fig/v2/received_response_user_info.h
new file mode 100644
index 000000000000..3c3faf119635
--- /dev/null
+++ b/hw/fig/v2/received_response_user_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_fcs_pass_count                                     : 12,
+                      mpdu_fcs_fail_count                                     : 12,
+                      qosnull_frame_count                                     :  4,
+                      reserved_0a                                             :  3,
+                      user_info_valid                                         :  1;
+             uint32_t null_delimiter_count                                    : 22,
+                      reserved_1a                                             :  9,
+                      ht_control_valid                                        :  1;
+             uint32_t ht_control                                              : 32;
+             uint32_t qos_control_valid                                       : 16,
+                      eosp                                                    : 16;
+             uint32_t qos_control_15_8_tid_0                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_3                                  :  8;
+             uint32_t qos_control_15_8_tid_4                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_7                                  :  8;
+             uint32_t qos_control_15_8_tid_8                                  :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_11                                 :  8;
+             uint32_t qos_control_15_8_tid_12                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_15                                 :  8;
+#else
+             uint32_t user_info_valid                                         :  1,
+                      reserved_0a                                             :  3,
+                      qosnull_frame_count                                     :  4,
+                      mpdu_fcs_fail_count                                     : 12,
+                      mpdu_fcs_pass_count                                     : 12;
+             uint32_t ht_control_valid                                        :  1,
+                      reserved_1a                                             :  9,
+                      null_delimiter_count                                    : 22;
+             uint32_t ht_control                                              : 32;
+             uint32_t eosp                                                    : 16,
+                      qos_control_valid                                       : 16;
+             uint32_t qos_control_15_8_tid_3                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_0                                  :  8;
+             uint32_t qos_control_15_8_tid_7                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_4                                  :  8;
+             uint32_t qos_control_15_8_tid_11                                 :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_8                                  :  8;
+             uint32_t qos_control_15_8_tid_15                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_12                                 :  8;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
+
+#endif
diff --git a/hw/fig/v2/received_trigger_info.h b/hw/fig/v2/received_trigger_info.h
new file mode 100644
index 000000000000..ff464f4e3bb5
--- /dev/null
+++ b/hw/fig/v2/received_trigger_info.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_H_
+#define _RECEIVED_TRIGGER_INFO_H_
+
+#include "received_trigger_info_details.h"
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
+
+#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
+
+struct received_trigger_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_trigger_info_details                             received_trigger_details;
+#else
+             struct   received_trigger_info_details                             received_trigger_details;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET          0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB             0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB             3
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK            0x000000000000000f
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK       0x0000000000000010
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB          5
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB          8
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK         0x00000000000001e0
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET   0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK     0x0000000000400000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK       0x0000000000800000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK   0x0000000001000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB        29
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB        30
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK       0x0000000060000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB              32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB              47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK             0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET  0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB     48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB     59
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK    0x0fff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK             0x2000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK         0x4000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK             0x8000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET         0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB            0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB            15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK           0x000000000000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB              16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK             0x00000000ffff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET            0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB               32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB               47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK              0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB              62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK             0xc000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET            0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB               0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB               31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK              0x00000000ffffffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET           0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB              40
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK             0xffffff0000000000
+
+#endif
diff --git a/hw/fig/v2/received_trigger_info_details.h b/hw/fig/v2/received_trigger_info_details.h
new file mode 100644
index 000000000000..071942ba26bd
--- /dev/null
+++ b/hw/fig/v2/received_trigger_info_details.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t trigger_type                                            :  4,
+                      ax_trigger_source                                       :  1,
+                      ax_trigger_type                                         :  4,
+                      trigger_source_sta_full_aid                             : 13,
+                      frame_control_valid                                     :  1,
+                      qos_control_valid                                       :  1,
+                      he_control_info_valid                                   :  1,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      txop_sharing_mode                                       :  2,
+                      tid_aggregation_limit_is_zero                           :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      lsig_response_length                                    : 12,
+                      __reserved_g_0035                                                 :  1,
+                      scsid_valid                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_1a                                             :  1;
+             uint32_t frame_control                                           : 16,
+                      qos_control                                             : 16;
+             uint32_t sw_peer_id                                              : 16,
+                      txop_sharing_allocation_duration                        :  9,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      __reserved_g_0017                                       :  1,
+                      reserved_3a                                             :  2;
+             uint32_t he_control                                              : 32;
+             uint32_t txop_sharing_duration_from_durid                        :  1,
+                      frame_durationid_lower_4                                :  4,
+                      frame_durationid_upper_3                                :  3,
+                      reserved_5a                                             : 24;
+#else
+             uint32_t tid_aggregation_limit_is_zero                           :  1,
+                      txop_sharing_mode                                       :  2,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      he_control_info_valid                                   :  1,
+                      qos_control_valid                                       :  1,
+                      frame_control_valid                                     :  1,
+                      trigger_source_sta_full_aid                             : 13,
+                      ax_trigger_type                                         :  4,
+                      ax_trigger_source                                       :  1,
+                      trigger_type                                            :  4;
+             uint32_t reserved_1a                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      scsid_valid                                             :  1,
+                      __reserved_g_0035                                                 :  1,
+                      lsig_response_length                                    : 12,
+                      phy_ppdu_id                                             : 16;
+             uint32_t qos_control                                             : 16,
+                      frame_control                                           : 16;
+             uint32_t reserved_3a                                             :  2,
+                      __reserved_g_0017                                       :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      txop_sharing_allocation_duration                        :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t he_control                                              : 32;
+             uint32_t reserved_5a                                             : 24,
+                      frame_durationid_upper_3                                :  3,
+                      frame_durationid_lower_4                                :  4,
+                      txop_sharing_duration_from_durid                        :  1;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET                           0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB                              0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB                              3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK                             0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK                        0x00000010
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET                        0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB                           5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB                           8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK                          0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB               9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB               21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK              0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET                    0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK                      0x00400000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK                        0x00800000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET                  0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK                    0x01000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB                         29
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB                         30
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK                        0x60000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET          0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK            0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB                               0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB                               15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK                              0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                   0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB                      16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB                      27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK                     0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK                              0x20000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET                        0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK                          0x40000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK                              0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET                          0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB                             0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB                             15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK                            0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET                            0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK                              0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET                             0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB                                15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK                               0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET       0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB          16
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB          24
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK         0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET                            0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB                               30
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK                              0xc0000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET                             0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB                                31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK                               0xffffffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET       0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK         0x00000001
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB                  1
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB                  4
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK                 0x0000001e
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB                  5
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB                  7
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK                 0x000000e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET                            0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB                               8
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK                              0xffffff00
+
+#endif
diff --git a/hw/fig/v2/reo_destination_ring.h b/hw/fig/v2/reo_destination_ring.h
new file mode 100644
index 000000000000..5147635121c1
--- /dev/null
+++ b/hw/fig/v2/reo_destination_ring.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
+
+struct reo_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB               0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB               7
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK              0x000000ff
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET         0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK           0x00000100
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET        0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK          0x00000200
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK              0x00000400
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET             0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK               0x00000800
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                0x00002000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET    0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK      0x00004000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                 15
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                 26
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                0x07ff8000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK  0x08000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                   0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                      28
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                      31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                     0xf0000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET        0x0000000c
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB           0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB           31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK          0xffffffff
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET                           0x00000014
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB                              0
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB                              2
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK                             0x00000007
+
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK                          0x00000008
+
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET                               0x00000014
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB                                  4
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB                                  5
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK                                 0x00000030
+
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB                                   6
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB                                   10
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK                                  0x000007c0
+
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK                                  0x00000800
+
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB                                   12
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB                                   31
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK                                  0xfffff000
+
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET                            0x00000018
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB                               0
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB                               3
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK                              0x0000000f
+
+#define REO_DESTINATION_RING_RESERVED_6A_OFFSET                                     0x00000018
+#define REO_DESTINATION_RING_RESERVED_6A_LSB                                        4
+#define REO_DESTINATION_RING_RESERVED_6A_MSB                                        31
+#define REO_DESTINATION_RING_RESERVED_6A_MASK                                       0xfffffff0
+
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK                              0x00000001
+
+#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB                                    1
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB                                    2
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK                                   0x00000006
+
+#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET                                  0x0000001c
+#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB                                     3
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB                                     7
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK                                    0x000000f8
+
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB                            8
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB                            11
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK                           0x00000f00
+
+#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET                                    0x0000001c
+#define REO_DESTINATION_RING_SW_EXCEPTION_LSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MASK                                      0x00001000
+
+#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET                                     0x0000001c
+#define REO_DESTINATION_RING_SRC_LINK_ID_LSB                                        13
+#define REO_DESTINATION_RING_SRC_LINK_ID_MSB                                        15
+#define REO_DESTINATION_RING_SRC_LINK_ID_MASK                                       0x0000e000
+
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB                   16
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB                   19
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK                  0x000f0000
+
+#define REO_DESTINATION_RING_RING_ID_OFFSET                                         0x0000001c
+#define REO_DESTINATION_RING_RING_ID_LSB                                            20
+#define REO_DESTINATION_RING_RING_ID_MSB                                            27
+#define REO_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
+
+#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000001c
+#define REO_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define REO_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define REO_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/fig/v2/reo_destination_ring_with_pn.h b/hw/fig/v2/reo_destination_ring_with_pn.h
new file mode 100644
index 000000000000..b486a8658388
--- /dev/null
+++ b/hw/fig/v2/reo_destination_ring_with_pn.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_WITH_PN_H_
+#define _REO_DESTINATION_RING_WITH_PN_H_
+
+#include "rx_msdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
+
+struct reo_destination_ring_with_pn {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t msdu_count                                              :  8,
+                      prev_pn_23_0                                            : 24;
+             uint32_t prev_pn_47_24                                           : 24,
+                      prev_pn_127_48_info                                     :  2,
+                      reserved_3a                                             :  6;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t prev_pn_23_0                                            : 24,
+                      msdu_count                                              :  8;
+             uint32_t reserved_3a                                             :  6,
+                      prev_pn_127_48_info                                     :  2,
+                      prev_pn_47_24                                           : 24;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET                              0x00000008
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB                                 0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB                                 7
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK                                0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET                            0x00000008
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB                               8
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB                               31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK                              0xffffff00
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET                           0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB                              0
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB                              23
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK                             0x00ffffff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET                     0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB                        24
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB                        25
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK                       0x03000000
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET                             0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB                                26
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK                               0xfc000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB      3
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB      16
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK     0x0001fff8
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK       0x00020000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK     0x00040000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK     0x00080000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET    0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK      0x00100000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK  0x00800000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK           0x01000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK           0x02000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK       0x04000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB     27
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB     28
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK    0x18000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB     29
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB     30
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK    0x60000000
+
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET                   0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB                      0
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB                      2
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK                     0x00000007
+
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET                0x00000014
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK                  0x00000008
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET                       0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB                          4
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB                          5
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK                         0x00000030
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB                           6
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB                           10
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK                          0x000007c0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK                          0x00000800
+
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB                           12
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB                           31
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET                    0x00000018
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB                       3
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK                      0x0000000f
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET                             0x00000018
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB                                4
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK                               0xfffffff0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET                    0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK                      0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB                            1
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB                            2
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK                           0x00000006
+
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET                          0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB                             3
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB                             7
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK                            0x000000f8
+
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB                    8
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB                    11
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK                   0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK                              0x00001000
+
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET                             0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB                                13
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB                                15
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK                               0x0000e000
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET        0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB           16
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB           19
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK          0x000f0000
+
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB                                    20
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB                                    27
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK                                   0x0ff00000
+
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET                           0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB                              28
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB                              31
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif
diff --git a/hw/fig/v2/reo_entrance_ring.h b/hw/fig/v2/reo_entrance_ring.h
new file mode 100644
index 000000000000..17a68d08ce25
--- /dev/null
+++ b/hw/fig/v2/reo_entrance_ring.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+
+#include "rx_mpdu_details.h"
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12
+
+struct reo_entrance_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_preamble_timestamp                                   : 32;
+             uint32_t reserved_7a                                             :  8,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reo_destination_indication                              :  5,
+                      frameless_bar                                           :  1,
+                      reserved_7b                                             :  4;
+             uint32_t rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      mpdu_fragment_number                                    :  4,
+                      sw_exception                                            :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_destination_ring                           :  5,
+                      mpdu_sequence_number                                    : 12,
+                      no_ack                                                  :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      src_link_id                                             :  3,
+                      reserved_9a                                             :  5,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t receive_queue_number                                    : 16,
+                      fw_reorder_push_reason                                  :  2,
+                      fw_reorder_error_code                                   :  5,
+                      reo_bypass                                              :  1,
+                      reserved_10a                                            :  8;
+             uint32_t phy_lmac_latency                                        : 16,
+                      reserved_15a                                            :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_preamble_timestamp                                   : 32;
+             uint32_t reserved_7b                                             :  4,
+                      frameless_bar                                           :  1,
+                      reo_destination_indication                              :  5,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reserved_7a                                             :  8;
+             uint32_t no_ack                                                  :  1,
+                      mpdu_sequence_number                                    : 12,
+                      sw_exception_destination_ring                           :  5,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception                                            :  1,
+                      mpdu_fragment_number                                    :  4,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      reserved_9a                                             :  5,
+                      src_link_id                                             :  3,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_10a                                            :  8,
+                      reo_bypass                                              :  1,
+                      fw_reorder_error_code                                   :  5,
+                      fw_reorder_push_reason                                  :  2,
+                      receive_queue_number                                    : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            :  4,
+                      phy_lmac_latency                                        : 16;
+#endif
+};
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000
+
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET                              0x00000018
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB                                 0
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB                                 31
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK                                0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7A_LSB                                           0
+#define REO_ENTRANCE_RING_RESERVED_7A_MSB                                           7
+#define REO_ENTRANCE_RING_RESERVED_7A_MASK                                          0x000000ff
+
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET                            0x0000001c
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB                               8
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB                               21
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK                              0x003fff00
+
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET                         0x0000001c
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB                            22
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB                            26
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK                           0x07c00000
+
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET                                      0x0000001c
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK                                        0x08000000
+
+#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7B_LSB                                           28
+#define REO_ENTRANCE_RING_RESERVED_7B_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_7B_MASK                                          0xf0000000
+
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET                                  0x00000020
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB                                     0
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB                                     1
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK                                    0x00000003
+
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET                                   0x00000020
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB                                      2
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB                                      6
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK                                     0x0000007c
+
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB                                  7
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB                                  10
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK                                 0x00000780
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET                                       0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK                                         0x00000800
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET                           0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK                             0x00001000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET                0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK                  0x00002000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET                      0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB                         14
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB                         18
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK                        0x0007c000
+
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB                                  19
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB                                  30
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK                                 0x7ff80000
+
+#define REO_ENTRANCE_RING_NO_ACK_OFFSET                                             0x00000020
+#define REO_ENTRANCE_RING_NO_ACK_LSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MASK                                               0x80000000
+
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB                                           0
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB                                           15
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB                                           16
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB                                           18
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK                                          0x00070000
+
+#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_RESERVED_9A_LSB                                           19
+#define REO_ENTRANCE_RING_RESERVED_9A_MSB                                           23
+#define REO_ENTRANCE_RING_RESERVED_9A_MASK                                          0x00f80000
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                       0x00000024
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                          24
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                          31
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                         0xff000000
+
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET                               0x00000028
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB                                  0
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB                                  15
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK                                 0x0000ffff
+
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET                             0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB                                16
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB                                17
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK                               0x00030000
+
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET                              0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB                                 18
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB                                 22
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK                                0x007c0000
+
+#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET                                         0x00000028
+#define REO_ENTRANCE_RING_REO_BYPASS_LSB                                            23
+#define REO_ENTRANCE_RING_REO_BYPASS_MSB                                            23
+#define REO_ENTRANCE_RING_REO_BYPASS_MASK                                           0x00800000
+
+#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET                                       0x00000028
+#define REO_ENTRANCE_RING_RESERVED_10A_LSB                                          24
+#define REO_ENTRANCE_RING_RESERVED_10A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_10A_MASK                                         0xff000000
+
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET                                   0x0000002c
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB                                      0
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB                                      15
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK                                     0x0000ffff
+
+#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET                                       0x0000002c
+#define REO_ENTRANCE_RING_RESERVED_15A_LSB                                          16
+#define REO_ENTRANCE_RING_RESERVED_15A_MSB                                          19
+#define REO_ENTRANCE_RING_RESERVED_15A_MASK                                         0x000f0000
+
+#define REO_ENTRANCE_RING_RING_ID_OFFSET                                            0x0000002c
+#define REO_ENTRANCE_RING_RING_ID_LSB                                               20
+#define REO_ENTRANCE_RING_RING_ID_MSB                                               27
+#define REO_ENTRANCE_RING_RING_ID_MASK                                              0x0ff00000
+
+#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET                                      0x0000002c
+#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB                                         28
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB                                         31
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK                                        0xf0000000
+
+#endif
diff --git a/hw/fig/v2/response_end_status.h b/hw/fig/v2/response_end_status.h
new file mode 100644
index 000000000000..a5dda1fec669
--- /dev/null
+++ b/hw/fig/v2/response_end_status.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_END_STATUS_H_
+#define _RESPONSE_END_STATUS_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
+
+#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5
+
+struct response_end_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0072                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      response_transmit_status                                :  4,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      generated_response                                      :  3,
+                      mba_user_count                                          :  7,
+                      mba_fake_bitmap_count                                   :  7,
+                      coex_based_tx_bw                                        :  3,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0035                                                 :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8;
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      reserved_2b                                             : 10,
+                      only_null_delim_sent                                    :  1,
+                      brp_info_valid                                          :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0051                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0030                                       :  1;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t mu_response_bitmap_36_32                                :  5,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mic_overwritten                                         :  1,
+                      trig_resp_cmd_found                                     :  1,
+                      reserved_4a                                             : 21;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      __reserved_g_0022                                                 :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      reserved_20a                                            : 13;
+#else
+             uint32_t __reserved_g_0035                                                 :  1,
+                      trig_response_related                                   :  1,
+                      coex_based_tx_bw                                        :  3,
+                      mba_fake_bitmap_count                                   :  7,
+                      mba_user_count                                          :  7,
+                      generated_response                                      :  3,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      response_transmit_status                                :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0072                                       :  1;
+             uint32_t cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t __reserved_g_0030                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0051                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0067                                       :  1,
+                      brp_info_valid                                          :  1,
+                      only_null_delim_sent                                    :  1,
+                      reserved_2b                                             : 10,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t reserved_4a                                             : 21,
+                      trig_resp_cmd_found                                     :  1,
+                      mic_overwritten                                         :  1,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mu_response_bitmap_36_32                                :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t reserved_20a                                            : 13,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      addr3_47_32                                             : 16;
+#endif
+};
+
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                      0x0000000000000008
+
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB                            4
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB                            7
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK                           0x00000000000000f0
+
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK                           0x0000000000000100
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000000000200
+
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET                               0x0000000000000000
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB                                  10
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB                                  12
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK                                 0x0000000000001c00
+
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET                                   0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB                                      13
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB                                      19
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK                                     0x00000000000fe000
+
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB                               20
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB                               26
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK                              0x0000000007f00000
+
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET                                 0x0000000000000000
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB                                    27
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB                                    29
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK                                   0x0000000038000000
+
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK                              0x0000000040000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET     0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB        40
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB        45
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK       0x00003f0000000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET        0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB           46
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB           47
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK          0x0000c00000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB                            48
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB                            55
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK                           0x00ff000000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB                               56
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB                               63
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK                              0xff00000000000000
+
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB                                0
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB                                8
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK                               0x00000000000001ff
+
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET                           0x0000000000000008
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB                              9
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB                              10
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK                             0x0000000000000600
+
+#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET                                      0x0000000000000008
+#define RESPONSE_END_STATUS_RESERVED_2B_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_2B_MSB                                         20
+#define RESPONSE_END_STATUS_RESERVED_2B_MASK                                        0x00000000001ff800
+
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK                               0x0000000000200000
+
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET                                   0x0000000000000008
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK                                     0x0000000000400000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET                          0x0000000000000008
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB                             32
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB                             63
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK                            0xffffffff00000000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET                         0x0000000000000010
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB                            0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB                            4
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK                           0x000000000000001f
+
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET               0x0000000000000010
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB                  5
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB                  8
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK                 0x00000000000001e0
+
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET                                  0x0000000000000010
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB                                     9
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB                                     9
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK                                    0x0000000000000200
+
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET                              0x0000000000000010
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB                                 10
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB                                 10
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK                                0x0000000000000400
+
+#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET                                      0x0000000000000010
+#define RESPONSE_END_STATUS_RESERVED_4A_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_4A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_4A_MASK                                        0x00000000fffff800
+
+#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET                                       0x0000000000000010
+#define RESPONSE_END_STATUS_ADDR1_31_0_LSB                                          32
+#define RESPONSE_END_STATUS_ADDR1_31_0_MSB                                          63
+#define RESPONSE_END_STATUS_ADDR1_31_0_MASK                                         0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR1_47_32_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR1_47_32_MSB                                         15
+#define RESPONSE_END_STATUS_ADDR1_47_32_MASK                                        0x000000000000ffff
+
+#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET                                       0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_15_0_LSB                                          16
+#define RESPONSE_END_STATUS_ADDR2_15_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR2_15_0_MASK                                         0x00000000ffff0000
+
+#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_47_16_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR2_47_16_MSB                                         63
+#define RESPONSE_END_STATUS_ADDR2_47_16_MASK                                        0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET                                       0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_31_0_LSB                                          0
+#define RESPONSE_END_STATUS_ADDR3_31_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR3_31_0_MASK                                         0x00000000ffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET                                      0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_47_32_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR3_47_32_MSB                                         47
+#define RESPONSE_END_STATUS_ADDR3_47_32_MASK                                        0x0000ffff00000000
+
+#define RESPONSE_END_STATUS_SECURE_OFFSET                                           0x0000000000000020
+#define RESPONSE_END_STATUS_SECURE_LSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MASK                                             0x0002000000000000
+
+#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET                                     0x0000000000000020
+#define RESPONSE_END_STATUS_RESERVED_20A_LSB                                        51
+#define RESPONSE_END_STATUS_RESERVED_20A_MSB                                        63
+#define RESPONSE_END_STATUS_RESERVED_20A_MASK                                       0xfff8000000000000
+
+#endif
diff --git a/hw/fig/v2/response_start_status.h b/hw/fig/v2/response_start_status.h
new file mode 100644
index 000000000000..0a3090f219fe
--- /dev/null
+++ b/hw/fig/v2/response_start_status.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_START_STATUS_H_
+#define _RESPONSE_START_STATUS_H_
+
+#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
+
+#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
+
+struct response_start_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t generated_response                                      :  3,
+                      __reserved_g_0012                                                  :  2,
+                      trig_response_related                                   :  1,
+                      response_sta_count                                      :  7,
+                      mba_for_cfp_ba                                          :  1,
+                      mba_for_cfp_ack                                         :  1,
+                      ects_response_type                                      :  2,
+                      eba_response_type                                       :  2,
+                      cfp_mba                                                 :  1,
+                      mba_for_ll_ack                                          :  1,
+                      mba_for_ll_ba                                           :  1,
+                      reserved                                                : 10;
+             uint32_t phy_ppdu_id                                             : 16,
+                      sw_peer_id                                              : 16;
+#else
+             uint32_t reserved                                                : 10,
+                      mba_for_ll_ba                                           :  1,
+                      mba_for_ll_ack                                          :  1,
+                      cfp_mba                                                 :  1,
+                      eba_response_type                                       :  2,
+                      ects_response_type                                      :  2,
+                      mba_for_cfp_ack                                         :  1,
+                      mba_for_cfp_ba                                          :  1,
+                      response_sta_count                                      :  7,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0012                                                  :  2,
+                      generated_response                                      :  3;
+             uint32_t sw_peer_id                                              : 16,
+                      phy_ppdu_id                                             : 16;
+#endif
+};
+
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB                                0
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB                                2
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK                               0x0000000000000007
+
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET                          0x0000000000000000
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK                            0x0000000000000020
+
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB                                6
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB                                12
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK                               0x0000000000001fc0
+
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET                                 0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB                                    13
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB                                    13
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK                                   0x0000000000002000
+
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET                                0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB                                   14
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB                                   14
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK                                  0x0000000000004000
+
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB                                15
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB                                16
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK                               0x0000000000018000
+
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET                              0x0000000000000000
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB                                 17
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB                                 18
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK                                0x0000000000060000
+
+#define RESPONSE_START_STATUS_CFP_MBA_OFFSET                                        0x0000000000000000
+#define RESPONSE_START_STATUS_CFP_MBA_LSB                                           19
+#define RESPONSE_START_STATUS_CFP_MBA_MSB                                           19
+#define RESPONSE_START_STATUS_CFP_MBA_MASK                                          0x0000000000080000
+
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET                                 0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB                                    20
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB                                    20
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK                                   0x0000000000100000
+
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET                                  0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB                                     21
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB                                     21
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK                                    0x0000000000200000
+
+#define RESPONSE_START_STATUS_RESERVED_OFFSET                                       0x0000000000000000
+#define RESPONSE_START_STATUS_RESERVED_LSB                                          22
+#define RESPONSE_START_STATUS_RESERVED_MSB                                          31
+#define RESPONSE_START_STATUS_RESERVED_MASK                                         0x00000000ffc00000
+
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET                                    0x0000000000000000
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB                                       32
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB                                       47
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK                                      0x0000ffff00000000
+
+#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET                                     0x0000000000000000
+#define RESPONSE_START_STATUS_SW_PEER_ID_LSB                                        48
+#define RESPONSE_START_STATUS_SW_PEER_ID_MSB                                        63
+#define RESPONSE_START_STATUS_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/ru_allocation_160_info.h b/hw/fig/v2/ru_allocation_160_info.h
new file mode 100644
index 000000000000..57d51dc44f8a
--- /dev/null
+++ b/hw/fig/v2/ru_allocation_160_info.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation_band0_0                                   :  9,
+                      ru_allocation_band0_1                                   :  9,
+                      reserved_0a                                             :  6,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      ru_allocations_23_subband80_mask                        :  4;
+             uint32_t ru_allocation_band0_2                                   :  9,
+                      ru_allocation_band0_3                                   :  9,
+                      reserved_1a                                             : 14;
+             uint32_t ru_allocation_band1_0                                   :  9,
+                      ru_allocation_band1_1                                   :  9,
+                      reserved_2a                                             : 14;
+             uint32_t ru_allocation_band1_2                                   :  9,
+                      ru_allocation_band1_3                                   :  9,
+                      reserved_3a                                             : 14;
+#else
+             uint32_t ru_allocations_23_subband80_mask                        :  4,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      reserved_0a                                             :  6,
+                      ru_allocation_band0_1                                   :  9,
+                      ru_allocation_band0_0                                   :  9;
+             uint32_t reserved_1a                                             : 14,
+                      ru_allocation_band0_3                                   :  9,
+                      ru_allocation_band0_2                                   :  9;
+             uint32_t reserved_2a                                             : 14,
+                      ru_allocation_band1_1                                   :  9,
+                      ru_allocation_band1_0                                   :  9;
+             uint32_t reserved_3a                                             : 14,
+                      ru_allocation_band1_3                                   :  9,
+                      ru_allocation_band1_2                                   :  9;
+#endif
+};
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
+
+#endif
diff --git a/hw/fig/v2/rx_attention.h b/hw/fig/v2/rx_attention.h
new file mode 100644
index 000000000000..cac7c2fb52c3
--- /dev/null
+++ b/hw/fig/v2/rx_attention.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+
+#define NUM_OF_DWORDS_RX_ATTENTION 4
+
+#define NUM_OF_QWORDS_RX_ATTENTION 2
+
+struct rx_attention {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_1a                                             :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      cce_match                                               :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      reserved_1b                                             :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      wifi_parser_error                                       :  1,
+                      amsdu_parser_error                                      :  1,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      msdu_limit_error                                        :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      sa_is_valid                                             :  1,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_2                                              : 17,
+                      msdu_done                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      reserved_1b                                             :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      cce_match                                               :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_1a                                             :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_2                                              : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      sa_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      msdu_limit_error                                        :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      amsdu_parser_error                                      :  1,
+                      wifi_parser_error                                       :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000000000000000
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x0000000000000003
+
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK                                         0x00000000000001fc
+
+#define RX_ATTENTION_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_RESERVED_0_LSB                                                 9
+#define RX_ATTENTION_RESERVED_0_MSB                                                 15
+#define RX_ATTENTION_RESERVED_0_MASK                                                0x000000000000fe00
+
+#define RX_ATTENTION_PHY_PPDU_ID_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_PHY_PPDU_ID_LSB                                                16
+#define RX_ATTENTION_PHY_PPDU_ID_MSB                                                31
+#define RX_ATTENTION_PHY_PPDU_ID_MASK                                               0x00000000ffff0000
+
+#define RX_ATTENTION_FIRST_MPDU_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_FIRST_MPDU_LSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MASK                                                0x0000000100000000
+
+#define RX_ATTENTION_RESERVED_1A_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1A_LSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MASK                                               0x0000000200000000
+
+#define RX_ATTENTION_MCAST_BCAST_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_MCAST_BCAST_LSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MASK                                               0x0000000400000000
+
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK                                       0x0000000800000000
+
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK                                         0x0000001000000000
+
+#define RX_ATTENTION_POWER_MGMT_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_POWER_MGMT_LSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MASK                                                0x0000002000000000
+
+#define RX_ATTENTION_NON_QOS_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_NON_QOS_LSB                                                    38
+#define RX_ATTENTION_NON_QOS_MSB                                                    38
+#define RX_ATTENTION_NON_QOS_MASK                                                   0x0000004000000000
+
+#define RX_ATTENTION_NULL_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_NULL_DATA_LSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MASK                                                 0x0000008000000000
+
+#define RX_ATTENTION_MGMT_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MGMT_TYPE_LSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MASK                                                 0x0000010000000000
+
+#define RX_ATTENTION_CTRL_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CTRL_TYPE_LSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MASK                                                 0x0000020000000000
+
+#define RX_ATTENTION_MORE_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MORE_DATA_LSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MASK                                                 0x0000040000000000
+
+#define RX_ATTENTION_EOSP_OFFSET                                                    0x0000000000000000
+#define RX_ATTENTION_EOSP_LSB                                                       43
+#define RX_ATTENTION_EOSP_MSB                                                       43
+#define RX_ATTENTION_EOSP_MASK                                                      0x0000080000000000
+
+#define RX_ATTENTION_A_MSDU_ERROR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_A_MSDU_ERROR_LSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MASK                                              0x0000100000000000
+
+#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET                                           0x0000000000000000
+#define RX_ATTENTION_FRAGMENT_FLAG_LSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MASK                                             0x0000200000000000
+
+#define RX_ATTENTION_ORDER_OFFSET                                                   0x0000000000000000
+#define RX_ATTENTION_ORDER_LSB                                                      46
+#define RX_ATTENTION_ORDER_MSB                                                      46
+#define RX_ATTENTION_ORDER_MASK                                                     0x0000400000000000
+
+#define RX_ATTENTION_CCE_MATCH_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CCE_MATCH_LSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MASK                                                 0x0000800000000000
+
+#define RX_ATTENTION_OVERFLOW_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_OVERFLOW_ERR_LSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MASK                                              0x0001000000000000
+
+#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK                                           0x0002000000000000
+
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK                                       0x0004000000000000
+
+#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK                                            0x0008000000000000
+
+#define RX_ATTENTION_SA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_SA_IDX_INVALID_LSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MASK                                            0x0010000000000000
+
+#define RX_ATTENTION_DA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_DA_IDX_INVALID_LSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MASK                                            0x0020000000000000
+
+#define RX_ATTENTION_RESERVED_1B_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1B_LSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MASK                                               0x0040000000000000
+
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET                                    0x0000000000000000
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK                                      0x0080000000000000
+
+#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET                                        0x0000000000000000
+#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK                                          0x0100000000000000
+
+#define RX_ATTENTION_DIRECTED_OFFSET                                                0x0000000000000000
+#define RX_ATTENTION_DIRECTED_LSB                                                   57
+#define RX_ATTENTION_DIRECTED_MSB                                                   57
+#define RX_ATTENTION_DIRECTED_MASK                                                  0x0200000000000000
+
+#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_BUFFER_FRAGMENT_LSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MASK                                           0x0400000000000000
+
+#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK                                           0x0800000000000000
+
+#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_TKIP_MIC_ERR_LSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MASK                                              0x1000000000000000
+
+#define RX_ATTENTION_DECRYPT_ERR_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_DECRYPT_ERR_LSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MASK                                               0x2000000000000000
+
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET                                   0x0000000000000000
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK                                     0x4000000000000000
+
+#define RX_ATTENTION_FCS_ERR_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_FCS_ERR_LSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MASK                                                   0x8000000000000000
+
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK                                          0x0000000000000001
+
+#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_INVALID_LSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MASK                                          0x0000000000000002
+
+#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET                                       0x0000000000000008
+#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK                                         0x0000000000000004
+
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET                                      0x0000000000000008
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK                                        0x0000000000000008
+
+#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK                                            0x0000000000000010
+
+#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK                                            0x0000000000000020
+
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK                                          0x0000000000000040
+
+#define RX_ATTENTION_DA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_DA_IS_VALID_LSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MASK                                               0x0000000000000080
+
+#define RX_ATTENTION_DA_IS_MCBC_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_DA_IS_MCBC_LSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MASK                                                0x0000000000000100
+
+#define RX_ATTENTION_SA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_SA_IS_VALID_LSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MASK                                               0x0000000000000200
+
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET                                     0x0000000000000008
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB                                        10
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB                                        12
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK                                       0x0000000000001c00
+
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET                                   0x0000000000000008
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK                                     0x0000000000002000
+
+#define RX_ATTENTION_RESERVED_2_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_RESERVED_2_LSB                                                 14
+#define RX_ATTENTION_RESERVED_2_MSB                                                 30
+#define RX_ATTENTION_RESERVED_2_MASK                                                0x000000007fffc000
+
+#define RX_ATTENTION_MSDU_DONE_OFFSET                                               0x0000000000000008
+#define RX_ATTENTION_MSDU_DONE_LSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MASK                                                 0x0000000080000000
+
+#define RX_ATTENTION_TLV64_PADDING_OFFSET                                           0x0000000000000008
+#define RX_ATTENTION_TLV64_PADDING_LSB                                              32
+#define RX_ATTENTION_TLV64_PADDING_MSB                                              63
+#define RX_ATTENTION_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_flow_search_entry.h b/hw/fig/v2/rx_flow_search_entry.h
new file mode 100644
index 000000000000..25f1f81c439f
--- /dev/null
+++ b/hw/fig/v2/rx_flow_search_entry.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t src_port                                                : 16,
+                      dest_port                                               : 16;
+             uint32_t l4_protocol                                             :  8,
+                      valid                                                   :  1,
+                      reserved_9                                              :  4,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      use_ppe                                                 :  1,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1,
+                      reo_destination_handler                                 :  2;
+             uint32_t metadata                                                : 32;
+             uint32_t aggregation_count                                       :  7,
+                      lro_eligible                                            :  1,
+                      msdu_count                                              : 24;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length_pmac1                              : 16,
+                      cumulative_ip_length                                    : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#else
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t dest_port                                               : 16,
+                      src_port                                                : 16;
+             uint32_t reo_destination_handler                                 :  2,
+                      msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      use_ppe                                                 :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_9                                              :  4,
+                      valid                                                   :  1,
+                      l4_protocol                                             :  8;
+             uint32_t metadata                                                : 32;
+             uint32_t msdu_count                                              : 24,
+                      lro_eligible                                            :  1,
+                      aggregation_count                                       :  7;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length                                    : 16,
+                      cumulative_ip_length_pmac1                              : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#endif
+};
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET                                   0x00000000
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET                                    0x00000004
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET                                    0x00000008
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET                                     0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB                                        31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK                                       0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET                                  0x00000010
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB                                     0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB                                     31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK                                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET                                   0x00000014
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET                                   0x00000018
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET                                    0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET                                        0x00000020
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB                                           15
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK                                          0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET                                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB                                          16
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK                                         0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET                                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB                                        7
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK                                       0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET                                           0x00000024
+#define RX_FLOW_SEARCH_ENTRY_VALID_LSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MASK                                             0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET                                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB                                         9
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB                                         12
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK                                        0x00001e00
+
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET                                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB                                       13
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB                                       21
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK                                      0x003fe000
+
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET                                  0x00000024
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK                                    0x00400000
+
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET                                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK                                           0x00800000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB                         24
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB                         28
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK                        0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET                                       0x00000024
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK                                         0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB                            30
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB                            31
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK                           0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET                                        0x00000028
+#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB                                           31
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK                                          0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET                               0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB                                  0
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB                                  6
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK                                 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET                                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK                                      0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET                                      0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB                                         8
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB                                         31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK                                        0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET                                 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB                                    0
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB                                    31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK                                   0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET                                       0x00000034
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB                                          0
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK                                         0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET                      0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB                         15
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK                        0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET                            0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB                               16
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB                               31
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK                              0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET                             0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB                                0
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB                                31
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK                               0xffffffff
+
+#endif
diff --git a/hw/fig/v2/rx_frame_1k_bitmap_ack.h b/hw/fig/v2/rx_frame_1k_bitmap_ack.h
new file mode 100644
index 000000000000..a43548b14a07
--- /dev/null
+++ b/hw/fig/v2/rx_frame_1k_bitmap_ack.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
+#define _RX_FRAME_1K_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38
+
+#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19
+
+struct rx_frame_1k_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  5,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0b                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0c                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      reserved_1a                                             : 20;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#else
+             uint32_t reserved_0c                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0b                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0a                                             :  5;
+             uint32_t reserved_1a                                             : 20,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#endif
+};
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB                                      4
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK                                     0x000000000000001f
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                   5
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                   6
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                  0x0000000000000060
+
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                            0x0000000000000080
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB                                      8
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB                                      9
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK                                     0x0000000000000300
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET                                        0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB                                           10
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB                                           13
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK                                          0x0000000000003c00
+
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB                                     14
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB                                     26
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK                                    0x0000000007ffc000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB                                      27
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK                                     0x00000000f8000000
+
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB                                       41
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK                                      0x000003ff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                            0x0000040000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                           0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                             0x0000080000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB                                      44
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB                                      63
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK                                     0xfffff00000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB                                       0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB                                       31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK                                      0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET                                   0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB                                      32
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB                                      47
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK                                     0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB                                       48
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB                                       63
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK                                      0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET                                   0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK                                     0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET                                    0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB                                       47
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK                                      0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET                                     0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB                                        48
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB                                        63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK                                       0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                             0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                            0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                               32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                               63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                              0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                            0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                               0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                               31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                              0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                           0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                              32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                              63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                             0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET                          0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET                         0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB                            32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB                            63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_frame_bitmap_ack.h b/hw/fig/v2/rx_frame_bitmap_ack.h
new file mode 100644
index 000000000000..0b68486b038e
--- /dev/null
+++ b/hw/fig/v2/rx_frame_bitmap_ack.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_ACK_H_
+#define _RX_FRAME_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7
+
+struct rx_frame_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_bitmap_available                                     :  1,
+                      explicit_ack                                            :  1,
+                      explict_ack_type                                        :  3,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0a                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0b                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_32_allowed                                      :  1,
+                      reserved_1a                                             : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#else
+             uint32_t reserved_0b                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0a                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      explict_ack_type                                        :  3,
+                      explicit_ack                                            :  1,
+                      no_bitmap_available                                     :  1;
+             uint32_t reserved_1a                                             : 16,
+                      ba_size_32_allowed                                      :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK                                0x0000000000000001
+
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK                                       0x0000000000000002
+
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET                                 0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB                                    2
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB                                    4
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK                                   0x000000000000001c
+
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                   0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                      5
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                      6
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                     0x0000000000000060
+
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                               0x0000000000000080
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB                                         8
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB                                         9
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK                                        0x0000000000000300
+
+#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET                                           0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_TID_LSB                                              10
+#define RX_FRAME_BITMAP_ACK_BA_TID_MSB                                              13
+#define RX_FRAME_BITMAP_ACK_BA_TID_MASK                                             0x0000000000003c00
+
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB                                        14
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB                                        26
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK                                       0x0000000007ffc000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB                                         27
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK                                        0x00000000f8000000
+
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB                                          41
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK                                         0x000003ff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                               0x0000040000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                                0x0000080000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK                                0x0000100000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK                                0x0000200000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK                                 0x0000400000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK                                 0x0000800000000000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB                                         48
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB                                         63
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB                                          0
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB                                          31
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK                                         0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET                                      0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB                                         32
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB                                         47
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK                                        0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB                                          48
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB                                          63
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK                                         0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET                                      0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB                                         0
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK                                        0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET                                       0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB                                          47
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK                                         0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET                                        0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB                                           48
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB                                           63
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK                                          0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                                0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                   0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                   31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                               0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                                  32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                                  63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                                 0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                               0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                                  0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                                  31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                                 0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                              0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                                 32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                                 63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                                0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                               0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                               0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_frame_bitmap_req.h b/hw/fig/v2/rx_frame_bitmap_req.h
new file mode 100644
index 000000000000..24f8ddd1c57c
--- /dev/null
+++ b/hw/fig/v2/rx_frame_bitmap_req.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_REQ_H_
+#define _RX_FRAME_BITMAP_REQ_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1
+
+struct rx_frame_bitmap_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t explicit_user_request                                   :  1,
+                      user_request_type                                       :  1,
+                      user_number                                             :  6,
+                      sw_peer_id                                              : 16,
+                      tid_specific_request                                    :  1,
+                      requested_tid                                           :  4,
+                      reserved_0                                              :  3;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  3,
+                      requested_tid                                           :  4,
+                      tid_specific_request                                    :  1,
+                      sw_peer_id                                              : 16,
+                      user_number                                             :  6,
+                      user_request_type                                       :  1,
+                      explicit_user_request                                   :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET                            0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK                              0x0000000000000001
+
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET                                0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK                                  0x0000000000000002
+
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB                                         2
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB                                         7
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK                                        0x00000000000000fc
+
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB                                          8
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB                                          23
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK                                         0x0000000000ffff00
+
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK                               0x0000000001000000
+
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB                                       25
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB                                       28
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK                                      0x000000001e000000
+
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB                                          29
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB                                          31
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK                                         0x00000000e0000000
+
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB                                       32
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB                                       63
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK                                      0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_location_info.h b/hw/fig/v2/rx_location_info.h
new file mode 100644
index 000000000000..ee000f6d4cda
--- /dev/null
+++ b/hw/fig/v2/rx_location_info.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
+
+struct rx_location_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_location_info_valid                                  :  1,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rtt___reserved_g_0020_mode                                           :  2,
+                      reserved_0                                              :  4,
+                      rtt_num_fac                                             :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_streams                                         :  8;
+             uint32_t rtt_first_selected_chain                                :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_cir_status                                          :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_che_buffer_pointer_high8                            :  8,
+                      reserved_3                                              :  8,
+                      rtt_pkt_bw_vht                                          :  4,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_mcs_rate                                            :  8;
+             uint32_t rtt_cfo_measurement                                     : 16,
+                      rtt_preamble_type                                       :  8,
+                      rtt_gi_type                                             :  8;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain0                                             : 16,
+                      gain_chain1                                             : 16;
+             uint32_t gain_chain2                                             : 16,
+                      gain_chain3                                             : 16;
+             uint32_t gain_report_status                                      :  8,
+                      rtt_timing_backoff_sel                                  :  8,
+                      rtt_fac_combined                                        : 16;
+             uint32_t rtt_fac_0                                               : 16,
+                      rtt_fac_1                                               : 16;
+             uint32_t rtt_fac_2                                               : 16,
+                      rtt_fac_3                                               : 16;
+             uint32_t rtt_fac_4                                               : 16,
+                      rtt_fac_5                                               : 16;
+             uint32_t rtt_fac_6                                               : 16,
+                      rtt_fac_7                                               : 16;
+             uint32_t rtt_fac_8                                               : 16,
+                      rtt_fac_9                                               : 16;
+             uint32_t rtt_fac_10                                              : 16,
+                      rtt_fac_11                                              : 16;
+             uint32_t rtt_fac_12                                              : 16,
+                      rtt_fac_13                                              : 16;
+             uint32_t rtt_fac_14                                              : 16,
+                      rtt_fac_15                                              : 16;
+             uint32_t rtt_fac_16                                              : 16,
+                      rtt_fac_17                                              : 16;
+             uint32_t rtt_fac_18                                              : 16,
+                      rtt_fac_19                                              : 16;
+             uint32_t rtt_fac_20                                              : 16,
+                      rtt_fac_21                                              : 16;
+             uint32_t rtt_fac_22                                              : 16,
+                      rtt_fac_23                                              : 16;
+             uint32_t rtt_fac_24                                              : 16,
+                      rtt_fac_25                                              : 16;
+             uint32_t rtt_fac_26                                              : 16,
+                      rtt_fac_27                                              : 16;
+             uint32_t rtt_fac_28                                              : 16,
+                      rtt_fac_29                                              : 16;
+             uint32_t rtt_fac_30                                              : 16,
+                      rtt_fac_31                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#else
+             uint32_t rtt_num_streams                                         :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_fac                                             :  8,
+                      reserved_0                                              :  4,
+                      rtt___reserved_g_0020_mode                                           :  2,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rx_location_info_valid                                  :  1;
+             uint32_t rtt_cir_status                                          :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_first_selected_chain                                :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_mcs_rate                                            :  8,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_pkt_bw_vht                                          :  4,
+                      reserved_3                                              :  8,
+                      rtt_che_buffer_pointer_high8                            :  8;
+             uint32_t rtt_gi_type                                             :  8,
+                      rtt_preamble_type                                       :  8,
+                      rtt_cfo_measurement                                     : 16;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain1                                             : 16,
+                      gain_chain0                                             : 16;
+             uint32_t gain_chain3                                             : 16,
+                      gain_chain2                                             : 16;
+             uint32_t rtt_fac_combined                                        : 16,
+                      rtt_timing_backoff_sel                                  :  8,
+                      gain_report_status                                      :  8;
+             uint32_t rtt_fac_1                                               : 16,
+                      rtt_fac_0                                               : 16;
+             uint32_t rtt_fac_3                                               : 16,
+                      rtt_fac_2                                               : 16;
+             uint32_t rtt_fac_5                                               : 16,
+                      rtt_fac_4                                               : 16;
+             uint32_t rtt_fac_7                                               : 16,
+                      rtt_fac_6                                               : 16;
+             uint32_t rtt_fac_9                                               : 16,
+                      rtt_fac_8                                               : 16;
+             uint32_t rtt_fac_11                                              : 16,
+                      rtt_fac_10                                              : 16;
+             uint32_t rtt_fac_13                                              : 16,
+                      rtt_fac_12                                              : 16;
+             uint32_t rtt_fac_15                                              : 16,
+                      rtt_fac_14                                              : 16;
+             uint32_t rtt_fac_17                                              : 16,
+                      rtt_fac_16                                              : 16;
+             uint32_t rtt_fac_19                                              : 16,
+                      rtt_fac_18                                              : 16;
+             uint32_t rtt_fac_21                                              : 16,
+                      rtt_fac_20                                              : 16;
+             uint32_t rtt_fac_23                                              : 16,
+                      rtt_fac_22                                              : 16;
+             uint32_t rtt_fac_25                                              : 16,
+                      rtt_fac_24                                              : 16;
+             uint32_t rtt_fac_27                                              : 16,
+                      rtt_fac_26                                              : 16;
+             uint32_t rtt_fac_29                                              : 16,
+                      rtt_fac_28                                              : 16;
+             uint32_t rtt_fac_31                                              : 16,
+                      rtt_fac_30                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#endif
+};
+
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET                              0x00000000
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK                                0x00000001
+
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET                                    0x00000000
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK                                      0x00000002
+
+#define RX_LOCATION_INFO_RESERVED_0_OFFSET                                          0x00000000
+#define RX_LOCATION_INFO_RESERVED_0_LSB                                             4
+#define RX_LOCATION_INFO_RESERVED_0_MSB                                             7
+#define RX_LOCATION_INFO_RESERVED_0_MASK                                            0x000000f0
+
+#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET                                         0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB                                            8
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB                                            15
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK                                           0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET                                   0x00000000
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB                                      16
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB                                      23
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET                                     0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB                                        24
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB                                        31
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK                                       0xff000000
+
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET                            0x00000004
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB                               0
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB                               7
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK                              0x000000ff
+
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET                           0x00000004
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB                              8
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB                              15
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK                             0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB                                         16
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB                                         23
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK                                        0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB                                         24
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB                                         31
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK                                        0xff000000
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET                        0x00000008
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB                           31
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK                          0xffffffff
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET                        0x0000000c
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB                           7
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK                          0x000000ff
+
+#define RX_LOCATION_INFO_RESERVED_3_OFFSET                                          0x0000000c
+#define RX_LOCATION_INFO_RESERVED_3_LSB                                             8
+#define RX_LOCATION_INFO_RESERVED_3_MSB                                             15
+#define RX_LOCATION_INFO_RESERVED_3_MASK                                            0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB                                         16
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB                                         19
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK                                        0x000f0000
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB                                         20
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB                                         23
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK                                        0x00f00000
+
+#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET                                        0x0000000c
+#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB                                           24
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB                                           31
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK                                          0xff000000
+
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET                                 0x00000010
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB                                    0
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB                                    15
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK                                   0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET                                   0x00000010
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB                                      16
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB                                      23
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET                                         0x00000010
+#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB                                            24
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB                                            31
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK                                           0xff000000
+
+#define RX_LOCATION_INFO_RX_START_TS_OFFSET                                         0x00000014
+#define RX_LOCATION_INFO_RX_START_TS_LSB                                            0
+#define RX_LOCATION_INFO_RX_START_TS_MSB                                            31
+#define RX_LOCATION_INFO_RX_START_TS_MASK                                           0xffffffff
+
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET                                   0x00000018
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB                                      0
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB                                      31
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK                                     0xffffffff
+
+#define RX_LOCATION_INFO_RX_END_TS_OFFSET                                           0x0000001c
+#define RX_LOCATION_INFO_RX_END_TS_LSB                                              0
+#define RX_LOCATION_INFO_RX_END_TS_MSB                                              31
+#define RX_LOCATION_INFO_RX_END_TS_MASK                                             0xffffffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET                                  0x00000028
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB                                     0
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB                                     7
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK                                    0x000000ff
+
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET                              0x00000028
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB                                 8
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB                                 15
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK                                0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET                                    0x00000028
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB                                       16
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB                                       31
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK                                      0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_0_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_0_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_0_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_1_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_1_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_1_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_2_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_2_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_2_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_3_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_3_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_3_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_4_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_4_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_4_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_5_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_5_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_5_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_6_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_6_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_6_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_7_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_7_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_7_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_8_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_8_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_8_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_9_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_9_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_9_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_10_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_10_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_10_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_11_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_11_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_11_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_12_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_12_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_12_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_13_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_13_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_13_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_14_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_14_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_14_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_15_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_15_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_15_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_16_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_16_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_16_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_17_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_17_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_17_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_18_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_18_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_18_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_19_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_19_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_19_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_20_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_20_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_20_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_21_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_21_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_21_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_22_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_22_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_22_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_23_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_23_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_23_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_24_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_24_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_24_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_25_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_25_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_25_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_26_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_26_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_26_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_27_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_27_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_27_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_28_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_28_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_28_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_29_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_29_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_29_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_30_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_30_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_30_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_31_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_31_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_31_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RESERVED_27A_OFFSET                                        0x0000006c
+#define RX_LOCATION_INFO_RESERVED_27A_LSB                                           0
+#define RX_LOCATION_INFO_RESERVED_27A_MSB                                           31
+#define RX_LOCATION_INFO_RESERVED_27A_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_desc_info.h b/hw/fig/v2/rx_mpdu_desc_info.h
new file mode 100644
index 000000000000..30f538fb1228
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_desc_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_count                                              :  8,
+                      fragment_flag                                           :  1,
+                      mpdu_retry_bit                                          :  1,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      raw_mpdu                                                :  1,
+                      more_fragment_flag                                      :  1,
+                      src_info                                                : 12,
+                      mpdu_qos_control_valid                                  :  1,
+                      tid                                                     :  4;
+             uint32_t peer_meta_data                                          : 32;
+#else
+             uint32_t tid                                                     :  4,
+                      mpdu_qos_control_valid                                  :  1,
+                      src_info                                                : 12,
+                      more_fragment_flag                                      :  1,
+                      raw_mpdu                                                :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      mpdu_retry_bit                                          :  1,
+                      fragment_flag                                           :  1,
+                      msdu_count                                              :  8;
+             uint32_t peer_meta_data                                          : 32;
+#endif
+};
+
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
+
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
+
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
+
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
+
+#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
+#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
+
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
+
+#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
+
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
+
+#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_SRC_INFO_LSB                                              15
+#define RX_MPDU_DESC_INFO_SRC_INFO_MSB                                              26
+#define RX_MPDU_DESC_INFO_SRC_INFO_MASK                                             0x07ff8000
+
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
+
+#define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
+#define RX_MPDU_DESC_INFO_TID_LSB                                                   28
+#define RX_MPDU_DESC_INFO_TID_MSB                                                   31
+#define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
+
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_details.h b/hw/fig/v2/rx_mpdu_details.h
new file mode 100644
index 000000000000..d2d96a0a9996
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_details.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+
+#include "rx_mpdu_ext_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6
+
+struct rx_mpdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB               0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB              0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB              7
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB               12
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                    0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                    7
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK                   0x000000ff
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET              0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK                0x00000100
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET             0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK               0x00000200
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK                   0x00000400
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET                  0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                    0x00000800
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                     0x00002000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET         0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK           0x00004000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                      15
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                      26
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                     0x07ff8000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET     0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK       0x08000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                        0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                           28
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                           31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                          0xf0000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET             0x0000000c
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB                0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB                31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK               0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET                0x00000010
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB                   0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB                   31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK                  0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET               0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB                  0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB                  15
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK                 0x0000ffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET         0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB            16
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB            17
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK           0x00030000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET   0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB      18
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB      21
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK     0x003c0000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET            0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB               22
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB               31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK              0xffc00000
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_end.h b/hw/fig/v2/rx_mpdu_end.h
new file mode 100644
index 000000000000..dc54ea129fdd
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_end.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_END 4
+
+#define NUM_OF_QWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_1a                                             :  9,
+                      cfp_mic_err                                             :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      overflow_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      fcs_err                                                 :  1,
+                      msdu_length_err                                         :  1,
+                      reserved1c                                              :  6,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      ifcs_present                                            :  1;
+             uint32_t mpdu_crc_ok_intermediate_fcs                            :  1,
+                      mpdu_length_intermediate_fcs                            : 14,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      rxpcu_mgmt_sequence_nr                                  : 16;
+             uint32_t __reserved_g_0002                                       : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t ifcs_present                                            :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved1c                                              :  6,
+                      msdu_length_err                                         :  1,
+                      fcs_err                                                 :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      cfp_mic_err                                             :  1,
+                      reserved_1a                                             :  9;
+             uint32_t rxpcu_mgmt_sequence_nr                                  : 16,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      mpdu_length_intermediate_fcs                            : 14,
+                      mpdu_crc_ok_intermediate_fcs                            :  1;
+             uint32_t __reserved_g_0002                                       : 32;
+#endif
+};
+
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MPDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED_0_LSB                                                  9
+#define RX_MPDU_END_RESERVED_0_MSB                                                  15
+#define RX_MPDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MPDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MPDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MPDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MPDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_RESERVED_1A_LSB                                                 32
+#define RX_MPDU_END_RESERVED_1A_MSB                                                 40
+#define RX_MPDU_END_RESERVED_1A_MASK                                                0x000001ff00000000
+
+#define RX_MPDU_END_CFP_MIC_ERR_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_CFP_MIC_ERR_LSB                                                 41
+#define RX_MPDU_END_CFP_MIC_ERR_MSB                                                 41
+#define RX_MPDU_END_CFP_MIC_ERR_MASK                                                0x0000020000000000
+
+#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET                                           0x0000000000000000
+#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB                                              42
+#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB                                              42
+#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK                                             0x0000040000000000
+
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET                                  0x0000000000000000
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK                                    0x0000080000000000
+
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000000
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000100000000000
+
+#define RX_MPDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_OVERFLOW_ERR_LSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MASK                                               0x0000200000000000
+
+#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000400000000000
+
+#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_TKIP_MIC_ERR_LSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MASK                                               0x0000800000000000
+
+#define RX_MPDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_DECRYPT_ERR_LSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MASK                                                0x0001000000000000
+
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0002000000000000
+
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                             0x0000000000000000
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK                               0x0004000000000000
+
+#define RX_MPDU_END_FCS_ERR_OFFSET                                                  0x0000000000000000
+#define RX_MPDU_END_FCS_ERR_LSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MASK                                                    0x0008000000000000
+
+#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK                                            0x0010000000000000
+
+#define RX_MPDU_END_RESERVED1C_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED1C_LSB                                                  53
+#define RX_MPDU_END_RESERVED1C_MSB                                                  58
+#define RX_MPDU_END_RESERVED1C_MASK                                                 0x07e0000000000000
+
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000000
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB                                         59
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB                                         61
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK                                        0x3800000000000000
+
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x4000000000000000
+
+#define RX_MPDU_END_IFCS_PRESENT_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_IFCS_PRESENT_LSB                                                63
+#define RX_MPDU_END_IFCS_PRESENT_MSB                                                63
+#define RX_MPDU_END_IFCS_PRESENT_MASK                                               0x8000000000000000
+
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB                                0
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB                                0
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK                               0x0000000000000001
+
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB                                1
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB                                14
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK                               0x0000000000007ffe
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK                               0x0000000000008000
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET                                   0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB                                      16
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB                                      31
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK                                     0x00000000ffff0000
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_ext_desc_info.h b/hw/fig/v2/rx_mpdu_ext_desc_info.h
new file mode 100644
index 000000000000..83f4df333c88
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_ext_desc_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_EXT_DESC_INFO_H_
+#define _RX_MPDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2
+
+struct rx_mpdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      pn_127_48_info                                          :  2,
+                      msdu_link_desc_index                                    :  4,
+                      reserved_1a                                             : 10;
+#else
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t reserved_1a                                             : 10,
+                      msdu_link_desc_index                                    :  4,
+                      pn_127_48_info                                          :  2,
+                      pn_47_32                                                : 16;
+#endif
+};
+
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET                                        0x00000000
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB                                           0
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB                                           31
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK                                          0xffffffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET                                       0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB                                          0
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB                                          15
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK                                         0x0000ffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET                                 0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB                                    16
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB                                    17
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK                                   0x00030000
+
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET                           0x00000004
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB                              18
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB                              21
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK                             0x003c0000
+
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET                                    0x00000004
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB                                       22
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB                                       31
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK                                      0xffc00000
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_info.h b/hw/fig/v2/rx_mpdu_info.h
new file mode 100644
index 000000000000..7a3e9a8d525a
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_info.h
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+
+#include "rxpt_classify_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_INFO 30
+
+struct rx_mpdu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t epd_en                                                  :  1,
+                      all_frames_shall_be_encrypted                           :  1,
+                      encrypt_type                                            :  4,
+                      wep_key_width_for_variable_key                          :  2,
+                      __reserved_g_0003                                                :  2,
+                      bssid_hit                                               :  1,
+                      bssid_number                                            :  4,
+                      tid                                                     :  4,
+                      reserved_7a                                             : 13;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      receive_queue_number                                    : 16,
+                      pre_delim_err_warning                                   :  1,
+                      first_delim_err                                         :  1,
+                      reserved_2a                                             :  6;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_frame_control_valid                                :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_fragment_number                                    :  4,
+                      more_fragment_flag                                      :  1,
+                      protected_cbf_cqi                                       :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      encrypted                                               :  1,
+                      mpdu_retry                                              :  1,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t ast_index                                               : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      ndp_frame                                               :  1,
+                      phy_err                                                 :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      protocol_version_err                                    :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      __reserved_g_0035                                                 :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t key_id_octet                                            :  8,
+                      new_peer_entry                                          :  1,
+                      decrypt_needed                                          :  1,
+                      decap_type                                              :  2,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      pre_delim_count                                         : 12,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      raw_mpdu                                                :  1,
+                      reserved_12                                             :  1;
+             uint32_t mpdu_length                                             : 14,
+                      first_mpdu                                              :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      u_apsd_trigger                                          :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      amsdu_present                                           :  1,
+                      reserved_13                                             :  1;
+             uint32_t mpdu_frame_control_field                                : 16,
+                      mpdu_duration_field                                     : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad1_47_32                                      : 16,
+                      mac_addr_ad2_15_0                                       : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mac_addr_ad3_47_32                                      : 16,
+                      mpdu_sequence_control_field                             : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mac_addr_ad4_47_32                                      : 16,
+                      mpdu_qos_control_field                                  : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t vdev_id                                                 :  8,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      src_info                                                : 12,
+                      smr_frame                                               :  1,
+                      __reserved_g_0029                                       :  1;
+             uint32_t __reserved_g_0060                                       : 32;
+             uint32_t __reserved_g_0057                                       : 16,
+                      __reserved_g_0059                                       : 16;
+             uint32_t __reserved_g_0056                                       : 32;
+             uint32_t authorized_to_send_wds                                  :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      rx_misc_config                                          :  3,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      multi_link_ds_addr_fromtods_00_raw_en                   :  1,
+                      multi_link_ds_addr_fromtods_non00_raw_en                :  1,
+                      multi_link_ds_addr_ad3_valid                            :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      multi_link_ds_addr_mgmt_en                              :  1,
+                      multi_link_ds_addr_ctrl_en                              :  1,
+                      reserved_27a                                            :  5;
+             uint32_t multi_link_ds_addr_ad3_31_0                             : 32;
+             uint32_t multi_link_ds_addr_ad3_47_32                            : 16,
+                      cfp_mic_err                                             :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      reserved_29a                                            : 14;
+#else
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t reserved_7a                                             : 13,
+                      tid                                                     :  4,
+                      bssid_number                                            :  4,
+                      bssid_hit                                               :  1,
+                      __reserved_g_0003                                                :  2,
+                      wep_key_width_for_variable_key                          :  2,
+                      encrypt_type                                            :  4,
+                      all_frames_shall_be_encrypted                           :  1,
+                      epd_en                                                  :  1;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             :  6,
+                      first_delim_err                                         :  1,
+                      pre_delim_err_warning                                   :  1,
+                      receive_queue_number                                    : 16,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      mpdu_retry                                              :  1,
+                      encrypted                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      protected_cbf_cqi                                       :  1,
+                      more_fragment_flag                                      :  1,
+                      mpdu_fragment_number                                    :  4,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mpdu_frame_control_valid                                :  1;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      ast_index                                               : 16;
+             uint32_t phy_ppdu_id                                             : 16,
+                      __reserved_g_0035                                                 :  1,
+                      __reserved_g_0022                                                 :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      protocol_version_err                                    :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      phy_err                                                 :  1,
+                      ndp_frame                                               :  1,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_12                                             :  1,
+                      raw_mpdu                                                :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      pre_delim_count                                         : 12,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      decap_type                                              :  2,
+                      decrypt_needed                                          :  1,
+                      new_peer_entry                                          :  1,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_13                                             :  1,
+                      amsdu_present                                           :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      u_apsd_trigger                                          :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      first_mpdu                                              :  1,
+                      mpdu_length                                             : 14;
+             uint32_t mpdu_duration_field                                     : 16,
+                      mpdu_frame_control_field                                : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad2_15_0                                       : 16,
+                      mac_addr_ad1_47_32                                      : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mpdu_sequence_control_field                             : 16,
+                      mac_addr_ad3_47_32                                      : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mpdu_qos_control_field                                  : 16,
+                      mac_addr_ad4_47_32                                      : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t __reserved_g_0029                                       :  1,
+                      smr_frame                                               :  1,
+                      src_info                                                : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      vdev_id                                                 :  8;
+             uint32_t __reserved_g_0060                                       : 32;
+             uint32_t __reserved_g_0059                                       : 16,
+                      __reserved_g_0057                                       : 16;
+             uint32_t __reserved_g_0056                                       : 32;
+             uint32_t reserved_27a                                            :  5,
+                      multi_link_ds_addr_ctrl_en                              :  1,
+                      multi_link_ds_addr_mgmt_en                              :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_ds_addr_ad3_valid                            :  1,
+                      multi_link_ds_addr_fromtods_non00_raw_en                :  1,
+                      multi_link_ds_addr_fromtods_00_raw_en                   :  1,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      rx_misc_config                                          :  3,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      authorized_to_send_wds                                  :  1;
+             uint32_t multi_link_ds_addr_ad3_31_0                             : 32;
+             uint32_t reserved_29a                                            : 14,
+                      cfp_pn_chk_err                                          :  1,
+                      cfp_mic_err                                             :  1,
+                      multi_link_ds_addr_ad3_47_32                            : 16;
+#endif
+};
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET   0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB      0
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB      4
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK     0x0000001f
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET             0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB                5
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB                6
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK               0x00000060
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET    0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK      0x00000080
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK    0x00000100
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK    0x00000200
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET        0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK          0x00000400
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB    11
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB    13
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK   0x00003800
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK         0x00020000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK         0x00040000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK              0x00080000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET                      0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK                        0x00100000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET           0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK             0x00200000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK              0x00400000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET                  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB                     23
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB                     31
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK                    0xff800000
+
+#define RX_MPDU_INFO_EPD_EN_OFFSET                                                  0x00000004
+#define RX_MPDU_INFO_EPD_EN_LSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MASK                                                    0x00000001
+
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET                           0x00000004
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK                             0x00000002
+
+#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB                                               2
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB                                               5
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK                                              0x0000003c
+
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET                          0x00000004
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB                             6
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB                             7
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK                            0x000000c0
+
+#define RX_MPDU_INFO_BSSID_HIT_OFFSET                                               0x00000004
+#define RX_MPDU_INFO_BSSID_HIT_LSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MASK                                                 0x00000400
+
+#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_BSSID_NUMBER_LSB                                               11
+#define RX_MPDU_INFO_BSSID_NUMBER_MSB                                               14
+#define RX_MPDU_INFO_BSSID_NUMBER_MASK                                              0x00007800
+
+#define RX_MPDU_INFO_TID_OFFSET                                                     0x00000004
+#define RX_MPDU_INFO_TID_LSB                                                        15
+#define RX_MPDU_INFO_TID_MSB                                                        18
+#define RX_MPDU_INFO_TID_MASK                                                       0x00078000
+
+#define RX_MPDU_INFO_RESERVED_7A_OFFSET                                             0x00000004
+#define RX_MPDU_INFO_RESERVED_7A_LSB                                                19
+#define RX_MPDU_INFO_RESERVED_7A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_7A_MASK                                               0xfff80000
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                             0x00000008
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                                0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                                31
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                            0x0000000c
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                               0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                               7
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                              0x000000ff
+
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x0000000c
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB                                       8
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB                                       23
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK                                      0x00ffff00
+
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET                                   0x0000000c
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK                                     0x01000000
+
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET                                         0x0000000c
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK                                           0x02000000
+
+#define RX_MPDU_INFO_RESERVED_2A_OFFSET                                             0x0000000c
+#define RX_MPDU_INFO_RESERVED_2A_LSB                                                26
+#define RX_MPDU_INFO_RESERVED_2A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_2A_MASK                                               0xfc000000
+
+#define RX_MPDU_INFO_PN_31_0_OFFSET                                                 0x00000010
+#define RX_MPDU_INFO_PN_31_0_LSB                                                    0
+#define RX_MPDU_INFO_PN_31_0_MSB                                                    31
+#define RX_MPDU_INFO_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_MPDU_INFO_PN_63_32_OFFSET                                                0x00000014
+#define RX_MPDU_INFO_PN_63_32_LSB                                                   0
+#define RX_MPDU_INFO_PN_63_32_MSB                                                   31
+#define RX_MPDU_INFO_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_95_64_OFFSET                                                0x00000018
+#define RX_MPDU_INFO_PN_95_64_LSB                                                   0
+#define RX_MPDU_INFO_PN_95_64_MSB                                                   31
+#define RX_MPDU_INFO_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_127_96_OFFSET                                               0x0000001c
+#define RX_MPDU_INFO_PN_127_96_LSB                                                  0
+#define RX_MPDU_INFO_PN_127_96_MSB                                                  31
+#define RX_MPDU_INFO_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET                                0x00000020
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK                                  0x00000001
+
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET                                     0x00000020
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK                                       0x00000002
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK                                        0x00000004
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK                                        0x00000008
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK                                        0x00000010
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK                                        0x00000020
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK                               0x00000040
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                                  0x00000020
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK                                    0x00000080
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET                                   0x00000020
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK                                     0x00000100
+
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK                               0x00000200
+
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB                                       10
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB                                       13
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK                                      0x00003c00
+
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK                                        0x00004000
+
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET                                       0x00000020
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB                                          15
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB                                          15
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK                                         0x00008000
+
+#define RX_MPDU_INFO_FR_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_FR_DS_LSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MASK                                                     0x00010000
+
+#define RX_MPDU_INFO_TO_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_TO_DS_LSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MASK                                                     0x00020000
+
+#define RX_MPDU_INFO_ENCRYPTED_OFFSET                                               0x00000020
+#define RX_MPDU_INFO_ENCRYPTED_LSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MASK                                                 0x00040000
+
+#define RX_MPDU_INFO_MPDU_RETRY_OFFSET                                              0x00000020
+#define RX_MPDU_INFO_MPDU_RETRY_LSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MASK                                                0x00080000
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB                                       20
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB                                       31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK                                      0xfff00000
+
+#define RX_MPDU_INFO_PEER_META_DATA_OFFSET                                          0x00000024
+#define RX_MPDU_INFO_PEER_META_DATA_LSB                                             0
+#define RX_MPDU_INFO_PEER_META_DATA_MSB                                             31
+#define RX_MPDU_INFO_PEER_META_DATA_MASK                                            0xffffffff
+
+#define RX_MPDU_INFO_AST_INDEX_OFFSET                                               0x00000028
+#define RX_MPDU_INFO_AST_INDEX_LSB                                                  0
+#define RX_MPDU_INFO_AST_INDEX_MSB                                                  15
+#define RX_MPDU_INFO_AST_INDEX_MASK                                                 0x0000ffff
+
+#define RX_MPDU_INFO_SW_PEER_ID_OFFSET                                              0x00000028
+#define RX_MPDU_INFO_SW_PEER_ID_LSB                                                 16
+#define RX_MPDU_INFO_SW_PEER_ID_MSB                                                 31
+#define RX_MPDU_INFO_SW_PEER_ID_MASK                                                0xffff0000
+
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000002c
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x00000003
+
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET                                       0x0000002c
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK                                         0x000001fc
+
+#define RX_MPDU_INFO_NDP_FRAME_OFFSET                                               0x0000002c
+#define RX_MPDU_INFO_NDP_FRAME_LSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MASK                                                 0x00000200
+
+#define RX_MPDU_INFO_PHY_ERR_OFFSET                                                 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_LSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MASK                                                   0x00000400
+
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET                              0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK                                0x00000800
+
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET                                    0x0000002c
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK                                      0x00001000
+
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET                                  0x0000002c
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK                                    0x00002000
+
+#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET                                             0x0000002c
+#define RX_MPDU_INFO_PHY_PPDU_ID_LSB                                                16
+#define RX_MPDU_INFO_PHY_PPDU_ID_MSB                                                31
+#define RX_MPDU_INFO_PHY_PPDU_ID_MASK                                               0xffff0000
+
+#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET                                            0x00000030
+#define RX_MPDU_INFO_KEY_ID_OCTET_LSB                                               0
+#define RX_MPDU_INFO_KEY_ID_OCTET_MSB                                               7
+#define RX_MPDU_INFO_KEY_ID_OCTET_MASK                                              0x000000ff
+
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK                                            0x00000100
+
+#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK                                            0x00000200
+
+#define RX_MPDU_INFO_DECAP_TYPE_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_DECAP_TYPE_LSB                                                 10
+#define RX_MPDU_INFO_DECAP_TYPE_MSB                                                 11
+#define RX_MPDU_INFO_DECAP_TYPE_MASK                                                0x00000c00
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK                              0x00001000
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK                              0x00002000
+
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK                                    0x00004000
+
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK                                    0x00008000
+
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET                                         0x00000030
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB                                            16
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB                                            27
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK                                           0x0fff0000
+
+#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_AMPDU_FLAG_LSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MASK                                                0x10000000
+
+#define RX_MPDU_INFO_BAR_FRAME_OFFSET                                               0x00000030
+#define RX_MPDU_INFO_BAR_FRAME_LSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MASK                                                 0x20000000
+
+#define RX_MPDU_INFO_RAW_MPDU_OFFSET                                                0x00000030
+#define RX_MPDU_INFO_RAW_MPDU_LSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MASK                                                  0x40000000
+
+#define RX_MPDU_INFO_RESERVED_12_OFFSET                                             0x00000030
+#define RX_MPDU_INFO_RESERVED_12_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MPDU_LENGTH_LSB                                                0
+#define RX_MPDU_INFO_MPDU_LENGTH_MSB                                                13
+#define RX_MPDU_INFO_MPDU_LENGTH_MASK                                               0x00003fff
+
+#define RX_MPDU_INFO_FIRST_MPDU_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_FIRST_MPDU_LSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MASK                                                0x00004000
+
+#define RX_MPDU_INFO_MCAST_BCAST_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MCAST_BCAST_LSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MASK                                               0x00008000
+
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET                                     0x00000034
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK                                       0x00010000
+
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET                                       0x00000034
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK                                         0x00020000
+
+#define RX_MPDU_INFO_POWER_MGMT_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_POWER_MGMT_LSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MASK                                                0x00040000
+
+#define RX_MPDU_INFO_NON_QOS_OFFSET                                                 0x00000034
+#define RX_MPDU_INFO_NON_QOS_LSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MASK                                                   0x00080000
+
+#define RX_MPDU_INFO_NULL_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_NULL_DATA_LSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MASK                                                 0x00100000
+
+#define RX_MPDU_INFO_MGMT_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MGMT_TYPE_LSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MASK                                                 0x00200000
+
+#define RX_MPDU_INFO_CTRL_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_CTRL_TYPE_LSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MASK                                                 0x00400000
+
+#define RX_MPDU_INFO_MORE_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MORE_DATA_LSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MASK                                                 0x00800000
+
+#define RX_MPDU_INFO_EOSP_OFFSET                                                    0x00000034
+#define RX_MPDU_INFO_EOSP_LSB                                                       24
+#define RX_MPDU_INFO_EOSP_MSB                                                       24
+#define RX_MPDU_INFO_EOSP_MASK                                                      0x01000000
+
+#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK                                             0x02000000
+
+#define RX_MPDU_INFO_ORDER_OFFSET                                                   0x00000034
+#define RX_MPDU_INFO_ORDER_LSB                                                      26
+#define RX_MPDU_INFO_ORDER_MSB                                                      26
+#define RX_MPDU_INFO_ORDER_MASK                                                     0x04000000
+
+#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET                                          0x00000034
+#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK                                            0x08000000
+
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET                                        0x00000034
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK                                          0x10000000
+
+#define RX_MPDU_INFO_DIRECTED_OFFSET                                                0x00000034
+#define RX_MPDU_INFO_DIRECTED_LSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MASK                                                  0x20000000
+
+#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_AMSDU_PRESENT_LSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MASK                                             0x40000000
+
+#define RX_MPDU_INFO_RESERVED_13_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_RESERVED_13_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET                                0x00000038
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB                                   15
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK                                  0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET                                     0x00000038
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB                                        16
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB                                        31
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK                                       0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET                                       0x0000003c
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET                                      0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET                                       0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB                                          16
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK                                         0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET                                      0x00000044
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB                                         31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK                                        0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET                                       0x00000048
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET                                      0x0000004c
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET                             0x0000004c
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB                                16
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB                                31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK                               0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET                                       0x00000050
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET                                      0x00000054
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET                                  0x00000054
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB                                     16
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB                                     31
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK                                    0xffff0000
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET                                   0x00000058
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB                                      0
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB                                      31
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK                                     0xffffffff
+
+#define RX_MPDU_INFO_VDEV_ID_OFFSET                                                 0x0000005c
+#define RX_MPDU_INFO_VDEV_ID_LSB                                                    0
+#define RX_MPDU_INFO_VDEV_ID_MSB                                                    7
+#define RX_MPDU_INFO_VDEV_ID_MASK                                                   0x000000ff
+
+#define RX_MPDU_INFO_SERVICE_CODE_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_SERVICE_CODE_LSB                                               8
+#define RX_MPDU_INFO_SERVICE_CODE_MSB                                               16
+#define RX_MPDU_INFO_SERVICE_CODE_MASK                                              0x0001ff00
+
+#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET                                          0x0000005c
+#define RX_MPDU_INFO_PRIORITY_VALID_LSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_SRC_INFO_OFFSET                                                0x0000005c
+#define RX_MPDU_INFO_SRC_INFO_LSB                                                   18
+#define RX_MPDU_INFO_SRC_INFO_MSB                                                   29
+#define RX_MPDU_INFO_SRC_INFO_MASK                                                  0x3ffc0000
+
+#define RX_MPDU_INFO_SMR_FRAME_OFFSET                                               0x0000005c
+#define RX_MPDU_INFO_SMR_FRAME_LSB                                                  30
+#define RX_MPDU_INFO_SMR_FRAME_MSB                                                  30
+#define RX_MPDU_INFO_SMR_FRAME_MASK                                                 0x40000000
+
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK                                    0x00000001
+
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET                        0x0000006c
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK                          0x00000002
+
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK                                 0x00000004
+
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK                                 0x00000008
+
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK                                 0x00000010
+
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK                                 0x00000020
+
+#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET                                          0x0000006c
+#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB                                             6
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB                                             8
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK                                            0x000001c0
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB                                     9
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB                                     10
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK                                    0x00000600
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB                                     11
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB                                     12
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK                                    0x00001800
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB                                     13
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB                                     14
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK                                    0x00006000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB                      15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB                      15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK                     0x00008000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET                0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB                   16
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB                   16
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK                  0x00010000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET                            0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB                               17
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB                               17
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK                              0x00020000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                     0x00040000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                          0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                            0x00080000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                           0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                             0x00100000
+
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB                                       21
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB                                       22
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK                                      0x00600000
+
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB                                       23
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB                                       24
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK                                      0x01800000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET                              0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB                                 25
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB                                 25
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK                                0x02000000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET                              0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB                                 26
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB                                 26
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK                                0x04000000
+
+#define RX_MPDU_INFO_RESERVED_27A_OFFSET                                            0x0000006c
+#define RX_MPDU_INFO_RESERVED_27A_LSB                                               27
+#define RX_MPDU_INFO_RESERVED_27A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_27A_MASK                                              0xf8000000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET                             0x00000070
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB                                0
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB                                31
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET                            0x00000074
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB                               0
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB                               15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK                              0x0000ffff
+
+#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET                                             0x00000074
+#define RX_MPDU_INFO_CFP_MIC_ERR_LSB                                                16
+#define RX_MPDU_INFO_CFP_MIC_ERR_MSB                                                16
+#define RX_MPDU_INFO_CFP_MIC_ERR_MASK                                               0x00010000
+
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET                                          0x00000074
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB                                             17
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB                                             17
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_RESERVED_29A_OFFSET                                            0x00000074
+#define RX_MPDU_INFO_RESERVED_29A_LSB                                               18
+#define RX_MPDU_INFO_RESERVED_29A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_29A_MASK                                              0xfffc0000
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_link_ptr.h b/hw/fig/v2/rx_mpdu_link_ptr.h
new file mode 100644
index 000000000000..e9d7e83a92cc
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_link_ptr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#else
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#endif
+};
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB              0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB             0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB             7
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB         8
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB         11
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB              12
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#endif
diff --git a/hw/fig/v2/rx_mpdu_start.h b/hw/fig/v2/rx_mpdu_start.h
new file mode 100644
index 000000000000..fc5029dc2da3
--- /dev/null
+++ b/hw/fig/v2/rx_mpdu_start.h
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+
+#include "rx_mpdu_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_START 30
+
+#define NUM_OF_QWORDS_RX_MPDU_START 15
+
+struct rx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#else
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#endif
+};
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK  0x0000000000100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET                            0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK                              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET     0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK       0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB                         34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB                         37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK                        0x0000003c00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET    0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB       39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK      0x000000c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET                         0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK                           0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB                         43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB                         46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK                        0x0000780000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET                               0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB                                  47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB                                  50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK                                 0x0007800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET                       0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB                          51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK                         0xfff8000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB         39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET              0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB                 40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK                0x00ffff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET             0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK               0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET                   0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK                     0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET                       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB                          58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK                         0xfc00000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET                           0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB                              0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB                              31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK                             0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET                          0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB                             32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB                             63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK                            0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET                          0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB                             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB                             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK                            0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET                         0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB                            32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB                            63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK                           0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET          0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK            0x0000000000000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET               0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK                 0x0000000000000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK                  0x0000000000000004
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK                  0x0000000000000008
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK                  0x0000000000000010
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK                  0x0000000000000020
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK         0x0000000000000040
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET            0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK              0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK               0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK         0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB                 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB                 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK                0x0000000000003c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK                  0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET                 0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB                    15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB                    15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK                   0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK                               0x0000000000010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK                               0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET                         0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK                           0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET                        0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK                          0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB                 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB                 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK                0x00000000fff00000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET                    0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB                       32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB                       63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK                      0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB                            0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB                            15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK                           0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET                        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB                           16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB                           31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK                          0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET     0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB        32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK       0x0000000300000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET                 0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB                    34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB                    40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK                   0x000001fc00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK                           0x0000020000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET                           0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK                             0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK          0x0000080000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET              0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK                0x0000100000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET            0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK              0x0000200000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET                       0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK                         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET                      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB                         7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK                        0x00000000000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK                      0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK                      0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB                           10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB                           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK                          0x0000000000000c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK        0x0000000000001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK        0x0000000000002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK              0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK              0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET                   0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB                      16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB                      27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK                     0x000000000fff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK                          0x0000000010000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK                           0x0000000020000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK                            0x0000000040000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK                         0x0000000080000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB                          32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB                          45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK                         0x00003fff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK                          0x0000400000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK                         0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET               0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK                 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET                 0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK                   0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK                          0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET                           0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK                             0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK                           0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK                           0x0020000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK                           0x0040000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK                           0x0080000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET                              0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK                                0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK                       0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET                             0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK                               0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK                      0x0800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET                  0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK                    0x1000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK                            0x2000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK                       0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK                         0x8000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET          0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB             15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK            0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET               0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB                  31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK                 0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET                 0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB                    32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB                    63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK                   0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK                  0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET                 0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB                    16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK                   0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB                   63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK                  0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET                 0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET                0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET       0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET                 0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET                0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET            0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB               48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB               63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK              0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET             0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB                0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB                31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK               0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET                           0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB                              32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB                              39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK                             0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET                      0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB                         40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB                         48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK                        0x0001ff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET                    0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK                      0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET                          0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB                             50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK                            0x3ffc000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET                         0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB                            62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB                            62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK                           0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET  0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK    0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK           0x0000000400000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK           0x0000000800000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK           0x0000001000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK           0x0000002000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET                    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB                       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB                       40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK                      0x000001c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB               41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB               42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK              0x0000060000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB               43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB               44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK              0x0000180000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB               46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK              0x0000600000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET      0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB         49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB         49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK        0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK      0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET     0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK       0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB                 53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB                 54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK                0x0060000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK                0x0180000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET        0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB           57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB           57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK          0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET        0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB           58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB           58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK          0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET                      0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB                         59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK                        0xf800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET       0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK         0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET      0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB         32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB         47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK        0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET                       0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK                         0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET                    0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK                      0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET                      0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB                         50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK                        0xfffc000000000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_desc_info.h b/hw/fig/v2/rx_msdu_desc_info.h
new file mode 100644
index 000000000000..88569b653b64
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_desc_info.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
+
+struct rx_msdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t first_msdu_in_mpdu_flag                                 :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      msdu_continuation                                       :  1,
+                      msdu_length                                             : 14,
+                      msdu_drop                                               :  1,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding_msb                                   :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      decap_format                                            :  2,
+                      __reserved_g_0015                                       :  1;
+#else
+             uint32_t __reserved_g_0015                                       :  1,
+                      decap_format                                            :  2,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      l3_header_padding_msb                                   :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      msdu_drop                                               :  1,
+                      msdu_length                                             : 14,
+                      msdu_continuation                                       :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      first_msdu_in_mpdu_flag                                 :  1;
+#endif
+};
+
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET                            0x00000000
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK                              0x00000001
+
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET                             0x00000000
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK                               0x00000002
+
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET                                  0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK                                    0x00000004
+
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB                                           3
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB                                           16
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK                                          0x0001fff8
+
+#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK                                            0x00020000
+
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK                                          0x00040000
+
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK                                          0x00080000
+
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET                                         0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK                                           0x00100000
+
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET                              0x00000000
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK                                0x00200000
+
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET                                0x00000000
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK                                  0x00400000
+
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET                                     0x00000000
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK                                       0x00800000
+
+#define RX_MSDU_DESC_INFO_FR_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_FR_DS_LSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MASK                                                0x01000000
+
+#define RX_MSDU_DESC_INFO_TO_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_TO_DS_LSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MASK                                                0x02000000
+
+#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK                                            0x04000000
+
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB                                          27
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB                                          28
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK                                         0x18000000
+
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB                                          29
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB                                          30
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK                                         0x60000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_details.h b/hw/fig/v2/rx_msdu_details.h
new file mode 100644
index 000000000000..0b763a473ce6
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_details.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_ext_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB               0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB              0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB              7
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB               12
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET    0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK      0x00000001
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET     0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK       0x00000002
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET          0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK            0x00000004
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB                   3
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB                   16
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK                  0x0001fff8
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                    0x00020000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK                  0x00040000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK                  0x00080000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET                 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK                   0x00100000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK        0x00200000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET        0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK          0x00400000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK               0x00800000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                        0x01000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                        0x02000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                    0x04000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB                  27
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB                  28
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK                 0x18000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB                   29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB                   31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK                  0xe0000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB                  29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET           0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB              5
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB              13
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK             0x00003fe0
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET         0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK           0x00004000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB               15
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB               26
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK              0x07ff8000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB               27
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB               29
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK              0x38000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB               30
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB               31
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK              0xc0000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_end.h b/hw/fig/v2/rx_msdu_end.h
new file mode 100644
index 000000000000..b05c9896b09a
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_end.h
@@ -0,0 +1,1094 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_END 32
+
+#define NUM_OF_QWORDS_RX_MSDU_END 16
+
+struct rx_msdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ip_hdr_chksum                                           : 16,
+                      reported_mpdu_length                                    : 14,
+                      reserved_1a                                             :  2;
+             uint32_t reserved_2a                                             :  8,
+                      cce_super_rule                                          :  6,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cumulative_l3_checksum                                  : 16;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t da_offset                                               :  6,
+                      sa_offset                                               :  6,
+                      da_offset_valid                                         :  1,
+                      sa_offset_valid                                         :  1,
+                      reserved_5a                                             :  2,
+                      l3_type                                                 : 16;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t tcp_flag                                                :  9,
+                      lro_eligible                                            :  1,
+                      reserved_9a                                             :  6,
+                      window_size                                             : 16;
+             uint32_t sa_sw_peer_id                                           : 16,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      to_ds                                                   :  1,
+                      tid                                                     :  4,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding                                       :  2,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail_copy                                     :  1;
+             uint32_t sa_idx                                                  : 16,
+                      da_idx_or_sw_peer_id                                    : 16;
+             uint32_t msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      flow_idx                                                : 20,
+                      use_ppe                                                 :  1,
+                      __reserved_g_0003                                                :  2,
+                      vlan_ctag_stripped                                      :  1,
+                      vlan_stag_stripped                                      :  1,
+                      fragment_flag                                           :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t cce_metadata                                            : 16,
+                      tcp_udp_chksum                                          : 16;
+             uint32_t aggregation_count                                       :  8,
+                      flow_aggregation_continuation                           :  1,
+                      fisa_timeout                                            :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      msdu_limit_error                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      cce_match                                               :  1,
+                      amsdu_parser_error                                      :  1,
+                      cumulative_ip_length                                    : 16;
+             uint32_t key_id_octet                                            :  8,
+                      reserved_16a                                            : 24;
+             uint32_t reserved_17a                                            :  6,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      multicast_echo                                          :  1,
+                      wds_learning_event                                      :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      __reserved_g_0015                                       :  1,
+                      reserved_17b                                            :  8;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  6,
+                      msdu_done_copy                                          :  1;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t reserved_28a                                            : 16,
+                      sa_15_0                                                 : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_30a                                            :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      reserved_30b                                            :  1,
+                      order                                                   :  1,
+                      wifi_parser_error                                       :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t reserved_31a                                            : 10,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      ifcs_present                                            :  1,
+                      reserved_31b                                            : 16,
+                      msdu_done                                               :  1;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1a                                             :  2,
+                      reported_mpdu_length                                    : 14,
+                      ip_hdr_chksum                                           : 16;
+             uint32_t cumulative_l3_checksum                                  : 16,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_super_rule                                          :  6,
+                      reserved_2a                                             :  8;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             :  2,
+                      sa_offset_valid                                         :  1,
+                      da_offset_valid                                         :  1,
+                      sa_offset                                               :  6,
+                      da_offset                                               :  6;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t window_size                                             : 16,
+                      reserved_9a                                             :  6,
+                      lro_eligible                                            :  1,
+                      tcp_flag                                                :  9;
+             uint32_t ip_chksum_fail_copy                                     :  1,
+                      fr_ds                                                   :  1,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      l3_header_padding                                       :  2,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      tid                                                     :  4,
+                      to_ds                                                   :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      sa_sw_peer_id                                           : 16;
+             uint32_t da_idx_or_sw_peer_id                                    : 16,
+                      sa_idx                                                  : 16;
+             uint32_t fragment_flag                                           :  1,
+                      vlan_stag_stripped                                      :  1,
+                      vlan_ctag_stripped                                      :  1,
+                      __reserved_g_0003                                                :  2,
+                      use_ppe                                                 :  1,
+                      flow_idx                                                : 20,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t tcp_udp_chksum                                          : 16,
+                      cce_metadata                                            : 16;
+             uint32_t cumulative_ip_length                                    : 16,
+                      amsdu_parser_error                                      :  1,
+                      cce_match                                               :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      msdu_limit_error                                        :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      fisa_timeout                                            :  1,
+                      flow_aggregation_continuation                           :  1,
+                      aggregation_count                                       :  8;
+             uint32_t reserved_16a                                            : 24,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_17b                                            :  8,
+                      __reserved_g_0015                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_learning_event                                      :  1,
+                      multicast_echo                                          :  1,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_17a                                            :  6;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t msdu_done_copy                                          :  1,
+                      mimo_ss_bitmap                                          :  6,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t sa_15_0                                                 : 16,
+                      reserved_28a                                            : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      wifi_parser_error                                       :  1,
+                      order                                                   :  1,
+                      reserved_30b                                            :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_30a                                            :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_31b                                            : 16,
+                      ifcs_present                                            :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved_31a                                            : 10;
+#endif
+};
+
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MSDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MSDU_END_RESERVED_0_LSB                                                  9
+#define RX_MSDU_END_RESERVED_0_MSB                                                  15
+#define RX_MSDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MSDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MSDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MSDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET                                            0x0000000000000000
+#define RX_MSDU_END_IP_HDR_CHKSUM_LSB                                               32
+#define RX_MSDU_END_IP_HDR_CHKSUM_MSB                                               47
+#define RX_MSDU_END_IP_HDR_CHKSUM_MASK                                              0x0000ffff00000000
+
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET                                     0x0000000000000000
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB                                        48
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB                                        61
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK                                       0x3fff000000000000
+
+#define RX_MSDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_RESERVED_1A_LSB                                                 62
+#define RX_MSDU_END_RESERVED_1A_MSB                                                 63
+#define RX_MSDU_END_RESERVED_1A_MASK                                                0xc000000000000000
+
+#define RX_MSDU_END_RESERVED_2A_OFFSET                                              0x0000000000000008
+#define RX_MSDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MSDU_END_RESERVED_2A_MSB                                                 7
+#define RX_MSDU_END_RESERVED_2A_MASK                                                0x00000000000000ff
+
+#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET                                           0x0000000000000008
+#define RX_MSDU_END_CCE_SUPER_RULE_LSB                                              8
+#define RX_MSDU_END_CCE_SUPER_RULE_MSB                                              13
+#define RX_MSDU_END_CCE_SUPER_RULE_MASK                                             0x0000000000003f00
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET                           0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK                             0x0000000000004000
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET                            0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK                              0x0000000000008000
+
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET                                   0x0000000000000008
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB                                      16
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB                                      31
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK                                     0x00000000ffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET                                     0x0000000000000008
+#define RX_MSDU_END_RULE_INDICATION_31_0_LSB                                        32
+#define RX_MSDU_END_RULE_INDICATION_31_0_MSB                                        63
+#define RX_MSDU_END_RULE_INDICATION_31_0_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET                                         0x0000000000000010
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB                                            0
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB                                            31
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK                                           0x00000000ffffffff
+
+#define RX_MSDU_END_DA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_LSB                                                   32
+#define RX_MSDU_END_DA_OFFSET_MSB                                                   37
+#define RX_MSDU_END_DA_OFFSET_MASK                                                  0x0000003f00000000
+
+#define RX_MSDU_END_SA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_LSB                                                   38
+#define RX_MSDU_END_SA_OFFSET_MSB                                                   43
+#define RX_MSDU_END_SA_OFFSET_MASK                                                  0x00000fc000000000
+
+#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_VALID_LSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MASK                                            0x0000100000000000
+
+#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_VALID_LSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MASK                                            0x0000200000000000
+
+#define RX_MSDU_END_RESERVED_5A_OFFSET                                              0x0000000000000010
+#define RX_MSDU_END_RESERVED_5A_LSB                                                 46
+#define RX_MSDU_END_RESERVED_5A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_5A_MASK                                                0x0000c00000000000
+
+#define RX_MSDU_END_L3_TYPE_OFFSET                                                  0x0000000000000010
+#define RX_MSDU_END_L3_TYPE_LSB                                                     48
+#define RX_MSDU_END_L3_TYPE_MSB                                                     63
+#define RX_MSDU_END_L3_TYPE_MASK                                                    0xffff000000000000
+
+#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET                                    0x0000000000000018
+#define RX_MSDU_END_RULE_INDICATION_63_32_LSB                                       0
+#define RX_MSDU_END_RULE_INDICATION_63_32_MSB                                       31
+#define RX_MSDU_END_RULE_INDICATION_63_32_MASK                                      0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET                                           0x0000000000000018
+#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB                                              32
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB                                              63
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET                                           0x0000000000000020
+#define RX_MSDU_END_TCP_ACK_NUMBER_LSB                                              0
+#define RX_MSDU_END_TCP_ACK_NUMBER_MSB                                              31
+#define RX_MSDU_END_TCP_ACK_NUMBER_MASK                                             0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_FLAG_OFFSET                                                 0x0000000000000020
+#define RX_MSDU_END_TCP_FLAG_LSB                                                    32
+#define RX_MSDU_END_TCP_FLAG_MSB                                                    40
+#define RX_MSDU_END_TCP_FLAG_MASK                                                   0x000001ff00000000
+
+#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET                                             0x0000000000000020
+#define RX_MSDU_END_LRO_ELIGIBLE_LSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_RESERVED_9A_LSB                                                 42
+#define RX_MSDU_END_RESERVED_9A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_9A_MASK                                                0x0000fc0000000000
+
+#define RX_MSDU_END_WINDOW_SIZE_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_WINDOW_SIZE_LSB                                                 48
+#define RX_MSDU_END_WINDOW_SIZE_MSB                                                 63
+#define RX_MSDU_END_WINDOW_SIZE_MASK                                                0xffff000000000000
+
+#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET                                            0x0000000000000028
+#define RX_MSDU_END_SA_SW_PEER_ID_LSB                                               0
+#define RX_MSDU_END_SA_SW_PEER_ID_MSB                                               15
+#define RX_MSDU_END_SA_SW_PEER_ID_MASK                                              0x000000000000ffff
+
+#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK                                             0x0000000000010000
+
+#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK                                             0x0000000000020000
+
+#define RX_MSDU_END_TO_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_TO_DS_LSB                                                       18
+#define RX_MSDU_END_TO_DS_MSB                                                       18
+#define RX_MSDU_END_TO_DS_MASK                                                      0x0000000000040000
+
+#define RX_MSDU_END_TID_OFFSET                                                      0x0000000000000028
+#define RX_MSDU_END_TID_LSB                                                         19
+#define RX_MSDU_END_TID_MSB                                                         22
+#define RX_MSDU_END_TID_MASK                                                        0x0000000000780000
+
+#define RX_MSDU_END_SA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_SA_IS_VALID_LSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MASK                                                0x0000000000800000
+
+#define RX_MSDU_END_DA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_DA_IS_VALID_LSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MASK                                                0x0000000001000000
+
+#define RX_MSDU_END_DA_IS_MCBC_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_DA_IS_MCBC_LSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MASK                                                 0x0000000002000000
+
+#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET                                        0x0000000000000028
+#define RX_MSDU_END_L3_HEADER_PADDING_LSB                                           26
+#define RX_MSDU_END_L3_HEADER_PADDING_MSB                                           27
+#define RX_MSDU_END_L3_HEADER_PADDING_MASK                                          0x000000000c000000
+
+#define RX_MSDU_END_FIRST_MSDU_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_FIRST_MSDU_LSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MASK                                                 0x0000000010000000
+
+#define RX_MSDU_END_LAST_MSDU_OFFSET                                                0x0000000000000028
+#define RX_MSDU_END_LAST_MSDU_LSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MASK                                                  0x0000000020000000
+
+#define RX_MSDU_END_FR_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_FR_DS_LSB                                                       30
+#define RX_MSDU_END_FR_DS_MSB                                                       30
+#define RX_MSDU_END_FR_DS_MASK                                                      0x0000000040000000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET                                      0x0000000000000028
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK                                        0x0000000080000000
+
+#define RX_MSDU_END_SA_IDX_OFFSET                                                   0x0000000000000028
+#define RX_MSDU_END_SA_IDX_LSB                                                      32
+#define RX_MSDU_END_SA_IDX_MSB                                                      47
+#define RX_MSDU_END_SA_IDX_MASK                                                     0x0000ffff00000000
+
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET                                     0x0000000000000028
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB                                        48
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB                                        63
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_MSDU_DROP_OFFSET                                                0x0000000000000030
+#define RX_MSDU_END_MSDU_DROP_LSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MASK                                                  0x0000000000000001
+
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET                               0x0000000000000030
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB                                  1
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB                                  5
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK                                 0x000000000000003e
+
+#define RX_MSDU_END_FLOW_IDX_OFFSET                                                 0x0000000000000030
+#define RX_MSDU_END_FLOW_IDX_LSB                                                    6
+#define RX_MSDU_END_FLOW_IDX_MSB                                                    25
+#define RX_MSDU_END_FLOW_IDX_MASK                                                   0x0000000003ffffc0
+
+#define RX_MSDU_END_USE_PPE_OFFSET                                                  0x0000000000000030
+#define RX_MSDU_END_USE_PPE_LSB                                                     26
+#define RX_MSDU_END_USE_PPE_MSB                                                     26
+#define RX_MSDU_END_USE_PPE_MASK                                                    0x0000000004000000
+
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK                                         0x0000000020000000
+
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK                                         0x0000000040000000
+
+#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET                                            0x0000000000000030
+#define RX_MSDU_END_FRAGMENT_FLAG_LSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MASK                                              0x0000000080000000
+
+#define RX_MSDU_END_FSE_METADATA_OFFSET                                             0x0000000000000030
+#define RX_MSDU_END_FSE_METADATA_LSB                                                32
+#define RX_MSDU_END_FSE_METADATA_MSB                                                63
+#define RX_MSDU_END_FSE_METADATA_MASK                                               0xffffffff00000000
+
+#define RX_MSDU_END_CCE_METADATA_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_CCE_METADATA_LSB                                                0
+#define RX_MSDU_END_CCE_METADATA_MSB                                                15
+#define RX_MSDU_END_CCE_METADATA_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET                                           0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB                                              16
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB                                              31
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK                                             0x00000000ffff0000
+
+#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET                                        0x0000000000000038
+#define RX_MSDU_END_AGGREGATION_COUNT_LSB                                           32
+#define RX_MSDU_END_AGGREGATION_COUNT_MSB                                           39
+#define RX_MSDU_END_AGGREGATION_COUNT_MASK                                          0x000000ff00000000
+
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET                            0x0000000000000038
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK                              0x0000010000000000
+
+#define RX_MSDU_END_FISA_TIMEOUT_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_FISA_TIMEOUT_LSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET                                 0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK                                   0x0000040000000000
+
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK                                           0x0000080000000000
+
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK                                           0x0000100000000000
+
+#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_INVALID_LSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MASK                                           0x0000200000000000
+
+#define RX_MSDU_END_CCE_MATCH_OFFSET                                                0x0000000000000038
+#define RX_MSDU_END_CCE_MATCH_LSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MASK                                                  0x0000400000000000
+
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET                                       0x0000000000000038
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK                                         0x0000800000000000
+
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET                                     0x0000000000000038
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB                                        48
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB                                        63
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_KEY_ID_OCTET_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_KEY_ID_OCTET_LSB                                                0
+#define RX_MSDU_END_KEY_ID_OCTET_MSB                                                7
+#define RX_MSDU_END_KEY_ID_OCTET_MASK                                               0x00000000000000ff
+
+#define RX_MSDU_END_RESERVED_16A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_16A_LSB                                                8
+#define RX_MSDU_END_RESERVED_16A_MSB                                                31
+#define RX_MSDU_END_RESERVED_16A_MASK                                               0x00000000ffffff00
+
+#define RX_MSDU_END_RESERVED_17A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17A_LSB                                                32
+#define RX_MSDU_END_RESERVED_17A_MSB                                                37
+#define RX_MSDU_END_RESERVED_17A_MASK                                               0x0000003f00000000
+
+#define RX_MSDU_END_SERVICE_CODE_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_SERVICE_CODE_LSB                                                38
+#define RX_MSDU_END_SERVICE_CODE_MSB                                                46
+#define RX_MSDU_END_SERVICE_CODE_MASK                                               0x00007fc000000000
+
+#define RX_MSDU_END_PRIORITY_VALID_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_PRIORITY_VALID_LSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MASK                                             0x0000800000000000
+
+#define RX_MSDU_END_INTRA_BSS_OFFSET                                                0x0000000000000040
+#define RX_MSDU_END_INTRA_BSS_LSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MASK                                                  0x0001000000000000
+
+#define RX_MSDU_END_DEST_CHIP_ID_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_DEST_CHIP_ID_LSB                                                49
+#define RX_MSDU_END_DEST_CHIP_ID_MSB                                                50
+#define RX_MSDU_END_DEST_CHIP_ID_MASK                                               0x0006000000000000
+
+#define RX_MSDU_END_MULTICAST_ECHO_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_MULTICAST_ECHO_LSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MASK                                             0x0008000000000000
+
+#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET                                       0x0000000000000040
+#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK                                         0x0010000000000000
+
+#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET                                        0x0000000000000040
+#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK                                          0x0020000000000000
+
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET                                     0x0000000000000040
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_RESERVED_17B_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17B_LSB                                                56
+#define RX_MSDU_END_RESERVED_17B_MSB                                                63
+#define RX_MSDU_END_RESERVED_17B_MASK                                               0xff00000000000000
+
+#define RX_MSDU_END_MSDU_LENGTH_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_LENGTH_LSB                                                 0
+#define RX_MSDU_END_MSDU_LENGTH_MSB                                                 13
+#define RX_MSDU_END_MSDU_LENGTH_MASK                                                0x0000000000003fff
+
+#define RX_MSDU_END_STBC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_STBC_LSB                                                        14
+#define RX_MSDU_END_STBC_MSB                                                        14
+#define RX_MSDU_END_STBC_MASK                                                       0x0000000000004000
+
+#define RX_MSDU_END_IPSEC_ESP_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_IPSEC_ESP_LSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MASK                                                  0x0000000000008000
+
+#define RX_MSDU_END_L3_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L3_OFFSET_LSB                                                   16
+#define RX_MSDU_END_L3_OFFSET_MSB                                                   22
+#define RX_MSDU_END_L3_OFFSET_MASK                                                  0x00000000007f0000
+
+#define RX_MSDU_END_IPSEC_AH_OFFSET                                                 0x0000000000000048
+#define RX_MSDU_END_IPSEC_AH_LSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MASK                                                   0x0000000000800000
+
+#define RX_MSDU_END_L4_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L4_OFFSET_LSB                                                   24
+#define RX_MSDU_END_L4_OFFSET_MSB                                                   31
+#define RX_MSDU_END_L4_OFFSET_MASK                                                  0x00000000ff000000
+
+#define RX_MSDU_END_MSDU_NUMBER_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_NUMBER_LSB                                                 32
+#define RX_MSDU_END_MSDU_NUMBER_MSB                                                 39
+#define RX_MSDU_END_MSDU_NUMBER_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_END_DECAP_FORMAT_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_DECAP_FORMAT_LSB                                                40
+#define RX_MSDU_END_DECAP_FORMAT_MSB                                                41
+#define RX_MSDU_END_DECAP_FORMAT_MASK                                               0x0000030000000000
+
+#define RX_MSDU_END_IPV4_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV4_PROTO_LSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MASK                                                 0x0000040000000000
+
+#define RX_MSDU_END_IPV6_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV6_PROTO_LSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MASK                                                 0x0000080000000000
+
+#define RX_MSDU_END_TCP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_TCP_PROTO_LSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MASK                                                  0x0000100000000000
+
+#define RX_MSDU_END_UDP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_UDP_PROTO_LSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MASK                                                  0x0000200000000000
+
+#define RX_MSDU_END_IP_FRAG_OFFSET                                                  0x0000000000000048
+#define RX_MSDU_END_IP_FRAG_LSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MASK                                                    0x0000400000000000
+
+#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_TCP_ONLY_ACK_LSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MASK                                               0x0000800000000000
+
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK                                          0x0001000000000000
+
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB                                           49
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB                                           50
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK                                          0x0006000000000000
+
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET                                    0x0000000000000048
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK                                      0x0008000000000000
+
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK                                       0x0010000000000000
+
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK                                       0x0020000000000000
+
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_LDPC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_LDPC_LSB                                                        55
+#define RX_MSDU_END_LDPC_MSB                                                        55
+#define RX_MSDU_END_LDPC_MASK                                                       0x0080000000000000
+
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                             0x0000000000000048
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                                56
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                                63
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                               0xff00000000000000
+
+#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_CTAG_CI_LSB                                                0
+#define RX_MSDU_END_VLAN_CTAG_CI_MSB                                                15
+#define RX_MSDU_END_VLAN_CTAG_CI_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_VLAN_STAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_STAG_CI_LSB                                                16
+#define RX_MSDU_END_VLAN_STAG_CI_MSB                                                31
+#define RX_MSDU_END_VLAN_STAG_CI_MASK                                               0x00000000ffff0000
+
+#define RX_MSDU_END_PEER_META_DATA_OFFSET                                           0x0000000000000050
+#define RX_MSDU_END_PEER_META_DATA_LSB                                              32
+#define RX_MSDU_END_PEER_META_DATA_MSB                                              63
+#define RX_MSDU_END_PEER_META_DATA_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_USER_RSSI_OFFSET                                                0x0000000000000058
+#define RX_MSDU_END_USER_RSSI_LSB                                                   0
+#define RX_MSDU_END_USER_RSSI_MSB                                                   7
+#define RX_MSDU_END_USER_RSSI_MASK                                                  0x00000000000000ff
+
+#define RX_MSDU_END_PKT_TYPE_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_PKT_TYPE_LSB                                                    8
+#define RX_MSDU_END_PKT_TYPE_MSB                                                    11
+#define RX_MSDU_END_PKT_TYPE_MASK                                                   0x0000000000000f00
+
+#define RX_MSDU_END_SGI_OFFSET                                                      0x0000000000000058
+#define RX_MSDU_END_SGI_LSB                                                         12
+#define RX_MSDU_END_SGI_MSB                                                         13
+#define RX_MSDU_END_SGI_MASK                                                        0x0000000000003000
+
+#define RX_MSDU_END_RATE_MCS_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_RATE_MCS_LSB                                                    14
+#define RX_MSDU_END_RATE_MCS_MSB                                                    18
+#define RX_MSDU_END_RATE_MCS_MASK                                                   0x000000000007c000
+
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET                                        0x0000000000000058
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB                                           19
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB                                           21
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK                                          0x0000000000380000
+
+#define RX_MSDU_END_RECEPTION_TYPE_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_RECEPTION_TYPE_LSB                                              22
+#define RX_MSDU_END_RECEPTION_TYPE_MSB                                              24
+#define RX_MSDU_END_RECEPTION_TYPE_MASK                                             0x0000000001c00000
+
+#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MIMO_SS_BITMAP_LSB                                              25
+#define RX_MSDU_END_MIMO_SS_BITMAP_MSB                                              30
+#define RX_MSDU_END_MIMO_SS_BITMAP_MASK                                             0x000000007e000000
+
+#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MSDU_DONE_COPY_LSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MASK                                             0x0000000080000000
+
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET                                         0x0000000000000058
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB                                            32
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB                                            63
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET                               0x0000000000000060
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB                                  0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB                                  31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK                                 0x00000000ffffffff
+
+#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET                                         0x0000000000000060
+#define RX_MSDU_END_SW_PHY_META_DATA_LSB                                            32
+#define RX_MSDU_END_SW_PHY_META_DATA_MSB                                            63
+#define RX_MSDU_END_SW_PHY_META_DATA_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET                                0x0000000000000068
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB                                   0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB                                   31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET                                     0x0000000000000068
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB                                        32
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB                                        63
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_RESERVED_28A_OFFSET                                             0x0000000000000070
+#define RX_MSDU_END_RESERVED_28A_LSB                                                0
+#define RX_MSDU_END_RESERVED_28A_MSB                                                15
+#define RX_MSDU_END_RESERVED_28A_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_SA_15_0_OFFSET                                                  0x0000000000000070
+#define RX_MSDU_END_SA_15_0_LSB                                                     16
+#define RX_MSDU_END_SA_15_0_MSB                                                     31
+#define RX_MSDU_END_SA_15_0_MASK                                                    0x00000000ffff0000
+
+#define RX_MSDU_END_SA_47_16_OFFSET                                                 0x0000000000000070
+#define RX_MSDU_END_SA_47_16_LSB                                                    32
+#define RX_MSDU_END_SA_47_16_MSB                                                    63
+#define RX_MSDU_END_SA_47_16_MASK                                                   0xffffffff00000000
+
+#define RX_MSDU_END_FIRST_MPDU_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_FIRST_MPDU_LSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MASK                                                 0x0000000000000001
+
+#define RX_MSDU_END_RESERVED_30A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30A_LSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MASK                                               0x0000000000000002
+
+#define RX_MSDU_END_MCAST_BCAST_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_MCAST_BCAST_LSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MASK                                                0x0000000000000004
+
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK                                        0x0000000000000008
+
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK                                          0x0000000000000010
+
+#define RX_MSDU_END_POWER_MGMT_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_POWER_MGMT_LSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MASK                                                 0x0000000000000020
+
+#define RX_MSDU_END_NON_QOS_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_NON_QOS_LSB                                                     6
+#define RX_MSDU_END_NON_QOS_MSB                                                     6
+#define RX_MSDU_END_NON_QOS_MASK                                                    0x0000000000000040
+
+#define RX_MSDU_END_NULL_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_NULL_DATA_LSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MASK                                                  0x0000000000000080
+
+#define RX_MSDU_END_MGMT_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MGMT_TYPE_LSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MASK                                                  0x0000000000000100
+
+#define RX_MSDU_END_CTRL_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_CTRL_TYPE_LSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MASK                                                  0x0000000000000200
+
+#define RX_MSDU_END_MORE_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MORE_DATA_LSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MASK                                                  0x0000000000000400
+
+#define RX_MSDU_END_EOSP_OFFSET                                                     0x0000000000000078
+#define RX_MSDU_END_EOSP_LSB                                                        11
+#define RX_MSDU_END_EOSP_MSB                                                        11
+#define RX_MSDU_END_EOSP_MASK                                                       0x0000000000000800
+
+#define RX_MSDU_END_A_MSDU_ERROR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_A_MSDU_ERROR_LSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MASK                                               0x0000000000001000
+
+#define RX_MSDU_END_RESERVED_30B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30B_LSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MASK                                               0x0000000000002000
+
+#define RX_MSDU_END_ORDER_OFFSET                                                    0x0000000000000078
+#define RX_MSDU_END_ORDER_LSB                                                       14
+#define RX_MSDU_END_ORDER_MSB                                                       14
+#define RX_MSDU_END_ORDER_MASK                                                      0x0000000000004000
+
+#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK                                          0x0000000000008000
+
+#define RX_MSDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_OVERFLOW_ERR_LSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MASK                                               0x0000000000010000
+
+#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK                                            0x0000000000020000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK                                        0x0000000000040000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK                                             0x0000000000080000
+
+#define RX_MSDU_END_SA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_SA_IDX_INVALID_LSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MASK                                             0x0000000000100000
+
+#define RX_MSDU_END_DA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_DA_IDX_INVALID_LSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MASK                                             0x0000000000200000
+
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK                                        0x0000000000400000
+
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000078
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000000000800000
+
+#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET                                         0x0000000000000078
+#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK                                           0x0000000001000000
+
+#define RX_MSDU_END_DIRECTED_OFFSET                                                 0x0000000000000078
+#define RX_MSDU_END_DIRECTED_LSB                                                    25
+#define RX_MSDU_END_DIRECTED_MSB                                                    25
+#define RX_MSDU_END_DIRECTED_MASK                                                   0x0000000002000000
+
+#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_BUFFER_FRAGMENT_LSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MASK                                            0x0000000004000000
+
+#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000000008000000
+
+#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_TKIP_MIC_ERR_LSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MASK                                               0x0000000010000000
+
+#define RX_MSDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_DECRYPT_ERR_LSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MASK                                                0x0000000020000000
+
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0000000040000000
+
+#define RX_MSDU_END_FCS_ERR_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_FCS_ERR_LSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MASK                                                    0x0000000080000000
+
+#define RX_MSDU_END_RESERVED_31A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31A_LSB                                                32
+#define RX_MSDU_END_RESERVED_31A_MSB                                                41
+#define RX_MSDU_END_RESERVED_31A_MASK                                               0x000003ff00000000
+
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB                                         42
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB                                         44
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK                                        0x00001c0000000000
+
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x0000200000000000
+
+#define RX_MSDU_END_IFCS_PRESENT_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_IFCS_PRESENT_LSB                                                46
+#define RX_MSDU_END_IFCS_PRESENT_MSB                                                46
+#define RX_MSDU_END_IFCS_PRESENT_MASK                                               0x0000400000000000
+
+#define RX_MSDU_END_RESERVED_31B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31B_LSB                                                47
+#define RX_MSDU_END_RESERVED_31B_MSB                                                62
+#define RX_MSDU_END_RESERVED_31B_MASK                                               0x7fff800000000000
+
+#define RX_MSDU_END_MSDU_DONE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MSDU_DONE_LSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MASK                                                  0x8000000000000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_ext_desc_info.h b/hw/fig/v2/rx_msdu_ext_desc_info.h
new file mode 100644
index 000000000000..70bda69ddfec
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_ext_desc_info.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_EXT_DESC_INFO_H_
+#define _RX_MSDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
+
+struct rx_msdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      data_offset                                             : 12,
+                      src_link_id                                             :  3,
+                      reserved_0a                                             :  2;
+#else
+             uint32_t reserved_0a                                             :  2,
+                      src_link_id                                             :  3,
+                      data_offset                                             : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET                     0x00000000
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB                        0
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB                        4
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK                       0x0000001f
+
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET                                   0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB                                      5
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB                                      13
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK                                     0x00003fe0
+
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET                                 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK                                   0x00004000
+
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB                                       15
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB                                       26
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK                                      0x07ff8000
+
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB                                       27
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB                                       29
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK                                      0x38000000
+
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB                                       30
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB                                       31
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK                                      0xc0000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_link.h b/hw/fig/v2/rx_msdu_link.h
new file mode 100644
index 000000000000..c54357dae2ef
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_link.h
@@ -0,0 +1,2051 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+#define NUM_OF_DWORDS_RX_MSDU_LINK 64
+
+struct rx_msdu_link {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#endif
+};
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET          0x00000004
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB             0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK            0xffffffff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET         0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB            0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB            7
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK           0x000000ff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET     0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB        8
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB        11
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK       0x00000f00
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET          0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB             12
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK            0xfffff000
+
+#define RX_MSDU_LINK_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_MSDU_LINK_RESERVED_3A_LSB                                                0
+#define RX_MSDU_LINK_RESERVED_3A_MSB                                                31
+#define RX_MSDU_LINK_RESERVED_3A_MASK                                               0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000010
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000020
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000030
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000040
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000050
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000060
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000070
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000080
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000090
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x000000a0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000b0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000c0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000d0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000e0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000f0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#endif
diff --git a/hw/fig/v2/rx_msdu_start.h b/hw/fig/v2/rx_msdu_start.h
new file mode 100644
index 000000000000..e1e99c027c85
--- /dev/null
+++ b/hw/fig/v2/rx_msdu_start.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_START 10
+
+#define NUM_OF_QWORDS_RX_MSDU_START 5
+
+struct rx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      rate_mcs                                                :  5,
+                      reserved_0                                              :  2,
+                      phy_ppdu_id                                             : 16;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      reserved_5a                                             :  4,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  2,
+                      rate_mcs                                                :  5,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t mimo_ss_bitmap                                          :  8,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      reserved_5a                                             :  4,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+#endif
+};
+
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x0000000000000000
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x0000000000000003
+
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x0000000000000000
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x00000000000001fc
+
+#define RX_MSDU_START_RATE_MCS_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_RATE_MCS_LSB                                                  9
+#define RX_MSDU_START_RATE_MCS_MSB                                                  13
+#define RX_MSDU_START_RATE_MCS_MASK                                                 0x0000000000003e00
+
+#define RX_MSDU_START_RESERVED_0_OFFSET                                             0x0000000000000000
+#define RX_MSDU_START_RESERVED_0_LSB                                                14
+#define RX_MSDU_START_RESERVED_0_MSB                                                15
+#define RX_MSDU_START_RESERVED_0_MASK                                               0x000000000000c000
+
+#define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
+#define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
+#define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0x00000000ffff0000
+
+#define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_MSDU_LENGTH_LSB                                               32
+#define RX_MSDU_START_MSDU_LENGTH_MSB                                               45
+#define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff00000000
+
+#define RX_MSDU_START_STBC_OFFSET                                                   0x0000000000000000
+#define RX_MSDU_START_STBC_LSB                                                      46
+#define RX_MSDU_START_STBC_MSB                                                      46
+#define RX_MSDU_START_STBC_MASK                                                     0x0000400000000000
+
+#define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_IPSEC_ESP_LSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MASK                                                0x0000800000000000
+
+#define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L3_OFFSET_LSB                                                 48
+#define RX_MSDU_START_L3_OFFSET_MSB                                                 54
+#define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f000000000000
+
+#define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_IPSEC_AH_LSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MASK                                                 0x0080000000000000
+
+#define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L4_OFFSET_LSB                                                 56
+#define RX_MSDU_START_L4_OFFSET_MSB                                                 63
+#define RX_MSDU_START_L4_OFFSET_MASK                                                0xff00000000000000
+
+#define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x0000000000000008
+#define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
+#define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
+#define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x00000000000000ff
+
+#define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
+#define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
+#define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x0000000000000300
+
+#define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV4_PROTO_LSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MASK                                               0x0000000000000400
+
+#define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV6_PROTO_LSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MASK                                               0x0000000000000800
+
+#define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_TCP_PROTO_LSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MASK                                                0x0000000000001000
+
+#define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_UDP_PROTO_LSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MASK                                                0x0000000000002000
+
+#define RX_MSDU_START_IP_FRAG_OFFSET                                                0x0000000000000008
+#define RX_MSDU_START_IP_FRAG_LSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MASK                                                  0x0000000000004000
+
+#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x0000000000008000
+
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x0000000000010000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x0000000000060000
+
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x0000000000000008
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x0000000000080000
+
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x0000000000100000
+
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x0000000000200000
+
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x0000000000400000
+
+#define RX_MSDU_START_LDPC_OFFSET                                                   0x0000000000000008
+#define RX_MSDU_START_LDPC_LSB                                                      23
+#define RX_MSDU_START_LDPC_MSB                                                      23
+#define RX_MSDU_START_LDPC_MASK                                                     0x0000000000800000
+
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x0000000000000008
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0x00000000ff000000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      32
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      63
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff00000000
+
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x0000000000000010
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_USER_RSSI_OFFSET                                              0x0000000000000010
+#define RX_MSDU_START_USER_RSSI_LSB                                                 32
+#define RX_MSDU_START_USER_RSSI_MSB                                                 39
+#define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x0000000000000010
+#define RX_MSDU_START_PKT_TYPE_LSB                                                  40
+#define RX_MSDU_START_PKT_TYPE_MSB                                                  43
+#define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f0000000000
+
+#define RX_MSDU_START_SGI_OFFSET                                                    0x0000000000000010
+#define RX_MSDU_START_SGI_LSB                                                       44
+#define RX_MSDU_START_SGI_MSB                                                       45
+#define RX_MSDU_START_SGI_MASK                                                      0x0000300000000000
+
+#define RX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define RX_MSDU_START_RESERVED_5A_LSB                                               46
+#define RX_MSDU_START_RESERVED_5A_MSB                                               49
+#define RX_MSDU_START_RESERVED_5A_MASK                                              0x0003c00000000000
+
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x0000000000000010
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         50
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         52
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c000000000000
+
+#define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_RECEPTION_TYPE_LSB                                            53
+#define RX_MSDU_START_RECEPTION_TYPE_MSB                                            55
+#define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e0000000000000
+
+#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            56
+#define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            63
+#define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff00000000000000
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000020
+#define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
+#define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
+#define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              32
+#define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              47
+#define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff00000000
+
+#define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_STAG_CI_LSB                                              48
+#define RX_MSDU_START_VLAN_STAG_CI_MSB                                              63
+#define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_ack_report.h b/hw/fig/v2/rx_ppdu_ack_report.h
new file mode 100644
index 000000000000..345b14ea4255
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_ack_report.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_ACK_REPORT_H_
+#define _RX_PPDU_ACK_REPORT_H_
+
+#include "ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2
+
+#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1
+
+struct rx_ppdu_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB           0
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB           3
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK          0x000000000000000f
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET                0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB                   4
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB                   7
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK                  0x00000000000000f0
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET                        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK                          0x0000000000000100
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET                       0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB                          9
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB                          15
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK                         0x000000000000fe00
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET                  0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB                     16
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB                     31
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK                    0x00000000ffff0000
+
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB                                        32
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB                                        63
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_end_user_stats.h b/hw/fig/v2/rx_ppdu_end_user_stats.h
new file mode 100644
index 000000000000..51db8f35a6ab
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_end_user_stats.h
@@ -0,0 +1,679 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15
+
+struct rx_ppdu_end_user_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t sta_full_aid                                            : 13,
+                      mcs                                                     :  5,
+                      nss                                                     :  3,
+                      expected_response_ack_or_ba                             :  1,
+                      reserved_1a                                             : 10;
+             uint32_t sw_peer_id                                              : 16,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      fw2rxdma1_buf_source_used                               :  1;
+             uint32_t mpdu_cnt_fcs_ok                                         : 11,
+                      frame_control_info_valid                                :  1,
+                      qos_control_info_valid                                  :  1,
+                      ht_control_info_valid                                   :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_null_valid                              :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      reserved_3a                                             :  1,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3b                                             :  7;
+             uint32_t ast_index                                               : 16,
+                      frame_control_field                                     : 16;
+             uint32_t first_data_seq_ctrl                                     : 16,
+                      qos_control_field                                       : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t udp_msdu_count                                          : 16,
+                      tcp_msdu_count                                          : 16;
+             uint32_t other_msdu_count                                        : 16,
+                      tcp_ack_msdu_count                                      : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_bitmap                            : 16,
+                      received_qos_data_tid_eosp_bitmap                       : 16;
+             uint32_t qosctrl_15_8_tid0                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid3                                       :  8;
+             uint32_t qosctrl_15_8_tid4                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid7                                       :  8;
+             uint32_t qosctrl_15_8_tid8                                       :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid11                                      :  8;
+             uint32_t qosctrl_15_8_tid12                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid15                                      :  8;
+             uint32_t mpdu_ok_byte_count                                      : 25,
+                      ampdu_delim_ok_count_6_0                                :  7;
+             uint32_t ampdu_delim_err_count                                   : 25,
+                      ampdu_delim_ok_count_13_7                               :  7;
+             uint32_t mpdu_err_byte_count                                     : 25,
+                      ampdu_delim_ok_count_20_14                              :  7;
+             uint32_t non_consecutive_delimiter_err                           : 16,
+                      retried_msdu_count                                      : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      frame_control_info_null_valid                           :  1,
+                      frame_control_field_null                                : 16,
+                      retried_mpdu_count                                      : 11,
+                      reserved_23a                                            :  3;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_24a                                            :  4,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mcast_bcast                                             :  1,
+                      frame_control_field_mgmt_ctrl                           : 16;
+             uint32_t user_ppdu_len                                           : 24,
+                      reserved_25a                                            :  8;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t mac_addr_ad2_47_32                                      : 16,
+                      amsdu_msdu_count                                        : 16;
+             uint32_t non_amsdu_msdu_count                                    : 16,
+                      ucast_msdu_count                                        : 16;
+             uint32_t bcast_msdu_count                                        : 16,
+                      mcast_bcast_msdu_count                                  : 16;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t reserved_1a                                             : 10,
+                      expected_response_ack_or_ba                             :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5,
+                      sta_full_aid                                            : 13;
+             uint32_t fw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_3b                                             :  7,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3a                                             :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      ht_control_info_null_valid                              :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_valid                                   :  1,
+                      qos_control_info_valid                                  :  1,
+                      frame_control_info_valid                                :  1,
+                      mpdu_cnt_fcs_ok                                         : 11;
+             uint32_t frame_control_field                                     : 16,
+                      ast_index                                               : 16;
+             uint32_t qos_control_field                                       : 16,
+                      first_data_seq_ctrl                                     : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t tcp_msdu_count                                          : 16,
+                      udp_msdu_count                                          : 16;
+             uint32_t tcp_ack_msdu_count                                      : 16,
+                      other_msdu_count                                        : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_eosp_bitmap                       : 16,
+                      received_qos_data_tid_bitmap                            : 16;
+             uint32_t qosctrl_15_8_tid3                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid0                                       :  8;
+             uint32_t qosctrl_15_8_tid7                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid4                                       :  8;
+             uint32_t qosctrl_15_8_tid11                                      :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid8                                       :  8;
+             uint32_t qosctrl_15_8_tid15                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid12                                      :  8;
+             uint32_t ampdu_delim_ok_count_6_0                                :  7,
+                      mpdu_ok_byte_count                                      : 25;
+             uint32_t ampdu_delim_ok_count_13_7                               :  7,
+                      ampdu_delim_err_count                                   : 25;
+             uint32_t ampdu_delim_ok_count_20_14                              :  7,
+                      mpdu_err_byte_count                                     : 25;
+             uint32_t retried_msdu_count                                      : 16,
+                      non_consecutive_delimiter_err                           : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t reserved_23a                                            :  3,
+                      retried_mpdu_count                                      : 11,
+                      frame_control_field_null                                : 16,
+                      frame_control_info_null_valid                           :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t frame_control_field_mgmt_ctrl                           : 16,
+                      mcast_bcast                                             :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      reserved_24a                                            :  4,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_25a                                            :  8,
+                      user_ppdu_len                                           : 24;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t amsdu_msdu_count                                        : 16,
+                      mac_addr_ad2_47_32                                      : 16;
+             uint32_t ucast_msdu_count                                        : 16,
+                      non_amsdu_msdu_count                                    : 16;
+             uint32_t mcast_bcast_msdu_count                                  : 16,
+                      bcast_msdu_count                                        : 16;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK  0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB          9
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB          15
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK         0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET      0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB         16
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB         31
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK        0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB                                     32
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB                                     44
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK                                    0x00001fff00000000
+
+#define RX_PPDU_END_USER_STATS_MCS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_MCS_LSB                                              45
+#define RX_PPDU_END_USER_STATS_MCS_MSB                                              49
+#define RX_PPDU_END_USER_STATS_MCS_MASK                                             0x0003e00000000000
+
+#define RX_PPDU_END_USER_STATS_NSS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_NSS_LSB                                              50
+#define RX_PPDU_END_USER_STATS_NSS_MSB                                              52
+#define RX_PPDU_END_USER_STATS_NSS_MASK                                             0x001c000000000000
+
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK                     0x0020000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB                                      54
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK                                     0xffc0000000000000
+
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET                                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB                                       0
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB                                       15
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK                                      0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET                              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB                                 16
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB                                 26
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK                                0x0000000007ff0000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000008000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000010000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000020000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK                       0x0000000040000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000080000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET                               0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB                                  32
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB                                  42
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK                                 0x000007ff00000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK                        0x0000080000000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET                        0x0000000000000008
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK                          0x0000100000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET                         0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK                           0x0000200000000000
+
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK                0x0000400000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK                      0x0000800000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK                             0x0001000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK                             0x0002000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK                         0x0004000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK                         0x0008000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK                                     0x0010000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB                        53
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB                        56
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK                       0x01e0000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB                                      57
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK                                     0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET                                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB                                        0
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB                                        15
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK                                       0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB                              16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB                              31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK                             0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB                              32
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB                              47
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK                             0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET                             0x0000000000000010
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK                               0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET                              0x0000000000000018
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB                                 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB                                 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET                            0x0000000000000018
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB                               32
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB                               63
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK                              0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET                           0x0000000000000020
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB                              0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB                              31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK                             0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB                                   32
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB                                   47
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK                                  0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB                                   48
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB                                   63
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK                                  0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET                              0x0000000000000028
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB                                 0
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB                                 15
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK                                0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET                            0x0000000000000028
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET                     0x0000000000000028
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB                        32
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB                        63
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET                  0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB                     0
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB                     15
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK                    0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB                16
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB                31
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK               0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB                                55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK                               0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB                                56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK                               0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK                               0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK                               0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB                                23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK                               0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB                                24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK                               0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB                               48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB                               55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK                              0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB                               56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB                               63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK                              0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB                               0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB                               7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK                              0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB                               8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB                               15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK                              0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB                               16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB                               23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK                              0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB                               24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB                               31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK                              0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB                               32
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB                               56
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK                              0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET                      0x0000000000000040
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB                         57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB                         63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK                        0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET                         0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB                            0
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB                            24
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK                           0x0000000001ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET                     0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB                        25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB                        31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK                       0x00000000fe000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET                           0x0000000000000048
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB                              32
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB                              56
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK                             0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET                    0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB                       57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB                       63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK                      0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET                 0x0000000000000050
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB                    0
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB                    15
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK                   0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET                            0x0000000000000050
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET                         0x0000000000000050
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB                            32
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB                            63
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK                           0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB                    0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB                    31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK                   0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                   0x0000000000000058
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                     0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK                   0x0000000200000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET                      0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB                         34
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB                         49
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK                        0x0003fffc00000000
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET                            0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB                               50
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB                               60
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK                              0x1ffc000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET                                  0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB                                     61
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK                                    0xe000000000000000
+
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                    0
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                    1
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                   0x0000000000000003
+
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET                             0x0000000000000060
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB                                2
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB                                8
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK                               0x00000000000001fc
+
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB                                     9
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB                                     12
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK                                    0x0000000000001e00
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK              0x0000000000002000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET                            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK                              0x0000000000004000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET                                   0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK                                     0x0000000000008000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB                    16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB                    31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK                   0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET                                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB                                    32
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB                                    55
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK                                   0x00ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB                                     56
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK                                    0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET                             0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB                                0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB                                31
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK                               0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET                            0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB                               32
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB                               47
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK                              0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET                              0x0000000000000068
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB                                 48
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB                                 63
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK                                0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET                          0x0000000000000070
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB                             0
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB                             15
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK                            0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB                                 16
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB                                 31
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK                                0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB                                 32
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB                                 47
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK                                0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET                        0x0000000000000070
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB                           48
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB                           63
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK                          0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_end_user_stats_ext.h b/hw/fig/v2/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 000000000000..0a11202db481
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4
+
+struct rx_ppdu_end_user_stats_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      reserved_7a                                             : 31;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t reserved_7a                                             : 31,
+                      corrupted_due_to_fifo_delay                             :  1;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB      9
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB      15
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK     0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB     16
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB     31
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK    0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET                       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB                          32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB                          63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK                         0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB                         0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB                         31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK                        0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET                     0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                 0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET                               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB                                  33
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB                                  63
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK                                 0xfffffffe00000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_no_ack_report.h b/hw/fig/v2/rx_ppdu_no_ack_report.h
new file mode 100644
index 000000000000..d9c54c04df32
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_no_ack_report.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_NO_ACK_REPORT_H_
+#define _RX_PPDU_NO_ACK_REPORT_H_
+
+#include "no_ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
+
+#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2
+
+struct rx_ppdu_no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   no_ack_report                                             no_ack_report_details;
+#else
+             struct   no_ack_report                                             no_ack_report_details;
+#endif
+};
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET   0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB      0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB      3
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK     0x000000000000000f
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB          4
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB          7
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK         0x00000000000000f0
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB          8
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB          15
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK         0x000000000000ff00
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET            0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB               16
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB               31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK              0x00000000ffff0000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET         0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB            32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB            55
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK           0x00ffffff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET      0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK        0x0100000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET               0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB                  61
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK                 0xe000000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB                  24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK                 0x00000000ff000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB                  44
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK                 0xfffff00000000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_start.h b/hw/fig/v2/rx_ppdu_start.h
new file mode 100644
index 000000000000..19765eb4409b
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_start.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+
+#define NUM_OF_DWORDS_RX_PPDU_START 6
+
+#define NUM_OF_QWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      preamble_time_to_rxframe                                :  8,
+                      reserved_0a                                             :  8;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      preamble_time_to_rxframe                                :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_PHY_PPDU_ID_LSB                                               0
+#define RX_PPDU_START_PHY_PPDU_ID_MSB                                               15
+#define RX_PPDU_START_PHY_PPDU_ID_MASK                                              0x000000000000ffff
+
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET                               0x0000000000000000
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB                                  16
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB                                  23
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK                                 0x0000000000ff0000
+
+#define RX_PPDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_RESERVED_0A_LSB                                               24
+#define RX_PPDU_START_RESERVED_0A_MSB                                               31
+#define RX_PPDU_START_RESERVED_0A_MASK                                              0x00000000ff000000
+
+#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000000
+#define RX_PPDU_START_SW_PHY_META_DATA_LSB                                          32
+#define RX_PPDU_START_SW_PHY_META_DATA_MSB                                          63
+#define RX_PPDU_START_SW_PHY_META_DATA_MASK                                         0xffffffff00000000
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET                               0x0000000000000010
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB                                  0
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB                                  31
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK                                 0x00000000ffffffff
+
+#define RX_PPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000010
+#define RX_PPDU_START_TLV64_PADDING_LSB                                             32
+#define RX_PPDU_START_TLV64_PADDING_MSB                                             63
+#define RX_PPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_ppdu_start_user_info.h b/hw/fig/v2/rx_ppdu_start_user_info.h
new file mode 100644
index 000000000000..16d3bb33edb4
--- /dev/null
+++ b/hw/fig/v2/rx_ppdu_start_user_info.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8
+
+#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4
+
+struct rx_ppdu_start_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB           0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB           15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK          0x000000000000ffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET          0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB             16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB             23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK            0x0000000000ff0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB              24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB              27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK             0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET               0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                 0x0000000010000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB        29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB        31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK       0x00000000e0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB              32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB              36
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK             0x0000001f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                   38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                  0x0000006000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB        40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB        47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK       0x0000ff0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET  0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB     48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB     50
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK    0x0007000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB           51
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK          0x00f8000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB   63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK  0xff00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK          0x0000000000000002
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB             2
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB             3
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK            0x000000000000000c
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB             4
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB             5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK            0x0000000000000030
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB             6
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB             7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK            0x00000000000000c0
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                   8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                   10
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                  0x0000000000000700
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET      0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB         11
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB         13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK        0x0000000000003800
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET            0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK              0x0000000000004000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET               0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                 0x0000000000008000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB          16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB          19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK         0x00000000000f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB          20
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB          23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK         0x0000000000f00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB          24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB          27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK         0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB          28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB          31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK         0x00000000f0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB   32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK  0x0000003f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB           38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB           39
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK          0x000000c000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB   40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB   45
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK  0x00003f0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB           46
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB           47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK          0x0000c00000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB   48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB   53
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK  0x003f000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB           54
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK          0x00c0000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB   61
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK  0x3f00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET   0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB      62
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB      62
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK     0x4000000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB           63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB           63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK          0x8000000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK    0xffffffff00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK    0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_preamble.h b/hw/fig/v2/rx_preamble.h
new file mode 100644
index 000000000000..807463753865
--- /dev/null
+++ b/hw/fig/v2/rx_preamble.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PREAMBLE_H_
+#define _RX_PREAMBLE_H_
+
+#define NUM_OF_DWORDS_RX_PREAMBLE 2
+
+#define NUM_OF_QWORDS_RX_PREAMBLE 1
+
+struct rx_preamble {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      pkt_type                                                :  4,
+                      direction                                               :  1,
+                      reserved_0a                                             : 21;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 21,
+                      direction                                               :  1,
+                      pkt_type                                                :  4,
+                      num_users                                               :  6;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PREAMBLE_NUM_USERS_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_NUM_USERS_LSB                                                   0
+#define RX_PREAMBLE_NUM_USERS_MSB                                                   5
+#define RX_PREAMBLE_NUM_USERS_MASK                                                  0x000000000000003f
+
+#define RX_PREAMBLE_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define RX_PREAMBLE_PKT_TYPE_LSB                                                    6
+#define RX_PREAMBLE_PKT_TYPE_MSB                                                    9
+#define RX_PREAMBLE_PKT_TYPE_MASK                                                   0x00000000000003c0
+
+#define RX_PREAMBLE_DIRECTION_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_DIRECTION_LSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MASK                                                  0x0000000000000400
+
+#define RX_PREAMBLE_RESERVED_0A_OFFSET                                              0x0000000000000000
+#define RX_PREAMBLE_RESERVED_0A_LSB                                                 11
+#define RX_PREAMBLE_RESERVED_0A_MSB                                                 31
+#define RX_PREAMBLE_RESERVED_0A_MASK                                                0x00000000fffff800
+
+#define RX_PREAMBLE_TLV64_PADDING_OFFSET                                            0x0000000000000000
+#define RX_PREAMBLE_TLV64_PADDING_LSB                                               32
+#define RX_PREAMBLE_TLV64_PADDING_MSB                                               63
+#define RX_PREAMBLE_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_response_required_info.h b/hw/fig/v2/rx_response_required_info.h
new file mode 100644
index 000000000000..11da8b5e0bb2
--- /dev/null
+++ b/hw/fig/v2/rx_response_required_info.h
@@ -0,0 +1,764 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
+#define _RX_RESPONSE_REQUIRED_INFO_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16
+
+#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8
+
+struct rx_response_required_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      su_or_uplink_mu_reception                               :  1,
+                      trigger_frame_received                                  :  1,
+                      __reserved_g_0012                                                  :  2,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      mac_security                                            :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2;
+             uint32_t general_frame_control                                   : 16,
+                      second_frame_control                                    : 16;
+             uint32_t duration                                                : 16,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      ampdu                                                   :  1,
+                      rts_ta_grp_bit                                          :  1;
+             uint32_t ctrl_frame_soliciting_resp                              :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      service_dynamic                                         :  1,
+                      m_pkt                                                   :  1,
+                      sta_partial_aid                                         : 12,
+                      group_id                                                :  6,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      response_indication                                     :  2,
+                      ndp_indication                                          :  1,
+                      ndp_frame_type                                          :  3,
+                      second_frame_control_valid                              :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      vht_ack                                                 :  1;
+             uint32_t sta_aid                                                 : 11,
+                      interference                                            :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      ll_traffic_indication                                   :  1,
+                      reserved_4a                                             :  2,
+                      ack_id_ext                                              : 10,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             uint32_t response_sta_count                                      :  7,
+                      __reserved_g_0035                                                 :  1,
+                      blackout_details_en                                     :  1,
+                      reserved                                                :  2,
+                      ht_vht_sig_cbw                                          :  3,
+                      cts_cbw                                                 :  3,
+                      response_ack_count                                      :  7,
+                      response_assoc_ack_count                                :  7,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t response_ba32_count                                     :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba256_count                                    :  7,
+                      multi_tid                                               :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      emlsr_main_tlv_if                                       :  1;
+             uint32_t sw_response_frame_length                                : 16,
+                      response_ba512_count                                    :  7,
+                      response_ba1024_count                                   :  7,
+                      reserved_7a                                             :  2;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      ftm_fields_valid                                        :  1,
+                      ftm_pe_nss                                              :  3,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_content                                          :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_chain_csd_en                                     :  1;
+             uint32_t dot11ax_response_rate_source                            :  8,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      sw_peer_id                                              : 16;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      force_extra_symbol                                      :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      reserved_13a                                            :  3,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t he_a_control_response_time                              : 12,
+                      reserved_after_struct16                                 :  4;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      q2q_mba                                                 :  1,
+                      reserved_15a                                            :  6;
+#else
+             uint32_t wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      mac_security                                            :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      __reserved_g_0012                                                  :  2,
+                      trigger_frame_received                                  :  1,
+                      su_or_uplink_mu_reception                               :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t second_frame_control                                    : 16,
+                      general_frame_control                                   : 16;
+             uint32_t rts_ta_grp_bit                                          :  1,
+                      ampdu                                                   :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      duration                                                : 16;
+             uint32_t vht_ack                                                 :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      second_frame_control_valid                              :  1,
+                      ndp_frame_type                                          :  3,
+                      ndp_indication                                          :  1,
+                      response_indication                                     :  2,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 12,
+                      m_pkt                                                   :  1,
+                      service_dynamic                                         :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      ctrl_frame_soliciting_resp                              :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      ack_id_ext                                              : 10,
+                      reserved_4a                                             :  2,
+                      ll_traffic_indication                                   :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      interference                                            :  1,
+                      sta_aid                                                 : 11;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      response_assoc_ack_count                                :  7,
+                      response_ack_count                                      :  7,
+                      cts_cbw                                                 :  3,
+                      ht_vht_sig_cbw                                          :  3,
+                      reserved                                                :  2,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0035                                                 :  1,
+                      response_sta_count                                      :  7;
+             uint32_t emlsr_main_tlv_if                                       :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      multi_tid                                               :  1,
+                      response_ba256_count                                    :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba32_count                                     :  7;
+             uint32_t reserved_7a                                             :  2,
+                      response_ba1024_count                                   :  7,
+                      response_ba512_count                                    :  7,
+                      sw_response_frame_length                                : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ftm_pe_chain_csd_en                                     :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_content                                          :  1,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_nss                                              :  3,
+                      ftm_fields_valid                                        :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t sw_peer_id                                              : 16,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      dot11ax_response_rate_source                            :  8;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_13a                                            :  3,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_after_struct16                                 :  4,
+                      he_a_control_response_time                              : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t reserved_15a                                            :  6,
+                      q2q_mba                                                 :  1,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+#endif
+};
+
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET                                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK                                  0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK                    0x0000000000010000
+
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK                       0x0000000000020000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET                               0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK                                 0x0000000000400000
+
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK                     0x0000000000800000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK                        0x0000000001000000
+
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK                     0x0000000002000000
+
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK                  0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK                       0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET                                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB                                     30
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB                                     31
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK                                    0x00000000c0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB                         32
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB                         47
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK                        0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET                       0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB                          63
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK                         0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB                                      0
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB                                      15
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK                                     0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB                                      16
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB                                      19
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK                                     0x00000000000f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK                          0x0000000000100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB                                      21
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB                                      25
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK                                     0x0000000003e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET                                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB                                           26
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB                                           27
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK                                          0x000000000c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK                                         0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK                                         0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK                                        0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK                               0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK                   0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET                0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK                              0x0000000400000000
+
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK                                        0x0000000800000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB                               36
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB                               47
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK                              0x0000fff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB                                      48
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB                                      53
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK                                     0x003f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET                         0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK                           0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB                           55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB                           56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK                          0x0180000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK                               0x0200000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB                                58
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB                                60
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK                               0x1c00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK                   0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK                        0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK                                      0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB                                       0
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB                                       10
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK                                      0x00000000000007ff
+
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET                               0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK                                 0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET                            0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK                              0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET                      0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB                         13
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB                         13
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK                        0x0000000000002000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB                                   14
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK                                  0x000000000000c000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET                                 0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB                                    25
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK                                   0x0000000003ff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB                                       26
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB                                       28
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK                                      0x000000001c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB                                   29
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK                                  0x00000000e0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB                            32
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB                            38
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK                           0x0000007f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET                        0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK                          0x0000010000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET                                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB                                      41
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB                                      42
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK                                     0x0000060000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET                             0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB                                43
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB                                45
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK                               0x0000380000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB                                       46
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB                                       48
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK                                      0x0001c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB                            55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK                           0x00fe000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB                      56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB                      62
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK                     0x7f00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET                     0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK                       0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB                           0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB                           6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK                          0x000000000000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB                           7
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB                           13
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK                          0x0000000000003f80
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB                          14
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB                          20
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK                         0x00000000001fc000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB                          21
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB                          27
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK                         0x000000000fe00000
+
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET                                  0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK                                    0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                  0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET                         0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK                           0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET                          0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK                            0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                   0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                      32
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                      47
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                     0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB                          54
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK                         0x007f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET                      0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB                         55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB                         61
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK                        0x3f80000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET                                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB                                   62
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB                                   63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK                                  0xc000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB                                    0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK                                   0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET                                0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB                                   32
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB                                   47
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK                                  0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB                                    48
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB                                    63
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK                                   0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET                                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK                                  0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET         0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK           0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET              0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                 34
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                 39
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                0x000000fc00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                40
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                43
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK               0x00000f0000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                   0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                      44
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                      45
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                     0x0000300000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                  0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                     46
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                     47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                    0x0000c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET                    0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK                      0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET                       0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK                         0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK          0x0004000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  51
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  54
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0078000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK                             0x0080000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET                                 0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB                                    56
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB                                    58
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK                                   0x0700000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET                            0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB                               59
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB                               60
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK                              0x1800000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET                             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK                               0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK                             0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET                        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK                          0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB                  0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB                  7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK                 0x00000000000000ff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB              8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB              15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK             0x000000000000ff00
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET                                 0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK                                   0x00000000ffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                    0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                       32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                       47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                      0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK                             0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK                           0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB                            50
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB                            51
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK                           0x000c000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK                           0x0010000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK                             0x0020000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET                            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK                              0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET                               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB                                  55
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB                                  57
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK                                 0x0380000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               58
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               63
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x00000000000003ff
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x0000000000000400
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x000000000000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB                    16
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB                    27
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK                   0x000000000fff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET                    0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB                       28
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB                       31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK                      0x00000000f0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB                    35
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK                   0x0000000f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB         36
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB         51
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK        0x000ffff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB                                  52
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB                                  56
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK                                 0x01f0000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET                                    0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB                                       57
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB                                       57
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK                                      0x0200000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB                                  58
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB                                  63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK                                 0xfc00000000000000
+
+#endif
diff --git a/hw/fig/v2/rx_rxpcu_classification_overview.h b/hw/fig/v2/rx_rxpcu_classification_overview.h
new file mode 100644
index 000000000000..92489a5f5b2d
--- /dev/null
+++ b/hw/fig/v2/rx_rxpcu_classification_overview.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t filter_pass_mpdus                                       :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      phyrx_abort_received                                    :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      phyrx_abort_received                                    :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      filter_pass_mpdus                                       :  1;
+#endif
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET                   0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK                     0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET            0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK              0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK                  0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK           0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET                 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK                   0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK            0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK                  0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET      0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK        0x00000080
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET                          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB                             9
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB                             15
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK                            0x0000fe00
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET                         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB                            16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB                            31
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK                           0xffff0000
+
+#endif
diff --git a/hw/fig/v2/rx_start_param.h b/hw/fig/v2/rx_start_param.h
new file mode 100644
index 000000000000..bb2b87e3cc97
--- /dev/null
+++ b/hw/fig/v2/rx_start_param.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_START_PARAM_H_
+#define _RX_START_PARAM_H_
+
+#define NUM_OF_DWORDS_RX_START_PARAM 2
+
+#define NUM_OF_QWORDS_RX_START_PARAM 1
+
+struct rx_start_param {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      reserved_0a                                             : 12,
+                      remaining_rx_time                                       : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t remaining_rx_time                                       : 16,
+                      reserved_0a                                             : 12,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_START_PARAM_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define RX_START_PARAM_PKT_TYPE_LSB                                                 0
+#define RX_START_PARAM_PKT_TYPE_MSB                                                 3
+#define RX_START_PARAM_PKT_TYPE_MASK                                                0x000000000000000f
+
+#define RX_START_PARAM_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define RX_START_PARAM_RESERVED_0A_LSB                                              4
+#define RX_START_PARAM_RESERVED_0A_MSB                                              15
+#define RX_START_PARAM_RESERVED_0A_MASK                                             0x000000000000fff0
+
+#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET                                     0x0000000000000000
+#define RX_START_PARAM_REMAINING_RX_TIME_LSB                                        16
+#define RX_START_PARAM_REMAINING_RX_TIME_MSB                                        31
+#define RX_START_PARAM_REMAINING_RX_TIME_MASK                                       0x00000000ffff0000
+
+#define RX_START_PARAM_TLV64_PADDING_OFFSET                                         0x0000000000000000
+#define RX_START_PARAM_TLV64_PADDING_LSB                                            32
+#define RX_START_PARAM_TLV64_PADDING_MSB                                            63
+#define RX_START_PARAM_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rx_timing_info.h b/hw/fig/v2/rx_timing_info.h
new file mode 100644
index 000000000000..ea6780e25c55
--- /dev/null
+++ b/hw/fig/v2/rx_timing_info.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TIMING_INFO_H_
+#define _RX_TIMING_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TIMING_INFO 5
+
+struct rx_timing_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t residual_phase_offset                                   : 12,
+                      sub_usec_ts_rx_end                                      : 10,
+                      reserved                                                : 10;
+#else
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t reserved                                                : 10,
+                      sub_usec_ts_rx_end                                      : 10,
+                      residual_phase_offset                                   : 12;
+#endif
+};
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET                              0x00000000
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET                              0x00000004
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET                              0x00000008
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET                              0x0000000c
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                                 0x00000010
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB                                    0
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB                                    11
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK                                   0x00000fff
+
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET                                    0x00000010
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB                                       12
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB                                       21
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK                                      0x003ff000
+
+#define RX_TIMING_INFO_RESERVED_OFFSET                                              0x00000010
+#define RX_TIMING_INFO_RESERVED_LSB                                                 22
+#define RX_TIMING_INFO_RESERVED_MSB                                                 31
+#define RX_TIMING_INFO_RESERVED_MASK                                                0xffc00000
+
+#endif
diff --git a/hw/fig/v2/rx_trig_info.h b/hw/fig/v2/rx_trig_info.h
new file mode 100644
index 000000000000..b6b074118bea
--- /dev/null
+++ b/hw/fig/v2/rx_trig_info.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TRIG_INFO_H_
+#define _RX_TRIG_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TRIG_INFO 2
+
+#define NUM_OF_QWORDS_RX_TRIG_INFO 1
+
+struct rx_trig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_trigger_frame_type                                   :  2,
+                      trigger_resp_type                                       :  3,
+                      reserved_0                                              : 27;
+             uint32_t ppdu_duration                                           : 16,
+                      unique_destination_id                                   : 16;
+#else
+             uint32_t reserved_0                                              : 27,
+                      trigger_resp_type                                       :  3,
+                      rx_trigger_frame_type                                   :  2;
+             uint32_t unique_destination_id                                   : 16,
+                      ppdu_duration                                           : 16;
+#endif
+};
+
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB                                      0
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB                                      1
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK                                     0x0000000000000003
+
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET                                       0x0000000000000000
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB                                          2
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB                                          4
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK                                         0x000000000000001c
+
+#define RX_TRIG_INFO_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_TRIG_INFO_RESERVED_0_LSB                                                 5
+#define RX_TRIG_INFO_RESERVED_0_MSB                                                 31
+#define RX_TRIG_INFO_RESERVED_0_MASK                                                0x00000000ffffffe0
+
+#define RX_TRIG_INFO_PPDU_DURATION_OFFSET                                           0x0000000000000000
+#define RX_TRIG_INFO_PPDU_DURATION_LSB                                              32
+#define RX_TRIG_INFO_PPDU_DURATION_MSB                                              47
+#define RX_TRIG_INFO_PPDU_DURATION_MASK                                             0x0000ffff00000000
+
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB                                      48
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB                                      63
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/rxpcu_early_rx_indication.h b/hw/fig/v2/rxpcu_early_rx_indication.h
new file mode 100644
index 000000000000..d2dc464cf1cf
--- /dev/null
+++ b/hw/fig/v2/rxpcu_early_rx_indication.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_EARLY_RX_INDICATION_H_
+#define _RXPCU_EARLY_RX_INDICATION_H_
+
+#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2
+
+#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1
+
+struct rxpcu_early_rx_indication {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      reserved_0a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 18,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB                                      0
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB                                      3
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK                                     0x000000000000000f
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK                          0x0000000000000010
+
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB                                      5
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB                                      9
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK                                     0x00000000000003e0
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  10
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  13
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0000000000003c00
+
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET                                0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB                                   14
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB                                   31
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK                                  0x00000000ffffc000
+
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET                              0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB                                 32
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB                                 63
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK                                0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rxpcu_ppdu_end_info.h b/hw/fig/v2/rxpcu_ppdu_end_info.h
new file mode 100644
index 000000000000..c97ad08c26a4
--- /dev/null
+++ b/hw/fig/v2/rxpcu_ppdu_end_info.h
@@ -0,0 +1,925 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+#include "rxpcu_ppdu_end_layout_info.h"
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32
+
+#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16
+
+struct rxpcu_ppdu_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t rx_antenna                                              : 24,
+                      tx_ht_vht_ack                                           :  1,
+                      unsupported_mu_nc                                       :  1,
+                      otp_txbf_disable                                        :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      coex_wan_tx_after_start_of_rx_ratid1                    :  1;
+             uint32_t coex_bt_tx_from_start_of_rx                             :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      __reserved_g_0012                                                  :  2,
+                      dialog_token                                            :  8,
+                      follow_up_dialog_token                                  :  8,
+                      bb_captured_channel                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_timeout                                     :  1,
+                      __reserved_g_0054                                       :  1,
+                      __reserved_g_0058                                       :  1;
+             uint32_t before_mpdu_count_passing_fcs                           : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      reserved_4                                              :  2;
+             uint32_t after_mpdu_count_failing_fcs                            : 10,
+                      reserved_5                                              : 22;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t bb_length                                               : 16,
+                      bb_data                                                 :  1,
+                      reserved_8                                              :  3,
+                      first_bt_broadcast_status_details                       : 12;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      reserved_9                                              :  8;
+             uint32_t ast_index                                               : 16,
+                      ast_index_valid                                         :  1,
+                      reserved_10                                             :  3,
+                      second_bt_broadcast_status_details                      : 12;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint16_t pre_bt_broadcast_status_details                         : 12,
+                      reserved_12a                                            :  4;
+             uint32_t non_qos_sn_info_valid                                   :  1,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      rts_or_trig_prot_type                                   :  2,
+                      reserved_13a                                            :  2,
+                      non_qos_sn_highest                                      : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_lowest_retry_setting                         :  1;
+             uint32_t qos_sn_1_info_valid                                     :  1,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_tid                                            :  4,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_lowest_retry_setting                           :  1;
+             uint32_t qos_sn_2_info_valid                                     :  1,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_tid                                            :  4,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_lowest_retry_setting                           :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      qos_sn_1_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_peer_addr_15_0                         : 16;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t coex_tracker2_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      reserved_30a                                            : 22;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#else
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t coex_wan_tx_after_start_of_rx_ratid1                    :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      otp_txbf_disable                                        :  1,
+                      unsupported_mu_nc                                       :  1,
+                      tx_ht_vht_ack                                           :  1,
+                      rx_antenna                                              : 24;
+             uint32_t __reserved_g_0058                                       :  1,
+                      __reserved_g_0054                                       :  1,
+                      bb_captured_timeout                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_channel                                     :  1,
+                      follow_up_dialog_token                                  :  8,
+                      dialog_token                                            :  8,
+                      __reserved_g_0012                                                  :  2,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_bt_tx_from_start_of_rx                             :  1;
+             uint32_t reserved_4                                              :  2,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      before_mpdu_count_passing_fcs                           : 10;
+             uint32_t reserved_5                                              : 22,
+                      after_mpdu_count_failing_fcs                            : 10;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t first_bt_broadcast_status_details                       : 12,
+                      reserved_8                                              :  3,
+                      bb_data                                                 :  1,
+                      bb_length                                               : 16;
+             uint32_t reserved_9                                              :  8,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_10                                             :  3,
+                      ast_index_valid                                         :  1,
+                      ast_index                                               : 16;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             uint32_t reserved_12a                                            :  4,
+                      pre_bt_broadcast_status_details                         : 12;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint32_t non_qos_sn_lowest_retry_setting                         :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_highest                                      : 12,
+                      reserved_13a                                            :  2,
+                      rts_or_trig_prot_type                                   :  2,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      non_qos_sn_info_valid                                   :  1;
+             uint32_t qos_sn_1_lowest_retry_setting                           :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_tid                                            :  4,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_info_valid                                     :  1;
+             uint32_t qos_sn_2_lowest_retry_setting                           :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_tid                                            :  4,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_info_valid                                     :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t rts_or_trig_prot_peer_addr_15_0                         : 16,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_1_more_frag_state                                :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t reserved_30a                                            : 22,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker2_tx_from_start_of_rx                       :  1;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB                               0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB                               31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK                              0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB                               32
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB                               63
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK                              0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET                                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB                                          0
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB                                          23
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK                                         0x0000000000ffffff
+
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK                                      0x0000000001000000
+
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET                                0x0000000000000008
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK                                  0x0000000002000000
+
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET                                 0x0000000000000008
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK                                   0x0000000004000000
+
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK                             0x0000000008000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000020000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK                0x0000000040000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET             0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK               0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET                      0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK                        0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK                       0x0000000400000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK                      0x0000000800000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK                      0x0000001000000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK                     0x0000002000000000
+
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK                         0x0000004000000000
+
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET                                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB                                        41
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB                                        48
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK                                       0x0001fe0000000000
+
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB                              49
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB                              56
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK                             0x01fe000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK                                0x0200000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET                               0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB                                  58
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB                                  60
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK                                 0x1c00000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK                                0x2000000000000000
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB                       0
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB                       9
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK                      0x00000000000003ff
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB                       10
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB                       19
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK                      0x00000000000ffc00
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB                        20
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB                        29
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK                       0x000000003ff00000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB                                          30
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK                                         0x00000000c0000000
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB                        32
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB                        41
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK                       0x000003ff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB                                          42
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK                                         0xfffffc0000000000
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB                           0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB                           31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK                          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB                           32
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB                           63
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK                          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET                                        0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB                                           0
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB                                           15
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET                                          0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_DATA_LSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MASK                                            0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB                                          17
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB                                          19
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK                                         0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                0x0000000000000020
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                   20
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                   31
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                  0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET                                 0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB                                    32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB                                    55
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK                                   0x00ffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB                                          56
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK                                         0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET                                        0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB                                           0
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB                                           15
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET                                  0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK                                    0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET                                      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB                                         17
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB                                         19
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK                                        0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET               0x0000000000000028
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                  20
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                  31
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                 0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK  0x0000200000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK   0x0000400000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB   48
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB   63
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK  0xffff000000000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         8
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         15
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                     16
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                     27
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                    0x000000000fff0000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB                                        28
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK                                       0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK                              0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET                       0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK                         0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB                               34
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB                               35
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK                              0x0000000c00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB                                        36
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB                                        37
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK                                       0x0000003000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET                               0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB                                  38
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB                                  49
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK                                 0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET                 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK                   0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET                                0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB                                   51
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB                                   62
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK                                  0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK                    0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK                                0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK                                       0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB                                        2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB                                        5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK                                       0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB                                    6
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB                                    17
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK                                   0x000000000003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK                     0x0000000000040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB                                     19
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB                                     30
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK                                    0x000000007ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK                      0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK                                0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK                                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB                                        34
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB                                        37
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK                                       0x0000003c00000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB                                    38
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB                                    49
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK                                   0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK                     0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB                                     51
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB                                     62
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK                                    0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK                      0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB    0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB    1
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK   0x0000000000000003
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB        2
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB        7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK       0x00000000000000fc
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB        8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB        13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK       0x0000000000003f00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET      0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB         14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB         19
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK        0x00000000000fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET   0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB      20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB      25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK     0x0000000003f00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB    32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB    37
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK   0x0000003f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB  50
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB  55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB        56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB        62
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK       0x7f00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET        0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK          0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB           28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK          0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB           60
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK          0xf000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB   0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB   6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK  0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB   7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB   13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK  0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB           29
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK          0x00000000e0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB           57
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK          0xfe00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET   0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB      0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB      7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK     0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB  16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB  23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET    0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB       24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB       31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK      0x00000000ff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET     0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB        40
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB        47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK       0x0000ff0000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET        0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB           56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK          0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB           0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB           32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                      0x0000000000000068
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                        0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK                           0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB                             2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB                             5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK                            0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK                           0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB                             7
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB                             10
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK                            0x0000000000000780
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK                           0x0000000000000800
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET                        0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB                           12
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB                           15
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK                          0x000000000000f000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET                  0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB                     16
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB                     31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK                    0x00000000ffff0000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET                 0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB                    32
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB                    63
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK                   0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB                                0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB                                31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK                               0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB                                32
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB                                63
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK                               0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK                  0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK                 0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK                  0x0000000000000004
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK                 0x0000000000000008
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK                  0x0000000000000010
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK                 0x0000000000000020
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK                  0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK                 0x0000000000000080
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK                  0x0000000000000100
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK                 0x0000000000000200
+
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET                                     0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB                                        10
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK                                       0x00000000fffffc00
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET                               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB                                  32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB                                  63
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/rxpcu_ppdu_end_layout_info.h b/hw/fig/v2/rxpcu_ppdu_end_layout_info.h
new file mode 100644
index 000000000000..9d54e91522ec
--- /dev/null
+++ b/hw/fig/v2/rxpcu_ppdu_end_layout_info.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
+#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
+
+struct rxpcu_ppdu_end_layout_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_legacy_offset                                      :  2,
+                      l_sig_a_offset                                          :  6,
+                      l_sig_b_offset                                          :  6,
+                      ht_sig_offset                                           :  6,
+                      vht_sig_a_offset                                        :  6,
+                      repeat_l_sig_a_offset                                   :  6;
+             uint32_t he_sig_a_su_offset                                      :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      generic_u_sig_offset                                    :  6,
+                      rssi_ht_offset                                          :  7,
+                      reserved_1a                                             :  1;
+             uint32_t vht_sig_b_su20_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su160_offset                                  :  7,
+                      reserved_2a                                             :  4;
+             uint32_t vht_sig_b_mu20_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      reserved_3a                                             :  4;
+             uint32_t he_sig_b1_mu_offset                                     :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      first_generic_eht_sig_offset                            :  7,
+                      multiple_generic_eht_sig_included                       :  1,
+                      reserved_4a                                             :  3;
+             uint32_t common_user_info_offset                                 :  7,
+                      first_debug_info_offset                                 :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_other_receive_info_included                    :  1,
+                      reserved_5a                                             :  7;
+             uint32_t data_done_offset                                        :  8,
+                      generated_cbf_details_offset                            :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      location_offset                                         :  8;
+             uint32_t __reserved_g_0011                                       :  8,
+                      pkt_end_offset                                          :  8,
+                      abort_request_ack_offset                                :  8,
+                      reserved_7a                                             :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#else
+             uint32_t repeat_l_sig_a_offset                                   :  6,
+                      vht_sig_a_offset                                        :  6,
+                      ht_sig_offset                                           :  6,
+                      l_sig_b_offset                                          :  6,
+                      l_sig_a_offset                                          :  6,
+                      rssi_legacy_offset                                      :  2;
+             uint32_t reserved_1a                                             :  1,
+                      rssi_ht_offset                                          :  7,
+                      generic_u_sig_offset                                    :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_su_offset                                      :  6;
+             uint32_t reserved_2a                                             :  4,
+                      vht_sig_b_su160_offset                                  :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su20_offset                                   :  7;
+             uint32_t reserved_3a                                             :  4,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu20_offset                                   :  7;
+             uint32_t reserved_4a                                             :  3,
+                      multiple_generic_eht_sig_included                       :  1,
+                      first_generic_eht_sig_offset                            :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b1_mu_offset                                     :  7;
+             uint32_t reserved_5a                                             :  7,
+                      multiple_other_receive_info_included                    :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_debug_info_offset                                 :  8,
+                      common_user_info_offset                                 :  7;
+             uint32_t location_offset                                         :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      generated_cbf_details_offset                            :  8,
+                      data_done_offset                                        :  8;
+             uint32_t reserved_7a                                             :  8,
+                      abort_request_ack_offset                                :  8,
+                      pkt_end_offset                                          :  8,
+                      __reserved_g_0011                                       :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET                        0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB                           1
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK                          0x00000003
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB                               2
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB                               7
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK                              0x000000fc
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB                               13
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK                              0x00003f00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET                             0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB                                14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB                                19
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK                               0x000fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET                          0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB                             20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB                             25
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK                            0x03f00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET                     0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB                        26
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB                        31
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK                       0xfc000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET                        0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB                           5
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK                          0x0000003f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB                        11
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK                       0x00000fc0
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB                        12
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB                        17
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK                       0x0003f000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET                      0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB                         18
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK                        0x00fc0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET                            0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB                               24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB                               30
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK                              0x7f000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET                               0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK                                 0x80000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET                    0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET                               0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET                               0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB                          0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB                          6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK                         0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB                          7
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB                          13
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK                         0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB                       14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB                       20
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK                      0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET              0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB                 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB                 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK                0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET         0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK           0x10000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET                               0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB                                  29
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK                                 0xe0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB                      0
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB                      6
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK                     0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB                      7
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB                      14
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK                     0x00007f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET              0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK                0x00008000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET           0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB              16
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB              23
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK             0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET      0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK        0x01000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET                               0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB                                  25
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK                                 0xfe000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET                          0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB                             0
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB                             7
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK                            0x000000ff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET              0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB                 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK                0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET                      0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB                         16
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK                        0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET                           0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB                              24
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB                              31
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK                             0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET                            0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB                               15
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK                              0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET                  0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB                     16
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB                     23
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK                    0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET                               0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB                                  24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK                                 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET                               0x00000020
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK                                 0xffffffff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET                               0x00000024
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/fig/v2/rxpt_classify_info.h b/hw/fig/v2/rxpt_classify_info.h
new file mode 100644
index 000000000000..7fc572ae2474
--- /dev/null
+++ b/hw/fig/v2/rxpt_classify_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      lmac_peer_id_msb                                        :  2,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_1000                                   :  1,
+                      rxdma0_source_ring_selection                            :  3,
+                      rxdma0_destination_ring_selection                       :  3,
+                      mcast_echo_drop_enable                                  :  1,
+                      wds_learning_detect_en                                  :  1,
+                      intrabss_check_en                                       :  1,
+                      use_ppe                                                 :  1,
+                      ppe_routing_enable                                      :  1,
+                      cce_source_sel_en                                       :  1,
+                      reserved_0b                                             :  9;
+#else
+             uint32_t reserved_0b                                             :  9,
+                      cce_source_sel_en                                       :  1,
+                      ppe_routing_enable                                      :  1,
+                      use_ppe                                                 :  1,
+                      intrabss_check_en                                       :  1,
+                      wds_learning_detect_en                                  :  1,
+                      mcast_echo_drop_enable                                  :  1,
+                      rxdma0_destination_ring_selection                       :  3,
+                      rxdma0_source_ring_selection                            :  3,
+                      pkt_selection_fp_1000                                   :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      lmac_peer_id_msb                                        :  2,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET                        0x00000000
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB                           0
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB                           4
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK                          0x0000001f
+
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET                                  0x00000000
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB                                     5
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB                                     6
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK                                    0x00000060
+
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET                         0x00000000
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK                           0x00000080
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK                         0x00000100
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK                         0x00000200
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET                             0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK                               0x00000400
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB                         11
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB                         13
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK                        0x00003800
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB                    14
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB                    16
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK                   0x0001c000
+
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK                              0x00020000
+
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK                              0x00040000
+
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK                                   0x00080000
+
+#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET                                           0x00000000
+#define RXPT_CLASSIFY_INFO_USE_PPE_LSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MASK                                             0x00100000
+
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET                                0x00000000
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK                                  0x00200000
+
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK                                   0x00400000
+
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB                                          23
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB                                          31
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK                                         0xff800000
+
+#endif
diff --git a/hw/fig/v2/seq_hwio.h b/hw/fig/v2/seq_hwio.h
new file mode 100644
index 000000000000..69111d08d535
--- /dev/null
+++ b/hw/fig/v2/seq_hwio.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/hw/fig/v2/tcl_assist_cmd.h b/hw/fig/v2/tcl_assist_cmd.h
new file mode 100644
index 000000000000..f7a5bd5287cb
--- /dev/null
+++ b/hw/fig/v2/tcl_assist_cmd.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_ASSIST_CMD_H_
+#define _TCL_ASSIST_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16
+
+struct tcl_assist_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t buf_or_ext_desc_type                                    :  1,
+                      bank_id                                                 :  6,
+                      vdev_id                                                 :  8,
+                      data_length                                             : 14,
+                      to_fw_tqm                                               :  2,
+                      reserved_2a                                             :  1;
+             uint32_t reserved_3a                                             : 25,
+                      metadata_length                                         :  7;
+             uint32_t txpt_classify_info_index                                :  8,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_override                             :  1,
+                      flow_override_enable                                    :  1,
+                      flow_select                                             :  1,
+                      hlos_tid                                                :  4,
+                      hlos_tid_overwrite                                      :  1,
+                      tos_tc_value                                            :  8,
+                      reserved_4a                                             :  3;
+             uint32_t reserved_5a                                             : 16,
+                      l3_type                                                 : 16;
+             uint32_t l4_protocol                                             :  8,
+                      l4_port                                                 : 16,
+                      l4_port_type                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      da_is_bcast                                             :  1,
+                      reserved_6a                                             :  5;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t ip_da_or_sa                                             :  1,
+                      encap_length_change                                     :  6,
+                      encap_length_decrease                                   :  1,
+                      encap_length_override                                   :  1,
+                      type_or_length                                          :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      msdu_color                                              :  2,
+                      tx_notify_frame                                         :  3,
+                      tqm_no_drop                                             :  1,
+                      reserved_11a                                            : 12,
+                      l3_checksum_enable                                      :  1,
+                      l4_checksum_enable                                      :  1;
+             uint32_t buffer_timestamp                                        : 19,
+                      buffer_timestamp_valid                                  :  1,
+                      s_vlan_tag_present                                      :  1,
+                      c_vlan_tag_present                                      :  1,
+                      wmac_hdr_len                                            :  7,
+                      reserved_12a                                            :  3;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t reserved_2a                                             :  1,
+                      to_fw_tqm                                               :  2,
+                      data_length                                             : 14,
+                      vdev_id                                                 :  8,
+                      bank_id                                                 :  6,
+                      buf_or_ext_desc_type                                    :  1;
+             uint32_t metadata_length                                         :  7,
+                      reserved_3a                                             : 25;
+             uint32_t reserved_4a                                             :  3,
+                      tos_tc_value                                            :  8,
+                      hlos_tid_overwrite                                      :  1,
+                      hlos_tid                                                :  4,
+                      flow_select                                             :  1,
+                      flow_override_enable                                    :  1,
+                      txpt_classify_info_override                             :  1,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_index                                :  8;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             : 16;
+             uint32_t reserved_6a                                             :  5,
+                      da_is_bcast                                             :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      l4_port_type                                            :  1,
+                      l4_port                                                 : 16,
+                      l4_protocol                                             :  8;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t l4_checksum_enable                                      :  1,
+                      l3_checksum_enable                                      :  1,
+                      reserved_11a                                            : 12,
+                      tqm_no_drop                                             :  1,
+                      tx_notify_frame                                         :  3,
+                      msdu_color                                              :  2,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      type_or_length                                          :  1,
+                      encap_length_override                                   :  1,
+                      encap_length_decrease                                   :  1,
+                      encap_length_change                                     :  6,
+                      ip_da_or_sa                                             :  1;
+             uint32_t reserved_12a                                            :  3,
+                      wmac_hdr_len                                            :  7,
+                      c_vlan_tag_present                                      :  1,
+                      s_vlan_tag_present                                      :  1,
+                      buffer_timestamp_valid                                  :  1,
+                      buffer_timestamp                                        : 19;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            : 20;
+#endif
+};
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                        0x00000000
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                           0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                          0xffffffff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                       0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                          0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                          7
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                         0x000000ff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                   0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                      8
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                      11
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                     0x00000f00
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                        0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                           12
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                  0x00000008
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                    0x00000001
+
+#define TCL_ASSIST_CMD_BANK_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_BANK_ID_LSB                                                  1
+#define TCL_ASSIST_CMD_BANK_ID_MSB                                                  6
+#define TCL_ASSIST_CMD_BANK_ID_MASK                                                 0x0000007e
+
+#define TCL_ASSIST_CMD_VDEV_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_VDEV_ID_LSB                                                  7
+#define TCL_ASSIST_CMD_VDEV_ID_MSB                                                  14
+#define TCL_ASSIST_CMD_VDEV_ID_MASK                                                 0x00007f80
+
+#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_DATA_LENGTH_LSB                                              15
+#define TCL_ASSIST_CMD_DATA_LENGTH_MSB                                              28
+#define TCL_ASSIST_CMD_DATA_LENGTH_MASK                                             0x1fff8000
+
+#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET                                             0x00000008
+#define TCL_ASSIST_CMD_TO_FW_TQM_LSB                                                29
+#define TCL_ASSIST_CMD_TO_FW_TQM_MSB                                                30
+#define TCL_ASSIST_CMD_TO_FW_TQM_MASK                                               0x60000000
+
+#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_RESERVED_2A_LSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MASK                                             0x80000000
+
+#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET                                           0x0000000c
+#define TCL_ASSIST_CMD_RESERVED_3A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_3A_MSB                                              24
+#define TCL_ASSIST_CMD_RESERVED_3A_MASK                                             0x01ffffff
+
+#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET                                       0x0000000c
+#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB                                          25
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB                                          31
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK                                         0xfe000000
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET                              0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB                                 0
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB                                 7
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK                                0x000000ff
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET                                0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB                                   8
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB                                   12
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK                                  0x00001f00
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET                           0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK                             0x00002000
+
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                  0x00000010
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK                                    0x00004000
+
+#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_FLOW_SELECT_LSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MASK                                             0x00008000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OFFSET                                              0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_LSB                                                 16
+#define TCL_ASSIST_CMD_HLOS_TID_MSB                                                 19
+#define TCL_ASSIST_CMD_HLOS_TID_MASK                                                0x000f0000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET                                    0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET                                          0x00000010
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB                                             21
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB                                             28
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK                                            0x1fe00000
+
+#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_RESERVED_4A_LSB                                              29
+#define TCL_ASSIST_CMD_RESERVED_4A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_4A_MASK                                             0xe0000000
+
+#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET                                           0x00000014
+#define TCL_ASSIST_CMD_RESERVED_5A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_5A_MSB                                              15
+#define TCL_ASSIST_CMD_RESERVED_5A_MASK                                             0x0000ffff
+
+#define TCL_ASSIST_CMD_L3_TYPE_OFFSET                                               0x00000014
+#define TCL_ASSIST_CMD_L3_TYPE_LSB                                                  16
+#define TCL_ASSIST_CMD_L3_TYPE_MSB                                                  31
+#define TCL_ASSIST_CMD_L3_TYPE_MASK                                                 0xffff0000
+
+#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB                                              0
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB                                              7
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK                                             0x000000ff
+
+#define TCL_ASSIST_CMD_L4_PORT_OFFSET                                               0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_LSB                                                  8
+#define TCL_ASSIST_CMD_L4_PORT_MSB                                                  23
+#define TCL_ASSIST_CMD_L4_PORT_MASK                                                 0x00ffff00
+
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET                                          0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK                                            0x01000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET                                     0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK                                       0x02000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK                                             0x04000000
+
+#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_RESERVED_6A_LSB                                              27
+#define TCL_ASSIST_CMD_RESERVED_6A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_6A_MASK                                             0xf8000000
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET                                       0x0000001c
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB                                          0
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB                                          31
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK                                         0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET                                      0x00000020
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET                                      0x00000024
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET                                     0x00000028
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB                                        0
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB                                        31
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK                                       0xffffffff
+
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK                                             0x00000001
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB                                      1
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB                                      6
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK                                     0x0000007e
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK                                   0x00000080
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK                                   0x00000100
+
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET                                        0x0000002c
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK                                          0x00000200
+
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK                                     0x00000400
+
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET                          0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK                            0x00000800
+
+#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET                                            0x0000002c
+#define TCL_ASSIST_CMD_MSDU_COLOR_LSB                                               12
+#define TCL_ASSIST_CMD_MSDU_COLOR_MSB                                               13
+#define TCL_ASSIST_CMD_MSDU_COLOR_MASK                                              0x00003000
+
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET                                       0x0000002c
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB                                          14
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB                                          16
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK                                         0x0001c000
+
+#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK                                             0x00020000
+
+#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET                                          0x0000002c
+#define TCL_ASSIST_CMD_RESERVED_11A_LSB                                             18
+#define TCL_ASSIST_CMD_RESERVED_11A_MSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_11A_MASK                                            0x3ffc0000
+
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK                                      0x40000000
+
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK                                      0x80000000
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET                                      0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB                                         0
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB                                         18
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK                                        0x0007ffff
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK                                  0x00080000
+
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK                                      0x00200000
+
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB                                             22
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB                                             28
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK                                            0x1fc00000
+
+#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_RESERVED_12A_LSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_12A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_12A_MASK                                            0xe0000000
+
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET                                        0x00000034
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB                                           0
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB                                           31
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK                                          0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET                                          0x00000038
+#define TCL_ASSIST_CMD_RESERVED_14A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_14A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_14A_MASK                                            0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET                                          0x0000003c
+#define TCL_ASSIST_CMD_RESERVED_15A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_15A_MSB                                             19
+#define TCL_ASSIST_CMD_RESERVED_15A_MASK                                            0x000fffff
+
+#define TCL_ASSIST_CMD_RING_ID_OFFSET                                               0x0000003c
+#define TCL_ASSIST_CMD_RING_ID_LSB                                                  20
+#define TCL_ASSIST_CMD_RING_ID_MSB                                                  27
+#define TCL_ASSIST_CMD_RING_ID_MASK                                                 0x0ff00000
+
+#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET                                         0x0000003c
+#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB                                            28
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB                                            31
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK                                           0xf0000000
+
+#endif
diff --git a/hw/fig/v2/tcl_status_ring.h b/hw/fig/v2/tcl_status_ring.h
new file mode 100644
index 000000000000..5a24217c95d5
--- /dev/null
+++ b/hw/fig/v2/tcl_status_ring.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t gse_ctrl                                                :  4,
+                      ase_fse_sel                                             :  1,
+                      cache_op_res                                            :  2,
+                      index_search_en                                         :  1,
+                      msdu_cnt_n                                              : 24;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t hash_indx_val                                           : 20,
+                      cache_set_num                                           :  4,
+                      reserved_5a                                             :  8;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t msdu_cnt_n                                              : 24,
+                      index_search_en                                         :  1,
+                      cache_op_res                                            :  2,
+                      ase_fse_sel                                             :  1,
+                      gse_ctrl                                                :  4;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             :  8,
+                      cache_set_num                                           :  4,
+                      hash_indx_val                                           : 20;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_STATUS_RING_GSE_CTRL_OFFSET                                             0x00000000
+#define TCL_STATUS_RING_GSE_CTRL_LSB                                                0
+#define TCL_STATUS_RING_GSE_CTRL_MSB                                                3
+#define TCL_STATUS_RING_GSE_CTRL_MASK                                               0x0000000f
+
+#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET                                          0x00000000
+#define TCL_STATUS_RING_ASE_FSE_SEL_LSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MASK                                            0x00000010
+
+#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET                                         0x00000000
+#define TCL_STATUS_RING_CACHE_OP_RES_LSB                                            5
+#define TCL_STATUS_RING_CACHE_OP_RES_MSB                                            6
+#define TCL_STATUS_RING_CACHE_OP_RES_MASK                                           0x00000060
+
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET                                      0x00000000
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK                                        0x00000080
+
+#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET                                           0x00000000
+#define TCL_STATUS_RING_MSDU_CNT_N_LSB                                              8
+#define TCL_STATUS_RING_MSDU_CNT_N_MSB                                              31
+#define TCL_STATUS_RING_MSDU_CNT_N_MASK                                             0xffffff00
+
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET                                      0x00000004
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET                                      0x00000008
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET                                   0x0000000c
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB                                      0
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB                                      31
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK                                     0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET                                  0x00000010
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB                                     0
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB                                     31
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK                                    0xffffffff
+
+#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_HASH_INDX_VAL_LSB                                           0
+#define TCL_STATUS_RING_HASH_INDX_VAL_MSB                                           19
+#define TCL_STATUS_RING_HASH_INDX_VAL_MASK                                          0x000fffff
+
+#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_CACHE_SET_NUM_LSB                                           20
+#define TCL_STATUS_RING_CACHE_SET_NUM_MSB                                           23
+#define TCL_STATUS_RING_CACHE_SET_NUM_MASK                                          0x00f00000
+
+#define TCL_STATUS_RING_RESERVED_5A_OFFSET                                          0x00000014
+#define TCL_STATUS_RING_RESERVED_5A_LSB                                             24
+#define TCL_STATUS_RING_RESERVED_5A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_5A_MASK                                            0xff000000
+
+#define TCL_STATUS_RING_RESERVED_6A_OFFSET                                          0x00000018
+#define TCL_STATUS_RING_RESERVED_6A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_6A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_6A_MASK                                            0xffffffff
+
+#define TCL_STATUS_RING_RESERVED_7A_OFFSET                                          0x0000001c
+#define TCL_STATUS_RING_RESERVED_7A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_7A_MSB                                             19
+#define TCL_STATUS_RING_RESERVED_7A_MASK                                            0x000fffff
+
+#define TCL_STATUS_RING_RING_ID_OFFSET                                              0x0000001c
+#define TCL_STATUS_RING_RING_ID_LSB                                                 20
+#define TCL_STATUS_RING_RING_ID_MSB                                                 27
+#define TCL_STATUS_RING_RING_ID_MASK                                                0x0ff00000
+
+#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET                                        0x0000001c
+#define TCL_STATUS_RING_LOOPING_COUNT_LSB                                           28
+#define TCL_STATUS_RING_LOOPING_COUNT_MSB                                           31
+#define TCL_STATUS_RING_LOOPING_COUNT_MASK                                          0xf0000000
+
+#endif
diff --git a/hw/fig/v2/tlv_hdr.h b/hw/fig/v2/tlv_hdr.h
new file mode 100644
index 000000000000..a2defe7be508
--- /dev/null
+++ b/hw/fig/v2/tlv_hdr.h
@@ -0,0 +1,634 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+
+#define _TLV_USERID_WIDTH_      6
+
+#define _TLV_MRV_EN_LEN_WIDTH_  9
+#define _TLV_MRV_DIS_LEN_WIDTH_ 12
+
+#define _TLV_DATA_WIDTH_        32
+#define _TLV_64_DATA_WIDTH_     64
+#define _TLV_CDATA_WIDTH_       32
+#define _TLV_77_DATA_WIDTH_     77
+#define _TLV_CDATA_77_WIDTH_    64
+
+#define _TLV_TAG_WIDTH_         10
+#define _TLV_CTAG_WIDTH_        6
+
+struct tlv_mlo_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6;
+#else
+           uint32_t             tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_52  :   52;
+           uint64_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint64_t             tlv_cdata_lower_52  :   52,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mlo_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_usr_c_77_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_20  :   20;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+           uint32_t             pad_96to128_bit     :   32;
+#else
+           uint32_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             pad_77to96_bit      :   20,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint32_t             pad_96to128_bit     :   32;
+#endif
+};
+
+struct tlv_usr_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_reserved        :   32;
+#else
+           uint64_t             tlv_reserved        :   32,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6,
+                                pad_32to64_bit      :   32;
+#else
+           uint64_t             pad_32to64_bit      :   32,
+                                tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to95_bit      :   19;
+#else
+           uint32_t             pad_77to95_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+#else
+           uint32_t             pad_77to96_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata           :   _TLV_CDATA_WIDTH_,
+                                pad_44to64_bit      :   20;
+#else
+           uint64_t             tlv_cdata_lower_20  :   20,
+                                pad_44to64_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+#endif
+};
+
+#endif
diff --git a/hw/fig/v2/tlv_tag_def.h b/hw/fig/v2/tlv_tag_def.h
new file mode 100644
index 000000000000..27ccee515a00
--- /dev/null
+++ b/hw/fig/v2/tlv_tag_def.h
@@ -0,0 +1,1948 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum tlv_tag_def {
+  WIFIMACTX_CBF_START_E                                    = 0  ,
+  WIFIPHYRX_DATA_E                                         = 1  ,
+  WIFIPHYRX_CBF_DATA_RESP_E                                = 2  ,
+  WIFIPHYRX_ABORT_REQUEST_E                                = 3  ,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E                      = 4  ,
+  WIFIMACTX_DATA_RESP_E                                    = 5  ,
+  WIFIMACTX_CBF_DATA_E                                     = 6  ,
+  WIFIMACTX_CBF_DONE_E                                     = 7  ,
+  WIFIPHYRX_LMR_DATA_RESP_E                                = 8  ,
+  WIFIRXPCU_TO_UCODE_START_E                               = 9  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E             = 10  ,
+  WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E                      = 11  ,
+  WIFIRXPCU_TO_UCODE_FCS_STATUS_E                          = 12  ,
+  WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E                      = 13  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E           = 14  ,
+  WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E                    = 15  ,
+  WIFIRXPCU_TO_UCODE_END_E                                 = 16  ,
+  WIFIPHYRX_RSSI_LEGACY_20MHZ_E                            = 17  ,
+  WIFIPHYRX_NC_ABORT_REQUEST_E                             = 18  ,
+  WIFIPHYRX_PKT_END_20MHZ_E                                = 19  ,
+  WIFIPHYRX_NC_DATA_E                                      = 20  ,
+  WIFIMACRX_CBF_READ_REQUEST_E                             = 64  ,
+  WIFIMACRX_CBF_DATA_REQUEST_E                             = 65  ,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E                         = 66  ,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E                       = 67  ,
+  WIFIMACRX_NDP_TIMEOUT_E                                  = 68  ,
+  WIFIMACRX_ABORT_ACK_E                                    = 69  ,
+  WIFIMACRX_REQ_IMPLICIT_FB_E                              = 70  ,
+  WIFIMACRX_CHAIN_MASK_E                                   = 71  ,
+  WIFIMACRX_NAP_USER_E                                     = 72  ,
+  WIFIMACRX_ABORT_REQUEST_E                                = 73  ,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E                        = 74  ,
+  WIFIPHYTX_ABORT_ACK_E                                    = 75  ,
+  WIFIPHYTX_ABORT_REQUEST_E                                = 76  ,
+  WIFIPHYTX_PKT_END_E                                      = 77  ,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E                     = 78  ,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E                            = 79  ,
+  WIFIPHYTX_DATA_REQUEST_E                                 = 80  ,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E                           = 81  ,
+  WIFIPHYTX_NAP_ACK_E                                      = 82  ,
+  WIFIPHYTX_NAP_DONE_E                                     = 83  ,
+  WIFIPHYTX_OFF_ACK_E                                      = 84  ,
+  WIFIPHYTX_ON_ACK_E                                       = 85  ,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                                = 86  ,
+  WIFIPHYTX_DEBUG16_E                                      = 87  ,
+  WIFIMACTX_ABORT_REQUEST_E                                = 88  ,
+  WIFIMACTX_ABORT_ACK_E                                    = 89  ,
+  WIFIMACTX_PKT_END_E                                      = 90  ,
+  WIFIMACTX_PRE_PHY_DESC_E                                 = 91  ,
+  WIFIMACTX_BF_PARAMS_COMMON_E                             = 92  ,
+  WIFIMACTX_BF_PARAMS_PER_USER_E                           = 93  ,
+  WIFIMACTX_PREFETCH_CV_E                                  = 94  ,
+  WIFIMACTX_USER_DESC_COMMON_E                             = 95  ,
+  WIFIMACTX_USER_DESC_PER_USER_E                           = 96  ,
+  WIFIEXAMPLE_USER_TLV_16_E                                = 97  ,
+  WIFIEXAMPLE_TLV_16_E                                     = 98  ,
+  WIFIMACTX_PHY_OFF_E                                      = 99  ,
+  WIFIMACTX_PHY_ON_E                                       = 100  ,
+  WIFIMACTX_SYNTH_OFF_E                                    = 101  ,
+  WIFIMACTX_EXPECT_CBF_COMMON_E                            = 102  ,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E                          = 103  ,
+  WIFIMACTX_PHY_DESC_E                                     = 104  ,
+  WIFIMACTX_L_SIG_A_E                                      = 105  ,
+  WIFIMACTX_L_SIG_B_E                                      = 106  ,
+  WIFIMACTX_HT_SIG_E                                       = 107  ,
+  WIFIMACTX_VHT_SIG_A_E                                    = 108  ,
+  WIFIMACTX_VHT_SIG_B_SU20_E                               = 109  ,
+  WIFIMACTX_VHT_SIG_B_SU40_E                               = 110  ,
+  WIFIMACTX_VHT_SIG_B_SU80_E                               = 111  ,
+  WIFIMACTX_VHT_SIG_B_SU160_E                              = 112  ,
+  WIFIMACTX_VHT_SIG_B_MU20_E                               = 113  ,
+  WIFIMACTX_VHT_SIG_B_MU40_E                               = 114  ,
+  WIFIMACTX_VHT_SIG_B_MU80_E                               = 115  ,
+  WIFIMACTX_VHT_SIG_B_MU160_E                              = 116  ,
+  WIFIMACTX_SERVICE_E                                      = 117  ,
+  WIFIMACTX_HE_SIG_A_SU_E                                  = 118  ,
+  WIFIMACTX_HE_SIG_A_MU_DL_E                               = 119  ,
+  WIFIMACTX_HE_SIG_A_MU_UL_E                               = 120  ,
+  WIFIMACTX_HE_SIG_B1_MU_E                                 = 121  ,
+  WIFIMACTX_HE_SIG_B2_MU_E                                 = 122  ,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E                              = 123  ,
+  WIFIMACTX_DELETE_CV_E                                    = 124  ,
+  WIFIMACTX_MU_UPLINK_COMMON_E                             = 125  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E                         = 126  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E                          = 127  ,
+  WIFIMACTX_PHY_NAP_E                                      = 128  ,
+  WIFIMACTX_DEBUG_E                                        = 129  ,
+  WIFIPHYRX_ABORT_ACK_E                                    = 130  ,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E                        = 131  ,
+  WIFIPHYRX_RSSI_LEGACY_E                                  = 132  ,
+  WIFIPHYRX_RSSI_HT_E                                      = 133  ,
+  WIFIPHYRX_USER_INFO_E                                    = 134  ,
+  WIFIPHYRX_PKT_END_E                                      = 135  ,
+  WIFIPHYRX_DEBUG_E                                        = 136  ,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E                            = 137  ,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E                           = 138  ,
+  WIFIPHYRX_L_SIG_A_E                                      = 139  ,
+  WIFIPHYRX_L_SIG_B_E                                      = 140  ,
+  WIFIPHYRX_HT_SIG_E                                       = 141  ,
+  WIFIPHYRX_VHT_SIG_A_E                                    = 142  ,
+  WIFIPHYRX_VHT_SIG_B_SU20_E                               = 143  ,
+  WIFIPHYRX_VHT_SIG_B_SU40_E                               = 144  ,
+  WIFIPHYRX_VHT_SIG_B_SU80_E                               = 145  ,
+  WIFIPHYRX_VHT_SIG_B_SU160_E                              = 146  ,
+  WIFIPHYRX_VHT_SIG_B_MU20_E                               = 147  ,
+  WIFIPHYRX_VHT_SIG_B_MU40_E                               = 148  ,
+  WIFIPHYRX_VHT_SIG_B_MU80_E                               = 149  ,
+  WIFIPHYRX_VHT_SIG_B_MU160_E                              = 150  ,
+  WIFIPHYRX_HE_SIG_A_SU_E                                  = 151  ,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E                               = 152  ,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E                               = 153  ,
+  WIFIPHYRX_HE_SIG_B1_MU_E                                 = 154  ,
+  WIFIPHYRX_HE_SIG_B2_MU_E                                 = 155  ,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E                              = 156  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E                           = 157  ,
+  WIFIPHYRX_COMMON_USER_INFO_E                             = 158  ,
+  WIFIPHYRX_DATA_DONE_E                                    = 159  ,
+  WIFICOEX_TX_REQ_E                                        = 160  ,
+  WIFIDUMMY_E                                              = 161  ,
+  WIFIEXAMPLE_TLV_32_NAME_E                                = 162  ,
+  WIFIMPDU_LIMIT_E                                         = 163  ,
+  WIFINA_LENGTH_END_E                                      = 164  ,
+  WIFIOLE_BUF_STATUS_E                                     = 165  ,
+  WIFIPCU_PPDU_SETUP_DONE_E                                = 166  ,
+  WIFIPCU_PPDU_SETUP_END_E                                 = 167  ,
+  WIFIPCU_PPDU_SETUP_INIT_E                                = 168  ,
+  WIFIPCU_PPDU_SETUP_START_E                               = 169  ,
+  WIFIPDG_FES_SETUP_E                                      = 170  ,
+  WIFIPDG_RESPONSE_E                                       = 171  ,
+  WIFIPDG_TX_REQ_E                                         = 172  ,
+  WIFISCH_WAIT_INSTR_E                                     = 173  ,
+  WIFIMACTX_SWITCH_TO_MAIN_E                               = 174  ,
+  WIFIPHYTX_LINK_STATE_E                                   = 175  ,
+  WIFIAUX_PPDU_END_E                                       = 176  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E                           = 177  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E                    = 178  ,
+  WIFITQM_GEN_MPDUS_E                                      = 179  ,
+  WIFITQM_GEN_MPDUS_STATUS_E                               = 180  ,
+  WIFITQM_REMOVE_MPDU_E                                    = 181  ,
+  WIFITQM_REMOVE_MPDU_STATUS_E                             = 182  ,
+  WIFITQM_REMOVE_MSDU_E                                    = 183  ,
+  WIFITQM_REMOVE_MSDU_STATUS_E                             = 184  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E                           = 185  ,
+  WIFITQM_WRITE_CMD_E                                      = 186  ,
+  WIFIOFDMA_TRIGGER_DETAILS_E                              = 187  ,
+  WIFITX_DATA_E                                            = 188  ,
+  WIFITX_FES_SETUP_E                                       = 189  ,
+  WIFIRX_PACKET_E                                          = 190  ,
+  WIFIEXPECTED_RESPONSE_E                                  = 191  ,
+  WIFITX_MPDU_END_E                                        = 192  ,
+  WIFITX_MPDU_START_E                                      = 193  ,
+  WIFITX_MSDU_END_E                                        = 194  ,
+  WIFITX_MSDU_START_E                                      = 195  ,
+  WIFITX_SW_MODE_SETUP_E                                   = 196  ,
+  WIFITXPCU_BUFFER_STATUS_E                                = 197  ,
+  WIFITXPCU_USER_BUFFER_STATUS_E                           = 198  ,
+  WIFIDATA_TO_TIME_CONFIG_E                                = 199  ,
+  WIFIEXAMPLE_USER_TLV_32_E                                = 200  ,
+  WIFIMPDU_INFO_E                                          = 201  ,
+  WIFIPDG_USER_SETUP_E                                     = 202  ,
+  WIFITX_11AH_SETUP_E                                      = 203  ,
+  WIFITX_PEER_ENTRY_E                                      = 205  ,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E                       = 206  ,
+  WIFIEXAMPLE_USER_TLV_44_E                                = 207  ,
+  WIFITX_FLUSH_E                                           = 208  ,
+  WIFITX_FLUSH_REQ_E                                       = 209  ,
+  WIFITQM_WRITE_CMD_STATUS_E                               = 210  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E                           = 211  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_E                            = 212  ,
+  WIFIEXAMPLE_USER_CTLV_44_E                               = 213  ,
+  WIFITX_FES_STATUS_START_E                                = 214  ,
+  WIFITX_FES_STATUS_USER_PPDU_E                            = 215  ,
+  WIFITX_FES_STATUS_USER_RESPONSE_E                        = 216  ,
+  WIFITX_FES_STATUS_END_E                                  = 217  ,
+  WIFIRX_TRIG_INFO_E                                       = 218  ,
+  WIFIRXPCU_TX_SETUP_CLEAR_E                               = 219  ,
+  WIFIRX_FRAME_BITMAP_REQ_E                                = 220  ,
+  WIFIRX_FRAME_BITMAP_ACK_E                                = 221  ,
+  WIFICOEX_RX_STATUS_E                                     = 222  ,
+  WIFIRX_START_PARAM_E                                     = 223  ,
+  WIFIRX_PPDU_START_E                                      = 224  ,
+  WIFIRX_PPDU_END_E                                        = 225  ,
+  WIFIRX_MPDU_START_E                                      = 226  ,
+  WIFIRX_MPDU_END_E                                        = 227  ,
+  WIFIRX_MSDU_START_E                                      = 228  ,
+  WIFIRX_MSDU_END_E                                        = 229  ,
+  WIFIRX_ATTENTION_E                                       = 230  ,
+  WIFIRECEIVED_RESPONSE_INFO_E                             = 231  ,
+  WIFIRX_PHY_SLEEP_E                                       = 232  ,
+  WIFIRX_HEADER_E                                          = 233  ,
+  WIFIRX_PEER_ENTRY_E                                      = 234  ,
+  WIFIRX_FLUSH_E                                           = 235  ,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E                          = 236  ,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E                           = 237  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E                    = 238  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E                     = 239  ,
+  WIFITX_CBF_INFO_E                                        = 240  ,
+  WIFIPCU_PPDU_SETUP_USER_E                                = 241  ,
+  WIFIRX_MPDU_PCU_START_E                                  = 242  ,
+  WIFIRX_PM_INFO_E                                         = 243  ,
+  WIFIRX_USER_PPDU_END_E                                   = 244  ,
+  WIFIRX_PRE_PPDU_START_E                                  = 245  ,
+  WIFIRX_PREAMBLE_E                                        = 246  ,
+  WIFITX_FES_SETUP_COMPLETE_E                              = 247  ,
+  WIFITX_LAST_MPDU_FETCHED_E                               = 248  ,
+  WIFITXDMA_STOP_REQUEST_E                                 = 249  ,
+  WIFIRXPCU_SETUP_E                                        = 250  ,
+  WIFIRXPCU_USER_SETUP_E                                   = 251  ,
+  WIFITX_FES_STATUS_ACK_OR_BA_E                            = 252  ,
+  WIFITQM_ACKED_MPDU_E                                     = 253  ,
+  WIFICOEX_TX_RESP_E                                       = 254  ,
+  WIFICOEX_TX_STATUS_E                                     = 255  ,
+  WIFIMACTX_COEX_PHY_CTRL_E                                = 256  ,
+  WIFICOEX_STATUS_BROADCAST_E                              = 257  ,
+  WIFIRESPONSE_START_STATUS_E                              = 258  ,
+  WIFIRESPONSE_END_STATUS_E                                = 259  ,
+  WIFICRYPTO_STATUS_E                                      = 260  ,
+  WIFIRECEIVED_TRIGGER_INFO_E                              = 261  ,
+  WIFICOEX_TX_STOP_CTRL_E                                  = 262  ,
+  WIFIRX_PPDU_ACK_REPORT_E                                 = 263  ,
+  WIFIRX_PPDU_NO_ACK_REPORT_E                              = 264  ,
+  WIFISCH_COEX_STATUS_E                                    = 265  ,
+  WIFISCHEDULER_COMMAND_STATUS_E                           = 266  ,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E               = 267  ,
+  WIFITX_FES_STATUS_PROT_E                                 = 268  ,
+  WIFITX_FES_STATUS_START_PPDU_E                           = 269  ,
+  WIFITX_FES_STATUS_START_PROT_E                           = 270  ,
+  WIFITXPCU_PHYTX_DEBUG32_E                                = 271  ,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E                  = 272  ,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E                         = 273  ,
+  WIFIWHO_ANCHOR_OFFSET_E                                  = 274  ,
+  WIFIWHO_ANCHOR_VALUE_E                                   = 275  ,
+  WIFIWHO_CCE_INFO_E                                       = 276  ,
+  WIFIWHO_COMMIT_E                                         = 277  ,
+  WIFIWHO_COMMIT_DONE_E                                    = 278  ,
+  WIFIWHO_FLUSH_E                                          = 279  ,
+  WIFIWHO_L2_LLC_E                                         = 280  ,
+  WIFIWHO_L2_PAYLOAD_E                                     = 281  ,
+  WIFIWHO_L3_CHECKSUM_E                                    = 282  ,
+  WIFIWHO_L3_INFO_E                                        = 283  ,
+  WIFIWHO_L4_CHECKSUM_E                                    = 284  ,
+  WIFIWHO_L4_INFO_E                                        = 285  ,
+  WIFIWHO_MSDU_E                                           = 286  ,
+  WIFIWHO_MSDU_MISC_E                                      = 287  ,
+  WIFIWHO_PACKET_DATA_E                                    = 288  ,
+  WIFIWHO_PACKET_HDR_E                                     = 289  ,
+  WIFIWHO_PPDU_END_E                                       = 290  ,
+  WIFIWHO_PPDU_START_E                                     = 291  ,
+  WIFIWHO_TSO_E                                            = 292  ,
+  WIFIWHO_WMAC_HEADER_PV0_E                                = 293  ,
+  WIFIWHO_WMAC_HEADER_PV1_E                                = 294  ,
+  WIFIWHO_WMAC_IV_E                                        = 295  ,
+  WIFIMPDU_INFO_END_E                                      = 296  ,
+  WIFIMPDU_INFO_BITMAP_E                                   = 297  ,
+  WIFITX_QUEUE_EXTENSION_E                                 = 298  ,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E                  = 299  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E                    = 300  ,
+  WIFITQM_ACKED_MPDU_STATUS_E                              = 301  ,
+  WIFITQM_ADD_MSDU_STATUS_E                                = 302  ,
+  WIFITQM_LIST_GEN_DONE_E                                  = 303  ,
+  WIFIWHO_TERMINATE_E                                      = 304  ,
+  WIFITX_LAST_MPDU_END_E                                   = 305  ,
+  WIFITX_CV_DATA_E                                         = 306  ,
+  WIFIPPDU_TX_END_E                                        = 307  ,
+  WIFIPROT_TX_END_E                                        = 308  ,
+  WIFIMPDU_INFO_GLOBAL_END_E                               = 309  ,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E                           = 310  ,
+  WIFIRX_PPDU_END_USER_STATS_E                             = 311  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E                         = 312  ,
+  WIFITQM_FLUSH_CACHE_E                                    = 321  ,
+  WIFITQM_UNBLOCK_CACHE_E                                  = 322  ,
+  WIFITQM_FLUSH_CACHE_STATUS_E                             = 323  ,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E                           = 324  ,
+  WIFIRX_PPDU_END_STATUS_DONE_E                            = 325  ,
+  WIFIRX_STATUS_BUFFER_DONE_E                              = 326  ,
+  WIFISCHEDULER_MLO_SW_MSG_STATUS_E                        = 327  ,
+  WIFISCHEDULER_TXOP_DURATION_TRIGGER_E                    = 328  ,
+  WIFITX_DATA_SYNC_E                                       = 329  ,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E                         = 330  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_E                             = 331  ,
+  WIFITQM_SYNC_CMD_E                                       = 332  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E                      = 333  ,
+  WIFITQM_SYNC_CMD_STATUS_E                                = 334  ,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E             = 335  ,
+  WIFITCC_TQM_WRAPPER_CMD_E                                = 336  ,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E          = 340  ,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E                           = 341  ,
+  WIFIRX_PPDU_START_USER_INFO_E                            = 342  ,
+  WIFIRX_RING_MASK_E                                       = 343  ,
+  WIFICOEX_MAC_NAP_E                                       = 344  ,
+  WIFIRXPCU_PPDU_END_INFO_E                                = 345  ,
+  WIFIWHO_MESH_CONTROL_E                                   = 346  ,
+  WIFIPDG_SW_MODE_BW_START_E                               = 347  ,
+  WIFIPDG_SW_MODE_BW_END_E                                 = 348  ,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E                           = 349  ,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E                           = 350  ,
+  WIFISCHEDULER_END_E                                      = 351  ,
+  WIFIRX_PPDU_START_DROPPED_E                              = 352  ,
+  WIFIRX_PPDU_END_DROPPED_E                                = 353  ,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E                    = 354  ,
+  WIFIRX_MPDU_START_DROPPED_E                              = 355  ,
+  WIFIRX_MSDU_START_DROPPED_E                              = 356  ,
+  WIFIRX_MSDU_END_DROPPED_E                                = 357  ,
+  WIFIRX_MPDU_END_DROPPED_E                                = 358  ,
+  WIFIRX_ATTENTION_DROPPED_E                               = 359  ,
+  WIFITXPCU_USER_SETUP_E                                   = 360  ,
+  WIFIRXPCU_USER_SETUP_EXT_E                               = 361  ,
+  WIFICMD_PART_0_END_E                                     = 362  ,
+  WIFIMACTX_SYNTH_ON_E                                     = 363  ,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E                         = 364  ,
+  WIFITQM_MPDU_GLOBAL_START_E                              = 365  ,
+  WIFIEXAMPLE_TLV_32_E                                     = 366  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E                            = 367  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E                      = 368  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E                     = 369  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E               = 370  ,
+  WIFITQM_2_SCH_MPDU_AVAILABLE_E                           = 372  ,
+  WIFIPDG_TRIG_RESPONSE_E                                  = 373  ,
+  WIFITRIGGER_RESPONSE_TX_DONE_E                           = 374  ,
+  WIFIABORT_FROM_PHYRX_DETAILS_E                           = 375  ,
+  WIFISCH_TQM_CMD_WRAPPER_E                                = 376  ,
+  WIFIMPDUS_AVAILABLE_E                                    = 377  ,
+  WIFIRECEIVED_RESPONSE_INFO_PART2_E                       = 378  ,
+  WIFIPHYRX_TX_START_TIMING_E                              = 379  ,
+  WIFITXPCU_PREAMBLE_DONE_E                                = 380  ,
+  WIFINDP_PREAMBLE_DONE_E                                  = 381  ,
+  WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E                       = 382  ,
+  WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E                      = 383  ,
+  WIFIMACTX_CLEAR_PREV_TX_INFO_E                           = 384  ,
+  WIFITX_PUNCTURE_SETUP_E                                  = 385  ,
+  WIFIR2R_STATUS_END_E                                     = 386  ,
+  WIFIMACTX_PREFETCH_CV_COMMON_E                           = 387  ,
+  WIFIEND_OF_FLUSH_MARKER_E                                = 388  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PUNC_E                        = 389  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E                    = 390  ,
+  WIFIRECEIVED_RESPONSE_USER_7_0_E                         = 391  ,
+  WIFIRECEIVED_RESPONSE_USER_15_8_E                        = 392  ,
+  WIFIRECEIVED_RESPONSE_USER_23_16_E                       = 393  ,
+  WIFIRECEIVED_RESPONSE_USER_31_24_E                       = 394  ,
+  WIFIRECEIVED_RESPONSE_USER_36_32_E                       = 395  ,
+  WIFITX_LOOPBACK_SETUP_E                                  = 396  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E                = 397  ,
+  WIFISCH_WAIT_INSTR_TX_PATH_E                             = 398  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E                    = 399  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E             = 400  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E               = 401  ,
+  WIFITX_WUR_DATA_E                                        = 402  ,
+  WIFIRX_PPDU_END_START_E                                  = 403  ,
+  WIFIRX_PPDU_END_MIDDLE_E                                 = 404  ,
+  WIFIRX_PPDU_END_LAST_E                                   = 405  ,
+  WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E                   = 406  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E              = 407  ,
+  WIFISRP_INFO_E                                           = 408  ,
+  WIFIOBSS_SR_INFO_E                                       = 409  ,
+  WIFISCHEDULER_SW_MSG_STATUS_E                            = 410  ,
+  WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E                  = 411  ,
+  WIFIRXPCU_SETUP_COMPLETE_E                               = 412  ,
+  WIFIMACTX_MCC_SWITCH_E                                   = 413  ,
+  WIFIMACTX_MCC_SWITCH_BACK_E                              = 414  ,
+  WIFIPHYTX_MCC_SWITCH_ACK_E                               = 415  ,
+  WIFIPHYTX_MCC_SWITCH_BACK_ACK_E                          = 416  ,
+  WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E                         = 417  ,
+  WIFILMR_TX_END_E                                         = 418  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E            = 419  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E              = 420  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E              = 421  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E          = 422  ,
+  WIFISCH_TLV_WRAPPER_E                                    = 423  ,
+  WIFISCHEDULER_STATUS_WRAPPER_E                           = 424  ,
+  WIFIMPDU_INFO_6X_E                                       = 425  ,
+  WIFIMACTX___RESERVED_G_0013                              = 426  ,
+  WIFIMACTX_U_SIG_EHT_SU_MU_E                              = 427  ,
+  WIFIMACTX_U_SIG_EHT_TB_E                                 = 428  ,
+  WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E                          = 429  ,
+  WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E                          = 430  ,
+  WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E                          = 431  ,
+  WIFIPHYRX_U_SIG_EHT_SU_MU_E                              = 432  ,
+  WIFIPHYRX_U_SIG_EHT_TB_E                                 = 433  ,
+  WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E                          = 434  ,
+  WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                      = 435  ,
+  WIFITX_PUNCTURE_6PATTERNS_SETUP_E                        = 436  ,
+  WIFIMACRX_LMR_READ_REQUEST_E                             = 437  ,
+  WIFIMACRX_LMR_DATA_REQUEST_E                             = 438  ,
+  WIFIPHYRX_LMR_TRANSFER_DONE_E                            = 439  ,
+  WIFIPHYRX_LMR_TRANSFER_ABORT_E                           = 440  ,
+  WIFIPHYRX_LMR_READ_REQUEST_ACK_E                         = 441  ,
+  WIFIMACRX_SECURE_LTF_SEQ_PTR_E                           = 442  ,
+  WIFIPHYRX_USER_INFO_MU_UL_E                              = 443  ,
+  WIFIMPDU_QUEUE_OVERVIEW_E                                = 444  ,
+  WIFISCHEDULER_NAV_INFO_E                                 = 445  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E                = 446  ,
+  WIFILMR_PEER_ENTRY_E                                     = 447  ,
+  WIFILMR_MPDU_START_E                                     = 448  ,
+  WIFILMR_DATA_E                                           = 449  ,
+  WIFILMR_MPDU_END_E                                       = 450  ,
+  WIFIRX_FRAME_1K_BITMAP_ACK_E                             = 452  ,
+  WIFITX_FES_STATUS_1K_BA_E                                = 453  ,
+  WIFITQM_ACKED_1K_MPDU_E                                  = 454  ,
+  WIFIMACRX_INBSS_OBSS_IND_E                               = 455  ,
+  WIFIPHYRX_LOCATION_E                                     = 456  ,
+  WIFIMLO_TX_NOTIFICATION_SU_E                             = 457  ,
+  WIFIMLO_TX_NOTIFICATION_MU_E                             = 458  ,
+  WIFIMLO_TX_REQ_SU_E                                      = 459  ,
+  WIFIMLO_TX_REQ_MU_E                                      = 460  ,
+  WIFIMLO_TX_RESP_E                                        = 461  ,
+  WIFIMLO_RX_NOTIFICATION_E                                = 462  ,
+  WIFIMLO_BKOFF_TRUNC_REQ_E                                = 463  ,
+  WIFIMLO_TBTT_NOTIFICATION_E                              = 464  ,
+  WIFIMLO_MESSAGE_E                                        = 465  ,
+  WIFIMLO_TS_SYNC_MSG_E                                    = 466  ,
+  WIFIMLO_FES_SETUP_E                                      = 467  ,
+  WIFIMLO_PDG_FES_SETUP_SU_E                               = 468  ,
+  WIFIMLO_PDG_FES_SETUP_MU_E                               = 469  ,
+  WIFIMPDU_INFO_1K_BITMAP_E                                = 470  ,
+  WIFIMON_BUFFER_ADDR_E                                    = 471  ,
+  WIFITX_FRAG_STATE_E                                      = 472  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E             = 473  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E              = 474  ,
+  WIFIMACTX_EHT_SIG_USR_OFDMA_E                            = 475  ,
+  WIFIMACTX_U_SIG_UHR_SU_MU_E                              = 476  ,
+  WIFIMACTX_U_SIG_UHR_TB_E                                 = 477  ,
+  WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E                     = 478  ,
+  WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E                     = 479  ,
+  WIFITX_MSDU_COMPONENT_DETAILS_TLV_E                      = 480  ,
+  WIFIPHYRX_EHT_SIG_USR_OFDMA_E                            = 481  ,
+  WIFISCHEDULER_IU_TEMPLATE_ID_E                           = 482  ,
+  WIFIPHYRX_PKT_END_PART1_E                                = 483  ,
+  WIFIMACTX_EXPECT_NDP_RECEPTION_E                         = 484  ,
+  WIFIMACTX_SECURE_LTF_SEQ_PTR_E                           = 485  ,
+  WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E                    = 486  ,
+  WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E                         = 487  ,
+  WIFIPHYRX___RESERVED_G_0014                              = 488  ,
+  WIFIPHYTX_LOCATION_E                                     = 489  ,
+  WIFIPHYTX___RESERVED_G_0014                              = 490  ,
+  WIFIMPDU_LENGTH_STRUCTS_START_E                          = 491  ,
+  WIFIMACTX_EHT_SIG_USR_SU_E                               = 492  ,
+  WIFIMACTX_EHT_SIG_USR_MU_MIMO_E                          = 493  ,
+  WIFIPHYRX_EHT_SIG_USR_SU_E                               = 494  ,
+  WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E                          = 495  ,
+  WIFIPHYRX_GENERIC_U_SIG_E                                = 496  ,
+  WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E                       = 497  ,
+  WIFIOVERWRITE_RESP_START_E                               = 498  ,
+  WIFIOVERWRITE_RESP_PREAMBLE_INFO_E                       = 499  ,
+  WIFIOVERWRITE_RESP_FRAME_INFO_E                          = 500  ,
+  WIFIOVERWRITE_RESP_END_E                                 = 501  ,
+  WIFIRXPCU_EARLY_RX_INDICATION_E                          = 502  ,
+  WIFIMON_DROP_E                                           = 503  ,
+  WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E                       = 504  ,
+  WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E                   = 505  ,
+  WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E                     = 506  ,
+  WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E                   = 507  ,
+  WIFIMACTX_PREFETCH_CV_DMA_E                              = 508  ,
+  WIFIMACTX_PREFETCH_CV_PER_USER_E                         = 509  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E          = 510  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E                      = 511  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E                    = 512  ,
+  WIFIRANGING_USER_DETAILS_E                               = 513  ,
+  WIFIPHYTX_CV_CORR_STATUS_E                               = 514  ,
+  WIFIPHYTX_CV_CORR_COMMON_E                               = 515  ,
+  WIFIPHYTX_CV_CORR_USER_E                                 = 516  ,
+  WIFIMACTX_CV_CORR_COMMON_E                               = 517  ,
+  WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E                       = 518  ,
+  WIFIBW_PUNCTURE_EVAL_WRAPPER_E                           = 519  ,
+  WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E                      = 520  ,
+  WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E                      = 521  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E                      = 522  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E                  = 523  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT2_E                        = 524  ,
+  WIFIFW2SW_MON_E                                          = 525  ,
+  WIFIWSI_DIRECT_MESSAGE_E                                 = 526  ,
+  WIFIMACTX_EMLSR_PRE_SWITCH_E                             = 527  ,
+  WIFIMACTX_EMLSR_SWITCH_E                                 = 528  ,
+  WIFIMACTX_EMLSR_SWITCH_BACK_E                            = 529  ,
+  WIFIPHYTX_EMLSR_SWITCH_ACK_E                             = 530  ,
+  WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E                        = 531  ,
+  WIFIEAD_COMMAND_E                                        = 532  ,
+  WIFIEAD_LEGACY_STATUS_CONTROL_E                          = 533  ,
+  WIFIEAD_LEGACY_INTERRUPT_CONTROL_E                       = 534  ,
+  WIFITPI_TX_INITIALIZATION_CONFIG_E                       = 535  ,
+  WIFITPI_ENABLE_RESPONSE_TIMEOUT_E                        = 536  ,
+  WIFITPI_LEGACY_STATUS_CONTROL_E                          = 537  ,
+  WIFITPI_LEGACY_INTERRUPT_CONTROL_E                       = 538  ,
+  WIFITPI_MPDU_START_E                                     = 539  ,
+  WIFITPI_MPDU_CONTINUATION_E                              = 540  ,
+  WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E               = 541  ,
+  WIFITPI_SEND_TLV_TO_PHYTX_E                              = 542  ,
+  WIFITPI_TX_START_TIME_ARRIVED_E                          = 543  ,
+  WIFITPI_STATUS_E                                         = 544  ,
+  WIFITPI_ERROR_STATUS_E                                   = 545  ,
+  WIFITPI_TIMESTAMP_STATUS_E                               = 546  ,
+  WIFIRPI_SEND_TLV_TO_PHYRX_E                              = 547  ,
+  WIFIRPI_LEGACY_STATUS_CONTROL_E                          = 548  ,
+  WIFIRPI_LEGACY_INTERRUPT_CONTROL_E                       = 549  ,
+  WIFIRPI_STATUS_E                                         = 550  ,
+  WIFIRPI_ERROR_STATUS_E                                   = 551  ,
+  WIFIRPI_TIMESTAMP_STATUS_E                               = 552  ,
+  WIFIRPI_RX_FRAME_UPDATE_STATUS_E                         = 553  ,
+  WIFITCC_PUSH_TRANSMIT_COMMAND_E                          = 554  ,
+  WIFITCC_TLV_FETCH_E                                      = 555  ,
+  WIFITCC_LEGACY_STATUS_CONTROL_E                          = 556  ,
+  WIFITCC_LEGACY_INTERRUPT_CONTROL_E                       = 557  ,
+  WIFITCC_STATUS_E                                         = 558  ,
+  WIFITCC_ERROR_STATUS_E                                   = 559  ,
+  WIFITCC_TIMESTAMP_STATUS_E                               = 560  ,
+  WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E                      = 561  ,
+  WIFITCC_SCHEDULER_CMD_E                                  = 562  ,
+  WIFITCC_BURST_CMD_AVAILABLE_E                            = 563  ,
+  WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E                    = 564  ,
+  WIFIEAD_RING_AIR_TIME_REFERENCE_E                        = 565  ,
+  WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E                        = 566  ,
+  WIFIRPI_WRITE_INFO_TO_EXT_MEM_E                          = 567  ,
+  WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E                        = 568  ,
+  WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E                        = 569  ,
+  WIFITPI_SEND_CBF_DATA_TO_PHYTX_E                         = 570  ,
+  WIFITPI_SEND_CTLV_44_TO_PHYTX_E                          = 571  ,
+  WIFITCC_FES_END_MESSAGE_E                                = 572  ,
+  WIFITPI_TX_FRAME_UPDATE_STATUS_E                         = 573  ,
+  WIFITPI_DISABLE_RESPONSE_TIMEOUT_E                       = 574  ,
+  WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E                   = 575  ,
+  WIFIEAD_MSDU_STATUS_START_E                              = 576  ,
+  WIFIEAD_MSDU_STATUS_DETAILS_E                            = 577  ,
+  WIFIMACTX_UHR_SIG_USR_SU_E                               = 578  ,
+  WIFIMACTX_UHR_SIG_USR_MU_MIMO_E                          = 579  ,
+  WIFIMACTX_UHR_SIG_USR_OFDMA_E                            = 580  ,
+  WIFIMACTX_ELR_SIG_UHR_SU_E                               = 581  ,
+  WIFICOEX_BLACKOUT_DETAILS_E                              = 582  ,
+  WIFIPEER_BLACKOUT_DETAILS_E                              = 583  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E             = 584  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_E                           = 585  ,
+  WIFIHDR_CTRL_PROT_MPDU_START_E                           = 586  ,
+  WIFIHDR_CTRL_PROT_DATA_E                                 = 587  ,
+  WIFIHDR_CTRL_PROT_MPDU_END_E                             = 588  ,
+  WIFIHDR_CTRL_PROT_MIC_STATUS_E                           = 589  ,
+  WIFIHDR_CTRL_PROT_PEER_INFO_E                            = 590  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E                      = 591  ,
+  WIFIMACTX_U_SIG_UHR_ELR_SU_E                             = 592  ,
+  WIFIMACTX_U_SIG_UHR_COBF_E                               = 593  ,
+  WIFIMACTX_UHR_SIG_USR_COBF_E                             = 594  ,
+  WIFIMACTX_U_SIG_UHR_COSR_E                               = 595  ,
+  WIFIMACTX_UHR_SIG_USR_COSR_E                             = 596  ,
+  WIFIOVERWRITE_CFP_INFO_E                                 = 597  ,
+  WIFISPARE_REUSE_TAG_0_E                                  = 598  ,
+  WIFISPARE_REUSE_TAG_1_E                                  = 599  ,
+  WIFISPARE_REUSE_TAG_2_E                                  = 600  ,
+  WIFISPARE_REUSE_TAG_3_E                                  = 601  ,
+  WIFISPARE_REUSE_TAG_4_E                                  = 602  ,
+  WIFISPARE_REUSE_TAG_5_E                                  = 603  ,
+  WIFISPARE_REUSE_TAG_6_E                                  = 604  ,
+  WIFISPARE_REUSE_TAG_7_E                                  = 605  ,
+  WIFISPARE_REUSE_TAG_8_E                                  = 606  ,
+  WIFISPARE_REUSE_TAG_9_E                                  = 607  ,
+  WIFISPARE_REUSE_TAG_10_E                                 = 608  ,
+  WIFISPARE_REUSE_TAG_11_E                                 = 609  ,
+  WIFISPARE_REUSE_TAG_12_E                                 = 610  ,
+  WIFISPARE_REUSE_TAG_13_E                                 = 611  ,
+  WIFISPARE_REUSE_TAG_14_E                                 = 612  ,
+  WIFISPARE_REUSE_TAG_15_E                                 = 613  ,
+  WIFISPARE_REUSE_TAG_16_E                                 = 614  ,
+  WIFISPARE_REUSE_TAG_17_E                                 = 615  ,
+  WIFISPARE_REUSE_TAG_18_E                                 = 616  ,
+  WIFISPARE_REUSE_TAG_19_E                                 = 617  ,
+  WIFISPARE_REUSE_TAG_20_E                                 = 618  ,
+  WIFISPARE_REUSE_TAG_21_E                                 = 619  ,
+  WIFISPARE_REUSE_TAG_22_E                                 = 620  ,
+  WIFISPARE_REUSE_TAG_23_E                                 = 621  ,
+  WIFISPARE_REUSE_TAG_24_E                                 = 622  ,
+  WIFISPARE_REUSE_TAG_25_E                                 = 623  ,
+  WIFISPARE_REUSE_TAG_26_E                                 = 624  ,
+  WIFISPARE_REUSE_TAG_27_E                                 = 625  ,
+  WIFISPARE_REUSE_TAG_28_E                                 = 626  ,
+  WIFISPARE_REUSE_TAG_29_E                                 = 627  ,
+  WIFISPARE_REUSE_TAG_30_E                                 = 628  ,
+  WIFISPARE_REUSE_TAG_31_E                                 = 629  ,
+  WIFISPARE_REUSE_TAG_32_E                                 = 630  ,
+  WIFISPARE_REUSE_TAG_33_E                                 = 631  ,
+  WIFISPARE_REUSE_TAG_34_E                                 = 632  ,
+  WIFISPARE_REUSE_TAG_35_E                                 = 633  ,
+  WIFISPARE_REUSE_TAG_36_E                                 = 634  ,
+  WIFISPARE_REUSE_TAG_37_E                                 = 635  ,
+  WIFISPARE_REUSE_TAG_38_E                                 = 636  ,
+  WIFISPARE_REUSE_TAG_39_E                                 = 637  ,
+  WIFISPARE_REUSE_TAG_40_E                                 = 638  ,
+  WIFISPARE_REUSE_TAG_41_E                                 = 639  ,
+  WIFISPARE_REUSE_TAG_42_E                                 = 640  ,
+  WIFISPARE_REUSE_TAG_43_E                                 = 641  ,
+  WIFISPARE_REUSE_TAG_44_E                                 = 642  ,
+  WIFISPARE_REUSE_TAG_45_E                                 = 643  ,
+  WIFISPARE_REUSE_TAG_46_E                                 = 644  ,
+  WIFISPARE_REUSE_TAG_47_E                                 = 645  ,
+  WIFISPARE_REUSE_TAG_48_E                                 = 646  ,
+  WIFISPARE_REUSE_TAG_49_E                                 = 647  ,
+  WIFISPARE_REUSE_TAG_50_E                                 = 648  ,
+  WIFISPARE_REUSE_TAG_51_E                                 = 649  ,
+  WIFISPARE_REUSE_TAG_52_E                                 = 650  ,
+  WIFISPARE_REUSE_TAG_53_E                                 = 651  ,
+  WIFISPARE_REUSE_TAG_54_E                                 = 652  ,
+  WIFISPARE_REUSE_TAG_55_E                                 = 653  ,
+  WIFISPARE_REUSE_TAG_56_E                                 = 654  ,
+  WIFISPARE_REUSE_TAG_57_E                                 = 655  ,
+  WIFISPARE_REUSE_TAG_58_E                                 = 656  ,
+  WIFISPARE_REUSE_TAG_59_E                                 = 657  ,
+  WIFISPARE_REUSE_TAG_60_E                                 = 658  ,
+  WIFISPARE_REUSE_TAG_61_E                                 = 659  ,
+  WIFISPARE_REUSE_TAG_62_E                                 = 660  ,
+  WIFISPARE_REUSE_TAG_63_E                                 = 661  ,
+  WIFISPARE_REUSE_TAG_64_E                                 = 662  ,
+  WIFISPARE_REUSE_TAG_65_E                                 = 663  ,
+  WIFISPARE_REUSE_TAG_66_E                                 = 664  ,
+  WIFISPARE_REUSE_TAG_67_E                                 = 665  ,
+  WIFISPARE_REUSE_TAG_68_E                                 = 666  ,
+  WIFISPARE_REUSE_TAG_69_E                                 = 667  ,
+  WIFISPARE_REUSE_TAG_70_E                                 = 668  ,
+  WIFISPARE_REUSE_TAG_71_E                                 = 669  ,
+  WIFISPARE_REUSE_TAG_72_E                                 = 670  ,
+  WIFISPARE_REUSE_TAG_73_E                                 = 671  ,
+  WIFISPARE_REUSE_TAG_74_E                                 = 672  ,
+  WIFISPARE_REUSE_TAG_75_E                                 = 673  ,
+  WIFISPARE_REUSE_TAG_76_E                                 = 674  ,
+  WIFISPARE_REUSE_TAG_77_E                                 = 675  ,
+  WIFISPARE_REUSE_TAG_78_E                                 = 676  ,
+  WIFISPARE_REUSE_TAG_79_E                                 = 677  ,
+  WIFISPARE_REUSE_TAG_80_E                                 = 678  ,
+  WIFISPARE_REUSE_TAG_81_E                                 = 679  ,
+  WIFISPARE_REUSE_TAG_82_E                                 = 680  ,
+  WIFISPARE_REUSE_TAG_83_E                                 = 681  ,
+  WIFISPARE_REUSE_TAG_84_E                                 = 682  ,
+  WIFISPARE_REUSE_TAG_85_E                                 = 683  ,
+  WIFISPARE_REUSE_TAG_86_E                                 = 684  ,
+  WIFISPARE_REUSE_TAG_87_E                                 = 685  ,
+  WIFISPARE_REUSE_TAG_88_E                                 = 686  ,
+  WIFISPARE_REUSE_TAG_89_E                                 = 687  ,
+  WIFISPARE_REUSE_TAG_90_E                                 = 688  ,
+  WIFISPARE_REUSE_TAG_91_E                                 = 689  ,
+  WIFISPARE_REUSE_TAG_92_E                                 = 690  ,
+  WIFISPARE_REUSE_TAG_93_E                                 = 691  ,
+  WIFISPARE_REUSE_TAG_94_E                                 = 692  ,
+  WIFISPARE_REUSE_TAG_95_E                                 = 693  ,
+  WIFISPARE_REUSE_TAG_96_E                                 = 694  ,
+  WIFISPARE_REUSE_TAG_97_E                                 = 695  ,
+  WIFISPARE_REUSE_TAG_98_E                                 = 696  ,
+  WIFISPARE_REUSE_TAG_99_E                                 = 697  ,
+  WIFISPARE_REUSE_TAG_100_E                                = 698  ,
+  WIFISPARE_REUSE_TAG_101_E                                = 699  ,
+  WIFISPARE_REUSE_TAG_102_E                                = 700  ,
+  WIFISPARE_REUSE_TAG_103_E                                = 701  ,
+  WIFISPARE_REUSE_TAG_104_E                                = 702  ,
+  WIFISPARE_REUSE_TAG_105_E                                = 703  ,
+  WIFISPARE_REUSE_TAG_106_E                                = 704  ,
+  WIFISPARE_REUSE_TAG_107_E                                = 705  ,
+  WIFISPARE_REUSE_TAG_108_E                                = 706  ,
+  WIFISPARE_REUSE_TAG_109_E                                = 707  ,
+  WIFISPARE_REUSE_TAG_110_E                                = 708  ,
+  WIFISPARE_REUSE_TAG_111_E                                = 709  ,
+  WIFISPARE_REUSE_TAG_112_E                                = 710  ,
+  WIFISPARE_REUSE_TAG_113_E                                = 711  ,
+  WIFISPARE_REUSE_TAG_114_E                                = 712  ,
+  WIFISPARE_REUSE_TAG_115_E                                = 713  ,
+  WIFISPARE_REUSE_TAG_116_E                                = 714  ,
+  WIFISPARE_REUSE_TAG_117_E                                = 715  ,
+  WIFISPARE_REUSE_TAG_118_E                                = 716  ,
+  WIFISPARE_REUSE_TAG_119_E                                = 717  ,
+  WIFISPARE_REUSE_TAG_120_E                                = 718  ,
+  WIFISPARE_REUSE_TAG_121_E                                = 719  ,
+  WIFISPARE_REUSE_TAG_122_E                                = 720  ,
+  WIFISPARE_REUSE_TAG_123_E                                = 721  ,
+  WIFISPARE_REUSE_TAG_124_E                                = 722  ,
+  WIFISPARE_REUSE_TAG_125_E                                = 723  ,
+  WIFISPARE_REUSE_TAG_126_E                                = 724  ,
+  WIFISPARE_REUSE_TAG_127_E                                = 725  ,
+  WIFISPARE_REUSE_TAG_128_E                                = 726  ,
+  WIFISPARE_REUSE_TAG_129_E                                = 727  ,
+  WIFISPARE_REUSE_TAG_130_E                                = 728  ,
+  WIFISPARE_REUSE_TAG_131_E                                = 729  ,
+  WIFISPARE_REUSE_TAG_132_E                                = 730  ,
+  WIFISPARE_REUSE_TAG_133_E                                = 731  ,
+  WIFISPARE_REUSE_TAG_134_E                                = 732  ,
+  WIFISPARE_REUSE_TAG_135_E                                = 733  ,
+  WIFISPARE_REUSE_TAG_136_E                                = 734  ,
+  WIFISPARE_REUSE_TAG_137_E                                = 735  ,
+  WIFISPARE_REUSE_TAG_138_E                                = 736  ,
+  WIFISPARE_REUSE_TAG_139_E                                = 737  ,
+  WIFISPARE_REUSE_TAG_140_E                                = 738  ,
+  WIFISPARE_REUSE_TAG_141_E                                = 739  ,
+  WIFISPARE_REUSE_TAG_142_E                                = 740  ,
+  WIFISPARE_REUSE_TAG_143_E                                = 741  ,
+  WIFISPARE_REUSE_TAG_144_E                                = 742  ,
+  WIFISPARE_REUSE_TAG_145_E                                = 743  ,
+  WIFISPARE_REUSE_TAG_146_E                                = 744  ,
+  WIFISPARE_REUSE_TAG_147_E                                = 745  ,
+  WIFISPARE_REUSE_TAG_148_E                                = 746  ,
+  WIFISPARE_REUSE_TAG_149_E                                = 747  ,
+  WIFISPARE_REUSE_TAG_150_E                                = 748  ,
+  WIFISPARE_REUSE_TAG_151_E                                = 749  ,
+  WIFISPARE_REUSE_TAG_152_E                                = 750  ,
+  WIFISPARE_REUSE_TAG_153_E                                = 751  ,
+  WIFISPARE_REUSE_TAG_154_E                                = 752  ,
+  WIFISPARE_REUSE_TAG_155_E                                = 753  ,
+  WIFISPARE_REUSE_TAG_156_E                                = 754  ,
+  WIFISPARE_REUSE_TAG_157_E                                = 755  ,
+  WIFISPARE_REUSE_TAG_158_E                                = 756  ,
+  WIFISPARE_REUSE_TAG_159_E                                = 757  ,
+  WIFISPARE_REUSE_TAG_160_E                                = 758  ,
+  WIFISPARE_REUSE_TAG_161_E                                = 759  ,
+  WIFISPARE_REUSE_TAG_162_E                                = 760  ,
+  WIFISPARE_REUSE_TAG_163_E                                = 761  ,
+  WIFISPARE_REUSE_TAG_164_E                                = 762  ,
+  WIFISPARE_REUSE_TAG_165_E                                = 763  ,
+  WIFISPARE_REUSE_TAG_166_E                                = 764  ,
+  WIFISPARE_REUSE_TAG_167_E                                = 765  ,
+  WIFISPARE_REUSE_TAG_168_E                                = 766  ,
+  WIFISPARE_REUSE_TAG_169_E                                = 767  ,
+  WIFISPARE_REUSE_TAG_170_E                                = 768  ,
+  WIFISPARE_REUSE_TAG_171_E                                = 769  ,
+  WIFISPARE_REUSE_TAG_172_E                                = 770  ,
+  WIFISPARE_REUSE_TAG_173_E                                = 771  ,
+  WIFISPARE_REUSE_TAG_174_E                                = 772  ,
+  WIFISPARE_REUSE_TAG_175_E                                = 773  ,
+  WIFISPARE_REUSE_TAG_176_E                                = 774  ,
+  WIFISPARE_REUSE_TAG_177_E                                = 775  ,
+  WIFISPARE_REUSE_TAG_178_E                                = 776  ,
+  WIFISPARE_REUSE_TAG_179_E                                = 777  ,
+  WIFISPARE_REUSE_TAG_180_E                                = 778  ,
+  WIFISPARE_REUSE_TAG_181_E                                = 779  ,
+  WIFISPARE_REUSE_TAG_182_E                                = 780  ,
+  WIFISPARE_REUSE_TAG_183_E                                = 781  ,
+  WIFISPARE_REUSE_TAG_184_E                                = 782  ,
+  WIFISPARE_REUSE_TAG_185_E                                = 783  ,
+  WIFISPARE_REUSE_TAG_186_E                                = 784  ,
+  WIFISPARE_REUSE_TAG_187_E                                = 785  ,
+  WIFISPARE_REUSE_TAG_188_E                                = 786  ,
+  WIFISPARE_REUSE_TAG_189_E                                = 787  ,
+  WIFISPARE_REUSE_TAG_190_E                                = 788  ,
+  WIFISPARE_REUSE_TAG_191_E                                = 789  ,
+  WIFISPARE_REUSE_TAG_192_E                                = 790  ,
+  WIFISPARE_REUSE_TAG_193_E                                = 791  ,
+  WIFISPARE_REUSE_TAG_194_E                                = 792  ,
+  WIFISPARE_REUSE_TAG_195_E                                = 793  ,
+  WIFISPARE_REUSE_TAG_196_E                                = 794  ,
+  WIFISPARE_REUSE_TAG_197_E                                = 795  ,
+  WIFISPARE_REUSE_TAG_198_E                                = 796  ,
+  WIFISPARE_REUSE_TAG_199_E                                = 797  ,
+  WIFISPARE_REUSE_TAG_200_E                                = 798  ,
+  WIFISPARE_REUSE_TAG_201_E                                = 799  ,
+  WIFISPARE_REUSE_TAG_202_E                                = 800  ,
+  WIFISPARE_REUSE_TAG_203_E                                = 801  ,
+  WIFISPARE_REUSE_TAG_204_E                                = 802  ,
+  WIFISPARE_REUSE_TAG_205_E                                = 803  ,
+  WIFISPARE_REUSE_TAG_206_E                                = 804  ,
+  WIFISPARE_REUSE_TAG_207_E                                = 805  ,
+  WIFISPARE_REUSE_TAG_208_E                                = 806  ,
+  WIFISPARE_REUSE_TAG_209_E                                = 807  ,
+  WIFISPARE_REUSE_TAG_210_E                                = 808  ,
+  WIFISPARE_REUSE_TAG_211_E                                = 809  ,
+  WIFISPARE_REUSE_TAG_212_E                                = 810  ,
+  WIFISPARE_REUSE_TAG_213_E                                = 811  ,
+  WIFISPARE_REUSE_TAG_214_E                                = 812  ,
+  WIFISPARE_REUSE_TAG_215_E                                = 813  ,
+  WIFISPARE_REUSE_TAG_216_E                                = 814  ,
+  WIFISPARE_REUSE_TAG_217_E                                = 815  ,
+  WIFISPARE_REUSE_TAG_218_E                                = 816  ,
+  WIFISPARE_REUSE_TAG_219_E                                = 817  ,
+  WIFISPARE_REUSE_TAG_220_E                                = 818  ,
+  WIFISPARE_REUSE_TAG_221_E                                = 819  ,
+  WIFISPARE_REUSE_TAG_222_E                                = 820  ,
+  WIFISPARE_REUSE_TAG_223_E                                = 821  ,
+  WIFISPARE_REUSE_TAG_224_E                                = 822  ,
+  WIFISPARE_REUSE_TAG_225_E                                = 823  ,
+  WIFISPARE_REUSE_TAG_226_E                                = 824  ,
+  WIFISPARE_REUSE_TAG_227_E                                = 825  ,
+  WIFISPARE_REUSE_TAG_228_E                                = 826  ,
+  WIFISPARE_REUSE_TAG_229_E                                = 827  ,
+  WIFISPARE_REUSE_TAG_230_E                                = 828  ,
+  WIFISPARE_REUSE_TAG_231_E                                = 829  ,
+  WIFISPARE_REUSE_TAG_232_E                                = 830  ,
+  WIFISPARE_REUSE_TAG_233_E                                = 831  ,
+  WIFISPARE_REUSE_TAG_234_E                                = 832  ,
+  WIFISPARE_REUSE_TAG_235_E                                = 833  ,
+  WIFISPARE_REUSE_TAG_236_E                                = 834  ,
+  WIFISPARE_REUSE_TAG_237_E                                = 835  ,
+  WIFISPARE_REUSE_TAG_238_E                                = 836  ,
+  WIFISPARE_REUSE_TAG_239_E                                = 837  ,
+  WIFISPARE_REUSE_TAG_240_E                                = 838  ,
+  WIFISPARE_REUSE_TAG_241_E                                = 839  ,
+  WIFISPARE_REUSE_TAG_242_E                                = 840  ,
+  WIFISPARE_REUSE_TAG_243_E                                = 841  ,
+  WIFISPARE_REUSE_TAG_244_E                                = 842  ,
+  WIFISPARE_REUSE_TAG_245_E                                = 843  ,
+  WIFISPARE_REUSE_TAG_246_E                                = 844  ,
+  WIFISPARE_REUSE_TAG_247_E                                = 845  ,
+  WIFISPARE_REUSE_TAG_248_E                                = 846  ,
+  WIFISPARE_REUSE_TAG_249_E                                = 847  ,
+  WIFISPARE_REUSE_TAG_250_E                                = 848  ,
+  WIFISPARE_REUSE_TAG_251_E                                = 849  ,
+  WIFISPARE_REUSE_TAG_252_E                                = 850  ,
+  WIFISPARE_REUSE_TAG_253_E                                = 851  ,
+  WIFISPARE_REUSE_TAG_254_E                                = 852  ,
+  WIFISPARE_REUSE_TAG_255_E                                = 853  ,
+  WIFISPARE_REUSE_TAG_256_E                                = 854  ,
+  WIFISPARE_REUSE_TAG_257_E                                = 855  ,
+  WIFISPARE_REUSE_TAG_258_E                                = 856  ,
+  WIFISPARE_REUSE_TAG_259_E                                = 857  ,
+  WIFISPARE_REUSE_TAG_260_E                                = 858  ,
+  WIFISPARE_REUSE_TAG_261_E                                = 859  ,
+  WIFISPARE_REUSE_TAG_262_E                                = 860  ,
+  WIFISPARE_REUSE_TAG_263_E                                = 861  ,
+  WIFISPARE_REUSE_TAG_264_E                                = 862  ,
+  WIFISPARE_REUSE_TAG_265_E                                = 863  ,
+  WIFISPARE_REUSE_TAG_266_E                                = 864  ,
+  WIFISPARE_REUSE_TAG_267_E                                = 865  ,
+  WIFISPARE_REUSE_TAG_268_E                                = 866  ,
+  WIFISPARE_REUSE_TAG_269_E                                = 867  ,
+  WIFISPARE_REUSE_TAG_270_E                                = 868  ,
+  WIFISPARE_REUSE_TAG_271_E                                = 869  ,
+  WIFISPARE_REUSE_TAG_272_E                                = 870  ,
+  WIFISPARE_REUSE_TAG_273_E                                = 871  ,
+  WIFISPARE_REUSE_TAG_274_E                                = 872  ,
+  WIFISPARE_REUSE_TAG_275_E                                = 873  ,
+  WIFISPARE_REUSE_TAG_276_E                                = 874  ,
+  WIFISPARE_REUSE_TAG_277_E                                = 875  ,
+  WIFISPARE_REUSE_TAG_278_E                                = 876  ,
+  WIFISPARE_REUSE_TAG_279_E                                = 877  ,
+  WIFISPARE_REUSE_TAG_280_E                                = 878  ,
+  WIFISPARE_REUSE_TAG_281_E                                = 879  ,
+  WIFISPARE_REUSE_TAG_282_E                                = 880  ,
+  WIFISPARE_REUSE_TAG_283_E                                = 881  ,
+  WIFISPARE_REUSE_TAG_284_E                                = 882  ,
+  WIFISPARE_REUSE_TAG_285_E                                = 883  ,
+  WIFISPARE_REUSE_TAG_286_E                                = 884  ,
+  WIFISPARE_REUSE_TAG_287_E                                = 885  ,
+  WIFISPARE_REUSE_TAG_288_E                                = 886  ,
+  WIFISPARE_REUSE_TAG_289_E                                = 887  ,
+  WIFISPARE_REUSE_TAG_290_E                                = 888  ,
+  WIFISPARE_REUSE_TAG_291_E                                = 889  ,
+  WIFISPARE_REUSE_TAG_292_E                                = 890  ,
+  WIFISPARE_REUSE_TAG_293_E                                = 891  ,
+  WIFISPARE_REUSE_TAG_294_E                                = 892  ,
+  WIFISPARE_REUSE_TAG_295_E                                = 893  ,
+  WIFISPARE_REUSE_TAG_296_E                                = 894  ,
+  WIFISPARE_REUSE_TAG_297_E                                = 895  ,
+  WIFISPARE_REUSE_TAG_298_E                                = 896  ,
+  WIFISPARE_REUSE_TAG_299_E                                = 897  ,
+  WIFISPARE_REUSE_TAG_300_E                                = 898  ,
+  WIFISPARE_REUSE_TAG_301_E                                = 899  ,
+  WIFISPARE_REUSE_TAG_302_E                                = 900  ,
+  WIFISPARE_REUSE_TAG_303_E                                = 901  ,
+  WIFISPARE_REUSE_TAG_304_E                                = 902  ,
+  WIFISPARE_REUSE_TAG_305_E                                = 903  ,
+  WIFISPARE_REUSE_TAG_306_E                                = 904  ,
+  WIFISPARE_REUSE_TAG_307_E                                = 905  ,
+  WIFISPARE_REUSE_TAG_308_E                                = 906  ,
+  WIFISPARE_REUSE_TAG_309_E                                = 907  ,
+  WIFISPARE_REUSE_TAG_310_E                                = 908  ,
+  WIFISPARE_REUSE_TAG_311_E                                = 909  ,
+  WIFISPARE_REUSE_TAG_312_E                                = 910  ,
+  WIFISPARE_REUSE_TAG_313_E                                = 911  ,
+  WIFISPARE_REUSE_TAG_314_E                                = 912  ,
+  WIFISPARE_REUSE_TAG_315_E                                = 913  ,
+  WIFISPARE_REUSE_TAG_316_E                                = 914  ,
+  WIFISPARE_REUSE_TAG_317_E                                = 915  ,
+  WIFISPARE_REUSE_TAG_318_E                                = 916  ,
+  WIFISPARE_REUSE_TAG_319_E                                = 917  ,
+  WIFISPARE_REUSE_TAG_320_E                                = 918  ,
+  WIFISPARE_REUSE_TAG_321_E                                = 919  ,
+  WIFISPARE_REUSE_TAG_322_E                                = 920  ,
+  WIFISPARE_REUSE_TAG_323_E                                = 921  ,
+  WIFISPARE_REUSE_TAG_324_E                                = 922  ,
+  WIFISPARE_REUSE_TAG_325_E                                = 923  ,
+  WIFISPARE_REUSE_TAG_326_E                                = 924  ,
+  WIFISPARE_REUSE_TAG_327_E                                = 925  ,
+  WIFISPARE_REUSE_TAG_328_E                                = 926  ,
+  WIFISPARE_REUSE_TAG_329_E                                = 927  ,
+  WIFISPARE_REUSE_TAG_330_E                                = 928  ,
+  WIFISPARE_REUSE_TAG_331_E                                = 929  ,
+  WIFISPARE_REUSE_TAG_332_E                                = 930  ,
+  WIFISPARE_REUSE_TAG_333_E                                = 931  ,
+  WIFISPARE_REUSE_TAG_334_E                                = 932  ,
+  WIFISPARE_REUSE_TAG_335_E                                = 933  ,
+  WIFISPARE_REUSE_TAG_336_E                                = 934  ,
+  WIFISPARE_REUSE_TAG_337_E                                = 935  ,
+  WIFISPARE_REUSE_TAG_338_E                                = 936  ,
+  WIFISPARE_REUSE_TAG_339_E                                = 937  ,
+  WIFISPARE_REUSE_TAG_340_E                                = 938  ,
+  WIFISPARE_REUSE_TAG_341_E                                = 939  ,
+  WIFISPARE_REUSE_TAG_342_E                                = 940  ,
+  WIFISPARE_REUSE_TAG_343_E                                = 941  ,
+  WIFISPARE_REUSE_TAG_344_E                                = 942  ,
+  WIFISPARE_REUSE_TAG_345_E                                = 943  ,
+  WIFISPARE_REUSE_TAG_346_E                                = 944  ,
+  WIFISPARE_REUSE_TAG_347_E                                = 945  ,
+  WIFISPARE_REUSE_TAG_348_E                                = 946  ,
+  WIFISPARE_REUSE_TAG_349_E                                = 947  ,
+  WIFISPARE_REUSE_TAG_350_E                                = 948  ,
+  WIFISPARE_REUSE_TAG_351_E                                = 949  ,
+  WIFISPARE_REUSE_TAG_352_E                                = 950  ,
+  WIFISPARE_REUSE_TAG_353_E                                = 951  ,
+  WIFISPARE_REUSE_TAG_354_E                                = 952  ,
+  WIFISPARE_REUSE_TAG_355_E                                = 953  ,
+  WIFISPARE_REUSE_TAG_356_E                                = 954  ,
+  WIFISPARE_REUSE_TAG_357_E                                = 955  ,
+  WIFISPARE_REUSE_TAG_358_E                                = 956  ,
+  WIFISPARE_REUSE_TAG_359_E                                = 957  ,
+  WIFISPARE_REUSE_TAG_360_E                                = 958  ,
+  WIFISPARE_REUSE_TAG_361_E                                = 959  ,
+  WIFISPARE_REUSE_TAG_362_E                                = 960  ,
+  WIFISPARE_REUSE_TAG_363_E                                = 961  ,
+  WIFISPARE_REUSE_TAG_364_E                                = 962  ,
+  WIFISPARE_REUSE_TAG_365_E                                = 963  ,
+  WIFISPARE_REUSE_TAG_366_E                                = 964  ,
+  WIFISPARE_REUSE_TAG_367_E                                = 965  ,
+  WIFISPARE_REUSE_TAG_368_E                                = 966  ,
+  WIFISPARE_REUSE_TAG_369_E                                = 967  ,
+  WIFISPARE_REUSE_TAG_370_E                                = 968  ,
+  WIFISPARE_REUSE_TAG_371_E                                = 969  ,
+  WIFISPARE_REUSE_TAG_372_E                                = 970  ,
+  WIFISPARE_REUSE_TAG_373_E                                = 971  ,
+  WIFISPARE_REUSE_TAG_374_E                                = 972  ,
+  WIFISPARE_REUSE_TAG_375_E                                = 973  ,
+  WIFISPARE_REUSE_TAG_376_E                                = 974  ,
+  WIFISPARE_REUSE_TAG_377_E                                = 975  ,
+  WIFISPARE_REUSE_TAG_378_E                                = 976  ,
+  WIFISPARE_REUSE_TAG_379_E                                = 977  ,
+  WIFISPARE_REUSE_TAG_380_E                                = 978  ,
+  WIFISPARE_REUSE_TAG_381_E                                = 979  ,
+  WIFISPARE_REUSE_TAG_382_E                                = 980  ,
+  WIFISPARE_REUSE_TAG_383_E                                = 981  ,
+  WIFISPARE_REUSE_TAG_384_E                                = 982  ,
+  WIFISPARE_REUSE_TAG_385_E                                = 983  ,
+  WIFISPARE_REUSE_TAG_386_E                                = 984  ,
+  WIFISPARE_REUSE_TAG_387_E                                = 985  ,
+  WIFISPARE_REUSE_TAG_388_E                                = 986  ,
+  WIFISPARE_REUSE_TAG_389_E                                = 987  ,
+  WIFISPARE_REUSE_TAG_390_E                                = 988  ,
+  WIFISPARE_REUSE_TAG_391_E                                = 989  ,
+  WIFISPARE_REUSE_TAG_392_E                                = 990  ,
+  WIFISPARE_REUSE_TAG_393_E                                = 991  ,
+  WIFISPARE_REUSE_TAG_394_E                                = 992  ,
+  WIFISPARE_REUSE_TAG_395_E                                = 993  ,
+  WIFISPARE_REUSE_TAG_396_E                                = 994  ,
+  WIFISPARE_REUSE_TAG_397_E                                = 995  ,
+  WIFISPARE_REUSE_TAG_398_E                                = 996  ,
+  WIFISPARE_REUSE_TAG_399_E                                = 997  ,
+  WIFISPARE_REUSE_TAG_400_E                                = 998  ,
+  WIFISPARE_REUSE_TAG_401_E                                = 999  ,
+  WIFISPARE_REUSE_TAG_402_E                                = 1000  ,
+  WIFISPARE_REUSE_TAG_403_E                                = 1001  ,
+  WIFISPARE_REUSE_TAG_404_E                                = 1002  ,
+  WIFISPARE_REUSE_TAG_405_E                                = 1003  ,
+  WIFISPARE_REUSE_TAG_406_E                                = 1004  ,
+  WIFISPARE_REUSE_TAG_407_E                                = 1005  ,
+  WIFISPARE_REUSE_TAG_408_E                                = 1006  ,
+  WIFISPARE_REUSE_TAG_409_E                                = 1007  ,
+  WIFISPARE_REUSE_TAG_410_E                                = 1008  ,
+  WIFISPARE_REUSE_TAG_411_E                                = 1009  ,
+  WIFISPARE_REUSE_TAG_412_E                                = 1010  ,
+  WIFISPARE_REUSE_TAG_413_E                                = 1011  ,
+  WIFISPARE_REUSE_TAG_414_E                                = 1012  ,
+  WIFISPARE_REUSE_TAG_415_E                                = 1013  ,
+  WIFISPARE_REUSE_TAG_416_E                                = 1014  ,
+  WIFISPARE_REUSE_TAG_417_E                                = 1015  ,
+  WIFISPARE_REUSE_TAG_418_E                                = 1016  ,
+  WIFISPARE_REUSE_TAG_419_E                                = 1017  ,
+  WIFISPARE_REUSE_TAG_420_E                                = 1018  ,
+  WIFISPARE_REUSE_TAG_421_E                                = 1019  ,
+  WIFISPARE_REUSE_TAG_422_E                                = 1020  ,
+  WIFISPARE_REUSE_TAG_423_E                                = 1021
+} tlv_tag_def__e;
+
+typedef enum {
+  WIFI_EXT_PHYRX_DATA_E                                    = 1  ,
+  WIFI_EXT_PHYRX_ABORT_REQUEST_E                           = 3  ,
+  WIFI_EXT_MACTX_DATA_RESP_E                               = 5  ,
+  WIFI_EXT_MACTX_CBF_DONE_E                                = 7  ,
+  WIFI_EXT_RXPCU_TO_UCODE_START_E                          = 9  ,
+  WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E                 = 11  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E                 = 13  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E               = 15  ,
+  WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E                       = 17  ,
+  WIFI_EXT_PHYRX_PKT_END_20MHZ_E                           = 19  ,
+  WIFI_EXT_MACRX_CBF_DATA_REQUEST_E                        = 65  ,
+  WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E                  = 67  ,
+  WIFI_EXT_MACRX_ABORT_ACK_E                               = 69  ,
+  WIFI_EXT_MACRX_CHAIN_MASK_E                              = 71  ,
+  WIFI_EXT_MACRX_ABORT_REQUEST_E                           = 73  ,
+  WIFI_EXT_PHYTX_ABORT_ACK_E                               = 75  ,
+  WIFI_EXT_PHYTX_PKT_END_E                                 = 77  ,
+  WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E                       = 79  ,
+  WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E                      = 81  ,
+  WIFI_EXT_PHYTX_NAP_DONE_E                                = 83  ,
+  WIFI_EXT_PHYTX_ON_ACK_E                                  = 85  ,
+  WIFI_EXT_PHYTX_DEBUG16_E                                 = 87  ,
+  WIFI_EXT_MACTX_ABORT_ACK_E                               = 89  ,
+  WIFI_EXT_MACTX_PRE_PHY_DESC_E                            = 91  ,
+  WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E                      = 93  ,
+  WIFI_EXT_MACTX_USER_DESC_COMMON_E                        = 95  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_16_E                           = 97  ,
+  WIFI_EXT_MACTX_PHY_OFF_E                                 = 99  ,
+  WIFI_EXT_MACTX_SYNTH_OFF_E                               = 101  ,
+  WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E                     = 103  ,
+  WIFI_EXT_MACTX_L_SIG_A_E                                 = 105  ,
+  WIFI_EXT_MACTX_HT_SIG_E                                  = 107  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU20_E                          = 109  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU80_E                          = 111  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU20_E                          = 113  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU80_E                          = 115  ,
+  WIFI_EXT_MACTX_SERVICE_E                                 = 117  ,
+  WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E                          = 119  ,
+  WIFI_EXT_MACTX_HE_SIG_B1_MU_E                            = 121  ,
+  WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E                         = 123  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_E                        = 125  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E                     = 127  ,
+  WIFI_EXT_MACTX_DEBUG_E                                   = 129  ,
+  WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E                   = 131  ,
+  WIFI_EXT_PHYRX_RSSI_HT_E                                 = 133  ,
+  WIFI_EXT_PHYRX_PKT_END_E                                 = 135  ,
+  WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E                       = 137  ,
+  WIFI_EXT_PHYRX_L_SIG_A_E                                 = 139  ,
+  WIFI_EXT_PHYRX_HT_SIG_E                                  = 141  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E                          = 143  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E                          = 145  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E                          = 147  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E                          = 149  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_SU_E                             = 151  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E                          = 153  ,
+  WIFI_EXT_PHYRX_HE_SIG_B2_MU_E                            = 155  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E                      = 157  ,
+  WIFI_EXT_PHYRX_DATA_DONE_E                               = 159  ,
+  WIFI_EXT_DUMMY_E                                         = 161  ,
+  WIFI_EXT_MPDU_LIMIT_E                                    = 163  ,
+  WIFI_EXT_OLE_BUF_STATUS_E                                = 165  ,
+  WIFI_EXT_PCU_PPDU_SETUP_END_E                            = 167  ,
+  WIFI_EXT_PCU_PPDU_SETUP_START_E                          = 169  ,
+  WIFI_EXT_PDG_RESPONSE_E                                  = 171  ,
+  WIFI_EXT_SCH_WAIT_INSTR_E                                = 173  ,
+  WIFI_EXT_PHYTX_LINK_STATE_E                              = 175  ,
+  WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E                      = 177  ,
+  WIFI_EXT_TQM_GEN_MPDUS_E                                 = 179  ,
+  WIFI_EXT_TQM_REMOVE_MPDU_E                               = 181  ,
+  WIFI_EXT_TQM_REMOVE_MSDU_E                               = 183  ,
+  WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E                      = 185  ,
+  WIFI_EXT_OFDMA_TRIGGER_DETAILS_E                         = 187  ,
+  WIFI_EXT_TX_FES_SETUP_E                                  = 189  ,
+  WIFI_EXT_EXPECTED_RESPONSE_E                             = 191  ,
+  WIFI_EXT_TX_MPDU_START_E                                 = 193  ,
+  WIFI_EXT_TX_MSDU_START_E                                 = 195  ,
+  WIFI_EXT_TXPCU_BUFFER_STATUS_E                           = 197  ,
+  WIFI_EXT_DATA_TO_TIME_CONFIG_E                           = 199  ,
+  WIFI_EXT_MPDU_INFO_E                                     = 201  ,
+  WIFI_EXT_TX_11AH_SETUP_E                                 = 203  ,
+  WIFI_EXT_TX_PEER_ENTRY_E                                 = 205  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_44_E                           = 207  ,
+  WIFI_EXT_TX_FLUSH_REQ_E                                  = 209  ,
+  WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E                      = 211  ,
+  WIFI_EXT_EXAMPLE_USER_CTLV_44_E                          = 213  ,
+  WIFI_EXT_TX_FES_STATUS_USER_PPDU_E                       = 215  ,
+  WIFI_EXT_TX_FES_STATUS_END_E                             = 217  ,
+  WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E                          = 219  ,
+  WIFI_EXT_RX_FRAME_BITMAP_ACK_E                           = 221  ,
+  WIFI_EXT_RX_START_PARAM_E                                = 223  ,
+  WIFI_EXT_RX_PPDU_END_E                                   = 225  ,
+  WIFI_EXT_RX_MPDU_END_E                                   = 227  ,
+  WIFI_EXT_RX_MSDU_END_E                                   = 229  ,
+  WIFI_EXT_RECEIVED_RESPONSE_INFO_E                        = 231  ,
+  WIFI_EXT_RX_HEADER_E                                     = 233  ,
+  WIFI_EXT_RX_FLUSH_E                                      = 235  ,
+  WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E                      = 237  ,
+  WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E                = 239  ,
+  WIFI_EXT_PCU_PPDU_SETUP_USER_E                           = 241  ,
+  WIFI_EXT_RX_PM_INFO_E                                    = 243  ,
+  WIFI_EXT_RX_PRE_PPDU_START_E                             = 245  ,
+  WIFI_EXT_TX_FES_SETUP_COMPLETE_E                         = 247  ,
+  WIFI_EXT_TXDMA_STOP_REQUEST_E                            = 249  ,
+  WIFI_EXT_RXPCU_USER_SETUP_E                              = 251  ,
+  WIFI_EXT_TQM_ACKED_MPDU_E                                = 253  ,
+  WIFI_EXT_COEX_TX_STATUS_E                                = 255  ,
+  WIFI_EXT_COEX_STATUS_BROADCAST_E                         = 257  ,
+  WIFI_EXT_RESPONSE_END_STATUS_E                           = 259  ,
+  WIFI_EXT_RECEIVED_TRIGGER_INFO_E                         = 261  ,
+  WIFI_EXT_RX_PPDU_ACK_REPORT_E                            = 263  ,
+  WIFI_EXT_SCH_COEX_STATUS_E                               = 265  ,
+  WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E          = 267  ,
+  WIFI_EXT_TX_FES_STATUS_START_PPDU_E                      = 269  ,
+  WIFI_EXT_TXPCU_PHYTX_DEBUG32_E                           = 271  ,
+  WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E                    = 273  ,
+  WIFI_EXT_WHO_ANCHOR_VALUE_E                              = 275  ,
+  WIFI_EXT_WHO_COMMIT_E                                    = 277  ,
+  WIFI_EXT_WHO_FLUSH_E                                     = 279  ,
+  WIFI_EXT_WHO_L2_PAYLOAD_E                                = 281  ,
+  WIFI_EXT_WHO_L3_INFO_E                                   = 283  ,
+  WIFI_EXT_WHO_L4_INFO_E                                   = 285  ,
+  WIFI_EXT_WHO_MSDU_MISC_E                                 = 287  ,
+  WIFI_EXT_WHO_PACKET_HDR_E                                = 289  ,
+  WIFI_EXT_WHO_PPDU_START_E                                = 291  ,
+  WIFI_EXT_WHO_WMAC_HEADER_PV0_E                           = 293  ,
+  WIFI_EXT_WHO_WMAC_IV_E                                   = 295  ,
+  WIFI_EXT_MPDU_INFO_BITMAP_E                              = 297  ,
+  WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E             = 299  ,
+  WIFI_EXT_TQM_ACKED_MPDU_STATUS_E                         = 301  ,
+  WIFI_EXT_TQM_LIST_GEN_DONE_E                             = 303  ,
+  WIFI_EXT_TX_LAST_MPDU_END_E                              = 305  ,
+  WIFI_EXT_PPDU_TX_END_E                                   = 307  ,
+  WIFI_EXT_MPDU_INFO_GLOBAL_END_E                          = 309  ,
+  WIFI_EXT_RX_PPDU_END_USER_STATS_E                        = 311  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_E                               = 321  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E                        = 323  ,
+  WIFI_EXT_RX_PPDU_END_STATUS_DONE_E                       = 325  ,
+  WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E                   = 327  ,
+  WIFI_EXT_TX_DATA_SYNC_E                                  = 329  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E                        = 331  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E                 = 333  ,
+  WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E        = 335  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E                      = 341  ,
+  WIFI_EXT_RX_RING_MASK_E                                  = 343  ,
+  WIFI_EXT_RXPCU_PPDU_END_INFO_E                           = 345  ,
+  WIFI_EXT_PDG_SW_MODE_BW_START_E                          = 347  ,
+  WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E                      = 349  ,
+  WIFI_EXT_SCHEDULER_END_E                                 = 351  ,
+  WIFI_EXT_RX_PPDU_END_DROPPED_E                           = 353  ,
+  WIFI_EXT_RX_MPDU_START_DROPPED_E                         = 355  ,
+  WIFI_EXT_RX_MSDU_END_DROPPED_E                           = 357  ,
+  WIFI_EXT_RX_ATTENTION_DROPPED_E                          = 359  ,
+  WIFI_EXT_RXPCU_USER_SETUP_EXT_E                          = 361  ,
+  WIFI_EXT_MACTX_SYNTH_ON_E                                = 363  ,
+  WIFI_EXT_TQM_MPDU_GLOBAL_START_E                         = 365  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E                       = 367  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E                = 369  ,
+  WIFI_EXT_PDG_TRIG_RESPONSE_E                             = 373  ,
+  WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E                      = 375  ,
+  WIFI_EXT_MPDUS_AVAILABLE_E                               = 377  ,
+  WIFI_EXT_PHYRX_TX_START_TIMING_E                         = 379  ,
+  WIFI_EXT_NDP_PREAMBLE_DONE_E                             = 381  ,
+  WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E                 = 383  ,
+  WIFI_EXT_TX_PUNCTURE_SETUP_E                             = 385  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E                      = 387  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E                   = 389  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E                    = 391  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E                  = 393  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E                  = 395  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E           = 397  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E               = 399  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E          = 401  ,
+  WIFI_EXT_RX_PPDU_END_START_E                             = 403  ,
+  WIFI_EXT_RX_PPDU_END_LAST_E                              = 405  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E         = 407  ,
+  WIFI_EXT_OBSS_SR_INFO_E                                  = 409  ,
+  WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E             = 411  ,
+  WIFI_EXT_MACTX_MCC_SWITCH_E                              = 413  ,
+  WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E                          = 415  ,
+  WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E                    = 417  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E       = 419  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E         = 421  ,
+  WIFI_EXT_SCH_TLV_WRAPPER_E                               = 423  ,
+  WIFI_EXT_MPDU_INFO_6X_E                                  = 425  ,
+  WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E                         = 427  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E                     = 429  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E                     = 431  ,
+  WIFI_EXT_PHYRX_U_SIG_EHT_TB_E                            = 433  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                 = 435  ,
+  WIFI_EXT_MACRX_LMR_READ_REQUEST_E                        = 437  ,
+  WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E                       = 439  ,
+  WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E                    = 441  ,
+  WIFI_EXT_PHYRX_USER_INFO_MU_UL_E                         = 443  ,
+  WIFI_EXT_SCHEDULER_NAV_INFO_E                            = 445  ,
+  WIFI_EXT_LMR_PEER_ENTRY_E                                = 447  ,
+  WIFI_EXT_LMR_DATA_E                                      = 449  ,
+  WIFI_EXT_TX_FES_STATUS_1K_BA_E                           = 453  ,
+  WIFI_EXT_MACRX_INBSS_OBSS_IND_E                          = 455  ,
+  WIFI_EXT_MLO_TX_NOTIFICATION_SU_E                        = 457  ,
+  WIFI_EXT_MLO_TX_REQ_SU_E                                 = 459  ,
+  WIFI_EXT_MLO_TX_RESP_E                                   = 461  ,
+  WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E                           = 463  ,
+  WIFI_EXT_MLO_MESSAGE_E                                   = 465  ,
+  WIFI_EXT_MLO_FES_SETUP_E                                 = 467  ,
+  WIFI_EXT_MLO_PDG_FES_SETUP_MU_E                          = 469  ,
+  WIFI_EXT_MON_BUFFER_ADDR_E                               = 471  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E        = 473  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E                       = 475  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_TB_E                            = 477  ,
+  WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E                = 479  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E                       = 481  ,
+  WIFI_EXT_PHYRX_PKT_END_PART1_E                           = 483  ,
+  WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E                      = 485  ,
+  WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E                    = 487  ,
+  WIFI_EXT_PHYTX_LOCATION_E                                = 489  ,
+  WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E                     = 491  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E                     = 493  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E                     = 495  ,
+  WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E                  = 497  ,
+  WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E                  = 499  ,
+  WIFI_EXT_OVERWRITE_RESP_END_E                            = 501  ,
+  WIFI_EXT_MON_DROP_E                                      = 503  ,
+  WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E              = 505  ,
+  WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E              = 507  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E                    = 509  ,
+  WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E                 = 511  ,
+  WIFI_EXT_RANGING_USER_DETAILS_E                          = 513  ,
+  WIFI_EXT_PHYTX_CV_CORR_COMMON_E                          = 515  ,
+  WIFI_EXT_MACTX_CV_CORR_COMMON_E                          = 517  ,
+  WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E                      = 519  ,
+  WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E                 = 521  ,
+  WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E             = 523  ,
+  WIFI_EXT_FW2SW_MON_E                                     = 525  ,
+  WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E                        = 527  ,
+  WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E                       = 529  ,
+  WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E                   = 531  ,
+  WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E                     = 533  ,
+  WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E                  = 535  ,
+  WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E                     = 537  ,
+  WIFI_EXT_TPI_MPDU_START_E                                = 539  ,
+  WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E          = 541  ,
+  WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E                     = 543  ,
+  WIFI_EXT_TPI_ERROR_STATUS_E                              = 545  ,
+  WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E                         = 547  ,
+  WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E                  = 549  ,
+  WIFI_EXT_RPI_ERROR_STATUS_E                              = 551  ,
+  WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E                    = 553  ,
+  WIFI_EXT_TCC_TLV_FETCH_E                                 = 555  ,
+  WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E                  = 557  ,
+  WIFI_EXT_TCC_ERROR_STATUS_E                              = 559  ,
+  WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E                 = 561  ,
+  WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E                       = 563  ,
+  WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E                   = 565  ,
+  WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E                     = 567  ,
+  WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E                   = 569  ,
+  WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E                     = 571  ,
+  WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E                    = 573  ,
+  WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E              = 575  ,
+  WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E                       = 577  ,
+  WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E                     = 579  ,
+  WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E                          = 581  ,
+  WIFI_EXT_PEER_BLACKOUT_DETAILS_E                         = 583  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E                      = 585  ,
+  WIFI_EXT_HDR_CTRL_PROT_DATA_E                            = 587  ,
+  WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E                      = 589  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E                 = 591  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_COBF_E                          = 593  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_COSR_E                          = 595  ,
+  WIFI_EXT_OVERWRITE_CFP_INFO_E                            = 597  ,
+  WIFI_EXT_SPARE_REUSE_TAG_1_E                             = 599  ,
+  WIFI_EXT_SPARE_REUSE_TAG_3_E                             = 601  ,
+  WIFI_EXT_SPARE_REUSE_TAG_5_E                             = 603  ,
+  WIFI_EXT_SPARE_REUSE_TAG_7_E                             = 605  ,
+  WIFI_EXT_SPARE_REUSE_TAG_9_E                             = 607  ,
+  WIFI_EXT_SPARE_REUSE_TAG_11_E                            = 609  ,
+  WIFI_EXT_SPARE_REUSE_TAG_13_E                            = 611  ,
+  WIFI_EXT_SPARE_REUSE_TAG_15_E                            = 613  ,
+  WIFI_EXT_SPARE_REUSE_TAG_17_E                            = 615  ,
+  WIFI_EXT_SPARE_REUSE_TAG_19_E                            = 617  ,
+  WIFI_EXT_SPARE_REUSE_TAG_21_E                            = 619  ,
+  WIFI_EXT_SPARE_REUSE_TAG_23_E                            = 621  ,
+  WIFI_EXT_SPARE_REUSE_TAG_25_E                            = 623  ,
+  WIFI_EXT_SPARE_REUSE_TAG_27_E                            = 625  ,
+  WIFI_EXT_SPARE_REUSE_TAG_29_E                            = 627  ,
+  WIFI_EXT_SPARE_REUSE_TAG_31_E                            = 629  ,
+  WIFI_EXT_SPARE_REUSE_TAG_33_E                            = 631  ,
+  WIFI_EXT_SPARE_REUSE_TAG_35_E                            = 633  ,
+  WIFI_EXT_SPARE_REUSE_TAG_37_E                            = 635  ,
+  WIFI_EXT_SPARE_REUSE_TAG_39_E                            = 637  ,
+  WIFI_EXT_SPARE_REUSE_TAG_41_E                            = 639  ,
+  WIFI_EXT_SPARE_REUSE_TAG_43_E                            = 641  ,
+  WIFI_EXT_SPARE_REUSE_TAG_45_E                            = 643  ,
+  WIFI_EXT_SPARE_REUSE_TAG_47_E                            = 645  ,
+  WIFI_EXT_SPARE_REUSE_TAG_49_E                            = 647  ,
+  WIFI_EXT_SPARE_REUSE_TAG_51_E                            = 649  ,
+  WIFI_EXT_SPARE_REUSE_TAG_53_E                            = 651  ,
+  WIFI_EXT_SPARE_REUSE_TAG_55_E                            = 653  ,
+  WIFI_EXT_SPARE_REUSE_TAG_57_E                            = 655  ,
+  WIFI_EXT_SPARE_REUSE_TAG_59_E                            = 657  ,
+  WIFI_EXT_SPARE_REUSE_TAG_61_E                            = 659  ,
+  WIFI_EXT_SPARE_REUSE_TAG_63_E                            = 661  ,
+  WIFI_EXT_SPARE_REUSE_TAG_65_E                            = 663  ,
+  WIFI_EXT_SPARE_REUSE_TAG_67_E                            = 665  ,
+  WIFI_EXT_SPARE_REUSE_TAG_69_E                            = 667  ,
+  WIFI_EXT_SPARE_REUSE_TAG_71_E                            = 669  ,
+  WIFI_EXT_SPARE_REUSE_TAG_73_E                            = 671  ,
+  WIFI_EXT_SPARE_REUSE_TAG_75_E                            = 673  ,
+  WIFI_EXT_SPARE_REUSE_TAG_77_E                            = 675  ,
+  WIFI_EXT_SPARE_REUSE_TAG_79_E                            = 677  ,
+  WIFI_EXT_SPARE_REUSE_TAG_81_E                            = 679  ,
+  WIFI_EXT_SPARE_REUSE_TAG_83_E                            = 681  ,
+  WIFI_EXT_SPARE_REUSE_TAG_85_E                            = 683  ,
+  WIFI_EXT_SPARE_REUSE_TAG_87_E                            = 685  ,
+  WIFI_EXT_SPARE_REUSE_TAG_89_E                            = 687  ,
+  WIFI_EXT_SPARE_REUSE_TAG_91_E                            = 689  ,
+  WIFI_EXT_SPARE_REUSE_TAG_93_E                            = 691  ,
+  WIFI_EXT_SPARE_REUSE_TAG_95_E                            = 693  ,
+  WIFI_EXT_SPARE_REUSE_TAG_97_E                            = 695  ,
+  WIFI_EXT_SPARE_REUSE_TAG_99_E                            = 697  ,
+  WIFI_EXT_SPARE_REUSE_TAG_101_E                           = 699  ,
+  WIFI_EXT_SPARE_REUSE_TAG_103_E                           = 701  ,
+  WIFI_EXT_SPARE_REUSE_TAG_105_E                           = 703  ,
+  WIFI_EXT_SPARE_REUSE_TAG_107_E                           = 705  ,
+  WIFI_EXT_SPARE_REUSE_TAG_109_E                           = 707  ,
+  WIFI_EXT_SPARE_REUSE_TAG_111_E                           = 709  ,
+  WIFI_EXT_SPARE_REUSE_TAG_113_E                           = 711  ,
+  WIFI_EXT_SPARE_REUSE_TAG_115_E                           = 713  ,
+  WIFI_EXT_SPARE_REUSE_TAG_117_E                           = 715  ,
+  WIFI_EXT_SPARE_REUSE_TAG_119_E                           = 717  ,
+  WIFI_EXT_SPARE_REUSE_TAG_121_E                           = 719  ,
+  WIFI_EXT_SPARE_REUSE_TAG_123_E                           = 721  ,
+  WIFI_EXT_SPARE_REUSE_TAG_125_E                           = 723  ,
+  WIFI_EXT_SPARE_REUSE_TAG_127_E                           = 725  ,
+  WIFI_EXT_SPARE_REUSE_TAG_129_E                           = 727  ,
+  WIFI_EXT_SPARE_REUSE_TAG_131_E                           = 729  ,
+  WIFI_EXT_SPARE_REUSE_TAG_133_E                           = 731  ,
+  WIFI_EXT_SPARE_REUSE_TAG_135_E                           = 733  ,
+  WIFI_EXT_SPARE_REUSE_TAG_137_E                           = 735  ,
+  WIFI_EXT_SPARE_REUSE_TAG_139_E                           = 737  ,
+  WIFI_EXT_SPARE_REUSE_TAG_141_E                           = 739  ,
+  WIFI_EXT_SPARE_REUSE_TAG_143_E                           = 741  ,
+  WIFI_EXT_SPARE_REUSE_TAG_145_E                           = 743  ,
+  WIFI_EXT_SPARE_REUSE_TAG_147_E                           = 745  ,
+  WIFI_EXT_SPARE_REUSE_TAG_149_E                           = 747  ,
+  WIFI_EXT_SPARE_REUSE_TAG_151_E                           = 749  ,
+  WIFI_EXT_SPARE_REUSE_TAG_153_E                           = 751  ,
+  WIFI_EXT_SPARE_REUSE_TAG_155_E                           = 753  ,
+  WIFI_EXT_SPARE_REUSE_TAG_157_E                           = 755  ,
+  WIFI_EXT_SPARE_REUSE_TAG_159_E                           = 757  ,
+  WIFI_EXT_SPARE_REUSE_TAG_161_E                           = 759  ,
+  WIFI_EXT_SPARE_REUSE_TAG_163_E                           = 761  ,
+  WIFI_EXT_SPARE_REUSE_TAG_165_E                           = 763  ,
+  WIFI_EXT_SPARE_REUSE_TAG_167_E                           = 765  ,
+  WIFI_EXT_SPARE_REUSE_TAG_169_E                           = 767  ,
+  WIFI_EXT_SPARE_REUSE_TAG_171_E                           = 769  ,
+  WIFI_EXT_SPARE_REUSE_TAG_173_E                           = 771  ,
+  WIFI_EXT_SPARE_REUSE_TAG_175_E                           = 773  ,
+  WIFI_EXT_SPARE_REUSE_TAG_177_E                           = 775  ,
+  WIFI_EXT_SPARE_REUSE_TAG_179_E                           = 777  ,
+  WIFI_EXT_SPARE_REUSE_TAG_181_E                           = 779  ,
+  WIFI_EXT_SPARE_REUSE_TAG_183_E                           = 781  ,
+  WIFI_EXT_SPARE_REUSE_TAG_185_E                           = 783  ,
+  WIFI_EXT_SPARE_REUSE_TAG_187_E                           = 785  ,
+  WIFI_EXT_SPARE_REUSE_TAG_189_E                           = 787  ,
+  WIFI_EXT_SPARE_REUSE_TAG_191_E                           = 789  ,
+  WIFI_EXT_SPARE_REUSE_TAG_193_E                           = 791  ,
+  WIFI_EXT_SPARE_REUSE_TAG_195_E                           = 793  ,
+  WIFI_EXT_SPARE_REUSE_TAG_197_E                           = 795  ,
+  WIFI_EXT_SPARE_REUSE_TAG_199_E                           = 797  ,
+  WIFI_EXT_SPARE_REUSE_TAG_201_E                           = 799  ,
+  WIFI_EXT_SPARE_REUSE_TAG_203_E                           = 801  ,
+  WIFI_EXT_SPARE_REUSE_TAG_205_E                           = 803  ,
+  WIFI_EXT_SPARE_REUSE_TAG_207_E                           = 805  ,
+  WIFI_EXT_SPARE_REUSE_TAG_209_E                           = 807  ,
+  WIFI_EXT_SPARE_REUSE_TAG_211_E                           = 809  ,
+  WIFI_EXT_SPARE_REUSE_TAG_213_E                           = 811  ,
+  WIFI_EXT_SPARE_REUSE_TAG_215_E                           = 813  ,
+  WIFI_EXT_SPARE_REUSE_TAG_217_E                           = 815  ,
+  WIFI_EXT_SPARE_REUSE_TAG_219_E                           = 817  ,
+  WIFI_EXT_SPARE_REUSE_TAG_221_E                           = 819  ,
+  WIFI_EXT_SPARE_REUSE_TAG_223_E                           = 821  ,
+  WIFI_EXT_SPARE_REUSE_TAG_225_E                           = 823  ,
+  WIFI_EXT_SPARE_REUSE_TAG_227_E                           = 825  ,
+  WIFI_EXT_SPARE_REUSE_TAG_229_E                           = 827  ,
+  WIFI_EXT_SPARE_REUSE_TAG_231_E                           = 829  ,
+  WIFI_EXT_SPARE_REUSE_TAG_233_E                           = 831  ,
+  WIFI_EXT_SPARE_REUSE_TAG_235_E                           = 833  ,
+  WIFI_EXT_SPARE_REUSE_TAG_237_E                           = 835  ,
+  WIFI_EXT_SPARE_REUSE_TAG_239_E                           = 837  ,
+  WIFI_EXT_SPARE_REUSE_TAG_241_E                           = 839  ,
+  WIFI_EXT_SPARE_REUSE_TAG_243_E                           = 841  ,
+  WIFI_EXT_SPARE_REUSE_TAG_245_E                           = 843  ,
+  WIFI_EXT_SPARE_REUSE_TAG_247_E                           = 845  ,
+  WIFI_EXT_SPARE_REUSE_TAG_249_E                           = 847  ,
+  WIFI_EXT_SPARE_REUSE_TAG_251_E                           = 849  ,
+  WIFI_EXT_SPARE_REUSE_TAG_253_E                           = 851  ,
+  WIFI_EXT_SPARE_REUSE_TAG_255_E                           = 853  ,
+  WIFI_EXT_SPARE_REUSE_TAG_257_E                           = 855  ,
+  WIFI_EXT_SPARE_REUSE_TAG_259_E                           = 857  ,
+  WIFI_EXT_SPARE_REUSE_TAG_261_E                           = 859  ,
+  WIFI_EXT_SPARE_REUSE_TAG_263_E                           = 861  ,
+  WIFI_EXT_SPARE_REUSE_TAG_265_E                           = 863  ,
+  WIFI_EXT_SPARE_REUSE_TAG_267_E                           = 865  ,
+  WIFI_EXT_SPARE_REUSE_TAG_269_E                           = 867  ,
+  WIFI_EXT_SPARE_REUSE_TAG_271_E                           = 869  ,
+  WIFI_EXT_SPARE_REUSE_TAG_273_E                           = 871  ,
+  WIFI_EXT_SPARE_REUSE_TAG_275_E                           = 873  ,
+  WIFI_EXT_SPARE_REUSE_TAG_277_E                           = 875  ,
+  WIFI_EXT_SPARE_REUSE_TAG_279_E                           = 877  ,
+  WIFI_EXT_SPARE_REUSE_TAG_281_E                           = 879  ,
+  WIFI_EXT_SPARE_REUSE_TAG_283_E                           = 881  ,
+  WIFI_EXT_SPARE_REUSE_TAG_285_E                           = 883  ,
+  WIFI_EXT_SPARE_REUSE_TAG_287_E                           = 885  ,
+  WIFI_EXT_SPARE_REUSE_TAG_289_E                           = 887  ,
+  WIFI_EXT_SPARE_REUSE_TAG_291_E                           = 889  ,
+  WIFI_EXT_SPARE_REUSE_TAG_293_E                           = 891  ,
+  WIFI_EXT_SPARE_REUSE_TAG_295_E                           = 893  ,
+  WIFI_EXT_SPARE_REUSE_TAG_297_E                           = 895  ,
+  WIFI_EXT_SPARE_REUSE_TAG_299_E                           = 897  ,
+  WIFI_EXT_SPARE_REUSE_TAG_301_E                           = 899  ,
+  WIFI_EXT_SPARE_REUSE_TAG_303_E                           = 901  ,
+  WIFI_EXT_SPARE_REUSE_TAG_305_E                           = 903  ,
+  WIFI_EXT_SPARE_REUSE_TAG_307_E                           = 905  ,
+  WIFI_EXT_SPARE_REUSE_TAG_309_E                           = 907  ,
+  WIFI_EXT_SPARE_REUSE_TAG_311_E                           = 909  ,
+  WIFI_EXT_SPARE_REUSE_TAG_313_E                           = 911  ,
+  WIFI_EXT_SPARE_REUSE_TAG_315_E                           = 913  ,
+  WIFI_EXT_SPARE_REUSE_TAG_317_E                           = 915  ,
+  WIFI_EXT_SPARE_REUSE_TAG_319_E                           = 917  ,
+  WIFI_EXT_SPARE_REUSE_TAG_321_E                           = 919  ,
+  WIFI_EXT_SPARE_REUSE_TAG_323_E                           = 921  ,
+  WIFI_EXT_SPARE_REUSE_TAG_325_E                           = 923  ,
+  WIFI_EXT_SPARE_REUSE_TAG_327_E                           = 925  ,
+  WIFI_EXT_SPARE_REUSE_TAG_329_E                           = 927  ,
+  WIFI_EXT_SPARE_REUSE_TAG_331_E                           = 929  ,
+  WIFI_EXT_SPARE_REUSE_TAG_333_E                           = 931  ,
+  WIFI_EXT_SPARE_REUSE_TAG_335_E                           = 933  ,
+  WIFI_EXT_SPARE_REUSE_TAG_337_E                           = 935  ,
+  WIFI_EXT_SPARE_REUSE_TAG_339_E                           = 937  ,
+  WIFI_EXT_SPARE_REUSE_TAG_341_E                           = 939  ,
+  WIFI_EXT_SPARE_REUSE_TAG_343_E                           = 941  ,
+  WIFI_EXT_SPARE_REUSE_TAG_345_E                           = 943  ,
+  WIFI_EXT_SPARE_REUSE_TAG_347_E                           = 945  ,
+  WIFI_EXT_SPARE_REUSE_TAG_349_E                           = 947  ,
+  WIFI_EXT_SPARE_REUSE_TAG_351_E                           = 949  ,
+  WIFI_EXT_SPARE_REUSE_TAG_353_E                           = 951  ,
+  WIFI_EXT_SPARE_REUSE_TAG_355_E                           = 953  ,
+  WIFI_EXT_SPARE_REUSE_TAG_357_E                           = 955  ,
+  WIFI_EXT_SPARE_REUSE_TAG_359_E                           = 957  ,
+  WIFI_EXT_SPARE_REUSE_TAG_361_E                           = 959  ,
+  WIFI_EXT_SPARE_REUSE_TAG_363_E                           = 961  ,
+  WIFI_EXT_SPARE_REUSE_TAG_365_E                           = 963  ,
+  WIFI_EXT_SPARE_REUSE_TAG_367_E                           = 965  ,
+  WIFI_EXT_SPARE_REUSE_TAG_369_E                           = 967  ,
+  WIFI_EXT_SPARE_REUSE_TAG_371_E                           = 969  ,
+  WIFI_EXT_SPARE_REUSE_TAG_373_E                           = 971  ,
+  WIFI_EXT_SPARE_REUSE_TAG_375_E                           = 973  ,
+  WIFI_EXT_SPARE_REUSE_TAG_377_E                           = 975  ,
+  WIFI_EXT_SPARE_REUSE_TAG_379_E                           = 977  ,
+  WIFI_EXT_SPARE_REUSE_TAG_381_E                           = 979  ,
+  WIFI_EXT_SPARE_REUSE_TAG_383_E                           = 981  ,
+  WIFI_EXT_SPARE_REUSE_TAG_385_E                           = 983  ,
+  WIFI_EXT_SPARE_REUSE_TAG_387_E                           = 985  ,
+  WIFI_EXT_SPARE_REUSE_TAG_389_E                           = 987  ,
+  WIFI_EXT_SPARE_REUSE_TAG_391_E                           = 989  ,
+  WIFI_EXT_SPARE_REUSE_TAG_393_E                           = 991  ,
+  WIFI_EXT_SPARE_REUSE_TAG_395_E                           = 993  ,
+  WIFI_EXT_SPARE_REUSE_TAG_397_E                           = 995  ,
+  WIFI_EXT_SPARE_REUSE_TAG_399_E                           = 997  ,
+  WIFI_EXT_SPARE_REUSE_TAG_401_E                           = 999  ,
+  WIFI_EXT_SPARE_REUSE_TAG_403_E                           = 1001  ,
+  WIFI_EXT_SPARE_REUSE_TAG_405_E                           = 1003  ,
+  WIFI_EXT_SPARE_REUSE_TAG_407_E                           = 1005  ,
+  WIFI_EXT_SPARE_REUSE_TAG_409_E                           = 1007  ,
+  WIFI_EXT_SPARE_REUSE_TAG_411_E                           = 1009  ,
+  WIFI_EXT_SPARE_REUSE_TAG_413_E                           = 1011  ,
+  WIFI_EXT_SPARE_REUSE_TAG_415_E                           = 1013  ,
+  WIFI_EXT_SPARE_REUSE_TAG_417_E                           = 1015  ,
+  WIFI_EXT_SPARE_REUSE_TAG_419_E                           = 1017  ,
+  WIFI_EXT_SPARE_REUSE_TAG_421_E                           = 1019  ,
+  WIFI_EXT_SPARE_REUSE_TAG_423_E                           = 1021
+} ext_tlv_tag_def__e;
+
+typedef enum {
+  WIFI_N_EXT_MACTX_CBF_START_E                             = 0  ,
+  WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E                         = 2  ,
+  WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E               = 4  ,
+  WIFI_N_EXT_MACTX_CBF_DATA_E                              = 6  ,
+  WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E                         = 8  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E      = 10  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E                   = 12  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E    = 14  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_END_E                          = 16  ,
+  WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E                      = 18  ,
+  WIFI_N_EXT_PHYRX_NC_DATA_E                               = 20  ,
+  WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E                      = 64  ,
+  WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E                  = 66  ,
+  WIFI_N_EXT_MACRX_NDP_TIMEOUT_E                           = 68  ,
+  WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E                       = 70  ,
+  WIFI_N_EXT_MACRX_NAP_USER_E                              = 72  ,
+  WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E                 = 74  ,
+  WIFI_N_EXT_PHYTX_ABORT_REQUEST_E                         = 76  ,
+  WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E              = 78  ,
+  WIFI_N_EXT_PHYTX_DATA_REQUEST_E                          = 80  ,
+  WIFI_N_EXT_PHYTX_NAP_ACK_E                               = 82  ,
+  WIFI_N_EXT_PHYTX_OFF_ACK_E                               = 84  ,
+  WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E                         = 86  ,
+  WIFI_N_EXT_MACTX_ABORT_REQUEST_E                         = 88  ,
+  WIFI_N_EXT_MACTX_PKT_END_E                               = 90  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E                      = 92  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_E                           = 94  ,
+  WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E                    = 96  ,
+  WIFI_N_EXT_EXAMPLE_TLV_16_E                              = 98  ,
+  WIFI_N_EXT_MACTX_PHY_ON_E                                = 100  ,
+  WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E                     = 102  ,
+  WIFI_N_EXT_MACTX_PHY_DESC_E                              = 104  ,
+  WIFI_N_EXT_MACTX_L_SIG_B_E                               = 106  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_A_E                             = 108  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E                        = 110  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E                       = 112  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E                        = 114  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E                       = 116  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_SU_E                           = 118  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E                        = 120  ,
+  WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E                          = 122  ,
+  WIFI_N_EXT_MACTX_DELETE_CV_E                             = 124  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E                  = 126  ,
+  WIFI_N_EXT_MACTX_PHY_NAP_E                               = 128  ,
+  WIFI_N_EXT_PHYRX_ABORT_ACK_E                             = 130  ,
+  WIFI_N_EXT_PHYRX_RSSI_LEGACY_E                           = 132  ,
+  WIFI_N_EXT_PHYRX_USER_INFO_E                             = 134  ,
+  WIFI_N_EXT_PHYRX_DEBUG_E                                 = 136  ,
+  WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E                    = 138  ,
+  WIFI_N_EXT_PHYRX_L_SIG_B_E                               = 140  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_A_E                             = 142  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E                        = 144  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E                       = 146  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E                        = 148  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E                       = 150  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E                        = 152  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E                          = 154  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E                       = 156  ,
+  WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E                      = 158  ,
+  WIFI_N_EXT_COEX_TX_REQ_E                                 = 160  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E                         = 162  ,
+  WIFI_N_EXT_NA_LENGTH_END_E                               = 164  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E                         = 166  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E                         = 168  ,
+  WIFI_N_EXT_PDG_FES_SETUP_E                               = 170  ,
+  WIFI_N_EXT_PDG_TX_REQ_E                                  = 172  ,
+  WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E                        = 174  ,
+  WIFI_N_EXT_AUX_PPDU_END_E                                = 176  ,
+  WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E             = 178  ,
+  WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E                        = 180  ,
+  WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E                      = 182  ,
+  WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E                      = 184  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_E                               = 186  ,
+  WIFI_N_EXT_TX_DATA_E                                     = 188  ,
+  WIFI_N_EXT_RX_PACKET_E                                   = 190  ,
+  WIFI_N_EXT_TX_MPDU_END_E                                 = 192  ,
+  WIFI_N_EXT_TX_MSDU_END_E                                 = 194  ,
+  WIFI_N_EXT_TX_SW_MODE_SETUP_E                            = 196  ,
+  WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E                    = 198  ,
+  WIFI_N_EXT_EXAMPLE_USER_TLV_32_E                         = 200  ,
+  WIFI_N_EXT_PDG_USER_SETUP_E                              = 202  ,
+  WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E                = 206  ,
+  WIFI_N_EXT_TX_FLUSH_E                                    = 208  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E                        = 210  ,
+  WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E                     = 212  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_E                         = 214  ,
+  WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E                 = 216  ,
+  WIFI_N_EXT_RX_TRIG_INFO_E                                = 218  ,
+  WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E                         = 220  ,
+  WIFI_N_EXT_COEX_RX_STATUS_E                              = 222  ,
+  WIFI_N_EXT_RX_PPDU_START_E                               = 224  ,
+  WIFI_N_EXT_RX_MPDU_START_E                               = 226  ,
+  WIFI_N_EXT_RX_MSDU_START_E                               = 228  ,
+  WIFI_N_EXT_RX_ATTENTION_E                                = 230  ,
+  WIFI_N_EXT_RX_PHY_SLEEP_E                                = 232  ,
+  WIFI_N_EXT_RX_PEER_ENTRY_E                               = 234  ,
+  WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E                   = 236  ,
+  WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E             = 238  ,
+  WIFI_N_EXT_TX_CBF_INFO_E                                 = 240  ,
+  WIFI_N_EXT_RX_MPDU_PCU_START_E                           = 242  ,
+  WIFI_N_EXT_RX_USER_PPDU_END_E                            = 244  ,
+  WIFI_N_EXT_RX_PREAMBLE_E                                 = 246  ,
+  WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E                        = 248  ,
+  WIFI_N_EXT_RXPCU_SETUP_E                                 = 250  ,
+  WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E                     = 252  ,
+  WIFI_N_EXT_COEX_TX_RESP_E                                = 254  ,
+  WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E                         = 256  ,
+  WIFI_N_EXT_RESPONSE_START_STATUS_E                       = 258  ,
+  WIFI_N_EXT_CRYPTO_STATUS_E                               = 260  ,
+  WIFI_N_EXT_COEX_TX_STOP_CTRL_E                           = 262  ,
+  WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E                       = 264  ,
+  WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E                    = 266  ,
+  WIFI_N_EXT_TX_FES_STATUS_PROT_E                          = 268  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_PROT_E                    = 270  ,
+  WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E           = 272  ,
+  WIFI_N_EXT_WHO_ANCHOR_OFFSET_E                           = 274  ,
+  WIFI_N_EXT_WHO_CCE_INFO_E                                = 276  ,
+  WIFI_N_EXT_WHO_COMMIT_DONE_E                             = 278  ,
+  WIFI_N_EXT_WHO_L2_LLC_E                                  = 280  ,
+  WIFI_N_EXT_WHO_L3_CHECKSUM_E                             = 282  ,
+  WIFI_N_EXT_WHO_L4_CHECKSUM_E                             = 284  ,
+  WIFI_N_EXT_WHO_MSDU_E                                    = 286  ,
+  WIFI_N_EXT_WHO_PACKET_DATA_E                             = 288  ,
+  WIFI_N_EXT_WHO_PPDU_END_E                                = 290  ,
+  WIFI_N_EXT_WHO_TSO_E                                     = 292  ,
+  WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E                         = 294  ,
+  WIFI_N_EXT_MPDU_INFO_END_E                               = 296  ,
+  WIFI_N_EXT_TX_QUEUE_EXTENSION_E                          = 298  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E             = 300  ,
+  WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E                         = 302  ,
+  WIFI_N_EXT_WHO_TERMINATE_E                               = 304  ,
+  WIFI_N_EXT_TX_CV_DATA_E                                  = 306  ,
+  WIFI_N_EXT_PROT_TX_END_E                                 = 308  ,
+  WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E                    = 310  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E                  = 312  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_E                           = 322  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E                    = 324  ,
+  WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E                       = 326  ,
+  WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E             = 328  ,
+  WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E                  = 330  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_E                                = 332  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E                         = 334  ,
+  WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E                         = 336  ,
+  WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E   = 340  ,
+  WIFI_N_EXT_RX_PPDU_START_USER_INFO_E                     = 342  ,
+  WIFI_N_EXT_COEX_MAC_NAP_E                                = 344  ,
+  WIFI_N_EXT_WHO_MESH_CONTROL_E                            = 346  ,
+  WIFI_N_EXT_PDG_SW_MODE_BW_END_E                          = 348  ,
+  WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E                    = 350  ,
+  WIFI_N_EXT_RX_PPDU_START_DROPPED_E                       = 352  ,
+  WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E             = 354  ,
+  WIFI_N_EXT_RX_MSDU_START_DROPPED_E                       = 356  ,
+  WIFI_N_EXT_RX_MPDU_END_DROPPED_E                         = 358  ,
+  WIFI_N_EXT_TXPCU_USER_SETUP_E                            = 360  ,
+  WIFI_N_EXT_CMD_PART_0_END_E                              = 362  ,
+  WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E                  = 364  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_E                              = 366  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E               = 368  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E        = 370  ,
+  WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E                    = 372  ,
+  WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E                    = 374  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E                         = 376  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E                = 378  ,
+  WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E                         = 380  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E                = 382  ,
+  WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E                    = 384  ,
+  WIFI_N_EXT_R2R_STATUS_END_E                              = 386  ,
+  WIFI_N_EXT_END_OF_FLUSH_MARKER_E                         = 388  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E             = 390  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E                 = 392  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E                = 394  ,
+  WIFI_N_EXT_TX_LOOPBACK_SETUP_E                           = 396  ,
+  WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E                      = 398  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E      = 400  ,
+  WIFI_N_EXT_TX_WUR_DATA_E                                 = 402  ,
+  WIFI_N_EXT_RX_PPDU_END_MIDDLE_E                          = 404  ,
+  WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E            = 406  ,
+  WIFI_N_EXT_SRP_INFO_E                                    = 408  ,
+  WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E                     = 410  ,
+  WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E                        = 412  ,
+  WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E                       = 414  ,
+  WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E                   = 416  ,
+  WIFI_N_EXT_LMR_TX_END_E                                  = 418  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E       = 420  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E   = 422  ,
+  WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E                    = 424  ,
+  WIFI_N_EXT_MACTX___RESERVED_G_0013                       = 426  ,
+  WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E                          = 428  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E                   = 430  ,
+  WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E                       = 432  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E                   = 434  ,
+  WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E                 = 436  ,
+  WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E                      = 438  ,
+  WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E                    = 440  ,
+  WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E                    = 442  ,
+  WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E                         = 444  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E         = 446  ,
+  WIFI_N_EXT_LMR_MPDU_START_E                              = 448  ,
+  WIFI_N_EXT_LMR_MPDU_END_E                                = 450  ,
+  WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E                      = 452  ,
+  WIFI_N_EXT_TQM_ACKED_1K_MPDU_E                           = 454  ,
+  WIFI_N_EXT_PHYRX_LOCATION_E                              = 456  ,
+  WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E                      = 458  ,
+  WIFI_N_EXT_MLO_TX_REQ_MU_E                               = 460  ,
+  WIFI_N_EXT_MLO_RX_NOTIFICATION_E                         = 462  ,
+  WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E                       = 464  ,
+  WIFI_N_EXT_MLO_TS_SYNC_MSG_E                             = 466  ,
+  WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E                        = 468  ,
+  WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E                         = 470  ,
+  WIFI_N_EXT_TX_FRAG_STATE_E                               = 472  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E       = 474  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E                       = 476  ,
+  WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E              = 478  ,
+  WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E               = 480  ,
+  WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E                    = 482  ,
+  WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E                  = 484  ,
+  WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E             = 486  ,
+  WIFI_N_EXT_PHYRX___RESERVED_G_0014                       = 488  ,
+  WIFI_N_EXT_PHYTX___RESERVED_G_0014                       = 490  ,
+  WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E                        = 492  ,
+  WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E                        = 494  ,
+  WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E                         = 496  ,
+  WIFI_N_EXT_OVERWRITE_RESP_START_E                        = 498  ,
+  WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E                   = 500  ,
+  WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E                   = 502  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E                = 504  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E              = 506  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E                       = 508  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E   = 510  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E             = 512  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E                        = 514  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_USER_E                          = 516  ,
+  WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E                = 518  ,
+  WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E               = 520  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E               = 522  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E                 = 524  ,
+  WIFI_N_EXT_WSI_DIRECT_MESSAGE_E                          = 526  ,
+  WIFI_N_EXT_MACTX_EMLSR_SWITCH_E                          = 528  ,
+  WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E                      = 530  ,
+  WIFI_N_EXT_EAD_COMMAND_E                                 = 532  ,
+  WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E                = 534  ,
+  WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E                 = 536  ,
+  WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E                = 538  ,
+  WIFI_N_EXT_TPI_MPDU_CONTINUATION_E                       = 540  ,
+  WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E                       = 542  ,
+  WIFI_N_EXT_TPI_STATUS_E                                  = 544  ,
+  WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E                        = 546  ,
+  WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E                   = 548  ,
+  WIFI_N_EXT_RPI_STATUS_E                                  = 550  ,
+  WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E                        = 552  ,
+  WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E                   = 554  ,
+  WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E                   = 556  ,
+  WIFI_N_EXT_TCC_STATUS_E                                  = 558  ,
+  WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E                        = 560  ,
+  WIFI_N_EXT_TCC_SCHEDULER_CMD_E                           = 562  ,
+  WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E             = 564  ,
+  WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E                 = 566  ,
+  WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E                 = 568  ,
+  WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E                  = 570  ,
+  WIFI_N_EXT_TCC_FES_END_MESSAGE_E                         = 572  ,
+  WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E                = 574  ,
+  WIFI_N_EXT_EAD_MSDU_STATUS_START_E                       = 576  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E                        = 578  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E                     = 580  ,
+  WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E                       = 582  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E      = 584  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E                    = 586  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E                      = 588  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E                     = 590  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E                      = 592  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E                      = 594  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_COSR_E                      = 596  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_0_E                           = 598  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_2_E                           = 600  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_4_E                           = 602  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_6_E                           = 604  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_8_E                           = 606  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_10_E                          = 608  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_12_E                          = 610  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_14_E                          = 612  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_16_E                          = 614  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_18_E                          = 616  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_20_E                          = 618  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_22_E                          = 620  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_24_E                          = 622  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_26_E                          = 624  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_28_E                          = 626  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_30_E                          = 628  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_32_E                          = 630  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_34_E                          = 632  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_36_E                          = 634  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_38_E                          = 636  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_40_E                          = 638  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_42_E                          = 640  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_44_E                          = 642  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_46_E                          = 644  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_48_E                          = 646  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_50_E                          = 648  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_52_E                          = 650  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_54_E                          = 652  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_56_E                          = 654  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_58_E                          = 656  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_60_E                          = 658  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_62_E                          = 660  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_64_E                          = 662  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_66_E                          = 664  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_68_E                          = 666  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_70_E                          = 668  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_72_E                          = 670  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_74_E                          = 672  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_76_E                          = 674  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_78_E                          = 676  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_80_E                          = 678  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_82_E                          = 680  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_84_E                          = 682  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_86_E                          = 684  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_88_E                          = 686  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_90_E                          = 688  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_92_E                          = 690  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_94_E                          = 692  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_96_E                          = 694  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_98_E                          = 696  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_100_E                         = 698  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_102_E                         = 700  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_104_E                         = 702  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_106_E                         = 704  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_108_E                         = 706  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_110_E                         = 708  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_112_E                         = 710  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_114_E                         = 712  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_116_E                         = 714  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_118_E                         = 716  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_120_E                         = 718  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_122_E                         = 720  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_124_E                         = 722  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_126_E                         = 724  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_128_E                         = 726  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_130_E                         = 728  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_132_E                         = 730  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_134_E                         = 732  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_136_E                         = 734  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_138_E                         = 736  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_140_E                         = 738  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_142_E                         = 740  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_144_E                         = 742  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_146_E                         = 744  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_148_E                         = 746  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_150_E                         = 748  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_152_E                         = 750  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_154_E                         = 752  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_156_E                         = 754  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_158_E                         = 756  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_160_E                         = 758  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_162_E                         = 760  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_164_E                         = 762  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_166_E                         = 764  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_168_E                         = 766  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_170_E                         = 768  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_172_E                         = 770  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_174_E                         = 772  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_176_E                         = 774  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_178_E                         = 776  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_180_E                         = 778  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_182_E                         = 780  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_184_E                         = 782  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_186_E                         = 784  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_188_E                         = 786  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_190_E                         = 788  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_192_E                         = 790  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_194_E                         = 792  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_196_E                         = 794  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_198_E                         = 796  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_200_E                         = 798  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_202_E                         = 800  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_204_E                         = 802  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_206_E                         = 804  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_208_E                         = 806  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_210_E                         = 808  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_212_E                         = 810  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_214_E                         = 812  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_216_E                         = 814  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_218_E                         = 816  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_220_E                         = 818  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_222_E                         = 820  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_224_E                         = 822  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_226_E                         = 824  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_228_E                         = 826  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_230_E                         = 828  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_232_E                         = 830  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_234_E                         = 832  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_236_E                         = 834  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_238_E                         = 836  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_240_E                         = 838  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_242_E                         = 840  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_244_E                         = 842  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_246_E                         = 844  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_248_E                         = 846  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_250_E                         = 848  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_252_E                         = 850  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_254_E                         = 852  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_256_E                         = 854  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_258_E                         = 856  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_260_E                         = 858  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_262_E                         = 860  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_264_E                         = 862  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_266_E                         = 864  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_268_E                         = 866  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_270_E                         = 868  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_272_E                         = 870  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_274_E                         = 872  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_276_E                         = 874  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_278_E                         = 876  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_280_E                         = 878  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_282_E                         = 880  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_284_E                         = 882  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_286_E                         = 884  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_288_E                         = 886  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_290_E                         = 888  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_292_E                         = 890  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_294_E                         = 892  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_296_E                         = 894  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_298_E                         = 896  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_300_E                         = 898  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_302_E                         = 900  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_304_E                         = 902  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_306_E                         = 904  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_308_E                         = 906  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_310_E                         = 908  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_312_E                         = 910  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_314_E                         = 912  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_316_E                         = 914  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_318_E                         = 916  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_320_E                         = 918  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_322_E                         = 920  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_324_E                         = 922  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_326_E                         = 924  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_328_E                         = 926  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_330_E                         = 928  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_332_E                         = 930  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_334_E                         = 932  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_336_E                         = 934  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_338_E                         = 936  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_340_E                         = 938  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_342_E                         = 940  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_344_E                         = 942  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_346_E                         = 944  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_348_E                         = 946  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_350_E                         = 948  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_352_E                         = 950  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_354_E                         = 952  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_356_E                         = 954  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_358_E                         = 956  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_360_E                         = 958  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_362_E                         = 960  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_364_E                         = 962  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_366_E                         = 964  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_368_E                         = 966  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_370_E                         = 968  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_372_E                         = 970  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_374_E                         = 972  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_376_E                         = 974  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_378_E                         = 976  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_380_E                         = 978  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_382_E                         = 980  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_384_E                         = 982  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_386_E                         = 984  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_388_E                         = 986  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_390_E                         = 988  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_392_E                         = 990  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_394_E                         = 992  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_396_E                         = 994  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_398_E                         = 996  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_400_E                         = 998  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_402_E                         = 1000  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_404_E                         = 1002  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_406_E                         = 1004  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_408_E                         = 1006  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_410_E                         = 1008  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_412_E                         = 1010  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_414_E                         = 1012  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_416_E                         = 1014  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_418_E                         = 1016  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_420_E                         = 1018  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_422_E                         = 1020
+} non_ext_tlv_tag_def__e;
+
+#endif
diff --git a/hw/fig/v2/tqm2sw_completion_ring.h b/hw/fig/v2/tqm2sw_completion_ring.h
new file mode 100644
index 000000000000..f67deea1f6a1
--- /dev/null
+++ b/hw/fig/v2/tqm2sw_completion_ring.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TQM2SW_COMPLETION_RING_H_
+#define _TQM2SW_COMPLETION_RING_H_
+
+#include "tx_rate_stats_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8
+
+struct tqm2sw_completion_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      cookie_conversion_status                                :  1,
+                      tqm_completion_error                                    :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t tqm_completion_error                                    :  1,
+                      cookie_conversion_status                                :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB                            0
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB                            2
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK                           0x00000007
+
+#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET                                      0x00000008
+#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK                                        0x00000008
+
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET                                   0x00000008
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB                                      4
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB                                      5
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK                                     0x00000030
+
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET                           0x00000008
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB                              6
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB                              8
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK                             0x000001c0
+
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB                            9
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB                            12
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK                           0x00001e00
+
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB                               13
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB                               16
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK                              0x0001e000
+
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK                              0x00020000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB                            18
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB                            29
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK                           0x3ffc0000
+
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET                      0x00000008
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK                        0x40000000
+
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET                          0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK                            0x80000000
+
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET                             0x0000000c
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB                                0
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB                                23
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK                               0x00ffffff
+
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET                                0x0000000c
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB                                   24
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB                                   30
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK                                  0x7f000000
+
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET                      0x0000000c
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK                        0x80000000
+
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET                                0x00000010
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB                                   0
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB                                   7
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK                                  0x000000ff
+
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET                                    0x00000010
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK                                      0x00000100
+
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET                                     0x00000010
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK                                       0x00000200
+
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET                            0x00000010
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB                               10
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB                               12
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK                              0x00001c00
+
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET                              0x00000010
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB                                 13
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB                                 31
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK                                0xffffe000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET        0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK          0x00000001
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB                        1
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB                        3
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK                       0x0000000e
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET               0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                  4
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                  7
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                 0x000000f0
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK                     0x00000100
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK                     0x00000200
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB                       10
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB                       11
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK                      0x00000c00
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB                       12
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB                       16
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK                      0x0001f000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET         0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB            17
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB            19
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK           0x000e0000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET              0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                0x00100000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB                        21
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB                        24
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK                       0x01e00000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB                        25
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB                        28
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK                       0x1e000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB                       29
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB                       31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK                      0xe0000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET           0x00000018
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB              0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB              31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK             0xffffffff
+
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET                                    0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB                                       0
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB                                       15
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK                                      0x0000ffff
+
+#define TQM2SW_COMPLETION_RING_TID_OFFSET                                           0x0000001c
+#define TQM2SW_COMPLETION_RING_TID_LSB                                              16
+#define TQM2SW_COMPLETION_RING_TID_MSB                                              19
+#define TQM2SW_COMPLETION_RING_TID_MASK                                             0x000f0000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET                        0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB                           20
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB                           27
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK                          0x0ff00000
+
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET                                 0x0000001c
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB                                    28
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB                                    31
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK                                   0xf0000000
+
+#endif
diff --git a/hw/fig/v2/tx_cbf_info.h b/hw/fig/v2/tx_cbf_info.h
new file mode 100644
index 000000000000..fed064ce95a8
--- /dev/null
+++ b/hw/fig/v2/tx_cbf_info.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_CBF_INFO_H_
+#define _TX_CBF_INFO_H_
+
+#define NUM_OF_DWORDS_TX_CBF_INFO 16
+
+#define NUM_OF_QWORDS_TX_CBF_INFO 8
+
+struct tx_cbf_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sw_peer_id                                              : 16,
+                      pre_cbf_duration                                        : 16;
+             uint32_t brpoll_info_valid                                       :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      bandwidth                                               :  3,
+                      brpoll_info                                             :  8,
+                      cbf_response_table_base_index                           :  8,
+                      peer_index                                              :  3,
+                      pkt_type                                                :  4,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t trigger_brpoll_common_info_15_0                         : 16,
+                      trigger_brpoll_common_info_31_16                        : 16;
+             uint32_t trigger_brpoll_user_info_15_0                           : 16,
+                      trigger_brpoll_user_info_31_16                          : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      sta_partial_aid                                         : 11,
+                      __reserved_g_0035                                                 :  1,
+                      reserved_8a                                             :  3,
+                      cbf_resp_pwr_mgmt                                       :  1;
+             uint32_t group_id                                                :  6,
+                      rssi_comb                                               :  8,
+                      reserved_9a                                             :  2,
+                      vht_ndpa_sta_info                                       : 16;
+             uint32_t he_eht_sta_info_15_0                                    : 16,
+                      he_eht_sta_info_31_16                                   : 16;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_11a                                            :  8;
+             uint32_t sw_response_frame_length                                : 16,
+                      sw_response_tlv_from_crypto                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2,
+                      __reserved_g_0022                                                 :  1,
+                      secure                                                  :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      emlsr_main_tlv_if                                       :  1,
+                      reserved_12a                                            :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      npda_info_11be_valid                                    :  1,
+                      eht_duplicate_mode                                      :  2,
+                      reserved_13a                                            : 11;
+             uint32_t eht_sta_info_39_32                                      :  8,
+                      unassociated___reserved_g_0022_peer                               :  1,
+                      reserved_14a                                            : 23;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t pre_cbf_duration                                        : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      pkt_type                                                :  4,
+                      peer_index                                              :  3,
+                      cbf_response_table_base_index                           :  8,
+                      brpoll_info                                             :  8,
+                      bandwidth                                               :  3,
+                      dot11ax_su_extended                                     :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      brpoll_info_valid                                       :  1;
+             uint32_t trigger_brpoll_common_info_31_16                        : 16,
+                      trigger_brpoll_common_info_15_0                         : 16;
+             uint32_t trigger_brpoll_user_info_31_16                          : 16,
+                      trigger_brpoll_user_info_15_0                           : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t cbf_resp_pwr_mgmt                                       :  1,
+                      reserved_8a                                             :  3,
+                      __reserved_g_0035                                                 :  1,
+                      sta_partial_aid                                         : 11,
+                      addr3_47_32                                             : 16;
+             uint32_t vht_ndpa_sta_info                                       : 16,
+                      reserved_9a                                             :  2,
+                      rssi_comb                                               :  8,
+                      group_id                                                :  6;
+             uint32_t he_eht_sta_info_31_16                                   : 16,
+                      he_eht_sta_info_15_0                                    : 16;
+             uint32_t reserved_11a                                            :  8,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_12a                                            :  1,
+                      emlsr_main_tlv_if                                       :  1,
+                      tb___reserved_g_0022_response_required                            :  2,
+                      secure                                                  :  1,
+                      __reserved_g_0022                                                 :  1,
+                      wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      sw_response_frame_length                                : 16;
+             uint32_t reserved_13a                                            : 11,
+                      eht_duplicate_mode                                      :  2,
+                      npda_info_11be_valid                                    :  1,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_14a                                            : 23,
+                      unassociated___reserved_g_0022_peer                               :  1,
+                      eht_sta_info_39_32                                      :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_CBF_INFO_SW_PEER_ID_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_SW_PEER_ID_LSB                                                  0
+#define TX_CBF_INFO_SW_PEER_ID_MSB                                                  15
+#define TX_CBF_INFO_SW_PEER_ID_MASK                                                 0x000000000000ffff
+
+#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET                                         0x0000000000000000
+#define TX_CBF_INFO_PRE_CBF_DURATION_LSB                                            16
+#define TX_CBF_INFO_PRE_CBF_DURATION_MSB                                            31
+#define TX_CBF_INFO_PRE_CBF_DURATION_MASK                                           0x00000000ffff0000
+
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET                                        0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK                                          0x0000000100000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET                                0x0000000000000000
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK                                  0x0000000200000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK                                       0x0000000400000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK                                       0x0000000800000000
+
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET                                      0x0000000000000000
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK                                        0x0000001000000000
+
+#define TX_CBF_INFO_BANDWIDTH_OFFSET                                                0x0000000000000000
+#define TX_CBF_INFO_BANDWIDTH_LSB                                                   37
+#define TX_CBF_INFO_BANDWIDTH_MSB                                                   39
+#define TX_CBF_INFO_BANDWIDTH_MASK                                                  0x000000e000000000
+
+#define TX_CBF_INFO_BRPOLL_INFO_OFFSET                                              0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_LSB                                                 40
+#define TX_CBF_INFO_BRPOLL_INFO_MSB                                                 47
+#define TX_CBF_INFO_BRPOLL_INFO_MASK                                                0x0000ff0000000000
+
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET                            0x0000000000000000
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB                               48
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB                               55
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK                              0x00ff000000000000
+
+#define TX_CBF_INFO_PEER_INDEX_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_PEER_INDEX_LSB                                                  56
+#define TX_CBF_INFO_PEER_INDEX_MSB                                                  58
+#define TX_CBF_INFO_PEER_INDEX_MASK                                                 0x0700000000000000
+
+#define TX_CBF_INFO_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_CBF_INFO_PKT_TYPE_LSB                                                    59
+#define TX_CBF_INFO_PKT_TYPE_MSB                                                    62
+#define TX_CBF_INFO_PKT_TYPE_MASK                                                   0x7800000000000000
+
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET                                   0x0000000000000000
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK                                     0x8000000000000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET                          0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB                             0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB                             15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK                            0x000000000000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET                         0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB                            16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB                            31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK                           0x00000000ffff0000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET                            0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB                               32
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB                               47
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK                              0x0000ffff00000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET                           0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB                              48
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB                              63
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK                             0xffff000000000000
+
+#define TX_CBF_INFO_ADDR1_31_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR1_31_0_LSB                                                  0
+#define TX_CBF_INFO_ADDR1_31_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR1_31_0_MASK                                                 0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR1_47_32_OFFSET                                              0x0000000000000010
+#define TX_CBF_INFO_ADDR1_47_32_LSB                                                 32
+#define TX_CBF_INFO_ADDR1_47_32_MSB                                                 47
+#define TX_CBF_INFO_ADDR1_47_32_MASK                                                0x0000ffff00000000
+
+#define TX_CBF_INFO_ADDR2_15_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR2_15_0_LSB                                                  48
+#define TX_CBF_INFO_ADDR2_15_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR2_15_0_MASK                                                 0xffff000000000000
+
+#define TX_CBF_INFO_ADDR2_47_16_OFFSET                                              0x0000000000000018
+#define TX_CBF_INFO_ADDR2_47_16_LSB                                                 0
+#define TX_CBF_INFO_ADDR2_47_16_MSB                                                 31
+#define TX_CBF_INFO_ADDR2_47_16_MASK                                                0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR3_31_0_OFFSET                                               0x0000000000000018
+#define TX_CBF_INFO_ADDR3_31_0_LSB                                                  32
+#define TX_CBF_INFO_ADDR3_31_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR3_31_0_MASK                                                 0xffffffff00000000
+
+#define TX_CBF_INFO_ADDR3_47_32_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_ADDR3_47_32_LSB                                                 0
+#define TX_CBF_INFO_ADDR3_47_32_MSB                                                 15
+#define TX_CBF_INFO_ADDR3_47_32_MASK                                                0x000000000000ffff
+
+#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET                                          0x0000000000000020
+#define TX_CBF_INFO_STA_PARTIAL_AID_LSB                                             16
+#define TX_CBF_INFO_STA_PARTIAL_AID_MSB                                             26
+#define TX_CBF_INFO_STA_PARTIAL_AID_MASK                                            0x0000000007ff0000
+
+#define TX_CBF_INFO_RESERVED_8A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_8A_LSB                                                 28
+#define TX_CBF_INFO_RESERVED_8A_MSB                                                 30
+#define TX_CBF_INFO_RESERVED_8A_MASK                                                0x0000000070000000
+
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK                                          0x0000000080000000
+
+#define TX_CBF_INFO_GROUP_ID_OFFSET                                                 0x0000000000000020
+#define TX_CBF_INFO_GROUP_ID_LSB                                                    32
+#define TX_CBF_INFO_GROUP_ID_MSB                                                    37
+#define TX_CBF_INFO_GROUP_ID_MASK                                                   0x0000003f00000000
+
+#define TX_CBF_INFO_RSSI_COMB_OFFSET                                                0x0000000000000020
+#define TX_CBF_INFO_RSSI_COMB_LSB                                                   38
+#define TX_CBF_INFO_RSSI_COMB_MSB                                                   45
+#define TX_CBF_INFO_RSSI_COMB_MASK                                                  0x00003fc000000000
+
+#define TX_CBF_INFO_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_9A_LSB                                                 46
+#define TX_CBF_INFO_RESERVED_9A_MSB                                                 47
+#define TX_CBF_INFO_RESERVED_9A_MASK                                                0x0000c00000000000
+
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB                                           48
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB                                           63
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK                                          0xffff000000000000
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB                                        0
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB                                        15
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK                                       0x000000000000ffff
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET                                    0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB                                       16
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB                                       31
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK                                      0x00000000ffff0000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK                         0x0000000100000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                              0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                                0x0000000200000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET                            0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                               34
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                               39
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                              0x000000fc00000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET                           0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                              40
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                              43
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK                             0x00000f0000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                                 0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                                    44
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                                    45
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                                   0x0000300000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                                0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                                   46
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                                   47
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                                  0x0000c00000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET                                  0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK                                    0x0001000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK                                       0x0002000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET                      0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK                        0x0004000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET                             0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                                51
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                                54
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                               0x0078000000000000
+
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET                                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK                                         0x0080000000000000
+
+#define TX_CBF_INFO_RESERVED_11A_OFFSET                                             0x0000000000000028
+#define TX_CBF_INFO_RESERVED_11A_LSB                                                56
+#define TX_CBF_INFO_RESERVED_11A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_11A_MASK                                               0xff00000000000000
+
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                                 0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                                    0
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                                    15
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                                   0x000000000000ffff
+
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                              0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                                0x0000000000010000
+
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                                   0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK                                     0x0000000000020000
+
+#define TX_CBF_INFO_WAIT_SIFS_OFFSET                                                0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_LSB                                                   18
+#define TX_CBF_INFO_WAIT_SIFS_MSB                                                   19
+#define TX_CBF_INFO_WAIT_SIFS_MASK                                                  0x00000000000c0000
+
+#define TX_CBF_INFO_SECURE_OFFSET                                                   0x0000000000000030
+#define TX_CBF_INFO_SECURE_LSB                                                      21
+#define TX_CBF_INFO_SECURE_MSB                                                      21
+#define TX_CBF_INFO_SECURE_MASK                                                     0x0000000000200000
+
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET                                        0x0000000000000030
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK                                          0x0000000001000000
+
+#define TX_CBF_INFO_RESERVED_12A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_12A_LSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MASK                                               0x0000000002000000
+
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                          0x0000000000000030
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                             26
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                             31
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                            0x00000000fc000000
+
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                                  0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                                     32
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                                     47
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                                    0x0000ffff00000000
+
+#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET                                         0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK                                           0x0001000000000000
+
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK                                         0x0002000000000000
+
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET                                     0x0000000000000030
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK                                       0x0004000000000000
+
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB                                          51
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB                                          52
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK                                         0x0018000000000000
+
+#define TX_CBF_INFO_RESERVED_13A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_13A_LSB                                                53
+#define TX_CBF_INFO_RESERVED_13A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_13A_MASK                                               0xffe0000000000000
+
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET                                       0x0000000000000038
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB                                          0
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB                                          7
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK                                         0x00000000000000ff
+
+#define TX_CBF_INFO_RESERVED_14A_OFFSET                                             0x0000000000000038
+#define TX_CBF_INFO_RESERVED_14A_LSB                                                9
+#define TX_CBF_INFO_RESERVED_14A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_14A_MASK                                               0x00000000fffffe00
+
+#define TX_CBF_INFO_TLV64_PADDING_OFFSET                                            0x0000000000000038
+#define TX_CBF_INFO_TLV64_PADDING_LSB                                               32
+#define TX_CBF_INFO_TLV64_PADDING_MSB                                               63
+#define TX_CBF_INFO_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_setup.h b/hw/fig/v2/tx_fes_setup.h
new file mode 100644
index 000000000000..143ee87f4a5f
--- /dev/null
+++ b/hw/fig/v2/tx_fes_setup.h
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_SETUP_H_
+#define _TX_FES_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_FES_SETUP 10
+
+#define NUM_OF_QWORDS_TX_FES_SETUP 5
+
+struct tx_fes_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t fes_in_11ax_trigger_response_config                     :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      __reserved_g_0022                                                 :  1,
+                      expect_i2r_lmr                                          :  1,
+                      transmit_start_reason                                   :  3,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      puncture_from_all_allowed_modes                         :  1,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      number_of_users                                         :  6,
+                      mu_type                                                 :  1,
+                      ofdma_triggered_response                                :  1,
+                      response_to_response_cmd                                :  1;
+             uint32_t schedule_try                                            :  4,
+                      reserved_2a                                             :  1,
+                      subband_antenna_selection_en                            :  1,
+                      txbf                                                    :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      ignore_bw_available                                     :  1,
+                      ignore_tbtt                                             :  1,
+                      static_bandwidth                                        :  3,
+                      set_txop_duration_all_ones                              :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      bw_restricted_frames_embedded                           :  1,
+                      ast_index                                               : 16;
+             uint32_t cv_id                                                   :  8,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      rxpcu_setup_complete_present                            :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      mu_ndp                                                  :  1,
+                      bf_type                                                 :  2,
+                      cbf_nc_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nr_index                                            :  3,
+                      secure___reserved_g_0022_ista                                     :  1,
+                      ndpa                                                    :  1,
+                      wait_sifs                                               :  2,
+                      cbf_feedback_type_mask                                  :  1,
+                      cbf_feedback_type                                       :  1;
+             uint32_t cbf_sounding_token                                      :  6,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_bw_mask                                             :  1,
+                      cbf_bw                                                  :  3,
+                      use_static_bw                                           :  1,
+                      coex_nack_count                                         :  5,
+                      sch_tx_burst_ongoing                                    :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      ndp_frame                                               :  3,
+                      optimal_bw_retry_count                                  :  4,
+                      fes_continuation_ratio_threshold                        :  5;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t tb___reserved_g_0022                                              :  1,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      min_cts2self_count                                      :  4,
+                      max_cts2self_count                                      :  4,
+                      wifi_radar_enable                                       :  1,
+                      reserved_6a                                             :  1,
+                      wait_for_chksum_done                                    :  1,
+                      txrx_self_test_enable                                   :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      secure___reserved_g_0022_rsta                                     :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      last_command_in_burst                                   :  1,
+                      retain_peer_blackout_details                            :  1,
+                      enable_hw_qos_null                                      :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t monitor_override_sta_36_32                              :  5,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      __reserved_g_0035                                                 :  1,
+                      secure___reserved_g_0035_smr                                      :  1,
+                      __reserved_g_0035_type                                            :  2,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      cfp_protected_fes                                       :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      multiple_triggers_indication                            :  1,
+                      cmf_uif_length                                          :  4,
+                      npca_switching_cts2self_duration                        :  8,
+                      reserved_8a                                             :  3;
+             uint32_t fw2sw_info                                              : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t response_to_response_cmd                                :  1,
+                      ofdma_triggered_response                                :  1,
+                      mu_type                                                 :  1,
+                      number_of_users                                         :  6,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      puncture_from_all_allowed_modes                         :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      transmit_start_reason                                   :  3,
+                      expect_i2r_lmr                                          :  1,
+                      __reserved_g_0022                                                 :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      fes_in_11ax_trigger_response_config                     :  1;
+             uint32_t ast_index                                               : 16,
+                      bw_restricted_frames_embedded                           :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      set_txop_duration_all_ones                              :  1,
+                      static_bandwidth                                        :  3,
+                      ignore_tbtt                                             :  1,
+                      ignore_bw_available                                     :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      txbf                                                    :  1,
+                      subband_antenna_selection_en                            :  1,
+                      reserved_2a                                             :  1,
+                      schedule_try                                            :  4;
+             uint32_t cbf_feedback_type                                       :  1,
+                      cbf_feedback_type_mask                                  :  1,
+                      wait_sifs                                               :  2,
+                      ndpa                                                    :  1,
+                      secure___reserved_g_0022_ista                                     :  1,
+                      cbf_nr_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nc_index_mask                                       :  1,
+                      bf_type                                                 :  2,
+                      mu_ndp                                                  :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      rxpcu_setup_complete_present                            :  1,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      cv_id                                                   :  8;
+             uint32_t fes_continuation_ratio_threshold                        :  5,
+                      optimal_bw_retry_count                                  :  4,
+                      ndp_frame                                               :  3,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_nack_count                                         :  5,
+                      use_static_bw                                           :  1,
+                      cbf_bw                                                  :  3,
+                      cbf_bw_mask                                             :  1,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_sounding_token                                      :  6;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t enable_hw_qos_null                                      :  1,
+                      retain_peer_blackout_details                            :  1,
+                      last_command_in_burst                                   :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      secure___reserved_g_0022_rsta                                     :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      txrx_self_test_enable                                   :  1,
+                      wait_for_chksum_done                                    :  1,
+                      reserved_6a                                             :  1,
+                      wifi_radar_enable                                       :  1,
+                      max_cts2self_count                                      :  4,
+                      min_cts2self_count                                      :  4,
+                      __reserved_g_0022_trigger_subtype                                 :  4,
+                      tb___reserved_g_0022                                              :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t reserved_8a                                             :  3,
+                      npca_switching_cts2self_duration                        :  8,
+                      cmf_uif_length                                          :  4,
+                      multiple_triggers_indication                            :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      cfp_protected_fes                                       :  1,
+                      __reserved_g_0035_trigger_subtype                                 :  4,
+                      __reserved_g_0035_type                                            :  2,
+                      secure___reserved_g_0035_smr                                      :  1,
+                      __reserved_g_0035                                                 :  1,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      monitor_override_sta_36_32                              :  5;
+             uint32_t fw2sw_info                                              : 32;
+#endif
+};
+
+#define TX_FES_SETUP_SCHEDULE_ID_OFFSET                                             0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_ID_LSB                                                0
+#define TX_FES_SETUP_SCHEDULE_ID_MSB                                                31
+#define TX_FES_SETUP_SCHEDULE_ID_MASK                                               0x00000000ffffffff
+
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                     0x0000000000000000
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                       0x0000000100000000
+
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000000
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB                             33
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB                             36
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK                            0x0000001e00000000
+
+#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET                                          0x0000000000000000
+#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK                                            0x0000004000000000
+
+#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET                                   0x0000000000000000
+#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB                                      39
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB                                      41
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK                                     0x0000038000000000
+
+#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK                                          0x0000040000000000
+
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK                                  0x0000080000000000
+
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                           0x0000100000000000
+
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET                               0x0000000000000000
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK                                 0x0000200000000000
+
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                           0x0000000000000000
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                             0x0000400000000000
+
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK                           0x0000800000000000
+
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET                                    0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB                                       48
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB                                       52
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK                                      0x001f000000000000
+
+#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_FES_CONTROL_MODE_LSB                                           53
+#define TX_FES_SETUP_FES_CONTROL_MODE_MSB                                           54
+#define TX_FES_SETUP_FES_CONTROL_MODE_MASK                                          0x0060000000000000
+
+#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET                                         0x0000000000000000
+#define TX_FES_SETUP_NUMBER_OF_USERS_LSB                                            55
+#define TX_FES_SETUP_NUMBER_OF_USERS_MSB                                            60
+#define TX_FES_SETUP_NUMBER_OF_USERS_MASK                                           0x1f80000000000000
+
+#define TX_FES_SETUP_MU_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_FES_SETUP_MU_TYPE_LSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MASK                                                   0x2000000000000000
+
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK                                  0x4000000000000000
+
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK                                  0x8000000000000000
+
+#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_SCHEDULE_TRY_LSB                                               0
+#define TX_FES_SETUP_SCHEDULE_TRY_MSB                                               3
+#define TX_FES_SETUP_SCHEDULE_TRY_MASK                                              0x000000000000000f
+
+#define TX_FES_SETUP_RESERVED_2A_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_RESERVED_2A_LSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MASK                                               0x0000000000000010
+
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK                              0x0000000000000020
+
+#define TX_FES_SETUP_TXBF_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_TXBF_LSB                                                       6
+#define TX_FES_SETUP_TXBF_MSB                                                       6
+#define TX_FES_SETUP_TXBF_MASK                                                      0x0000000000000040
+
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK                              0x0000000000000080
+
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET                                     0x0000000000000008
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK                                       0x0000000000000100
+
+#define TX_FES_SETUP_IGNORE_TBTT_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_IGNORE_TBTT_LSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MASK                                               0x0000000000000200
+
+#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET                                        0x0000000000000008
+#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB                                           10
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB                                           12
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK                                          0x0000000000001c00
+
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET                              0x0000000000000008
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK                                0x0000000000002000
+
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK                              0x0000000000004000
+
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK                             0x0000000000008000
+
+#define TX_FES_SETUP_AST_INDEX_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_AST_INDEX_LSB                                                  16
+#define TX_FES_SETUP_AST_INDEX_MSB                                                  31
+#define TX_FES_SETUP_AST_INDEX_MASK                                                 0x00000000ffff0000
+
+#define TX_FES_SETUP_CV_ID_OFFSET                                                   0x0000000000000008
+#define TX_FES_SETUP_CV_ID_LSB                                                      32
+#define TX_FES_SETUP_CV_ID_MSB                                                      39
+#define TX_FES_SETUP_CV_ID_MASK                                                     0x000000ff00000000
+
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET                        0x0000000000000008
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB                           40
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB                           41
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK                          0x0000030000000000
+
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK                              0x0000040000000000
+
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB                              43
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB                              46
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK                             0x0000780000000000
+
+#define TX_FES_SETUP_MU_NDP_OFFSET                                                  0x0000000000000008
+#define TX_FES_SETUP_MU_NDP_LSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MASK                                                    0x0000800000000000
+
+#define TX_FES_SETUP_BF_TYPE_OFFSET                                                 0x0000000000000008
+#define TX_FES_SETUP_BF_TYPE_LSB                                                    48
+#define TX_FES_SETUP_BF_TYPE_MSB                                                    49
+#define TX_FES_SETUP_BF_TYPE_MASK                                                   0x0003000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK                                         0x0004000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_LSB                                               51
+#define TX_FES_SETUP_CBF_NC_INDEX_MSB                                               53
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK                                              0x0038000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK                                         0x0040000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_LSB                                               55
+#define TX_FES_SETUP_CBF_NR_INDEX_MSB                                               57
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK                                              0x0380000000000000
+
+#define TX_FES_SETUP_NDPA_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_NDPA_LSB                                                       59
+#define TX_FES_SETUP_NDPA_MSB                                                       59
+#define TX_FES_SETUP_NDPA_MASK                                                      0x0800000000000000
+
+#define TX_FES_SETUP_WAIT_SIFS_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_WAIT_SIFS_LSB                                                  60
+#define TX_FES_SETUP_WAIT_SIFS_MSB                                                  61
+#define TX_FES_SETUP_WAIT_SIFS_MASK                                                 0x3000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET                                  0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK                                    0x4000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK                                         0x8000000000000000
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET                                      0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB                                         0
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB                                         5
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK                                        0x000000000000003f
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET                                 0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK                                   0x0000000000000040
+
+#define TX_FES_SETUP_CBF_BW_MASK_OFFSET                                             0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_MASK_LSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MASK                                               0x0000000000000080
+
+#define TX_FES_SETUP_CBF_BW_OFFSET                                                  0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_LSB                                                     8
+#define TX_FES_SETUP_CBF_BW_MSB                                                     10
+#define TX_FES_SETUP_CBF_BW_MASK                                                    0x0000000000000700
+
+#define TX_FES_SETUP_USE_STATIC_BW_OFFSET                                           0x0000000000000010
+#define TX_FES_SETUP_USE_STATIC_BW_LSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MASK                                             0x0000000000000800
+
+#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET                                         0x0000000000000010
+#define TX_FES_SETUP_COEX_NACK_COUNT_LSB                                            12
+#define TX_FES_SETUP_COEX_NACK_COUNT_MSB                                            16
+#define TX_FES_SETUP_COEX_NACK_COUNT_MASK                                           0x000000000001f000
+
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET                                    0x0000000000000010
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK                                      0x0000000000020000
+
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET                           0x0000000000000010
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK                             0x0000000000040000
+
+#define TX_FES_SETUP_NDP_FRAME_OFFSET                                               0x0000000000000010
+#define TX_FES_SETUP_NDP_FRAME_LSB                                                  20
+#define TX_FES_SETUP_NDP_FRAME_MSB                                                  22
+#define TX_FES_SETUP_NDP_FRAME_MASK                                                 0x0000000000700000
+
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET                                  0x0000000000000010
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB                                     23
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB                                     26
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK                                    0x0000000007800000
+
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET                        0x0000000000000010
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB                           27
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB                           31
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK                          0x00000000f8000000
+
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET                                     0x0000000000000010
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB                                        32
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB                                        63
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK                                       0xffffffff00000000
+
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB                                         5
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB                                         8
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK                                        0x00000000000001e0
+
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB                                         9
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB                                         12
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK                                        0x0000000000001e00
+
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET                                       0x0000000000000018
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK                                         0x0000000000002000
+
+#define TX_FES_SETUP_RESERVED_6A_OFFSET                                             0x0000000000000018
+#define TX_FES_SETUP_RESERVED_6A_LSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MASK                                               0x0000000000004000
+
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK                                      0x0000000000008000
+
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK                                     0x0000000000010000
+
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET                                     0x0000000000000018
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK                                       0x0000000000020000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK                                      0x0000000000080000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET                                  0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK                                    0x0000000000100000
+
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB                               21
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB                               28
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK                              0x000000001fe00000
+
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK                                     0x0000000020000000
+
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK                              0x0000000040000000
+
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK                                        0x0000000080000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET                               0x0000000000000018
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB                                  32
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB                                  63
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK                                 0xffffffff00000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET                              0x0000000000000020
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB                                 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB                                 4
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK                                0x000000000000001f
+
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET                         0x0000000000000020
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK                           0x0000000000000020
+
+#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET                                       0x0000000000000020
+#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB                                          14
+#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB                                          14
+#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK                                         0x0000000000004000
+
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                          0x0000000000000020
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                             15
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                             15
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                            0x0000000000008000
+
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET                            0x0000000000000020
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB                               16
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB                               16
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK                              0x0000000000010000
+
+#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET                                          0x0000000000000020
+#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB                                             17
+#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB                                             20
+#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK                                            0x00000000001e0000
+
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET                        0x0000000000000020
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB                           21
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB                           28
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK                          0x000000001fe00000
+
+#define TX_FES_SETUP_RESERVED_8A_OFFSET                                             0x0000000000000020
+#define TX_FES_SETUP_RESERVED_8A_LSB                                                29
+#define TX_FES_SETUP_RESERVED_8A_MSB                                                31
+#define TX_FES_SETUP_RESERVED_8A_MASK                                               0x00000000e0000000
+
+#define TX_FES_SETUP_FW2SW_INFO_OFFSET                                              0x0000000000000020
+#define TX_FES_SETUP_FW2SW_INFO_LSB                                                 32
+#define TX_FES_SETUP_FW2SW_INFO_MSB                                                 63
+#define TX_FES_SETUP_FW2SW_INFO_MASK                                                0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_1k_ba.h b/hw/fig/v2/tx_fes_status_1k_ba.h
new file mode 100644
index 000000000000..4409dc03ac03
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_1k_ba.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_1K_BA_H_
+#define _TX_FES_STATUS_1K_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17
+
+struct tx_fes_status_1k_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#endif
+};
+
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK                                 0x0000000000000001
+
+#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK                                            0x0000000000000002
+
+#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TID_LSB                                              2
+#define TX_FES_STATUS_1K_BA_BA_TID_MSB                                              5
+#define TX_FES_STATUS_1K_BA_BA_TID_MASK                                             0x000000000000003c
+
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK                               0x0000000000000040
+
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK                                   0x0000000000000080
+
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB                                      8
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB                                      15
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK                                     0x000000000000ff00
+
+#define TX_FES_STATUS_1K_BA_SSN_OFFSET                                              0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SSN_LSB                                                 16
+#define TX_FES_STATUS_1K_BA_SSN_MSB                                                 27
+#define TX_FES_STATUS_1K_BA_SSN_MASK                                                0x000000000fff0000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB                                         28
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB                                         31
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK                                        0x00000000f0000000
+
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB                                          32
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB                                          47
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK                                         0x0000ffff00000000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB                                         48
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB                                         63
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB                                      0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB                                      31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK                                     0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB                                     32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB                                     63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK                                    0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET                                  0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB                                     0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB                                     31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK                                    0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB                                    32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB                                    63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK                                   0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET                                0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET                               0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB                                  32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB                                  63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_ack_or_ba.h b/hw/fig/v2/tx_fes_status_ack_or_ba.h
new file mode 100644
index 000000000000..678c639141ba
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_ack_or_ba.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
+#define _TX_FES_STATUS_ACK_OR_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5
+
+struct tx_fes_status_ack_or_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#endif
+};
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK                             0x0000000000000001
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK                                        0x0000000000000002
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB                                          2
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB                                          5
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK                                         0x000000000000003c
+
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK                           0x0000000000000040
+
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK                               0x0000000000000080
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB                                  8
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB                                  15
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK                                 0x000000000000ff00
+
+#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB                                             16
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB                                             27
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK                                            0x000000000fff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB                                     28
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB                                     31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK                                    0x00000000f0000000
+
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB                                      32
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB                                      47
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK                                     0x0000ffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB                                     48
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB                                     63
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK                                    0xffff000000000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB                                  0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB                                  31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET                              0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB                                 32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB                                 63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK                                0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB                                 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB                                 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK                                0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET                             0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB                                32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB                                63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK                               0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK                              0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK                              0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_end.h b/hw/fig/v2/tx_fes_status_end.h
new file mode 100644
index 000000000000..450b9227f8b2
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_end.h
@@ -0,0 +1,602 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_END_H_
+#define _TX_FES_STATUS_END_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_END 12
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_END 6
+
+struct tx_fes_status_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0052                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0035                                       :  1,
+                      __reserved_g_0036                                       :  1,
+                      __reserved_g_0032                                       :  1,
+                      __reserved_g_0033                                       :  1,
+                      __reserved_g_0072                                       :  1,
+                      __reserved_g_0073                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0066                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0063                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      global_fes_transmit_result                              :  4,
+                      cbf_bw_received_valid                                   :  1,
+                      cbf_bw_received                                         :  3,
+                      actual_received_ack_type                                :  4,
+                      sta_response_count                                      :  6,
+                      more_data_received                                      :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_after_struct16                                 :  4,
+                      brp_info_valid                                          :  1,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      reserved_1a                                             :  5,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      only_null_delim_sent                                    :  1;
+             uint32_t terminate___reserved_g_0022_sequence                              :  1,
+                      unsolicited_erts_tx                                     :  1,
+                      ects_response_type                                      :  2,
+                      eba_response_type                                       :  2,
+                      response_type                                           :  5,
+                      r2r_end_status_to_follow                                :  1,
+                      service_cbw                                             :  3,
+                      __reserved_g_0039                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0017                                       :  1,
+                      __reserved_g_0018                                       :  1,
+                      __reserved_g_0030                                       :  1,
+                      __reserved_g_0031                                       :  1,
+                      reserved_2c                                             : 11;
+             uint32_t beamform_masked_user_bitmap_15_0                        : 16,
+                      beamform_masked_user_bitmap_31_16                       : 16;
+             uint32_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8,
+                      highest_achieved_data_null_ratio                        :  5,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      pdg_mpdu_ready                                          :  1;
+             uint32_t pdg_mpdu_count                                          : 16,
+                      pdg_est_mpdu_tx_count                                   : 16;
+             uint32_t pdg_overview_length                                     : 24,
+                      txop_duration                                           :  7,
+                      pdg_dropped_mpdu_warning                                :  1;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      fec_type                                                :  1,
+                      stbc                                                    :  1,
+                      num_data_symbols                                        : 16,
+                      ru_size                                                 :  4,
+                      reserved_17a                                            :  4;
+             uint32_t num_ltf_symbols                                         :  3,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      reserved_18a                                            :  5,
+                      dcm                                                     :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      reserved_18b                                            :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8;
+             uint32_t __reserved_g_0022_active_user_map                                 : 16,
+                      __reserved_g_0022_sent_dummy_tx                                   :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0037                                       :  1,
+                      __reserved_g_0038                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0070                                       :  1,
+                      cv_corr_status                                          :  8;
+             uint32_t current_tx_duration                                     : 16,
+                      reserved_21a                                            :  4,
+                      hw_qos_null_bitmap                                      :  8,
+                      hw_qos_null_setup_missing                               :  1,
+                      interference                                            :  1,
+                      reserved_21b                                            :  2;
+             uint32_t reserved_22b                                            :  4,
+                      __reserved_g_0027                                       :  1,
+                      __reserved_g_0028                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0050                                       :  1,
+                      __reserved_g_0025                                       :  1,
+                      __reserved_g_0026                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0048                                       :  1,
+                      __reserved_g_0023                                       :  1,
+                      __reserved_g_0024                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0021                                       :  1,
+                      __reserved_g_0022                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0044                                       :  1,
+                      __reserved_g_0019                                       :  1,
+                      __reserved_g_0020                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0042                                       :  1,
+                      coex_signaling_status                                   :  8;
+#else
+             uint32_t more_data_received                                      :  1,
+                      sta_response_count                                      :  6,
+                      actual_received_ack_type                                :  4,
+                      cbf_bw_received                                         :  3,
+                      cbf_bw_received_valid                                   :  1,
+                      global_fes_transmit_result                              :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0063                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0066                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0073                                       :  1,
+                      __reserved_g_0072                                       :  1,
+                      __reserved_g_0033                                       :  1,
+                      __reserved_g_0032                                       :  1,
+                      __reserved_g_0036                                       :  1,
+                      __reserved_g_0035                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0052                                       :  1;
+             uint32_t only_null_delim_sent                                    :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      reserved_1a                                             :  5,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      brp_info_valid                                          :  1,
+                      reserved_after_struct16                                 :  4;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t reserved_2c                                             : 11,
+                      __reserved_g_0031                                       :  1,
+                      __reserved_g_0030                                       :  1,
+                      __reserved_g_0018                                       :  1,
+                      __reserved_g_0017                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0039                                       :  1,
+                      service_cbw                                             :  3,
+                      r2r_end_status_to_follow                                :  1,
+                      response_type                                           :  5,
+                      eba_response_type                                       :  2,
+                      ects_response_type                                      :  2,
+                      unsolicited_erts_tx                                     :  1,
+                      terminate___reserved_g_0022_sequence                              :  1;
+             uint32_t beamform_masked_user_bitmap_31_16                       : 16,
+                      beamform_masked_user_bitmap_15_0                        : 16;
+             uint32_t pdg_mpdu_ready                                          :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      highest_achieved_data_null_ratio                        :  5,
+                      cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             uint32_t pdg_est_mpdu_tx_count                                   : 16,
+                      pdg_mpdu_count                                          : 16;
+             uint32_t pdg_dropped_mpdu_warning                                :  1,
+                      txop_duration                                           :  7,
+                      pdg_overview_length                                     : 24;
+             uint32_t reserved_17a                                            :  4,
+                      ru_size                                                 :  4,
+                      num_data_symbols                                        : 16,
+                      stbc                                                    :  1,
+                      fec_type                                                :  1,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      reserved_18b                                            :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      dcm                                                     :  1,
+                      reserved_18a                                            :  5,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      num_ltf_symbols                                         :  3;
+             uint32_t cv_corr_status                                          :  8,
+                      __reserved_g_0070                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0038                                       :  1,
+                      __reserved_g_0037                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0022_ftm_frame_sent                                  :  1,
+                      __reserved_g_0022_sent_dummy_tx                                   :  1,
+                      __reserved_g_0022_active_user_map                                 : 16;
+             uint32_t reserved_21b                                            :  2,
+                      interference                                            :  1,
+                      hw_qos_null_setup_missing                               :  1,
+                      hw_qos_null_bitmap                                      :  8,
+                      reserved_21a                                            :  4,
+                      current_tx_duration                                     : 16;
+             uint32_t coex_signaling_status                                   :  8,
+                      __reserved_g_0042                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0020                                       :  1,
+                      __reserved_g_0019                                       :  1,
+                      __reserved_g_0044                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0022                                       :  1,
+                      __reserved_g_0021                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0024                                       :  1,
+                      __reserved_g_0023                                       :  1,
+                      __reserved_g_0048                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0026                                       :  1,
+                      __reserved_g_0025                                       :  1,
+                      __reserved_g_0050                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0028                                       :  1,
+                      __reserved_g_0027                                       :  1,
+                      reserved_22b                                            :  4;
+#endif
+};
+
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                        0x0000000000001000
+
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB                            13
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB                            16
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK                           0x000000000001e000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK                                0x0000000000020000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB                                       18
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB                                       20
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK                                      0x00000000001c0000
+
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB                              21
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB                              24
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK                             0x0000000001e00000
+
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB                                    25
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB                                    30
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK                                   0x000000007e000000
+
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB   32
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB   39
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK  0x000000ff00000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET       0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB          40
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB          45
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK         0x00003f0000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET          0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB             46
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB             47
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK            0x0000c00000000000
+
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB                               48
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB                               51
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK                              0x000f000000000000
+
+#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK                                       0x0010000000000000
+
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK                        0x0020000000000000
+
+#define TX_FES_STATUS_END_RESERVED_1A_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_1A_LSB                                           54
+#define TX_FES_STATUS_END_RESERVED_1A_MSB                                           58
+#define TX_FES_STATUS_END_RESERVED_1A_MASK                                          0x07c0000000000000
+
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK                             0x0800000000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                       0x1000000000000000
+
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                  0x2000000000000000
+
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK                                 0x8000000000000000
+
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB                                   1
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB                                   1
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK                                  0x0000000000000002
+
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB                                    2
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB                                    3
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK                                   0x000000000000000c
+
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB                                     4
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB                                     5
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK                                    0x0000000000000030
+
+#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET                                      0x0000000000000008
+#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB                                         6
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB                                         10
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK                                        0x00000000000007c0
+
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK                             0x0000000000000800
+
+#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_SERVICE_CBW_LSB                                           12
+#define TX_FES_STATUS_END_SERVICE_CBW_MSB                                           14
+#define TX_FES_STATUS_END_SERVICE_CBW_MASK                                          0x0000000000007000
+
+#define TX_FES_STATUS_END_RESERVED_2C_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_RESERVED_2C_LSB                                           21
+#define TX_FES_STATUS_END_RESERVED_2C_MSB                                           31
+#define TX_FES_STATUS_END_RESERVED_2C_MASK                                          0x00000000ffe00000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                   0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                      32
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                      47
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                     0x0000ffff00000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                     48
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                     63
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                    0xffff000000000000
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB                              0
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB                              7
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK                             0x00000000000000ff
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB                                 8
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB                                 15
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK                                0x000000000000ff00
+
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET                   0x0000000000000010
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB                      16
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB                      20
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK                     0x00000000001f0000
+
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK                                     0x0000000000200000
+
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK                             0x0000000000400000
+
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                      0x0000000000800000
+
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET                          0x0000000000000010
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK                            0x0000000001000000
+
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                      0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                        0x0000000002000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                  0x0000000000000010
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                     26
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                     30
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                    0x000000007c000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK                                       0x0000000080000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB                                        32
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB                                        47
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK                                       0x0000ffff00000000
+
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB                                 48
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB                                 63
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK                                0xffff000000000000
+
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB                                   0
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB                                   23
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK                                  0x0000000000ffffff
+
+#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET                                      0x0000000000000018
+#define TX_FES_STATUS_END_TXOP_DURATION_LSB                                         24
+#define TX_FES_STATUS_END_TXOP_DURATION_MSB                                         30
+#define TX_FES_STATUS_END_TXOP_DURATION_MASK                                        0x000000007f000000
+
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET                           0x0000000000000018
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK                             0x0000000080000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET                          0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB                             32
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB                             33
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK                            0x0000000300000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                     0x0000000400000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB                                      35
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB                                      37
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK                                     0x0000003800000000
+
+#define TX_FES_STATUS_END_FEC_TYPE_OFFSET                                           0x0000000000000018
+#define TX_FES_STATUS_END_FEC_TYPE_LSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MASK                                             0x0000004000000000
+
+#define TX_FES_STATUS_END_STBC_OFFSET                                               0x0000000000000018
+#define TX_FES_STATUS_END_STBC_LSB                                                  39
+#define TX_FES_STATUS_END_STBC_MSB                                                  39
+#define TX_FES_STATUS_END_STBC_MASK                                                 0x0000008000000000
+
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB                                      40
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB                                      55
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK                                     0x00ffff0000000000
+
+#define TX_FES_STATUS_END_RU_SIZE_OFFSET                                            0x0000000000000018
+#define TX_FES_STATUS_END_RU_SIZE_LSB                                               56
+#define TX_FES_STATUS_END_RU_SIZE_MSB                                               59
+#define TX_FES_STATUS_END_RU_SIZE_MASK                                              0x0f00000000000000
+
+#define TX_FES_STATUS_END_RESERVED_17A_OFFSET                                       0x0000000000000018
+#define TX_FES_STATUS_END_RESERVED_17A_LSB                                          60
+#define TX_FES_STATUS_END_RESERVED_17A_MSB                                          63
+#define TX_FES_STATUS_END_RESERVED_17A_MASK                                         0xf000000000000000
+
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB                                       0
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB                                       2
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK                                      0x0000000000000007
+
+#define TX_FES_STATUS_END_LTF_SIZE_OFFSET                                           0x0000000000000020
+#define TX_FES_STATUS_END_LTF_SIZE_LSB                                              3
+#define TX_FES_STATUS_END_LTF_SIZE_MSB                                              4
+#define TX_FES_STATUS_END_LTF_SIZE_MASK                                             0x0000000000000018
+
+#define TX_FES_STATUS_END_CP_SETTING_OFFSET                                         0x0000000000000020
+#define TX_FES_STATUS_END_CP_SETTING_LSB                                            5
+#define TX_FES_STATUS_END_CP_SETTING_MSB                                            6
+#define TX_FES_STATUS_END_CP_SETTING_MASK                                           0x0000000000000060
+
+#define TX_FES_STATUS_END_RESERVED_18A_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18A_LSB                                          7
+#define TX_FES_STATUS_END_RESERVED_18A_MSB                                          11
+#define TX_FES_STATUS_END_RESERVED_18A_MASK                                         0x0000000000000f80
+
+#define TX_FES_STATUS_END_DCM_OFFSET                                                0x0000000000000020
+#define TX_FES_STATUS_END_DCM_LSB                                                   12
+#define TX_FES_STATUS_END_DCM_MSB                                                   12
+#define TX_FES_STATUS_END_DCM_MASK                                                  0x0000000000001000
+
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET                                  0x0000000000000020
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK                                    0x0000000000002000
+
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET                                 0x0000000000000020
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK                                   0x0000000000004000
+
+#define TX_FES_STATUS_END_RESERVED_18B_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18B_LSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MASK                                         0x0000000000008000
+
+#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET                                      0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB                                         16
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB                                         23
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK                                        0x0000000000ff0000
+
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB                                       24
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB                                       31
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK                                      0x00000000ff000000
+
+#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET                                     0x0000000000000020
+#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB                                        56
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB                                        63
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK                                       0xff00000000000000
+
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB                                   0
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB                                   15
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_END_RESERVED_21A_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21A_LSB                                          16
+#define TX_FES_STATUS_END_RESERVED_21A_MSB                                          19
+#define TX_FES_STATUS_END_RESERVED_21A_MASK                                         0x00000000000f0000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET                                 0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB                                    20
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB                                    27
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK                                   0x000000000ff00000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET                          0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK                            0x0000000010000000
+
+#define TX_FES_STATUS_END_INTERFERENCE_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_INTERFERENCE_LSB                                          29
+#define TX_FES_STATUS_END_INTERFERENCE_MSB                                          29
+#define TX_FES_STATUS_END_INTERFERENCE_MASK                                         0x0000000020000000
+
+#define TX_FES_STATUS_END_RESERVED_21B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21B_LSB                                          30
+#define TX_FES_STATUS_END_RESERVED_21B_MSB                                          31
+#define TX_FES_STATUS_END_RESERVED_21B_MASK                                         0x00000000c0000000
+
+#define TX_FES_STATUS_END_RESERVED_22B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_22B_LSB                                          32
+#define TX_FES_STATUS_END_RESERVED_22B_MSB                                          35
+#define TX_FES_STATUS_END_RESERVED_22B_MASK                                         0x0000000f00000000
+
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET                              0x0000000000000028
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB                                 56
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB                                 63
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_prot.h b/hw/fig/v2/tx_fes_status_prot.h
new file mode 100644
index 000000000000..702cc1add940
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_prot.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_PROT_H_
+#define _TX_FES_STATUS_PROT_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2
+
+struct tx_fes_status_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t success                                                 :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      reserved_0                                              : 19,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5;
+             uint32_t frame_type                                              :  2,
+                      frame_subtype                                           :  4,
+                      rx_pwr_mgmt                                             :  1,
+                      status                                                  :  1,
+                      duration_field                                          : 16,
+                      reserved_1a                                             :  2,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_2a                                             : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      reserved_0                                              : 19,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      success                                                 :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      reserved_1a                                             :  2,
+                      duration_field                                          : 16,
+                      status                                                  :  1,
+                      rx_pwr_mgmt                                             :  1,
+                      frame_subtype                                           :  4,
+                      frame_type                                              :  2;
+             uint32_t reserved_2a                                             : 16;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_PROT_SUCCESS_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_SUCCESS_LSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MASK                                             0x0000000000000001
+
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK                            0x0000000000000002
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                      0x0000000000000004
+
+#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_0_LSB                                           3
+#define TX_FES_STATUS_PROT_RESERVED_0_MSB                                           21
+#define TX_FES_STATUS_PROT_RESERVED_0_MASK                                          0x00000000003ffff8
+
+#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PKT_TYPE_LSB                                             22
+#define TX_FES_STATUS_PROT_PKT_TYPE_MSB                                             25
+#define TX_FES_STATUS_PROT_PKT_TYPE_MASK                                            0x0000000003c00000
+
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK                                 0x0000000004000000
+
+#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_RATE_MCS_LSB                                             27
+#define TX_FES_STATUS_PROT_RATE_MCS_MSB                                             31
+#define TX_FES_STATUS_PROT_RATE_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB                                           32
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB                                           33
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK                                          0x0000000300000000
+
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB                                        34
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB                                        37
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK                                       0x0000003c00000000
+
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK                                         0x0000004000000000
+
+#define TX_FES_STATUS_PROT_STATUS_OFFSET                                            0x0000000000000000
+#define TX_FES_STATUS_PROT_STATUS_LSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MASK                                              0x0000008000000000
+
+#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB                                       40
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB                                       55
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK                                      0x00ffff0000000000
+
+#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_1A_LSB                                          56
+#define TX_FES_STATUS_PROT_RESERVED_1A_MSB                                          57
+#define TX_FES_STATUS_PROT_RESERVED_1A_MASK                                         0x0300000000000000
+
+#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_AGC_CBW_LSB                                              58
+#define TX_FES_STATUS_PROT_AGC_CBW_MSB                                              60
+#define TX_FES_STATUS_PROT_AGC_CBW_MASK                                             0x1c00000000000000
+
+#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB                                          61
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB                                          63
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK                                         0xe000000000000000
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB  0
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB  7
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET      0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB         8
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB         13
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK        0x0000000000003f00
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET         0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB            14
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB            15
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK           0x000000000000c000
+
+#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET                                       0x0000000000000008
+#define TX_FES_STATUS_PROT_RESERVED_2A_LSB                                          16
+#define TX_FES_STATUS_PROT_RESERVED_2A_MSB                                          31
+#define TX_FES_STATUS_PROT_RESERVED_2A_MASK                                         0x00000000ffff0000
+
+#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB                                        32
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB                                        63
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_start.h b/hw/fig/v2/tx_fes_status_start.h
new file mode 100644
index 000000000000..bc8e06ec59fb
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_start.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_H_
+#define _TX_FES_STATUS_START_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START 2
+
+struct tx_fes_status_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1a                                             :  8,
+                      transmit_start_reason                                   :  3,
+                      disabled_user_bitmap_36_32                              :  5,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      schedule_try                                            :  4,
+                      medium_prot_type                                        :  3,
+                      reserved_1b                                             :  2;
+             uint32_t optimal_bw_try_count                                    :  4,
+                      number_of_users                                         :  7,
+                      coex_nack_count                                         :  5,
+                      cca_ed0                                                 : 16;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1b                                             :  2,
+                      medium_prot_type                                        :  3,
+                      schedule_try                                            :  4,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      disabled_user_bitmap_36_32                              :  5,
+                      transmit_start_reason                                   :  3,
+                      reserved_1a                                             :  8;
+             uint32_t cca_ed0                                                 : 16,
+                      coex_nack_count                                         :  5,
+                      number_of_users                                         :  7,
+                      optimal_bw_try_count                                    :  4;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_ID_LSB                                         0
+#define TX_FES_STATUS_START_SCHEDULE_ID_MSB                                         31
+#define TX_FES_STATUS_START_SCHEDULE_ID_MASK                                        0x00000000ffffffff
+
+#define TX_FES_STATUS_START_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1A_LSB                                         32
+#define TX_FES_STATUS_START_RESERVED_1A_MSB                                         39
+#define TX_FES_STATUS_START_RESERVED_1A_MASK                                        0x000000ff00000000
+
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB                               40
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB                               42
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK                              0x0000070000000000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB                          43
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB                          47
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK                         0x0000f80000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB                                48
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB                                52
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK                               0x001f000000000000
+
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB                                    53
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB                                    54
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK                                   0x0060000000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB                                        55
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB                                        58
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK                                       0x0780000000000000
+
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB                                    59
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB                                    61
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK                                   0x3800000000000000
+
+#define TX_FES_STATUS_START_RESERVED_1B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1B_LSB                                         62
+#define TX_FES_STATUS_START_RESERVED_1B_MSB                                         63
+#define TX_FES_STATUS_START_RESERVED_1B_MASK                                        0xc000000000000000
+
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET                             0x0000000000000008
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB                                0
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB                                3
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK                               0x000000000000000f
+
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB                                     4
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB                                     10
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK                                    0x00000000000007f0
+
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB                                     11
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB                                     15
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK                                    0x000000000000f800
+
+#define TX_FES_STATUS_START_CCA_ED0_OFFSET                                          0x0000000000000008
+#define TX_FES_STATUS_START_CCA_ED0_LSB                                             16
+#define TX_FES_STATUS_START_CCA_ED0_MSB                                             31
+#define TX_FES_STATUS_START_CCA_ED0_MASK                                            0x00000000ffff0000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB                           32
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB                           63
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK                          0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_start_ppdu.h b/hw/fig/v2/tx_fes_status_start_ppdu.h
new file mode 100644
index 000000000000..a87b3b0a0ccc
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_start_ppdu.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PPDU_H_
+#define _TX_FES_STATUS_START_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3
+
+struct tx_fes_status_start_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      ndp_frame                                               :  3,
+                      reserved_2b                                             :  1,
+                      coex_based_tx_bw                                        :  3,
+                      coex_based_ant_mask                                     :  8,
+                      reserved_2c                                             :  1;
+             uint32_t coex_based_tx_pwr_shared_ant                            :  8,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      concurrent_bt_tx                                        :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wan_rx                                       :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_result_alt_based                                   :  1,
+                      request_packet_bw                                       :  3,
+                      response_type                                           :  5;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t reserved_2c                                             :  1,
+                      coex_based_ant_mask                                     :  8,
+                      coex_based_tx_bw                                        :  3,
+                      reserved_2b                                             :  1,
+                      ndp_frame                                               :  3,
+                      subband_mask                                            : 16;
+             uint32_t response_type                                           :  5,
+                      request_packet_bw                                       :  3,
+                      coex_result_alt_based                                   :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      concurrent_wan_rx                                       :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_bt_tx                                        :  1,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      coex_based_tx_pwr_shared_ant                            :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB                                      16
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB                                      18
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK                                     0x0000000000070000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK                                   0x0000000000080000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB                               20
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB                               22
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK                              0x0000000000700000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET                         0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB                            23
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB                            30
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK                           0x000000007f800000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB                   32
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB                   39
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK                  0x000000ff00000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB                          40
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB                          47
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK                         0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK                              0x0001000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK                            0x0002000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK                             0x0004000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK                             0x0008000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK                         0x0010000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK                       0x0020000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK                        0x0040000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK                         0x0080000000000000
+
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB                              56
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB                              58
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK                             0x0700000000000000
+
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB                                  59
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK                                 0xf800000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_start_prot.h b/hw/fig/v2/tx_fes_status_start_prot.h
new file mode 100644
index 000000000000..aca9ac5eb28b
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_start_prot.h
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PROT_H_
+#define _TX_FES_STATUS_START_PROT_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3
+
+struct tx_fes_status_start_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      reserved_2b                                             :  4,
+                      prot_coex_based_tx_bw                                   :  3,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_result_alt_based                              :  1;
+             uint32_t prot_coex_tx_pwr_shared_ant                             :  8,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_request_packet_bw                                  :  3,
+                      response_type                                           :  5,
+                      reserved_3a                                             :  1;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t prot_coex_result_alt_based                              :  1,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_based_tx_bw                                   :  3,
+                      reserved_2b                                             :  4,
+                      subband_mask                                            : 16;
+             uint32_t reserved_3a                                             :  1,
+                      response_type                                           :  5,
+                      prot_request_packet_bw                                  :  3,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_coex_tx_pwr_shared_ant                             :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB                                    16
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK                                   0x00000000000f0000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB                          20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB                          22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK                         0x0000000000700000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET                    0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB                       23
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB                       30
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK                      0x000000007f800000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK                    0x0000000080000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB                    32
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB                    39
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK                   0x000000ff00000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB                           40
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB                           47
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK                          0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK                         0x0001000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK                       0x0002000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK                        0x0004000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK                        0x0008000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK                    0x0010000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK                  0x0020000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK                   0x0040000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB                         55
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB                         57
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK                        0x0380000000000000
+
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB                                  58
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB                                  62
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK                                 0x7c00000000000000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK                                   0x8000000000000000
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_user_ppdu.h b/hw/fig/v2/tx_fes_status_user_ppdu.h
new file mode 100644
index 000000000000..dad9a040ff46
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_user_ppdu.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_PPDU_H_
+#define _TX_FES_STATUS_USER_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3
+
+struct tx_fes_status_user_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      bw_drop_underflow_warning                               :  1,
+                      qc_eosp_setting                                         :  1,
+                      mpdu_tx_count                                           : 11,
+                      user_blocked                                            :  1,
+                      pre_trig_response_delim_count                           :  7;
+             uint32_t underflow_byte_count                                    : 16,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      coex_abort_mpdu_count                                   :  9,
+                      transmitted_tid                                         :  4,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      cv_corr_user_valid_in_phy                               :  1;
+             uint32_t duration                                                : 16,
+                      num_eof_delim_added                                     : 16;
+             uint32_t psdu_octet                                              : 24,
+                      qos_buf_state                                           :  8;
+             uint32_t num_null_delim_added                                    : 22,
+                      fc_more_data_setting                                    :  1,
+                      fc_pwr_mgt_setting                                      :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5;
+             uint32_t ht_control                                              : 32;
+#else
+             uint32_t pre_trig_response_delim_count                           :  7,
+                      user_blocked                                            :  1,
+                      mpdu_tx_count                                           : 11,
+                      qc_eosp_setting                                         :  1,
+                      bw_drop_underflow_warning                               :  1,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t cv_corr_user_valid_in_phy                               :  1,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      transmitted_tid                                         :  4,
+                      coex_abort_mpdu_count                                   :  9,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      underflow_byte_count                                    : 16;
+             uint32_t num_eof_delim_added                                     : 16,
+                      duration                                                : 16;
+             uint32_t qos_buf_state                                           :  8,
+                      psdu_octet                                              : 24;
+             uint32_t mcs                                                     :  5,
+                      nss                                                     :  3,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  1,
+                      num_null_delim_added                                    : 22;
+             uint32_t ht_control                                              : 32;
+#endif
+};
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB                            8
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK                           0x00000000000001ff
+
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB                          9
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB                          10
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK                         0x0000000000000600
+
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK                                0x0000000000001000
+
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET                                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB                                   13
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB                                   23
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK                                  0x0000000000ffe000
+
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK                                   0x0000000001000000
+
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB                   25
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB                   31
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK                  0x00000000fe000000
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB                            32
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB                            47
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK                           0x0000ffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK                    0x0001000000000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET                        0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB                           49
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB                           57
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK                          0x03fe000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB                                 58
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB                                 61
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK                                0x3c00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK                      0x8000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_DURATION_LSB                                        0
+#define TX_FES_STATUS_USER_PPDU_DURATION_MSB                                        15
+#define TX_FES_STATUS_USER_PPDU_DURATION_MASK                                       0x000000000000ffff
+
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB                             16
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB                             31
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK                            0x00000000ffff0000
+
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB                                      55
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK                                     0x00ffffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB                                   56
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB                                   63
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK                                  0xff00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB                            21
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK                           0x00000000003fffff
+
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK                           0x0000000000400000
+
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK                             0x0000000000800000
+
+#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NSS_LSB                                             24
+#define TX_FES_STATUS_USER_PPDU_NSS_MSB                                             26
+#define TX_FES_STATUS_USER_PPDU_NSS_MASK                                            0x0000000007000000
+
+#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_MCS_LSB                                             27
+#define TX_FES_STATUS_USER_PPDU_MCS_MSB                                             31
+#define TX_FES_STATUS_USER_PPDU_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB                                      63
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_fes_status_user_response.h b/hw/fig/v2/tx_fes_status_user_response.h
new file mode 100644
index 000000000000..dea7df35887f
--- /dev/null
+++ b/hw/fig/v2/tx_fes_status_user_response.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
+#define _TX_FES_STATUS_USER_RESPONSE_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1
+
+struct tx_fes_status_user_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fes_transmit_result                                     :  4,
+                      reserved_0                                              : 23,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mic_overwritten                                         :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t pre_padding_fcs_overwritten                             :  1,
+                      reserved_after_struct16                                 : 15;
+#else
+             uint32_t mic_overwritten                                         :  1,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      reserved_0                                              : 23,
+                      fes_transmit_result                                     :  4;
+             uint32_t reserved_after_struct16                                 : 15,
+                      pre_padding_fcs_overwritten                             :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB                         0
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB                         3
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK                        0x000000000000000f
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB                                  4
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB                                  26
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK                                 0x0000000007fffff0
+
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET       0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB          27
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB          30
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK         0x0000000078000000
+
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET                          0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB                             31
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB                             31
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK                            0x0000000080000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB   46
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB   47
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK  0x0000c00000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET              0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK                0x0001000000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB                     49
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB                     63
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK                    0xfffe000000000000
+
+#endif
diff --git a/hw/fig/v2/tx_flush_req.h b/hw/fig/v2/tx_flush_req.h
new file mode 100644
index 000000000000..af502ec619eb
--- /dev/null
+++ b/hw/fig/v2/tx_flush_req.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FLUSH_REQ_H_
+#define _TX_FLUSH_REQ_H_
+
+#define NUM_OF_DWORDS_TX_FLUSH_REQ 2
+
+#define NUM_OF_QWORDS_TX_FLUSH_REQ 1
+
+struct tx_flush_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t flush_req_reason                                        :  8,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_user_number_or_link_id                        :  6,
+                      mlo_abort_reason                                        :  5,
+                      reserved_0a                                             :  5;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      mlo_abort_reason                                        :  5,
+                      flush_req_user_number_or_link_id                        :  6,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_reason                                        :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB                                           0
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB                                           7
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK                                          0x00000000000000ff
+
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET                                      0x0000000000000000
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB                                         8
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB                                         15
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK                                        0x000000000000ff00
+
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB                           16
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB                           21
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK                          0x00000000003f0000
+
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB                                           22
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB                                           26
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK                                          0x0000000007c00000
+
+#define TX_FLUSH_REQ_RESERVED_0A_OFFSET                                             0x0000000000000000
+#define TX_FLUSH_REQ_RESERVED_0A_LSB                                                27
+#define TX_FLUSH_REQ_RESERVED_0A_MSB                                                31
+#define TX_FLUSH_REQ_RESERVED_0A_MASK                                               0x00000000f8000000
+
+#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET                                           0x0000000000000000
+#define TX_FLUSH_REQ_TLV64_PADDING_LSB                                              32
+#define TX_FLUSH_REQ_TLV64_PADDING_MSB                                              63
+#define TX_FLUSH_REQ_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_mpdu_start.h b/hw/fig/v2/tx_mpdu_start.h
new file mode 100644
index 000000000000..1a0c370d2963
--- /dev/null
+++ b/hw/fig/v2/tx_mpdu_start.h
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MPDU_START_H_
+#define _TX_MPDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MPDU_START 10
+
+#define NUM_OF_QWORDS_TX_MPDU_START 5
+
+struct tx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_length                                             : 14,
+                      frame_not_from_tqm                                      :  1,
+                      vht_control_present                                     :  1,
+                      mpdu_header_length                                      :  8,
+                      retry_count                                             :  7,
+                      wds                                                     :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      mpdu_sequence_number                                    : 12,
+                      raw_already_encrypted                                   :  1,
+                      frame_type                                              :  2,
+                      txdma_dropped_mpdu_warning                              :  1;
+             uint32_t iv_byte_0                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_3                                               :  8;
+             uint32_t iv_byte_4                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_7                                               :  8;
+             uint32_t iv_byte_8                                               :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_11                                              :  8;
+             uint32_t iv_byte_12                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_15                                              :  8;
+             uint32_t iv_byte_16                                              :  8,
+                      iv_byte_17                                              :  8,
+                      iv_len                                                  :  5,
+                      icv_len                                                 :  5,
+                      vht_control_offset                                      :  6;
+             uint32_t mpdu_type                                               :  1,
+                      transmit_bw_restriction                                 :  1,
+                      allowed_transmit_bw                                     :  4,
+                      tx_notify_frame                                         :  3,
+                      frame_subtype                                           :  4,
+                      reserved_8a                                             : 19;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t wds                                                     :  1,
+                      retry_count                                             :  7,
+                      mpdu_header_length                                      :  8,
+                      vht_control_present                                     :  1,
+                      frame_not_from_tqm                                      :  1,
+                      mpdu_length                                             : 14;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t txdma_dropped_mpdu_warning                              :  1,
+                      frame_type                                              :  2,
+                      raw_already_encrypted                                   :  1,
+                      mpdu_sequence_number                                    : 12,
+                      pn_47_32                                                : 16;
+             uint32_t iv_byte_3                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_0                                               :  8;
+             uint32_t iv_byte_7                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_4                                               :  8;
+             uint32_t iv_byte_11                                              :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_8                                               :  8;
+             uint32_t iv_byte_15                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_12                                              :  8;
+             uint32_t vht_control_offset                                      :  6,
+                      icv_len                                                 :  5,
+                      iv_len                                                  :  5,
+                      iv_byte_17                                              :  8,
+                      iv_byte_16                                              :  8;
+             uint32_t reserved_8a                                             : 19,
+                      frame_subtype                                           :  4,
+                      tx_notify_frame                                         :  3,
+                      allowed_transmit_bw                                     :  4,
+                      transmit_bw_restriction                                 :  1,
+                      mpdu_type                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MPDU_START_MPDU_LENGTH_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_MPDU_LENGTH_LSB                                               0
+#define TX_MPDU_START_MPDU_LENGTH_MSB                                               13
+#define TX_MPDU_START_MPDU_LENGTH_MASK                                              0x0000000000003fff
+
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK                                       0x0000000000004000
+
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET                                    0x0000000000000000
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK                                      0x0000000000008000
+
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB                                        16
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB                                        23
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK                                       0x0000000000ff0000
+
+#define TX_MPDU_START_RETRY_COUNT_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_RETRY_COUNT_LSB                                               24
+#define TX_MPDU_START_RETRY_COUNT_MSB                                               30
+#define TX_MPDU_START_RETRY_COUNT_MASK                                              0x000000007f000000
+
+#define TX_MPDU_START_WDS_OFFSET                                                    0x0000000000000000
+#define TX_MPDU_START_WDS_LSB                                                       31
+#define TX_MPDU_START_WDS_MSB                                                       31
+#define TX_MPDU_START_WDS_MASK                                                      0x0000000080000000
+
+#define TX_MPDU_START_PN_31_0_OFFSET                                                0x0000000000000000
+#define TX_MPDU_START_PN_31_0_LSB                                                   32
+#define TX_MPDU_START_PN_31_0_MSB                                                   63
+#define TX_MPDU_START_PN_31_0_MASK                                                  0xffffffff00000000
+
+#define TX_MPDU_START_PN_47_32_OFFSET                                               0x0000000000000008
+#define TX_MPDU_START_PN_47_32_LSB                                                  0
+#define TX_MPDU_START_PN_47_32_MSB                                                  15
+#define TX_MPDU_START_PN_47_32_MASK                                                 0x000000000000ffff
+
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET                                   0x0000000000000008
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB                                      16
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB                                      27
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK                                     0x000000000fff0000
+
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET                                  0x0000000000000008
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK                                    0x0000000010000000
+
+#define TX_MPDU_START_FRAME_TYPE_OFFSET                                             0x0000000000000008
+#define TX_MPDU_START_FRAME_TYPE_LSB                                                29
+#define TX_MPDU_START_FRAME_TYPE_MSB                                                30
+#define TX_MPDU_START_FRAME_TYPE_MASK                                               0x0000000060000000
+
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET                             0x0000000000000008
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK                               0x0000000080000000
+
+#define TX_MPDU_START_IV_BYTE_0_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_0_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_0_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_0_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_1_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_1_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_1_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_1_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_2_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_2_LSB                                                 48
+#define TX_MPDU_START_IV_BYTE_2_MSB                                                 55
+#define TX_MPDU_START_IV_BYTE_2_MASK                                                0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_3_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_3_LSB                                                 56
+#define TX_MPDU_START_IV_BYTE_3_MSB                                                 63
+#define TX_MPDU_START_IV_BYTE_3_MASK                                                0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_4_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_4_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_4_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_4_MASK                                                0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_5_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_5_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_5_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_5_MASK                                                0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_6_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_6_LSB                                                 16
+#define TX_MPDU_START_IV_BYTE_6_MSB                                                 23
+#define TX_MPDU_START_IV_BYTE_6_MASK                                                0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_7_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_7_LSB                                                 24
+#define TX_MPDU_START_IV_BYTE_7_MSB                                                 31
+#define TX_MPDU_START_IV_BYTE_7_MASK                                                0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_8_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_8_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_8_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_8_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_9_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_9_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_9_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_9_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_10_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_10_LSB                                                48
+#define TX_MPDU_START_IV_BYTE_10_MSB                                                55
+#define TX_MPDU_START_IV_BYTE_10_MASK                                               0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_11_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_11_LSB                                                56
+#define TX_MPDU_START_IV_BYTE_11_MSB                                                63
+#define TX_MPDU_START_IV_BYTE_11_MASK                                               0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_12_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_12_LSB                                                0
+#define TX_MPDU_START_IV_BYTE_12_MSB                                                7
+#define TX_MPDU_START_IV_BYTE_12_MASK                                               0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_13_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_13_LSB                                                8
+#define TX_MPDU_START_IV_BYTE_13_MSB                                                15
+#define TX_MPDU_START_IV_BYTE_13_MASK                                               0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_14_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_14_LSB                                                16
+#define TX_MPDU_START_IV_BYTE_14_MSB                                                23
+#define TX_MPDU_START_IV_BYTE_14_MASK                                               0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_15_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_15_LSB                                                24
+#define TX_MPDU_START_IV_BYTE_15_MSB                                                31
+#define TX_MPDU_START_IV_BYTE_15_MASK                                               0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_16_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_16_LSB                                                32
+#define TX_MPDU_START_IV_BYTE_16_MSB                                                39
+#define TX_MPDU_START_IV_BYTE_16_MASK                                               0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_17_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_17_LSB                                                40
+#define TX_MPDU_START_IV_BYTE_17_MSB                                                47
+#define TX_MPDU_START_IV_BYTE_17_MASK                                               0x0000ff0000000000
+
+#define TX_MPDU_START_IV_LEN_OFFSET                                                 0x0000000000000018
+#define TX_MPDU_START_IV_LEN_LSB                                                    48
+#define TX_MPDU_START_IV_LEN_MSB                                                    52
+#define TX_MPDU_START_IV_LEN_MASK                                                   0x001f000000000000
+
+#define TX_MPDU_START_ICV_LEN_OFFSET                                                0x0000000000000018
+#define TX_MPDU_START_ICV_LEN_LSB                                                   53
+#define TX_MPDU_START_ICV_LEN_MSB                                                   57
+#define TX_MPDU_START_ICV_LEN_MASK                                                  0x03e0000000000000
+
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET                                     0x0000000000000018
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB                                        58
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB                                        63
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK                                       0xfc00000000000000
+
+#define TX_MPDU_START_MPDU_TYPE_OFFSET                                              0x0000000000000020
+#define TX_MPDU_START_MPDU_TYPE_LSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MASK                                                0x0000000000000001
+
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET                                0x0000000000000020
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK                                  0x0000000000000002
+
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET                                    0x0000000000000020
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB                                       2
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB                                       5
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK                                      0x000000000000003c
+
+#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET                                        0x0000000000000020
+#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB                                           6
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB                                           8
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK                                          0x00000000000001c0
+
+#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET                                          0x0000000000000020
+#define TX_MPDU_START_FRAME_SUBTYPE_LSB                                             9
+#define TX_MPDU_START_FRAME_SUBTYPE_MSB                                             12
+#define TX_MPDU_START_FRAME_SUBTYPE_MASK                                            0x0000000000001e00
+
+#define TX_MPDU_START_RESERVED_8A_OFFSET                                            0x0000000000000020
+#define TX_MPDU_START_RESERVED_8A_LSB                                               13
+#define TX_MPDU_START_RESERVED_8A_MSB                                               31
+#define TX_MPDU_START_RESERVED_8A_MASK                                              0x00000000ffffe000
+
+#define TX_MPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000020
+#define TX_MPDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MPDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_msdu_extension.h b/hw/fig/v2/tx_msdu_extension.h
new file mode 100644
index 000000000000..f8da5593497b
--- /dev/null
+++ b/hw/fig/v2/tx_msdu_extension.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tso_enable                                              :  1,
+                      reserved_0a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      reserved_0b                                             :  7;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      udp_length                                              : 16;
+             uint32_t checksum_offset                                         : 14,
+                      partial_checksum_en                                     :  1,
+                      reserved_4a                                             :  1,
+                      payload_start_offset                                    : 14,
+                      reserved_4b                                             :  2;
+             uint32_t payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      wds                                                     :  1,
+                      reserved_5b                                             : 15;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_ptr_39_32                                          :  8,
+                      reserved_7a                                             :  8,
+                      buf0_len                                                : 16;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_ptr_39_32                                          :  8,
+                      reserved_9a                                             :  8,
+                      buf1_len                                                : 16;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_ptr_39_32                                          :  8,
+                      reserved_11a                                            :  8,
+                      buf2_len                                                : 16;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_ptr_39_32                                          :  8,
+                      reserved_13a                                            :  8,
+                      buf3_len                                                : 16;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_ptr_39_32                                          :  8,
+                      reserved_15a                                            :  8,
+                      buf4_len                                                : 16;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_ptr_39_32                                          :  8,
+                      reserved_17a                                            :  8,
+                      buf5_len                                                : 16;
+#else
+             uint32_t reserved_0b                                             :  7,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_0a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t udp_length                                              : 16,
+                      ip_identification                                       : 16;
+             uint32_t reserved_4b                                             :  2,
+                      payload_start_offset                                    : 14,
+                      reserved_4a                                             :  1,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 14;
+             uint32_t reserved_5b                                             : 15,
+                      wds                                                     :  1,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_len                                                : 16,
+                      reserved_7a                                             :  8,
+                      buf0_ptr_39_32                                          :  8;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_len                                                : 16,
+                      reserved_9a                                             :  8,
+                      buf1_ptr_39_32                                          :  8;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_len                                                : 16,
+                      reserved_11a                                            :  8,
+                      buf2_ptr_39_32                                          :  8;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_len                                                : 16,
+                      reserved_13a                                            :  8,
+                      buf3_ptr_39_32                                          :  8;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_len                                                : 16,
+                      reserved_15a                                            :  8,
+                      buf4_ptr_39_32                                          :  8;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_len                                                : 16,
+                      reserved_17a                                            :  8,
+                      buf5_ptr_39_32                                          :  8;
+#endif
+};
+
+#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
+#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
+
+#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
+#define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
+#define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
+#define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
+#define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
+
+#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
+#define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
+#define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
+
+#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
+#define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
+#define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
+
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
+
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
+
+#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
+#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
+
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
+
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
+
+#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
+#define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
+
+#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
+#define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
+
+#define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
+#define TX_MSDU_EXTENSION_WDS_LSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
+
+#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
+#define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET                                        0x0000001c
+#define TX_MSDU_EXTENSION_RESERVED_7A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_7A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_7A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
+#define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
+#define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
+#define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
+#define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
+#define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
+#define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
+#define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
+#define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
+
+#endif
diff --git a/hw/fig/v2/tx_msdu_start.h b/hw/fig/v2/tx_msdu_start.h
new file mode 100644
index 000000000000..e62a76009f3a
--- /dev/null
+++ b/hw/fig/v2/tx_msdu_start.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_START_H_
+#define _TX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_START 8
+
+#define NUM_OF_QWORDS_TX_MSDU_START 4
+
+struct tx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_len                                                : 14,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      encap_type                                              :  2,
+                      epd_en                                                  :  1,
+                      da_sa_present                                           :  2,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      dummy_msdu_delimitation                                 :  1,
+                      reserved_0a                                             :  5;
+             uint32_t tso_enable                                              :  1,
+                      reserved_1a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      mesh_enable                                             :  1,
+                      reserved_1b                                             :  6;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      checksum_offset                                         : 13,
+                      partial_checksum_en                                     :  1,
+                      reserved_4                                              :  2;
+             uint32_t payload_start_offset                                    : 14,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5b                                             :  2;
+             uint32_t udp_length                                              : 16,
+                      reserved_6                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      dummy_msdu_delimitation                                 :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      da_sa_present                                           :  2,
+                      epd_en                                                  :  1,
+                      encap_type                                              :  2,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      msdu_len                                                : 14;
+             uint32_t reserved_1b                                             :  6,
+                      mesh_enable                                             :  1,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_1a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t reserved_4                                              :  2,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 13,
+                      ip_identification                                       : 16;
+             uint32_t reserved_5b                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      payload_start_offset                                    : 14;
+             uint32_t reserved_6                                              : 16,
+                      udp_length                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MSDU_START_MSDU_LEN_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_MSDU_LEN_LSB                                                  0
+#define TX_MSDU_START_MSDU_LEN_MSB                                                  13
+#define TX_MSDU_START_MSDU_LEN_MASK                                                 0x0000000000003fff
+
+#define TX_MSDU_START_FIRST_MSDU_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_FIRST_MSDU_LSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MASK                                               0x0000000000004000
+
+#define TX_MSDU_START_LAST_MSDU_OFFSET                                              0x0000000000000000
+#define TX_MSDU_START_LAST_MSDU_LSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MASK                                                0x0000000000008000
+
+#define TX_MSDU_START_ENCAP_TYPE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_ENCAP_TYPE_LSB                                                16
+#define TX_MSDU_START_ENCAP_TYPE_MSB                                                17
+#define TX_MSDU_START_ENCAP_TYPE_MASK                                               0x0000000000030000
+
+#define TX_MSDU_START_EPD_EN_OFFSET                                                 0x0000000000000000
+#define TX_MSDU_START_EPD_EN_LSB                                                    18
+#define TX_MSDU_START_EPD_EN_MSB                                                    18
+#define TX_MSDU_START_EPD_EN_MASK                                                   0x0000000000040000
+
+#define TX_MSDU_START_DA_SA_PRESENT_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_DA_SA_PRESENT_LSB                                             19
+#define TX_MSDU_START_DA_SA_PRESENT_MSB                                             20
+#define TX_MSDU_START_DA_SA_PRESENT_MASK                                            0x0000000000180000
+
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET                                       0x0000000000000000
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK                                         0x0000000000200000
+
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000000400000
+
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000000800000
+
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000001000000
+
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000002000000
+
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET                                0x0000000000000000
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK                                  0x0000000004000000
+
+#define TX_MSDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_0A_LSB                                               27
+#define TX_MSDU_START_RESERVED_0A_MSB                                               31
+#define TX_MSDU_START_RESERVED_0A_MASK                                              0x00000000f8000000
+
+#define TX_MSDU_START_TSO_ENABLE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_TSO_ENABLE_LSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MASK                                               0x0000000100000000
+
+#define TX_MSDU_START_RESERVED_1A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1A_LSB                                               33
+#define TX_MSDU_START_RESERVED_1A_MSB                                               38
+#define TX_MSDU_START_RESERVED_1A_MASK                                              0x0000007e00000000
+
+#define TX_MSDU_START_TCP_FLAG_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_LSB                                                  39
+#define TX_MSDU_START_TCP_FLAG_MSB                                                  47
+#define TX_MSDU_START_TCP_FLAG_MASK                                                 0x0000ff8000000000
+
+#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_MASK_LSB                                             48
+#define TX_MSDU_START_TCP_FLAG_MASK_MSB                                             56
+#define TX_MSDU_START_TCP_FLAG_MASK_MASK                                            0x01ff000000000000
+
+#define TX_MSDU_START_MESH_ENABLE_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_MESH_ENABLE_LSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MASK                                              0x0200000000000000
+
+#define TX_MSDU_START_RESERVED_1B_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1B_LSB                                               58
+#define TX_MSDU_START_RESERVED_1B_MSB                                               63
+#define TX_MSDU_START_RESERVED_1B_MASK                                              0xfc00000000000000
+
+#define TX_MSDU_START_L2_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_L2_LENGTH_LSB                                                 0
+#define TX_MSDU_START_L2_LENGTH_MSB                                                 15
+#define TX_MSDU_START_L2_LENGTH_MASK                                                0x000000000000ffff
+
+#define TX_MSDU_START_IP_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_IP_LENGTH_LSB                                                 16
+#define TX_MSDU_START_IP_LENGTH_MSB                                                 31
+#define TX_MSDU_START_IP_LENGTH_MASK                                                0x00000000ffff0000
+
+#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET                                         0x0000000000000008
+#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB                                            32
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB                                            63
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK                                           0xffffffff00000000
+
+#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET                                      0x0000000000000010
+#define TX_MSDU_START_IP_IDENTIFICATION_LSB                                         0
+#define TX_MSDU_START_IP_IDENTIFICATION_MSB                                         15
+#define TX_MSDU_START_IP_IDENTIFICATION_MASK                                        0x000000000000ffff
+
+#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET                                        0x0000000000000010
+#define TX_MSDU_START_CHECKSUM_OFFSET_LSB                                           16
+#define TX_MSDU_START_CHECKSUM_OFFSET_MSB                                           28
+#define TX_MSDU_START_CHECKSUM_OFFSET_MASK                                          0x000000001fff0000
+
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET                                    0x0000000000000010
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK                                      0x0000000020000000
+
+#define TX_MSDU_START_RESERVED_4_OFFSET                                             0x0000000000000010
+#define TX_MSDU_START_RESERVED_4_LSB                                                30
+#define TX_MSDU_START_RESERVED_4_MSB                                                31
+#define TX_MSDU_START_RESERVED_4_MASK                                               0x00000000c0000000
+
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET                                   0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB                                      32
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB                                      45
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK                                     0x00003fff00000000
+
+#define TX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5A_LSB                                               46
+#define TX_MSDU_START_RESERVED_5A_MSB                                               47
+#define TX_MSDU_START_RESERVED_5A_MASK                                              0x0000c00000000000
+
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET                                     0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB                                        48
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB                                        61
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK                                       0x3fff000000000000
+
+#define TX_MSDU_START_RESERVED_5B_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5B_LSB                                               62
+#define TX_MSDU_START_RESERVED_5B_MSB                                               63
+#define TX_MSDU_START_RESERVED_5B_MASK                                              0xc000000000000000
+
+#define TX_MSDU_START_UDP_LENGTH_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_UDP_LENGTH_LSB                                                0
+#define TX_MSDU_START_UDP_LENGTH_MSB                                                15
+#define TX_MSDU_START_UDP_LENGTH_MASK                                               0x000000000000ffff
+
+#define TX_MSDU_START_RESERVED_6_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_RESERVED_6_LSB                                                16
+#define TX_MSDU_START_RESERVED_6_MSB                                                31
+#define TX_MSDU_START_RESERVED_6_MASK                                               0x00000000ffff0000
+
+#define TX_MSDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000018
+#define TX_MSDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MSDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MSDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_peer_entry.h b/hw/fig/v2/tx_peer_entry.h
new file mode 100644
index 000000000000..c26c7f6a3e05
--- /dev/null
+++ b/hw/fig/v2/tx_peer_entry.h
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_PEER_ENTRY_H_
+#define _TX_PEER_ENTRY_H_
+
+#define NUM_OF_DWORDS_TX_PEER_ENTRY 22
+
+#define NUM_OF_QWORDS_TX_PEER_ENTRY 11
+
+struct tx_peer_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_a_47_32                                        : 16,
+                      mac_addr_b_15_0                                         : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t use_ad_b                                                :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      vlan_llc_mode                                           :  1,
+                      key_type                                                :  4,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      ignore_hard_filters                                     :  1,
+                      ignore_soft_filters                                     :  1,
+                      epd_output                                              :  1,
+                      wds                                                     :  1,
+                      insert_or_strip                                         :  1,
+                      sw_filter_id                                            : 16;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t sta_partial_aid                                         : 11,
+                      transmit_vif                                            :  4,
+                      block_this_user                                         :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      use_qos_alt_mute_mask                                   :  1,
+                      dl_ul_direction                                         :  1,
+                      use_ad_c                                                :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      multi_link_addr_ad3_valid                               :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      reserved_12                                             :  1;
+             uint32_t insert_vlan_outer_tci                                   : 16,
+                      insert_vlan_inner_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t multi_link_addr_crypto_enable                           :  1,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      reserved_17a                                            :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t mac_addr_c_47_32                                        : 16,
+                      multi_link_addr_ad3_47_32                               : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_b_15_0                                         : 16,
+                      mac_addr_a_47_32                                        : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t sw_filter_id                                            : 16,
+                      insert_or_strip                                         :  1,
+                      wds                                                     :  1,
+                      epd_output                                              :  1,
+                      ignore_soft_filters                                     :  1,
+                      ignore_hard_filters                                     :  1,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      key_type                                                :  4,
+                      vlan_llc_mode                                           :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      use_ad_b                                                :  1;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t reserved_12                                             :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_ad3_valid                               :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      use_ad_c                                                :  1,
+                      dl_ul_direction                                         :  1,
+                      use_qos_alt_mute_mask                                   :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      block_this_user                                         :  1,
+                      transmit_vif                                            :  4,
+                      sta_partial_aid                                         : 11;
+             uint32_t insert_vlan_inner_tci                                   : 16,
+                      insert_vlan_outer_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_17a                                            :  9,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      multi_link_addr_crypto_enable                           :  1;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t multi_link_addr_ad3_47_32                               : 16,
+                      mac_addr_c_47_32                                        : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET                                       0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB                                           48
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB                                           63
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK                                          0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET                                       0x0000000000000008
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB                                          0
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB                                          31
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK                                         0x00000000ffffffff
+
+#define TX_PEER_ENTRY_USE_AD_B_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_USE_AD_B_LSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MASK                                                 0x0000000100000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK                                  0x0000000200000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK                                  0x0000000400000000
+
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET                                          0x0000000000000008
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK                                            0x0000000800000000
+
+#define TX_PEER_ENTRY_KEY_TYPE_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_KEY_TYPE_LSB                                                  36
+#define TX_PEER_ENTRY_KEY_TYPE_MSB                                                  39
+#define TX_PEER_ENTRY_KEY_TYPE_MASK                                                 0x000000f000000000
+
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET                                     0x0000000000000008
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB                                        40
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB                                        42
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK                                       0x0000070000000000
+
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK                                      0x0000080000000000
+
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK                                      0x0000100000000000
+
+#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET                                             0x0000000000000008
+#define TX_PEER_ENTRY_EPD_OUTPUT_LSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MASK                                               0x0000200000000000
+
+#define TX_PEER_ENTRY_WDS_OFFSET                                                    0x0000000000000008
+#define TX_PEER_ENTRY_WDS_LSB                                                       46
+#define TX_PEER_ENTRY_WDS_MSB                                                       46
+#define TX_PEER_ENTRY_WDS_MASK                                                      0x0000400000000000
+
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET                                        0x0000000000000008
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK                                          0x0000800000000000
+
+#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET                                           0x0000000000000008
+#define TX_PEER_ENTRY_SW_FILTER_ID_LSB                                              48
+#define TX_PEER_ENTRY_SW_FILTER_ID_MSB                                              63
+#define TX_PEER_ENTRY_SW_FILTER_ID_MASK                                             0xffff000000000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET                                      0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB                                         0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB                                         31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK                                        0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET                                     0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB                                        32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB                                        63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK                                       0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET                                     0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB                                        0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB                                        31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK                                       0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET                                    0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB                                       32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB                                       63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK                                      0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB                                           0
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB                                           10
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK                                          0x00000000000007ff
+
+#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET                                           0x0000000000000030
+#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB                                              11
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB                                              14
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK                                             0x0000000000007800
+
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK                                          0x0000000000008000
+
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB                                           16
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB                                           17
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK                                          0x0000000000030000
+
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK                                    0x0000000000040000
+
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK                                          0x0000000000080000
+
+#define TX_PEER_ENTRY_USE_AD_C_OFFSET                                               0x0000000000000030
+#define TX_PEER_ENTRY_USE_AD_C_LSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MASK                                                 0x0000000000100000
+
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET                             0x0000000000000030
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB                                21
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB                                22
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK                               0x0000000000600000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET                              0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK                                0x0000000000800000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                  0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                    0x0000000001000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                         0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                           0x0000000002000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                          0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                            0x0000000004000000
+
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB                                      27
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB                                      28
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK                                     0x0000000018000000
+
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB                                      29
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB                                      30
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK                                     0x0000000060000000
+
+#define TX_PEER_ENTRY_RESERVED_12_OFFSET                                            0x0000000000000030
+#define TX_PEER_ENTRY_RESERVED_12_LSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MASK                                              0x0000000080000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB                                     32
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB                                     47
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK                                    0x0000ffff00000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB                                     48
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB                                     63
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK                                    0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET                          0x0000000000000040
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK                            0x0000000100000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB                                    33
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB                                    34
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK                                   0x0000000600000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB                                    35
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB                                    36
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK                                   0x0000001800000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB                                    37
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB                                    38
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK                                   0x0000006000000000
+
+#define TX_PEER_ENTRY_RESERVED_17A_OFFSET                                           0x0000000000000040
+#define TX_PEER_ENTRY_RESERVED_17A_LSB                                              39
+#define TX_PEER_ENTRY_RESERVED_17A_MSB                                              47
+#define TX_PEER_ENTRY_RESERVED_17A_MASK                                             0x0000ff8000000000
+
+#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET                                             0x0000000000000040
+#define TX_PEER_ENTRY_SW_PEER_ID_LSB                                                48
+#define TX_PEER_ENTRY_SW_PEER_ID_MSB                                                63
+#define TX_PEER_ENTRY_SW_PEER_ID_MASK                                               0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET                                        0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET                                       0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET                              0x0000000000000048
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB                                 48
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB                                 63
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK                                0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET                               0x0000000000000050
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB                                  0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB                                  31
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET                                          0x0000000000000050
+#define TX_PEER_ENTRY_TLV64_PADDING_LSB                                             32
+#define TX_PEER_ENTRY_TLV64_PADDING_MSB                                             63
+#define TX_PEER_ENTRY_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_queue_extension.h b/hw/fig/v2/tx_queue_extension.h
new file mode 100644
index 000000000000..e46bae7cff4c
--- /dev/null
+++ b/hw/fig/v2/tx_queue_extension.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_QUEUE_EXTENSION_H_
+#define _TX_QUEUE_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18
+
+#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9
+
+struct tx_queue_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t frame_ctl                                               : 16,
+                      qos_ctl                                                 : 16;
+             uint32_t ampdu_flag                                              :  1,
+                      tx_notify_no_htc_override                               :  1,
+                      reserved_1a                                             :  7,
+                      checksum_tso_disable_for_frag                           :  1,
+                      key_id                                                  :  8,
+                      qos_buf_state_overwrite                                 :  1,
+                      buf_state_sta_id                                        :  1,
+                      buf_state_source                                        :  1,
+                      ht_control_overwrite_enable                             :  1,
+                      ht_control_overwrite_source                             :  4,
+                      reserved_1b                                             :  6;
+             uint32_t ul_headroom_insertion_enable                            :  1,
+                      ul_headroom_offset                                      :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      bqrp_offset                                             :  5,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqr_rsvd_9_8                                            :  2,
+                      base_pn_63_48                                           : 16;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_default_tb_ppdu                              : 32;
+             uint32_t ht_control_default_non_tb_ppdu                          : 32;
+             uint32_t ht_control_overwrite_tb_ppdu_enable                     :  1,
+                      ht_control_overwrite_non_tb_ppdu_enable                 :  1,
+                      reserved_7a                                             : 30;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t cas_control_info                                        :  8,
+                      cas_offset                                              :  5,
+                      cas_insertion_enable                                    :  1,
+                      reserved_10a                                            :  2,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      reserved_10b                                            :  5,
+                      mpdu_hdr_len_override_en                                :  1,
+                      bar_ssn_overwrite_enable                                :  1;
+             uint32_t bar_ssn_offset                                          : 12,
+                      mpdu_hdr_len_override_val                               :  9,
+                      reserved_11a                                            : 11;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t pre_padding_fcs_overwrite_offset                        : 16,
+                      icf_blackout_info_offset                                : 16;
+             uint32_t trigger_common_info_length                              :  6,
+                      cmf_overwrite_offset                                    : 14,
+                      reserved_15a                                            : 12;
+             uint32_t hdr_ctrl_prot_key_id_byte_offset                        : 14,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      reserved_16a                                            :  2;
+             uint32_t pad_byte_offset                                         : 16,
+                      pad_byte_offset_valid                                   :  1,
+                      txop_duration_overwrite_enable                          :  1,
+                      txop_duration_offset                                    : 14;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t qos_ctl                                                 : 16,
+                      frame_ctl                                               : 16;
+             uint32_t reserved_1b                                             :  6,
+                      ht_control_overwrite_source                             :  4,
+                      ht_control_overwrite_enable                             :  1,
+                      buf_state_source                                        :  1,
+                      buf_state_sta_id                                        :  1,
+                      qos_buf_state_overwrite                                 :  1,
+                      key_id                                                  :  8,
+                      checksum_tso_disable_for_frag                           :  1,
+                      reserved_1a                                             :  7,
+                      tx_notify_no_htc_override                               :  1,
+                      ampdu_flag                                              :  1;
+             uint32_t base_pn_63_48                                           : 16,
+                      bqr_rsvd_9_8                                            :  2,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqrp_offset                                             :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      ul_headroom_offset                                      :  5,
+                      ul_headroom_insertion_enable                            :  1;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_default_tb_ppdu                              : 32;
+             uint32_t ht_control_default_non_tb_ppdu                          : 32;
+             uint32_t reserved_7a                                             : 30,
+                      ht_control_overwrite_non_tb_ppdu_enable                 :  1,
+                      ht_control_overwrite_tb_ppdu_enable                     :  1;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t bar_ssn_overwrite_enable                                :  1,
+                      mpdu_hdr_len_override_en                                :  1,
+                      reserved_10b                                            :  5,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      reserved_10a                                            :  2,
+                      cas_insertion_enable                                    :  1,
+                      cas_offset                                              :  5,
+                      cas_control_info                                        :  8;
+             uint32_t reserved_11a                                            : 11,
+                      mpdu_hdr_len_override_val                               :  9,
+                      bar_ssn_offset                                          : 12;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t icf_blackout_info_offset                                : 16,
+                      pre_padding_fcs_overwrite_offset                        : 16;
+             uint32_t reserved_15a                                            : 12,
+                      cmf_overwrite_offset                                    : 14,
+                      trigger_common_info_length                              :  6;
+             uint32_t reserved_16a                                            :  2,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      hdr_ctrl_prot_key_id_byte_offset                        : 14;
+             uint32_t txop_duration_offset                                    : 14,
+                      txop_duration_overwrite_enable                          :  1,
+                      pad_byte_offset_valid                                   :  1,
+                      pad_byte_offset                                         : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET                                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB                                            0
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB                                            15
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK                                           0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET                                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_CTL_LSB                                              16
+#define TX_QUEUE_EXTENSION_QOS_CTL_MSB                                              31
+#define TX_QUEUE_EXTENSION_QOS_CTL_MASK                                             0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET                                        0x0000000000000000
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK                                          0x0000000100000000
+
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK                           0x0000000200000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB                                          34
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB                                          40
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK                                         0x000001fc00000000
+
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET                     0x0000000000000000
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK                       0x0000020000000000
+
+#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET                                            0x0000000000000000
+#define TX_QUEUE_EXTENSION_KEY_ID_LSB                                               42
+#define TX_QUEUE_EXTENSION_KEY_ID_MSB                                               49
+#define TX_QUEUE_EXTENSION_KEY_ID_MASK                                              0x0003fc0000000000
+
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK                             0x0004000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK                                    0x0008000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK                                    0x0010000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK                         0x0020000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB                          54
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB                          57
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK                         0x03c0000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB                                          58
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB                                          63
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK                                         0xfc00000000000000
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK                        0x0000000000000001
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET                                0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB                                   1
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB                                   5
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK                                  0x000000000000003e
+
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET                             0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK                               0x0000000000000040
+
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET                                       0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB                                          7
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB                                          11
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK                                         0x0000000000000f80
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET                              0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB                                 12
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB                                 13
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK                                0x0000000000003000
+
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET                                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB                                         14
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB                                         15
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB                                        16
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB                                        31
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK                                       0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB                                        32
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB                                        63
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK                                       0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET                                    0x0000000000000010
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB                                       0
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB                                       31
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK                                      0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET                        0x0000000000000010
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB                           32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB                           63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK                          0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET                    0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB                       0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB                       31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK                      0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET               0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB                  32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB                  32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK                 0x0000000100000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET           0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB              33
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB              33
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK             0x0000000200000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET                                       0x0000000000000018
+#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB                                          34
+#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB                                          63
+#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK                                         0xfffffffc00000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET                                       0x0000000000000020
+#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB                                          0
+#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB                                          31
+#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK                                         0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET                         0x0000000000000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB                            32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB                            63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK                           0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET                                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB                                     0
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB                                     7
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK                                    0x00000000000000ff
+
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET                                        0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB                                           8
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB                                           12
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK                                          0x0000000000001f00
+
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET                              0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK                                0x0000000000002000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB                                         14
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB                                         15
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET               0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB                  16
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB                  19
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK                 0x00000000000f0000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET              0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB                 20
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB                 23
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK                0x0000000000f00000
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK                    0x0000000001000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB                                         25
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB                                         29
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK                                        0x000000003e000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK                            0x0000000040000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK                            0x0000000080000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET                                    0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB                                       32
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB                                       43
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK                                      0x00000fff00000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET                         0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB                            44
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB                            52
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK                           0x001ff00000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB                                         53
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK                                        0xffe0000000000000
+
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET                                        0x0000000000000030
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB                                           0
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB                                           31
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK                                          0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET                  0x0000000000000030
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB                     32
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB                     47
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK                    0x0000ffff00000000
+
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET                          0x0000000000000030
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB                             48
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB                             63
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK                            0xffff000000000000
+
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET                        0x0000000000000038
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB                           0
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB                           5
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK                          0x000000000000003f
+
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET                              0x0000000000000038
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB                                 6
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB                                 19
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK                                0x00000000000fffc0
+
+#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET                                      0x0000000000000038
+#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB                                         20
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB                                         31
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK                                        0x00000000fff00000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET                  0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB                     32
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB                     45
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK                    0x00003fff00000000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET                   0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB                      46
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB                      48
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK                     0x0001c00000000000
+
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET                                  0x0000000000000038
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB                                     49
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB                                     49
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK                                    0x0002000000000000
+
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET                                   0x0000000000000038
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB                                      50
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB                                      50
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK                                     0x0004000000000000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET                         0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB                            51
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB                            61
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK                           0x3ff8000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET                                      0x0000000000000038
+#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB                                         62
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK                                        0xc000000000000000
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET                                   0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB                                      0
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB                                      15
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK                                     0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET                             0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB                                16
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB                                16
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK                               0x0000000000010000
+
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET                    0x0000000000000040
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB                       17
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB                       17
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK                      0x0000000000020000
+
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET                              0x0000000000000040
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB                                 18
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB                                 31
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK                                0x00000000fffc0000
+
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET                                     0x0000000000000040
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB                                        32
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB                                        63
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/tx_rate_stats_info.h b/hw/fig/v2/tx_rate_stats_info.h
new file mode 100644
index 000000000000..ce84032dd353
--- /dev/null
+++ b/hw/fig/v2/tx_rate_stats_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_rate_stats_info_valid                                :  1,
+                      transmit_bw                                             :  3,
+                      transmit_pkt_type                                       :  4,
+                      transmit_stbc                                           :  1,
+                      transmit_ldpc                                           :  1,
+                      transmit_sgi                                            :  2,
+                      transmit_mcs                                            :  5,
+                      unequal_modulation_info                                 :  3,
+                      ofdma_transmission                                      :  1,
+                      reserved_0a                                             :  4,
+                      tones_in_ru                                             :  4,
+                      transmit_nss                                            :  3;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#else
+             uint32_t transmit_nss                                            :  3,
+                      tones_in_ru                                             :  4,
+                      reserved_0a                                             :  4,
+                      ofdma_transmission                                      :  1,
+                      unequal_modulation_info                                 :  3,
+                      transmit_mcs                                            :  5,
+                      transmit_sgi                                            :  2,
+                      transmit_ldpc                                           :  1,
+                      transmit_stbc                                           :  1,
+                      transmit_pkt_type                                       :  4,
+                      transmit_bw                                             :  3,
+                      tx_rate_stats_info_valid                                :  1;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#endif
+};
+
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET                          0x00000000
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK                            0x00000001
+
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB                                          1
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB                                          3
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK                                         0x0000000e
+
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET                                 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB                                    4
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB                                    7
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK                                   0x000000f0
+
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK                                       0x00000100
+
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK                                       0x00000200
+
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB                                         10
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB                                         11
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK                                        0x00000c00
+
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB                                         12
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB                                         16
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK                                        0x0001f000
+
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET                           0x00000000
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB                              17
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB                              19
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK                             0x000e0000
+
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET                                0x00000000
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK                                  0x00100000
+
+#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_RESERVED_0A_LSB                                          21
+#define TX_RATE_STATS_INFO_RESERVED_0A_MSB                                          24
+#define TX_RATE_STATS_INFO_RESERVED_0A_MASK                                         0x01e00000
+
+#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB                                          25
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB                                          28
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK                                         0x1e000000
+
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB                                         29
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB                                         31
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK                                        0xe0000000
+
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET                             0x00000004
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB                                0
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB                                31
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK                               0xffffffff
+
+#endif
diff --git a/hw/fig/v2/tx_raw_or_native_frame_setup.h b/hw/fig/v2/tx_raw_or_native_frame_setup.h
new file mode 100644
index 000000000000..220a82edf96d
--- /dev/null
+++ b/hw/fig/v2/tx_raw_or_native_frame_setup.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4
+
+#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
+
+struct tx_raw_or_native_frame_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fc_to_ds_mask                                           :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_order_mask                                           :  1,
+                      duration_field_mask                                     :  1,
+                      sequence_control_mask                                   :  1,
+                      qc_tid_mask                                             :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_amsdu_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_15to8_mask                                           :  1,
+                      iv_mask                                                 :  1,
+                      fc_to_ds_setting                                        :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_more_frag_setting                                    :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  2,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_order_setting                                        :  1,
+                      qc_tid_setting                                          :  4;
+             uint32_t qc_eosp_setting                                         :  2,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_amsdu_setting                                        :  1,
+                      qc_15to8_setting                                        :  8,
+                      mlo_addr_override                                       :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      sequence_control_source                                 :  1,
+                      fragment_number                                         :  4,
+                      sequence_number                                         : 12;
+             uint32_t mlo_addr_override_for_ctrl                              :  1,
+                      reserved_2a                                             : 31;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t qc_tid_setting                                          :  4,
+                      fc_order_setting                                        :  1,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_more_data_setting                                    :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_more_frag_setting                                    :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_to_ds_setting                                        :  1,
+                      iv_mask                                                 :  1,
+                      qc_15to8_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_amsdu_mask                                           :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_tid_mask                                             :  1,
+                      sequence_control_mask                                   :  1,
+                      duration_field_mask                                     :  1,
+                      fc_order_mask                                           :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_to_ds_mask                                           :  1;
+             uint32_t sequence_number                                         : 12,
+                      fragment_number                                         :  4,
+                      sequence_control_source                                 :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      mlo_addr_override                                       :  1,
+                      qc_15to8_setting                                        :  8,
+                      qc_amsdu_setting                                        :  1,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_eosp_setting                                         :  2;
+             uint32_t reserved_2a                                             : 31,
+                      mlo_addr_override_for_ctrl                              :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK                             0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK                           0x0000000000000002
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK                         0x0000000000000004
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK                             0x0000000000000008
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK                           0x0000000000000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK                         0x0000000000000020
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK                        0x0000000000000040
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK                             0x0000000000000080
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET                     0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK                       0x0000000000000100
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK                     0x0000000000000200
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK                               0x0000000000000400
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET                            0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK                              0x0000000000000800
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK                        0x0000000000001000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK                             0x0000000000002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK                               0x0000000000004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK                             0x0000000000008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET                                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK                                   0x0000000000010000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK                          0x0000000000020000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK                        0x0000000000040000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK                      0x0000000000080000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB                           20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB                           21
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK                          0x0000000000300000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK                        0x0000000000400000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB                       23
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB                       24
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK                      0x0000000001800000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB                      25
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB                      26
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK                     0x0000000006000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK                          0x0000000008000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET                          0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB                             28
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB                             31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK                            0x00000000f0000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB                            32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB                            33
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK                           0x0000000300000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB                      34
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB                      35
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK                     0x0000000c00000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK                          0x0000001000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB                           37
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB                           44
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK                          0x00001fe000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK                         0x0000200000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET               0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK                 0x0000400000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK                   0x0000800000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB                            48
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB                            51
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK                           0x000f000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB                            52
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB                            63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK                           0xfff0000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET              0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK                0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET                             0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB                                1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB                                31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK                               0x00000000fffffffe
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET                           0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB                              32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB                              63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK                             0xffffffff00000000
+
+#endif
diff --git a/hw/fig/v2/txpcu_buffer_basics.h b/hw/fig/v2/txpcu_buffer_basics.h
new file mode 100644
index 000000000000..4032a78ad617
--- /dev/null
+++ b/hw/fig/v2/txpcu_buffer_basics.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t available_memory                                        :  8,
+                      partial_tx_data_tlv_count                               :  8,
+                      tx_data_tlv_count                                       : 16;
+#else
+             uint32_t tx_data_tlv_count                                       : 16,
+                      partial_tx_data_tlv_count                               :  8,
+                      available_memory                                        :  8;
+#endif
+};
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET                                 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB                                    0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB                                    7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK                                   0x000000ff
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET                        0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB                           8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB                           15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK                          0x0000ff00
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET                                0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB                                   16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB                                   31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK                                  0xffff0000
+
+#endif
diff --git a/hw/fig/v2/txpcu_buffer_status.h b/hw/fig/v2/txpcu_buffer_status.h
new file mode 100644
index 000000000000..847ca277267d
--- /dev/null
+++ b/hw/fig/v2/txpcu_buffer_status.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_STATUS_H_
+#define _TXPCU_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
+
+struct txpcu_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t reserved                                                : 15,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved                                                : 15;
+#endif
+};
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x00000000000000ff
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x000000000000ff00
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0x00000000ffff0000
+
+#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            32
+#define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            46
+#define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff00000000
+
+#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x0000800000000000
+
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  48
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  63
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/txpcu_user_buffer_status.h b/hw/fig/v2/txpcu_user_buffer_status.h
new file mode 100644
index 000000000000..f6ad0fd73721
--- /dev/null
+++ b/hw/fig/v2/txpcu_user_buffer_status.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_USER_BUFFER_STATUS_H_
+#define _TXPCU_USER_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1
+
+struct txpcu_user_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t stored_word_count_user                                  : 14,
+                      reserved_1a                                             :  1,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved_1a                                             :  1,
+                      stored_word_count_user                                  : 14;
+#endif
+};
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB       0
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB       7
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK      0x00000000000000ff
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET   0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB      16
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB      31
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK     0x00000000ffff0000
+
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET                      0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB                         32
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB                         45
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK                        0x00003fff00000000
+
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET                                 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK                                   0x0000400000000000
+
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET                                    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK                                      0x0000800000000000
+
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                          0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                             48
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                             63
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                            0xffff000000000000
+
+#endif
diff --git a/hw/fig/v2/u_sig_eht_su_mu_info.h b/hw/fig/v2/u_sig_eht_su_mu_info.h
new file mode 100644
index 000000000000..1a08f3ab39b2
--- /dev/null
+++ b/hw/fig/v2/u_sig_eht_su_mu_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  5,
+                      validate_0b                                             :  1,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1b                                             :  1,
+                      mcs_of_eht_sig                                          :  2,
+                      num_eht_sig_symbols                                     :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      reserved_1d                                             :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      validate_0b                                             :  1,
+                      disregard_0a                                            :  5,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      reserved_1d                                             :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      num_eht_sig_symbols                                     :  5,
+                      mcs_of_eht_sig                                          :  2,
+                      validate_1b                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB                                        0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK                                       0x00000007
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB                                        3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB                                        5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK                                       0x00000038
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET                                      0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK                                        0x00000040
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB                                       7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB                                       12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK                                      0x00001f80
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET                                   0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB                                      13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB                                      19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK                                     0x000fe000
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB                                       20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB                                       24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK                                      0x01f00000
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK                                       0x02000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB                                        26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB                                        31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK                                       0xfc000000
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                           0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                              0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                              1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                             0x00000003
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK                                       0x00000004
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET                   0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB                      3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB                      7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK                     0x000000f8
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK                                       0x00000100
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET                                  0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB                                     9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB                                     10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK                                    0x00000600
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB                                11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB                                15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK                               0x0000f800
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET                                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB                                                16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB                                                19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK                                               0x000f0000
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET                                            0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB                                               20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB                                               25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK                                              0x03f00000
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK                               0x04000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB                                        27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB                                        29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK                                       0x38000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET                                          0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK                                            0x40000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#endif
diff --git a/hw/fig/v2/u_sig_eht_tb_info.h b/hw/fig/v2/u_sig_eht_tb_info.h
new file mode 100644
index 000000000000..8e417b38d233
--- /dev/null
+++ b/hw/fig/v2/u_sig_eht_tb_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  6,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      spatial_reuse                                           :  8,
+                      disregard_1b                                            :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1c                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      disregard_0a                                            :  6,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1c                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      disregard_1b                                            :  5,
+                      spatial_reuse                                           :  8,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB                                           0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB                                           2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK                                          0x00000007
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB                                           3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB                                           5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK                                          0x00000038
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET                                         0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK                                           0x00000040
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB                                          7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB                                          12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK                                         0x00001f80
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET                                      0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB                                         13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB                                         19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK                                        0x000fe000
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB                                          20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB                                          25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK                                         0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB                                           31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK                                          0xfc000000
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                              0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                                 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                                 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                                0x00000003
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK                                          0x00000004
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET                                      0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB                                         3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB                                         10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK                                        0x000007f8
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET                                       0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB                                          11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB                                          15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK                                         0x0000f800
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET                                                0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB                                                   16
+#define U_SIG_EHT_TB_INFO_CRC_MSB                                                   19
+#define U_SIG_EHT_TB_INFO_CRC_MASK                                                  0x000f0000
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET                                               0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB                                                  20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB                                                  25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK                                                 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB                                           30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK                                          0x7c000000
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/fig/v2/unallocated_ru_160_info.h b/hw/fig/v2/unallocated_ru_160_info.h
new file mode 100644
index 000000000000..ccd4a7bab9ad
--- /dev/null
+++ b/hw/fig/v2/unallocated_ru_160_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t subband80_0_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_1_cc1                                         :  8;
+#else
+             uint32_t subband80_1_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_0_cc0                                         :  8;
+#endif
+};
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB                                 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB                                 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK                                0x000000ff
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB                                 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB                                 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK                                0x0000ff00
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB                                 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB                                 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK                                0x00ff0000
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB                                 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB                                 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK                                0xff000000
+
+#endif
diff --git a/hw/fig/v2/uniform_descriptor_header.h b/hw/fig/v2/uniform_descriptor_header.h
new file mode 100644
index 000000000000..7a2de6ccd8df
--- /dev/null
+++ b/hw/fig/v2/uniform_descriptor_header.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t owner                                                   :  4,
+                      buffer_type                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      reserved_0a                                             :  4;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      buffer_type                                             :  4,
+                      owner                                                   :  4;
+#endif
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET                                      0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB                                         0
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB                                         3
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK                                        0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                                   4
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                                   7
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
+
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_a_info.h b/hw/fig/v2/vht_sig_a_info.h
new file mode 100644
index 000000000000..acd20f43949e
--- /dev/null
+++ b/hw/fig/v2/vht_sig_a_info.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t bandwidth                                               :  2,
+                      vhta_reserved_0                                         :  1,
+                      stbc                                                    :  1,
+                      group_id                                                :  6,
+                      n_sts                                                   : 12,
+                      txop_ps_not_allowed                                     :  1,
+                      vhta_reserved_0b                                        :  1,
+                      reserved_0                                              :  8;
+             uint32_t gi_setting                                              :  2,
+                      su_mu_coding                                            :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      mcs                                                     :  4,
+                      beamformed                                              :  1,
+                      vhta_reserved_1                                         :  1,
+                      crc                                                     :  8,
+                      tail                                                    :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      vhta_reserved_0b                                        :  1,
+                      txop_ps_not_allowed                                     :  1,
+                      n_sts                                                   : 12,
+                      group_id                                                :  6,
+                      stbc                                                    :  1,
+                      vhta_reserved_0                                         :  1,
+                      bandwidth                                               :  2;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      tail                                                    :  6,
+                      crc                                                     :  8,
+                      vhta_reserved_1                                         :  1,
+                      beamformed                                              :  1,
+                      mcs                                                     :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      su_mu_coding                                            :  1,
+                      gi_setting                                              :  2;
+#endif
+};
+
+#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET                                             0x00000000
+#define VHT_SIG_A_INFO_BANDWIDTH_LSB                                                0
+#define VHT_SIG_A_INFO_BANDWIDTH_MSB                                                1
+#define VHT_SIG_A_INFO_BANDWIDTH_MASK                                               0x00000003
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK                                         0x00000004
+
+#define VHT_SIG_A_INFO_STBC_OFFSET                                                  0x00000000
+#define VHT_SIG_A_INFO_STBC_LSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MASK                                                    0x00000008
+
+#define VHT_SIG_A_INFO_GROUP_ID_OFFSET                                              0x00000000
+#define VHT_SIG_A_INFO_GROUP_ID_LSB                                                 4
+#define VHT_SIG_A_INFO_GROUP_ID_MSB                                                 9
+#define VHT_SIG_A_INFO_GROUP_ID_MASK                                                0x000003f0
+
+#define VHT_SIG_A_INFO_N_STS_OFFSET                                                 0x00000000
+#define VHT_SIG_A_INFO_N_STS_LSB                                                    10
+#define VHT_SIG_A_INFO_N_STS_MSB                                                    21
+#define VHT_SIG_A_INFO_N_STS_MASK                                                   0x003ffc00
+
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET                                   0x00000000
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK                                     0x00400000
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET                                      0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK                                        0x00800000
+
+#define VHT_SIG_A_INFO_RESERVED_0_OFFSET                                            0x00000000
+#define VHT_SIG_A_INFO_RESERVED_0_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_0_MSB                                               31
+#define VHT_SIG_A_INFO_RESERVED_0_MASK                                              0xff000000
+
+#define VHT_SIG_A_INFO_GI_SETTING_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_GI_SETTING_LSB                                               0
+#define VHT_SIG_A_INFO_GI_SETTING_MSB                                               1
+#define VHT_SIG_A_INFO_GI_SETTING_MASK                                              0x00000003
+
+#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET                                          0x00000004
+#define VHT_SIG_A_INFO_SU_MU_CODING_LSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MASK                                            0x00000004
+
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                     0x00000004
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK                                       0x00000008
+
+#define VHT_SIG_A_INFO_MCS_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_MCS_LSB                                                      4
+#define VHT_SIG_A_INFO_MCS_MSB                                                      7
+#define VHT_SIG_A_INFO_MCS_MASK                                                     0x000000f0
+
+#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_BEAMFORMED_LSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MASK                                              0x00000100
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK                                         0x00000200
+
+#define VHT_SIG_A_INFO_CRC_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_CRC_LSB                                                      10
+#define VHT_SIG_A_INFO_CRC_MSB                                                      17
+#define VHT_SIG_A_INFO_CRC_MASK                                                     0x0003fc00
+
+#define VHT_SIG_A_INFO_TAIL_OFFSET                                                  0x00000004
+#define VHT_SIG_A_INFO_TAIL_LSB                                                     18
+#define VHT_SIG_A_INFO_TAIL_MSB                                                     23
+#define VHT_SIG_A_INFO_TAIL_MASK                                                    0x00fc0000
+
+#define VHT_SIG_A_INFO_RESERVED_1_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_RESERVED_1_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_1_MSB                                               30
+#define VHT_SIG_A_INFO_RESERVED_1_MASK                                              0x7f000000
+
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                             0x00000004
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                               0x80000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_mu160_info.h b/hw/fig/v2/vht_sig_b_mu160_info.h
new file mode 100644
index 000000000000..13931c5c3556
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_mu160_info.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+             uint32_t length_copy_d                                           : 19,
+                      mcs_copy_d                                              :  4,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  3;
+             uint32_t length_copy_e                                           : 19,
+                      mcs_copy_e                                              :  4,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  3;
+             uint32_t length_copy_f                                           : 19,
+                      mcs_copy_f                                              :  4,
+                      tail_copy_f                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_g                                           : 19,
+                      mcs_copy_g                                              :  4,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t reserved_2                                              :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+             uint32_t reserved_4                                              :  3,
+                      tail_copy_d                                             :  6,
+                      mcs_copy_d                                              :  4,
+                      length_copy_d                                           : 19;
+             uint32_t reserved_5                                              :  3,
+                      tail_copy_e                                             :  6,
+                      mcs_copy_e                                              :  4,
+                      length_copy_e                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_f                                             :  6,
+                      mcs_copy_f                                              :  4,
+                      length_copy_f                                           : 19;
+             uint32_t reserved_7                                              :  3,
+                      tail_copy_g                                             :  6,
+                      mcs_copy_g                                              :  4,
+                      length_copy_g                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB                                             18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK                                            0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB                                                19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB                                                22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK                                               0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET                                      0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET                                  0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB                                     29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB                                     31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK                                    0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK                                        0xe0000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_mu20_info.h b/hw/fig/v2/vht_sig_b_mu20_info.h
new file mode 100644
index 000000000000..c51ac839a757
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_mu20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 16,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      mu_user_number                                          :  3,
+                      reserved_0                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      mu_user_number                                          :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 16;
+#endif
+};
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB                                              15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK                                             0x0000ffff
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB                                                 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB                                                 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK                                                0x000f0000
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB                                      26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB                                      28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK                                     0x1c000000
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_mu40_info.h b/hw/fig/v2/vht_sig_b_mu40_info.h
new file mode 100644
index 000000000000..0eb4c164cca1
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_mu40_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy                                             : 17,
+                      mcs_copy                                                :  4,
+                      tail_copy                                               :  6,
+                      reserved_1                                              :  5;
+#else
+             uint32_t mu_user_number                                          :  3,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 17;
+             uint32_t reserved_1                                              :  5,
+                      tail_copy                                               :  6,
+                      mcs_copy                                                :  4,
+                      length_copy                                             : 17;
+#endif
+};
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB                                                 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB                                                 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK                                                0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB                                          28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK                                         0x18000000
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB                                         16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK                                        0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET                                         0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB                                            17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB                                            20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK                                           0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK                                         0xf8000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_mu80_info.h b/hw/fig/v2/vht_sig_b_mu80_info.h
new file mode 100644
index 000000000000..33d0f1bc08fc
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_mu80_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB                                                 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB                                                 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK                                                0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET                                       0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_su160_info.h b/hw/fig/v2/vht_sig_b_su160_info.h
new file mode 100644
index 000000000000..7ba503724b56
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_su160_info.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+             uint32_t length_copy_d                                           : 21,
+                      vhtb_reserved_copy_d                                    :  2,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  2,
+                      rx_ndp_copy_d                                           :  1;
+             uint32_t length_copy_e                                           : 21,
+                      vhtb_reserved_copy_e                                    :  2,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  2,
+                      rx_ndp_copy_e                                           :  1;
+             uint32_t length_copy_f                                           : 21,
+                      vhtb_reserved_copy_f                                    :  2,
+                      tail_copy_f                                             :  6,
+                      reserved_6                                              :  2,
+                      rx_ndp_copy_f                                           :  1;
+             uint32_t length_copy_g                                           : 21,
+                      vhtb_reserved_copy_g                                    :  2,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  2,
+                      rx_ndp_copy_g                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+             uint32_t rx_ndp_copy_d                                           :  1,
+                      reserved_4                                              :  2,
+                      tail_copy_d                                             :  6,
+                      vhtb_reserved_copy_d                                    :  2,
+                      length_copy_d                                           : 21;
+             uint32_t rx_ndp_copy_e                                           :  1,
+                      reserved_5                                              :  2,
+                      tail_copy_e                                             :  6,
+                      vhtb_reserved_copy_e                                    :  2,
+                      length_copy_e                                           : 21;
+             uint32_t rx_ndp_copy_f                                           :  1,
+                      reserved_6                                              :  2,
+                      tail_copy_f                                             :  6,
+                      vhtb_reserved_copy_f                                    :  2,
+                      length_copy_f                                           : 21;
+             uint32_t rx_ndp_copy_g                                           :  1,
+                      reserved_7                                              :  2,
+                      tail_copy_g                                             :  6,
+                      vhtb_reserved_copy_g                                    :  2,
+                      length_copy_g                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB                                             20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK                                            0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET                                   0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB                                      21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB                                      22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK                                     0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK                                            0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET                            0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET                            0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET                            0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET                            0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET                            0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET                            0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET                                      0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET                            0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK                                     0x80000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_su20_info.h b/hw/fig/v2/vht_sig_b_su20_info.h
new file mode 100644
index 000000000000..2c7f11ba3c21
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_su20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      vhtb_reserved                                           :  3,
+                      tail                                                    :  6,
+                      reserved                                                :  5,
+                      rx_ndp                                                  :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  5,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  3,
+                      length                                                  : 17;
+#endif
+};
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_su40_info.h b/hw/fig/v2/vht_sig_b_su40_info.h
new file mode 100644
index 000000000000..467259003e8d
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_su40_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved                                                :  4,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy                                             : 19,
+                      vhtb_reserved_copy                                      :  2,
+                      tail_copy                                               :  6,
+                      reserved_copy                                           :  4,
+                      rx_ndp_copy                                             :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  4,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 19;
+             uint32_t rx_ndp_copy                                             :  1,
+                      reserved_copy                                           :  4,
+                      tail_copy                                               :  6,
+                      vhtb_reserved_copy                                      :  2,
+                      length_copy                                             : 19;
+#endif
+};
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB                                       19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB                                       20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK                                      0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB                                            27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK                                           0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB                                         18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK                                        0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET                               0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB                                  19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB                                  20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK                                 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB                                       27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB                                       30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK                                      0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK                                        0x80000000
+
+#endif
diff --git a/hw/fig/v2/vht_sig_b_su80_info.h b/hw/fig/v2/vht_sig_b_su80_info.h
new file mode 100644
index 000000000000..92ceeab9b476
--- /dev/null
+++ b/hw/fig/v2/vht_sig_b_su80_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB                                              20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK                                             0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB                                       21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB                                       22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK                                      0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET                             0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET                             0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET                                       0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET                             0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK                                      0x80000000
+
+#endif
diff --git a/hw/fig/v2/wbm2sw_completion_ring_rx.h b/hw/fig/v2/wbm2sw_completion_ring_rx.h
new file mode 100644
index 000000000000..e40a7e796a87
--- /dev/null
+++ b/hw/fig/v2/wbm2sw_completion_ring_rx.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM2SW_COMPLETION_RING_RX_H_
+#define _WBM2SW_COMPLETION_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8
+
+struct wbm2sw_completion_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      wbm_internal_error                                      :  1;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t buffer_phys_addr_39_32                                  :  8,
+                      sw_buffer_cookie                                        : 20,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie                                        : 20,
+                      buffer_phys_addr_39_32                                  :  8;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET                                  0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB                                     3
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB                                     5
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK                                    0x00000038
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB                                   13
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB                                   14
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK                                  0x00006000
+
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK                                     0x00008000
+
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK                     0x00010000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET                          0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB                             17
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB                             18
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK                            0x00060000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET                           0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB                              19
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB                              23
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK                             0x00f80000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET                            0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB                               24
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB                               25
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK                              0x03000000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET                             0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB                                26
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB                                30
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK                               0x7c000000
+
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB          0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB          7
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK         0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET    0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK      0x00000100
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET   0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK     0x00000200
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK         0x00000400
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET        0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK          0x00000800
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK           0x00002000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB            15
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB            26
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK           0x07ff8000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET              0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                0xf0000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000010
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB      0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB      31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK  0x00000004
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB         3
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB         16
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK        0x0001fff8
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK          0x00020000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK        0x00040000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK        0x00080000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET       0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK         0x00100000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET   0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK     0x00800000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK              0x01000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK              0x02000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK          0x04000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB        27
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB        28
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK       0x18000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB        29
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB        30
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK       0x60000000
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET                      0x00000018
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB                        7
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK                       0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET                           0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB                              8
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB                              27
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK                             0x0fffff00
+
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/fig/v2/wbm_buffer_ring.h b/hw/fig/v2/wbm_buffer_ring.h
new file mode 100644
index 000000000000..b1532e15595b
--- /dev/null
+++ b/hw/fig/v2/wbm_buffer_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+#endif
+};
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                       0x00000000
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                          0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                         0xffffffff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                      0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                         0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                         7
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                        0x000000ff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                  0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                     8
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                     11
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                    0x00000f00
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                       0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                          12
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                         0xfffff000
+
+#endif
diff --git a/hw/fig/v2/wbm_link_descriptor_ring.h b/hw/fig/v2/wbm_link_descriptor_ring.h
new file mode 100644
index 000000000000..851807aa4c1c
--- /dev/null
+++ b/hw/fig/v2/wbm_link_descriptor_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          desc_addr_info;
+#else
+             struct   buffer_addr_info                                          desc_addr_info;
+#endif
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET             0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB                0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK               0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET            0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB               0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB               7
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK              0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET        0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB           8
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB           11
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK          0x00000f00
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET             0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB                12
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK               0xfffff000
+
+#endif
diff --git a/hw/fig/v2/wbm_release_ring.h b/hw/fig/v2/wbm_release_ring.h
new file mode 100644
index 000000000000..e86d52753912
--- /dev/null
+++ b/hw/fig/v2/wbm_release_ring.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      reserved_2a                                             :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2b                                             : 22,
+                      wbm_internal_error                                      :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 28,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      reserved_2b                                             : 22,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_7a                                             : 28;
+#endif
+};
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET    0x00000000
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB       0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK      0xffffffff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET   0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB      0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB      7
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK     0x000000ff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB  8
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB  11
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET    0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB       12
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK      0xfffff000
+
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB                                  0
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB                                  2
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK                                 0x00000007
+
+#define WBM_RELEASE_RING_RESERVED_2A_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2A_LSB                                            3
+#define WBM_RELEASE_RING_RESERVED_2A_MSB                                            5
+#define WBM_RELEASE_RING_RESERVED_2A_MASK                                           0x00000038
+
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB                                    6
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB                                    8
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK                                   0x000001c0
+
+#define WBM_RELEASE_RING_RESERVED_2B_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2B_LSB                                            9
+#define WBM_RELEASE_RING_RESERVED_2B_MSB                                            30
+#define WBM_RELEASE_RING_RESERVED_2B_MASK                                           0x7ffffe00
+
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET                                  0x00000008
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK                                    0x80000000
+
+#define WBM_RELEASE_RING_RESERVED_3A_OFFSET                                         0x0000000c
+#define WBM_RELEASE_RING_RESERVED_3A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_3A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_3A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_4A_OFFSET                                         0x00000010
+#define WBM_RELEASE_RING_RESERVED_4A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_4A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_4A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_5A_OFFSET                                         0x00000014
+#define WBM_RELEASE_RING_RESERVED_5A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_5A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_5A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_6A_OFFSET                                         0x00000018
+#define WBM_RELEASE_RING_RESERVED_6A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_6A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_6A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_7A_OFFSET                                         0x0000001c
+#define WBM_RELEASE_RING_RESERVED_7A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_7A_MSB                                            27
+#define WBM_RELEASE_RING_RESERVED_7A_MASK                                           0x0fffffff
+
+#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET                                       0x0000001c
+#define WBM_RELEASE_RING_LOOPING_COUNT_LSB                                          28
+#define WBM_RELEASE_RING_LOOPING_COUNT_MSB                                          31
+#define WBM_RELEASE_RING_LOOPING_COUNT_MASK                                         0xf0000000
+
+#endif
diff --git a/hw/fig/v2/wbm_release_ring_rx.h b/hw/fig/v2/wbm_release_ring_rx.h
new file mode 100644
index 000000000000..a68bc8115a82
--- /dev/null
+++ b/hw/fig/v2/wbm_release_ring_rx.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_RX_H_
+#define _WBM_RELEASE_RING_RX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4
+
+struct wbm_release_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 14,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t reserved_3a                                             : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      reserved_2a                                             : 14,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         19
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x000fffc0
+
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET                             0x00000008
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB                                20
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB                                31
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK                               0xfff00000
+
+#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET                                      0x0000000c
+#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB                                         0
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB                                         31
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK                                        0xffffffff
+
+#endif
diff --git a/hw/fig/v2/wbm_release_ring_tx.h b/hw/fig/v2/wbm_release_ring_tx.h
new file mode 100644
index 000000000000..d1412153c6ae
--- /dev/null
+++ b/hw/fig/v2/wbm_release_ring_tx.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_TX_H_
+#define _WBM_RELEASE_RING_TX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4
+
+struct wbm_release_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 26;
+             uint32_t tqm_status_number                                       : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t reserved_2a                                             : 26,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t tqm_status_number                                       : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         31
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0xffffffc0
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   31
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0xffffffff
+
+#endif
diff --git a/hw/fig/v2/wcss_seq_hwiobase.h b/hw/fig/v2/wcss_seq_hwiobase.h
new file mode 100644
index 000000000000..4e455f399300
--- /dev/null
+++ b/hw/fig/v2/wcss_seq_hwiobase.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOBASE_H
+#define WCSS_SEQ_HWIOBASE_H
+
+#define UMAC_NOC_BASE                                                 0x140000
+#define UMAC_NOC_BASE_SIZE                                          0x00004480
+#define UMAC_NOC_BASE_PHYS                                          0x00140000
+
+#define PHYA0_BASE                                                    0x300000
+#define PHYA0_BASE_SIZE                                             0x00300000
+#define PHYA0_BASE_PHYS                                             0x00300000
+
+#define PHYA1_BASE                                                    0x600000
+#define PHYA1_BASE_SIZE                                             0x00300000
+#define PHYA1_BASE_PHYS                                             0x00600000
+
+#define DMAC_BASE                                                     0x900000
+#define DMAC_BASE_SIZE                                              0x00080000
+#define DMAC_BASE_PHYS                                              0x00900000
+
+#define UMAC_BASE                                                     0xa00000
+#define UMAC_BASE_SIZE                                              0x0004d000
+#define UMAC_BASE_PHYS                                              0x00a00000
+
+#define PMAC0_BASE                                                    0xa80000
+#define PMAC0_BASE_SIZE                                             0x00040000
+#define PMAC0_BASE_PHYS                                             0x00a80000
+
+#define PMAC1_BASE                                                    0xac0000
+#define PMAC1_BASE_SIZE                                             0x00040000
+#define PMAC1_BASE_PHYS                                             0x00ac0000
+
+#define WFSS_AMCSS_BASE                                               0xb00000
+#define WFSS_AMCSS_BASE_SIZE                                        0x00040000
+#define WFSS_AMCSS_BASE_PHYS                                        0x00b00000
+
+#define CXC_BASE                                                      0xb40000
+#define CXC_BASE_SIZE                                               0x00010000
+#define CXC_BASE_PHYS                                               0x00b40000
+
+#define WFSS_PMM_BASE                                                 0xb50000
+#define WFSS_PMM_BASE_SIZE                                          0x00002401
+#define WFSS_PMM_BASE_PHYS                                          0x00b50000
+
+#define WFSS_CC_BASE                                                  0xb60000
+#define WFSS_CC_BASE_SIZE                                           0x00008000
+#define WFSS_CC_BASE_PHYS                                           0x00b60000
+
+#define WCMN_CORE_BASE                                                0xb68000
+#define WCMN_CORE_BASE_SIZE                                         0x000008a9
+#define WCMN_CORE_BASE_PHYS                                         0x00b68000
+
+#define WIFI_CFGBUS_APB_TSLV_BASE                                     0xb6b000
+#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS                              0x00b6b000
+
+#define WFSS_CFGBUS_BASE                                              0xb6c000
+#define WFSS_CFGBUS_BASE_SIZE                                       0x000000a0
+#define WFSS_CFGBUS_BASE_PHYS                                       0x00b6c000
+
+#define WIFI_CFGBUS_AHB_TSLV_BASE                                     0xb6d000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS                              0x00b6d000
+
+#define UMAC_ACMT_BASE                                                0xb6e000
+#define UMAC_ACMT_BASE_SIZE                                         0x00001000
+#define UMAC_ACMT_BASE_PHYS                                         0x00b6e000
+
+#define WCSS_CC_BASE                                                  0xb80000
+#define WCSS_CC_BASE_SIZE                                           0x00010000
+#define WCSS_CC_BASE_PHYS                                           0x00b80000
+
+#define PMM_TOP_BASE                                                  0xb90000
+#define PMM_TOP_BASE_SIZE                                           0x00010000
+#define PMM_TOP_BASE_PHYS                                           0x00b90000
+
+#define WCSS_TOP_CMN_BASE                                             0xba0000
+#define WCSS_TOP_CMN_BASE_SIZE                                      0x00004000
+#define WCSS_TOP_CMN_BASE_PHYS                                      0x00ba0000
+
+#define WCSS_CFGBUS_BASE                                              0xba4000
+#define WCSS_CFGBUS_BASE_SIZE                                       0x00008000
+#define WCSS_CFGBUS_BASE_PHYS                                       0x00ba4000
+
+#define MSIP_BASE                                                     0xbb0000
+#define MSIP_BASE_SIZE                                              0x00010000
+#define MSIP_BASE_PHYS                                              0x00bb0000
+
+#define RFA_BASE                                                      0xbc0000
+#define RFA_BASE_SIZE                                               0x00040000
+#define RFA_BASE_PHYS                                               0x00bc0000
+
+#define DBG_BASE                                                     0x1000000
+#define DBG_BASE_SIZE                                               0x00100000
+#define DBG_BASE_PHYS                                               0x01000000
+
+#define Q6SS_WLAN_BASE                                               0x1100000
+#define Q6SS_WLAN_BASE_SIZE                                         0x00100000
+#define Q6SS_WLAN_BASE_PHYS                                         0x01100000
+
+#endif
diff --git a/hw/fig/v2/wcss_seq_hwioreg_umac.h b/hw/fig/v2/wcss_seq_hwioreg_umac.h
new file mode 100644
index 000000000000..2f111c881406
--- /dev/null
+++ b/hw/fig/v2/wcss_seq_hwioreg_umac.h
@@ -0,0 +1,2481 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+#ifndef WCSS_SEQ_HWIOREG_UMAC_H
+
+#include "seq_hwio.h"
+#include "wcss_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+#include "HALhwio.h"
+#else
+#include "msmhwio.h"
+#endif
+
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS                                                        (0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK                                                        0xf8000007
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK                                            0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT                                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS                                           (0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK                                            0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR                                            0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK                                       0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR                                                        0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK                    0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK                       0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT                            1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK                            0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK                                    0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT                                        12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK                                     0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT                                        11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK                                     0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT                                        10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK                                     0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT                                         9
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS                                                   (0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR                                                    0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR                                                                0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK                                 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT                                         24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK                                   0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT                                         16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK                                     0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK                                       0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT                                          0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n)                                            (0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK                                                    0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn                                                       31
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR                                                0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK                                           0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR                                                            0x1
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK                                   0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT                                       0
+
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS                                                       (0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK                                                              0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR                                                        0x00000000
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR                                                                    0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK                                                 0x2
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT                                                   1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK                                                  0x1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT                                                    0
+
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n)                                                      (0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn                                                                 63
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT                                                             0
+
+#define WBM_REG_REG_BASE                                                                                        (UMAC_BASE      + 0x00034000)
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x)                                                                        ((x) + 0x40)
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)                                                                   ((x) + 0x130)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK                                                       0x7fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT                                                           2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK                                                    0x2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT                                                      1
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)                                                                      ((x) + 0x134)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK                                0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT                                        16
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK                                          0xffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT                                               0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)                                                   ((x) + 0x138)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)                                                   ((x) + 0x13c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK                                    0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT                                             8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK                                         0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT                                            0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)                                               ((x) + 0x140)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)                                               ((x) + 0x144)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)                                               ((x) + 0x148)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)                                               ((x) + 0x14c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)                                                          ((x) + 0x150)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)                                                            ((x) + 0x24c)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                       0xffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                              8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x8000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                        27
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0x51c)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xfffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)                                                             ((x) + 0x52c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                            0x8000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                   27
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                       (0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                   (0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                       (0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                   (0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS                                                                            (0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK                                                                                  0x3f
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR                                                                             0x00000000
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK                                                                        0xffffffff
+#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR                                                                                         0x3
+#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK                                                         0x20
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT                                                            5
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK                                                         0x10
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT                                                            4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                    0x8
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                      3
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                    0x4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                      2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                             0x2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                               1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                         0x1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                           0
+
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS                                                                     (0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK                                                                     0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR                                                                      0x00000000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK                                                                 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR                                                                                  0x3
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK                                                          0xffe00000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT                                                                  21
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK                                                            0x1f0000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT                                                                  16
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK                                                                  0xf800
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT                                                                      11
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK                                                                   0x7c0
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT                                                                       6
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK                                                                    0x3e
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT                                                                       1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK                                                                       0x1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT                                                                         0
+
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                 (0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                      0x3ff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                  0x00000020
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                              0x1
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK                                                 0x200
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT                                                     9
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK                                                 0x100
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT                                                     8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                            0x80
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                               7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                            0x40
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                               6
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                     0x20
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                        5
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                  0x10
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                     4
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                     0x8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                       3
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                               0x7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                 0
+
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                   (0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK                                                                      0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn                                                                             255
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR                                                                       0x00000000
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                  0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                   0x1
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                          0
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)                                                                  ((x) + 0x3010)
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)                                                               ((x) + 0x3040)
+
+#define REO_REG_REG_BASE                                                                                               (UMAC_BASE      + 0x00038000)
+
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                                                                             ((x) + 0x0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT                                                        28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT                                                        24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT                                                        20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT                                                        16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT                                                        12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT                                                         8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT                                                         4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT                                                         0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)                                                                 ((x) + 0xc)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)                                                                 ((x) + 0x10)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS                                                          (0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR                                                           0x76043210
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK                            0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT                                    28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK                             0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT                                    24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK                              0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT                                    20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK                               0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT                                    16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK                                0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT                                    12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK                                 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT                                     8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS                                                          (0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x6666ba98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS                                                          (0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT                                    0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS                                                          (0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT                                    0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)                                                             ((x) + 0x38)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK                                       0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT                                               28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK                                        0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT                                               24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK                                         0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT                                               20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK                                          0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT                                               16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK                                           0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT                                               12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK                                            0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT                                                8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK                                             0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK                                              0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)                                                             ((x) + 0x3c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT                                              24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT                                              20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT                                              16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT                                              12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT                                               8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS                                                      (0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK                   0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT                           28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK                    0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT                           24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK                     0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT                           20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK                      0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT                           16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK                       0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT                           12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK                        0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT                            8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT                            0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS                                                      (0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK               0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT                       28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK                   0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT                          24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK                    0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT                          20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK                     0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT                          16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK                      0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT                          12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK                       0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT                           8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT                            0
+
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS                                                                         (0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK                                                                            0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR                                                                          0x00000000
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR                                                                                      0x3
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)            \
+                in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK                                                                   0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT                                                                         0
+
+#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)                                                                             ((x) + 0x6c)
+
+#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)                                                                             ((x) + 0x70)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK                                                  0x100000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT                                                        20
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK                                                          0x80000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT                                                               19
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                                    0x40000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                         18
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                                 0x3e000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                      13
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                                    0x1f00
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                         8
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                             0xff
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                                0
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                                                                       ((x) + 0x344)
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK                                                                  0xffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                                                                         8
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK                                                               0x400000
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     22
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x7d0)
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0x7d4)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                                                                            ((x) + 0x7d8)
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)                                                                        ((x) + 0x7dc)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                           0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                                   16
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK                                                               0xffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT                                                                    0
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                                                                          ((x) + 0x7e0)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0x7e4)
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0x7e8)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)                                                            ((x) + 0x7f4)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x818)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x81c)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x820)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x824)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x828)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x82c)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)                                                                     ((x) + 0x830)
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x844)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x848)
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0xc08)
+
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x8000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     27
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x8000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                                27
+
+#define HWIO_REO_R0_MISC_CFG_ADDR(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_PHYS(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_OFFS                                                                                      (0x1458)
+#define HWIO_REO_R0_MISC_CFG_RMSK                                                                                             0x1
+#define HWIO_REO_R0_MISC_CFG_POR                                                                                       0x00000000
+#define HWIO_REO_R0_MISC_CFG_POR_RMSK                                                                                  0xffffffff
+#define HWIO_REO_R0_MISC_CFG_ATTR                                                                                                   0x3
+#define HWIO_REO_R0_MISC_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x))
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK                                                                        0x1
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT                                                                          0
+
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS                                                                           (0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK                                                                                0x7ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR                                                                            0x000003ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR                                                                                        0x3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)            \
+                in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x))
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x))
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK                                                                         0x400
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT                                                                            10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK                                                                        0x200
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT                                                                            9
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK                                                                        0x100
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT                                                                            8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK                                                                         0x80
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT                                                                            7
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK                                                                         0x40
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT                                                                            6
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK                                                                         0x20
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT                                                                            5
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK                                                                         0x10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT                                                                            4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK                                                                          0x8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT                                                                            3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK                                                                          0x4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT                                                                            2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK                                                                          0x2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT                                                                            1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK                                                                          0x1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT                                                                            0
+
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS                                                                            (0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK                                                                                 0x1ff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR                                                                             0x0000002d
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR                                                                                         0x3
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK                                                             0x1fe
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT                                                                 1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK                                                                           0x1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT                                                                             0
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                                                                       ((x) + 0x1468)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                                                                       ((x) + 0x146c)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                                                                       ((x) + 0x1470)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                                                                       ((x) + 0x1474)
+
+#define HWIO_REO_R0_MISC_CTL_ADDR(x)                                                                                   ((x) + 0x14dc)
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK                                                                         0x1e00000
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT                                                                                21
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK                                                                     0x1e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT                                                                           17
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                          (0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                      (0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                          (0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                      (0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_CREDIT_ADDR(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_PHYS(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_OFFS                                                                                        (0x16d0)
+#define HWIO_REO_R0_CREDIT_RMSK                                                                                        0xffffffff
+#define HWIO_REO_R0_CREDIT_POR                                                                                         0x00000000
+#define HWIO_REO_R0_CREDIT_POR_RMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_ATTR                                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_ADDR(x))
+#define HWIO_REO_R0_CREDIT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x))
+#define HWIO_REO_R0_CREDIT_VAL_BMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_VAL_SHFT                                                                                             0
+
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS                                                                        (0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK                                                                               0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR                                                                         0x00000002
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK                                                                        0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT                                                                          0
+
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS                                                                         (0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR                                                                          0x00000000
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR                                                                                      0x1
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x))
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT                                                                              0
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK                                                 0x2000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT                                                     13
+
+#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_OFFS                                                                                   (0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_RMSK                                                                                          0x7
+#define HWIO_REO_R0_LPM_FW_CTRL_POR                                                                                    0x00000000
+#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK                                                                               0xffffffff
+#define HWIO_REO_R0_LPM_FW_CTRL_ATTR                                                                                                0x3
+#define HWIO_REO_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                           0x4
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                             2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                           0x2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                             1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                                0x1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                                  0
+
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS                                                                (0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK                                             0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT                                                     28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK                                              0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT                                                     24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK                                               0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT                                                     20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK                                                0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT                                                     16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK                                                 0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT                                                     12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK                                                  0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT                                                      8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT                                                      0
+
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS                                                                (0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK                                            0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT                                                    28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK                                             0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT                                                    24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK                                              0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT                                                    20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK                                               0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT                                                    16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK                                                0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT                                                    12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK                                                 0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT                                                     8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT                                                      0
+
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS                                                                             (0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK                                                                                   0x3f
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR                                                                              0x00000000
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR                                                                                          0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x))
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK                                                         0x20
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT                                                            5
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK                                                                   0x10
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT                                                                      4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK                                                                0x8
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT                                                                  3
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK                                                            0x4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT                                                              2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK                                                                      0x2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT                                                                        1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK                                                                  0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT                                                                    0
+
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS                                                         (0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK                                                         0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR                                                          0x00000000
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR                                                                      0x3
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)            \
+                in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK                                                   0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT                                                            0
+
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                        (0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                              0x7f
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR                                                                         0x00000000
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                                     0x1
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                                   0x40
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                      6
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                                   0x20
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                      5
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                         0x10
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                            4
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                            0x8
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                              3
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                      0x7
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                        0
+
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                          (0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK                                                                             0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn                                                                                    255
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR                                                                              0x00000000
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR                                                                                          0x1
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                        0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                                 0
+
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                                                                             ((x) + 0x3028)
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                                                                            ((x) + 0x3070)
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                                                                            ((x) + 0x3074)
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                                                                            ((x) + 0x3078)
+
+#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)                                                                            ((x) + 0x30b8)
+
+#define TQM_REG_REG_BASE                                                                                         (UMAC_BASE      + 0x0003c000)
+#define TQM_REG_REG_BASE_SIZE                                                                                    0x4000
+
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK                                                             0x80
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT                                                                7
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK                                                    0x40
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT                                                       6
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK                                                     0x20
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT                                                        5
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK                                                           0x10
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT                                                              4
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK                                                          0x8
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT                                                            3
+
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x8000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT                                                           27
+
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS                                                           (0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS                                                           (0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                    (0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                (0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                    (0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                (0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK                                                          0x80000000
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT                                                                  31
+
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK                                                            0x8000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT                                                                15
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK                                                        0x4000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT                                                            14
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK                                                                0x2000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT                                                                    13
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK                                                            0x1000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT                                                                12
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK                                               0x800
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT                                                  11
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK                                               0x400
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT                                                  10
+
+#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS                                                                             (0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK                                                                                    0xf
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR                                                                              0x00000000
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK                                                                         0xffffffff
+#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR                                                                                          0x3
+#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                     0x8
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                       3
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                     0x4
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                       2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                              0x2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                                1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                          0x1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                            0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS                                                                          (0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK                                                                             0x1ffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR                                                                           0x00000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)            \
+                in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK                                             0x2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT                                               1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK                                                     0x1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT                                                       0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK                                                     0x20000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT                                                             29
+
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS                                                     (0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR                                                      0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR                                                                  0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT                                                        0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS                                              (0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS                                              (0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS                                                                           (0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK                                                                                0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR                                                                            0x00000710
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR                                                                                        0x3
+#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)            \
+                in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK                                                                          0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT                                                                              0
+
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS                                                                   (0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK                                                                        0x1ff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR                                                                    0x000001fe
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK                                          0x100
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT                                              8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK                                            0x80
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT                                               7
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK                                            0x40
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT                                               6
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK                                            0x20
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT                                               5
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK                                            0x10
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT                                               4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK                                             0x8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT                                               3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK                                             0x4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT                                               2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK                                             0x2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT                                               1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK                                              0x1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT                                                0
+
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS                                                                  (0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK                                                                    0x3fefff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR                                                                   0x00080170
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR                                                                               0x3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK                                            0x200000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT                                                  21
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK                                         0x100000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT                                               20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK                                      0x80000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT                                           19
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK                                             0x40000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT                                                  18
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK                                                    0x20000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT                                                         17
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK                                                        0x10000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT                                                             16
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK                                          0x8000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT                                              15
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK                                                 0x4000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT                                                     14
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK                                                0x2000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT                                                    13
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK                                                     0x800
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT                                                        11
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK                                                      0x400
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT                                                         10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK                                                0x200
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT                                                    9
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK                                             0x100
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT                                                 8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK                                               0x80
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT                                                  7
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK                                                       0x40
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT                                                          6
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK                                                  0x20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT                                                     5
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK                                                 0x10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT                                                    4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK                                               0x8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT                                                 3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK                                                 0x4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT                                                   2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK                                               0x2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT                                                 1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK                                             0x1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT                                               0
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS                                                                          (0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK                                                                          0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR                                                                           0x00000000
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT                                                           0
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS                                                                          (0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK                                                                             0x7ffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR                                                                           0x00011100
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                              0x40000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                   18
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                           0x3e000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                13
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                              0x1f00
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                   8
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                       0xff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                          0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS                                                   (0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR                                                    0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK                                               0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR                                                                0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK                                              0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT                                                 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS                                                    (0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR                                                     0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR                                                                 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT                                                   0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS                                                (0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK                                                      0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR                                                 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR                                                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK                                           0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS                                                 (0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK                                                 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR                                                  0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR                                                              0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK                                       0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT                                                0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS                                              (0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK                                              0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR                                               0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR                                                           0x3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK                                    0xffff0000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT                                            16
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK                            0xfff0
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT                                 4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK                                  0x8
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT                                    3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK                                       0x4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT                                         2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT                               1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK                                         0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT                                           0
+
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS                                                                       (0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS                                                                      (0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK                                                                         0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR                                                                       0x00000000
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR                                                                                   0x3
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK                                                             0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                   0
+
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS                                                                       (0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS                                                                 (0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK                                                                        0xf
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR                                                                  0x00000000
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR                                                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x))
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK                                                0x8
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT                                                  3
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x4
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT                                                   2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT                                                   1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT                                                0
+
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS                                                                     (0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK                                                                     0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR                                                                      0x00000000
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR                                                                                  0x1
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK                                                               0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT                                                                        0
+
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS                                                                  (0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR                                                                   0x00000000
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR                                                                               0x1
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK                                                            0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT                                                                     0
+
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                  (0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                        0xff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                   0x00000000
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                               0x1
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                             0x80
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                             0x40
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                6
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                      0x20
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                         5
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                   0x10
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                      4
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                      0x8
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                        3
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                0x7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                  0
+
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                    (0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn                                                                              127
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR                                                                        0x00000000
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                    0x1
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                           0
+
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS                                                                 (0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS                                                                 (0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT                                                           7
+
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK                                             0x40
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT                                                6
+
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS                                                (0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK                                                       0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR                                                 0x0000000a
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK                                                 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT                                                   0
+
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS                                                                   (0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK                                                                         0x1f
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK                                                   0x10
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT                                                      4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK                                                    0x8
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT                                                      3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK                                                    0x4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT                                                      2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK                                                    0x2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT                                                      1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_LINK_ID_ADDR(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_PHYS(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_OFFS                                                                       (0x170)
+#define HWIO_UMCMN_R0_LINK_ID_RMSK                                                                           0xffff
+#define HWIO_UMCMN_R0_LINK_ID_POR                                                                        0x000052c8
+#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_LINK_ID_ATTR                                                                                    0x3
+#define HWIO_UMCMN_R0_LINK_ID_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x))
+#define HWIO_UMCMN_R0_LINK_ID_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m)
+#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v)
+#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x))
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK                                                               0x80
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT                                                                  7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK                                                               0x40
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT                                                                  6
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK                                                               0x38
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT                                                                  3
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK                                                                0x7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK                                                    0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT                                                        14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK                                                0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT                                                    13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK                                                    0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT                                                        12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK                                                     0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT                                                        11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK                                                     0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT                                                        10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK                                                     0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT                                                         9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK                                                     0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT                                                         8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK                                                       0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT                                                          7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK                                                       0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT                                                          6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK                                                       0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT                                                          5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK                                                       0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT                                                          4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK                                                         0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT                                                           3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK                                                        0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT                                                          2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK                                                         0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT                                                           1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK                                                        0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT                                                          0
+
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS                                                             (0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK                                                                    0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR                                                              0x00000000
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK                                                         0xffffffff
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR                                                                          0x3
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS                                                (0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK                                                   0x1ffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR                                                 0x00000000
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK                   0x1fe00
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT                         9
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK                    0x1fe
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT                        1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK                         0x1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT                           0
+
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                             0x1ff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK                                           0x100
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT                                               8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK                                            0x80
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT                                               7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK                                            0x40
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT                                               6
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK                                            0x20
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT                                               5
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n)                                                 (0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn                                                             7
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR                                                     0x00000000
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR                                                                 0x3
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)                \
+                in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT                                                         0
+
+#define MAC_TCL_REG_REG_BASE                                                                           (UMAC_BASE      + 0x00044000)
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                                                     ((x) + 0x20)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK                                  0x800000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT                                        23
+
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK                                      0x200000
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT                                            21
+
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n)                                                      ((base) + 0X74 + (0x4*(n)))
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT                                                   17
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT                                                     14
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT                                                          12
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT                                                        8
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT                                                       7
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT                                                          3
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT                                                            1
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT                                                                   0
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n)                                                        ((base) + 0X174 + (0x4*(n)))
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK                                                                0xffffffff
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK                                              0x800000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT                                                    23
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK                                                        0x40
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT                                                           6
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK                                                    0x20
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT                                                       5
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS                                                              (0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK                                                                     0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR                                                               0x00000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK                                                          0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR                                                                           0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)            \
+                in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK                                                        0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT                                                          1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK                                                        0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT                                                          0
+
+#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS                                                                   (0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK                                                                          0x7
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                           0x4
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                             2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                           0x2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                             1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x8c8)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0x8cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK                                                0xfffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                                                            ((x) + 0x8d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                                                          ((x) + 0x8d8)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                                                   ((x) + 0x8e4)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                                                   ((x) + 0x8e8)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                        ((x) + 0x8f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                         16
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                       0x7fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                            0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                        ((x) + 0x8fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                 0xffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0x910)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0x914)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0x918)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x940)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                             0x8000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                    27
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                              (0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                          (0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                              (0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                          (0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                              0x7f
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                   0x40
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                      6
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                   0x20
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                      5
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                                  0x10000
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                       16
+
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                             0x10000
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                  16
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS                                                                  (0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK                                                                       0x1ff
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR                                                                   0x00000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK                                                              0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR                                                                               0x3
+#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                                  0x100
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                                      8
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK                                                           0xc0
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT                                                              6
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK                                                        0x3f
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT                                                           0
+
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                          (0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK                                                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn                                                                    511
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR                                                              0x00000000
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR                                                                          0x1
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                        0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                 0
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                                                            ((x) + 0x2000)
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                                                            ((x) + 0x2004)
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                                                            ((x) + 0x2008)
+
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                               0x1000000
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                      24
+
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+
+#endif
diff --git a/hw/fig/v2/wcss_version.h b/hw/fig/v2/wcss_version.h
new file mode 100644
index 000000000000..6a417dcd42e5
--- /dev/null
+++ b/hw/fig/v2/wcss_version.h
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#define WCSS_VERSION 3175

From b2701fcc4def8040265cab44039e750dfe3350df Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 12 Dec 2025 18:01:39 -0800
Subject: [PATCH 087/290] fw-api: CL 31181068 - update fw common interface
 files

Change-Id: I7d934e3ff23f2c6cc3c8aa6f572ae4a446fc0bb0
CRs-Fixed: 3830439
---
 fw/htt.h       |   2 +
 fw/htt_stats.h | 533 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 535 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index dd992e5a4e0f..2bf685b12aa2 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -883,6 +883,8 @@ typedef enum {
     HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG               = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */
     HTT_STATS_OPTIONAL_CONFIGS_TAG                  = 232, /* htt_stats_optional_configs_tlv */
     HTT_STATS_PDEV_SAM_TAG                          = 233, /* htt_stats_pdev_sam_tlv */
+    HTT_STATS_FTM_TAG                               = 234, /* htt_stats_ftm_tlv */
+    HTT_STATS_PDEV_FTM_TPCCAL_EXT_TAG               = 235, /* htt_stats_pdev_ftm_tpccal_ext_tlv */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 4ccf44f631ec..993385b7c706 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -866,6 +866,22 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_PDEV_SAM = 78,
 
+    /** HTT_DBG_EXT_STATS_FTM
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_ftm_tlv
+     */
+    HTT_DBG_EXT_STATS_FTM = 79,
+
+    /** HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *    - htt_stats_pdev_ftm_tpccal_ext_tlv
+     */
+    HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT = 80,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -10727,6 +10743,8 @@ typedef struct {
  */
 #define HTT_MAX_TPCCAL_STATS 25
 #define HTT_STATS_TPC_CAL_MAX_NUM_POINTS 64
+#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT 16
+#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT 10
 
 typedef struct {
     htt_tlv_hdr_t   tlv_hdr;
@@ -10859,8 +10877,186 @@ typedef struct {
             };
         };
     } tpccal_stats_postproc;
+
+    /* cal DB timeout in ms */
+    A_UINT32 calDbTimeoutMs;
+
+    struct{
+        /* tgtMeasPwr uses dBm units */
+        A_INT32  tgtMeasPwr[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT];
+        A_UINT32 tgtPdadc[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT];
+    } tpcTargets;
 } htt_stats_pdev_ftm_tpccal_tlv;
 
+
+#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_M 0x000000ff
+#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_S 0
+
+#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_PDADC_LAST_IDX_M) >> \
+     HTT_STATS_TPCCAL_PDADC_LAST_IDX_S)
+
+#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_M 0x000000ff
+#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_S 0
+
+#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_PDADC_NUMGAIN_M) >> \
+     HTT_STATS_TPCCAL_PDADC_NUMGAIN_S)
+
+#define HTT_STATS_TPCCAL_PDADC_BAND_M 0x000000ff
+#define HTT_STATS_TPCCAL_PDADC_BAND_S 0
+
+#define HTT_STATS_TPCCAL_PDADC_BAND_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_PDADC_BAND_M) >> \
+     HTT_STATS_TPCCAL_PDADC_BAND_S)
+
+#define HTT_STATS_TPCCAL_PDADC_CHANNEL_M 0x00ffff00
+#define HTT_STATS_TPCCAL_PDADC_CHANNEL_S 8
+
+#define HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_PDADC_CHANNEL_M) >> \
+     HTT_STATS_TPCCAL_PDADC_CHANNEL_S)
+
+#define HTT_STATS_TPCCAL_PDADC_CHAIN_M 0xff000000
+#define HTT_STATS_TPCCAL_PDADC_CHAIN_S 24
+
+#define HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_PDADC_CHAIN_M) >> \
+     HTT_STATS_TPCCAL_PDADC_CHAIN_S)
+
+#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M 0x000000ff
+#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S 0
+
+#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M) >> \
+     HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S)
+
+#define HTT_STATS_TPCCAL_RES_PDADC_VAL_M 0x0000ff00
+#define HTT_STATS_TPCCAL_RES_PDADC_VAL_S 8
+
+#define HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_RES_PDADC_VAL_M) >> \
+     HTT_STATS_TPCCAL_RES_PDADC_VAL_S)
+
+#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M 0x0000ffff
+#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S 0
+
+#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) \
+    (((_var) & HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M) >> \
+     HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S)
+
+#define HTT_STATS_TPC_CAL_PDADC_BUF_LEN 3
+
+#define  HTT_STATS_FTM_TPCCAL_CALDATA   (1 << 0)
+#define  HTT_STATS_FTM_TPCCAL_CALINFO   (1 << 1)
+#define  HTT_STATS_FTM_TPCCAL_CALERROR  (1 << 2)
+
+#define  HTT_STATS_FTM_TPCCAL_DONE_MASK (1 << 7)
+
+#define  HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED  (1 << 16)
+#define  HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR   (1 << 17)
+#define  HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18)
+#define  HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED   (1 << 19)
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+
+    /*
+     * calStatus can be intrepreted with the below values:
+     *   TPCCAL_CALDATA                                 (1 << 0)
+     *   TPCCAL_CALINFO                                 (1 << 1)
+     *   TPCCAL_CALERROR                                (1 << 2)
+     *   bits 6:4 - reserved
+     *   TPCCAL_DONE_MASK                               (1 << 7)
+     *   bits 15:8 - reserved
+     *   TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED  (1 << 16)
+     *   TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR   (1 << 17)
+     *   TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18)
+     *   TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED   (1 << 19)
+     *   bits 31:20 - reserved
+     */
+    A_UINT32 calStatus;
+
+    /* dword__tpccal_pdadc_last_idx:
+     * Hold the last updated index for pdadc buffer which holds
+     * band,chain,chanIdx,gainIdx for pdadc non-linearity
+     * BIT [7 : 0]   :- tpcccal_pdadc_last_idx
+     * BIT [31 : 8]  :- rsvd
+     */
+    union {
+        A_UINT32 dword__tpccal_pdadc_last_idx;
+        struct {
+            A_UINT32 tpccal_pdadc_last_idx:8,
+                     rsvd:24;
+        };
+    };
+
+    struct {
+        /* dword__tpccal_pdadc_numgain:
+         * Hold the number of gainIdx for band for which PDADC
+         * non-linearity is observed
+         * BIT [7 : 0]   :- tpccal_pdadc_numgain
+         * BIT [31 : 8]  :- rsvd1
+         */
+        union {
+            A_UINT32 dword__tpccal_pdadc_numgain;
+            struct {
+                A_UINT32 tpccal_pdadc_numgain:8,
+                         rsvd1:24;
+            };
+        };
+
+        /*
+         * dword__band_channel_chain:
+         * band, channel, chain for which pdadc is non-linear
+         * BIT [7 : 0]   :- band
+         * BIT [23 : 8]  :- channel
+         * BIT [31 : 24] :- chain
+         */
+        union {
+            A_UINT32 dword__band_channel_chain;
+            struct {
+                A_UINT32 band:8,
+                         channel:16,
+                         chain:8;
+            };
+        };
+    } tpccal_stats_pdadc[HTT_STATS_TPC_CAL_PDADC_BUF_LEN];
+
+    struct {
+        /* dword__calres_gainIdx_pdadc:
+         * holds pdadc, gainindex from tpcCalResult for
+         * band, channel, chain, gainIdx for which pdadc is non-linear
+         * dword__calres_gainIdx_pdadc
+         * BIT [7 : 0]  :- gainIdx
+         * BIT [15 : 8] :- pdadc
+         * BIT [31 : 16] :- rsvd2
+         */
+        union {
+            A_UINT32 dword__calres_gainIdx_pdadc;
+            struct {
+                A_UINT32 gainIdx:8,
+                         pdadc:8,
+                         rsvd2:16;
+            };
+        };
+
+        /*
+         * dword__measPwr:
+         * BIT [15 : 0]  :- measPwr
+         * BIT [31 : 16] :- rsvd3
+         */
+        union {
+            A_INT32 dword__measPwr;
+            struct {
+                A_INT32 measPwr:16, /* dBm units */
+                        rsvd3:16;
+            };
+        };
+    } tpccal_stats_tpcCalResult[HTT_STATS_TPC_CAL_PDADC_BUF_LEN][HTT_STATS_TPC_CAL_MAX_NUM_POINTS];
+} htt_stats_pdev_ftm_tpccal_ext_tlv;
+
+
 #define HTT_DLPAGER_STATS_MAX_HIST            10
 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF
 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0
@@ -11230,6 +11426,13 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv;
         ((_var) |= ((_val) << HTT_STATS_ANI_MODE_S)); \
     } while (0)
 
+#define HTT_STATS_CURR_EANI_MODE_M 0x000000ff
+#define HTT_STATS_CURR_EANI_MODE_S 0
+
+#define HTT_STATS_CURR_EANI_MODE_GET(_var) \
+    (((_var) & HTT_STATS_CURR_EANI_MODE_M) >> \
+     HTT_STATS_CURR_EANI_MODE_S)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** per chain hw noise floor values in dBm */
@@ -11300,6 +11503,36 @@ typedef struct {
                 reserved: 24;
         };
     };
+
+    /* dl_max_ANI:
+     * Maximum ANI level that would be allowable for algorithm
+     * to choose the desense levels and its in dB units,
+     * higher values indicating more noise interference/more desense.
+     */
+    A_INT32 dl_max_ANI;
+
+    /* Minimum RSSI of connected clients - dBm units */
+    A_INT32 ani_dl_max_for_rssi;
+
+    /*
+     * BIT [ 7 :  0]   :- curEANIMode
+     * BIT [31 :  8]   :- rsvd
+     *
+     * curEANIMode:
+     * EANI_MODE_MIN_DESENSE = 0,
+     * EANI_MODE_MAX_DESENSE = 1,
+     * EANI_MODE_DEFAULT_DESENSE = 2,
+     * EANI_MODE_MAX,
+     * EANI_MODE_TYPE_INVALID = 0xFF
+     */
+    union {
+        A_UINT32 dword_curEANIMode;
+        struct {
+            A_UINT32
+                curEANIMode: 8,
+                rsvd: 24;
+        };
+    };
 } htt_stats_phy_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
@@ -12065,6 +12298,306 @@ typedef struct {
     ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8))
 
 
+/* FTM STATS */
+/* ================= dword_txparams ================= */
+#define HTT_STATS_XTAL_GAIN_IDX_M        0x000000FF
+#define HTT_STATS_XTAL_GAIN_IDX_S        0
+#define HTT_STATS_GET_XTAL_GAIN_IDX(word) \
+    (((word) & HTT_STATS_XTAL_GAIN_IDX_M) >> HTT_STATS_XTAL_GAIN_IDX_S)
+
+#define HTT_STATS_INFINITE_BURST_MODE_M  0x0000FF00
+#define HTT_STATS_INFINITE_BURST_MODE_S  8
+#define HTT_STATS_GET_INFINITE_BURST_MODE(word) \
+    (((word) & HTT_STATS_INFINITE_BURST_MODE_M) >> HTT_STATS_INFINITE_BURST_MODE_S)
+
+#define HTT_STATS_FTM_MODE_M             0x00FF0000
+#define HTT_STATS_FTM_MODE_S             16
+#define HTT_STATS_GET_FTM_MODE(word) \
+    (((word) & HTT_STATS_FTM_MODE_M) >> HTT_STATS_FTM_MODE_S)
+
+#define HTT_STATS_SIFS_US_M              0xFF000000
+#define HTT_STATS_SIFS_US_S              24
+#define HTT_STATS_GET_SIFS_US(word) \
+    (((word) & HTT_STATS_SIFS_US_M) >> HTT_STATS_SIFS_US_S)
+
+/* ================= dword_txparams_ext_1 ================= */
+#define HTT_STATS_AGG_STATUS_M           0x00000001
+#define HTT_STATS_AGG_STATUS_S           0
+#define HTT_STATS_GET_AGG_STATUS(word) \
+    (((word) & HTT_STATS_AGG_STATUS_M) >> HTT_STATS_AGG_STATUS_S)
+
+#define HTT_STATS_DPD_FLAG_M             0x00000002
+#define HTT_STATS_DPD_FLAG_S             1
+#define HTT_STATS_GET_DPD_FLAG(word) \
+    (((word) & HTT_STATS_DPD_FLAG_M) >> HTT_STATS_DPD_FLAG_S)
+
+/* Bits [9:2] -> 8-bit field */
+#define HTT_STATS_PPDU_DUR_LAST_IDX_M    0x000003FC
+#define HTT_STATS_PPDU_DUR_LAST_IDX_S    2
+#define HTT_STATS_GET_PPDU_DUR_LAST_IDX(word) \
+    (((word) & HTT_STATS_PPDU_DUR_LAST_IDX_M) >> HTT_STATS_PPDU_DUR_LAST_IDX_S)
+
+/* ================= dword_txparams_ext_2 ================= */
+#define HTT_STATS_TARGET_TX_DUTY_M       0x000000FF
+#define HTT_STATS_TARGET_TX_DUTY_S       0
+#define HTT_STATS_GET_TARGET_TX_DUTY(word) \
+    (((word) & HTT_STATS_TARGET_TX_DUTY_M) >> HTT_STATS_TARGET_TX_DUTY_S)
+
+#define HTT_STATS_PPDU_TYPE_M            0x0000FF00
+#define HTT_STATS_PPDU_TYPE_S            8
+#define HTT_STATS_GET_PPDU_TYPE(word) \
+    (((word) & HTT_STATS_PPDU_TYPE_M) >> HTT_STATS_PPDU_TYPE_S)
+
+#define HTT_STATS_NUM_USERS_OFDMA_M      0x00FF0000
+#define HTT_STATS_NUM_USERS_OFDMA_S      16
+#define HTT_STATS_GET_NUM_USERS_OFDMA(word) \
+    (((word) & HTT_STATS_NUM_USERS_OFDMA_M) >> HTT_STATS_NUM_USERS_OFDMA_S)
+
+#define HTT_STATS_NUM_USERS_OFDMA_EHT_M  0xFF000000
+#define HTT_STATS_NUM_USERS_OFDMA_EHT_S  24
+#define HTT_STATS_GET_NUM_USERS_OFDMA_EHT(word) \
+    (((word) & HTT_STATS_NUM_USERS_OFDMA_EHT_M) >> HTT_STATS_NUM_USERS_OFDMA_EHT_S)
+
+/* ================= dword_TimingStats ================= */
+#define HTT_STATS_TLV_TIMESTAMP_CNT_M    0x000000FF
+#define HTT_STATS_TLV_TIMESTAMP_CNT_S    0
+#define HTT_STATS_GET_TLV_TIMESTAMP_CNT(word) \
+    (((word) & HTT_STATS_TLV_TIMESTAMP_CNT_M) >> HTT_STATS_TLV_TIMESTAMP_CNT_S)
+
+/* ================= dword_TlvcmdInfo ================= */
+#define HTT_STATS_TLV_CMD_ENTRY_M        0x0000FFFF
+#define HTT_STATS_TLV_CMD_ENTRY_S        0
+#define HTT_STATS_GET_TLV_CMD_ENTRY(word) \
+    (((word) & HTT_STATS_TLV_CMD_ENTRY_M) >> HTT_STATS_TLV_CMD_ENTRY_S)
+
+#define HTT_STATS_TLV_CAL_TYPE_M         0x00FF0000
+#define HTT_STATS_TLV_CAL_TYPE_S         16
+#define HTT_STATS_GET_TLV_CAL_TYPE(word) \
+    (((word) & HTT_STATS_TLV_CAL_TYPE_M) >> HTT_STATS_TLV_CAL_TYPE_S)
+
+/* ================= dword_TlvCmdParsing ================= */
+#define HTT_STATS_FLAG_TLV_CMD_PARSING_M 0x00000001
+#define HTT_STATS_FLAG_TLV_CMD_PARSING_S 0
+#define HTT_STATS_GET_FLAG_TLV_CMD_PARSING(word) \
+    (((word) & HTT_STATS_FLAG_TLV_CMD_PARSING_M) >> HTT_STATS_FLAG_TLV_CMD_PARSING_S)
+
+#define HTT_STATS_NUM_TLV_CMD_DROPPED_M  0x000001FE
+#define HTT_STATS_NUM_TLV_CMD_DROPPED_S  1
+#define HTT_STATS_GET_NUM_TLV_CMD_DROPPED(word) \
+    (((word) & HTT_STATS_NUM_TLV_CMD_DROPPED_M) >> HTT_STATS_NUM_TLV_CMD_DROPPED_S)
+
+/* ================= dword_rxGaincalMaxNumchan ================= */
+#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M     0x000000FF
+#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S     0
+#define HTT_STATS_GET_RXGAINCAL_MAX_NUMCHAN(word) \
+    (((word) & HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M) >> HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S)
+
+/* ================= dword_rxgainCalRefISS ================= */
+#define HTT_STATS_RXGAINCAL_REF_ISS_M         0x000000FF
+#define HTT_STATS_RXGAINCAL_REF_ISS_S         0
+#define HTT_STATS_GET_RXGAINCAL_REF_ISS(word) \
+    (((word) & HTT_STATS_RXGAINCAL_REF_ISS_M) >> HTT_STATS_RXGAINCAL_REF_ISS_S)
+
+
+#define HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT 50
+#define HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT 10
+#define HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2 16
+#define HTT_STATS_FTM_FPC_TIMING_SHIFT    32ULL
+
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+
+    struct {
+        /* TX PARAMS
+         *
+         * BIT [7 : 0]   :- gain idx used for xtal cal CW tone
+         * BIT [15 : 8]  :- infinite_bursting_mode
+         * BIT [23 : 16] :- ftm_mode
+         * BIT [31 : 24] :- sifs_us
+         */
+        union {
+            A_UINT32 dword_txparams;
+            struct {
+                A_UINT32
+                     xtalCal_gain_idx:       8,
+                     infinite_bursting_mode: 8,
+                     ftm_mode:               8,
+                     sifs_us:                8;
+            };
+        };
+
+        /* dword_txparams_ext_1
+         * BIT [0]       :- agg_status
+         * BIT [1]       :- dpdFlag
+         * BIT [9 : 2]   :- ppdu_dur_buf_last_idx (last idx of ppdu duration
+         *                  circular buffer - 'actual_ppdu_dur_us')
+         * BIT [31 : 10] :- rsvd
+         */
+        union {
+            A_UINT32 dword_txparams_ext_1;
+            struct {
+                A_UINT32
+                    agg_status:             1,
+                    dpdFlag:                1,
+                    ppdu_dur_buf_last_idx:  8,
+                    rsvd:                  22;
+            };
+        };
+
+        /* Circular buffer containing actual ppdu duration_us */
+        A_UINT32 actual_ppdu_dur_us[HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT];
+
+        A_UINT32 target_fes_duration_us;  /* TX time */
+        A_UINT32 target_txoff_duration_us; /* TX OFF duration */
+        A_UINT32 phy_mode; /* PHY mode selected */
+        A_UINT32 pkt_len_post_truncation; /* Packet length post truncation */
+
+        /* dword_txparams_ext_2
+         * BIT [7 : 0]   :- target_tx_duty (TX ON ratio)
+         * BIT [15 : 8]  :- PpduType
+         * BIT [23 : 16] :- numUsers_ofdmaTonePlan
+         * BIT [31 : 24] :- numUsers_ofdmaTonePlanEHT
+         */
+        union {
+            A_UINT32 dword_txparams_ext_2;
+            struct {
+                A_UINT32
+                    target_tx_duty:            8,
+                    PpduType:                  8,
+                    numUsers_ofdmaTonePlan:    8,
+                    numUsers_ofdmaTonePlanEHT: 8;
+            };
+        };
+    } tx_params;
+
+    /* CALIBRATION VERIFICATION FW ONLY TIMING STATS (uS) */
+    struct {
+        /*
+         * ts_FPC - 64 bits,
+         * ts_FPC_low  - bits[31:0] of 64 bits
+         * ts_FPC_high - bits[63:32] of 64 bits
+         */
+        A_UINT32 ts_FPC_low;
+        A_UINT32 ts_FPC_high;
+
+        A_UINT32 ts_calDbRegenTime; /* calDb regeneration time for FPC */
+        A_UINT32 ts_OPC;
+        A_UINT32 ts_xtalcal;
+        A_UINT32 ts_rxgaincal;
+        A_UINT32 ts_nfcal;
+        A_UINT32 ts_tx_ver;
+        A_UINT32 ts_rx_ver;
+
+        /* Overall channel change time for tx/rx verification */
+        A_UINT32 tx_ver_OverallChanChangeTiming_ts;
+        A_UINT32 rx_ver_OverallChanChangeTiming_ts;
+
+        /* dword_TimingStats:
+         * Number of TLVs for which TlvCmdInfo to be dumped
+         * BIT [7:0]      :- TlvTimeStampCntFilled
+         * BIT [31 :8]   :- rsvd1
+         */
+        union {
+            A_UINT32 dword_TimingStats;
+            struct {
+                A_UINT32
+                    TlvTimeStampCntFilled:  8,
+                    rsvd1:                 24;
+            };
+        };
+
+        /* TLV cmd and timing info */
+        struct {
+            A_UINT32 TlvTimeStamp_delta; /* Time of TLV CMD entry in ts */
+
+            /* dword_TlvcmdInfo
+             * TLV CMD ID and calType corresponding to TLV
+             * BIT [15:0]       :- TlvCmd_entry - TLV cmd ID
+             * BIT [23 : 16]    :- TlvCalType - calType
+             * BIT [31 : 24]    :- rsvd2
+             */
+            union {
+                A_UINT32 dword_TlvcmdInfo;
+                struct {
+                    A_UINT32
+                        TlvCmd_entry: 16,
+                        TlvCalType:    8,
+                        rsvd2:         8;
+                };
+            };
+        } TlvCmdTimingInfo[HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT];
+    } timingStats;
+
+    /* TLV params */
+    struct {
+        /* Total number of TLV parameters for last TLV */
+        A_UINT32 LastTlv_numParams;
+
+        /* Number of TLV params parsed for last TLV */
+        A_UINT32 LastTlv_numParamsParsed;
+
+        A_UINT32 LastTlvCmd; /* Last TLV CMD being executed */
+        A_UINT32 LastTlvRspCmd; /* Last TLV CMD for which RSP is sent */
+
+        /* dword_TlvCmdParsing
+         * BIT [0]      :- flagTlvCmdParsing - Flag indicating entire TLV CMD
+         *                 being parsed/dropped
+         * BIT [8 : 1]  :- numTlvCmdDropped  - count of entire TLV CMDs dropped
+         * BIT [31 : 9] :- rsvd3
+         */
+        union {
+            A_UINT32 dword_TlvCmdParsing;
+            struct {
+                A_UINT32
+                    flagTlvCmdParsing:  1,
+                    numTlvCmdDropped:   8,
+                    rsvd3:             23;
+            };
+        };
+
+        A_UINT32 LastTlvCmdDropped; /* Last TLV CMD dropped */
+    } tlvParams;
+
+    /* RX gain cal params */
+    struct{
+        /* dword_rxGaincalMaxNumchan
+         * Num channels for which goodPktCnt for RX gain cal to be dumped
+         * BIT [7 : 0]     :- rxGaincalMaxNumchan
+         * BIT [31 : 8]    :- rsvd4
+         */
+        union {
+            A_UINT32 dword_rxGaincalMaxNumchan;
+            struct {
+                A_UINT32
+                    rxGaincalMaxNumchan:  8,
+                    rsvd4:               24;
+            };
+        };
+
+        A_UINT32 goodPktCnt[HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2];
+
+        /* dword_rxgainCalRefISS
+         * Reference Input Signal Strength for Rx gain cal in dBm
+         * BIT [7 : 0]     :- RxGainCal_refISS
+         * BIT [31 : 8]    :- rsvd
+         */
+        union {
+            A_INT32 dword_rxgainCalRefISS;
+            struct {
+                A_INT32
+                    RxGainCal_refISS:  8,
+                    rsvd5:            24;
+            };
+        };
+    } rxGainCalParams;
+
+    /* Miscellaneous params */
+
+    A_UINT32 bdReadRsp;
+} htt_stats_ftm_tlv;
+
+
 typedef struct {
     union {
         A_UINT32 word32;

From b4d8fce29fbb75e7dc14575b0c3dd86086672ac3 Mon Sep 17 00:00:00 2001
From: jinbao liu <quic_jinbliu@quicinc.com>
Date: Mon, 15 Dec 2025 15:47:16 +0800
Subject: [PATCH 088/290] qcacld-3.0: Validate fse metadata before aggregation
 of FISA flow

When aggregation of a flow is in progress, there can be case
when the HW flow table entry match may fail for few packets.
Such packets, even though belong to a flow already present in
flow table, are routed independently to any RX ring.

When software checks this rx ring ID, from the independently routed
packet and compares the ring ID against the one which is assigned
for the flow, there will be a mismatch leading to unwanted behaviour.

Hence, always validate the fse_metadata before taking any
action on the basis of rx ring ID mismatch. The non-matching
packets, with invalid fse metadata can be submitted to network
stack independently.

Change-Id: Ia95f20ef1050bc981b2d22571b612fd2af6f6a65
CRs-Fixed: 3272353
---
 core/dp/txrx3.0/dp_fisa_rx.c | 24 +++++++++++++++++++++---
 core/dp/txrx3.0/dp_rx_fst.c  | 18 ++++++++++++++++++
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/core/dp/txrx3.0/dp_fisa_rx.c b/core/dp/txrx3.0/dp_fisa_rx.c
index d0d84e40a9ce..835f795e7736 100644
--- a/core/dp/txrx3.0/dp_fisa_rx.c
+++ b/core/dp/txrx3.0/dp_fisa_rx.c
@@ -1677,15 +1677,33 @@ static int dp_add_nbuf_to_fisa_flow(struct dp_rx_fst *fisa_hdl,
 		fse_metadata =
 			hal_rx_msdu_fse_metadata_get(hal_soc_hdl, rx_tlv_hdr);
 		cce_match = hal_rx_msdu_cce_match_get(rx_tlv_hdr);
-		if (cce_match || (fisa_hdl->del_flow_count &&
-		    fse_metadata != fisa_flow->metadata)) {
+		/*
+		 * For two cases the fse_metadata will not match the metadata
+		 * from the fisa_flow_table entry
+		 * 1) Flow has been evicted (lru deletion), and this packet is
+		 * one of the few packets pending in the rx ring from the prev
+		 * flow
+		 * 2) HW flow table match fails for some packets in the
+		 * currently active flow.
+		 */
+		if (cce_match) {
 			dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id);
+			DP_STATS_INC(fisa_hdl, reo_mismatch.allow_cce_match,
+				     1);
+			return FISA_AGGR_NOT_ELIGIBLE;
+		}
+
+		if (fse_metadata != fisa_flow->metadata) {
+			dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id);
+			DP_STATS_INC(fisa_hdl,
+				     reo_mismatch.allow_fse_metdata_mismatch,
+				     1);
 			return FISA_AGGR_NOT_ELIGIBLE;
 		}
 
 		dp_err("REO id mismatch flow: %pK napi_id: %u nbuf: %pK reo_id: %u",
 		       fisa_flow, fisa_flow->napi_id, nbuf, napi_id);
-		DP_STATS_INC(fisa_hdl, reo_mismatch, 1);
+		DP_STATS_INC(fisa_hdl, reo_mismatch.allow_non_aggr, 1);
 		QDF_BUG(0);
 		dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id);
 		return FISA_AGGR_NOT_ELIGIBLE;
diff --git a/core/dp/txrx3.0/dp_rx_fst.c b/core/dp/txrx3.0/dp_rx_fst.c
index 023729a53bf1..4d88045dedf1 100644
--- a/core/dp/txrx3.0/dp_rx_fst.c
+++ b/core/dp/txrx3.0/dp_rx_fst.c
@@ -63,6 +63,24 @@ void dp_rx_dump_fisa_table(struct dp_soc *soc)
 	}
 }
 
+void dp_print_fisa_stats(struct dp_soc *soc)
+{
+	struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
+	struct dp_rx_fst *fst = soc->rx_fst;
+
+	/* Check if it is enabled in the INI */
+	if (!wlan_cfg_is_rx_fisa_enabled(cfg))
+		return;
+
+	dp_info("invalid flow index: %u", fst->stats.invalid_flow_index);
+	dp_info("reo_mismatch: cce_match: %u",
+		fst->stats.reo_mismatch.allow_cce_match);
+	dp_info("reo_mismatch: allow_fse_metdata_mismatch: %u",
+		fst->stats.reo_mismatch.allow_fse_metdata_mismatch);
+	dp_info("reo_mismatch: allow_non_aggr: %u",
+		fst->stats.reo_mismatch.allow_non_aggr);
+}
+
 /**
  * dp_rx_flow_send_htt_operation_cmd() - Invalidate FSE cache on FT change
  * @pdev: handle to DP pdev

From fe2013a1c608b0efc2eb5bdb68c5c100d64fa774 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Dec 2025 12:01:43 -0800
Subject: [PATCH 089/290] fw-api: CL 31184747 - update fw common interface
 files

Change-Id: I0073de38d656d38f3535d5efe5d55823c97fb367
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 13 +++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index cbf8aca631ef..f4016f0f5c5a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -23006,6 +23006,19 @@ typedef struct {
      * If per_chain_noise_floor value is 0 then it should be ignored.
      */
     A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS];
+    /**
+     * FW will update the Noise Floor in dBr and send it to host
+     * if this field is set then host will display NF value in dBr
+     */
+    A_UINT32 nf_db_is_valid;
+    /**
+     * Noise Floor (NF) value in dBr. If the NF is not converged then
+     * NF value is returned as 0 to host. Theoretical minimum NF value
+     * is -101 dB for 20 MHz bandwidth and the max value can be 0.
+     * PHY reports 0 incase of very high NF values.
+     * This field should be ignored unless the nf_db_is_valid flag is set.
+     */
+    A_UINT32 noise_floor_in_db;
 
 /**
  * Following this structure is the optional TLV:
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9396537c897a..08a172601ed1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1683
+#define __WMI_REVISION_ 1684
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9a2d97b2eb8cfbb268c87104f75b9e1d3eb2e7e2 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Dec 2025 12:04:12 -0800
Subject: [PATCH 090/290] fw-api: CL 31184750 - update fw common interface
 files

Change-Id: I610b95360bfeb3320d91fd7b4be2944dfaca1d93
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 993385b7c706..eb3fc67cfd32 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -3515,6 +3515,36 @@ typedef enum {
     HTT_RU_ALLOC_NUM_MODES
 } HTT_RU_ALLOC_MODE;
 
+typedef enum {
+    HTT_TX_PDEV_STATS_BN_DRU_SIZE_26,
+    HTT_TX_PDEV_STATS_BN_DRU_SIZE_52,
+    HTT_TX_PDEV_STATS_BN_DRU_SIZE_106,
+    HTT_TX_PDEV_STATS_BN_DRU_SIZE_242,
+    HTT_TX_PDEV_STATS_BN_DRU_SIZE_484,
+
+    HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS
+} HTT_TX_PDEV_STATS_BN_DRU_SIZE;
+
+typedef enum {
+    HTT_BN_UL_OFDMA_RRU_ONLY_ALLOC_MODE,
+    HTT_BN_UL_OFDMA_DRU_ONLY_ALLOC_MODE,
+    HTT_BN_UL_OFDMA_HYBRID_RU_ALLOC_MODE,
+
+    /* Reserving additional modes for future use */
+    HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_1,
+    HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_2,
+
+    HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES
+} HTT_BN_UL_OFDMA_RU_ALLOC_MODE;
+
+typedef enum {
+    HTT_BN_UL_OFDMA_DRU_SBW_20MHZ,
+    HTT_BN_UL_OFDMA_DRU_SBW_40MHZ,
+    HTT_BN_UL_OFDMA_DRU_SBW_80MHZ,
+
+    HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT
+} HTT_BN_UL_OFDMA_DRU_SBW_SIZE;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -3829,6 +3859,9 @@ typedef struct {
     A_UINT32 manual_bn_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
     /** 11BN UHR Manual Multi-User UL OFDMA Trigger completed with error(s) */
     A_UINT32 manual_bn_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+
+    /** 11BN UHR UL OFDMA RU allocation mode */
+    A_UINT32 bn_basic_trig_ru_alloc_mode[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES];
 } htt_stats_tx_selfgen_bn_tlv;
 
 typedef struct { /* DEPRECATED */
@@ -7727,6 +7760,11 @@ typedef struct {
      * response to basic trigger. Typically a data response is expected.
      */
     A_UINT32 bn_ul_ofdma_basic_trigger_rx_qos_null_only;
+
+    /* UL OFDMA DRU spreading BW size */
+    A_UINT32 bn_ul_ofdma_rx_dru_sbw[HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT];
+    /* UL OFDMA DRU size of data PPDU */
+    A_UINT32 bn_rx_ulofdma_data_dru_size_ppdu[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS];
 } htt_stats_rx_pdev_be_bn_ul_trig_tlv;
 /* preserve old names as aliases */
 typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv
@@ -9534,6 +9572,9 @@ typedef struct {
 
     /* PER stats for iMCS 1.1, 3.1, 4.1, 7.1 */
     htt_tx_rate_stats_t per_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+
+    /* PER stats per DRU size */
+    htt_tx_rate_stats_t per_dru[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS];
 } htt_stats_per_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv;

From dd1a0ccd00c59e52f50d4b669b276a1f174626e3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Dec 2025 12:07:34 -0800
Subject: [PATCH 091/290] fw-api: CL 31209256 - update fw common interface
 files

Change-Id: I6504dacf6dc37457710e25d7af7206943d8a9024
CRs-Fixed: 3830439
---
 fw/wlan_module_ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wlan_module_ids.h b/fw/wlan_module_ids.h
index 6ccf2d652f95..fc65f819f510 100644
--- a/fw/wlan_module_ids.h
+++ b/fw/wlan_module_ids.h
@@ -198,6 +198,7 @@ typedef enum {
   WLAN_MODULE_OPT_DATA,                 /* 0x9a */
   WLAN_MODULE_ASD,                      /* 0x9b */
   WLAN_MODULE_ENERGY_MGMT,              /* 0x9c */
+  WLAN_MODULE_SMD,                      /* 0x9d */
 
   WLAN_MODULE_ID_MAX,
   WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,

From 531f3c19ffe2669c6bd3907088abe23e813dcbbd Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 17 Dec 2025 12:09:16 -0800
Subject: [PATCH 092/290] fw-api: CL 31209257 - update fw common interface
 files

Change-Id: I62d6ecad767301dcdb708e865967f54f800330b8
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 30 ++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 871590bb4e78..97bdb4d1d8d6 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1538,6 +1538,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_beacon_stats,
     WMITLV_TAG_STRUC_wmi_vdev_congestion_stats,
     WMITLV_TAG_STRUC_wmi_vdev_data_stats,
+    WMITLV_TAG_STRUC_wmi_em_pcie_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -7725,7 +7726,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_beacon_stats, vdev_beacon_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_congestion_stats, vdev_congestion_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_pcie_stats, ctrl_path_em_pcie_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
 
 /*
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f4016f0f5c5a..f5c3c72ac8df 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -38054,6 +38054,7 @@ typedef enum {
     WMI_REQUEST_CTRL_PATH_ML_RECONFIG_STAT  = 22,
     WMI_REQUEST_CTRL_PATH_STA_DAR_STAT      = 23,
     WMI_REQUEST_ENHANCED_STAT               = 24,
+    WMI_REQUEST_CTRL_PATH_EM_PCIE_STAT      = 25,
 } wmi_ctrl_path_stats_id;
 
 typedef enum {
@@ -47356,6 +47357,35 @@ typedef struct {
 } wmi_vdev_data_stats;
 
 
+#define WMI_EM_PCIE_MAX_CHIP 4
+#define WMI_EM_PCIE_MAX_NUM_MAC 3
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_pcie_stats */
+    A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */
+    A_UINT32 enable;   /* set to '1' if feature enable, else set to '0' */
+    A_UINT32 config_type; /* feature configuration type */
+    /* mlo_partner_chip_bw:
+     * MLO partner chip BW information, represented as a FW-internal BW enum
+     * (Thus, this field is intended only for interactive debugging, and not
+     * for interpretation by the host SW.)
+     */
+    A_UINT32 mlo_partner_bw[WMI_EM_PCIE_MAX_CHIP];
+    /* mlo_partner_nss: MLO partner chip NSS information */
+    A_UINT32 mlo_partner_nss[WMI_EM_PCIE_MAX_CHIP];
+    /* pdev_bw:
+     * Per PDEV BW, represented as a FW-internal BW enum
+     * (Thus, this field is intended only for interactive debugging, and not
+     * for interpretation by the host SW.)
+     */
+    A_UINT32 pdev_bw[WMI_EM_PCIE_MAX_NUM_MAC];
+    A_UINT32 curr_pcie_gen;      /* current PCIe generation number */
+    A_UINT32 curr_pcie_lanes;    /* current number of PCIe lanes */
+    A_UINT32 pending_pcie_gen;   /* pending PCIe generation number */
+    A_UINT32 pending_pcie_lanes; /* pending number of PCIe lanes */
+} wmi_em_pcie_stats;
+
+
 #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff
 #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \
     ((A_UINT16) ((tlv)->chain_phase[chain_idx] & WMI_UNIFIED_CHAIN_PHASE_MASK))
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 08a172601ed1..86041e35cff8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1684
+#define __WMI_REVISION_ 1685
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9fb7187f22d323d3ce31f9095960154de45e7511 Mon Sep 17 00:00:00 2001
From: Rakesh Pillai <quic_pillair@quicinc.com>
Date: Fri, 26 Aug 2022 03:08:43 -0700
Subject: [PATCH 093/290] qcacmn: Add reo_mismatch stats for FISA path

Add reo_mismatch stats for FISA path.

Change-Id: I954c9604b98cfb0b08be09ef0bf3e2235f47a3db
CRs-Fixed: 3277338
---
 dp/wifi3.0/dp_internal.h | 12 ++++++++++++
 dp/wifi3.0/dp_main.c     |  1 +
 dp/wifi3.0/dp_types.h    | 15 ++++++++++++++-
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/dp/wifi3.0/dp_internal.h b/dp/wifi3.0/dp_internal.h
index 77b1337baca5..61c290aea844 100644
--- a/dp/wifi3.0/dp_internal.h
+++ b/dp/wifi3.0/dp_internal.h
@@ -2363,6 +2363,14 @@ void dp_is_hw_dbs_enable(struct dp_soc *soc,
 #if defined(WLAN_SUPPORT_RX_FISA)
 void dp_rx_dump_fisa_table(struct dp_soc *soc);
 
+/**
+ * dp_print_fisa_stats() - Print FISA stats
+ * @soc: DP soc handle
+ *
+ * Return: None
+ */
+void dp_print_fisa_stats(struct dp_soc *soc);
+
 /*
  * dp_rx_fst_update_cmem_params() - Update CMEM FST params
  * @soc:		DP SoC context
@@ -2388,6 +2396,10 @@ static inline void
 dp_rx_fst_update_pm_suspend_status(struct dp_soc *soc, bool suspended)
 {
 }
+
+static inline void dp_print_fisa_stats(struct dp_soc *soc)
+{
+}
 #endif /* WLAN_SUPPORT_RX_FISA */
 
 #ifdef MAX_ALLOC_PAGE_SIZE
diff --git a/dp/wifi3.0/dp_main.c b/dp/wifi3.0/dp_main.c
index 7016cfacc9e6..c0806f998969 100644
--- a/dp/wifi3.0/dp_main.c
+++ b/dp/wifi3.0/dp_main.c
@@ -10101,6 +10101,7 @@ static QDF_STATUS dp_txrx_dump_stats(struct cdp_soc_t *psoc, uint16_t value,
 		dp_txrx_path_stats(soc);
 		dp_print_soc_interrupt_stats(soc);
 		hal_dump_reg_write_stats(soc->hal_soc);
+		dp_print_fisa_stats(soc);
 		break;
 
 	case CDP_RX_RING_STATS:
diff --git a/dp/wifi3.0/dp_types.h b/dp/wifi3.0/dp_types.h
index 25ba47531cd1..65057170c078 100644
--- a/dp/wifi3.0/dp_types.h
+++ b/dp/wifi3.0/dp_types.h
@@ -3134,10 +3134,23 @@ struct dp_rx_fst {
 #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse)
 #elif WLAN_SUPPORT_RX_FISA
 
+/**
+ * struct dp_fisa_reo_mismatch_stats - reo mismatch sub-case stats for FISA
+ * @allow_cce_match: packet allowed due to cce mismatch
+ * @allow_fse_metdata_mismatch: packet allowed since it belongs to same flow,
+ *			only fse_metadata is not same.
+ * @allow_non_aggr: packet allowed due to any other reason.
+ */
+struct dp_fisa_reo_mismatch_stats {
+	uint32_t allow_cce_match;
+	uint32_t allow_fse_metdata_mismatch;
+	uint32_t allow_non_aggr;
+};
+
 struct dp_fisa_stats {
 	/* flow index invalid from RX HW TLV */
 	uint32_t invalid_flow_index;
-	uint32_t reo_mismatch;
+	struct dp_fisa_reo_mismatch_stats reo_mismatch;
 	 uint32_t incorrect_rdi;
 };
 

From b2f42dc353e8e353054d7eea7486c053c98e5156 Mon Sep 17 00:00:00 2001
From: Paul Zhang <quic_paulz@quicinc.com>
Date: Wed, 31 Aug 2022 17:11:03 +0800
Subject: [PATCH 094/290] qcacmn: Replace ap reg rules with client reg rules

Currently, there is no ap reg rules from the regdomain for
some countries. But function reg_append_mas_chan_list_for_6g_lpi
and reg_append_mas_chan_list_for_6g_vlp get the master chan per
the ap reg rules number. It casues it can't get the master chan
list for 6 GHz even it has client reg rules.

To resolve this issue, using num_of_6g_client_reg_rules instead of
num_of_6g_ap_reg_rules.

Change-Id: If2dc6510edc61531cb1a3b8002e43a1bd69311e0
CRs-Fixed: 3278250
---
 umac/regulatory/core/src/reg_build_chan_list.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/umac/regulatory/core/src/reg_build_chan_list.c b/umac/regulatory/core/src/reg_build_chan_list.c
index 40959dbe6df2..38e7556df477 100644
--- a/umac/regulatory/core/src/reg_build_chan_list.c
+++ b/umac/regulatory/core/src/reg_build_chan_list.c
@@ -1079,7 +1079,7 @@ reg_append_mas_chan_list_for_6g_lpi(struct wlan_regulatory_pdev_priv_obj
 	struct regulatory_channel *master_chan_list_6g_client_lpi;
 	uint8_t i, j;
 
-	if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_INDOOR_AP]) {
+	if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_INDOOR_AP]) {
 		reg_debug("No LPI reg rules");
 		return;
 	}
@@ -1117,7 +1117,7 @@ reg_append_mas_chan_list_for_6g_vlp(struct wlan_regulatory_pdev_priv_obj
 	struct regulatory_channel *master_chan_list_6g_client_vlp;
 	uint8_t i, j;
 
-	if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_VERY_LOW_POWER_AP]) {
+	if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_VERY_LOW_POWER_AP]) {
 		reg_debug("No VLP reg rules");
 		return;
 	}

From 7bd07f4759a54a939e364421824f7fa201b60329 Mon Sep 17 00:00:00 2001
From: Gururaj Pandurangi <panduran@qti.qualcomm.com>
Date: Tue, 7 Sep 2021 23:09:58 +0530
Subject: [PATCH 095/290] qcacmn: Remove 6G domain check on Maschan list

If a country does not support 6G, then the 6G channel list is not
appended to the master channel list. Due to this, 6G center frequency
in the master channel list is zero. This leads to the problem in the
intersection of channels and chip range in the 5G Radio.

When the target sends the WMI_REG_CHAN_LIST_CC_EXT_EVENT, do not set
the is_6g_channel_list_populated flag based on the presence of a 6G
subdomain code. The flag should be set to true whenever the event is
received.

Change-Id: Ice714c961512fc1d86f8553b9870ab7385bbe9d5
CRs-Fixed: 3007334
---
 umac/regulatory/core/src/reg_build_chan_list.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/umac/regulatory/core/src/reg_build_chan_list.c b/umac/regulatory/core/src/reg_build_chan_list.c
index 40959dbe6df2..f5e0be5d512c 100644
--- a/umac/regulatory/core/src/reg_build_chan_list.c
+++ b/umac/regulatory/core/src/reg_build_chan_list.c
@@ -1758,9 +1758,8 @@ static void reg_store_regulatory_ext_info_to_socpriv(
 		soc_reg->domain_code_6g_ap[i] =
 			regulat_info->domain_code_6g_ap[i];
 
-		if (soc_reg->domain_code_6g_ap[i])
-			soc_reg->mas_chan_params[phy_id].
-				is_6g_channel_list_populated = true;
+		soc_reg->mas_chan_params[phy_id].
+			is_6g_channel_list_populated = true;
 
 		qdf_mem_copy(soc_reg->domain_code_6g_client[i],
 			     regulat_info->domain_code_6g_client[i],

From 74cfc7685c20bb4931eddac3693281f1d4f428be Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 18 Dec 2025 18:03:42 -0800
Subject: [PATCH 096/290] fw-api: CL 31221789 - update fw common interface
 files

Change-Id: I9d8246164f36970408b17320b4b3e3de8efbb6e3
CRs-Fixed: 3830439
---
 fw/htt.h         | 142 ++++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_unified.h |   6 +-
 fw/wmi_version.h |   2 +-
 3 files changed, 144 insertions(+), 6 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 2bf685b12aa2..c9cdde10f19c 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -276,9 +276,10 @@
  * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def.
  * 3.147 Add direct_refill flag in SRING_SETUP msg.
  * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def.
+ * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 148
+#define HTT_CURRENT_VERSION_MINOR 149
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -11783,6 +11784,19 @@ PREPACK struct htt_h2t_mpduq_and_msduq_info_hdr {
  *              tid_num (in bits 16:12)
  *              msduq_mpduq_type (in bits 21:17)
  * dword3 - b'31:0  - pn_addr_0_31: Lower 32 bits of 40 bit pn physical address
+ * dword4 - b'0:0   - sam_mpduq_allocated: Indicates whether a SAM MPDUQ has
+ *                    been allocated for this TQM MPDUQ.
+ *          b'11:1  - sam_mpduq_id: The SAM MPDUQ ID assigned by the host for
+ *                    this TQM MPDUQ. The value in this field is ignored if
+ *                    sam_mpduq_allocated is 0.
+ *          b'13:12 - sam_mpduq_priority: The SAM priority assigned by the
+ *                    host. A SAM priority MUST ALWAYS be provided for chipsets
+ *                    that have SAM support, regardless of whether or not a SAM
+ *                    MPDUQ has been allocated.
+ *          b'14:14 - sam_mpduq_sched_eligible: Indicates that this SAM MPDUQ
+ *                    is eligible for autonomous SAM scheduling. The value in
+ *                    this field is ignored if sam_mpduq_allocated is 0.
+ *          b'31:15 – reserved
  * Additional reserved dwords for future use cases
  *
  *
@@ -11807,6 +11821,24 @@ PREPACK struct htt_h2t_mpduq_and_msduq_info_hdr {
  * dword2 - b'31:0  - msduq_address_39_8: 256 byte aligned msduq physical
  *                    address, since lowest octet is zero for 256 byte aligned
  *                    addresses just passing upper 32 bits of 40 bit address
+ * dword3 - b'0:0   - svc_inst_req_type_valid: Indicates whether
+ *                    svc_inst_req_type is valid.
+ *          b'3:1   - svc_inst_req_type: Contains one of the values from
+ *                    HTT_SAWF_SVC_INST_REQ_TYPE. Only valid if
+ *                    svc_inst_req_type_valid is 1.
+ *          b'4:4   - sam_msduq_allocated: Indicates whether a SAM MSDUQ has
+ *                    been allocated for this TQM MSDUQ.
+ *          b'17:5  - sam_msduq_id: The SAM MSDUQ ID assigned by the host for
+ *                    this TQM MSDUQ. The value in this field is ignored if
+ *                    sam_msduq_allocated is 0.
+ *          b'19:18 - sam_msduq_priority: The SAM priority assigned by the
+ *                    host. A SAM priority MUST ALWAYS be provided for chipsets
+ *                    that have SAM support, regardless of whether or not a SAM
+ *                    MSDUQ has been allocated.
+ *          b'20:20 - sam_msduq_sched_eligible: Indicates that this SAM MSDUQ
+ *                    is eligible for autonomous SAM scheduling. The value in
+ *                    this field is ignored if sam_msduq_allocated is 0.
+ *          b'31:21 – reserved
  * Additional reserved dwords for future use cases
  */
 
@@ -11869,7 +11901,11 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
             A_UINT32 mpduq_number:            24, /* bits 23:0  */
                      pn_addr_39_32:            8; /* bits 31:24 */
             A_UINT32 pn_addr_31_0;                /* bits 31:0  */
-            A_UINT32 reserved1a;                  /* bits 31:0  */
+            A_UINT32 sam_mpduq_allocated:      1, /* bit     0  */
+                     sam_mpduq_id:            11, /* bits 11:1  */
+                     sam_mpduq_priority:       2, /* bits 13:12 */
+                     sam_mpduq_sched_eligible: 1, /* bit     14 */
+                     reserved1a:              17; /* bits 31:15 */
             A_UINT32 reserved1b;                  /* bits 31:0  */
             A_UINT32 reserved1c;                  /* bits 31:0  */
             A_UINT32 reserved1d;                  /* bits 31:0  */
@@ -11885,7 +11921,11 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
                       * contains a HTT_SAWF_SVC_INST_REQ_TYPE value
                       */
                      svc_inst_req_type:        3, /* bits  3:1  */
-                     reserved2a:              28; /* bits 31:4  */
+                     sam_msduq_allocated:      1, /* bit     4  */
+                     sam_msduq_id:            13, /* bits 17:5  */
+                     sam_msduq_priority:       2, /* bits 19:18 */
+                     sam_msduq_sched_eligible: 1, /* bit     20 */
+                     reserved2a:              11; /* bits 31:21 */
             A_UINT32 reserved2b;                  /* bits 31:0  */
             A_UINT32 reserved2c;                  /* bits 31:0  */
             A_UINT32 reserved2d;                  /* bits 31:0  */
@@ -11896,6 +11936,8 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
     };
 } POSTPACK;
 
+/* MPDUQ/MSDUQ shared fields of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */
+
 #define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_M    0x00001F00
 #define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S             8
 #define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_GET(_var) \
@@ -11953,6 +11995,9 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
         ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S)); \
     } while (0)
 
+
+/* MPDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */
+
 #define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_M   0xFFFFFFFF
 #define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S            0
 #define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_GET(_var) \
@@ -11999,6 +12044,53 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
         ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S)); \
     } while (0)
 
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M    0x00000001
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S             0
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M) >> \
+                HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S)
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M    0x00000FFE
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S             1
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M) >> \
+                HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S)
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M    0x00003000
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S            12
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M) >> \
+                HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S)
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M    0x00004000
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S            14
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M) >> \
+                HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S)
+#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S)); \
+    } while (0)
+
+
+/* MSDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */
+
 #define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_M           0x00FFFFFF
 #define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S                    0
 #define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_GET(_var) \
@@ -12054,6 +12146,50 @@ PREPACK struct htt_h2t_mpduq_or_msduq_info {
         ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S)); \
     } while (0)
 
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M    0x00000010
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S             4
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M    0x0003FFE0
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S             5
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M    0x000C0000
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S            18
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S)); \
+    } while (0)
+
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M    0x00100000
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S            20
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_GET(_var) \
+        (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M) >> \
+                HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S)
+#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S)); \
+    } while (0)
+
 
 /*
  * @brief  host -> target HTT_AST_INFO message
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f5c3c72ac8df..aa5e519d9064 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -22808,7 +22808,8 @@ typedef struct {
                       */
                      peer_cck_rx_support_5ghz : 1,
                      peer_cck_tx_support_5ghz : 1,
-                     reserved                 :28;
+                     sam_peer_id_valid        : 1,
+                     reserved                 :27;
         };
         A_UINT32 flags;
     };
@@ -22818,7 +22819,8 @@ typedef struct {
     A_UINT32 hw_peer_id;
     /** peer type: see enum values above */
     A_UINT32 peer_type;
-
+    /** Global SAM Peer ID, valid only if sam_peer_id_valid is set */
+    A_UINT32 sam_peer_id;
 
 /* Following this struct are the TLV's:
  *     A_UINT8 peer_legacy_rates[];
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 86041e35cff8..60111ef218f3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1685
+#define __WMI_REVISION_ 1686
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 1b5486814cfd3745e94d73a743d212f13d2860ee Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 19 Dec 2025 12:01:45 -0800
Subject: [PATCH 097/290] fw-api: CL 31233932 - update fw common interface
 files

Change-Id: Ie79884e4b7909997062b2b1edd770434f657ddea
CRs-Fixed: 3830439
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index c9cdde10f19c..f7bc2acb345d 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -886,6 +886,7 @@ typedef enum {
     HTT_STATS_PDEV_SAM_TAG                          = 233, /* htt_stats_pdev_sam_tlv */
     HTT_STATS_FTM_TAG                               = 234, /* htt_stats_ftm_tlv */
     HTT_STATS_PDEV_FTM_TPCCAL_EXT_TAG               = 235, /* htt_stats_pdev_ftm_tpccal_ext_tlv */
+    HTT_STATS_TX_PDEV_BN_RATE_TAG                   = 236, /* htt_stats_tx_pdev_bn_rate_tlv */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index eb3fc67cfd32..f8054fed0032 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -7148,6 +7148,56 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv;
 
+
+#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S 0
+#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) \
+    (((_var) & HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M) >> \
+     HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S)
+#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_MAC_ID, _val); \
+        ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S)); \
+    } while (0)
+
+#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M 0x00000f00
+#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S 8
+#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M) >> \
+     HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S)
+#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S)); \
+    } while (0)
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * BIT [ 7 :  0]   :- mac_id
+     * BIT [11 :  8]   :- wifi_version
+     * BIT [31 : 12]   :- reserved
+     */
+    union {
+        struct {
+            A_UINT32 mac_id:        8,
+                     /* wifi_version:
+                      * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value.
+                      * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET
+                      * / _SET macros for accessing this bitfield.
+                      */
+                     wifi_version:  4,
+                     reserved:     20;
+        };
+        A_UINT32 mac_id__word;
+    };
+    /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */
+    A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+    A_UINT32 tx_gi_ext_3[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+    A_UINT32 tx_stbc_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+} htt_stats_tx_pdev_bn_rate_tlv;
+
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
  * TLV_TAGS:
  *      - HTT_STATS_TX_PDEV_RATE_STATS_TAG
@@ -7158,6 +7208,7 @@ typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv;
  */
 #ifdef ATH_TARGET
 typedef struct {
+    htt_stats_tx_pdev_bn_rate_tlv rate_bn_tlv;
     htt_stats_tx_pdev_rate_stats_tlv rate_tlv;
     htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv;
     htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv;

From 9a532b1012c561475dd7a39be41bd79fc960d2d8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 19 Dec 2025 12:05:07 -0800
Subject: [PATCH 098/290] fw-api: CL 31233937 - update fw common interface
 files

Change-Id: I1bea4a6cd42d05b271fb12faa9727504f7796f39
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 15 +++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index aa5e519d9064..319e53e6213e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10869,6 +10869,21 @@ typedef struct {
      * ack_rssi is reported in dBm.
      */
     A_INT32    ack_rssi;
+
+    /* ieee_link_id_valid:
+     * For MLO cases, ieee_link_id_valid is set to 1, which indicates that
+     * the ieee_link_id field contains a valid value.
+     * For non-MLO and legacy cases, ieee_link_id_valid is set to 0, which
+     * means ignore the ieee_link_id field.
+     */
+    A_UINT32   ieee_link_id_valid;
+    /* ieee_link_id:
+     * For MLO cases, this indicates the link on which the QoS Null frame
+     * is sent.
+     * For non-MLO cases, this is not required because the QoS Null frame
+     * is sent on the connected link.
+     */
+    A_UINT32   ieee_link_id;
 } wmi_qos_null_frame_tx_compl_event_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 60111ef218f3..3ec8142cc532 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1686
+#define __WMI_REVISION_ 1687
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From be6daa59e381b8f6aa5c75d0658c30890e5450c4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 20 Dec 2025 12:04:21 -0800
Subject: [PATCH 099/290] fw-api: CL 31244431 - update fw common interface
 files

Change-Id: Ic75b325ce96d60d94cd5f7d4d228bc82b246ae52
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  | 51 +++++++++++++++++++++++++++++++++--------------
 fw/wmi_version.h  |  2 +-
 3 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index e156876d0d78..4ad68b2ab547 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -747,6 +747,7 @@ typedef  enum  {
     WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */
     WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */
     WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485,  /* Indicates FW support for WOW timeline optimization feature */
+    WMI_SERVICE_VENDOR_OUI_SUPPORT_EXCLUSIVE_MAC_ADDRESS = 486, /* FW supports parse exclusive_mac_address in wmi_vendor_oui_ext */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 319e53e6213e..420f679cdbcd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -27406,26 +27406,47 @@ typedef struct {
 } wmi_pdev_set_rx_filter_promiscuous_cmd_fixed_param;
 
 typedef enum {
-    WMI_BEACON_INFO_PRESENCE_OUI_EXT            = 1 <<  0,
-    WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS        = 1 <<  1,
-    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS  = 1 <<  2,
-    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT   = 1 <<  3,
-    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT  = 1 <<  4,
-    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND = 1 <<  5,
+    WMI_BEACON_INFO_PRESENCE_OUI_EXT               = 1 << 0,
+    WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS           = 1 << 1,
+    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS     = 1 << 2,
+    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT      = 1 << 3,
+    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT     = 1 << 4,
+    WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND    = 1 << 5,
+    WMI_BEACON_INFO_PRESENCE_EXCLUSIVE_MAC_ADDRESS = 1 << 6,
 } wmi_beacon_info_presence_items;
 
 typedef struct _wmi_vendor_oui_ext {
     A_UINT32 tlv_header;
-    A_UINT32 buf_data_length;        /* length of data in bytes for this OUI including index byte */
-    A_UINT32 info_presence_bit_mask; /* see enum wmi_beacon_info_presence_items */
-    A_UINT32 oui_header_length;      /* either 3 or 5 bytes */
-    A_UINT32 oui_data_length;        /* length of oui_data to compare in beacon which follows OUI header. Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes */
-    A_UINT32 mac_address_length;     /* MAC address length in bytes
-                                     ** (This value will always be 6,
-                                     ** but is explicitly specified for sake
-                                     ** of uniformity and completeness).
-                                     */
+
+    /* length of data in bytes for this OUI including index byte */
+    A_UINT32 buf_data_length;
+
+    /* see enum wmi_beacon_info_presence_items */
+    A_UINT32 info_presence_bit_mask;
+
+    A_UINT32 oui_header_length; /* either 3 or 5 bytes */
+
+    /* oui_data_length:
+     * Length of oui_data to compare in beacon which follows OUI header.
+     * Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes.
+     */
+    A_UINT32 oui_data_length;
+
+    /* mac_address_length:
+     * MAC address length in bytes
+     * (This value will always be 6, but is explicitly specified for sake
+     * of uniformity and completeness).
+     */
+    A_UINT32 mac_address_length;
+
     A_UINT32 capability_data_length; /* length of capability in bytes */
+
+    /* exclusive_mac_address_length:
+     * Exclusive MAC address length in bytes
+     * (This value will always be 6, but is explicitly specified for sake
+     * of uniformity and completeness).
+     */
+    A_UINT32 exclusive_mac_address_length;
 } wmi_vendor_oui_ext;
 
 #define WMI_INFO_CAPABILITY_NSS_MASK                       0x0f
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 3ec8142cc532..6d0f251bf5d6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1687
+#define __WMI_REVISION_ 1688
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 62e8165c6bf2459cc1a1146f1a5a2d16e6aa61e1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 22 Dec 2025 12:01:33 -0800
Subject: [PATCH 100/290] fw-api: CL 31250105 - update fw common interface
 files

Change-Id: I7aeed9724169ef42f34bc6ad3c0deb49c7a479b5
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_version.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 4ad68b2ab547..079cf240e77a 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -748,6 +748,7 @@ typedef  enum  {
     WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */
     WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485,  /* Indicates FW support for WOW timeline optimization feature */
     WMI_SERVICE_VENDOR_OUI_SUPPORT_EXCLUSIVE_MAC_ADDRESS = 486, /* FW supports parse exclusive_mac_address in wmi_vendor_oui_ext */
+    WMI_SERVICE_P2P_CANCEL_ONE_SHOT_NOA_SUPPORT = 487, /* Indicates FW support for P2P GO/GC cancel one-shot NOA feature */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 6d0f251bf5d6..ba193e13f50c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1688
+#define __WMI_REVISION_ 1689
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 4d85d7128cf3150790a037aec3aecaff03b5b13c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 25 Dec 2025 12:01:54 -0800
Subject: [PATCH 101/290] fw-api: CL 31274786 - update fw common interface
 files

Change-Id: I5abbfd38332508c9283113d003dea07f0aa83d55
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 420f679cdbcd..4b0e5cc13f4b 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19956,6 +19956,20 @@ typedef enum {
      */
     WMI_VDEV_PARAM_SET_GO_CANCEL_NOA,                     /* 0xCD */
 
+    /*
+     * WMI command to set ACK rate
+     * param_value refer to rate code (legacy CCK/OFDM rates) definitions
+     * for ACK Rates
+     * valid values:
+     *      ACK_RATE_CODE_6MBPS_OFDM (0x003):   Set 6Mbps OFDM ACK rate
+     *      ACK_RATE_CODE_12MBPS_OFDM (0x002):  Set 12Mbps OFDM ACK rate
+     *      ACK_RATE_CODE_24MBPS_OFDM (0x001):  Set 24Mbps OFDM ACK rate
+     *      ...
+     *      ACK_RATE_RESTORE_ORIGINAL (0xFFFF): Restore original rates
+     */
+    WMI_VDEV_PARAM_ACK_RATE,                              /* 0xCE */
+
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
@@ -47402,7 +47416,10 @@ typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_pcie_stats */
     A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */
     A_UINT32 enable;   /* set to '1' if feature enable, else set to '0' */
-    A_UINT32 config_type; /* feature configuration type */
+    /* config_type:
+     * feature configuration type (holds a wmi_pcie_config_type_e value)
+     */
+    A_UINT32 config_type;
     /* mlo_partner_chip_bw:
      * MLO partner chip BW information, represented as a FW-internal BW enum
      * (Thus, this field is intended only for interactive debugging, and not

From 66920b15c4434f32cf0b39b450bc76c36e37ab17 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 25 Dec 2025 12:05:29 -0800
Subject: [PATCH 102/290] fw-api: CL 31274787 - update fw common interface
 files

Change-Id: I6d27c652540b6409d0d9000b28558ce92f88bcd9
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index f8054fed0032..06798623fdd3 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1330,6 +1330,18 @@ typedef struct {
     A_UINT32 hw_reaped_sp;
     /** Number of hardware reaped (Tx completed) packets in VLP mode */
     A_UINT32 hw_reaped_vlp;
+    /** num_combined_sched_cmds_success_per_ac:
+     * Total number of successfully transmitted combined sched_cmd
+     * sequences per AC
+     */
+    A_UINT32 num_combined_sched_cmds_success_per_ac[HTT_NUM_AC_WMM];
+    /** Total number of failed combined sched_cmd sequences per AC */
+    A_UINT32 num_combined_sched_cmds_failed_per_ac[HTT_NUM_AC_WMM];
+    /** num_aborted_comb_sched_cmds_per_ac:
+     * Total number of aborted sched_cmds by scheduler before posting
+     * to TAC per AC
+     */
+    A_UINT32 num_aborted_comb_sched_cmds_per_ac[HTT_NUM_AC_WMM];
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;

From dda9ab273a6979476586549f2ccd7c879e4b924a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 28 Dec 2025 12:01:57 -0800
Subject: [PATCH 103/290] fw-api: CL 31281768 - update fw common interface
 files

Change-Id: I7d82384a438592e36a802dcab6e6901915493c81
CRs-Fixed: 3830439
---
 fw/htt.h       |   4 +-
 fw/htt_stats.h | 123 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 126 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index f7bc2acb345d..d052173156b8 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -887,7 +887,9 @@ typedef enum {
     HTT_STATS_FTM_TAG                               = 234, /* htt_stats_ftm_tlv */
     HTT_STATS_PDEV_FTM_TPCCAL_EXT_TAG               = 235, /* htt_stats_pdev_ftm_tpccal_ext_tlv */
     HTT_STATS_TX_PDEV_BN_RATE_TAG                   = 236, /* htt_stats_tx_pdev_bn_rate_tlv */
-
+    HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG         = 237, /* htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv, TOPIC=advanced */
+    HTT_STATS_RX_PDEV_BN_UL_MIMO_USER_TAG           = 238, /* htt_stats_rx_pdev_bn_ul_mimo_user_tlv */
+    HTT_STATS_TX_PDEV_BN_UL_MU_MIMO_TAG             = 239, /* htt_stats_tx_pdev_bn_ul_mu_mimo_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 06798623fdd3..faa6680df3f7 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1037,6 +1037,11 @@ typedef enum {
      * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv
      */
     HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE,
+    /*
+     * Upload 11bn UL MUMIMO RX Trigger stats
+     * TLV: htt_rx_pdev_ul_mumimo_trig_bn_stats_tlv
+     */
+    HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BN,
 } htt_rx_ul_mumimo_trigger_stats_upload_t;
 
 /* htt_tx_pdev_txbf_ofdma_stats_upload_t
@@ -3495,6 +3500,7 @@ typedef enum {
 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4
 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8
+#define HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS 8
 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
 #define HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS 16
 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8
@@ -3874,6 +3880,28 @@ typedef struct {
 
     /** 11BN UHR UL OFDMA RU allocation mode */
     A_UINT32 bn_basic_trig_ru_alloc_mode[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES];
+
+    /** 11bn UHR MU UL-MUMIMO Trigger frame sent over the air */
+    A_UINT32 bn_ulmumimo_trigger;
+    /**
+     * 11bn UHR UL-MUMIMO Trigger frame for users 0 - 7
+     * successfully sent over the air
+     */
+    A_UINT32 bn_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS];
+    /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger frame sent over the air */
+    A_UINT32 combined_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM];
+    /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger completed with error(s) */
+    A_UINT32 combined_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM];
+    /**
+     * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger frame
+     * sent over the air
+     */
+    A_UINT32 standalone_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM];
+    /**
+     * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger
+     * completed with error(s)
+     */
+    A_UINT32 standalone_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM];
 } htt_stats_tx_selfgen_bn_tlv;
 
 typedef struct { /* DEPRECATED */
@@ -4642,6 +4670,13 @@ typedef struct {
     A_UINT32 bn_mu_rts_trigger_blocked;
     /** 11BN UHR MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */
     A_UINT32 bn_bsr_trigger_blocked;
+
+    /** 11BN UHR MU ULMUMIMO Trigger frame completed with error(s) */
+    A_UINT32 bn_ulmumimo_trigger_err;
+    /**
+     * 11BN UHR UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s)
+     */
+    A_UINT32 bn_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS];
 } htt_stats_tx_selfgen_bn_err_tlv;
 
 /*
@@ -5061,6 +5096,18 @@ typedef struct {
 typedef htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv
     htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * Represents the count for 11BN UL MU MIMO sequences with Basic Triggers
+     */
+    A_UINT32 bn_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
+    /**
+     * Represents the count for 11BN UL MU MIMO sequences with BRP Triggers
+     */
+    A_UINT32 bn_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
+} htt_stats_tx_pdev_bn_ul_mu_mimo_tlv;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** 11AC DL MU MIMO number of mpdus queued to HW, per user */
@@ -7936,6 +7983,21 @@ typedef struct {
 typedef htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv
     htt_rx_pdev_be_ul_mimo_user_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+
+    A_UINT32 user_index;
+    /** PPDU level */
+    A_UINT32 bn_rx_ulmumimo_non_data_ppdu;
+    /** PPDU level */
+    A_UINT32 bn_rx_ulmumimo_data_ppdu;
+    /** MPDU level */
+    A_UINT32 bn_rx_ulmumimo_mpdu_ok;
+    /** MPDU level */
+    A_UINT32 bn_rx_ulmumimo_mpdu_fail;
+} htt_stats_rx_pdev_bn_ul_mimo_user_tlv;
+
+
 /* == RX PDEV/SOC STATS == */
 
 typedef struct {
@@ -8065,15 +8127,76 @@ typedef struct {
 typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv
     htt_rx_pdev_ul_mumimo_trig_be_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+
+    /**
+     * BIT [ 7 :  0]   :- mac_id
+     * BIT [31 :  8]   :- reserved
+     *
+     * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros.
+     */
+    union {
+        struct {
+            A_UINT32 mac_id:    8,
+                     reserved: 24;
+        };
+        A_UINT32 mac_id__word;
+    };
+
+    /** Number of times UL MUMIMO RX packets received */
+    A_UINT32 rx_11bn_ul_mumimo;
+
+    /** 11BN UHR UL MU-MIMO RX TB PPDU MCS stats */
+    A_UINT32 bn_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS];
+    /**
+     * 11BN UHR UL MU-MIMO RX GI & LTF stats.
+     * Index 0 indicates 1xLTF + 1.6 msec GI
+     * Index 1 indicates 2xLTF + 1.6 msec GI
+     * Index 2 indicates 4xLTF + 3.2 msec GI
+     */
+    A_UINT32 bn_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS];
+    /**
+     * 11BN UHR UL MU-MIMO RX TB PPDU NSS stats
+     * (Increments the individual user NSS in the UL MU MIMO PPDU received)
+     */
+    A_UINT32 bn_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
+    /** 11BN UHR UL MU-MIMO RX TB PPDU BW stats */
+    A_UINT32 bn_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    /** Number of times UL MUMIMO TB PPDUs received with STBC */
+    A_UINT32 bn_ul_mumimo_rx_stbc;
+    /** Number of times UL MUMIMO TB PPDUs received with LDPC */
+    A_UINT32 bn_ul_mumimo_rx_ldpc;
+
+    /** RSSI in dBm for Rx TB PPDUs */
+    A_INT8 bn_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS];
+    /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */
+    A_INT8 bn_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS];
+    /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */
+    A_INT8 bn_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
+    /** Average pilot EVM measued for RX UL TB PPDU */
+    A_INT8 bn_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS];
+    /** Number of times UL MUMIMO TB PPDUs received in a punctured mode */
+    A_UINT32 bn_rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+    /*
+     * Number of UHR UL MU-MIMO per-user responses containing only a QoS null
+     * in response to basic trigger. Typically a data response is expected.
+     */
+    A_UINT32 bn_ul_mumimo_basic_trigger_rx_qos_null_only;
+} htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv;
+
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS
  * TLV_TAGS:
  *    - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG
  *    - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG
+ *    - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG
  */
 #ifdef ATH_TARGET
 typedef struct {
     htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv    ul_mumimo_trig_tlv;
     htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv;
+    htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv       ul_mumimo_trig_bn_tlv;
 } htt_rx_pdev_ul_mumimo_trig_stats_t;
 #endif /* ATH_TARGET */
 

From 3da3641c46da04c7ba99d1cc9ae9658e12126890 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 28 Dec 2025 12:03:48 -0800
Subject: [PATCH 104/290] fw-api: CL 31282590 - update fw common interface
 files

Change-Id: Id99c01da3a7bd638331e1dc3cb8160e1403700ed
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   1 +
 fw/wmi_tlv_defs.h |  46 ++++++++-
 fw/wmi_unified.h  | 235 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 4 files changed, 277 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 079cf240e77a..f7e458b2c14a 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -749,6 +749,7 @@ typedef  enum  {
     WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485,  /* Indicates FW support for WOW timeline optimization feature */
     WMI_SERVICE_VENDOR_OUI_SUPPORT_EXCLUSIVE_MAC_ADDRESS = 486, /* FW supports parse exclusive_mac_address in wmi_vendor_oui_ext */
     WMI_SERVICE_P2P_CANCEL_ONE_SHOT_NOA_SUPPORT = 487, /* Indicates FW support for P2P GO/GC cancel one-shot NOA feature */
+    WMI_SERVICE_SMD_BSS_TRANSITION_SUPPORT = 488, /* Indicates FW supports S(eamless)M(obility)D(omain) BSS transition */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 97bdb4d1d8d6..1301f470eae7 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1539,6 +1539,13 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_congestion_stats,
     WMITLV_TAG_STRUC_wmi_vdev_data_stats,
     WMITLV_TAG_STRUC_wmi_em_pcie_stats,
+    WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params,
+    WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param,
+    WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param,
+    WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_prep_resp_status_list,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2124,6 +2131,9 @@ typedef enum {
     OP(WMI_NAN_DISABLE_CMDID) \
     OP(WMI_VDEV_UNIFIED_CONNECT_CMDID) \
     OP(WMI_VDEV_UNIFIED_DISCONNECT_CMDID) \
+    OP(WMI_ROAM_SMD_CONFIG_CMDID) \
+    OP(WMI_ROAM_SMD_START_STATUS_CMDID) \
+    OP(WMI_VDEV_REPURPOSE_RESP_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -3034,7 +3044,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
 /* NOTE:
  * Any new TLV addition in WMI_PEER_ASSOC_V2_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
@@ -3613,7 +3624,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE);
 
 /* Roam sync complete Cmd */
 #define WMITLV_TABLE_WMI_ROAM_SYNCH_COMPLETE(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_COMPLETE);
 
@@ -4179,6 +4191,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DSM_FILTER_CMDID);
     WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, non_tx_bssid, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_DFS_AP_CONFIG_CMDID);
 
+/* Configure roam SMD parameters */
+#define WMITLV_TABLE_WMI_ROAM_SMD_CONFIG_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param, wmi_roam_smd_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_CONFIG_CMDID);
+
+/* SMD preparation completion status command */
+#define WMITLV_TABLE_WMI_ROAM_SMD_START_STATUS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param, wmi_roam_smd_start_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_prep_resp_status_list, status_list, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kck, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_START_STATUS_CMDID);
+
 #define WMITLV_TABLE_WMI_ROAM_BLACKLIST_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param, wmi_roam_blacklist_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_blacklist_with_timeout_tlv_param, blacklist_with_timeout, WMITLV_SIZE_VAR)
@@ -6103,7 +6129,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \
  \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
@@ -6119,6 +6146,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
 
+/** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */
+#define WMITLV_TABLE_WMI_VDEV_REPURPOSE_RESP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param, wmi_vdev_repurpose_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_REPURPOSE_RESP_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -6487,7 +6520,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_partner_link_param, partner_link_param, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_partner_link_param, partner_link_param, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
 
 /* Roam Synch Event */
@@ -6506,7 +6541,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_pmk_cache_synch_tlv_param, roam_pmk_cache_synch_info, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_setup_links_param, setup_links_param, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID);
 
 /* Roam Synch key Event */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4b0e5cc13f4b..c5910df1eb6c 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -753,6 +753,9 @@ typedef enum {
     /** WMI cmd for unified disconnect */
     WMI_VDEV_UNIFIED_DISCONNECT_CMDID,
 
+    /** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */
+    WMI_VDEV_REPURPOSE_RESP_CMDID,
+
 
     /* peer specific commands */
 
@@ -1033,6 +1036,10 @@ typedef enum {
     WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID,
     /** Get firmware ini value */
     WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID,
+    /** configure SMD parameters for roaming */
+    WMI_ROAM_SMD_CONFIG_CMDID,
+    /** SMD preparation completion status command */
+    WMI_ROAM_SMD_START_STATUS_CMDID,
 
     /** offload scan specific commands */
     /** set offload scan AP profile   */
@@ -5147,8 +5154,14 @@ typedef struct {
      *      This bit will be set by host to inform FW that HOST will be
      *      expecting and will be able to handle DCS stats event sent
      *      by FW for concurrent vdevs (event can support max 2 vdevs data).
+     *  Bit 25
+     *      This bit will be set by host to inform FW that HOST will support
+     *      SMD BSS transition.
+     *      Refer to the below definitions of
+     *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET and _SET
+     *      macros.
      *
-     *  Bits 31:25 - Reserved
+     *  Bits 31:26 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -5761,6 +5774,12 @@ typedef struct {
 #define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_SET(host_service_flags, value) \
     WMI_SET_BITS(host_service_flags, 24, 1, value)
 
+/* This bit will be used to inform FW that HOST enables SMD BSS transition */
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET(host_service_flags) \
+    WMI_GET_BITS(host_service_flags, 25, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_SET(host_service_flags, value) \
+    WMI_SET_BITS(host_service_flags, 25, 1, value)
+
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \
@@ -5811,6 +5830,7 @@ typedef enum {
     WMI_WIFI_STANDARD_6     = 2,
     WMI_WIFI_STANDARD_6E    = 3,
     WMI_WIFI_STANDARD_7     = 4,
+    WMI_WIFI_STANDARD_8     = 5,
 } WMI_WIFI_STANDARD;
 
 typedef enum {
@@ -22664,6 +22684,15 @@ typedef struct {
     A_UINT32 cfp_padding_delay;
 } wmi_peer_assoc_cfp_params; /* cfp -> control frame protection */
 
+/* This TLV structure used to pass smd Parameters on peer assoc */
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params */
+    /** The SMD Identifier field indicates a unique identifier for the SMD and is in the format of a 48-bit MAC address. */
+    wmi_mac_addr smd_identifier;
+    /** SMD capabilities defined in 802.11BN-SMD Information element */
+    A_UINT32 smd_capabilities;
+} wmi_peer_assoc_smd_params;
+
 /*
  * PEER assoc_flags for assoc complete:
  * Bit 0: Set for peer data flush
@@ -23846,6 +23875,11 @@ typedef struct {
 #define WMI_ROAM_SET_SECURITY_SCORE_PERCENTAGE(value32, score_pcnt, security_index) \
     WMI_SET_BITS(value32, (8 * (security_index)), 8, score_pcnt)
 
+/* Boost the APs that belong to the same SMD as the current AP.*/
+#define WLAN_ROAM_SCORE_INTRA_SMD_INDEX 0
+#define WMI_ROAM_GET_INTRA_SMD_SCORE_PERCENTAGE(value32, index)               WMI_GET_BITS(value32, (8 * (index)), 8)
+#define WMI_ROAM_SET_INTRA_SMD_SCORE_PERCENTAGE(value32, score_pcnt, index)   WMI_SET_BITS(value32, (8 * (index)), 8, score_pcnt)
+
 /**
     best_rssi_threshold: Roamable AP RSSI equal or better than this threshold, full RSSI score 100. Units in dBm.
     good_rssi_threshold: Below this threshold, scoring linear percentage between rssi_good_pcnt and 100. Units in dBm.
@@ -24123,6 +24157,14 @@ typedef struct {
     A_UINT32 mcc_score_factor_pcnt;
     /* Scoring weightage for privacy support like 11bi */
     A_UINT32 privacy_weightage_pcnt;
+    /* uhr_weightage_pcnt:
+     * 11bn weightage out of total score in percentage.
+     */
+    A_UINT32 uhr_weightage_pcnt;
+    /* smd_weightage_pcnt:
+     * give weightage to candidate based on SMD support.
+     */
+    A_UINT32 smd_weightage_pcnt;
 } wmi_roam_cnd_scoring_param;
 
 typedef struct {
@@ -24738,6 +24780,61 @@ typedef struct {
     A_UINT32 deleted_ieee_link_id_bmap;
 } wmi_roam_partner_link_param;
 
+/*
+ * useful macros defined for flags field in wmi_vdev_repurpose_request_tlv_param */
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_INACTIVE(flags) \
+    WMI_GET_BITS(flags, 0, 1)
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_INACTIVE(flags, val) \
+    WMI_SET_BITS(flags, 0, 1, val)
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_DISCONNECT(flags) \
+    WMI_GET_BITS(flags, 1, 1)
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_DISCONNECT(flags, val) \
+    WMI_SET_BITS(flags, 1, 1, val)
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_CONNECT(flags) \
+    WMI_GET_BITS(flags, 2, 1)
+#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_CONNECT(flags, val) \
+    WMI_SET_BITS(flags, 2, 1, val)
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param */
+    A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */
+    /* flags - refer WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET and _SET macro
+     * BIT 0 -
+     *   Host shall inactive link with sending WMI_MLO_LINK_SET_ACTIVE_CMDID
+     *   before issue  WMI_VDEV_UNIFIED_DISCONNECT_CMDID if the bit is set.
+     * BIT 1 -
+     *   Host shall send WMI_VDEV_UNIFIED_DISCONNECT_CMDID on the
+     *   repurpose_vdev_id if the bit is set.
+     * BIT 2 -
+     *   Host shall send WMI_VDEV_UNIFIED_CONNECT_CMDID on the
+     *   repurpose_vdev_id if the bit is set.
+     */
+    A_UINT32 flags;
+    /* bassid:
+     * repurposed AP bssid, valid when BIT2 is set in flags
+     */
+    wmi_mac_addr bssid;
+    /* mld_addr:
+     * repurposed AP mld address, valid when BIT2 is set in flags
+     */
+    wmi_mac_addr mld_addr;
+    /* smd_addr:
+     * repurposed AP smd address, valid when BIT2 is set in flags
+     */
+    wmi_mac_addr smd_addr;
+} wmi_vdev_repurpose_request_tlv_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param */
+    A_UINT32 vdev_id;
+} wmi_vdev_repurpose_resp_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param */
+    A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */
+    A_UINT32 status;            /* 0 is success */
+} wmi_vdev_repurpose_response_tlv_param;
+
 /* roam_reason: bits 0-3 */
 #define WMI_ROAM_REASON_INVALID   0x0 /** invalid reason. Do not interpret reason field */
 #define WMI_ROAM_REASON_BETTER_AP 0x1 /** found a better AP */
@@ -24797,6 +24894,9 @@ typedef enum
     (((roam_reason) & WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_MASK) >> \
      WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_SHIFT)
 
+#define WMI_GET_ROAM_SMD_BSS_TRANSITION(roam_reason)      WMI_GET_BITS(roam_reason, 16, 1)
+#define WMI_SET_ROAM_SMD_BSS_TRANSITION(roam_reason, val) WMI_SET_BITS(roam_reason, 16, 1, val)
+
 /* Bits  0-3: stores 4 LSbs of trigger reason.
  *            Old host will get trigger reasons <= 15 from this bitfield.
  * Bit 7 will be 1 always to indicate that bits 8-15 are valid.
@@ -24826,6 +24926,7 @@ typedef enum
 #define WMI_ROAM_NOTIF_SCAN_MODE_SUCCESS_WITH_HO_FAIL 0xb /** indicate that roaming scan mode is successful but cause disconnection and subsequent
                                                            ** WMI_ROAM_REASON_HO_FAILED is event expected */
 #define WMI_ROAM_NOTIF_SCAN_END          0xc /** indicate roam scan end, notif_params to be sent as WMI_ROAM_TRIGGER_REASON_ID */
+#define WMI_ROAM_NOTIF_ROAM_SMD_START    0xd /** indicate that SMD BSS transtion is started, notif_params1 to be sent as requested setup ieee links bitmap for target AP MLD */
 
 /**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc)
 * Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on this information
@@ -31528,6 +31629,12 @@ typedef struct {
     A_UINT8  replay_counter[GTK_REPLAY_COUNTER_BYTES];
 } wmi_key_material;
 
+#ifndef WMI_MAX_PMK_LEN
+#define WMI_MAX_SMD_KDK_LEN 64
+#else
+#define WMI_MAX_SMD_KDK_LEN WMI_MAX_PMK_LEN
+#endif
+
 typedef struct {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */
     A_UINT32 tlv_header;
@@ -31541,6 +31648,10 @@ typedef struct {
     A_UINT32 kck_len;
     /* length of kek in key_buffer */
     A_UINT32 kek_len;
+    /* length of smd kdk */
+    A_UINT32 smd_kdk_len;
+    /* smd kdk buffer */
+    A_UINT8  smd_kdk_buffer[WMI_MAX_SMD_KDK_LEN];
 } wmi_key_material_ext;
 
 typedef struct {
@@ -31557,6 +31668,8 @@ typedef struct {
      * bit  7    0x1 to show bits 8-15 are valid
      * bits 8-15 full WMI_ROAM_TRIGGER_REASON_ID/WMI_ROAM_TRIGGER_EXT_REASON_ID
      *           since 4 bits are not enough.
+     * bit 16    SMD BSS transition if it's set, see GET / SET
+     *           ROAM_SMD_BSS_TRANSITION macros
      */
     A_UINT32 roam_reason;
     /** associated AP's RSSI calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */
@@ -31590,6 +31703,11 @@ typedef struct {
      *     EPPKE authentication
      */
     A_UINT32 auth_algo;
+    /** smd_identifier:
+     * The SMD identifier of the roamed AP must not be zero in cases of
+     * an SMD BSS transition or a reassociation with SMD capability.
+     */
+    wmi_mac_addr smd_identifier;
     /**
      * TLV (tag length value) parameters follows roam_synch_event
      * The TLV's are:
@@ -40769,6 +40887,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_NAN_ENABLE_CMDID);
         WMI_RETURN_STRING(WMI_NAN_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_NAN_DISABLE_CMDID);
+        WMI_RETURN_STRING(WMI_ROAM_SMD_CONFIG_CMDID);
+        WMI_RETURN_STRING(WMI_ROAM_SMD_START_STATUS_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -44310,6 +44431,10 @@ typedef enum {
     WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_M4,
     WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M1,
     WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M2,
+    WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_REQ,
+    WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_RESP,
+    WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_REQ,
+    WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_RESP,
 } WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE;
 
 typedef enum {
@@ -44885,6 +45010,114 @@ typedef enum {
     WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP          = 0x00020000,
 } wlan_crypto_roam_eht_config;
 
+typedef enum {
+    /*
+     * Low-latency mode is suitable for applications with strict
+     * latency requirements and is also the default mode in the firmware.
+     * e.g VOIP, Online gaming.
+     */
+    WMI_ROAM_LOWLATENCY_MODE     = 0x0,
+    /*
+     * Packet-loss mode is suitable for applications that do not have
+     * strict latency requirements but have low tolerance for packet loss.
+     * e.g file transfer.
+     */
+    WMI_ROAM_PACKETLOSSLESS_MODE = 0x1,
+    /* This mode is only used for WFA test purpose. */
+    WMI_ROAM_MANUAL_MODE         = 0x2,
+} WMI_ROAM_SMD_MODE_PARAMS;
+
+/*
+ * useful macros defined for flags field in wmi_roam_smd_config_cmd_fixed_param
+ */
+#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_ASSOC(flags) \
+    WMI_GET_BITS(flags, 0, 1)
+#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_ASSOC(flags, val) \
+    WMI_SET_BITS(flags, 0, 1, val)
+
+#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_TRANSITION(flags) \
+    WMI_GET_BITS(flags, 1, 1)
+#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_TRANSITION(flags, val) \
+    WMI_SET_BITS(flags, 1, 1, val)
+
+/*
+ * useful macros defined for manual_conf field in
+ * wmi_roam_smd_config_cmd_fixed_param
+ */
+#define WMI_SMD_CONFIG_MANUAL_CONF_GET_EXECUTION_VIA_NEW_AP(conf) \
+    WMI_GET_BITS(conf, 0, 1)
+#define WMI_SMD_CONFIG_MANUAL_CONF_SET_EXECUTION_VIA_NEW_AP(conf, val) \
+    WMI_SET_BITS(conf, 0, 1, val)
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param */
+    A_UINT32 vdev_id;
+
+    /*
+     * The mode used to control SMD transition involves a trade-off
+     * between low latency and packet loss.
+     * Depending on the upper-layer application, the choice may also vary.
+     * refer WMI_ROAM_SMD_MODE_PARAMS definition
+     */
+    A_UINT32 prefer_mode;
+    /* flags:
+     * refer WMI_SMD_CONFIG_FLAGS_GET and _SET macros
+     * BIT 0 - Disable SMD association.
+     * BIT 1 - Disable SMD BSS transition, invalid when BIT 0 is set.
+     */
+    A_UINT32 flags;
+    /* manual_conf:
+     * Valid only when prefer_mode is WMI_ROAM_MANUAL_MODE
+     * BIT 0 - SMD transition execution via new AP if set.
+     */
+    A_UINT32 manual_conf;
+} wmi_roam_smd_config_cmd_fixed_param;
+
+typedef enum {
+    WMI_SMD_START_STATUS_SUCCESS = 0,
+
+    /* Failure that is not specifically defined  */
+    WMI_SMD_START_STATUS_UNSPECIFIC_FAILURE,
+
+    /* Abort due to disconnection from upper layer */
+    WMI_SMD_START_STATUS_ABORT_DISCONNECTION,
+
+    /* Vdev repurpose failure */
+    WMI_SMD_START_STATUS_VDEV_REPURPOSE_FAILURE,
+
+    /* Preparation request frame no ACK */
+    WMI_SMD_START_STATUS_PREP_REQ_TX_NO_ACK,
+
+   /* No Preparation response frame received */
+    WMI_SMD_START_STATUS_PREP_RESP_RX_TIMEOUT,
+} WMI_SMD_START_STATUS_CODE;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prep_resp_status_list */
+    A_UINT32 ieee_link_id;
+    A_UINT32 status_code;  /* same value defined in 'status code' in standard */
+} wmi_prep_resp_status_list;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param */
+
+    A_UINT32 vdev_id;
+    A_UINT32 status; /* Refer WMI_SMD_START_STATUS_CODE */
+    /* kck_len:
+     * Valid when per AP-MLD ptk mode is used, KCK is used to
+     * calculate MIC in ST execution request frame.
+     */
+   A_UINT32 kck_len;
+
+    /*
+     * This fixed_param TLV is followed by the below TLVs:
+     *
+     * A_UINT8 smd_transition_ie[];
+     * wmi_prep_resp_status_list status_list[];
+     * A_UINT8 kck[];
+     */
+} wmi_roam_smd_start_status_cmd_fixed_param;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param */
     A_UINT32 vdev_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ba193e13f50c..5a146e5248a1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1689
+#define __WMI_REVISION_ 1690
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 62bc78b71bd2ad498227666312fa1ccdee10e65b Mon Sep 17 00:00:00 2001
From: Kiran Kumar Reddy A E <kreddyae@qti.qualcomm.com>
Date: Wed, 31 Dec 2025 12:01:43 -0800
Subject: [PATCH 105/290] fw-api: CL 31295115 - update fw common interface
 files

Change-Id: I3089ec880d785a98bc25c826a540c70a33492322
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 16 ++++++++++++++++
 fw/wmi_unified.h  | 43 +++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 1301f470eae7..40816c1f6681 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1546,6 +1546,9 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param,
     WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_prep_resp_status_list,
+    WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_ipa_ring_stat_entry,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2134,6 +2137,7 @@ typedef enum {
     OP(WMI_ROAM_SMD_CONFIG_CMDID) \
     OP(WMI_ROAM_SMD_START_STATUS_CMDID) \
     OP(WMI_VDEV_REPURPOSE_RESP_CMDID) \
+    OP(WMI_IPA_RING_STATS_REQ_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2484,6 +2488,7 @@ typedef enum {
     OP(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID) \
     OP(WMI_VDEV_UNIFIED_CONNECT_EVENTID) \
     OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \
+    OP(WMI_IPA_RING_STATS_CONF_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6152,6 +6157,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_REPURPOSE_RESP_CMDID);
 
+/* Get IPA ring stats */
+#define WMITLV_TABLE_WMI_IPA_RING_STATS_REQ_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, wmi_ipa_ring_stats_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8420,6 +8430,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID);
 
+/* get IPA ring stats event */
+#define WMITLV_TABLE_WMI_IPA_RING_STATS_CONF_EVENTID(id,op,buf,len) \
+WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param, wmi_ipa_ring_stats_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_ring_stat_entry, ipa_ring_stat_entry, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_CONF_EVENTID);
+
 
 
 #ifdef __cplusplus
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c5910df1eb6c..5b740596370e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1577,6 +1577,8 @@ typedef enum {
 
     /** IPA Offload features related commands */
     WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_IPA),
+    /** WMI cmd to get IPA ring stats */
+    WMI_IPA_RING_STATS_REQ_CMDID,
 
     /** mDNS responder offload commands */
     WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MDNS_OFL),
@@ -2602,6 +2604,9 @@ typedef enum {
     /* mDNS offload events */
     WMI_MDNS_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MDNS_OFL),
 
+    /** WMI Event to send IPA ring stats to host */
+    WMI_IPA_RING_STATS_CONF_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_IPA),
+
     /* SAP Authentication offload events */
     WMI_SAP_OFL_ADD_STA_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SAP_OFL),
     WMI_SAP_OFL_DEL_STA_EVENTID,
@@ -15948,6 +15953,11 @@ typedef struct {
      * Includes rx_time but not tx_time.
      */
     A_UINT32 cca_time;
+    /* pending_mpdu_msdus:
+     * count of the pending mpdu + msdus for all tids within all peers
+     * for the specified vdev
+     */
+    A_UINT32 pending_mpdu_msdus;
 } wmi_vdev_extd_stats;
 
 /**
@@ -40890,6 +40900,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_ROAM_SMD_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_ROAM_SMD_START_STATUS_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID);
+        WMI_RETURN_STRING(WMI_IPA_RING_STATS_REQ_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -53367,6 +53378,38 @@ typedef struct {
     A_UINT32 status;
 } wmi_wlan_mode_resp_event_fixed_param;
 
+/* Optional version for future expansion */
+typedef enum {
+    WMI_IPA_RING_STATS_EVENT_VERSION1 = 1,
+
+} WMI_IPA_RING_STATS_EVENT_VERSIONS;
+
+typedef struct {
+    A_UINT32 tlv_header;
+    /* version:
+     * For future extensions; currently 1 (WMI_IPA_RING_STATS_EVENT_VERSION1)
+     * Refer to WMI_IPA_RING_STATS_EVENT_VERSIONS.
+     */
+    A_UINT32 version;
+    A_UINT32 ring_id;
+} wmi_ipa_ring_stats_req_cmd_fixed_param;
+
+/* Per-ring sample (indices and sizes in entries to keep host parsing simple) */
+typedef struct {
+    A_UINT32 tlv_header;
+    A_UINT32 ring_id;        /* e.g., HAL ring_id or your own enum */
+    A_UINT32 hp_idx;         /* head pointer index (entry index) */
+    A_UINT32 tp_idx;         /* tail pointer index (entry index) */
+    A_UINT32 free_entries;   /* how many entries free */
+    A_UINT32 ring_entries;   /* total entries */
+} wmi_ipa_ring_stat_entry;
+
+/* Event fixed params (TLV-safe layout) */
+typedef struct {
+    A_UINT32 tlv_header;
+    A_UINT32 version; /* Refer to WMI_RING_STATS_EVENT_VERSIONS */
+} wmi_ipa_ring_stats_conf_event_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 5a146e5248a1..a3b7876bbba1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1690
+#define __WMI_REVISION_ 1691
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3423723ef3f6a7260cb15d6f1baefcce3efd69bb Mon Sep 17 00:00:00 2001
From: Kiran Kumar Reddy A E <kreddyae@qti.qualcomm.com>
Date: Sat, 3 Jan 2026 12:01:45 -0800
Subject: [PATCH 106/290] fw-api: CL 31305348 - update fw common interface
 files

Change-Id: I07c60c6125d62f5ca7778ce9ea867e59bc0eec38
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 37 +++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 40816c1f6681..4fa3ef3bdf9a 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1549,6 +1549,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_ipa_ring_stat_entry,
+    WMITLV_TAG_STRUC_wmi_em_dcvs_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -7773,7 +7774,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_beacon_stats, vdev_beacon_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_congestion_stats, vdev_congestion_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_pcie_stats, ctrl_path_em_pcie_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_pcie_stats, ctrl_path_em_pcie_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_dcvs_stats, ctrl_path_em_dcvs_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
 
 /*
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 5b740596370e..72135d85c5f6 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -38235,6 +38235,7 @@ typedef enum {
     WMI_REQUEST_CTRL_PATH_STA_DAR_STAT      = 23,
     WMI_REQUEST_ENHANCED_STAT               = 24,
     WMI_REQUEST_CTRL_PATH_EM_PCIE_STAT      = 25,
+    WMI_REQUEST_CTRL_PATH_EM_DCVS_STAT      = 26,
 } wmi_ctrl_path_stats_id;
 
 typedef enum {
@@ -47684,6 +47685,42 @@ typedef struct {
     A_UINT32 pending_pcie_lanes; /* pending number of PCIe lanes */
 } wmi_em_pcie_stats;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_dcvs_stats */
+    A_UINT32 num_mac; /* Number of active MAC */
+    /* DCVS feature config (holds a wmi_dcvs_config_e value) */
+    A_UINT32 dcvs_cfg;
+    A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */
+    /* pdev_curr_bw:
+     * Per PDEV BW, represented as a FW-internal BW enum
+     * (Thus, this field is intended only for interactive debugging, and not
+     * for interpretation by the host SW.)
+     */
+    A_UINT32 pdev_curr_bw[WMI_EM_PCIE_MAX_NUM_MAC];
+    /* pdev_sla_status:
+     * SLA active status per pdev.
+     * set to '1' if SLA connection is active per pdev, else set to '0'
+     */
+    A_UINT32 pdev_sla_status[WMI_EM_PCIE_MAX_NUM_MAC];
+    A_UINT32 ofdma_ul_user_limit; /* OFDMA UL user limit for SVS entry */
+    A_UINT32 ofdma_dl_user_limit; /* OFDMA DL user limit for SVS entry */
+    /* set to '1' if OFDMA user limit is applied, else set to '0' */
+    A_UINT32 is_ofdma_limit_applied;
+    A_UINT32 cv_corr_limit; /* CV corr limit for SVS entry */
+    /* set to '1' if cv corr limit is applied, else set to '0' */
+    A_UINT32 is_cv_corr_limit_applied;
+    /* set to '1' if mu sniffer limit is applied, else set to '0' */
+    A_UINT32 is_mu_sniff_limit_applied[WMI_EM_PCIE_MAX_NUM_MAC];
+    A_UINT32 pending_dcvs_vote; /* pending vote level (0-SVS, 1-NOM) */
+    /* pending DCVS BW, represented as a FW-internal BW enum */
+    A_UINT32 pending_dcvs_bw;
+    A_UINT32 pending_dcvs_level_switch; /* pending DCVS level change */
+    A_UINT32 current_dcvs_vote; /* current vote level (0-SVS, 1-NOM) */
+    /* current, DCVS BW, represented as a FW-internal BW enum */
+    A_UINT32 current_dcvs_bw;
+    A_UINT32 current_dcvs_level_switch; /* current DCVS level change */
+} wmi_em_dcvs_stats;
+
 
 #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff
 #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a3b7876bbba1..c5bb771be73c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1691
+#define __WMI_REVISION_ 1692
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From befc99cb8784fcbbae4b252c5292fec0e2f7afeb Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 6 Jan 2026 12:01:48 -0800
Subject: [PATCH 107/290] fw-api: CL 31316506 - update fw common interface
 files

Change-Id: I5ac2ff0277ddf0caa84b08f532151b43f2d55cb9
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  56 +++++--
 fw/wmi_unified.h  | 409 +++++++++++++++++++++++++++++++++++++---------
 fw/wmi_version.h  |   2 +-
 3 files changed, 370 insertions(+), 97 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 4fa3ef3bdf9a..35c3db289d5d 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1502,10 +1502,10 @@ typedef enum {
             WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params,
     WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_co_located_chan_info,
-    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, /* deprecated */
     WMITLV_TAG_STRUC_wmi_peer_npca_cap_params,
     WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param,
-    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, /*deprecated*/
     WMITLV_TAG_STRUC_wmi_wfa_config_ml,
     WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param,
@@ -1550,6 +1550,17 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_ipa_ring_stat_entry,
     WMITLV_TAG_STRUC_wmi_em_dcvs_stats,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params,
+    WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status,
+    WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2122,7 +2133,6 @@ typedef enum {
     OP(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID) \
     OP(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID) \
     OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \
-    OP(WMI_PDEV_NPCA_AP_CAP_CMDID) \
     OP(WMI_PEER_NPCA_CAP_CMDID) \
     OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
@@ -2139,6 +2149,8 @@ typedef enum {
     OP(WMI_ROAM_SMD_START_STATUS_CMDID) \
     OP(WMI_VDEV_REPURPOSE_RESP_CMDID) \
     OP(WMI_IPA_RING_STATS_REQ_CMDID) \
+    OP(WMI_VDEV_UHR_CU_CMDID) \
+    OP(WMI_PDEV_UHR_CU_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2476,7 +2488,6 @@ typedef enum {
     OP(WMI_OPT_DP_DIAG_EVENTID) \
     OP(WMI_HW_BLACKLIST_CHAN_EVENTID) \
     OP(WMI_PDEV_SUSPEND_EVENTID) \
-    OP(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID) \
     OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \
     OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \
     OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \
@@ -2490,6 +2501,7 @@ typedef enum {
     OP(WMI_VDEV_UNIFIED_CONNECT_EVENTID) \
     OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \
     OP(WMI_IPA_RING_STATS_CONF_EVENTID) \
+    OP(WMI_PDEV_UHR_CU_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5109,11 +5121,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID);
 
-/* WMI_PDEV_NPCA_AP_CAP_CMDID */
-#define WMITLV_TABLE_WMI_PDEV_NPCA_AP_CAP_CMDID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, wmi_pdev_npca_ap_cap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
-WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_NPCA_AP_CAP_CMDID);
-
 #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_update_pkt_routing_cmd_fixed_param, wmi_pdev_update_pkt_routing_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UPDATE_PKT_ROUTING_CMDID);
@@ -6163,6 +6170,27 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_REPURPOSE_RESP_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, wmi_ipa_ring_stats_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID);
 
+#define WMITLV_TABLE_WMI_VDEV_UHR_CU_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param, wmi_vdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
+
+#define WMITLV_TABLE_WMI_PDEV_UHR_CU_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param, wmi_pdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -7999,11 +8027,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHANNEL_ANI_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids_bitmap, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID);
 
-/* WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID */
-#define WMITLV_TABLE_WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, wmi_pdev_npca_ap_cap_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
-WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID);
-
 /* Roam scan channel list event */
 #define WMITLV_TABLE_WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_channel_list_event_fixed_param, wmi_roam_scan_channel_list_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -8438,7 +8461,10 @@ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_
 WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_ring_stat_entry, ipa_ring_stat_entry, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_CONF_EVENTID);
 
-
+#define WMITLV_TABLE_WMI_PDEV_UHR_CU_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param, wmi_pdev_uhr_cu_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_uhr_cu_status, cu_status, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_EVENTID);
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 72135d85c5f6..c5a8549b3ede 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -602,6 +602,7 @@ typedef enum {
      */
     WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID,
     /**
+     * This command is deprecated - DO NOT USE
      * WMI cmd to to Enable/Disable NPCA and its capabilities
      */
     WMI_PDEV_NPCA_AP_CAP_CMDID,
@@ -612,6 +613,11 @@ typedef enum {
     WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID,
     /* Event to indicate the status of the set tx chainmask command */
     WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID,
+    /**
+     * WMI cmd to send the detailed information of each UHR feature,
+     * that are applicable for critical update.
+     */
+    WMI_PDEV_UHR_CU_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -756,6 +762,9 @@ typedef enum {
     /** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */
     WMI_VDEV_REPURPOSE_RESP_CMDID,
 
+    /** WMI cmd for UHR critical update */
+    WMI_VDEV_UHR_CU_CMDID,
+
 
     /* peer specific commands */
 
@@ -1998,6 +2007,7 @@ typedef enum {
     WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID,
 
     /*
+     * This event is deprecated - DO NOT USE
      * WMI_PDEV_NPCA_AP_CAP_CMDID response event
      */
     WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID,
@@ -2005,6 +2015,9 @@ typedef enum {
     /* Event to share the per-access-category queue pending packets */
     WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID,
 
+    /* WMI event for the UHR critical Update */
+    WMI_PDEV_UHR_CU_EVENTID,
+
 
     /* VDEV specific events */
     /** VDEV started event in response to VDEV_START request */
@@ -20547,9 +20560,6 @@ typedef struct {
 #define WMI_VDEV_START_RESPONSE_INCORRECT_CHANNEL_PARAMS        0x9 /** home channel params are incorrect */
 #define WMI_VDEV_START_RESPONSE_GENERIC_VDEV_START_FAILURE      0xa /** generic reason code for vdev start request reject */
 
-/** NPCA AP CAP response status code */
-#define WMI_PDEV_NPCA_AP_CAP_RESPONSE_STATUS_SUCCESS 0x0 /** NPCA Cap update Success */
-
 
 /** Beacon processing related command and event structures */
 typedef struct {
@@ -48879,15 +48889,6 @@ typedef struct {
      */
 } wmi_pdev_multiple_vdev_restart_resp_event_fixed_param;
 
-typedef struct {
-    /** TLV tag and len; tag equals
-    * WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param */
-    A_UINT32 tlv_header;
-    A_UINT32 pdev_id; /* ID of the pdev this response belongs to */
-    /** Return status. As per WMI_PDEV_NPCA_AP_CAP_RESPONSE_XXXXX */
-    A_UINT32 status;
-} wmi_pdev_npca_ap_cap_resp_event_fixed_param;
-
 /** WMI event for Firmware to report soundbar audio frame statistics to Host **/
 typedef struct {
     /** TLV tag and len **/
@@ -52841,75 +52842,6 @@ typedef struct {
     A_UINT32 size;
 } wmi_pdev_power_boost_mem_addr_cmd_fixed_param;
 
-typedef struct _wmi_npca_info{
-    /* WMI Non-PrimaryChannelAccess channel
-     * Specifically, this is the "other primary" channel used if the
-     * "main primary" is occupied by low-bandwidth OBSS traffic.
-     */
-    wmi_channel npca_chan;
-    /* NPCA punctured bitmap */
-    A_UINT32 puncture_20mhz_bitmap;
-    /*
-     * flags
-     * Bit0     :  NPCA Enabled/Disabled
-     *             WMI_NPCA_AP_CAP_ENABLED_GET / WMI_NPCA_AP_CAP_ENABLED_SET
-     *
-     * Bit1-3   :  NPCA Types
-     *             0:   Type1 - Two STF detectors
-     *             1:   Type2 - One STF detector
-     *             2-7: Reserved for future purpose
-     *             WMI_NPCA_AP_CAP_TYPE_GET / WMI_NPCA_AP_CAP_TYPE_SET
-     *
-     * Bit4-9   :  NPCA Minium Threshold
-     *             The NPCA minimum duration threshold T, in units of 128
-     *             us, is T = 512 + NMDT x 128, where NMDT is the field
-     *             value, which yields a minimum of 512 us and a maximum of
-     *             2432 us. The minimum is chosen to cover at least the
-     *             transmission time of NPCA ICF and ICR exchange plus a
-     *             typical Data and Ack/BA exchange using non-HT or non-
-     *             HT duplicate PPDU format with 6 Mb/s data rate
-     *             WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET
-     *
-     * Bit10-15 :  NPCA Switch Delay
-     *             The time needed by an NPCA STA to switch from the
-     *             BSS primary channel to the NPCA primary channel,
-     *             in units of 4 us.
-     *             WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
-     *
-     * Bit16:21 :  NPCA Switch Back Delay
-     *             The time needed by an NPCA STA to switch from the
-     *             NPCA primary channel to the BSS primary channel,
-     *             in units of 4 us.
-     *             WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
-     *
-     * Bit22:31 :  Reserved
-     */
-    A_UINT32 npca_cap;
-    A_UINT32 reserved; /* reserved for future purpose */
-} wmi_npca_ap_info;
-
-typedef struct {
-    /* WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param */
-    A_UINT32 tlv_header;
-    A_UINT32 pdev_id;
-    wmi_npca_ap_info npca_ap_info;
-} wmi_pdev_npca_ap_cap_cmd_fixed_param;
-
-#define WMI_NPCA_AP_CAP_ENABLED_GET(_var)          WMI_GET_BITS(_var, 0, 1)
-#define WMI_NPCA_AP_CAP_ENABLED_SET(_var, _val)    WMI_SET_BITS(_var, 0, 1, _val)
-
-#define WMI_NPCA_AP_CAP_TYPE_GET(_var)             WMI_GET_BITS(_var, 1, 3)
-#define WMI_NPCA_AP_CAP_TYPE_SET(_var, _val)       WMI_SET_BITS(_var, 1, 3, _val)
-
-#define WMI_NPCA_AP_CAP_MIN_THRES_GET(_var)        WMI_GET_BITS(_var, 4, 4)
-#define WMI_NPCA_AP_CAP_MIN_THRES_SET(_var, _val)  WMI_SET_BITS(_var, 4, 4, _val)
-
-#define WMI_NPCA_AP_CAP_SWT_DELAY_GET(_var)        WMI_GET_BITS(_var, 8, 6)
-#define WMI_NPCA_AP_CAP_SWT_DELAY_SET(_var, _val)  WMI_SET_BITS(_var, 8, 6, _val)
-
-#define WMI_NPCA_AP_CAP_SWTB_DELAY_GET(_var)       WMI_GET_BITS(_var, 14, 6)
-#define WMI_NPCA_AP_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 14, 6, _val)
-
 typedef struct {
     /* WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param */
     A_UINT32 tlv_header;
@@ -53448,6 +53380,321 @@ typedef struct {
 } wmi_ipa_ring_stats_conf_event_fixed_param;
 
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether DPS for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the DPS params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add the required fields below*/
+} wmi_uhr_ap_dps_params;
+
+#define WMI_DPS_MODE_TUPLE_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_DPS_MODE_TUPLE_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_DPS_MODE_TUPLE_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_DPS_MODE_TUPLE_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* npca_chan:
+     * WMI Non-Primary Channel Access channel
+     * Specifically, this is the "other primary" channel used if the
+     * "main primary" is occupied by low-bandwidth OBSS traffic.
+     */
+    wmi_channel npca_chan;
+    /* NPCA punctured bitmap */
+    A_UINT32 puncture_20mhz_bitmap;
+    /*
+     * Bit0-7  : NPCA Primary Channel
+     *           WMI_NPCA_PRIM_CHAN_GET / WMI_NPCA_PRIM_CHAN_SET
+     *
+     * Bit8-11 : NPCA Minium Threshold
+     *           The NPCA minimum duration threshold T, in units of 128
+     *           us, is T = 512 + NMDT x 128, where NMDT is the field
+     *           value, which yields a minimum of 512 us and a maximum of
+     *           2432 us. The minimum is chosen to cover at least the
+     *           transmission time of NPCA ICF and ICR exchange plus a
+     *           typical Data and Ack/BA exchange using non-HT or non-
+     *           HT duplicate PPDU format with 6 Mb/s data rate
+     *           WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET
+     *
+     * Bit12-17: NPCA Switch Delay
+     *           The time needed by an NPCA STA to switch from the
+     *           BSS primary channel to the NPCA primary channel,
+     *           in units of 4 us.
+     *           WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
+     *
+     * Bit18:23: NPCA Switch Back Delay
+     *           The time needed by an NPCA STA to switch from the
+     *           NPCA primary channel to the BSS primary channel,
+     *           in units of 4 us.
+     *           WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
+     *
+     * Bit24:25: The Initial NPCA QSRC field indicates the value
+     *           that is used to initialize the EDCAF QSRC[AC] variables
+     *           when an NPCA STA in the BSS switches to NPCA operation.
+     *           WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET
+     *
+     * Bit26   : The MOPLEN NPCA field indicates which conditions can be used
+     *           to initiate an NPCA operation. A value of 1 in this field
+     *           indicates that both PHYLEN NPCA operation and MOPLEN NPCA
+     *           operations are permitted in the BSS.
+     *           A value of 0 in this field indicates that only PHYLEN NPCA
+     *           operation is allowed in the BSS.
+     *           WMI_NPCA_AP_CAP_MOPLEN_GET / _SET
+     *
+     * Bit27   : The NPCA Disabled Subchannel Bitmap Present field indicates
+     *           whether the NPCA Disabled Subchannel Bitmap field is present.
+     *           This field indicates that the NPCA Disabled Subchannel Bitmap
+     *           field is present.
+     *           WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET / _SET
+     *
+     * Bit28-31: Reserved
+     */
+    A_UINT32 npca_cap1;
+
+    /*
+     * Bit0-15 : The NPCA Disabled Subchannel Bitmap field is a bitmap where
+     *           the lowest numbered bit corresponds to the 20 MHz subchannel
+     *           that lies within the BSS bandwidth and is the lowest in
+     *           frequency of the set of all 20MHz subchannels within the BSS
+     *           bandwidth. Each successive bit in the bitmap corresponds to
+     *           the next higher frequency 20 MHz subchannel. A bit in the
+     *           bitmap that lies within the BSS bandwidth is set to 1 to
+     *           indicate that the corresponding 20MHz subchannel is
+     *           punctured and is set to 0 to indicate that the corresponding
+     *           20 MHz subchannel is not punctured. A bit in the bitmap that
+     *           falls outside of the BSS bandwidth is reserved.
+     *           This field is present when the value of the NPCA Disabled
+     *           Subchannel Bitmap Field Present field is equal to 1, and
+     *           not present, otherwise.
+     *           WMI_NPCA_AP_CAP_DISABLED_SB_GET / _SET
+     *
+     * Bit16-31: Reserved
+     */
+    A_UINT32 npca_cap2;
+} wmi_uhr_ap_npca_params;
+
+#define WMI_NPCA_MODE_TUPLE_ENABLE_GET(_var)                WMI_GET_BITS(_var, 0, 1)
+#define WMI_NPCA_MODE_TUPLE_ENABLE_SET(_var, _val)          WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_NPCA_MODE_TUPLE_UPDATE_GET(_var)                WMI_GET_BITS(_var, 1, 1)
+#define WMI_NPCA_MODE_TUPLE_UPDATE_SET(_var, _val)          WMI_SET_BITS(_var, 1, 1, _val)
+
+#define WMI_NPCA_PRIM_CHAN_GET(_var)                        WMI_GET_BITS(_var, 0, 8)
+#define WMI_NPCA_PRIM_CHAN_SET(_var, _val)                  WMI_SET_BITS(_var, 0, 8, _val)
+
+#define WMI_NPCA_AP_CAP_MIN_THRESH_GET(_var)                WMI_GET_BITS(_var, 8, 4)
+#define WMI_NPCA_AP_CAP_MIN_THRESH_SET(_var, _val)          WMI_SET_BITS(_var, 8, 4, _val)
+
+#define WMI_NPCA_AP_CAP_SWITCH_DELAY_GET(_var)              WMI_GET_BITS(_var, 12, 6)
+#define WMI_NPCA_AP_CAP_SWITCH_DELAY_SET(_var, _val)        WMI_SET_BITS(_var, 12, 6, _val)
+
+#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET(_var)         WMI_GET_BITS(_var, 18, 6)
+#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_SET(_var, _val)   WMI_SET_BITS(_var, 18, 6, _val)
+
+#define WMI_NPCA_AP_CAP_QSRC_GET(_var)                      WMI_GET_BITS(_var, 24, 2)
+#define WMI_NPCA_AP_CAP_QSRC_SET(_var, _val)                WMI_SET_BITS(_var, 24, 2, _val)
+
+#define WMI_NPCA_AP_CAP_MOPLEN_GET(_var)                    WMI_GET_BITS(_var, 26, 1)
+#define WMI_NPCA_AP_CAP_MOPLEN_SET(_var, _val)              WMI_SET_BITS(_var, 26, 1, _val)
+
+#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET(_var)       WMI_GET_BITS(_var, 27, 1)
+#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_SET(_var, _val) WMI_SET_BITS(_var, 27, 1, _val)
+
+#define WMI_NPCA_AP_CAP_DISABLED_SB_GET(_var)               WMI_GET_BITS(_var, 0, 16)
+#define WMI_NPCA_AP_CAP_DISABLED_SB_SET(_var, _val)         WMI_SET_BITS(_var, 0, 16, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add any new required fields below */
+} wmi_uhr_ap_duo_params;
+
+#define WMI_UHR_AP_DUO_PARAMS_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_UHR_AP_DUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_UHR_AP_DUO_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_UHR_AP_DUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     *
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     *
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     *
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add any new required fields below */
+} wmi_uhr_ap_pedca_params;
+
+#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add any new required fields below */
+} wmi_uhr_ap_dbe_params;
+
+#define WMI_UHR_AP_DBE_PARAMS_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_UHR_AP_DBE_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_UHR_AP_DBE_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_UHR_AP_DBE_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add any new required fields below */
+} wmi_uhr_ap_puo_params;
+
+#define WMI_UHR_AP_PUO_PARAMS_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_UHR_AP_PUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_UHR_AP_PUO_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_UHR_AP_PUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /*
+     * Bit0    : Mode enable - 1 / disable - 0
+     *           This indicates whether NPCA for this VAP is enabled or disabled
+     * Bit1    : Mode Update
+     *           This should be set when any of the NPCA params needs an update
+     * Bit2-31 : Reserved
+     */
+    A_UINT32 mode_tuple_field;
+    /* Add any new required fields below */
+} wmi_uhr_ap_elr_reception_params;
+
+#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_GET(_var)       WMI_GET_BITS(_var, 0, 1)
+#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val)
+
+#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
+#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /* This fixed param TLV will be followed by the below TLVs
+     *   - wmi_uhr_ap_dps_params
+     *   - wmi_uhr_ap_npca_params
+     *   - wmi_uhr_ap_duo_params
+     *   - wmi_uhr_ap_pedca_params
+     *   - wmi_uhr_ap_dbe_params
+     *   - wmi_uhr_ap_ap_puo_params
+     *   - wmi_uhr_ap_elr_reception_params
+     */
+} wmi_vdev_uhr_cu_cmd_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* This fixed param TLV will be followed by the below TLVs
+     *   - wmi_uhr_ap_dps_params[]
+     *   - wmi_uhr_ap_npca_params[]
+     *   - wmi_uhr_ap_duo_params[]
+     *   - wmi_uhr_ap_pedca_params[]
+     *   - wmi_uhr_ap_dbe_params[]
+     *   - wmi_uhr_ap_ap_puo_params[]
+     *   - wmi_uhr_ap_elr_reception_params[]
+     */
+} wmi_pdev_uhr_cu_cmd_fixed_param;
+
+typedef enum {
+    WMI_VDEV_UHR_CU_IN_PROGRESS,
+    WMI_VDEV_UHR_CU_ESTABLISHED,
+    WMI_VDEV_UHR_CU_SESSION_END,
+} wmi_vdev_uhr_cu_state;
+
+typedef struct {
+   /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /* Refer wmi_vdev_uhr_cu_state*/
+    A_UINT32 status;
+} wmi_vdev_uhr_cu_status;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 pdev_id;
+
+    /* This fixed param TLV will be followed by the below TLVs
+     *   - wmi_vdev_uhr_cu_status[]
+     */
+} wmi_pdev_uhr_cu_event_fixed_param;
+
+
 
 /* ADD NEW DEFS HERE */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c5bb771be73c..0b476f1ffa20 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1692
+#define __WMI_REVISION_ 1693
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From da36413400139ceae76aa2d8b17059d62ec0ce19 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 7 Jan 2026 12:01:49 -0800
Subject: [PATCH 108/290] fw-api: CL 31328053 - update fw common interface
 files

Change-Id: I574f5d437acc21948c3cbbbcdc30610f95f4cffe
CRs-Fixed: 3830439
---
 fw/htt.h       | 16 ++++++++-
 fw/htt_stats.h | 95 +++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 109 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index d052173156b8..919575802bc4 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -890,6 +890,20 @@ typedef enum {
     HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG         = 237, /* htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv, TOPIC=advanced */
     HTT_STATS_RX_PDEV_BN_UL_MIMO_USER_TAG           = 238, /* htt_stats_rx_pdev_bn_ul_mimo_user_tlv */
     HTT_STATS_TX_PDEV_BN_UL_MU_MIMO_TAG             = 239, /* htt_stats_tx_pdev_bn_ul_mu_mimo_tlv */
+    /* HTT_STATS_PDEV_ANI_HIST_TAG:
+     * htt_stats_pdev_ani_hist_tlv
+     * ani_hist_type:
+     *     0 = 1 sec,
+     *     1 = granular
+     *     2 = 1 sec disabled
+     *     3 = granular disabled
+     */
+    HTT_STATS_PDEV_ANI_HIST_TAG                     = 240,
+    HTT_STATS_ANI_SCALAR_TAG                        = 241, /* htt_stats_ani_scalar_tlv */
+    HTT_STATS_ANI_PKT_CNT_TAG                       = 242, /* htt_stats_ani_pkt_cnt_tlv */
+    HTT_STATS_ANI_CRC_PASS_TAG                      = 243, /* htt_stats_ani_crc_pass_tlv */
+    HTT_STATS_ANI_PER_BLK_ERR_TAG                   = 244, /* htt_stats_ani_per_blk_err_tlv */
+    HTT_STATS_ANI_OTA_ERR_TAG                       = 245, /* htt_stats_ani_ota_err_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index faa6680df3f7..69973598075d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -882,6 +882,14 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT = 80,
 
+    /** HTT_DBG_EXT_STATS_ANI_HISTOGRAM
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_phy_ani_hist_tlv
+     *   */
+    HTT_DBG_EXT_STATS_ANI_HISTOGRAM = 81,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -12330,6 +12338,91 @@ typedef struct {
 } htt_vdevs_txrx_stats_t;
 #endif /* ATH_TARGET */
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /** The channel number on which these stats were collected */
+    A_UINT32 chan_num;
+    /** num of records provided */
+    A_UINT32 num_records;
+    /** Indicates the stats collection interval
+     *  Valid Values:
+     *      100  - For the 100 ms interval stats histogram
+     *      1000 - For 1 sec interval histogram
+     */
+    A_UINT32 collection_interval;
+    /** ani_hist_type:
+     * single flag to differentiate histogram type
+     * Valid Values:
+     *      0 - (default) For 1 sec interval histogram
+     *      1 - For granular (100 ms) interval histogram
+     *      2 - 1 sec histogram not enabled
+     *      3 - Granular histogram not enabled
+     */
+    A_UINT32 ani_hist_type;
+} htt_stats_pdev_ani_hist_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 rx_ofdma_timing_err_cnt;
+    A_UINT32 rx_cck_fail_cnt;
+    A_UINT32 rx_cck1_fail_cnt;
+    A_UINT32 rx_cck2_fail_cnt;
+    A_UINT32 rx_cck7_fail_cnt;
+    A_UINT32 mactx_abort_cnt;
+    A_UINT32 macrx_abort_cnt;
+    A_UINT32 phytx_abort_cnt;
+    A_UINT32 phyrx_abort_cnt;
+    A_UINT32 phyrx_defer_abort_cnt;
+    A_UINT32 rx_sizing1_event_cnt; /* a.k.a sizing1 */
+    A_UINT32 rx_sizing2_event_cnt; /* a.k.a sizing2 */
+} htt_stats_ani_scalar_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* rx_pkt_cnt -
+     * Received EOP (end-of-packet) count per packet type;
+     * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax;
+     * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ
+     */
+    A_UINT32 rx_pkt_cnt[9];
+} htt_stats_ani_pkt_cnt_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* rx_pkt_crc_pass_cnt -
+     * CRC pass count per packet type;
+     * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax;
+     * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ
+     */
+    A_UINT32 rx_pkt_crc_pass_cnt[9];
+} htt_stats_ani_crc_pass_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* per_blk_err_cnt -
+     * Error count per error source;
+     * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG;
+     * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE;
+     * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF
+     * [13-15]=RSVD
+     */
+    A_UINT32 per_blk_err_cnt[16];
+} htt_stats_ani_per_blk_err_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* rx_ota_err_cnt -
+     * RXTD OTA (over-the-air) error count per error reason;
+     * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail;
+     * [3] = cck fail; [4] = power surge;
+     * [5] = btcf timing timeout error; [6] = btcf packet detect error;
+     * [7] = coarse timing timeout error
+     * [8-9]=RSVD
+     */
+    A_UINT32 rx_ota_err_cnt[10];
+} htt_stats_ani_ota_err_tlv;
+
+
 /* PAPRD and power boost stats and counters */
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;

From 2fad0241ca95e53495c5934c61dcf20668c250cf Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 8 Jan 2026 12:04:14 -0800
Subject: [PATCH 109/290] fw-api: CL 31338231 - update fw common interface
 files

Change-Id: I3144f9432646710c0b41c6053be757747149b400
CRs-Fixed: 3830439
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 95 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 919575802bc4..16e6134a8e61 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -904,6 +904,7 @@ typedef enum {
     HTT_STATS_ANI_CRC_PASS_TAG                      = 243, /* htt_stats_ani_crc_pass_tlv */
     HTT_STATS_ANI_PER_BLK_ERR_TAG                   = 244, /* htt_stats_ani_per_blk_err_tlv */
     HTT_STATS_ANI_OTA_ERR_TAG                       = 245, /* htt_stats_ani_ota_err_tlv */
+    HTT_STATS_RESET_HISTORY_TAG                     = 246, /* htt_stats_reset_history_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 69973598075d..a5147b8e829b 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -890,6 +890,14 @@ enum htt_dbg_ext_stats_type {
      *   */
     HTT_DBG_EXT_STATS_ANI_HISTOGRAM = 81,
 
+    /** HTT_DBG_EXT_STATS_RESET_HISTORY
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_reset_history_tlv
+     */
+    HTT_DBG_EXT_STATS_RESET_HISTORY = 82,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -15691,4 +15699,90 @@ typedef struct {
 } htt_stats_pdev_sam_tlv;
 
 
+#define HTT_STATS_RESET_HISTORY_MAX_ENTRIES 10
+
+/**
+ * @brief TLV structure for wifistats 82 (reset history)
+ *
+ * This structure holds the last 10 reset history entries.
+ * The entries are copied from the firmware's internal circular buffer.
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * @brief An array of structures, each holding the details of a single
+     *        reset event. The entries are ordered chronologically from
+     *        oldest to newest.
+     */
+    struct {
+        A_UINT32 timestamp_ms;
+        /* reset_flags is only for debugging, not for host interpretation */
+        A_UINT32 reset_flags;
+        /* reset_cause is only for debugging, not for host interpretation */
+        A_UINT32 reset_cause;
+        /* reset_reason is only for debugging, not for host interpretation */
+        A_UINT32 reset_reason;
+        A_UINT32 phy_mode;
+        union {
+            A_UINT32 channel_freq;
+            struct {
+                A_UINT32
+                    mhz:              16,
+                    band_center_freq1:16;
+            };
+        };
+        union {
+            A_UINT32 channel_info;
+            struct {
+                A_UINT32
+                    flags:    16, /* only for debug, not for host interpret */
+                    phy_id:    8,
+                    swprofile: 8; /* only for debug, not for host interpret */
+            };
+        };
+        union {
+            A_UINT32 home_channel_info;
+            struct {
+                A_UINT32
+                    is_home_chan: 1,
+                    reserved:    31;
+            };
+        };
+        A_UINT32 reserved_dwords[2]; /* reserved for future use */
+    } reset_history[HTT_STATS_RESET_HISTORY_MAX_ENTRIES];
+    A_UINT32 idx;   /** Current write index of the circular buffer */
+    A_UINT32 count; /** Total number of resets captured (up to 10) */
+} htt_stats_reset_history_tlv;
+
+#define HTT_STATS_RESET_HISTORY_MHZ_GET(word) \
+    ((word) & 0x0000ffff)
+#define HTT_STATS_RESET_HISTORY_MHZ_SET(word, value) \
+    ((word) |= ((value) & 0x0000ffff))
+
+#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \
+    (((word) & 0xffff0000) >> 16)
+#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_SET(word, value) \
+    ((word) |= (((value) << 16) & 0xffff0000))
+
+#define HTT_STATS_RESET_HISTORY_FLAGS_GET(word) \
+    ((word) & 0x0000ffff)
+#define HTT_STATS_RESET_HISTORY_FLAGS_SET(word, value) \
+    ((word) |= ((value) & 0x0000ffff))
+
+#define HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) \
+    (((word) & 0x00ff0000) >> 16)
+#define HTT_STATS_RESET_HISTORY_PHY_ID_SET(word, value) \
+    ((word) |= (((value) << 16) & 0x00ff0000))
+
+#define HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) \
+    (((word) & 0xff000000) >> 24)
+#define HTT_STATS_RESET_HISTORY_SWPROFILE_SET(word, value) \
+    ((word) |= (((value) << 24) & 0xff000000))
+
+#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) \
+    (((word) & 0x00000001) >> 0)
+#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_SET(word, value) \
+    ((word) |= (((value) << 0) & 0x00000001))
+
+
 #endif /* __HTT_STATS_H__ */

From cbd2592170ed250b6ad7ed5f1647fe269381a81e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 8 Jan 2026 12:08:20 -0800
Subject: [PATCH 110/290] fw-api: CL 31341426 - update fw common interface
 files

Change-Id: I117b050e97ea2d8ec465c50bbcaba6e58ef6e11e
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 129 ++++++++++++++++++++++++++---------------------
 fw/wmi_version.h |   4 +-
 2 files changed, 74 insertions(+), 59 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c5a8549b3ede..8860e335c6cd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -611,8 +611,13 @@ typedef enum {
      * for the pdev
      */
     WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID,
-    /* Event to indicate the status of the set tx chainmask command */
-    WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID,
+    /* WMI_PDEV_RESERVED_CMDID:
+     * The value is now deprecated / reserved - it was initially erroneously
+     * given to WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID, but now that
+     * WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID has been moved to the EVENTID
+     * enum, this value is available to use for a future PDEV CMDID.
+     */
+    WMI_PDEV_RESERVED_CMDID,
     /**
      * WMI cmd to send the detailed information of each UHR feature,
      * that are applicable for critical update.
@@ -1857,166 +1862,176 @@ typedef enum {
 
     /* PDEV specific events */
     /** TPC config for the current operating channel */
-    WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV),
+    WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), /* 0 */
     /** Channel stats event    */
-    WMI_CHAN_INFO_EVENTID,
+    WMI_CHAN_INFO_EVENTID, /* 1 */
 
     /** PHY Error specific WMI event */
-    WMI_PHYERR_EVENTID,
+    WMI_PHYERR_EVENTID, /* 2 */
 
     /** eeprom dump event  */
-    WMI_PDEV_DUMP_EVENTID,
+    WMI_PDEV_DUMP_EVENTID, /* 3 */
 
     /** traffic pause event */
-    WMI_TX_PAUSE_EVENTID,
+    WMI_TX_PAUSE_EVENTID, /* 4 */
 
     /** DFS radar event  */
-    WMI_DFS_RADAR_EVENTID,
+    WMI_DFS_RADAR_EVENTID, /* 5 */
 
     /** track L1SS entry and residency event */
-    WMI_PDEV_L1SS_TRACK_EVENTID,
+    WMI_PDEV_L1SS_TRACK_EVENTID, /* 6 */
 
     /** Report current temperature of the chip in Celcius degree */
-    WMI_PDEV_TEMPERATURE_EVENTID,
+    WMI_PDEV_TEMPERATURE_EVENTID, /* 7 */
 
     /** Extension of WMI_SERVICE_READY msg with extra target capability info */
-    WMI_SERVICE_READY_EXT_EVENTID,
+    WMI_SERVICE_READY_EXT_EVENTID, /* 8 */
 
     /** FIPS test mode event */
-    WMI_PDEV_FIPS_EVENTID,
+    WMI_PDEV_FIPS_EVENTID, /* 9 */
 
     /** Channel hopping avoidance */
-    WMI_PDEV_CHANNEL_HOPPING_EVENTID,
+    WMI_PDEV_CHANNEL_HOPPING_EVENTID, /* 10 */
 
     /** CCK ANI level event */
-    WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
+    WMI_PDEV_ANI_CCK_LEVEL_EVENTID, /* 11 */
 
     /** OFDM ANI level event */
-    WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
+    WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, /* 12 */
 
     /** Tx PPDU params */
-    WMI_PDEV_TPC_EVENTID,
+    WMI_PDEV_TPC_EVENTID, /* 13 */
 
     /** NF Cal Power in DBR/DBM for all channels */
-    WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
+    WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, /* 14 */
 
     /** SOC/PDEV events */
-    WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
-    WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
-    WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
+    WMI_PDEV_SET_HW_MODE_RESP_EVENTID, /* 15 */
+    WMI_PDEV_HW_MODE_TRANSITION_EVENTID, /* 16 */
+    WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, /* 17 */
     /** Report ANT DIV feature's status */
-    WMI_PDEV_ANTDIV_STATUS_EVENTID,
+    WMI_PDEV_ANTDIV_STATUS_EVENTID, /* 18 */
     /** Chip level Power stats */
-    WMI_PDEV_CHIP_POWER_STATS_EVENTID,
+    WMI_PDEV_CHIP_POWER_STATS_EVENTID, /* 19 */
     /** Power Save Failure Detected */
-    WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
+    WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, /* 20 */
 
     /* Event to report the switch count in csa of one or more VDEVs */
-    WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
+    WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, /* 21 */
 
     /** Report the caldata version to host */
-    WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
+    WMI_PDEV_CHECK_CAL_VERSION_EVENTID, /* 22 */
 
     /** Report chain RSSI and antenna index to host */
-    WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
+    WMI_PDEV_DIV_RSSI_ANTID_EVENTID, /* 23 */
 
     /** provide noise floor and cycle counts for a channel */
-    WMI_PDEV_BSS_CHAN_INFO_EVENTID,
+    WMI_PDEV_BSS_CHAN_INFO_EVENTID, /* 24 */
 
     /** Response received the ctl table to host */
-    WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
+    WMI_PDEV_UPDATE_CTLTABLE_EVENTID, /* 25 */
 
-    WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
+    WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, /* 26 */
 
-    WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
+    WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, /* 27 */
 
     /** WMI Event to deliver CTL Failsafe application */
-    WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
+    WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, /* 28 */
 
     /* Event to report the switch count in BSS color of one or more VDEVs */
-    WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
+    WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, /* 29 */
 
     /* Event to send cold boot calibration data */
-    WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
+    WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, /* 30 */
 
     /* Event to report a rogue ap info that is detected in fw */
-    WMI_PDEV_RAP_INFO_EVENTID,
+    WMI_PDEV_RAP_INFO_EVENTID, /* 31 */
 
-    WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
+    WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, /* 32 */
 
     /** 2nd extension of SERVICE_READY msg with extra target capability info */
-    WMI_SERVICE_READY_EXT2_EVENTID,
+    WMI_SERVICE_READY_EXT2_EVENTID, /* 33 */
 
     /**
      * vdev restart response for multiple vdevs in response to
      * MULTIPLE_VDEV_RESTART_REQUEST
      */
-    WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID,
+    WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, /* 34 */
 
     /** WMI event in response to TPC STATS command */
-    WMI_PDEV_GET_TPC_STATS_EVENTID,
+    WMI_PDEV_GET_TPC_STATS_EVENTID, /* 35 */
 
     /* Event to get DPD status from HALPHY */
-    WMI_PDEV_GET_DPD_STATUS_EVENTID,
+    WMI_PDEV_GET_DPD_STATUS_EVENTID, /* 36 */
 
     /* Event to get Calibration status from HALPHY */
-    WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID,
+    WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, /* 37 */
 
     /* Event to set halphy cal bitmap */
-    WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID,
+    WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, /* 38 */
 
     /* Event to get AOA phasedelta values from HALPHY */
-    WMI_PDEV_AOA_PHASEDELTA_EVENTID,
+    WMI_PDEV_AOA_PHASEDELTA_EVENTID, /* 39 */
 
-    WMI_PDEV_FIPS_EXTEND_EVENTID,
+    WMI_PDEV_FIPS_EXTEND_EVENTID, /* 40 */
 
     /* Event to send packet log decode information */
-    WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID,
+    WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, /* 41 */
 
     /**
      * RSSI dB to dBm conversion params info event
      * sent to host after channel/bw/chainmask change per pdev.
      */
-    WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID,
+    WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, /* 42 */
 
     /* Event to indicate Schedule tid queue suspended info */
-    WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID,
+    WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, /* 43 */
 
     /* Event to send target rate to power table update status */
-    WMI_PDEV_SET_TGTR2P_TABLE_EVENTID,
+    WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, /* 44 */
 
     /* Event to indicate completion on RF path */
-    WMI_PDEV_SET_RF_PATH_RESP_EVENTID,
+    WMI_PDEV_SET_RF_PATH_RESP_EVENTID, /* 45 */
 
     /* Event to get AOA phasedelta values for all gain tables from HALPHY */
-    WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID,
+    WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* 46 */
 
     /* Event to indicate the status of WiFi Radar calibration */
-    WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID,
+    WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, /* 47 */
 
     /* Event to indicate xLNA is enabled */
-    WMI_PDEV_ENABLE_XLNA_EVENTID,
+    WMI_PDEV_ENABLE_XLNA_EVENTID, /* 48 */
 
     /* Event to indicate ANN Power Boost update status from Target */
-    WMI_PDEV_POWER_BOOST_EVENTID,
+    WMI_PDEV_POWER_BOOST_EVENTID, /* 49 */
 
     /*
      * WMI event to share Wi-Fi Radar -
      * monostatic Wi-Fi sensing technique capabalites
      */
-    WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID,
+    WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID, /* 50 */
 
     /*
      * This event is deprecated - DO NOT USE
      * WMI_PDEV_NPCA_AP_CAP_CMDID response event
      */
-    WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID,
+    WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID, /* 51 */
 
     /* Event to share the per-access-category queue pending packets */
-    WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID,
+    WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID, /* 52 */
 
     /* WMI event for the UHR critical Update */
-    WMI_PDEV_UHR_CU_EVENTID,
+    WMI_PDEV_UHR_CU_EVENTID, /* 53 */
+
+
+
+    /***
+     *** add new WMI_PDEV EVENTID defs directly above here,
+     *** until EVENTID offset 89 is reached, then continue
+     *** from 90 below WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID
+     ***/
+    WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID = 0x405a, /* 89 */
+
 
 
     /* VDEV specific events */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0b476f1ffa20..adfac5a22cec 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1693
+#define __WMI_REVISION_ 1694
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 86dd9cd294fa0ced8e859e133d2132916d9628fc Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 9 Jan 2026 12:04:49 -0800
Subject: [PATCH 111/290] fw-api: CL 31348242 - update fw common interface
 files

Change-Id: I9f5427e5a5fe2b058f986e491a156c033c5103c7
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 4 +++-
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8860e335c6cd..656378699327 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -52614,7 +52614,9 @@ typedef struct {
 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_WEB_BROWSING_S              19
 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_M 0x00100000
 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_S 20
-/* bits 21-31 are reserved for new interactive traffic types */
+#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_M                  0x00200000
+#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_S                  21
+/* bits 22-31 are reserved for new interactive traffic types */
 
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_active_traffic_map_cmd_fixed_param */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index adfac5a22cec..0b4b622bd6fe 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1694
+#define __WMI_REVISION_ 1695
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3dc3ed51d04601aad2e8eacbae29d0a9caa81a09 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 9 Jan 2026 12:08:48 -0800
Subject: [PATCH 112/290] fw-api: CL 31351405 - update fw common interface
 files

Change-Id: I16609f4f4ab698ce61ddb9db7a9055ab3aff5c4f
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 5 +++++
 fw/wmi_version.h | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 656378699327..eae73b284fe2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -20027,6 +20027,11 @@ typedef enum {
      */
     WMI_VDEV_PARAM_ACK_RATE,                              /* 0xCE */
 
+    /* Enable TWT in Concurrency for this vdev */
+    WMI_VDEV_PARAM_ENABLE_TWT_CONCURRENCY,                /* 0xCF */
+
+    /* Use BTWT ID0 for this vdev */
+    WMI_VDEV_PARAM_USE_BTWT_ID0,                          /* 0xD0 */
 
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0b4b622bd6fe..b04895d91adc 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1695
+#define __WMI_REVISION_ 1696
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 068cf92467f7dd3648357915e212a6cc770194ba Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 10 Jan 2026 12:02:14 -0800
Subject: [PATCH 113/290] fw-api: CL 31360546 - update fw common interface
 files

Change-Id: Ie6d3dcc98c772a96fea8a40fed7304c5a0839644
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index a5147b8e829b..fb6a04c9407c 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -3918,6 +3918,15 @@ typedef struct {
      * completed with error(s)
      */
     A_UINT32 standalone_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM];
+
+    /** 11bn UHR BSRP trigger to DPS client sent over the air */
+    A_UINT32 sta_dps_bn_bsr_trigger[HTT_NUM_AC_WMM];
+    /** 11bn UHR MU RTS trigger to DPS client sent over the air */
+    A_UINT32 sta_dps_bn_mu_rts_trigger[HTT_NUM_AC_WMM];
+    /** 11bn UHR BSRP trigger to DPS client completed with error(s) */
+    A_UINT32 sta_dps_bn_bsr_trigger_err[HTT_NUM_AC_WMM];
+    /** 11bn UHR MU RTS trigger to DPS client completed with errors(s) */
+    A_UINT32 sta_dps_bn_mu_rts_trigger_err[HTT_NUM_AC_WMM];
 } htt_stats_tx_selfgen_bn_tlv;
 
 typedef struct { /* DEPRECATED */

From aac2fc3ced203b6c0d51cd05c0575cb30fd424c7 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 11 Jan 2026 12:02:05 -0800
Subject: [PATCH 114/290] fw-api: CL 31362795 - update fw common interface
 files

Change-Id: I8be8809cb217cd190a37159ee6e2e246bfa93f23
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fb6a04c9407c..cd62325cd86f 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -5511,6 +5511,28 @@ typedef struct {
     A_UINT32 num_subcycles_no_sort;
     /** num of times DPS client is scheduled */
     A_UINT32 num_dps_client_scheduled;
+    /**
+     * Number of first sched_cmd allowed for DL+UL/UL+DL sched_cmd combining
+     */
+    A_UINT32 num_allowed_first_sched_command_for_combining;
+    /**
+     * Number of second sched_cmd allowed for DL+UL/UL+DL sched_cmd combining
+     */
+    A_UINT32 num_allowed_second_command_for_combining;
+    /**
+     * Number of first sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd
+     * combining
+     */
+    A_UINT32 num_aborted_first_sched_command;
+    /**
+     * Number of second sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd
+     * combining
+     */
+    A_UINT32 num_aborted_second_sched_command;
+    /** Number combined sched_cmds sucessfully transmitted */
+    A_UINT32 total_combined_sched_cmds_success;
+    /** Number combined sched_cmds failed to transmit */
+    A_UINT32 total_combined_sched_cmds_failed;
 } htt_stats_tx_pdev_scheduler_txq_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv

From 1474e194976202f50a00293fab586605c538c980 Mon Sep 17 00:00:00 2001
From: Sanskar Jain <sansjain@qti.qualcomm.com>
Date: Tue, 25 Nov 2025 10:22:26 +0530
Subject: [PATCH 115/290] qcacld-3.0: Add buffer overflow check in
 wma_fill_rx_stats function

The wma_fill_rx_stats function accesses wmi_rx array using index
wmi_rx[i * WLAN_MAX_AC + k] without validating that wmi_rx buffer
has sufficient elements. This can lead to buffer overflow when
num_peer_ac_rx_stats * WLAN_MAX_AC exceeds the available num_rx_stats.

Add validation check to ensure wmi_rx does not reach out of bound
before accessing the array.

CRs-Fixed: 4315163
Change-Id: I91cf41d8f931aef7d5666b2744fc5d8a167d43f3
---
 core/wma/src/wma_utils.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/core/wma/src/wma_utils.c b/core/wma/src/wma_utils.c
index 3f34979096b8..68bd4241fd04 100644
--- a/core/wma/src/wma_utils.c
+++ b/core/wma/src/wma_utils.c
@@ -1361,6 +1361,15 @@ wma_fill_rx_stats(struct sir_wifi_ll_ext_stats *ll_stats,
 			 wmi_peer_rx, wmi_rx, peer_stats);
 		return QDF_STATUS_E_FAILURE;
 	}
+
+	/* Check if num_rx_stats is sufficient to avoid buffer overflow */
+	if (param_buf->num_rx_stats <
+	    fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC) {
+		wma_err("Insufficient rx_stats buffer: available %d, required %d",
+			param_buf->num_rx_stats,
+			fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC);
+		return QDF_STATUS_E_FAILURE;
+	}
 	for (i = 0; i < fix_param->num_peer_ac_rx_stats; i++) {
 		uint32_t peer_id = wmi_peer_rx[i].peer_id;
 		struct sir_wifi_rx *ac;

From 9bdb071c770cb59218227cd492076a7f9e1fc412 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 13 Jan 2026 12:04:42 -0800
Subject: [PATCH 116/290] fw-api: CL 31376775 - update fw common interface
 files

Change-Id: Ia7305ce1e4812915798d59a0b644464a76009a27
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  8 +++++--
 fw/wmi_unified.h  | 53 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 35c3db289d5d..28cb810c2b1d 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1561,6 +1561,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status,
     WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_config,
+    WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -5476,7 +5478,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_GET_SCHED_METHOD_CMDID);
 /* CFR Capture Filter cmd */
 #define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_cmd_fixed_param, wmi_cfr_capture_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_config, fix_agc_gain_config, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_CMDID);
 
 /* VLAN config */
@@ -8431,7 +8434,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_RESP_EVENTID);
 
 /* CFR capture filter response event */
 #define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_RESP_EVENTID(id,op,buf,len) \
-WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, wmi_cfr_capture_filter_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, wmi_cfr_capture_filter_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_info, fix_agc_gain_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID);
 
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index eae73b284fe2..d07b82a8f873 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -47591,6 +47591,44 @@ typedef struct {
 #define WMI_CFR_FRAME_SEQ_NUM_SET(frame_seq_ctrl, value) \
         WMI_SET_BITS(frame_seq_ctrl, 4, 12, value)
 
+/**
+ * CFR capture fix agc gain status codes
+ * These values are sent to host in wmi_cfr_capture_filter_resp_event
+ */
+typedef enum {
+    /** Configuration successful */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_STATUS_SUCCESS             = 0,
+
+    /** RX AGC Gain index out of range */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_INDEX_OUT_OF_RANGE  = 1,
+
+    /** Fixed AGC not supported in current PHY mode */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_PHYMODE_REJECT      = 2,
+
+    /** Failed to disable Scan */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SCAN_DISABLE_FAILED = 3,
+
+    /** Failed to disable ANI */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_ANI_DISABLE_FAILED  = 4,
+
+    /** AGC control is already owned by another module */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_AGC_CONFLICT        = 5,
+
+    /** Another CFR/AGC session is in progress */
+    WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SESSION_BUSY        = 6,
+} wmi_cfr_capture_fix_agc_gain_status_t;
+
+typedef struct {
+    /* Info of the CFR capture fix AGC gain configuration based on wmi_cfr_capture_fix_agc_gain_status_t */
+    A_UINT32 tlv_header;
+
+    /* wmi_cfr_capture_fix_agc_gain_status_t */
+    A_UINT32 status;
+
+    /* RX agc gain index for cfr capture in HW */
+    A_UINT32 cfr_agc_gain_index;
+} wmi_cfr_capture_fix_agc_gain_info;
+
 /**
  * CFR capture filter command response status codes
  * These values are sent to host in wmi_cfr_capture_filter_resp_event
@@ -48488,6 +48526,21 @@ typedef struct {
     A_UINT32 data_subtype_filter;
 } wmi_cfr_filter_group_config;
 
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cfr_fix_agc_gain_config */
+
+    /*
+     * 0 - disable CFR fix agc gain feature
+     * 1 - enable CFR fix agc gain feature
+     */
+    A_UINT32 cfr_fix_agc_gain_enable;
+
+    /* Forced RX agc gain index for cfr capture, which is set by user in host */
+    A_UINT32 force_cfr_agc_gain_index;
+} wmi_cfr_capture_fix_agc_gain_config;
+
+
 #define WMI_CFR_DIRECTED_FTM_ACK_EN_BIT_POS           0
 #define WMI_CFR_ALL_FTM_ACK_EN_BIT_POS                1
 #define WMI_CFR_NDPA_NDP_DIRECTED_EN_BIT_POS          2
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b04895d91adc..1c4aad0cca49 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1696
+#define __WMI_REVISION_ 1697
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 53e6c70140b9f47652ccf3475b7665fa061a950d Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 14 Jan 2026 12:02:06 -0800
Subject: [PATCH 117/290] fw-api: CL 31386508 - update fw common interface
 files

Change-Id: Ic278e3696d2b09efc4c1cfd15b2f18008b658d67
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index d07b82a8f873..1a7af72fae24 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -50165,6 +50165,8 @@ typedef enum {
     WMI_MAP_SWITCH_TIMER_EXPIRED,
     /* Expected Duration Expired */
     WMI_EXPECTED_DUR_EXPIRED,
+    /* Expected Duration Near to Expiry */
+    WMI_EXPECTED_DUR_NEAR_TO_EXPIRY,
 } WMI_MLO_TID_TO_LINK_MAP_STATUS;
 
 #define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1c4aad0cca49..bdd112fad6a1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1697
+#define __WMI_REVISION_ 1698
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f2ba7465e697540256d40eeeaeaaa59d6ccc1a39 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 14 Jan 2026 12:03:52 -0800
Subject: [PATCH 118/290] fw-api: CL 31390056 - update fw common interface
 files

Change-Id: I2c589f3e4a99cf930bdc090b9dfdfe0fabbaa112
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  21 +++++++
 fw/wmi_unified.h  | 155 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 177 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 28cb810c2b1d..9ee30a751ee5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1563,6 +1563,10 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_config,
     WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_info,
+    WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_power_stats_info,
+    WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2153,6 +2157,7 @@ typedef enum {
     OP(WMI_IPA_RING_STATS_REQ_CMDID) \
     OP(WMI_VDEV_UHR_CU_CMDID) \
     OP(WMI_PDEV_UHR_CU_CMDID) \
+    OP(WMI_PDEV_POWER_DATAPATH_STATS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2504,6 +2509,7 @@ typedef enum {
     OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \
     OP(WMI_IPA_RING_STATS_CONF_EVENTID) \
     OP(WMI_PDEV_UHR_CU_EVENTID) \
+    OP(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5020,6 +5026,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID);
 
+/*
+ * WMI command for setting the pdev power stats enable/disable
+ * and getting the pdev power stats
+ */
+#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_CMDID(id,op,buf,len) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param, wmi_pdev_power_datapath_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_CMDID);
+
 /* WLAN GET mws conflict */
 #define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_INFO_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_info_cmd_fixed_param, wmi_vdev_get_mws_coex_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -7540,6 +7554,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_STATS_EVENTID);
 
+/* WMI event to provide pdev power stats */
+#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_EVENTID(id,op,buf,len) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param, wmi_pdev_power_datapath_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_power_stats_info, power_stats, WMITLV_SIZE_VAR) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_tx_rate_info, tx_rate_stats, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID);
+
 #define WMITLV_TABLE_WMI_VDEV_BCN_RECEPTION_STATS_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_recv_stats_event_fixed_param, wmi_vdev_bcn_recv_stats_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_RECEPTION_STATS_EVENTID);
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 1a7af72fae24..188e99947010 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -623,6 +623,8 @@ typedef enum {
      * that are applicable for critical update.
      */
     WMI_PDEV_UHR_CU_CMDID,
+    /** WMI cmd used to enable/disable and get power and data path stats */
+    WMI_PDEV_POWER_DATAPATH_STATS_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -2023,6 +2025,11 @@ typedef enum {
     /* WMI event for the UHR critical Update */
     WMI_PDEV_UHR_CU_EVENTID, /* 53 */
 
+    /**
+     * WMI Event to send power and data path stats info to Host
+     */
+    WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */
+
 
 
     /***
@@ -37266,6 +37273,39 @@ typedef struct {
     A_UINT32 pdev_id;
 } wmi_pdev_get_chip_power_stats_cmd_fixed_param;
 
+
+typedef enum {
+    /* Enable the stats by default*/
+   WMI_PDEV_POWER_DATAPATH_STATS_OP_DISABLE = 0,
+   WMI_PDEV_POWER_DATAPATH_STATS_OP_ENBLE = 1,
+   WMI_PDEV_POWER_DATAPATH_STATS_OP_RETRIEVE = 2,
+   WMI_PDEV_POWER_DATAPATH_STATS_OP_MAX,
+} WMI_PDEV_POWER_DATAPATH_STATS_OPERATION;
+
+typedef enum {
+   WMI_PDEV_POWER_STATS_TYPE = 0x00000001,
+   WMI_PDEV_DATAPATH_STATS_TYPE = 0x00000002,
+   WMI_PDEV_POWER_DATAPATH_STATS_ALL = 0x00000003,
+   WMI_PDEV_STATS_TYPE_MAX,
+} WMI_PDEV_POWER_DATAPATH_STATS_TYPE;
+
+/* WMI command to enable/disable or get the power/datapath stats */
+typedef struct {
+   A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param */
+
+   /** pdev_id for identifying the MAC
+    * See macros starting with WMI_PDEV_ID_ for values.
+    */
+   A_UINT32 core_index;
+
+   /** Operation type - distinguishes between enable/disable/retrieve */
+   A_UINT32 operation;  /* wmi_pdev_power_datapath_stats_operation */
+
+   /** Stats type bitmap - specifies which stats to enable/disable/retrieve */
+   A_UINT32 stats_type_bitmap; /* wmi_pdev_power_datapath_stats_type */
+} wmi_pdev_power_datapath_stats_cmd_fixed_param;
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_bcn_recv_stats_cmd_fixed_param */
     /** VDEV identifier */
@@ -37426,6 +37466,120 @@ typedef struct {
      */
 } wmi_pdev_chip_power_stats_event_fixed_param;
 
+
+typedef enum {
+    WMI_PDEV_RATE_CCK_1M,
+    WMI_PDEV_RATE_CCK_2M,
+    WMI_PDEV_RATE_CCK_5M, /* CCK 5.5Mbps */
+    WMI_PDEV_RATE_CCK_11M,
+    WMI_PDEV_RATE_OFDM_6M,
+    WMI_PDEV_RATE_OFDM_9M,
+    WMI_PDEV_RATE_OFDM_12M,
+    WMI_PDEV_RATE_OFDM_18M,
+    WMI_PDEV_RATE_OFDM_24M,
+    WMI_PDEV_RATE_OFDM_36M,
+    WMI_PDEV_RATE_OFDM_48M,
+    WMI_PDEV_RATE_OFDM_54M,
+    WMI_PDEV_RATE_MCS0, /* includes HT MCS 0 (1ss)/8 (2ss)/16 (3ss)/24 (4ss), VHT/HE MCS 0 */
+    WMI_PDEV_RATE_MCS1, /* includes HT MCS 1 (1ss)/9 (2ss)/17 (3ss)/25 (4ss), VHT/HE MCS 1 */
+    WMI_PDEV_RATE_MCS2, /* includes HT MCS 2 (1ss)/10 (2ss)/18 (3ss)/26 (4ss), VHT/HE MCS 2 */
+    WMI_PDEV_RATE_MCS3, /* includes HT MCS 3 (1ss)/11 (2ss)/19 (3ss)/27 (4ss), VHT/HE MCS 3 */
+    WMI_PDEV_RATE_MCS4, /* includes HT MCS 4 (1ss)/12 (2ss)/20 (3ss)/28 (4ss), VHT/HE MCS 4 */
+    WMI_PDEV_RATE_MCS5, /* includes HT MCS 5 (1ss)/13 (2ss)/21 (3ss)/29 (4ss), VHT/HE MCS 5 */
+    WMI_PDEV_RATE_MCS6, /* includes HT MCS 6 (1ss)/14 (2ss)/22 (3ss)/30 (4ss), VHT/HE MCS 6 */
+    WMI_PDEV_RATE_MCS7, /* includes HT MCS 7 (1ss)/15 (2ss)/23 (3ss)/31 (4ss), VHT/HE MCS 7 */
+    WMI_PDEV_RATE_MCS8, /* includes VHT/HE MCS 8 */
+    WMI_PDEV_RATE_MCS9, /* includes VHT/HE MCS 9 */
+    WMI_PDEV_RATE_MCS10, /* includes VHT/HE MCS 10 */
+    WMI_PDEV_RATE_MCS11, /* includes VHT/HE MCS 11 */
+    WMI_PDEV_RATE_MCS12, /* includes BE MCS 12 */
+    WMI_PDEV_RATE_MCS13, /* includes BE MCS 13 */
+    WMI_PDEV_RATE_RATE_IDX_MAX,
+} WMI_PDEV_RATE_IDX;
+
+#define WMI_MAX_SLEEP_LEVELS 5
+
+typedef struct {
+    A_UINT32 tlv_header;/* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info */
+
+   /** Common element - core_index (PDEV ID) */
+    A_UINT32 core_index;
+
+    /* An index representing a specific transmit data rate */
+    A_UINT32 rate_index;
+
+    /*
+     * The operating band of the transmit rate.
+     * 0: 2.4 GHz, 1: 5 GHz, 2: 6 GHz
+     */
+    A_UINT32 band;
+
+    /*
+     * The bandwidth of the transmit rate.
+     * 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 MHz, 4: 320 MHz
+     */
+    A_UINT32 bw;
+
+    /*
+     * The number of spatial streams (NSS) used for this transmit rate.
+     * 0: NSS1, 1: NSS2, 2: NSS3, 3: NSS4, 4: NSS5
+     */
+    A_UINT32 nss;
+
+    /*
+     * The number of times a transmit occurred with this specific
+     * combination of rate index, band, bandwidth, and NSS
+     */
+    A_UINT32 count;
+    A_UINT32 tx_retry_count; /* accumulated over time */
+} wmi_pdev_tx_rate_info;
+
+/* Power stats in event payload*/
+typedef struct {
+   /** Power Statistics */
+   A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_stats_info */
+
+   /** Common element - core_index (PDEV ID) */
+   A_UINT32 core_index;
+
+   A_UINT32 radio_on_time;    /* Time radio was on (ms) */
+   A_UINT32 radio_off_time;   /* Time radio was off (ms) */
+   A_UINT32 wlan_pwr_on_time; /* WLAN power on time (ms) */
+   /* tx_time:
+    * ms duration the radio is in a continuous transmit state
+    * encompassing all packet types (management, data, action frames)
+    */
+   A_UINT32 tx_time;
+   /* rx_time:
+    * ms duration the radio is in a continuous receiving data state
+    * Including all Rx packets instead of only collecting for my BSS data
+    */
+   A_UINT32 rx_time;
+
+   /* Number of sleep levels being sent to the host */
+   A_UINT32 sleep_levels_num;
+   A_UINT32 sleep_time_per_levels[WMI_MAX_SLEEP_LEVELS]; /* ms */
+} wmi_pdev_power_stats_info;
+
+typedef struct {
+   A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param */
+
+   /** Status of the operation */
+   A_UINT32 status; /* 0 = success, non-zero = error */
+
+   /** Stats type bitmap indicating which stats are included */
+   A_UINT32 stats_type_bitmap;
+
+   /*
+    * Following this structure are the TLVs:
+    *     wmi_pdev_power_stats_info[num_cores];
+    *     wmi_pdev_tx_rate_info[num_tx_rate_info]
+    * where num_cores and num_tx_rate_info are determined from the TLV array
+    * (i.e. array size / array element size)
+    */
+} wmi_pdev_power_datapath_stats_event_fixed_param;
+
+
 typedef struct {
     A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param */
     A_UINT32 vdev_id;
@@ -40932,6 +41086,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_ROAM_SMD_START_STATUS_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID);
         WMI_RETURN_STRING(WMI_IPA_RING_STATS_REQ_CMDID);
+        WMI_RETURN_STRING(WMI_PDEV_POWER_DATAPATH_STATS_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index bdd112fad6a1..f49b955a18f5 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1698
+#define __WMI_REVISION_ 1699
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 21261b977ace8ab77323a610b0ccc0b0e8a93cc0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 15 Jan 2026 12:02:22 -0800
Subject: [PATCH 119/290] fw-api: CL 31397472 - update fw common interface
 files

Change-Id: I5e865c268d7723ea33d896a4364fe1f3bd20ffc4
CRs-Fixed: 3830439
---
 fw/htt.h | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index 16e6134a8e61..807bcf009f86 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -277,9 +277,10 @@
  * 3.147 Add direct_refill flag in SRING_SETUP msg.
  * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def.
  * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO.
+ * 3.150 Add htt_reg_write_selection definitions.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 149
+#define HTT_CURRENT_VERSION_MINOR 150
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -6263,6 +6264,30 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
     A_UINT32 rdi_based_source_cfg;
 } POSTPACK;
 
+/**
+ * Enumeration for Reg Write block index selection
+ * Each Enum position corresponds to respective
+ * UMAC_UMCMN_R0_REG_ADDR_LSB_IX_n
+ * UMAC_UMCMN_R0_REG_ADDR_MSB_IX_n
+ * UMAC_UMCMN_R2_REG_VALUE_IX_n
+ *
+ * Any value written to the value register will be copied by
+ * Reg Writer Block to Address written in Reg Address Register.
+ *
+ * NOTE: Only value Registers defined in the enum should be used by the Host.
+ * Rest are unconfigured, and if used may result in invalid memory access
+ */
+enum htt_reg_write_selection {
+    HTT_REG_WRITER_RXMON_SW2MON_BUF_RING,
+    HTT_REG_WRITER_TXMON_SW2MON_BUF_RING,
+    HTT_REG_WRITER_RXMON_M0_MON2SW_DEST_RING,
+    HTT_REG_WRITER_RXMON_M1_MON2SW_DEST_RING,
+    HTT_REG_WRITER_TXMON_M0_MON2SW_DEST_RING,
+    HTT_REG_WRITER_TXMON_M1_MON2SW_DEST_RING,
+    HTT_REG_WRITER_RXOLE2SW_ASE_DEST_RING,
+};
+
+
 #define HTT_RX_RING_SELECTION_CFG_SZ    (sizeof(struct htt_rx_ring_selection_cfg_t))
 
 #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M                    0x0000ff00

From 2910712e9e9b846cf4339bb72c89c3a2832efea1 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 15 Jan 2026 12:04:28 -0800
Subject: [PATCH 120/290] fw-api: CL 31399985 - update fw common interface
 files

Change-Id: I5abc99a1656415e69eac339bfa2e13acddc16809
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 5 +++++
 fw/wmi_version.h | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 188e99947010..8a08d0ff98a5 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -4034,6 +4034,11 @@ typedef struct {
      */
     A_UINT32 supported_wifi_certified_generations;
 
+    /*
+     * max number of CFR filter groups supported by FW.
+     */
+    A_UINT32 max_cfr_filter_groups_supp;
+
     /* Followed by next TLVs:
      *     WMI_DMA_RING_CAPABILITIES          dma_ring_caps[];
      *     wmi_spectral_bin_scaling_params    wmi_bin_scaling_params[];
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f49b955a18f5..c88a7063f569 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1699
+#define __WMI_REVISION_ 1700
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 2044eb5632b53e9e68a67229879c59c978c94ab5 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 16 Jan 2026 12:05:18 -0800
Subject: [PATCH 121/290] fw-api: CL 31404904 - update fw common interface
 files

Change-Id: I368177a34713c2e21c07f844d68f3b0d69dac6a4
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   6 ++
 fw/wmi_tlv_defs.h | 150 +++++++++++++++++++++++++++++++---
 fw/wmi_unified.h  | 199 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 4 files changed, 344 insertions(+), 13 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index f7e458b2c14a..59d421607c6c 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -751,6 +751,12 @@ typedef  enum  {
     WMI_SERVICE_P2P_CANCEL_ONE_SHOT_NOA_SUPPORT = 487, /* Indicates FW support for P2P GO/GC cancel one-shot NOA feature */
     WMI_SERVICE_SMD_BSS_TRANSITION_SUPPORT = 488, /* Indicates FW supports S(eamless)M(obility)D(omain) BSS transition */
 
+    /* Service caps related to SMD Roaming - start */
+    WMI_SERVICE_SMD_SUPPORT_ROAMING = 489,
+    WMI_SERVICE_SMD_SUPPORT_DL_FORWARD = 490,
+    WMI_SERVICE_SMD_SUPPORT_UL_FORWARD = 491,
+    /* Service caps related to SMD Roaming - end */
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 9ee30a751ee5..13f000568137 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1567,6 +1567,12 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_power_stats_info,
     WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info,
+    WMITLV_TAG_STRUC_wmi_vdev_start_smd_params,
+    WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2158,6 +2164,8 @@ typedef enum {
     OP(WMI_VDEV_UHR_CU_CMDID) \
     OP(WMI_PDEV_UHR_CU_CMDID) \
     OP(WMI_PDEV_POWER_DATAPATH_STATS_CMDID) \
+    OP(WMI_SMD_ROAM_CONFIG_CMDID) \
+    OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2510,6 +2518,8 @@ typedef enum {
     OP(WMI_IPA_RING_STATS_CONF_EVENTID) \
     OP(WMI_PDEV_UHR_CU_EVENTID) \
     OP(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID) \
+    OP(WMI_SMD_ROAM_CONFIG_EVENTID) \
+    OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -2531,8 +2541,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, mlo_params, WMITLV_SIZE_VAR)
 /* NOTE:
- * Any new TLV addition in WMI_PEER_CREATE_CMDID needs to be included as
- * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ * To maintain compatibility, any new TLV addition in WMI_PEER_CREATE_CMDID
+ * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID.
  *
  * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
  * cmds:
@@ -2541,6 +2552,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID);
  *     WMI_PEER_ASSOC_CMDID,
  *     WMI_PEER_ASSOC_V2_CMDID,
  *     WMI_VDEV_UP_CMDID
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_INSTALL_KEY
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID);
 
@@ -2914,7 +2931,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params,  WMITLV_SIZE_VAR)
 /* NOTE:
  * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
@@ -3005,7 +3023,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FD_TMPL_CMDID);
 #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR)
-
+/* NOTE:
+ * To maintain compatibility, any new TLV added in WMI_VDEV_INSTALL_KEY_CMDID
+ * needs to be included as a TLV in WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID too.
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_INSTALL_KEY
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID);
 
 /* VDEV set LTF key seed Cmd */
@@ -3073,8 +3100,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
 /* NOTE:
- * Any new TLV addition in WMI_PEER_ASSOC_V2_CMDID needs to be included as
- * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
+ * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID
+ * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID.
  *
  * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related
  * cmds:
@@ -3083,6 +3111,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
  *     WMI_PEER_ASSOC_CMDID,
  *     WMI_PEER_ASSOC_V2_CMDID,
  *     WMI_VDEV_UP_CMDID
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related
+ * cmds:
+ *     WMI_PEER_CREATE_CMDID,
+ *     WMI_PEER_ASSOC_CMDID,
+ *     WMI_PEER_ASSOC_V2_CMDID,
+ *     WMI_VDEV_INSTALL_KEY
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
 
@@ -6160,8 +6194,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
  \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
-
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
 /* WMI command for unified disconnect cmd */
@@ -6209,6 +6244,57 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
 
+/* WMI command for unified SMD PEER SETUP cmd */
+#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param, wmi_smd_roam_peer_unified_setup_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, key_install_fixed_param, WMITLV_SIZE_FIX)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
+
+/* WMI command for unified SMD Config cmd */
+#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param, wmi_smd_roam_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID);
+
+
 
 /************************** TLV definitions of WMI events *******************************/
 
@@ -6490,6 +6576,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_RESP_EVENTID);
 /* VDEV Install Key Complete Event */
 #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+/* NOTE:
+ * To maintain compatibility, any new TLV added in
+ * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID needs to also be included as a TLV in
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID.
+ *
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for
+ * 3 connection related events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID,
+ *     WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID);
 
 /* VDEV disconnect Event */
@@ -7288,14 +7385,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID);
 #define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 /* NOTE:
- * Any new TLV addition in WMI_PEER_ASSOC_CONF_EVENTID needs to be included
- * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility.
+ * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_CONF_EVENTID
+ * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID.
  *
  * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related
  * events:
  *     WMI_PEER_CREATE_CONF_EVENTID,
  *     WMI_VDEV_START_RESP_EVENTID,
  *     WMI_PEER_ASSOC_CONF_EVENTID
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for
+ * 3 connection related events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID,
+ *     WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID);
 
@@ -7303,14 +7406,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID);
 #define WMITLV_TABLE_WMI_PEER_CREATE_CONF_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 /* NOTE:
- * Any new TLV addition in WMI_PEER_CREATE_CONF_EVENTID needs to be included
- * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility.
+ * To maintain compatibility, any new TLV added in WMI_PEER_CREATE_CONF_EVENTID
+ * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID.
  *
  * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related
  * events:
  *     WMI_PEER_CREATE_CONF_EVENTID,
  *     WMI_VDEV_START_RESP_EVENTID,
  *     WMI_PEER_ASSOC_CONF_EVENTID
+ * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for
+ * 3 connection related events:
+ *     WMI_PEER_CREATE_CONF_EVENTID,
+ *     WMI_PEER_ASSOC_CONF_EVENTID,
+ *     WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CONF_EVENTID);
 
@@ -8491,6 +8600,23 @@ WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_CONF_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_uhr_cu_status, cu_status, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_EVENTID);
 
+/* WMI unified SMD PEER SETUP event */
+#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_conf_fixed_param, WMITLV_SIZE_FIX) \
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_conf_fixed_param, WMITLV_SIZE_FIX)\
+    /*---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, vdev_install_key_complete_fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID);
+
+/* WMI unified SMD Config event */
+#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, wmi_smd_roam_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_EVENTID);
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8a08d0ff98a5..9afe991a4661 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -373,6 +373,7 @@ typedef enum {
     WMI_GRP_TDMA,           /* 0x4c TDMA */
     WMI_GRP_MANUAL_UL_TRIG, /* 0x4d Manual UL OFDMA Trigger */
     WMI_GRP_ENERGY_MGMT,    /* 0x4e energy management */
+    WMI_GRP_SMD,            /* 0x4f SMD Roaming */
 } WMI_GRP_ID;
 
 #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -1814,6 +1815,14 @@ typedef enum {
     WMI_ENERGY_MGMT_PUO_CONFIG_CMDID,
     /** WMI cmd used to control ECO mode config */
     WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID,
+
+    /** WMI cmd used to set the SMD Roam config */
+    WMI_SMD_ROAM_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SMD),
+    /**
+     * WMI cmd used to set up the peer on the target AP during Prep Phase
+     * (Combine PeerCreate,Assoc, Key Install)
+     */
+    WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID,
 } WMI_CMD_ID;
 
 typedef enum {
@@ -2778,6 +2787,14 @@ typedef enum {
      * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host
      */
     WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID,
+
+    /* WMI event used during SMD Roaming */
+    WMI_SMD_ROAM_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SMD),
+    /*
+     * WMI event to indicate the status of the SMD_ROAM_PEER_UNIFIED_SETUP_CMD
+     * used during SMD Roaming
+     */
+    WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID,
 } WMI_EVT_ID;
 
 /* defines for OEM message sub-types */
@@ -7961,6 +7978,9 @@ typedef struct {
 #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV 0x00000008
 #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_GET(tx_flags) WMI_GET_BITS(tx_flags, 3, 1)
 #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 3, 1, value)
+#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME 0x00000010
+#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_GET(tx_flags) WMI_GET_BITS(tx_flags, 4, 1)
+#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 4, 1, value)
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_send_params */
@@ -17586,6 +17606,33 @@ typedef struct {
 
 #define WMI_SCAN_MODE_VDEV_FLAG_ENABLED(flag)        ((flag & VDEV_FLAGS_SCAN_MODE_VAP) ? 1 : 0)
 
+
+#define WMI_VDEV_START_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags)              WMI_GET_BITS(mlo_flags, 0, 1)
+#define WMI_VDEV_START_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value)       WMI_SET_BITS(mlo_flags, 0, 1, value)
+#define WMI_VDEV_START_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags)        WMI_GET_BITS(mlo_flags, 1, 1)
+#define WMI_VDEV_START_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value)
+#define WMI_VDEV_START_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags)        WMI_GET_BITS(mlo_flags, 2, 1)
+#define WMI_VDEV_START_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value)
+#define WMI_VDEV_START_SMD_FLAGS_GET_PTK_MODE(mlo_flags)                  WMI_GET_BITS(mlo_flags, 3, 1)
+#define WMI_VDEV_START_SMD_FLAGS_SET_PTK_MODE(mlo_flags, value)           WMI_SET_BITS(mlo_flags, 3, 1, value)
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_smd_params*/
+    /** MLD MAC address */
+    wmi_mac_addr smd_macaddr;
+    union {
+        struct {
+            A_UINT32 roam_enabled       :1,
+                     dl_data_forwarding :1,
+                     ul_data_forwarding :1,
+                     ptk_mode           :1,
+                     reserved           :28;
+        };
+        A_UINT32 smd_flags;
+    };
+} wmi_vdev_start_smd_params;
+
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
@@ -18653,6 +18700,7 @@ typedef struct {
  *         optional TLV for dbw_chan
  *     wmi_dbw_chan_info dbw_chan_info
  *         optional TLV used for dbw_chan_info
+ *     wmi_vdev_start_smd_params smd_params;
  */
 } wmi_vdev_start_request_cmd_fixed_param;
 
@@ -22418,6 +22466,8 @@ typedef struct {
 #define WMI_PEER_EXT_PROTECTED_TWT      0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */
 #define WMI_PEER_EXT_UHR                0x00000080 /* UHR enabled */
 #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000
+#define WMI_PEER_EXT_SMD_ASSOC          0x80000000
+
 
 /**
  * Peer rate capabilities.
@@ -22736,6 +22786,13 @@ typedef struct {
     A_UINT32 cfp_padding_delay;
 } wmi_peer_assoc_cfp_params; /* cfp -> control frame protection */
 
+#define WMI_PEER_ASSOC_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags)              WMI_GET_BITS(mlo_flags, 0, 1)
+#define WMI_PEER_ASSOC_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value)       WMI_SET_BITS(mlo_flags, 0, 1, value)
+#define WMI_PEER_ASSOC_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags)        WMI_GET_BITS(mlo_flags, 1, 1)
+#define WMI_PEER_ASSOC_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value)
+#define WMI_PEER_ASSOC_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags)        WMI_GET_BITS(mlo_flags, 2, 1)
+#define WMI_PEER_ASSOC_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value)
+
 /* This TLV structure used to pass smd Parameters on peer assoc */
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params */
@@ -22743,6 +22800,15 @@ typedef struct {
     wmi_mac_addr smd_identifier;
     /** SMD capabilities defined in 802.11BN-SMD Information element */
     A_UINT32 smd_capabilities;
+    union {
+        struct {
+            A_UINT32 roam_enabled       :1,
+                     dl_data_forwarding :1,
+                     ul_data_forwarding :1,
+                     reserved           :29;
+        };
+        A_UINT32 smd_flags;
+    };
 } wmi_peer_assoc_smd_params;
 
 /*
@@ -22953,6 +23019,7 @@ typedef struct {
  *         If the peer is non-MLO, the array length should be 0.
  *         Only mlo_enable flag required by MCC to decide MAC address
  *         to be used.
+ *     wmi_peer_assoc_smd_params peer_assoc_smd_params;
  */
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
@@ -41092,6 +41159,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID);
         WMI_RETURN_STRING(WMI_IPA_RING_STATS_REQ_CMDID);
         WMI_RETURN_STRING(WMI_PDEV_POWER_DATAPATH_STATS_CMDID);
+        WMI_RETURN_STRING(WMI_SMD_ROAM_CONFIG_CMDID);
+        WMI_RETURN_STRING(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -53932,6 +54001,136 @@ typedef struct {
 } wmi_pdev_uhr_cu_event_fixed_param;
 
 
+typedef enum {
+    WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1,
+    WMI_SMD_ROAM_CONFIG_ROLE_TARGET_AP,
+    WMI_SMD_ROAM_CONFIG_ROLE_STA,
+} wmi_smd_roam_config_role;
+
+typedef enum {
+    WMI_SMD_ROAM_CONFIG_CMD_PREP_REQ = 1,
+    WMI_SMD_ROAM_CONFIG_CMD_PREP_RESP,
+    WMI_SMD_ROAM_CONFIG_CMD_EXEC_REQ,
+    WMI_SMD_ROAM_CONFIG_CMD_EXEC_RESP,
+    WMI_SMD_ROAM_CONFIG_CMD_DYNAMIC_CONTEXT,
+    WMI_SMD_ROAM_CONFIG_CMD_TERMINATION,
+} wmi_smd_roam_config_cmd_type;
+
+#define  WMI_SMD_ROAM_FLAG_DL_SN_NOT_TRANSFFERED 0x01
+#define  WMI_SMD_ROAM_FLAG_UL_SN_NOT_TRANSFFERED 0x02
+#define  WMI_SMD_ROAM_FLAG_DISABLE_LINK          0x04
+
+#define WMI_SMD_ROAM_PEER_GET_MLSN(dword) \
+        WMI_GET_BITS(dword, 0, 16)
+#define WMI_SMD_ROAM_PEER_SET_MLSN(dword, value) \
+        WMI_SET_BITS(dword, 0, 16, value)
+
+#define WMI_SMD_ROAM_PEER_GET_OFFSET(dword) \
+        WMI_GET_BITS(dword, 16, 16)
+#define WMI_SMD_ROAM_PEER_SET_OFFSET(dword, value) \
+        WMI_SET_BITS(dword, 16, 16, value)
+
+typedef struct {
+    A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info */
+    A_UINT32 tid_num;
+    union {
+        A_UINT32 mlsn__offset__word32;
+        struct {
+            A_UINT32 mlsn: 16,
+                     offset: 16;
+        };
+    };
+} wmi_smd_roam_peer_tid_info;
+
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROLE(cmd_flags)                      WMI_GET_BITS(mlo_flags, 0, 4)
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROLE(cmd_flags, value)               WMI_SET_BITS(mlo_flags, 0, 4, value)
+
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_CMD_TYPE(cmd_flags)                  WMI_GET_BITS(mlo_flags, 4, 8)
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_CMD_TYPE(cmd_flags, value)           WMI_SET_BITS(mlo_flags, 4, 8, value)
+
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_STATUS(cmd_flags)                    WMI_GET_BITS(mlo_flags, 12, 8)
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_STATUS(cmd_flags, value)             WMI_SET_BITS(mlo_flags, 12, 8, value)
+
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROAM_FLAGS(cmd_flags)                WMI_GET_BITS(mlo_flags, 20, 8)
+#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROAM_FLAGS(cmd_flags, value)         WMI_SET_BITS(mlo_flags, 20, 8, value)
+
+typedef enum {
+    WMI_SMD_ROAM_CONFIG_CMD_SUCCESS = 0,
+    WMI_SMD_ROAM_CONFIG_CMD_FAILURE,
+} wmi_smd_roam_config_cmd_status;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param */
+    /** global unique ID identifying vdev */
+    A_UINT32 vdev_id;
+    /** PEER MAC address */
+    wmi_mac_addr peer_mac_addr;
+    union {
+        A_UINT32 cmd_flags;
+        struct {
+            A_UINT32 role       :4, /* wmi_smd_config_role */
+                     cmd_type   :8, /* wmi_smd_config_cmd_type */
+                     status     :8, /* wmi_smd_roam_config_cmd_status */
+                     roam_flags :8, /* WMI_SMD_ROAM_FLAG_* */
+                     reserved   :4;
+        };
+    };
+    A_UINT32 dl_drain_time; /* units = milliseconds */
+    /*
+     * Followed by per tid tlv wmi_smd_roam_peer_tid_info[].
+     * Present when dynamic context is set.
+     */
+} wmi_smd_roam_config_cmd_fixed_param;
+
+#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_ROLE(event_flags)            WMI_GET_BITS(mlo_flags, 0, 4)
+#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_ROLE(event_flags, value)     WMI_SET_BITS(mlo_flags, 0, 4, value)
+
+#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_CMD_TYPE(event_flags)        WMI_GET_BITS(mlo_flags, 4, 8)
+#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_CMD_TYPE(event_flags, value) WMI_SET_BITS(mlo_flags, 4, 8, value)
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; */
+    /** global unique ID identifying vdev */
+    A_UINT32 vdev_id;
+    /** PEER MAC address */
+    wmi_mac_addr peer_mac_address;
+    /* maximum ST Transitory Duration */
+    A_UINT32 dl_drain_time; /* units = milliseconds */
+    union {
+        A_UINT32 event_flags;
+        struct {
+            A_UINT32 role:4,
+                     cmd_type:8,
+                     unused:20;
+        };
+    };
+} wmi_smd_roam_config_event_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param */
+
+    /** global unique ID identifying peer */
+    A_UINT32 peer_id;
+    /*
+     * Following this struct are the TLV's:
+     *     wmi_smd_roam_peer_tid_info smd_tid_info[], TLV per TID;
+     */
+} wmi_smd_roam_peer_unified_setup_cmd_fixed_param;
+
+typedef enum {
+    WMI_SMD_PEER_SETUP_SUCCESS = 0,
+    WMI_SMD_PEER_SETUP_FAILURE,
+} wmi_smd_peer_setup_status_type;
+
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** global unique ID identifying peer */
+    A_UINT32 peer_id;
+    A_UINT32 status; /** wmi_smd_peer_setup_status_type */
+} wmi_smd_roam_peer_unified_setup_complete_event_fixed_param;
+
+
 
 /* ADD NEW DEFS HERE */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c88a7063f569..0bd9b2d0d6f2 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1700
+#define __WMI_REVISION_ 1701
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f70ce95a71d93754a6bfb90af4ffb17723739c87 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 17 Jan 2026 12:02:10 -0800
Subject: [PATCH 122/290] fw-api: CL 31412194 - update fw common interface
 files

Change-Id: I2380834eec68b3f416411acce7d9d366eac85dbe
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index cd62325cd86f..f97316aa98d4 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1351,18 +1351,6 @@ typedef struct {
     A_UINT32 hw_reaped_sp;
     /** Number of hardware reaped (Tx completed) packets in VLP mode */
     A_UINT32 hw_reaped_vlp;
-    /** num_combined_sched_cmds_success_per_ac:
-     * Total number of successfully transmitted combined sched_cmd
-     * sequences per AC
-     */
-    A_UINT32 num_combined_sched_cmds_success_per_ac[HTT_NUM_AC_WMM];
-    /** Total number of failed combined sched_cmd sequences per AC */
-    A_UINT32 num_combined_sched_cmds_failed_per_ac[HTT_NUM_AC_WMM];
-    /** num_aborted_comb_sched_cmds_per_ac:
-     * Total number of aborted sched_cmds by scheduler before posting
-     * to TAC per AC
-     */
-    A_UINT32 num_aborted_comb_sched_cmds_per_ac[HTT_NUM_AC_WMM];
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;

From 77230395069bfc4b31bc4086ebb6ac8d7b7e3778 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 18 Jan 2026 12:02:02 -0800
Subject: [PATCH 123/290] fw-api: CL 31413468 - update fw common interface
 files

Change-Id: Icaae39d21c33c2c460b17afaef4c634f0d5f77bd
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 43 +++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9afe991a4661..0441933f8755 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3870,6 +3870,22 @@ typedef enum {
 #define WMI_SUPPORTED_WIFI_8_CERTIFIED_GENERATION_SET(wifi_generations, value) \
         WMI_SET_BITS(wifi_generations, 4, 1, value)
 
+/* Begin SAM related capabilities */
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_GET(sam_capability_1) \
+    WMI_GET_BITS(sam_capability_1, 0, 12)
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_SET(sam_capability_1, value) \
+    WMI_SET_BITS(sam_capability_1, 0, 12, value)
+
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_GET(sam_capability_1) \
+    WMI_GET_BITS(sam_capability_1, 12, 13)
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_SET(sam_capability_1, value) \
+    WMI_SET_BITS(sam_capability_1, 12, 13, value)
+
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_GET(sam_capability_2) \
+    WMI_GET_BITS(sam_capability_2, 0, 12)
+#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_SET(sam_capability_2, value) \
+    WMI_SET_BITS(sam_capability_2, 0, 12, value)
+/* End SAM related capabilities */
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/
@@ -4056,6 +4072,33 @@ typedef struct {
      */
     A_UINT32 max_cfr_filter_groups_supp;
 
+    /*
+     * The maximum number of supported SAM Peer/MSDUQ/MPDUQ elements. This does
+     * NOT indicate the support limits for the HW, but rather the FW limit.
+     * Some FW targets may not support the maximum HW capability.
+     *
+     * When the host allocates the associated SAM data structure, it should do
+     * so with IDs strictly less than the limit indicated below. For example if
+     * only 64 SAM Peers are supported by a target, then only SAM Peer IDs 0-63
+     * should be utilized.
+     *
+     * If a target does not support utilizing SAM, all of these SAM
+     * configuration values will be 0.
+     */
+    union {
+        struct {
+            A_UINT32 num_supported_sam_peer  : 12; /* bits  0:11 */
+            A_UINT32 num_supported_sam_msduq : 13; /* bits 12:24 */
+            A_UINT32 sam_reserved_1          :  7; /* bits 25:31 */
+            A_UINT32 num_supported_sam_mpduq : 12; /* bits  0:11 */
+            A_UINT32 sam_reserved_2          : 20; /* bits 12:31 */
+        };
+        struct {
+            A_UINT32 sam_capability_1;
+            A_UINT32 sam_capability_2;
+        };
+    };
+
     /* Followed by next TLVs:
      *     WMI_DMA_RING_CAPABILITIES          dma_ring_caps[];
      *     wmi_spectral_bin_scaling_params    wmi_bin_scaling_params[];
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0bd9b2d0d6f2..d9e5b35688a7 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1701
+#define __WMI_REVISION_ 1702
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 01534f76da1ff8c445d3fb59abb518eb763fa8f7 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 20 Jan 2026 12:02:41 -0800
Subject: [PATCH 124/290] fw-api: CL 31424696 - update fw common interface
 files

Change-Id: Ic35a9126657d19a8598ae9e48963f81e4cc8378c
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 10 +++++-----
 fw/wmi_version.h |  2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 0441933f8755..afca6a51b319 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -15892,6 +15892,11 @@ typedef struct {
      * (end of packet)
      */
     A_UINT32 rx_other_11ax_msdu_cnt;
+    /* pending_mpdu_msdus:
+     * count of the pending MPDUs + MSDUs for all TIDs within all peers
+     * for all the vdev under the specified pdev
+     */
+    A_UINT32 pending_mpdu_msdus;
 } wmi_pdev_extd_stats;
 
 /**
@@ -16056,11 +16061,6 @@ typedef struct {
      * Includes rx_time but not tx_time.
      */
     A_UINT32 cca_time;
-    /* pending_mpdu_msdus:
-     * count of the pending mpdu + msdus for all tids within all peers
-     * for the specified vdev
-     */
-    A_UINT32 pending_mpdu_msdus;
 } wmi_vdev_extd_stats;
 
 /**
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d9e5b35688a7..6b23e472d51d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1702
+#define __WMI_REVISION_ 1703
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 5dd2f1cb9de4bb09afb2ff49a0ca638c44aabe4e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 21 Jan 2026 12:04:34 -0800
Subject: [PATCH 125/290] fw-api: CL 31436976 - update fw common interface
 files

Change-Id: I7b14a339e17ec1c9e6f8e9ca13fbe39451670edd
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 16 ++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index afca6a51b319..9954bd0ece9d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -20136,6 +20136,20 @@ typedef enum {
     /* Use BTWT ID0 for this vdev */
     WMI_VDEV_PARAM_USE_BTWT_ID0,                          /* 0xD0 */
 
+    /*
+     * Enable or disable UHR ELR capability in Auto rate and
+     * Fixed rate UHR data packet transmissions.
+     * Enable or disable Enhanced Long range
+     * valid values: 0 - Disable ELR, 1 - Enable ELR.
+     */
+    WMI_VDEV_PARAM_UHR_ELR,                               /* 0xD1 */
+
+    /*
+     * Enable or disable Non-data UHR Enhanced Long Range
+     * valid values: 0 - Disable ELR, 1 - Enable ELR.
+     */
+    WMI_VDEV_PARAM_NON_DATA_UHR_ELR,                      /* 0xD2 */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
@@ -41204,6 +41218,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_PDEV_POWER_DATAPATH_STATS_CMDID);
         WMI_RETURN_STRING(WMI_SMD_ROAM_CONFIG_CMDID);
         WMI_RETURN_STRING(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_UNIFIED_CONNECT_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 6b23e472d51d..ae04da8a3278 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1703
+#define __WMI_REVISION_ 1704
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3e4f626d3d9d38954c6e9786030aa260533eac69 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 21 Jan 2026 12:06:33 -0800
Subject: [PATCH 126/290] fw-api: CL 31440102 - update fw common interface
 files

Change-Id: I8e46362f9ad0fe60303f942069686bcd8816b34a
CRs-Fixed: 3830439
---
 fw/htt.h       |   5 +
 fw/htt_stats.h | 435 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 440 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 807bcf009f86..5bc71a8ace87 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -906,6 +906,11 @@ typedef enum {
     HTT_STATS_ANI_PER_BLK_ERR_TAG                   = 244, /* htt_stats_ani_per_blk_err_tlv */
     HTT_STATS_ANI_OTA_ERR_TAG                       = 245, /* htt_stats_ani_ota_err_tlv */
     HTT_STATS_RESET_HISTORY_TAG                     = 246, /* htt_stats_reset_history_tlv */
+    HTT_STATS_REGDB_CTRY_TAG                        = 247, /* htt_stats_regdb_ctry_tlv */
+    HTT_STATS_REGDB_REGDOMAIN_TAG                   = 248, /* htt_stats_regdb_regdomain_tlv */
+    HTT_STATS_REG_6G_TAG                            = 249, /* htt_stats_reg_6g_tlv*/
+    HTT_STATS_REG_6G_CH_PWR_INFO_TAG                = 250, /* htt_stats_reg_6g_ch_power_info_tlv*/
+    HTT_STATS_REG_6G_OOBE_TAG                       = 251, /* htt_stats_reg_6g_oobe_tlv*/
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index f97316aa98d4..34e0f0926773 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -898,6 +898,33 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_RESET_HISTORY = 82,
 
+    /** HTT_DBG_EXT_STATS_REGULATORY
+     * PARAMS:
+     *   - config_param0 : Regulatory stats subtype:
+     *                     htt_stats_regulatory_subtype_t
+     *   - config_param1 : (Depends on Subtype)
+     * RESP MSG:
+     *
+     * if (subtype == HTT_STATS_REGULATORY_SUBTYPE_REGDB):
+     *     config_param1 - Bitmap of Regdomains to include
+     *         [bit 0 - 2G,
+     *          bit 1 - 5G,
+     *          bit 2 - unused
+     *          bits 3-5 - 6G AP (LPI/SP/VLP)
+     *          bits 6-8 - 6G CLIENT 1 (LPI/SP/VLP)
+     *          bits 9-11- 6G CLIENT 2 (LPI/SP/VLP)]
+     *     RESP Tags:
+     *       - htt_stats_regdb_ctry_tlv
+     *       - htt_stats_regdb_regdomain_tlv * n (based on config_param1)
+     * else if(subtype == HTT_STATS_REGULATORY_SUBTYPE_6GHZ):
+     *     no params
+     *     RESP Tags:
+     *       - htt_stats_reg_6g_tlv
+     *       - htt_stats_reg_6g_ch_power_info_tlv * n
+     *       - htt_stats_reg_6g_oobe_tlv
+     */
+    HTT_DBG_EXT_STATS_REGULATORY = 83,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -12336,6 +12363,8 @@ typedef struct {
      * tx_power_neg[9]: cnt of PPDUs with tx pwr < -9 dBm
      */
     A_UINT32 tx_power_neg[HTT_MAX_NEGATIVE_POWER_LEVEL];
+    /* Tx Power computed for TPC IE for Beacon and related frames, in dBm */
+    A_UINT32 tpc_ie_power;
 } htt_stats_phy_tpc_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv;
@@ -15804,4 +15833,410 @@ typedef struct {
     ((word) |= (((value) << 0) & 0x00000001))
 
 
+/*===================== Start Regulatory stats ==================== { */
+
+typedef enum {
+    HTT_STATS_REGULATORY_SUBTYPE_REGDB = 0,
+    HTT_STATS_REGULATORY_SUBTYPE_6GHZ  = 1,
+    HTT_STATS_REGULATORY_SUBTYPE_MAX
+} htt_stats_regulatory_subtype_t;
+
+typedef struct {
+    htt_tlv_hdr_t   tlv_hdr;
+    union {
+        struct {
+            A_UINT32    major_version : 8,
+                        minor_version : 8,
+                        custom_version: 8,
+                        rsvd          : 8;
+        };
+        A_UINT32 regdb_version;
+    };
+    A_UINT32    country_code;
+    A_UINT32    alpha_code; /* [7:0]->alpha[0], [15:8]->alpha[1] and so on */
+    /* RegDomain and SuperDomain IDs are from Regdb */
+    A_UINT32    reg_domain_pair_id;
+    A_UINT32    super_domain_id;
+    A_UINT32    phymode_bitmap;     /* WMI_REGULATORY_PHYBITMAP */
+    A_UINT32    chan_priority_freq; /* in MHz */
+    A_UINT32    tpc_region;
+    A_UINT32    max_bw_2g;          /* in MHz */
+    A_UINT32    max_bw_5g;          /* in MHz */
+    A_UINT32    max_bw_6g;          /* in MHz */
+} htt_stats_regdb_ctry_tlv;
+
+#define HTT_STATS_GET_FIELD(mask,shift,word) (((word) & (mask)) >> (shift))
+#define HTT_STATS_SET_FIELD(mask,shift,word,value) \
+        (word) = (((word) & ~((mask))) | (((value) << (shift)) & (mask)))
+
+#define HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) \
+    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+#define HTT_STATS_REGDB_CTRY_SET_MAJOR_VERSION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) \
+    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+#define HTT_STATS_REGDB_CTRY_SET_MINOR_VERSION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+
+#define HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REGDB_CTRY_SET_CUSTOM_VERSION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REGDB_CTRY_GET_ALPHA_CODE_CHAR(word, idx) \
+    HTT_STATS_GET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word))
+#define HTT_STATS_REGDB_CTRY_SET_ALPHA_CODE_CHAR(word, idx, value) \
+    HTT_STATS_SET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word), (value))
+
+typedef struct {
+    union {
+        struct {
+            A_UINT32 start_freq : 16, /* in MHz */
+                     end_freq   : 16; /* in MHz */
+        };
+        A_UINT32 freq_info;
+    };
+    union {
+        struct {
+            A_UINT32 max_bw     : 16, /* in MHz */
+                     reg_power  : 8,  /* in dBm */
+                     ant_gain   : 8;  /* in dB */
+        };
+        A_UINT32 bw_pwr_info;
+    };
+    union {
+        struct {
+            A_UINT32 flags      : 16, /* enum WMI_REGULATORY_FLAGS */
+                     ctl_region : 8,  /* enum RegdbCtl */
+                     rsvd       : 8;
+        };
+        A_UINT32 flag_info;
+    };
+    union {
+        struct {
+            A_UINT32 is_psd     : 1,
+                     rsvd1      : 15,
+                     psd_power  : 16; /* dBm / MHz */
+        };
+        A_UINT32 psd_power_info;
+    };
+} htt_stats_regdb_reg_rule_t;
+
+#define HTT_STATS_REGDB_REG_RULE_GET_START_FREQ(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_START_FREQ(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_END_FREQ(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_END_FREQ(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_MAX_BW(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_MAX_BW(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_REG_POWER(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_REG_POWER(word, value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_ANT_GAIN(word) \
+    HTT_STATS_GET_FIELD(0xFF000000, 24, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_ANT_GAIN(word, value) \
+    HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_FLAGS(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_FLAGS(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_CTL_REGION(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_CTL_REGION(word, value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_IS_PSD(word) \
+    HTT_STATS_GET_FIELD(0x1, 0, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_IS_PSD(word, value) \
+    HTT_STATS_SET_FIELD(0x1, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REG_RULE_GET_PSD_POWER(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REGDB_REG_RULE_SET_PSD_POWER(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+typedef enum {
+    HTT_STATS_REGULATORY_REG_DMN_2G             = 0,
+    HTT_STATS_REGULATORY_REG_DMN_5G             = 1,
+    /* 2 is unused to allow octal grouping for 6G */
+    HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI      = 3,
+    HTT_STATS_REGULATORY_REG_DMN_6G_AP_SP       = 4,
+    HTT_STATS_REGULATORY_REG_DMN_6G_AP_VLP      = 5,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI     = 6,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL1_SP      = 7,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL1_VLP     = 8,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL2_LPI     = 9,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL2_SP      = 10,
+    HTT_STATS_REGULATORY_REG_DMN_6G_CL2_VLP     = 11,
+} htt_stats_regulatory_rd_type;
+
+#define HTT_STATS_REGULATORY_REG_DMN_6G_AP(power_mode) \
+    (HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI + (power_mode))
+#define HTT_STATS_REGULATORY_REG_DMN_6G_CL(cl,power_mode) \
+    (HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI +(cl)*3 + (power_mode))
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32      rd_type; /* enum htt_stats_regulatory_rd_type */
+    union {
+        struct {
+            A_UINT32 ctl_region : 8, /* enum RegdbCtl */
+                     cca_region : 8, /* enum CCA_REGION_MAP */
+                     dfs_region : 8, /* enum WMI_REG_DFS_REGION */
+                     rsvd       : 8;
+        };
+        A_UINT32 ctl_cca_dfs;
+    };
+    A_UINT32 rd_code; /* from regdb.bin */
+    /*
+     * Due to variable length array at end, this struture cannot be extended
+     * further. Hence use this reserved for any future parameters.
+     */
+    A_UINT32 reserved;
+    union {
+        struct {
+            A_UINT32 num_rules : 16, /* number of elements in 'rules' array */
+                     rule_size : 16; /* size of single 'rule' in bytes */
+        };
+        A_UINT32 rule_num_and_size;
+    };
+    htt_stats_regdb_reg_rule_t rules[1];
+} htt_stats_regdb_regdomain_tlv;
+
+#define HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) \
+    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_CTL_REGION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) \
+    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_CCA_REGION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+
+#define HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_DFS_REGION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_NUM_RULES(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_RULE_SIZE(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    union {
+        struct {
+            A_UINT32 afc_local_rsvd : 8,
+                     /* enum WMI_AFC_FEATURE_6G_DEPLOYMENT_TYPE */
+                     deployment_type: 8,
+                     /* Bit 0 : LPI, Bit 1 : SP, Bit 2 : VLP, others: rsvd */
+                     power_mode_mask: 8,
+                     reserved       : 8;
+        };
+        A_UINT32 afc_ini_params; /* AFC_INI_CONFIG */
+    };
+    A_UINT32 tx_allowed_reason_code;
+    union {
+        struct {
+            A_UINT32 set_tpc_count      : 16,
+                     set_tpc_pass_count : 16;
+        };
+        A_UINT32 set_tpc_counters;
+    };
+    union {
+        struct {
+            A_UINT32
+                /* enum WMI_6GHZ_REG_PWRMODE_TYPE */
+                current_power_mode              : 4,
+                /* enum WMI_6GHZ_REG_PWRMODE_TYPE */
+                last_best_power_mode            : 4,
+                is_current_mode_best_power_mode : 1,
+                rsvd1                           : 7,
+                best_power_mode_count           : 16;
+        };
+        A_UINT32 power_mode_stats;
+    };
+} htt_stats_reg_6g_tlv;
+
+#define HTT_STATS_REG_6G_GET_AFC_LOCAL_RSVD(word) \
+    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+#define HTT_STATS_REG_6G_SET_AFC_LOCAL_RSVD(word,value) \
+    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) \
+    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+#define HTT_STATS_REG_6G_SET_DEPLOYMENT_TYPE(word,value) \
+    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REG_6G_SET_SET_TPC_COUNT(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REG_6G_SET_SET_TPC_PASS_COUNT(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) \
+    HTT_STATS_GET_FIELD(0xF, 0, (word))
+#define HTT_STATS_REG_6G_SET_CURRENT_POWER_MODE(word,value) \
+    HTT_STATS_SET_FIELD(0xF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) \
+    HTT_STATS_GET_FIELD(0xF0, 4, (word))
+#define HTT_STATS_REG_6G_SET_LAST_BEST_POWER_MODE(word,value) \
+    HTT_STATS_SET_FIELD(0xF0, 4, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) \
+    HTT_STATS_GET_FIELD(0x100, 8, (word))
+#define HTT_STATS_REG_6G_SET_IS_CURRENT_POWER_MODE_BEST(word,value) \
+    HTT_STATS_SET_FIELD(0x100, 8, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REG_6G_SET_BEST_POWER_MODE_COUNT(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+#define HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS 16
+
+typedef struct {
+    union {
+        struct {
+            A_UINT32 freq  : 16, /* in MHz */
+                     power : 16; /* in dBm */
+        };
+        A_UINT32 freq_power_pair;
+    };
+    /*
+     * NOTE: no new fields can be added to this struct
+     * due to backwards-compatibility constraints.
+     */
+} htt_stats_reg_freq_power_pair_t;
+
+#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_FREQ_VALUE(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_POWER_VALUE(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 index;
+    union {
+        A_UINT32 power_info_word;
+        struct {
+            A_UINT32 power_type_6ghz : 8, /* enum WMI_6GHZ_REG_PWRMODE_TYPE */
+                     eirp_power : 8,      /* in dBm */
+                     is_psd_power : 1,
+                     both_psd_eirp_support : 1,
+                     rsvd :14;
+        };
+    };
+    union {
+        A_UINT32 num_levels_word;
+        struct {
+            A_UINT32 num_power_levels : 8,
+                     num_psd_levels : 8,
+                     num_eirp_levels : 8,
+                     unused : 8;
+        };
+    };
+    A_UINT32 puncture_bitmap;
+    htt_stats_reg_freq_power_pair_t
+        tx_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS];
+    htt_stats_reg_freq_power_pair_t
+        psd_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS];
+    htt_stats_reg_freq_power_pair_t
+        eirp_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS];
+} htt_stats_reg_6g_ch_power_info_tlv;
+
+#define HTT_STATS_REG_6G_GET_POWER_TYPE(word) \
+    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+#define HTT_STATS_REG_6G_SET_POWER_TYPE(word,value) \
+    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_EIRP_POWER(word) \
+    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+#define HTT_STATS_REG_6G_SET_EIRP_POWER(word,value) \
+    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_IS_PSD(word) \
+    HTT_STATS_GET_FIELD(0x10000, 16, (word))
+#define HTT_STATS_REG_6G_SET_IS_PSD(word,value) \
+    HTT_STATS_SET_FIELD(0x10000, 16, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) \
+    HTT_STATS_GET_FIELD(0x20000, 17, (word))
+#define HTT_STATS_REG_6G_SET_BOTH_PSD_EIRP_SUPPORT(word,value) \
+    HTT_STATS_SET_FIELD(0x20000, 17, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) \
+    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+#define HTT_STATS_REG_6G_SET_NUM_POWER_LEVELS(word,value) \
+    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) \
+    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+#define HTT_STATS_REG_6G_SET_NUM_PSD_LEVELS(word,value) \
+    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) \
+    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+#define HTT_STATS_REG_6G_SET_NUM_EIRP_LEVELS(word,value) \
+    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+
+#define HTT_STATS_REG_OOBE_MAX_BW 5
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_INT32 oobe_psd[HTT_STATS_REG_OOBE_MAX_BW]; /* dBm / MHz */
+    union {
+        struct {
+            A_INT32 oobe_limit_offset : 16,  /* in MHz */
+                    oobe_limit_psd    : 16;  /* in dBm / MHz */
+        };
+        A_UINT32 offset_mask_pair;
+    } oobe_limit[HTT_STATS_REG_OOBE_MAX_BW];
+} htt_stats_reg_6g_oobe_tlv;
+
+#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) \
+    HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_OFFSET(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+/*======================= End Regulatory stats ==================== } */
+
+
 #endif /* __HTT_STATS_H__ */

From c0315ffd418e6e81e4b4ad9909083a77c228dd4c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 23 Jan 2026 12:01:46 -0800
Subject: [PATCH 127/290] fw-api: CL 31459767 - update fw common interface
 files

Change-Id: I115ba960a233a3896ed850426f44e07b99a243e4
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9954bd0ece9d..3439bbba2c63 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -53083,6 +53083,8 @@ typedef enum {
 typedef enum {
     WMI_PDEV_POWER_BOOST_TS_FIRST_PASS = 0,
     WMI_PDEV_POWER_BOOST_TS_SECOND_PASS,
+    WMI_PDEV_POWER_BOOST_TS_THIRD_PASS,
+    WMI_PDEV_POWER_BOOST_TS_FOURTH_PASS,
 
     WMI_PDEV_POWER_BOOST_TS_MAX
 } wmi_pdev_power_boost_training_stage;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ae04da8a3278..7161a8e4f08a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1704
+#define __WMI_REVISION_ 1705
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 0c978c79c285eea96fedeb268905c6929c059682 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 23 Jan 2026 12:03:48 -0800
Subject: [PATCH 128/290] fw-api: CL 31460336 - update fw common interface
 files

Change-Id: If3ea9c061551fa1ad63e172c83f568bc5b17da64
CRs-Fixed: 3830439
---
 fw/htt.h       |   1 +
 fw/htt_stats.h | 274 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 275 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 5bc71a8ace87..ecf779745184 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -911,6 +911,7 @@ typedef enum {
     HTT_STATS_REG_6G_TAG                            = 249, /* htt_stats_reg_6g_tlv*/
     HTT_STATS_REG_6G_CH_PWR_INFO_TAG                = 250, /* htt_stats_reg_6g_ch_power_info_tlv*/
     HTT_STATS_REG_6G_OOBE_TAG                       = 251, /* htt_stats_reg_6g_oobe_tlv*/
+    HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_TAG       = 252, /* htt_stats_tx_selfgen_resp_frame_stats_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 34e0f0926773..6651bfcbf97a 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -925,6 +925,14 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_REGULATORY = 83,
 
+    /** HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_tx_selfgen_resp_frame_stats_tlv
+     */
+    HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS = 84,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -16238,5 +16246,271 @@ typedef struct {
 
 /*======================= End Regulatory stats ==================== } */
 
+/*
+ * Self response frame types. Aligning with
+ * WHAL_RESP_FRAMES (WHAL_MAX_RESP_FRAMES).
+ */
+typedef enum {
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11L_MBPS = 0,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5L_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2L_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_1L_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11S_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5S_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2S_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_6_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_9_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_12_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_18_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_24_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_36_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_48_MBPS,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_54_MBPS,
+    HTT_RESP_FRAME_TYPE_CBF_11AC,
+    HTT_RESP_FRAME_TYPE_CBF_11AX,
+    HTT_RESP_FRAME_TYPE_CBF_11BE,
+    HTT_RESP_FRAME_TYPE_CBF_11AX_EXT,
+    HTT_RESP_FRAME_TYPE_ACK_CTS_11AX_EXT_DCM,
+    HTT_RESP_FRAME_TYPE_RTT_11N_MCS0,
+    HTT_RESP_FRAME_TYPE_RTT_11N_MCS1,
+    HTT_RESP_FRAME_TYPE_RTT_11N_MCS3,
+    HTT_RESP_FRAME_TYPE_RTT_11AC_MCS0,
+    HTT_RESP_FRAME_TYPE_RTT_11AC_MCS1,
+    HTT_RESP_FRAME_TYPE_RTT_11AC_MCS3,
+    HTT_RESP_FRAME_TYPE_RTT_11A_6_MBPS,
+    HTT_RESP_FRAME_TYPE_RTT_11A_12_MBPS,
+    HTT_RESP_FRAME_TYPE_RTT_11A_24_MBPS,
+    HTT_RESP_FRAME_TYPE_RTT_11AX_MCS0,
+    HTT_RESP_FRAME_TYPE_RTT_11AX_MCS1,
+    HTT_RESP_FRAME_TYPE_RTT_11AX_MCS3,
+    HTT_RESP_FRAME_TYPE_AX_BE_EXT_DEF,
+    HTT_RESP_FRAME_TYPE_11BE_MCS14_MCS15,
+    HTT_RESP_FRAME_TYPE_MAX
+} HTT_RESP_FRAME_TYPES;
+
+/*
+ * This structure stores the essential fields from WHAL_RESP_FRAME_PARAMS
+ * that are accessed in the WHAL SELFGEN RESP FRAME STATS.
+ */
+typedef struct {
+    union {
+        A_UINT32 type_rate_chainmask;
+        struct {
+            A_UINT32
+                /* pkt_type:
+                 * 0 = CCK, 1 = OFDM, 2 = HT,
+                 * 3 = VHT, 4 = HE,   5 = EHT,
+                 */
+                pkt_type       : 4,  /* 0-3 */
+                nss            : 3,  /* 4-6:   Number of spatial streams */
+                rate_mcs       : 4,  /* 7-10:  Rate/MCS value */
+                /* bandwith:
+                 * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz
+                 */
+                bandwidth      : 3,  /* 11-13 */
+                chain_mask     : 8,  /* 14-21: Primary chain mask */
+                alt_chain_mask : 8,  /* 22-29: Alternate chain mask */
+                reserved       : 2;  /* 30-31: Reserved for future use */
+        };
+    };
+
+    union {
+        A_UINT32 tx_pwr_alt;
+        struct {
+            A_UINT32
+                tx_pwr       : 8,  /* 0-7:   Primary TX power (dBm) */
+                tx_pwr_1     : 8,  /* 8-15:  Secondary TX power (dBm) */
+                alt_tx_pwr   : 8,  /* 16-23: Alternate TX power (dBm) */
+                alt_tx_pwr_1 : 8;  /* 24-31: Alternate secondary TX pwr (dBm) */
+        };
+    };
+/*
+ * NOTE: due to backwards-compatibility constraints,
+ * this struct cannot be expanded.
+ */
+} HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY;
+
+/* Mask and shift definitions for type_rate_chainmask fields */
+#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M           0x0000000F
+#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S           0
+#define HTT_STATS_WHAL_SELFGEN_NSS_M                0x00000070
+#define HTT_STATS_WHAL_SELFGEN_NSS_S                4
+#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_M           0x00000780
+#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_S           7
+#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M          0x00003800
+#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S          11
+#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M         0x003FC000
+#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S         14
+#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M     0x3FC00000
+#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S     22
+
+#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M) >> \
+     HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S)
+#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_PKT_TYPE, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_NSS_M) >> \
+     HTT_STATS_WHAL_SELFGEN_NSS_S)
+#define HTT_STATS_WHAL_SELFGEN_NSS_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_NSS, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_NSS_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_RATE_MCS_M) >> \
+     HTT_STATS_WHAL_SELFGEN_RATE_MCS_S)
+#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_RATE_MCS, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_RATE_MCS_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M) >> \
+     HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S)
+#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_BANDWIDTH, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M) >> \
+     HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S)
+#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHAIN_MASK, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M) >> \
+     HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S)
+#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S)); \
+    } while (0)
+
+/* Mask and shift definitions for tx_pwr_alt fields */
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_M             0x000000FF
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_S             0
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M           0x0000FF00
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S           8
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M         0x00FF0000
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S         16
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M       0xFF000000
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S       24
+
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_M) >> \
+     HTT_STATS_WHAL_SELFGEN_TX_PWR_S)
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M) >> \
+     HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S)
+#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR_1, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M) >> \
+     HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S)
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) \
+    (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M) >> \
+     HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S)
+#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1, _val); \
+        ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S)); \
+    } while (0)
+
+/**
+ * HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT - Channel context information
+ *
+ * This structure stores common channel context information that is
+ * NOT per frame.
+ * It contains channel frequency, flags, and PHY mode information that applies
+ * to all self-generated response frames.
+ */
+typedef struct {
+    union {
+        A_UINT32 channel_info;
+        struct {
+            A_UINT32
+                mhz   : 16, /* 0-15:  Channel frequency in MHz */
+                /* flags:
+                 * Channel flags, with a FW-internal definition of flag values.
+                 * This fields is intended only for debugging, since the
+                 * definitions of the flag values are not provided.
+                 */
+                flags : 16; /* 16-31 */
+        };
+    };
+    A_UINT32 phy_mode; /* PHY mode (WLAN_PHY_MODE: 11a/11g/11ax/11be etc.) */
+/*
+ * NOTE: due to backwards-compatibility constraints,
+ * this struct cannot be expanded.
+ */
+} HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT;
+
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M        0x0000FFFF
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S        0
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M      0xFFFF0000
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S      16
+
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_GET(_var) \
+    (((_var).channel_context.channel_info & \
+      HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M) >> \
+     HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S)
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ, _val); \
+        ((_var).channel_context.channel_info |= \
+         ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S)); \
+    } while (0)
+
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_GET(_var) \
+    (((_var).channel_context.channel_info & \
+      HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M) >> \
+     HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S)
+#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS, _val); \
+        ((_var).channel_context.channel_info |= \
+         ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S)); \
+    } while (0)
+
+/*
+ * Statistics for self-generated response frames Rate, Pkt type, Chainmask.
+ * Has context that was captured when it was programmed.
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* Common channel context - NOT per frame */
+    HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT channel_context;
+    /* Array indexed by WHAL_RESP_FRAMES enum values */
+    HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY frame_data[HTT_RESP_FRAME_TYPE_MAX];
+} htt_stats_tx_selfgen_resp_frame_stats_tlv;
+
 
 #endif /* __HTT_STATS_H__ */

From 776dbf3f8c7ac314d3fa5e312a94d8a918c72a94 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 24 Jan 2026 12:01:45 -0800
Subject: [PATCH 129/290] fw-api: CL 31472689 - update fw common interface
 files

Change-Id: I2d700648255267af0b3831bffe0f63a404683334
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 6651bfcbf97a..39ff2f7409a5 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2669,7 +2669,7 @@ typedef enum {
     HTT_STATS_PREAM_VHT,
     HTT_STATS_PREAM_HE,
     HTT_STATS_PREAM_EHT,
-    HTT_STATS_PREAM_RSVD1,
+    HTT_STATS_PREAM_UHR,
 
     HTT_STATS_PREAM_COUNT,
 } HTT_STATS_PREAM_TYPE;

From 0b92f2f99b2adddea5c0c8f67eb70ebe29918f6d Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 24 Jan 2026 12:03:32 -0800
Subject: [PATCH 130/290] fw-api: CL 31472949 - update fw common interface
 files

Change-Id: I6d9ce5c5c7742c69f5fc45bb0ad4a4e775a71d2e
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 166 ++++++++++++++++++++++++++++++++++++++++++++---
 fw/wmi_version.h |   2 +-
 2 files changed, 159 insertions(+), 9 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 3439bbba2c63..576462dccc3f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -28292,15 +28292,14 @@ typedef struct {
      *     1 - full bandwidth need put to NOL
      *     Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros
      *
-     * Bits 1-7:
+     * Bits 1-16:
      *     RADAR TYPE field (currently reserved for future use)
      *     When implemented, this field will indicate the type of
-     *     radar detected.
-     *     The meaning of the different values of this radar type field
-     *     will be specified in the future.
+     *     radar detected, and also the domain.
+     *     For example, a value of 0x4001 means domain = 4 and radar type = 1.
      *     Refer to WMI_RADAR_FLAGS_RADAR_TYPE_GET and _SET macros.
      *
-     * Bits 8-15:
+     * Bits 17-24:
      *     RADAR RSSI in dBm in the range of -128 to +127.
      *     This 8-bit value is interpreted as a twos-complement signed number
      *     (so for example, 0x80 = -128, 0x0 = 0, and 0x7f = 127).
@@ -28308,7 +28307,7 @@ typedef struct {
      *     WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT
      *     wmi service flag is set.
      *
-     * [16:31] reserved
+     * [25:31] reserved
      */
     A_UINT32 flags;
 }  WMI_RADAR_FLAGS;
@@ -28317,9 +28316,9 @@ typedef struct {
 #define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS  1
 
 #define WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS     1
-#define WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS   7
+#define WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS   16
 
-#define WMI_RADAR_FLAGS_RSSI_DBM_BITPOS       8
+#define WMI_RADAR_FLAGS_RSSI_DBM_BITPOS       17
 #define WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS     8
 
 #define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \
@@ -28349,6 +28348,157 @@ typedef struct {
         WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \
         WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS, val)
 
+/* Bitfield layout constants */
+#define WMI_RADAR_DOMAIN_SHIFT 12
+#define WMI_RADAR_DOMAIN_MASK  0xF000
+#define WMI_RADAR_TYPE_MASK    0x0FFF
+
+/* Helper Macros */
+#define WMI_MAKE_RADAR_TYPE(domain, type) \
+    (((domain) << WMI_RADAR_DOMAIN_SHIFT) | ((type) & WMI_RADAR_TYPE_MASK))
+
+#define WMI_GET_RADAR_DOMAIN(radar_type) \
+    (((radar_type) & WMI_RADAR_DOMAIN_MASK) >> WMI_RADAR_DOMAIN_SHIFT)
+
+#define WMI_GET_RADAR_TYPE(radar_type) \
+    ((radar_type) & WMI_RADAR_TYPE_MASK)
+
+#define WMI_IS_RADAR_DOMAIN(radar_type, domain) \
+    (GET_RADAR_DOMAIN(radar_type) == (domain))
+
+/* Regulatory Domain Codes (4 bits = 0-15) */
+#define WMI_RADAR_DOMAIN_FCC        0x0    /* United States */
+#define WMI_RADAR_DOMAIN_ETSI_301   0x1    /* Europe EN 301 893 */
+#define WMI_RADAR_DOMAIN_ETSI_302   0x2    /* Europe EN 302 502 */
+#define WMI_RADAR_DOMAIN_CHINA      0x3    /* China */
+#define WMI_RADAR_DOMAIN_KOREA      0x4    /* Korea */
+#define WMI_RADAR_DOMAIN_JAPAN_W53  0x5    /* Japan W53 band */
+#define WMI_RADAR_DOMAIN_JAPAN_W56  0x6    /* Japan W56 band */
+#define WMI_RADAR_DOMAIN_JAPAN_W564 0x7    /* Japan W56.4 band */
+#define WMI_RADAR_DOMAIN_UNDEFINED  0xF    /* Undefined/Unknown */
+/* Reserved for future use: 0x8-0xE */
+
+/* Radar Type Codes within each domain (12 bits = 0-4095) */
+/* ===== FCC (United States) Radar Types ===== */
+#define WMI_DFS_RADAR_FCC_TYPE_0 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x001)
+#define WMI_DFS_RADAR_FCC_TYPE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x002)
+#define WMI_DFS_RADAR_FCC_TYPE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x004)
+#define WMI_DFS_RADAR_FCC_TYPE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x008)
+#define WMI_DFS_RADAR_FCC_TYPE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x010)
+#define WMI_DFS_RADAR_FCC_TYPE_5 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x020)
+#define WMI_DFS_RADAR_FCC_TYPE_6 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x040)
+
+/* ===== ETSI EN 301 893 Radar Types ===== */
+#define WMI_DFS_RADAR_ETSI301_TYPE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x001)
+#define WMI_DFS_RADAR_ETSI301_TYPE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x002)
+#define WMI_DFS_RADAR_ETSI301_TYPE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x004)
+#define WMI_DFS_RADAR_ETSI301_TYPE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x008)
+#define WMI_DFS_RADAR_ETSI301_TYPE_52 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x010)
+#define WMI_DFS_RADAR_ETSI301_TYPE_62 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x020)
+#define WMI_DFS_RADAR_ETSI301_TYPE_1_2 \
+    /* Combined Type 1+2 */ \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x003)
+#define WMI_DFS_RADAR_ETSI301_TYPE_1_2_6  \
+    /* Combined Type 1+2+6 */ \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x023)
+
+/* ===== ETSI EN 302 502 Radar Types ===== */
+#define WMI_DFS_RADAR_ETSI302_TYPE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x001)
+#define WMI_DFS_RADAR_ETSI302_TYPE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x002)
+#define WMI_DFS_RADAR_ETSI302_TYPE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x004)
+#define WMI_DFS_RADAR_ETSI302_TYPE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x008)
+#define WMI_DFS_RADAR_ETSI302_TYPE_5 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x010)
+#define WMI_DFS_RADAR_ETSI302_TYPE_6 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x020)
+#define WMI_DFS_RADAR_ETSI302_TYPE_1_2 \
+    /* Combined Type 1+2 */ \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x003)
+
+/* ===== China Radar Types ===== */
+#define WMI_DFS_RADAR_CHN_TYPE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x001)
+#define WMI_DFS_RADAR_CHN_TYPE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x002)
+#define WMI_DFS_RADAR_CHN_TYPE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x004)
+#define WMI_DFS_RADAR_CHN_TYPE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x008)
+#define WMI_DFS_RADAR_CHN_TYPE_5 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x010)
+#define WMI_DFS_RADAR_CHN_TYPE_6 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x020)
+#define WMI_DFS_RADAR_CHN_TYPE_1_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x003) /* Combined Type 1+2 */
+#define WMI_DFS_RADAR_CHN_TYPE_1_2_6 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x023) /* Combined Type 1+2+6 */
+#define WMI_DFS_RADAR_CHN_TYPE_3_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x00C) /* Combined Type 3+4 */
+
+/* ===== Korea Radar Types ===== */
+#define WMI_DFS_RADAR_KOR_TYPE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x001)
+#define WMI_DFS_RADAR_KOR_TYPE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x002)
+#define WMI_DFS_RADAR_KOR_TYPE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x004)
+#define WMI_DFS_RADAR_KOR_TYPE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x008)
+
+/* ===== Japan W53 Band Radar Types ===== */
+#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x001)
+#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x002)
+#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x004)
+#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x008)
+
+/* ===== Japan W56 Band Radar Types ===== */
+#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x001)
+#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_2 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x002)
+#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_3 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x004)
+#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_4 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x008)
+#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_5 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x010)
+#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_6 \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x020)
+#define WMI_DFS_RADAR_JAP_W56_CHIRP \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x040)
+#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1_2 \
+    /* Combined Type 1+2 */ \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x003)
+
+/* ===== Japan W56.4 Band Radar Types ===== */
+#define WMI_DFS_RADAR_JAP_W564_HOPPING \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W564, 0x001)
+
+/* ===== Undefined/Unknown ===== */
+#define WMI_DFS_RADAR_TYPE_UNDEF \
+    WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_UNDEFINED, 0xFFF)
+
 
 typedef enum {
     OCAC_COMPLETE = 0,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7161a8e4f08a..2bd65e41e0d9 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1705
+#define __WMI_REVISION_ 1706
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 24986c6937a388ad5b610aa0519dce3eeac8662b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 27 Jan 2026 12:04:22 -0800
Subject: [PATCH 131/290] fw-api: CL 31480148 - update fw common interface
 files

Change-Id: I5e0d31a6d8cc97cd862242a026650ca11f8ed425
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 3 ++-
 fw/wmi_unified.h  | 7 +++++++
 fw/wmi_version.h  | 2 +-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 13f000568137..d600f7988797 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -6695,7 +6695,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_setup_links_param, setup_links_param, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kde_data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID);
 
 /* Roam Synch key Event */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 576462dccc3f..ee51f2e77a36 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -32034,6 +32034,12 @@ typedef struct {
      * an SMD BSS transition or a reassociation with SMD capability.
      */
     wmi_mac_addr smd_identifier;
+    /**
+     * Length of KDE data which is received on EAPOL M3 frame or
+     * reassoc reponse frame.
+     * Ex: SAE PW ID KDE data
+     */
+    A_UINT32 kde_length;
     /**
      * TLV (tag length value) parameters follows roam_synch_event
      * The TLV's are:
@@ -32052,6 +32058,7 @@ typedef struct {
      *     wmi_key_material_ext key_ext[];
      *     wmi_roam_pmk_cache_synch_tlv_param roam_pmk_cache_synch_info[];
      *     wmi_pdev_band_to_mac mac_freq_mapping[];
+     *     A_UINT8 kde_data[];
      */
 } wmi_roam_synch_event_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2bd65e41e0d9..7cc50e443421 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1706
+#define __WMI_REVISION_ 1707
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c6aba369b5011d70c6d7f55cc3ff0e6d4640f78a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 28 Jan 2026 12:02:06 -0800
Subject: [PATCH 132/290] fw-api: CL 31493387 - update fw common interface
 files

Change-Id: Id802dbfa3bfd0c2b20d08adeb6249b012b7cc69c
CRs-Fixed: 3830439
---
 fw/htt.h       |  4 +++
 fw/htt_stats.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index ecf779745184..00af0588a35f 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -912,6 +912,10 @@ typedef enum {
     HTT_STATS_REG_6G_CH_PWR_INFO_TAG                = 250, /* htt_stats_reg_6g_ch_power_info_tlv*/
     HTT_STATS_REG_6G_OOBE_TAG                       = 251, /* htt_stats_reg_6g_oobe_tlv*/
     HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_TAG       = 252, /* htt_stats_tx_selfgen_resp_frame_stats_tlv */
+    HTT_STATS_DPD_HALPHY_TAG                        = 253, /* htt_stats_dpd_halphy_tlv */
+    HTT_STATS_DPD_HW_CAL_PARAMS_TAG                 = 254, /* htt_stats_dpd_hw_cal_params_tlv */
+    HTT_STATS_DPD_HW_CAL_RESULTS_TAG                = 255, /* htt_stats_dpd_hw_cal_results_tlv */
+
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 39ff2f7409a5..653deaacb2e2 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -933,6 +933,16 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS = 84,
 
+    /** HTT_DBG_EXT_STATS_DPD
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_stats_dpd_halphy_tlv
+     *   - htt_stats_dpd_hw_cal_params_tlv
+     *   - htt_stats_dpd_hw_cal_results_tlv
+     */
+    HTT_DBG_EXT_STATS_DPD = 85,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -16513,4 +16523,67 @@ typedef struct {
 } htt_stats_tx_selfgen_resp_frame_stats_tlv;
 
 
+#define HTT_STATS_NUM_DPD_CAL_TABLE 12
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 pdev_id;
+    A_UINT32 dpd_cal_start_time; /* ms units */
+    A_UINT32 dpd_cal_end_time; /* ms units */
+    A_UINT32 total_tx_pass_cnt;
+    A_UINT32 total_tx_fail_cnt;
+    /* dpd_trigger_reason:
+     * The definition of trigger reasons is internal to the
+     * target FW, hence, this field is opaque to the host and cannot be
+     * interpreted; this field is intended only for manual debugging.
+     */
+    A_UINT32 dpd_trigger_reason;
+    /* dpd_training_temp: units = Celsius degrees */
+    A_INT32  dpd_training_temp[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    A_INT32  cal_start_temp; /* Celsius degrees */
+    A_INT32  cal_end_temp; /* Celsius degrees */
+    A_UINT32 cal_channel; /* MHz */
+    A_UINT32 cal_phy_mode; /* WLAN_PHY_MODE */
+    A_UINT32 cal_chan_flags; /* HTT_STATS_CHANNEL_FLAGS */
+    A_UINT32 mem_dpd_post_proc_trigger_cnt;
+    A_UINT32 mem_dpd_post_proc_complete_cnt;
+    /* sch_cmd_result_per_chain:
+     * The definition of scheduler command results is internal to the
+     * target FW, hence, this field is opaque to the host and cannot be
+     * interpreted; this field is intended only for manual debugging.
+     */
+    A_UINT32 sch_cmd_result_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    /* tx_status_per_chain: 0 = success, 1 = abort, 2 = error */
+    A_UINT32 tx_status_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    /* dpd_cal_state:
+     * The definition of cal states is internal to the
+     * target FW, hence, this field is opaque to the host and cannot be
+     * interpreted; this field is intended only for manual debugging.
+     */
+    A_UINT32 dpd_cal_state;
+    A_UINT32 dpd_cal_status; /* 1 = success, 0 = failure */
+    /* dpd_fail_reason:
+     * The definition of DPD cal failure reasons is internal to the
+     * target FW, hence, this field is opaque to the host and cannot be
+     * interpreted; this field is intended only for manual debugging.
+     */
+    A_UINT32 dpd_fail_reason;
+} htt_stats_dpd_halphy_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 dpd_rx_gain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    A_UINT32 tpc_gain_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    A_UINT32 tpc_glut[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+} htt_stats_dpd_hw_cal_params_tlv;
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /* Signal Quality */
+    A_UINT32 sq_value[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    A_UINT32 sq_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+    A_INT32  nmse_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
+} htt_stats_dpd_hw_cal_results_tlv;
+
+
 #endif /* __HTT_STATS_H__ */

From f955beb16c6f31d8ca18cf688aa42ffd4df50076 Mon Sep 17 00:00:00 2001
From: Surya Prakash Sivaraj <suryapra@qti.qualcomm.com>
Date: Wed, 28 Jan 2026 16:51:15 +0530
Subject: [PATCH 133/290] qcacld-3.0: Add runtime pm lock during roaming

Acquire the runtime pm lock when roam sync event is received
and release after roam sync complete is sent.

Change-Id: Ic56d353dd343f5fcbc228a8d7251e047177b9a9b
CRs-Fixed: 3238723
---
 core/wma/inc/wma.h           |  5 +++--
 core/wma/inc/wma_internal.h  | 17 +++++++++++++++++
 core/wma/src/wma_main.c      |  3 +++
 core/wma/src/wma_scan_roam.c | 15 +++++++++++----
 core/wma/src/wma_utils.c     | 16 ++++++++++++++++
 5 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/core/wma/inc/wma.h b/core/wma/inc/wma.h
index 5474fe767d0f..787f5d3c3e6f 100644
--- a/core/wma/inc/wma.h
+++ b/core/wma/inc/wma.h
@@ -909,11 +909,11 @@ struct wma_wlm_stats_data {
  * @dynamic_nss_chains_update: per vdev nss, chains update
  * @ito_repeat_count: Indicates ito repeated count
  * @wma_fw_time_sync_timer: timer used for firmware time sync
- * * @fw_therm_throt_support: FW Supports thermal throttling?
+ * @fw_therm_throt_support: FW Supports thermal throttling?
+ * @roam_sync_runtime_lock: roam sync runtime lock
  *
  * This structure is the global wma context.  It contains global wma
  * module parameters and handles of other modules.
-
  */
 typedef struct {
 	void *wmi_handle;
@@ -1045,6 +1045,7 @@ typedef struct {
 	qdf_mc_timer_t wma_fw_time_sync_timer;
 	bool fw_therm_throt_support;
 	bool enable_tx_compl_tsf64;
+	qdf_runtime_lock_t roam_sync_runtime_lock;
 } t_wma_handle, *tp_wma_handle;
 
 /**
diff --git a/core/wma/inc/wma_internal.h b/core/wma/inc/wma_internal.h
index 1d7f88d5392c..45e2e678442b 100644
--- a/core/wma/inc/wma_internal.h
+++ b/core/wma/inc/wma_internal.h
@@ -1587,6 +1587,23 @@ void wma_acquire_wakelock(qdf_wake_lock_t *wl, uint32_t msec);
  */
 void wma_release_wakelock(qdf_wake_lock_t *wl);
 
+/**
+ * wma_prevent_pm_during_roam_sync() - prevent runtime PM during roam sync
+ * @wma: a reference to the global WMA handle
+ *
+ * Return: None
+ */
+void wma_prevent_pm_during_roam_sync(t_wma_handle *wma);
+
+/**
+ * wma_allow_pm_after_roam_sync() -  allow runtime PM after roam
+ * sync complete
+ * @wma: a reference to the global WMA handle
+ *
+ * Return: None
+ */
+void wma_allow_pm_after_roam_sync(t_wma_handle *wma);
+
 /**
  * wma_send_vdev_stop_to_fw() - send the vdev stop command to firmware
  * @wma: a reference to the global WMA handle
diff --git a/core/wma/src/wma_main.c b/core/wma/src/wma_main.c
index b48b2729e9ae..6165e7fc31e2 100644
--- a/core/wma/src/wma_main.c
+++ b/core/wma/src/wma_main.c
@@ -3428,6 +3428,7 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc,
 					"wlan_fw_rsp_wakelock");
 	qdf_runtime_lock_init(&wma_handle->wmi_cmd_rsp_runtime_lock);
 	qdf_runtime_lock_init(&wma_handle->sap_prevent_runtime_pm_lock);
+	qdf_runtime_lock_init(&wma_handle->roam_sync_runtime_lock);
 
 	/* Register peer assoc conf event handler */
 	wmi_unified_register_event_handler(wma_handle->wmi_handle,
@@ -3538,6 +3539,7 @@ err_dbglog_init:
 	qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock);
 	qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock);
 	qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock);
+	qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock);
 err_event_init:
 	wmi_unified_unregister_event_handler(wma_handle->wmi_handle,
 					     wmi_debug_print_event_id);
@@ -4592,6 +4594,7 @@ QDF_STATUS wma_close(void)
 	qdf_wake_lock_destroy(&wma_handle->wmi_cmd_rsp_wake_lock);
 	qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock);
 	qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock);
+	qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock);
 	qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock);
 
 	if (wma_handle->pGetRssiReq) {
diff --git a/core/wma/src/wma_scan_roam.c b/core/wma/src/wma_scan_roam.c
index 702063ef6170..994e08c449d7 100644
--- a/core/wma/src/wma_scan_roam.c
+++ b/core/wma/src/wma_scan_roam.c
@@ -1617,21 +1617,23 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event,
 		return status;
 	}
 
+	wma_prevent_pm_during_roam_sync(wma);
+
 	param_buf = (WMI_ROAM_SYNCH_EVENTID_param_tlvs *)event;
 	if (!param_buf) {
 		wma_err_rl("received null buf from target");
-		return status;
+		goto fail;
 	}
 	synch_event = param_buf->fixed_param;
 	if (!synch_event) {
 		wma_err_rl("received null event data from target");
-		return status;
+		goto fail;
 	}
 
 	if (synch_event->vdev_id >= wma->max_bssid) {
 		wma_err_rl("received invalid vdev_id %d",
 			   synch_event->vdev_id);
-		return status;
+		goto fail;
 	}
 
 	iface = &wma->interfaces[synch_event->vdev_id];
@@ -1647,10 +1649,14 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event,
 	if (QDF_IS_STATUS_ERROR(qdf_status)) {
 		wma_err("Failed to send the EV_ROAM");
 		wma_post_roam_sync_failure(wma, synch_event->vdev_id);
-		return status;
+		goto fail;
 	}
 	wma_debug("Posted EV_ROAM to VDEV SM");
 	return 0;
+
+fail:
+	wma_allow_pm_after_roam_sync(wma);
+	return status;
 }
 
 int wma_roam_auth_offload_event_handler(WMA_HANDLE handle, uint8_t *event,
@@ -2833,6 +2839,7 @@ void wma_process_roam_synch_complete(WMA_HANDLE handle, uint8_t vdev_id)
 	wma_info("LFR3: vdev[%d] Sent ROAM_SYNCH_COMPLETE", vdev_id);
 	wlan_roam_debug_log(vdev_id, DEBUG_ROAM_SYNCH_CNF,
 			    DEBUG_INVALID_PEER_ID, NULL, NULL, 0, 0);
+	wma_allow_pm_after_roam_sync(wma_handle);
 
 }
 #endif /* WLAN_FEATURE_ROAM_OFFLOAD */
diff --git a/core/wma/src/wma_utils.c b/core/wma/src/wma_utils.c
index 68bd4241fd04..28c927fbcd41 100644
--- a/core/wma/src/wma_utils.c
+++ b/core/wma/src/wma_utils.c
@@ -3822,6 +3822,22 @@ void wma_release_wakelock(qdf_wake_lock_t *wl)
 	qdf_runtime_pm_allow_suspend(&wma->wmi_cmd_rsp_runtime_lock);
 }
 
+void wma_prevent_pm_during_roam_sync(t_wma_handle *wma)
+{
+	if (!wma)
+		return;
+
+	qdf_runtime_pm_prevent_suspend(&wma->roam_sync_runtime_lock);
+}
+
+void wma_allow_pm_after_roam_sync(t_wma_handle *wma)
+{
+	if (!wma)
+		return;
+
+	qdf_runtime_pm_allow_suspend(&wma->roam_sync_runtime_lock);
+}
+
 QDF_STATUS wma_send_vdev_stop_to_fw(t_wma_handle *wma, uint8_t vdev_id)
 {
 	QDF_STATUS status = QDF_STATUS_E_FAILURE;

From 3a3ead7c317c4912945cb787e2defb92006cce28 Mon Sep 17 00:00:00 2001
From: Surya Prakash Sivaraj <suryapra@qti.qualcomm.com>
Date: Wed, 28 Jan 2026 23:24:10 -0800
Subject: [PATCH 134/290] qcacld-3.0: Prevent ping loss due to runtime suspend

Scenario:
1) FW sends roam start to the host, and host disables the netif
queues. Therefore, the ping from the stack does not reach the
driver.
3) The driver goes into runtime suspend, and the firmware aborts
roaming due to pmf assoc retry.
4) After assoc comeback timeout, the firmware successfully roams.
However, both roam abort and roam sync are not wakeable events.
5) Therefore, the host stays in runtime suspend until the timeout
as part of the serialization command queued during roam start.
6) Netif queues are enabled back after roam start timeout and ping
resumes.

This results in a data loss for a longer time, eventhough the
firmware has aborted the roaming. Currently, the host driver prevents
runtime suspend only from roam sync event until roam sync completion.

To fix this issue, prevent the runtime suspend from the roam start
until roam sync completion/roam abort/roam ho-failure.

Change-Id: I9d63dd6af09d17e90d7d2d6a63a8aaa59297a047
CRs-Fixed: 4413987
---
 core/wma/inc/wma.h           | 2 ++
 core/wma/src/wma_main.c      | 1 +
 core/wma/src/wma_scan_roam.c | 3 +++
 core/wma/src/wma_utils.c     | 8 ++++++++
 4 files changed, 14 insertions(+)

diff --git a/core/wma/inc/wma.h b/core/wma/inc/wma.h
index 787f5d3c3e6f..99b2164e618a 100644
--- a/core/wma/inc/wma.h
+++ b/core/wma/inc/wma.h
@@ -911,6 +911,7 @@ struct wma_wlm_stats_data {
  * @wma_fw_time_sync_timer: timer used for firmware time sync
  * @fw_therm_throt_support: FW Supports thermal throttling?
  * @roam_sync_runtime_lock: roam sync runtime lock
+ * @is_roam_lock_acquired: Is roam_sync_runtime_lock acquired
  *
  * This structure is the global wma context.  It contains global wma
  * module parameters and handles of other modules.
@@ -1046,6 +1047,7 @@ typedef struct {
 	bool fw_therm_throt_support;
 	bool enable_tx_compl_tsf64;
 	qdf_runtime_lock_t roam_sync_runtime_lock;
+	bool is_roam_lock_acquired;
 } t_wma_handle, *tp_wma_handle;
 
 /**
diff --git a/core/wma/src/wma_main.c b/core/wma/src/wma_main.c
index 6165e7fc31e2..7021b8720fc3 100644
--- a/core/wma/src/wma_main.c
+++ b/core/wma/src/wma_main.c
@@ -3429,6 +3429,7 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc,
 	qdf_runtime_lock_init(&wma_handle->wmi_cmd_rsp_runtime_lock);
 	qdf_runtime_lock_init(&wma_handle->sap_prevent_runtime_pm_lock);
 	qdf_runtime_lock_init(&wma_handle->roam_sync_runtime_lock);
+	wma_handle->is_roam_lock_acquired = false;
 
 	/* Register peer assoc conf event handler */
 	wmi_unified_register_event_handler(wma_handle->wmi_handle,
diff --git a/core/wma/src/wma_scan_roam.c b/core/wma/src/wma_scan_roam.c
index 994e08c449d7..276f64af9cf8 100644
--- a/core/wma/src/wma_scan_roam.c
+++ b/core/wma/src/wma_scan_roam.c
@@ -4558,10 +4558,12 @@ static void wma_invalid_roam_reason_handler(tp_wma_handle wma_handle,
 	if (notif == WMI_ROAM_NOTIF_ROAM_START) {
 		wma_handle->interfaces[vdev_id].roaming_in_progress = true;
 		op_code = SIR_ROAMING_START;
+		wma_prevent_pm_during_roam_sync(wma_handle);
 	} else if (notif == WMI_ROAM_NOTIF_ROAM_ABORT) {
 		wma_handle->interfaces[vdev_id].roaming_in_progress = false;
 		op_code = SIR_ROAMING_ABORT;
 		lim_sae_auth_cleanup_retry(wma_handle->mac_context, vdev_id);
+		wma_allow_pm_after_roam_sync(wma_handle);
 	} else {
 		wma_debug("Invalid notif %d", notif);
 		return;
@@ -4737,6 +4739,7 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf,
 									= false;
 		lim_sae_auth_cleanup_retry(wma_handle->mac_context,
 					   wmi_event->vdev_id);
+		wma_allow_pm_after_roam_sync(wma_handle);
 		break;
 #endif
 	case WMI_ROAM_REASON_INVALID:
diff --git a/core/wma/src/wma_utils.c b/core/wma/src/wma_utils.c
index 28c927fbcd41..87c194ee45f0 100644
--- a/core/wma/src/wma_utils.c
+++ b/core/wma/src/wma_utils.c
@@ -3827,7 +3827,11 @@ void wma_prevent_pm_during_roam_sync(t_wma_handle *wma)
 	if (!wma)
 		return;
 
+	if (wma->is_roam_lock_acquired)
+		return;
+
 	qdf_runtime_pm_prevent_suspend(&wma->roam_sync_runtime_lock);
+	wma->is_roam_lock_acquired = true;
 }
 
 void wma_allow_pm_after_roam_sync(t_wma_handle *wma)
@@ -3835,7 +3839,11 @@ void wma_allow_pm_after_roam_sync(t_wma_handle *wma)
 	if (!wma)
 		return;
 
+	if (!wma->is_roam_lock_acquired)
+		return;
+
 	qdf_runtime_pm_allow_suspend(&wma->roam_sync_runtime_lock);
+	wma->is_roam_lock_acquired = false;
 }
 
 QDF_STATUS wma_send_vdev_stop_to_fw(t_wma_handle *wma, uint8_t vdev_id)

From 33dbbc502a8e63e65432e6347f4cafe9716895f8 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 30 Jan 2026 12:01:53 -0800
Subject: [PATCH 135/290] fw-api: CL 31516593 - update fw common interface
 files

Change-Id: I3f3ebcc04b007437715d8070ae1a042ede3e49a2
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 653deaacb2e2..2d6df062ee6c 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -7757,6 +7757,8 @@ typedef struct {
 
 #define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5
 
+#define HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR 12
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -7820,6 +7822,17 @@ typedef struct {
      * response to basic trigger. Typically a data response is expected.
      */
     A_UINT32 ul_ofdma_basic_trigger_rx_qos_null_only;
+
+    /* tcp_aware_implicit_trig_hist_ms:
+     * Each histogram bin represents a 3 ms range:
+     * tcp_aware_implicit_trig_hist_ms[0] -> 0-3 ms,
+     * tcp_aware_implicit_trig_hist_ms[1] -> 3-6 ms,
+     * etc.
+     */
+    A_UINT32 tcp_aware_implicit_trig_hist_ms[HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR];
+
+    A_UINT32 ulofdma_implicit_trig_tried;
+    A_UINT32 ulofdma_implicit_trig_qos_null;
 } htt_stats_rx_pdev_ul_trig_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv;
@@ -7955,6 +7968,11 @@ typedef struct {
     A_UINT32 bn_ul_ofdma_rx_dru_sbw[HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT];
     /* UL OFDMA DRU size of data PPDU */
     A_UINT32 bn_rx_ulofdma_data_dru_size_ppdu[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS];
+
+    A_UINT32 be_ulofdma_implicit_trig_tried;
+    A_UINT32 be_ulofdma_implicit_trig_qos_null;
+    A_UINT32 bn_ulofdma_implicit_trig_tried;
+    A_UINT32 bn_ulofdma_implicit_trig_qos_null;
 } htt_stats_rx_pdev_be_bn_ul_trig_tlv;
 /* preserve old names as aliases */
 typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv

From 41583e2eb5c83267b1935c4b0f5edcde349cb004 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 30 Jan 2026 12:04:24 -0800
Subject: [PATCH 136/290] fw-api: CL 31516597 - update fw common interface
 files

Change-Id: I25fbcee4adddcd4590c7a38a59cb8bacd9cfac4b
CRs-Fixed: 3830439
---
 fw/htt.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 00af0588a35f..b970ceb92c44 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -5563,8 +5563,8 @@ enum htt_srng_ring_id {
     HTT_HOST3_TO_FW_RXBUF_RING,    /* used by host for EasyMesh feature */
     HTT_HOST4_TO_FW_RXBUF_RING,    /* fourth ring used by host to provide buffers for MGMT packets */
     HTT_RXDMA_WBM_BUF0_RING,       /* used for SFE Datapath */
-    HTT_RXDMA_WBM_BUF1_RING,       /* used for PPE Datapath */
-    HTT_RXDMA_WBM_BUF2_RING,       /* used for MGMT path */
+    HTT_RXDMA_WBM_BUF1_RING,       /* used for MGMT Datapath */
+    HTT_RXDMA_WBM_BUF2_RING,       /* used for PPE path */
     HTT_RXOLE_ASE_STATUS_RING,     /* RxOLE2SW ASE Status ring */
     /* Add Other SRING which can't be directly configured by host software above this line */
 };

From 19a4fe8ad1ec70d171148753779875618170e5b8 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 30 Jan 2026 12:06:32 -0800
Subject: [PATCH 137/290] fw-api: CL 31516598 - update fw common interface
 files

Change-Id: I61bf972c3dfb2af23618ae7bdd25991b3578394b
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  29 ++++---
 fw/wmi_unified.h  | 213 +++++++++++++++++++++++++++++++++++++---------
 fw/wmi_version.h  |   2 +-
 3 files changed, 192 insertions(+), 52 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d600f7988797..7313097043aa 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1503,8 +1503,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_co_located_chan_info,
     WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, /* deprecated */
-    WMITLV_TAG_STRUC_wmi_peer_npca_cap_params,
-    WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_npca_cap_params,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, /*deprecated*/
     WMITLV_TAG_STRUC_wmi_wfa_config_ml,
     WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param,
@@ -1573,6 +1573,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_dis_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2145,7 +2146,7 @@ typedef enum {
     OP(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID) \
     OP(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID) \
     OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \
-    OP(WMI_PEER_NPCA_CAP_CMDID) \
+    OP(WMI_PEER_UHR_MODE_UPDATE_CMDID) \
     OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \
     OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \
     OP(WMI_PEER_ASSOC_V2_CMDID) \
@@ -3095,7 +3096,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
@@ -5404,11 +5405,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID);
 
-/* Multi Peer NPCA Capabilities command */
-#define WMITLV_TABLE_WMI_PEER_NPCA_CAP_CMDID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_param, wmi_peer_npca_cap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)
-WMITLV_CREATE_PARAM_STRUC(WMI_PEER_NPCA_CAP_CMDID);
+/* Multi Peer UHR Mode Update command */
+#define WMITLV_TABLE_WMI_PEER_UHR_MODE_UPDATE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param, wmi_peer_uhr_mode_update_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_MODE_UPDATE_CMDID);
 
 /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */
 #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \
@@ -6188,7 +6189,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \
  \
@@ -6230,7 +6231,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tup_dis_params, mode_tup_dis_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
 
 #define WMITLV_TABLE_WMI_PDEV_UHR_CU_CMDID(id,op,buf,len) \
@@ -6241,7 +6243,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tup_dis_params, mode_tup_dis_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
 
 /* WMI command for unified SMD PEER SETUP cmd */
@@ -6279,7 +6282,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ee51f2e77a36..6848ea2ee781 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -904,8 +904,8 @@ typedef enum {
     /** Customize MCS range for specific tid */
     WMI_PEER_TID_RATE_CUSTOM_CMDID,
 
-    /** Peer NPCA CAP Command **/
-    WMI_PEER_NPCA_CAP_CMDID,
+    /** Peer UHR Mode Update Command **/
+    WMI_PEER_UHR_MODE_UPDATE_CMDID,
 
     /* WMI_PEER_ASSOC_V2_CMDID: extended alternative for WMI_PEER_ASSOC_CMDID */
     WMI_PEER_ASSOC_V2_CMDID,
@@ -23069,7 +23069,7 @@ typedef struct {
  *     wmi_peer_assoc_operating_mode_params <-- operating mode param that
  *         host sends to AP in peer assoc req, optional TLV
  * --- the below only apply to WMI_PEER_ASSOC_V2_CMD, not WMI_PEER_ASSOC_CMDID
- *     wmi_peer_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA
+ *     wmi_peer_uhr_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA
  *         capabilities, host sends NPCA peer capabilities as an optional TLV
  *     wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create
  *         Optional TLV, only present for MLO peers.
@@ -23093,55 +23093,50 @@ typedef struct {
 #define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
 
 typedef struct {
-    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_params*/
+    A_UINT32 tlv_header;
     A_UINT32 sw_peer_id;
     /*
      * flags
-     * Bit0    :   NPCA Enabled/Disabled
-     *             WMI_NPCA_AP_CAP_ENABLED_GET / WMI_NPCA_AP_CAP_ENABLED_SET
+     * Bit 0    :   NPCA Cap supported/Not supported
+     *              WMI_NPCA_PEER_CAP_SUPPORTED_GET / _SET
      *
-     * Bit1-3  :   NPCA Types
-     *             0:   Type1 - Two STF detectors
-     *             1:   Type2 - One STF detector
-     *             2-7: reserved for future purpose
-     *             WMI_NPCA_AP_CAP_TYPE_GET / WMI_NPCA_AP_CAP_TYPE_SET
+     * Bit 1    :   NPCA Enabled / Disabled
+     *              WMI_NPCA_PEER_CAP_ENABLED_GET / _SET
      *
-     * Bit4-9  :   NPCA Switch Delay
-     *             The time needed by an NPCA STA to switch from the
-     *             BSS primary channel to the NPCA primary channel,
-     *             in units of 4 us.
-     *             WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
+     * Bit 2-7  :   NPCA Switch Delay
+     *              The time needed by an NPCA STA to switch from the
+     *              BSS primary channel to the NPCA primary channel,
+     *              in units of 4 us.
+     *              WMI_NPCA_PEER_CAP_SWT_DELAY_GET / _SET
      *
-     * Bit10:15:   NPCA Switch Back Delay
-     *             The time needed by an NPCA STA to switch from the
-     *             NPCA primary channel to the BSS primary channel,
-     *             in units of 4 us.
-     *             WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
+     * Bit 8:13 :   NPCA Switch Back Delay
+     *              The time needed by an NPCA STA to switch from the
+     *              NPCA primary channel to the BSS primary channel,
+     *              in units of 4 us.
+     *              WMI_NPCA_PEER_CAP_SWTB_DELAY_GET / _SET
      *
-     * Bit16:31:   Reserved
-    */
+     * Bit 14:31:   Reserved
+     */
     A_UINT32 npca_cap;
-} wmi_peer_npca_cap_params;
+} wmi_peer_uhr_npca_cap_params;
 
-#define WMI_NPCA_PEER_CAP_ENABLED_GET(_var)          WMI_GET_BITS(_var, 0, 1)
-#define WMI_NPCA_PEER_CAP_ENABLED_SET(_var, _val)    WMI_SET_BITS(_var, 0, 1, _val)
-
-#define WMI_NPCA_PEER_CAP_TYPE_GET(_var)             WMI_GET_BITS(_var, 1, 3)
-#define WMI_NPCA_PEER_CAP_TYPE_SET(_var, _val)       WMI_SET_BITS(_var, 1, 3, _val)
-
-#define WMI_NPCA_PEER_CAP_SWT_DELAY_GET(_var)        WMI_GET_BITS(_var, 4, 6)
-#define WMI_NPCA_PEER_CAP_SWT_DELAY_SET(_var, _val)  WMI_SET_BITS(_var, 4, 6, _val)
-
-#define WMI_NPCA_PEER_CAP_SWTB_DELAY_GET(_var)       WMI_GET_BITS(_var, 10, 6)
-#define WMI_NPCA_PEER_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 10, 6, _val)
+#define WMI_NPCA_PEER_CAP_SUPPORTED_GET(_var)           WMI_GET_BITS(_var, 0, 1)
+#define WMI_NPCA_PEER_CAP_SUPPORTED_SET(_var, _val)     WMI_SET_BITS(_var, 0, 1, _val)
+#define WMI_NPCA_PEER_CAP_ENABLED_GET(_var)             WMI_GET_BITS(_var, 1, 1)
+#define WMI_NPCA_PEER_CAP_ENABLED_SET(_var, _val)       WMI_SET_BITS(_var, 1, 1, _val)
+#define WMI_NPCA_PEER_CAP_SWT_DELAY_GET(_var)           WMI_GET_BITS(_var, 2, 6)
+#define WMI_NPCA_PEER_CAP_SWT_DELAY_SET(_var, _val)     WMI_SET_BITS(_var, 2, 6, _val)
+#define WMI_NPCA_PEER_CAP_SWTB_DELAY_GET(_var)          WMI_GET_BITS(_var, 8, 6)
+#define WMI_NPCA_PEER_CAP_SWTB_DELAY_SET(_var, _val)    WMI_SET_BITS(_var, 8, 6, _val)
 
 typedef struct {
-    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_npca_cap_cmd_fixed_params*/
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_params */
+    A_UINT32 pdev_id;
     /*
      *  Following this structure is the TLV:
-     * struct wmi_peer_npca_cap_params peer_npca_cap_params[num_peers];
+     * struct wmi_peer_uhr_npca_cap_params peer_npca_cap_params[num_peers];
      */
-} wmi_peer_npca_cap_cmd_fixed_param;
+} wmi_peer_uhr_mode_update_cmd_fixed_param;
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */
@@ -54161,6 +54156,145 @@ typedef struct {
 #define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_GET(_var)       WMI_GET_BITS(_var, 1, 1)
 #define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val)
 
+
+/* ---------------- Mode bit positions ---------------- */
+typedef enum {
+    WMI_UHR_AP_MODE_TUP_DPS    = 0,
+    WMI_UHR_AP_MODE_TUP_NPCA   = 1,
+    WMI_UHR_AP_MODE_TUP_DUO    = 2,
+    WMI_UHR_AP_MODE_TUP_PEDCA  = 3,
+    WMI_UHR_AP_MODE_TUP_DBE    = 4,
+    WMI_UHR_AP_MODE_TUP_PUO    = 5,
+    WMI_UHR_AP_MODE_TUP_ELR    = 6,
+    /* Future modes -> 6..23 */
+    WMI_UHR_MAX_MODES = 24
+} WMI_UHR_AP_MODE_TUP;
+
+/* ============================================================================
+ * Packed layout:
+ *   bits [7:0]   -> vdev_id (8 bits)
+ *   bits [31:8]  -> mode disable bitmap (24 bits)
+ * ========================================================================== */
+
+#define WMI_UHR_AP_VDEV_ID_MASK                         0x000000FF
+#define WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK          0x00FFFFFF
+#define WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT                  8
+
+#define WMI_UHR_AP_GET_VDEV_ID(var) \
+    ((var) & WMI_UHR_AP_VDEV_ID_MASK)
+
+#define WMI_UHR_AP_MODE_TUP_GET_BITS(var) \
+    (((var) >> WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT) & WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK)
+
+#define WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK(vdev_id, bits) \
+    (((vdev_id) & WMI_UHR_AP_VDEV_ID_MASK) | \
+     (((bits) & WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK) << WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT))
+
+/* Set a disable bit (bit := 1) */
+#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET(var, vdev_id, bit)                  \
+    do {                                                                     \
+        if (WMI_MAX_VDEV_CHECK(vdev_id) && (bit) < WMI_UHR_MAX_MODES) {      \
+            A_UINT32 bits = WMI_UHR_AP_MODE_TUP_GET_BITS(var);                 \
+            bits |= (1 << (bit));                                           \
+            (var) = WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK((vdev_id), bits);                 \
+        }                                                                    \
+    } while (0)
+
+/* Clear a disable bit (bit := 0) */
+#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR(var, vdev_id, bit)                  \
+    do {                                                                     \
+        if (WMI_MAX_VDEV_CHECK(vdev_id) && (bit) < WMI_UHR_MAX_MODES) {      \
+            A_UINT32 bits = WMI_UHR_AP_MODE_TUP_GET_BITS(var);                 \
+            bits &= ~(1 << (bit));                                          \
+            (var) = WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK((vdev_id), bits);                 \
+        }                                                                    \
+    } while (0)
+
+/* Read a disable bit (returns 0 or 1) */
+#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET(var, bit)                           \
+    (((bit) < WMI_UHR_MAX_MODES) ?                                          \
+     ((WMI_UHR_AP_MODE_TUP_GET_BITS(var) >> (bit)) & 1) : 0)
+
+/* ============================================================================
+ *  Per‑MODE Macros to Get/Set/CLR Modes
+ * ========================================================================== */
+
+/* NPCA */
+#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_NPCA)
+#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_NPCA)
+#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_NPCA)
+
+/* DBE */
+#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DBE)
+#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DBE)
+#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DBE)
+
+/* DPS */
+#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DPS)
+#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DPS)
+#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DPS)
+
+/* DUO */
+#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DUO)
+#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DUO)
+#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DUO)
+
+/* PUO */
+#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PUO)
+#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PUO)
+#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_PUO)
+
+/* ELR */
+#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_ELR)
+#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_ELR)
+#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_ELR)
+
+/* PEDCA */
+#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_SET(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PEDCA)
+#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_CLR(var, vdev_id) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PEDCA)
+#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_GET(var) \
+    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_PEDCA)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_dis_params */
+    A_UINT32 tlv_header;
+    /*
+     * WMI_UHR_AP_MODE_TUP_NPCA/DBE/DPS/DUO/PUO/ELR/PEDCA
+     * Modes are defined in WMI_UHR_AP_MODE_TUP
+     * WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_SET/CLR/GET
+     * similarly for DBE/DPS/DUO/PUO/ELR/PEDCA
+     */
+    union{
+        A_UINT32 vdev_id_mode_tuple_disabled_bits;
+        struct{
+            A_UINT32 vdev_id:8,
+                     mode_tup_disabled_bits:24;
+        };
+    };
+    /* Add any new required fields below */
+} wmi_uhr_ap_mode_tup_dis_params;
+
 typedef struct {
     /** TLV tag and len; tag equals
      * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param */
@@ -54174,6 +54308,7 @@ typedef struct {
      *   - wmi_uhr_ap_dbe_params
      *   - wmi_uhr_ap_ap_puo_params
      *   - wmi_uhr_ap_elr_reception_params
+     *   - wmi_uhr_ap_mode_tup_dis_params[]
      */
 } wmi_vdev_uhr_cu_cmd_fixed_param;
 
@@ -54181,6 +54316,7 @@ typedef struct {
     /** TLV tag and len; tag equals
      * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param */
     A_UINT32 tlv_header;
+    A_UINT32 pdev_id;
     /* This fixed param TLV will be followed by the below TLVs
      *   - wmi_uhr_ap_dps_params[]
      *   - wmi_uhr_ap_npca_params[]
@@ -54189,6 +54325,7 @@ typedef struct {
      *   - wmi_uhr_ap_dbe_params[]
      *   - wmi_uhr_ap_ap_puo_params[]
      *   - wmi_uhr_ap_elr_reception_params[]
+     *   - wmi_uhr_ap_mode_tup_dis_params[]
      */
 } wmi_pdev_uhr_cu_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7cc50e443421..ccc436207f40 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1707
+#define __WMI_REVISION_ 1708
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 7df31b43f1857388c7a0e8862d113a2a650180d9 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 31 Jan 2026 12:03:39 -0800
Subject: [PATCH 138/290] fw-api: CL 31528807 - update fw common interface
 files

Change-Id: I546fd188d0fc4a17518b7ef92341133e440b1a2d
CRs-Fixed: 3830439
---
 fw/htt.h          | 99 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  |  7 +++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 107 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index b970ceb92c44..0d47067f68db 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -21907,6 +21907,102 @@ PREPACK struct htt_rx_peer_metadata_v1b {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \
     } while (0)
 
+
+/*
+ * htt_rx_peer_metadata_v2 - HTT RX peer metadata version 2
+ *
+ * |31        21|20    13|12|11  9|8   6|  5  |4   0|
+ * |------------+--------+--+-----+-----+-----+-----|
+ * |  reserved  |peer    |Q | Log |VDEV | ML  |Peer |
+ * |            |session |D |Link | ID  |Peer | ID  |
+ * |            |ID      |R | ID  |     |Valid|     |
+ * |------------+--------+--+-----+-----+-----+-----|
+ * Where:
+ *     QDR = queue data refill
+ */
+PREPACK struct htt_rx_peer_metadata_v2 {
+    A_UINT32
+        peer_id:          5,
+        ml_peer_valid:    1,
+        vdev_id:          3,
+        logical_link_id:  3,
+        qdata_refill:     1,
+        peer_session_id:  8,
+        reserved:        11;
+} POSTPACK;
+
+#define HTT_RX_PEER_META_DATA_V2_PEER_ID_S 0
+#define HTT_RX_PEER_META_DATA_V2_PEER_ID_M 0x0000001f
+
+#define HTT_RX_PEER_META_DATA_V2_PEER_ID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_ID_M) >> \
+    HTT_RX_PEER_META_DATA_V2_PEER_ID_S)
+#define HTT_RX_PEER_META_DATA_V2_PEER_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_ID, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_ID_S)); \
+    } while (0)
+
+#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S 5
+#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M 0x00000020
+#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M) >> \
+    HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S)
+#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S)); \
+    } while (0)
+
+#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_S 6
+#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_M 0x000001c0
+
+#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_VDEV_ID_M) >> \
+    HTT_RX_PEER_META_DATA_V2_VDEV_ID_S)
+#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_VDEV_ID, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_VDEV_ID_S)); \
+    } while (0)
+
+#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S 9
+#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M 0x00000e00
+
+#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M) >> \
+    HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S)
+#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S)); \
+    } while (0)
+
+#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S 12
+#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M 0x00001000
+
+#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M) >> \
+    HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S)
+#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_REFILL, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S)); \
+    } while (0)
+
+#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S 13
+#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M 0x001fe000
+
+#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M) >> \
+    HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S)
+#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S)); \
+    } while (0)
+
+
 /* generic variables for masks and shifts for various fields */
 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S;
 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M;
@@ -21939,6 +22035,9 @@ extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val
 extern A_UINT32 (*HTT_RX_PEER_META_DATA_QDATA_REFILL_GET) (A_UINT32 var);
 extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 val);
 
+extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_GET) (A_UINT32 var);
+extern void (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_SET) (A_UINT32 *var, A_UINT32 val);
+
 
 /*
  * In some systems, the host SW wants to specify priorities between
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 59d421607c6c..68af4910efa1 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -757,6 +757,7 @@ typedef  enum  {
     WMI_SERVICE_SMD_SUPPORT_UL_FORWARD = 491,
     /* Service caps related to SMD Roaming - end */
 
+    WMI_SERVICE_PEER_METADATA_V2_SUPPORT = 492, /* Support rx peer meta data v2 */
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6848ea2ee781..9906e5cff062 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3758,6 +3758,10 @@ typedef struct {
 #define WMI_TARGET_CAP_TOTAL_ML_LINKS_NUM_SET(target_cap_flags, value) \
     WMI_SET_BITS(target_cap_flags, 23, 3, value)
 
+#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_GET(target_cap_flags) \
+    WMI_GET_BITS(target_cap_flags, 26, 3)
+#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_SET(target_cap_flags, value) \
+    WMI_SET_BITS(target_cap_flags, 26, 3, value)
 
 /*
  * wmi_htt_msdu_idx_to_htt_msdu_qtype GET/SET APIs
@@ -3976,7 +3980,8 @@ typedef struct {
      * Bits 19:17 - max number of ML STA BSS supported, range [0-7]
      * Bits 22:20 - max number of ML SAP BSS supported, range [0-7]
      * Bits 25:23 - total number of ML links supported, range [0-7]
-     * Bits 31:26 - Reserved
+     * Bits 28:27 - extended rx peer metadata version capabilities
+     * Bits 31:29 - Reserved
      */
     A_UINT32 target_cap_flags;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ccc436207f40..01e2de570fe3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1708
+#define __WMI_REVISION_ 1709
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From dea1e510517b0aa6bd5c83810e487edd36ed1bcd Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 31 Jan 2026 12:07:35 -0800
Subject: [PATCH 139/290] fw-api: CL 31530723 - update fw common interface
 files

Change-Id: Ic6d5772cb394c2554dd12d8abe9df12020b99eba
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index be9e8f863c29..29f92c75c981 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -1986,6 +1986,14 @@ typedef enum HTT_PPDU_STATS_RU_SIZE {
     HTT_PPDU_STATS_RU_996x4,
 } HTT_PPDU_STATS_RU_SIZE;
 
+typedef enum HTT_PPDU_STATS_DRU_SIZE {
+    HTT_PPDU_STATS_DRU_26,
+    HTT_PPDU_STATS_DRU_52,
+    HTT_PPDU_STATS_DRU_106,
+    HTT_PPDU_STATS_DRU_242,
+    HTT_PPDU_STATS_DRU_484,
+} HTT_PPDU_STATS_DRU_SIZE;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -2023,6 +2031,7 @@ typedef struct {
      * Discriminant is field ru_format:
      *     - ru_format = 0: ru_end, ru_start
      *     - ru_format = 1: ru_index, ru_size
+     *     - ru_format = 2: dru_index, dru_size, dru_sbw, dru_sbw_idx
      *     - ru_format = other: reserved for future expansion
      *
      * ru_start and ru_end are RU 26 indices
@@ -2055,10 +2064,15 @@ typedef struct {
      *
      * resp_ru_size is an HTT_PPDU_STATS_RU_SIZE, resp_ru_index
      * is a size specific index for the given ru_size.
+     *
+     * 'is_dru' field indicates if the current RU allocation
+     * is a distributed RU allocation or not.
+     * 'dru_sbw' is the spreading BW size of current dru_size.
      */
     union {
         A_UINT32 resp_ru_start__ru_end;
         A_UINT32 resp_ru_size__ru_index;
+        A_UINT32 dru_size__dru_index__dru_sbw_idx__dru_sbw__is_dru;
         struct {
             A_UINT32 resp_ru_end:   16,
                      resp_ru_start: 16;
@@ -2067,6 +2081,14 @@ typedef struct {
             A_UINT32 resp_ru_index: 16,
                      resp_ru_size:  16;
         };
+        struct {
+            A_UINT32 is_dru:         1,
+                     dru_sbw:        3,
+                     dru_sbw_idx:    2,
+                     dru_index:     16,
+                     dru_size:       4,
+                     reserved5:       6;
+        };
     };
 
     /* BIT [ 0 :   0 ]   :- resp_type_valid

From 98ede42b7c3f14cda113ddfee6579a299821cd67 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 31 Jan 2026 12:09:22 -0800
Subject: [PATCH 140/290] fw-api: CL 31531034 - update fw common interface
 files

Change-Id: I134d2bbbba6df71aa4d71821e2d0ed07d94b28b7
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 12 ++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9906e5cff062..a1a69af33bbd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -34040,16 +34040,28 @@ typedef struct {
     A_UINT32 vdev_id;
 } wmi_vdev_unified_disconnect_cmd_fixed_param;
 
+typedef enum {
+    WMI_VDEV_UNIFIED_CONNECT_EVENT_SUCCESS,
+    WMI_VDEV_UNIFIED_CONNECT_EVENT_FAILURE,
+} WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
     A_UINT32 vdev_id;
+    A_UINT32 status; /* WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS */
 } wmi_vdev_unified_connect_event_fixed_param;
 
+typedef enum {
+    WMI_VDEV_UNIFIED_DISCONNECT_EVENT_SUCCESS,
+    WMI_VDEV_UNIFIED_DISCONNECT_EVENT_FAILURE,
+} WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
     A_UINT32 vdev_id;
+    A_UINT32 status; /* WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS */
 } wmi_vdev_unified_disconnect_event_fixed_param;
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 01e2de570fe3..ded5778bec4e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1709
+#define __WMI_REVISION_ 1710
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c2c7dcca3b51c708c1fdb292ec6ee5d03bcfb5fc Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 1 Feb 2026 12:01:56 -0800
Subject: [PATCH 141/290] fw-api: CL 31532680 - update fw common interface
 files

Change-Id: I209f4547df6ff7432b06226ebe98434447e5f635
CRs-Fixed: 3830439
---
 fw/htt.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 0d47067f68db..eda0e62c2f35 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -11898,8 +11898,9 @@ PREPACK struct htt_h2t_mpduq_and_msduq_info_hdr {
 /*
  * Enum describes the various msduq/mpduq types,
  * First 8 types correspond to the standard msduq types for data
- * Next come custom flows for specific purposes
- * enum 30 is reserved for mpduq type
+ * Next come custom flows for specific purposes.
+ * Values 23-29 will be used for MGMT flows.
+ * The value 30 is reserved for mpduq type
  */
 typedef enum {
     HTT_H2T_TID_MSDUQ_NONUDP,                                    /* 0 */
@@ -11916,7 +11917,15 @@ typedef enum {
     HTT_H2T_TID_MSDUQ_MCAST,                                     /* 9 */
     HTT_H2T_TID_MSDUQ_FAST_ROAMING,                              /* 10 */
 
-    HTT_H2T_TID_MSDUQ_DATA_TYPE_END = 29,                        /* 29 */
+    HTT_H2T_TID_MSDUQ_DATA_TYPE_END = 23,                        /* 23 */
+
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_0,                      /* 24 */
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_1,                      /* 25 */
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_2,                      /* 26 */
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_3,                      /* 27 */
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_4,                      /* 28 */
+    HTT_H2T_TID_MSDUQ_MGMT_LINK_AGNOSTIC,                        /* 29 */
+
     HTT_H2T_TID_MPDUQ_TYPE,                                      /* 30 */
     HTT_H2T_TID_MSDUQ_MPDUQ_TYPE_END,                            /* 31 */
 } HTT_H2T_TID_MSDUQ_MPDUQ_TYPE;

From c9d0ab810a77087817d6eb33d205e1dec60b0298 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 3 Feb 2026 12:02:19 -0800
Subject: [PATCH 142/290] fw-api: CL 31548353 - update fw common interface
 files

Change-Id: I864f6f8ad86f37e4b996a20a8da736eb4ec94e75
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 2d6df062ee6c..5bcbf328e61e 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -7334,6 +7334,8 @@ typedef struct {
     A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
     A_UINT32 tx_gi_ext_3[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
     A_UINT32 tx_stbc_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
+    /* Stats for UHR ELR */
+    A_UINT32 tx_11bn_su_elr; 
 } htt_stats_tx_pdev_bn_rate_tlv;
 
 
@@ -7605,6 +7607,7 @@ typedef struct {
 
     /* Stats for MCS 12/13 */
     A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS];
+    A_UINT32 rx_11bn_su_elr;
 /*
  * NOTE - this TLV is already large enough that it causes the HTT message
  * carrying it to be nearly at the message size limit that applies to

From 8cea9b478dd7ac94438e009ce08a77d9e4fffe01 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 3 Feb 2026 12:04:18 -0800
Subject: [PATCH 143/290] fw-api: CL 31548376 - update fw common interface
 files

Change-Id: Idaec7d9e175740c601c5ab6e14950ca8dff03f8e
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |   4 +-
 fw/wmi_unified.h  | 167 +++++++++++++++++-----------------------------
 fw/wmi_version.h  |   2 +-
 3 files changed, 65 insertions(+), 108 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 7313097043aa..cb599d519855 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -6232,7 +6232,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tup_dis_params, mode_tup_dis_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
 
 #define WMITLV_TABLE_WMI_PDEV_UHR_CU_CMDID(id,op,buf,len) \
@@ -6244,7 +6244,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tup_dis_params, mode_tup_dis_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
 
 /* WMI command for unified SMD PEER SETUP cmd */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a1a69af33bbd..e1fece5440b0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3172,7 +3172,7 @@ typedef struct _wmi_ppe_threshold {
 #define WMI_MAX_EHTCAP_PHY_SIZE  3
 
 #define WMI_MAX_UHRCAP_MAC_SIZE  4
-#define WMI_MAX_UHRCAP_PHY_SIZE  3
+#define WMI_MAX_UHRCAP_PHY_SIZE  8 /* as per spec recommendation */
 
 /*
  * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid)
@@ -5097,8 +5097,11 @@ typedef struct {
      *      1 -> enable the feature
      *     Refer to below WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_GET/SET
      *     macros.
+     *  Bits 28:26 - extension bits for specifing the format version of the
+     *     rx peer metadata the target needs to use (to cover versions V2 and
+     *     beyond).
      *
-     *  Bits 31:26 - Reserved
+     *  Bits 31:29 - Reserved
      */
     A_UINT32 flags2;
     /** @brief host_service_flags - can be used by Host to indicate
@@ -5737,6 +5740,10 @@ typedef struct {
 #define WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_SET(flags2, value) \
     WMI_SET_BITS(flags2, 25, 1, value)
 
+#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_GET(flags2) \
+    WMI_GET_BITS(flags2, 26, 3)
+#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_SET(flags2, value) \
+    WMI_SET_BITS(flags2, 26, 3, value)
 
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
     WMI_GET_BITS(host_service_flags, 0, 1)
@@ -54187,130 +54194,80 @@ typedef enum {
     WMI_UHR_MAX_MODES = 24
 } WMI_UHR_AP_MODE_TUP;
 
-/* ============================================================================
- * Packed layout:
- *   bits [7:0]   -> vdev_id (8 bits)
- *   bits [31:8]  -> mode disable bitmap (24 bits)
- * ========================================================================== */
+typedef enum{
+    WMI_UHR_AP_MODE_TUP_STATE_DISABLE   = 0,
+    WMI_UHR_AP_MODE_TUP_STATE_ENABLE    = 1,
+    WMI_UHR_AP_MODE_TUP_STATE_UPDATE    = 2,
+    WMI_UHR_AP_MODE_TUP_STATE_RESERVED  = 3,
+    WMI_UHR_AP_MODE_TUP_STATE_MAX       = 4
+} WMI_UHR_AP_MODE_TUP_STATE;
 
-#define WMI_UHR_AP_VDEV_ID_MASK                         0x000000FF
-#define WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK          0x00FFFFFF
-#define WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT                  8
+#define WMI_UHR_AP_VDEV_ID_GET(var)             WMI_GET_BITS(var, 0, 8)
+#define WMI_UHR_AP_VDEV_ID_SET(var, val)        WMI_SET_BITS(var, 0, 8, val)
 
-#define WMI_UHR_AP_GET_VDEV_ID(var) \
-    ((var) & WMI_UHR_AP_VDEV_ID_MASK)
 
-#define WMI_UHR_AP_MODE_TUP_GET_BITS(var) \
-    (((var) >> WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT) & WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK)
+#define WMI_UHR_AP_MODE_TUP_DPS_GET(var)        WMI_GET_BITS(var, 8, 2)
+#define WMI_UHR_AP_MODE_TUP_DPS_SET(var, val)   WMI_SET_BITS(var, 8, 2, val)
 
-#define WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK(vdev_id, bits) \
-    (((vdev_id) & WMI_UHR_AP_VDEV_ID_MASK) | \
-     (((bits) & WMI_UHR_AP_MODE_TUP_DISABLED_BITS_MASK) << WMI_UHR_AP_MODE_TUP_DISABLED_BITS_SHIFT))
+#define WMI_UHR_AP_MODE_TUP_NPCA_GET(var)       WMI_GET_BITS(var, 10, 2)
+#define WMI_UHR_AP_MODE_TUP_NPCA_SET(var, val)  WMI_SET_BITS(var, 10, 2, val)
 
-/* Set a disable bit (bit := 1) */
-#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET(var, vdev_id, bit)                  \
-    do {                                                                     \
-        if (WMI_MAX_VDEV_CHECK(vdev_id) && (bit) < WMI_UHR_MAX_MODES) {      \
-            A_UINT32 bits = WMI_UHR_AP_MODE_TUP_GET_BITS(var);                 \
-            bits |= (1 << (bit));                                           \
-            (var) = WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK((vdev_id), bits);                 \
-        }                                                                    \
-    } while (0)
+#define WMI_UHR_AP_MODE_TUP_DUO_GET(var)        WMI_GET_BITS(var, 12, 2)
+#define WMI_UHR_AP_MODE_TUP_DUO_SET(var, val)   WMI_SET_BITS(var, 12, 2, val)
 
-/* Clear a disable bit (bit := 0) */
-#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR(var, vdev_id, bit)                  \
-    do {                                                                     \
-        if (WMI_MAX_VDEV_CHECK(vdev_id) && (bit) < WMI_UHR_MAX_MODES) {      \
-            A_UINT32 bits = WMI_UHR_AP_MODE_TUP_GET_BITS(var);                 \
-            bits &= ~(1 << (bit));                                          \
-            (var) = WMI_UHR_AP_VDEV_ID_MODE_TUP_DISABLED_PACK((vdev_id), bits);                 \
-        }                                                                    \
-    } while (0)
+#define WMI_UHR_AP_MODE_TUP_PEDCA_GET(var)      WMI_GET_BITS(var, 14, 2)
+#define WMI_UHR_AP_MODE_TUP_PEDCA_SET(var, val) WMI_SET_BITS(var, 14, 2, val)
 
-/* Read a disable bit (returns 0 or 1) */
-#define WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET(var, bit)                           \
-    (((bit) < WMI_UHR_MAX_MODES) ?                                          \
-     ((WMI_UHR_AP_MODE_TUP_GET_BITS(var) >> (bit)) & 1) : 0)
+#define WMI_UHR_AP_MODE_TUP_DBE_GET(var)        WMI_GET_BITS(var, 16, 2)
+#define WMI_UHR_AP_MODE_TUP_DBE_SET(var, val)   WMI_SET_BITS(var, 16, 2, val)
 
-/* ============================================================================
- *  Per‑MODE Macros to Get/Set/CLR Modes
- * ========================================================================== */
+#define WMI_UHR_AP_MODE_TUP_PUO_GET(var)        WMI_GET_BITS(var, 18, 2)
+#define WMI_UHR_AP_MODE_TUP_PUO_SET(var, val)   WMI_SET_BITS(var, 18, 2, val)
 
-/* NPCA */
-#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_NPCA)
-#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_NPCA)
-#define WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_NPCA)
-
-/* DBE */
-#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DBE)
-#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DBE)
-#define WMI_UHR_AP_MODE_TUP_DBE_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DBE)
-
-/* DPS */
-#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DPS)
-#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DPS)
-#define WMI_UHR_AP_MODE_TUP_DPS_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DPS)
-
-/* DUO */
-#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DUO)
-#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_DUO)
-#define WMI_UHR_AP_MODE_TUP_DUO_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_DUO)
-
-/* PUO */
-#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PUO)
-#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PUO)
-#define WMI_UHR_AP_MODE_TUP_PUO_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_PUO)
-
-/* ELR */
-#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_ELR)
-#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_ELR)
-#define WMI_UHR_AP_MODE_TUP_ELR_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_ELR)
-
-/* PEDCA */
-#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_SET(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_SET((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PEDCA)
-#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_CLR(var, vdev_id) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_CLR((var), (vdev_id), WMI_UHR_AP_MODE_TUP_PEDCA)
-#define WMI_UHR_AP_MODE_TUP_PEDCA_DISABLED_BIT_GET(var) \
-    WMI_UHR_AP_MODE_TUP_DISABLED_BIT_GET((var), WMI_UHR_AP_MODE_TUP_PEDCA)
+#define WMI_UHR_AP_MODE_TUP_ELR_GET(var)        WMI_GET_BITS(var, 20, 2)
+#define WMI_UHR_AP_MODE_TUP_ELR_SET(var, val)   WMI_SET_BITS(var, 20, 2, val)
 
 typedef struct {
     /** TLV tag and len; tag equals
-     * WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_dis_params */
+     * WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tuple_enable_disable_update_params */
     A_UINT32 tlv_header;
     /*
-     * WMI_UHR_AP_MODE_TUP_NPCA/DBE/DPS/DUO/PUO/ELR/PEDCA
+     * WMI_UHR_AP_MODE_TUP_DPS_GET/_NPCA/DBE/DUO/PUO/ELR/PEDCA
      * Modes are defined in WMI_UHR_AP_MODE_TUP
-     * WMI_UHR_AP_MODE_TUP_NPCA_DISABLED_BIT_SET/CLR/GET
+     * WMI_UHR_AP_MODE_TUP_DPS_SET/
      * similarly for DBE/DPS/DUO/PUO/ELR/PEDCA
      */
     union{
-        A_UINT32 vdev_id_mode_tuple_disabled_bits;
+        /*
+         * Bits 0:7   - vdev_id (8 bits)
+         * Bits 8:31  - mode enable/disable/update bitmap
+         *              (24 bits, using 2 bits for each mode)
+         *     WMI_UHR_AP_MODE_TUP_STATE
+         *     WMI_UHR_MAX_MODES
+         *     Bits 8:9      DPS
+         *     Bits 10:11    NPCA
+         *     Bits 12:13    DUO
+         *     Bits 14:15    PEDCA
+         *     Bits 16:17    DBE
+         *     Bits 18:19    PUO
+         *     Bits 20:21    ELR
+         *     Bits 22:31    reserved
+         */
+        A_UINT32 vdev_id_mode_tuple_enable_disable_update_bits;
         struct{
             A_UINT32 vdev_id:8,
-                     mode_tup_disabled_bits:24;
+                     mode_tup_dps_enable_disable_update_bits:   2,
+                     mode_tup_npca_enable_disable_update_bits:  2,
+                     mode_tup_duo_enable_disable_update_bits:   2,
+                     mode_tup_pedca_enable_disable_update_bits: 2,
+                     mode_tup_dbe_enable_disable_update_bits:   2,
+                     mode_tup_puo_enable_disable_update_bits:   2,
+                     mode_tup_elr_enable_disable_update_bits:   2,
+                     reserved:10;
         };
     };
     /* Add any new required fields below */
-} wmi_uhr_ap_mode_tup_dis_params;
+} wmi_uhr_ap_mode_tuple_enable_disable_update_params;
 
 typedef struct {
     /** TLV tag and len; tag equals
@@ -54325,7 +54282,7 @@ typedef struct {
      *   - wmi_uhr_ap_dbe_params
      *   - wmi_uhr_ap_ap_puo_params
      *   - wmi_uhr_ap_elr_reception_params
-     *   - wmi_uhr_ap_mode_tup_dis_params[]
+     *   - wmi_uhr_ap_mode_tuple_enable_disable_update_params[]
      */
 } wmi_vdev_uhr_cu_cmd_fixed_param;
 
@@ -54342,7 +54299,7 @@ typedef struct {
      *   - wmi_uhr_ap_dbe_params[]
      *   - wmi_uhr_ap_ap_puo_params[]
      *   - wmi_uhr_ap_elr_reception_params[]
-     *   - wmi_uhr_ap_mode_tup_dis_params[]
+     *   - wmi_uhr_ap_mode_tuple_enable_disable_update_params[]
      */
 } wmi_pdev_uhr_cu_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ded5778bec4e..aa12b911f0e3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1710
+#define __WMI_REVISION_ 1711
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e3f2797193b29fbff9c32be96d53a5b0fdf30584 Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <prakashp@qti.qualcomm.com>
Date: Tue, 3 Feb 2026 16:45:09 -0800
Subject: [PATCH 144/290] fw-api: hw_headers: Add v2 3181 hw headers for fig

Add v2 3181 hw headers for fig. No other files are changing.

Change-Id: I943b645e1d1a3205b0427e271fe8e0df19e12c50
CRs-Fixed: 4427629
---
 hw/fig/v2/wcss_version.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/fig/v2/wcss_version.h b/hw/fig/v2/wcss_version.h
index 6a417dcd42e5..a543f80cca7c 100644
--- a/hw/fig/v2/wcss_version.h
+++ b/hw/fig/v2/wcss_version.h
@@ -3,4 +3,4 @@
  * SPDX-License-Identifier: ISC
  */
 
-#define WCSS_VERSION 3175
+#define WCSS_VERSION 3181

From 416559764da4f54b62b1a7f0137cc30becd45b93 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 4 Feb 2026 12:02:14 -0800
Subject: [PATCH 145/290] fw-api: CL 31562430 - update fw common interface
 files

Change-Id: I59000166bb75ee84445e338d4a016c52955e3dde
CRs-Fixed: 3830439
---
 fw/htt.h | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 73 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index eda0e62c2f35..021493e8078b 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -278,9 +278,10 @@
  * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def.
  * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO.
  * 3.150 Add htt_reg_write_selection definitions.
+ * 3.151 Add HTT_H2T DAL_MODE_INFO def.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 150
+#define HTT_CURRENT_VERSION_MINOR 151
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -994,6 +995,7 @@ enum htt_h2t_msg_type {
     HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR               = 0x29,
     HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO                    = 0x2a,
     HTT_H2T_MSG_TYPE_AST_INFO                               = 0x2b,
+    HTT_H2T_MSG_TYPE_DAL_MODE_INFO                          = 0x2c,
 
     /* keep this last */
     HTT_H2T_NUM_MSGS
@@ -12424,6 +12426,76 @@ PREPACK struct htt_ast_info_t {
         } while (0)
 
 
+/*
+ * @brief  host -> target HTT_H2T_MSG_TYPE_DAL_MODE_INFO message
+ *
+ * MSG_TYPE => HTT_H2T_MSG_TYPE_DAL_MODE_INFO (0x2C)
+ *
+ *    The message would appear as follows:
+ *    |31                16|15              8|7                 0|
+ *    |--------------------+-----------------+-------------------|
+ *    |       mode         |     pdev_id     |     msg_type      |
+ *    |----------------------------------------------------------|
+ *    |                    write_data_addr_lo                    |
+ *    |----------------------------------------------------------|
+ *    |                    write_data_addr_hi                    |
+ *    |----------------------------------------------------------|
+ *    |                    write_msi_addr_lo                     |
+ *    |----------------------------------------------------------|
+ *    |                    write_msi_addr_hi                     |
+ *    |----------------------------------------------------------|
+ *    |                    write_msi_data                        |
+ *    |----------------------------------------------------------|
+ *
+ * The message is interpreted as follows:
+ * dword0  - b'7:0   - msg_type
+ *           b'15:8  - pdev_id
+ *           b'31:16 - mode
+ * dword1  - b'31:0  - write_data_addr_lo
+ * dword2  - b'31:0  - write_data_addr_hi
+ * dword3  - b'31:0  - write_msi_addr_lo
+ * dword4  - b'31:0  - write_msi_addr_hi
+ * dword5  - b'31:0  - write_msi_data
+ */
+PREPACK struct htt_h2t_msg_dal_mode_info {
+        A_UINT32 msg_type:  8,
+                 pdev_id:   8,
+                 mode:     16;
+        A_UINT32 write_data_addr_lo;
+        A_UINT32 write_data_addr_hi;
+        A_UINT32 write_msi_addr_lo;
+        A_UINT32 write_msi_addr_hi;
+        A_UINT32 write_msi_data;
+} POSTPACK;
+
+#define HTT_H2T_MSG_DAL_MODE_INFO_SZ (sizeof(struct htt_h2t_msg_dal_mode_info))
+
+/* DWORD0 */
+#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M                  0x0000ff00
+#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S                  8
+
+#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_GET(_var) \
+        (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M) >> \
+            HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S)
+#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_SET(_var, _val) \
+        do { \
+            HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID, _val); \
+            ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S)); \
+        } while (0)
+
+#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_M                  0xffff0000
+#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_S                  16
+
+#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_GET(_var) \
+        (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_MODE_M) >> \
+            HTT_H2T_MSG_DAL_MODE_INFO_MODE_S)
+#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_SET(_var, _val) \
+        do { \
+            HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_MODE, _val); \
+            ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_MODE_S)); \
+        } while (0)
+
+
 
 /*=== target -> host messages ===============================================*/
 

From ada83e0f3ce2759766d3b323031ff7a72f82c88f Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 4 Feb 2026 12:04:12 -0800
Subject: [PATCH 146/290] fw-api: CL 31562446 - update fw common interface
 files

Change-Id: Iecd52929276cf9376dc3b699a2f5e50f0e053fed
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 8 ++++----
 fw/wmi_unified.h  | 1 +
 fw/wmi_version.h  | 2 +-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index cb599d519855..f8e83b61f45f 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1573,7 +1573,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info,
-    WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_dis_param,
+    WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_enable_disable_update_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -3099,7 +3099,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX)
 /* NOTE:
  * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID
  * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and
@@ -6195,9 +6195,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
  \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params,  WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
 /* WMI command for unified disconnect cmd */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e1fece5440b0..910980dc7706 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -25825,6 +25825,7 @@ typedef enum event_type_e {
     WOW_P2P_NOA_EVENT,                    /* 32 + 14 */
     WOW_XGAP_EVENT,                       /* 32 + 15 */
     WOW_PAGE_FAULT_EVENT,                 /* 32 + 16 */
+    WOW_ACTION_FRAME_RECV_EVENT,          /* 32 + 17 */
 } WOW_WAKE_EVENT_TYPE;
 
 typedef enum wake_reason_e {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index aa12b911f0e3..657f8a7059c0 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1711
+#define __WMI_REVISION_ 1712
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 83c0d1cc53e8f1956336f744aba433246b1a87d7 Mon Sep 17 00:00:00 2001
From: Rakesh Pillai <pillair@qti.qualcomm.com>
Date: Thu, 5 Feb 2026 03:42:07 -0800
Subject: [PATCH 147/290] fw-api: Add PMM spare registers address related
 header files

Add the PMM spare registers address related HW header
files for FIG v1 and v2.

Change-Id: I266f49b1a2ec6f8ff799a0d3741706ed64880f1f
CRs-Fixed: 4430192
---
 hw/fig/v1/wcss_seq_hwioreg_wifi_top.h | 15 +++++++++++++++
 hw/fig/v2/wcss_seq_hwioreg_wifi_top.h | 15 +++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
 create mode 100644 hw/fig/v2/wcss_seq_hwioreg_wifi_top.h

diff --git a/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h b/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
new file mode 100644
index 000000000000..072ec2ed4af7
--- /dev/null
+++ b/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H
+#define WCSS_SEQ_HWIOREG_WIFI_TOP_H
+
+#include "wcss_seq_hwiobase.h"
+
+#define WFSS_PMM_REG_BASE                                                                                            (WFSS_PMM_BASE      + 0x00000000)
+
+#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x)                                                            ((x) + 0x164)
+
+#endif
diff --git a/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h b/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h
new file mode 100644
index 000000000000..072ec2ed4af7
--- /dev/null
+++ b/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H
+#define WCSS_SEQ_HWIOREG_WIFI_TOP_H
+
+#include "wcss_seq_hwiobase.h"
+
+#define WFSS_PMM_REG_BASE                                                                                            (WFSS_PMM_BASE      + 0x00000000)
+
+#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x)                                                            ((x) + 0x164)
+
+#endif

From ec3873fc344da9ef6bcb1f832fb9ce79fa7e9ea9 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 5 Feb 2026 12:02:22 -0800
Subject: [PATCH 148/290] fw-api: CL 31579265 - update fw common interface
 files

Change-Id: I2cff07cc6d4e6fe6d604123d581022149a448b79
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 29f92c75c981..a1c406b742dc 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -962,7 +962,16 @@ typedef struct {
      * BIT [3 : 3] - is_combined_ul_bsrp_trigger - Flag to indicate if a
      *               given UL BSRP trigger is sent combined as part of
      *               an existing DL/UL data sequence
-     * BIT [31: 4] - reserved
+     * BIT [4 : 4] - is_sta_dps_seq - Flag to indicate if a TX is to a STA with
+     *               active Dynamic Power Save state (DPS)
+     * BIT [5 : 5] - is_allow_comb_sched_cmd - Flag to indicate if a given TX
+     *               is part of a allowed combined sched_cmd sequence
+     * BIT [6 : 6] - is_abort_comb_sched_cmd - Flag to indicate if a given TX
+     *               is part of a aborted combined sched_cmd sequence
+     * BIT [7 : 7] - is_comb_sched_cmd_pending - Flag to indicate if a the
+     *               first sched_cmd of a combined sched_cmd sequence is
+     *               pending in the current ring.
+     * BIT [31: 8] - reserved
      */
     union {
         A_UINT32 reserved__htt_seq_type;
@@ -972,7 +981,10 @@ typedef struct {
                      is_manual_ulofdma_trigger: 1,
                      is_combined_ul_bsrp_trigger: 1,
                      is_sta_dps_seq: 1,
-                     reserved3:     27;
+                     is_allow_comb_sched_cmd: 1,
+                     is_abort_comb_sched_cmd: 1,
+                     is_comb_sched_cmd_pending: 1,
+                     reserved3:     24;
         };
     };
     /* Flag to indicate if the channel chosen is 320_1 / 320_2 */

From 0860650a9a2de5a177e328b8ba9f182b9f28b05f Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 5 Feb 2026 12:04:17 -0800
Subject: [PATCH 149/290] fw-api: CL 31580439 - update fw common interface
 files

Change-Id: I0371168b2bd97ee2b53be02bddb9e042a32ac498
CRs-Fixed: 3830439
---
 fw/htt.h       |  3 +-
 fw/htt_stats.h | 76 +++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 021493e8078b..c5b9e0ac10fa 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -916,7 +916,8 @@ typedef enum {
     HTT_STATS_DPD_HALPHY_TAG                        = 253, /* htt_stats_dpd_halphy_tlv */
     HTT_STATS_DPD_HW_CAL_PARAMS_TAG                 = 254, /* htt_stats_dpd_hw_cal_params_tlv */
     HTT_STATS_DPD_HW_CAL_RESULTS_TAG                = 255, /* htt_stats_dpd_hw_cal_results_tlv */
-
+    HTT_STATS_TX_PDEV_TXOP_DUR_TAG                  = 256, /* htt_stats_tx_pdev_txop_dur_tlv */
+    HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG            = 257, /* htt_stats_sched_txq_combined_seq_state_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 5bcbf328e61e..d744c4cc42e4 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1154,6 +1154,8 @@ typedef enum {
 #define HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST 4
 /* For BE max active seq_ctrl that can be in HWQ */
 #define HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST 2
+#define HTT_PDEV_STATS_TXOP_DUR_HIST_BINS 12
+#define HTT_PDEV_STATS_TXOP_DUR_HIST_INTERVAL_US 1000
 
 typedef enum {
     HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
@@ -5410,6 +5412,60 @@ typedef struct {
 typedef htt_stats_sched_txq_supercycle_trigger_tlv
     htt_sched_txq_supercycle_triggers_tlv_v;
 
+/* htt_tx_pdev_txq_stats_upload_t
+ * Enumerations for specifying which stats to upload in response to
+ * HTT_DBG_PDEV_TXQ_STATS.
+ */
+typedef enum {
+    /* upload all data TXQ stats */
+    HTT_UPLOAD_DATA_TXQ_STATS,
+    /* upload MGMT/TWT TXQ stats */
+    HTT_UPLOAD_MGMT_TWT_TXQ_STATS,
+} htt_tx_pdev_txq_stats_upload_t;
+
+typedef enum {
+    /* Sequence combine successful */
+    HTT_SCHED_COMBINED_SEQ_STATUS_SUCCESS = 0,
+
+    /* Seq combine abort due to no prev sequence */
+    HTT_SCHED_COMBINED_SEQ_STATUS_NO_ACTIVE_PREV_SEQ,
+
+    /* Seq combine abort due to back to back allow flag set */
+    HTT_SCHED_COMBINED_SEQ_STATUS_B2B_ALLOW_FLAG,
+
+    /* combining will be disabled if sounding sequence is to be combined */
+    HTT_SCHED_COMBINED_SEQ_STATUS_SOUNDING_SEQ_ABORT,
+
+    /* Seq combine abort due to seq not constructed */
+    HTT_SCHED_COMBINED_SEQ_STATUS_SEQ_NOT_CONSTRUCTED,
+
+    /* Seq combine abort and subring change */
+    HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_CONSRUCTED,
+
+    /* Seq combine abort and indicate TAC */
+    HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_NOT_CONSTRUCTED,
+
+    /* Seq combine abort and seq restart */
+    HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_POSTED,
+
+    HTT_SCHED_COMBINED_SEQ_STATUS_MAX
+} htt_sched_txq_combined_seq_status_tlv_enum;
+
+#define HTT_SCHED_TXQ_COMBINED_SEQ_STATE_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
+
+/* NOTE: Variable length TLV, use length spec to infer array size */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /**
+     * combined_seq_state counts the number of occurrences of different
+     * reasons for aborting combining two different sequence in TAC
+     * during posting
+     *
+     * Indexed by htt_sched_txq_combined_seq_status_tlv_enum.
+     */
+    HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, combined_seq_state);
+} htt_stats_sched_txq_combined_seq_state_tlv;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     union {
@@ -5629,6 +5685,7 @@ typedef struct {
         htt_stats_sched_txq_supercycle_trigger_tlv
             htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv;
         htt_stats_sched_txq_early_compl_tlv         early_compl_tlv;
+        htt_stats_sched_txq_combined_seq_state_tlv  combined_seq_state_tlv;
     } txq[1];
 } htt_stats_tx_sched_t;
 #endif
@@ -7287,6 +7344,17 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /** tx_txop_dur_hist:
+     * Tx txop duration histogram, which holds the total txop used
+     * under histogram bins of interval 1ms
+     */
+     A_UINT32 tx_su_mdsb_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
+     A_UINT32 tx_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
+     A_UINT32 tx_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
+     A_UINT32 combined_sched_cmd_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
+} htt_stats_tx_pdev_txop_dur_tlv;
 
 #define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M 0x000000ff
 #define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S 0
@@ -7335,7 +7403,7 @@ typedef struct {
     A_UINT32 tx_gi_ext_3[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
     A_UINT32 tx_stbc_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS];
     /* Stats for UHR ELR */
-    A_UINT32 tx_11bn_su_elr; 
+    A_UINT32 tx_11bn_su_elr;
 } htt_stats_tx_pdev_bn_rate_tlv;
 
 
@@ -7354,6 +7422,7 @@ typedef struct {
     htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv;
     htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv;
     htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv;
+    htt_stats_tx_pdev_txop_dur_tlv tx_txop_dur_tlv;
 } htt_tx_pdev_rate_stats_t;
 #endif /* ATH_TARGET */
 
@@ -7836,6 +7905,9 @@ typedef struct {
 
     A_UINT32 ulofdma_implicit_trig_tried;
     A_UINT32 ulofdma_implicit_trig_qos_null;
+
+    /* Txop duration history from 0 to 12 ms with interval of 1000us */
+    A_UINT32 ul_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
 } htt_stats_rx_pdev_ul_trig_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv;
@@ -8161,6 +8233,8 @@ typedef struct {
      * response to basic trigger. Typically a data response is expected.
      */
     A_UINT32 ul_mumimo_basic_trigger_rx_qos_null_only;
+    /* Txop duration history from 0 to 12 ms with interval of 1000us */
+    A_UINT32 ul_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS];
 } htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv

From 7423f0e7f32e546095b526fe803149a906ad97c9 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 5 Feb 2026 12:06:08 -0800
Subject: [PATCH 150/290] fw-api: CL 31580442 - update fw common interface
 files

Change-Id: Ib12f288036e41358979f66e3d0d357255fca91cb
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 39 +++++++++++++++++++
 fw/wmi_unified.h  | 96 +++++++++++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 3 files changed, 132 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index f8e83b61f45f..97e8e5cb089b 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1574,6 +1574,12 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info,
     WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_enable_disable_update_param,
+    WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param,
+    WMITLV_TAG_STRUC_wmi_conc_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2167,6 +2173,9 @@ typedef enum {
     OP(WMI_PDEV_POWER_DATAPATH_STATS_CMDID) \
     OP(WMI_SMD_ROAM_CONFIG_CMDID) \
     OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID) \
+    OP(WMI_SCAN_SUPPRESS_CMDID) \
+    OP(WMI_GET_SCAN_STATS_CMDID) \
+    OP(WMI_PDEV_GET_CONC_INFO_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2521,6 +2530,8 @@ typedef enum {
     OP(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID) \
     OP(WMI_SMD_ROAM_CONFIG_EVENTID) \
     OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID) \
+    OP(WMI_GET_SCAN_STATS_RESP_EVENTID) \
+    OP(WMI_PDEV_GET_CONC_INFO_RESP_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -3935,6 +3946,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_CMDID);
 
 WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_UPDATE_REQUEST_CMDID);
 
+/* suppress scan Cmd */
+#define WMITLV_TABLE_WMI_SCAN_SUPPRESS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param, wmi_scan_suppress_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_SUPPRESS_CMDID);
+
+/* get scan stats Cmd */
+#define WMITLV_TABLE_WMI_GET_SCAN_STATS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param, wmi_get_scan_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_CMDID);
+
 #define WMITLV_TABLE_WMI_SCAN_PROB_REQ_OUI_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, wmi_scan_prob_req_oui_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vendor_oui, vendor_oui, WMITLV_SIZE_VAR)
@@ -3947,6 +3970,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_PROB_REQ_OUI_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID);
 
+/* get concurrency info Cmd */
+#define WMITLV_TABLE_WMI_PDEV_GET_CONC_INFO_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param, wmi_pdev_get_conc_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CONC_INFO_CMDID);
+
 #define WMITLV_TABLE_WMI_CHATTER_ADD_COALESCING_FILTER_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, chatter_pkt_coalescing_filter, coalescing_filter, WMITLV_SIZE_VAR)
@@ -8212,6 +8240,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SSCAN_FW_PARAM_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sscan_evt_message_fixed_param, wmi_sscan_evt_message_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_SSCAN_EVT_MESSAGE_EVENTID);
 
+/* Send scan related stats to host */
+#define WMITLV_TABLE_WMI_GET_SCAN_STATS_RESP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param, wmi_get_scan_stats_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_RESP_EVENTID);
+
 /* Roam capability report event */
 #define WMITLV_TABLE_WMI_ROAM_CAPABILITY_REPORT_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_capability_report_event_fixed_param, wmi_roam_capability_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -8229,6 +8262,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CAPABILITY_REPORT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ctl_buf, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_EVENTID);
 
+/* Send concurrency info to host */
+#define WMITLV_TABLE_WMI_PDEV_GET_CONC_INFO_RESP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param, wmi_pdev_get_conc_info_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_conc_info, conc_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CONC_INFO_RESP_EVENTID);
+
 /* Send Bcn Latency ie related params to host */
 #define WMITLV_TABLE_WMI_VDEV_BCN_LATENCY_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param, wmi_vdev_bcn_latency_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 910980dc7706..0b69486f2118 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -410,6 +410,10 @@ typedef enum {
     WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
     /** Only applicable to DBS capable product */
     WMI_SET_SCAN_DBS_DUTY_CYCLE_CMDID,
+    /** enable/disable any scan request **/
+    WMI_SCAN_SUPPRESS_CMDID,
+    /** get scan stats**/
+    WMI_GET_SCAN_STATS_CMDID,
 
     /* PDEV(physical device) specific commands */
     /** set regulatorty ctl id used by FW to determine the exact ctl power limits */
@@ -626,6 +630,8 @@ typedef enum {
     WMI_PDEV_UHR_CU_CMDID,
     /** WMI cmd used to enable/disable and get power and data path stats */
     WMI_PDEV_POWER_DATAPATH_STATS_CMDID,
+    /** WMI cmd to get the concurrency info for all vdevs within a pdev */
+    WMI_PDEV_GET_CONC_INFO_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -1870,6 +1876,9 @@ typedef enum {
     /** Spectral scan capabilities advertisement */
     WMI_SPECTRAL_CAPABILITIES_EVENTID,
 
+    /** Send scan stats to HOST */
+    WMI_GET_SCAN_STATS_RESP_EVENTID,
+
 
     /* PDEV specific events */
     /** TPC config for the current operating channel */
@@ -2039,6 +2048,8 @@ typedef enum {
      */
     WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */
 
+    /* Event to share the concurrency info to HOST */
+    WMI_PDEV_GET_CONC_INFO_RESP_EVENTID, /* 55 */
 
 
     /***
@@ -7075,6 +7086,37 @@ typedef struct {
     A_UINT32 flags;
 } wmi_scan_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param */
+
+    /** suppress_scan:
+     * set to 0: to enable scan
+     * set to 1: to suppress scan
+     */
+    A_UINT32 suppress_scan;
+    /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */
+    A_UINT32 scan_client_id;
+} wmi_scan_suppress_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param */
+
+    /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */
+    A_UINT32 scan_client_id;
+} wmi_get_scan_stats_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_stats_rsp_fixed_param */
+
+    /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */
+    A_UINT32 scan_client_id;
+    /** scan_count:
+     * Total number of scans triggered/started for a given scan_clnt_id
+     * which is requested by scan stats command
+     */
+    A_UINT32 scan_count;
+} wmi_get_scan_stats_resp_fixed_param;
+
 /* WMI Diag event */
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag is WMITLV_TAG_STRUC_wmi_diag_event_fixed_param */
@@ -8381,6 +8423,48 @@ typedef struct {
     A_UINT32 scan_start;
 } wmi_pdev_scan_cmd;
 
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param */
+
+    A_UINT32 pdev_id;
+} wmi_pdev_get_conc_info_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_conc_info */
+
+    A_UINT32     vdev_id;
+    A_UINT32     type; /* interface type : WMI_VDEV_MODE */
+    wmi_mac_addr bssid;
+    A_UINT32     freq; /* in MHz*/
+    /* rssi value (in dBm) valid for STA vdev, for other INVALID_RSSI */
+    A_INT32      rssi;
+} wmi_conc_info;
+
+typedef enum {
+    WMI_VDEV_MODE_STA      = 0,
+    WMI_VDEV_MODE_SAP      = 1,
+    WMI_VDEV_MODE_MLO_STA  = 2,
+    WMI_VDEV_MODE_MLO_SAP  = 3,
+    WMI_VDEV_MODE_P2P_CLI  = 4,
+    WMI_VDEV_MODE_P2P_GO   = 5,
+    WMI_VDEV_MODE_NAN      = 6,
+    WMI_VDEV_MODE_NDI      = 7,
+
+    WMI_VDEV_MODE_MAX
+} WMI_VDEV_MODE;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param */
+
+    A_UINT32 pdev_id;
+    /*
+     * Following this fixed_param TLV is a variable-length TLV array:
+     * wmi_conc_info conc_info_list[];
+     */
+} wmi_pdev_get_conc_info_resp_fixed_param;
+
+
 /* WMI support for setting ratemask in target */
 
 typedef struct {
@@ -29507,14 +29591,18 @@ typedef enum {
    WMI_LPI_STATUS_MEDIUM_BUSY = 6,
    /** Extscan is the scan client whose scan complete event is triggered */
    WMI_LPI_STATUS_EXTSCAN_CYCLE_AND_SCAN_REQ_COMPLETED = 7,
-} wmi_lpi_staus;
+   /** LPI scan is suspended*/
+   WMI_LPI_STATUS_SCAN_SUSPENDED = 8,
+} wmi_lpi_status;
+/* preserve old name (with typo) as alias for corrected name */
+typedef wmi_lpi_status wmi_lpi_staus;
 
 typedef struct
 {
-    A_UINT32      tlv_header;
-    wmi_lpi_staus status;
+    A_UINT32       tlv_header;
+    wmi_lpi_status status;
     /** Scan requestor ID */
-    A_UINT32      scan_req_id;
+    A_UINT32       scan_req_id;
 }  wmi_lpi_status_event_fixed_param;
 
 typedef struct
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 657f8a7059c0..008f679eb91a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1712
+#define __WMI_REVISION_ 1713
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 26da8275589a0d6dacb627512b64d317ade6654f Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 6 Feb 2026 12:02:01 -0800
Subject: [PATCH 151/290] fw-api: CL 31593469 - update fw common interface
 files

Change-Id: I7ac37216f0a51f1ff79f3a23b86e9de9144db4d2
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index d744c4cc42e4..6765dff1404d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1156,6 +1156,7 @@ typedef enum {
 #define HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST 2
 #define HTT_PDEV_STATS_TXOP_DUR_HIST_BINS 12
 #define HTT_PDEV_STATS_TXOP_DUR_HIST_INTERVAL_US 1000
+#define HTT_PDEV_STATS_MAX_DATA_TID_COUNT 8
 
 typedef enum {
     HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
@@ -1398,6 +1399,8 @@ typedef struct {
     A_UINT32 hw_reaped_sp;
     /** Number of hardware reaped (Tx completed) packets in VLP mode */
     A_UINT32 hw_reaped_vlp;
+    A_UINT32 avg_channel_access_latency_per_ac[HTT_NUM_AC_WMM]; /* usec units */
+    A_UINT32 seq_posted_per_tid[HTT_PDEV_STATS_MAX_DATA_TID_COUNT];
 } htt_stats_tx_pdev_cmn_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;

From 98b64c2aee85346eaa0cc9700021e1cfa1943b67 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 6 Feb 2026 12:03:55 -0800
Subject: [PATCH 152/290] fw-api: CL 31593473 - update fw common interface
 files

Change-Id: Ib1a480abd3ca6df4f2a7a3222d5fe4543ae022a0
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  67 +++++++++++++++---
 fw/wmi_unified.h  | 171 ++++++++++++++++++++++++++++++++++++++++++----
 fw/wmi_version.h  |   2 +-
 3 files changed, 214 insertions(+), 26 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 97e8e5cb089b..2ea898ac3a12 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1576,10 +1576,16 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_enable_disable_update_param,
     WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param,
-    WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param,
-    WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param,
+    WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param,
     WMITLV_TAG_STRUC_wmi_conc_info,
+    WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2175,7 +2181,10 @@ typedef enum {
     OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID) \
     OP(WMI_SCAN_SUPPRESS_CMDID) \
     OP(WMI_GET_SCAN_STATS_CMDID) \
-    OP(WMI_PDEV_GET_CONC_INFO_CMDID) \
+    OP(WMI_SOC_GET_CONC_INFO_CMDID) \
+    OP(WMI_NAN_LOCAL_SCHEDULE_CMDID) \
+    OP(WMI_NAN_PEER_SCHEDULE_CMDID) \
+    OP(WMI_NAN_PEER_PARAMS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2531,7 +2540,10 @@ typedef enum {
     OP(WMI_SMD_ROAM_CONFIG_EVENTID) \
     OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID) \
     OP(WMI_GET_SCAN_STATS_RESP_EVENTID) \
-    OP(WMI_PDEV_GET_CONC_INFO_RESP_EVENTID) \
+    OP(WMI_SOC_GET_CONC_INFO_RESP_EVENTID) \
+    OP(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID) \
+    OP(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID) \
+    OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -3971,9 +3983,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_PROB_REQ_OUI_CMDID);
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID);
 
 /* get concurrency info Cmd */
-#define WMITLV_TABLE_WMI_PDEV_GET_CONC_INFO_CMDID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param, wmi_pdev_get_conc_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
-WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CONC_INFO_CMDID);
+#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param, wmi_soc_get_conc_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_CMDID);
 
 #define WMITLV_TABLE_WMI_CHATTER_ADD_COALESCING_FILTER_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \
@@ -4368,6 +4380,26 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CONFIG_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, wmi_nan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CMDID);
 
+/* NAN local Schedule Command */
+#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, wmi_nan_local_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, committed_channel_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CMDID);
+
+/* NAN Peer Schedule Command */
+#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, wmi_nan_peer_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, committed_channel_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CMDID);
+
+/* NAN Peer Params Command */
+#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param, wmi_nan_peer_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_caps_ie_data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CMDID);
+
 /* NAN Data Get Capabilities Cmd */
 #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX)
@@ -7255,6 +7287,21 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CNF_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, wmi_nan_disable_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_IND_EVENTID);
 
+/* NAN Local Schedule Confirm Event */
+#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param, wmi_nan_local_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID);
+
+/* NAN Peer Schedule Confirm Event */
+#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CNF_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param, wmi_nan_peer_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID);
+
+/* NAN Peer Params Confirm Event */
+#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CNF_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, wmi_nan_peer_params_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CNF_EVENTID);
+
 /* Coex report antenna isolation event */
 #define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -8263,10 +8310,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CAPABILITY_REPORT_EVENTID);
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_EVENTID);
 
 /* Send concurrency info to host */
-#define WMITLV_TABLE_WMI_PDEV_GET_CONC_INFO_RESP_EVENTID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param, wmi_pdev_get_conc_info_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_RESP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param, wmi_soc_get_conc_info_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_conc_info, conc_info, WMITLV_SIZE_VAR)
-WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CONC_INFO_RESP_EVENTID);
+WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_RESP_EVENTID);
 
 /* Send Bcn Latency ie related params to host */
 #define WMITLV_TABLE_WMI_VDEV_BCN_LATENCY_EVENTID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 0b69486f2118..68c93205f158 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -630,8 +630,6 @@ typedef enum {
     WMI_PDEV_UHR_CU_CMDID,
     /** WMI cmd used to enable/disable and get power and data path stats */
     WMI_PDEV_POWER_DATAPATH_STATS_CMDID,
-    /** WMI cmd to get the concurrency info for all vdevs within a pdev */
-    WMI_PDEV_GET_CONC_INFO_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -1546,6 +1544,22 @@ typedef enum {
     WMI_NAN_CONFIG_CMDID,
     /** Command to disable NAN mode */
     WMI_NAN_DISABLE_CMDID,
+    /**
+     * Command to indicate our committed local discovery schedule
+     * (pre NAN datapath/ranging setup etc.) which FW needs to follow.
+     */
+    WMI_NAN_LOCAL_SCHEDULE_CMDID,
+    /**
+     * Command to indicate negotiated committed schedule which FW
+     * has to follow with a given peer.
+     */
+    WMI_NAN_PEER_SCHEDULE_CMDID,
+    /**
+     * Command to indicate negotiated rate control parameters with a
+     * given peer (during NAN datapath/ranging setup or schedule
+     * negotiation etc.).
+     */
+    WMI_NAN_PEER_PARAMS_CMDID,
 
 
     /** Modem power state command */
@@ -1637,6 +1651,8 @@ typedef enum {
      * and specifiy packets of interest for classification.
      */
     WMI_SOC_TX_PACKET_CUSTOM_CLASSIFY_CMDID,
+    /** WMI cmd to get the concurrency info for all vdevs within the target */
+    WMI_SOC_GET_CONC_INFO_CMDID,
 
     /* packet filter commands */
     WMI_PACKET_FILTER_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PKT_FILTER),
@@ -2048,9 +2064,6 @@ typedef enum {
      */
     WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */
 
-    /* Event to share the concurrency info to HOST */
-    WMI_PDEV_GET_CONC_INFO_RESP_EVENTID, /* 55 */
-
 
     /***
      *** add new WMI_PDEV EVENTID defs directly above here,
@@ -2633,6 +2646,12 @@ typedef enum {
     WMI_NAN_DISABLE_CNF_EVENTID,
     /** Event notifying FW triggered NAN disable indication */
     WMI_NAN_DISABLE_IND_EVENTID,
+    /** Confirmation event to NAN local schedule command */
+    WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID,
+    /** Confirmation event to NAN peer schedule command */
+    WMI_NAN_PEER_SCHEDULE_CNF_EVENTID,
+    /* Confirmation event that FW has received WMI_NAN_PEER_PARAMS_CMDID */
+    WMI_NAN_PEER_PARAMS_CNF_EVENTID,
 
     /* Coex Event */
     WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
@@ -2681,6 +2700,8 @@ typedef enum {
     WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SOC),
     WMI_SOC_HW_MODE_TRANSITION_EVENTID,
     WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
+    /* Event to share the concurrency info to HOST */
+    WMI_SOC_GET_CONC_INFO_RESP_EVENTID,
 
     /** Motion Aided WiFi Connectivity (MAWC) events */
     WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MAWC),
@@ -8425,10 +8446,8 @@ typedef struct {
 
 
 typedef struct {
-    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_cmd_fixed_param */
-
-    A_UINT32 pdev_id;
-} wmi_pdev_get_conc_info_cmd_fixed_param;
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param */
+} wmi_soc_get_conc_info_cmd_fixed_param;
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_conc_info */
@@ -8455,14 +8474,13 @@ typedef enum {
 } WMI_VDEV_MODE;
 
 typedef struct {
-    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_conc_info_resp_fixed_param */
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param */
 
-    A_UINT32 pdev_id;
     /*
      * Following this fixed_param TLV is a variable-length TLV array:
      * wmi_conc_info conc_info_list[];
      */
-} wmi_pdev_get_conc_info_resp_fixed_param;
+} wmi_soc_get_conc_info_resp_fixed_param;
 
 
 /* WMI support for setting ratemask in target */
@@ -30993,6 +31011,87 @@ typedef struct {
     A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
 } wmi_nan_disable_cmd_fixed_param;
 
+#define WMI_NAN_SCHED_NOT_AVAIL_SLOT 0xFF
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param */
+
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */
+    /** schedule_chan_bitmap_len:
+     * number of valid bytes (i.e. excluding final alignment-padding)
+     * in the TLV nan_schedule_chan_bitmap[]
+     */
+    A_UINT32 schedule_chan_bitmap_len;
+/*
+ * TLVs following this structure:
+ *
+ * A_UINT8  nan_schedule_chan_bitmap[];
+ *     A mapping of time slots to channel indexes in the schedule's
+ *     committed_channel_list. Each slot lasts 16TUs.
+ *     An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT.
+ * wmi_channel committed_channel_list[];
+ */
+} wmi_nan_local_schedule_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param */
+
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */
+    wmi_mac_addr peer_nmi_addr;
+    /** schedule_chan_bitmap_len:
+     * number of valid bytes (i.e. excluding final alignment-padding)
+     * in the TLV nan_schedule_chan_bitmap[]
+     */
+    A_UINT32 schedule_chan_bitmap_len;
+    A_UINT32 peer_committed_dw;
+    A_UINT32 peer_max_chan_switch;
+/*
+ * TLVs following this structure:
+ *
+ * A_UINT8 nan_schedule_chan_bitmap[]:
+ *     A mapping of time slots to channel indexes in the schedule's
+ *     committed_channel_list. Each slot lasts 16TUs.
+ *     An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT.
+ * wmi_channel committed_channel_list[];
+ */
+} wmi_nan_peer_schedule_cmd_fixed_param;
+
+typedef enum {
+    WMI_NAN_PEER_FLAG_PMF           = 0x01,
+    WMI_NAN_PEER_FLAG_AUTHENTICATED = 0x02,
+    WMI_NAN_PEER_FLAG_ASSOCIATED    = 0x04,
+    WMI_NAN_PEER_FLAG_AUTHORIZED    = 0x08,
+} WMI_NAN_PEER_PARAMS_FLAGS;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param */
+
+    /* Virtual device ID used for NAN operations (either NMI or NDI VDEV) */
+    A_UINT32 vdev_id;
+    /** peer NMI MAC address */
+    wmi_mac_addr peer_nmi_addr;
+    /** peer NDI MAC address */
+    wmi_mac_addr peer_ndi_macaddr;
+    /** peer_flags:
+     * peer station flags, for indicating PMF is enabled,
+     * authorization is done etc..
+     * Possible values are enum WMI_NAN_PEER_PARAMS_FLAGS.
+     */
+    A_UINT32 peer_flags;
+    /** peer_caps_ie_len:
+     * number of valid bytes (i.e. excluding final alignment-padding)
+     * in the TLV peer_caps_ie_data[]
+     */
+    A_UINT32 peer_caps_ie_len;
+/*
+ * TLVs following this structure:
+ *
+ * A_UINT8 peer_caps_ie_data[]:
+ *     HT/VHT/HE/EHT etc. capability IEs (along with header)
+ *     are sent in stream of bytes (ieee80211 protocol order).
+ */
+} wmi_nan_peer_params_cmd_fixed_param;
+
 #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag)      WMI_GET_BITS(flag, 0, 1)
 #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val)
 #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag)      WMI_GET_BITS(flag, 1, 1)
@@ -31141,6 +31240,38 @@ typedef struct {
     A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */
 } wmi_nan_disable_ind_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param */
+
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */
+    /** Status code; 0 indicates NAN local schedule got applied successfully */
+    A_UINT32 status;
+} wmi_nan_local_schedule_cnf_event_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param */
+
+    A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */
+    /** Status code; 0 indicates NAN peer schedule got applied successfully */
+    A_UINT32 status;
+} wmi_nan_peer_schedule_cnf_event_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param */
+
+    /** Virtual device ID used for NDP operations(either NMI or NDI VDEV) */
+    A_UINT32 vdev_id;
+    /** peer NMI MAC address */
+    wmi_mac_addr peer_nmi_addr;
+    /** peer NDI MAC address */
+    wmi_mac_addr peer_ndi_macaddr;
+    /** status:
+     * 0 indicates NDP setup/schedule_negotiation peer params
+     * were applied successfully.
+     */
+    A_UINT32 status;
+} wmi_nan_peer_params_cnf_event_fixed_param;
+
 typedef enum {
     WMI_NDP_BAND_CAP_2GHZ = 0x01,
     WMI_NDP_BAND_CAP_5GHZ = 0x02,
@@ -31188,6 +31319,10 @@ typedef enum {
         WMI_GET_BITS(word32, 0, 16)
 #define WMI_DEVICE_CAPS_SET_MAX_CHAN_SWITCH_TIME(word32, val) \
         WMI_SET_BITS(word32, 0, 16, val)
+#define WMI_DEVICE_CAPS_GET_MAX_FAW_CHAN_PER_PEER(word32) \
+        WMI_GET_BITS(word32, 16, 4)
+#define WMI_DEVICE_CAPS_SET_MAX_FAW_CHAN_PER_PEER(word32, val) \
+        WMI_SET_BITS(word32, 16, 4, val)
 
 typedef struct {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_nan_capabilities */
@@ -31217,9 +31352,12 @@ typedef struct {
         /* Second 32-bit word of device capabilities */
         A_UINT32 device_caps_word1;
         struct {
-            A_UINT32 max_chan_switch_time:16, /* Max channel switch time,
-                                               * in microseconds */
-                     reserved2:           16; /* Reserved bits */
+            A_UINT32
+                /* Max channel switch time, in microseconds */
+                max_chan_switch_time:16,
+                /* Max FAW channels to be allowed for a NDP peer */
+                max_faw_chan_per_peer: 4,
+                reserved2:           12; /* Reserved bits */
         };
     };
 } wmi_nan_capabilities;
@@ -41485,6 +41623,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_UNIFIED_CONNECT_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_LOCAL_SCHEDULE_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_PEER_SCHEDULE_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 008f679eb91a..494adb36c3e1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1713
+#define __WMI_REVISION_ 1714
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 6123108bcf74fa95a30f6b4994a84653d969dd6a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 6 Feb 2026 12:05:45 -0800
Subject: [PATCH 153/290] fw-api: CL 31594124 - update fw common interface
 files

Change-Id: I88557789763f6bb2b004a7d15cb0a7889dc00b39
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 68af4910efa1..cd76e2e6a5a5 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -758,6 +758,13 @@ typedef  enum  {
     /* Service caps related to SMD Roaming - end */
 
     WMI_SERVICE_PEER_METADATA_V2_SUPPORT = 492, /* Support rx peer meta data v2 */
+    /* WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE:
+     * Indicates support to handle roaming triggers while host is doing
+     * the EAPOL process for 4way HS offload disable case.
+     * FW needs to disable the roam triggers except deauth roaming.
+     */
+    WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE = 493,
+
 
     WMI_MAX_EXT2_SERVICE
 

From 31ca6d9fa85cf7dcf84247b08ad2d4b1d49ff56a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 8 Feb 2026 12:02:01 -0800
Subject: [PATCH 154/290] fw-api: CL 31606165 - update fw common interface
 files

Change-Id: I747f3cdadda54c6bf721e05525df40bce279c47a
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  5 +++--
 fw/wmi_unified.h  | 34 ++++++++++++++++++++++++++++++----
 fw/wmi_version.h  |  2 +-
 3 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 2ea898ac3a12..d8766e151ff8 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1586,6 +1586,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_channel,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -4384,14 +4385,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CMDID);
 #define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, wmi_nan_local_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, committed_channel_list, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CMDID);
 
 /* NAN Peer Schedule Command */
 #define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, wmi_nan_peer_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, committed_channel_list, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CMDID);
 
 /* NAN Peer Params Command */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 68c93205f158..be88c0257646 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -23843,7 +23843,10 @@ typedef struct {
  *              is set
  *  BIT 11    : Detect the missing band from BTM request when compared to
  *              roam scan results and consider them as valid candidate
- *  BIT 12-31 : Reserved
+ *  BIT 12    : Defer BTM roam scan if another roam scan is in progress.
+ *              Applicable only when BTM Disassoc imminent and BSS termination
+ *              is not set
+ *  BIT 13-31 : Reserved
  */
 #define WMI_ROAM_BTM_SET_ENABLE(flags, val)                        WMI_SET_BITS(flags, 0, 1, val)
 #define WMI_ROAM_BTM_GET_ENABLE(flags)                             WMI_GET_BITS(flags, 0, 1)
@@ -23863,6 +23866,8 @@ typedef struct {
 #define WMI_ROAM_BTM_GET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags)      WMI_GET_BITS(flags, 10, 1)
 #define WMI_ROAM_BTM_SET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags, val) WMI_SET_BITS(flags, 11, 1, val)
 #define WMI_ROAM_BTM_GET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags)      WMI_GET_BITS(flags, 11, 1)
+#define WMI_ROAM_BTM_SET_DEFER_BTM_SCAN_FLAG(flags, val)           WMI_SET_BITS(flags, 12, 1, val)
+#define WMI_ROAM_BTM_GET_DEFER_BTM_SCAN_FLAG(flags)                WMI_GET_BITS(flags, 12, 1)
 
 
 /** WMI_ROAM_BTM_SET_NON_MATCHING_CNDS_ACTION definition: When BTM candidate is not matched with cache by WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION, determine what to do */
@@ -31013,6 +31018,24 @@ typedef struct {
 
 #define WMI_NAN_SCHED_NOT_AVAIL_SLOT 0xFF
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_channel */
+
+    A_UINT32 chan_freq; /* in MHz */
+    A_UINT32 center_freq1; /* Center frequency 1 in MHz */
+    A_UINT32 center_freq2; /* Center frequency 2 in MHz */
+    /* Channel bandwidth. Possible values are wmi_channel_width */
+    A_UINT32 chan_width;
+    A_UINT32 rx_nss; /* advertised RX NSS */
+    /* chan_entry_fields:
+     * opaque 6-byte bytestream (with a 2-byte alignment suffix)
+     * The host must manually byteswap these bytes within each 4-byte word
+     * if the host's endianness doesn’t match the target’s, to ensure the
+     * network byte order is maintained.
+     */
+    A_UINT8 chan_entry_fields[8];
+} wmi_nan_channel;
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param */
 
@@ -31025,11 +31048,11 @@ typedef struct {
 /*
  * TLVs following this structure:
  *
- * A_UINT8  nan_schedule_chan_bitmap[];
+ * A_UINT8 nan_schedule_chan_bitmap[];
  *     A mapping of time slots to channel indexes in the schedule's
  *     committed_channel_list. Each slot lasts 16TUs.
  *     An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT.
- * wmi_channel committed_channel_list[];
+ * wmi_nan_channel committed_nan_channel_list[];
  */
 } wmi_nan_local_schedule_cmd_fixed_param;
 
@@ -31052,7 +31075,7 @@ typedef struct {
  *     A mapping of time slots to channel indexes in the schedule's
  *     committed_channel_list. Each slot lasts 16TUs.
  *     An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT.
- * wmi_channel committed_channel_list[];
+ * wmi_nan_channel committed_nan_channel_list[];
  */
 } wmi_nan_peer_schedule_cmd_fixed_param;
 
@@ -31089,6 +31112,9 @@ typedef struct {
  * A_UINT8 peer_caps_ie_data[]:
  *     HT/VHT/HE/EHT etc. capability IEs (along with header)
  *     are sent in stream of bytes (ieee80211 protocol order).
+ *     The host must manually byteswap these bytes within each 4-byte word
+ *     if the host's endianness doesn’t match the target’s, to ensure the
+ *     expected byte order is maintained.
  */
 } wmi_nan_peer_params_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 494adb36c3e1..fbc6fec5cc6c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1714
+#define __WMI_REVISION_ 1715
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 08d0784e99c42d301d4aac169cf6e7140529ed3d Mon Sep 17 00:00:00 2001
From: jinguiw <quic_jinguiw@quicinc.com>
Date: Thu, 11 Jul 2024 18:03:15 +0530
Subject: [PATCH 155/290] msm: camera: ope: check cpu buffer offset and cmd buf
 idx

No check for cpu buffer offset, which may lead to out of cpu buffer
map. No check for cmd buffer index, which may lead to out of bound
or negative index. Adding check for cpu buffer map offset and
adding check for cmd buffer index.

CRs-Fixed: 3864084
Change-Id: I39494b0a9f323cb5569d37a0c033b2eaf8fbd32c
Signed-off-by: jinguiw <quic_jinguiw@quicinc.com>
---
 drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
index 64ed8f360348..31cad8f760a8 100644
--- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
+++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
@@ -2192,6 +2192,14 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr,
 						hw_mgr->iommu_hdl);
 					goto end;
 				}
+				if ((len <= frame_process->cmd_buf[i][j].offset) ||
+					(frame_process->cmd_buf[i][j].size <
+					frame_process->cmd_buf[i][j].length) ||
+					((len - frame_process->cmd_buf[i][j].offset) <
+					 frame_process->cmd_buf[i][j].length)) {
+					CAM_ERR(CAM_OPE, "Invalid offset.");
+					return -EINVAL;
+				}
 				cpu_addr = cpu_addr +
 					frame_process->cmd_buf[i][j].offset;
 				CAM_DBG(CAM_OPE, "Hdl %x size %d len %d off %d",
@@ -2240,6 +2248,10 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr,
 				uint32_t s_idx = 0;
 
 				s_idx = cmd_buf->stripe_idx;
+				if (s_idx < 0 || s_idx >= OPE_MAX_STRIPES) {
+					CAM_ERR(CAM_OPE, "Invalid index.");
+					return -EINVAL;
+				}
 				num_cmd_bufs =
 				ope_request->num_stripe_cmd_bufs[i][s_idx];
 

From c74ff3c92db62a2f48db0ca1e7bf26ffdf364112 Mon Sep 17 00:00:00 2001
From: jinguiw <quic_jinguiw@quicinc.com>
Date: Tue, 2 Jul 2024 15:22:37 +0530
Subject: [PATCH 156/290] msm: camera: icp: io buf config num validation

There are only limitations for CAM_BUF_IN and CAM_BUF_OUT in
config validation, but there will be CAM_BUF_IN_OUT type also.
In process io config, both CAM_BUF_OUT and CAM_BUF_IN_OUT types
are in out_map_entries. No limitation for CAM_BUF_IN_OUT will
lead to out of bound for out_map_entries. This change adds check
for num of io config need in out_map_entries to avoid
out of bound risk.

CRs-Fixed: 3857308
Change-Id: I69163a4264d226d617cbe4f37ba1deb4e6434e31
Signed-off-by: jinguiw <quic_jinguiw@quicinc.com>
---
 drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
index 56ebba91e6bf..3889b58679de 100644
--- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
+++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
@@ -4162,7 +4162,8 @@ static bool cam_icp_mgr_is_valid_outconfig(struct cam_packet *packet)
 					packet->io_configs_offset/4);
 
 	for (i = 0 ; i < packet->num_io_configs; i++)
-		if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT)
+		if ((io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) ||
+			(io_cfg_ptr[i].direction == CAM_BUF_IN_OUT))
 			num_out_map_entries++;
 
 	if (num_out_map_entries <= CAM_MAX_OUT_RES) {
@@ -4313,10 +4314,17 @@ static int cam_icp_mgr_process_io_cfg(struct cam_icp_hw_mgr *hw_mgr,
 		if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) {
 			sync_in_obj[j++] = io_cfg_ptr[i].fence;
 			prepare_args->num_in_map_entries++;
-		} else {
+		} else if ((io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) ||
+			(io_cfg_ptr[i].direction == CAM_BUF_IN_OUT)) {
 			prepare_args->out_map_entries[k++].sync_id =
 				io_cfg_ptr[i].fence;
 			prepare_args->num_out_map_entries++;
+		} else {
+			CAM_ERR(CAM_ICP, "dir: %d, max_out:%u, out %u",
+				io_cfg_ptr[i].direction,
+				prepare_args->max_out_map_entries,
+				prepare_args->num_out_map_entries);
+			return -EINVAL;
 		}
 		CAM_DBG(CAM_REQ,
 			"ctx_id: %u req_id: %llu dir[%d]: %u, fence: %u resource_type = %u memh %x",

From 4bc8ff3984e6accb136871b12b7017d0aa943812 Mon Sep 17 00:00:00 2001
From: jinguiw <quic_jinguiw@quicinc.com>
Date: Wed, 31 Jul 2024 15:01:07 +0530
Subject: [PATCH 157/290] msm: camera: sensor: handling condition for random
 read

Get i2c setting count twice in different location for i2c setting,
may lead to out of bound for reg settings. Record i2c setting count
in the first fetch to avoid this risk.

CRs-Fixed: 3885312
Change-Id: I2a81410fecdf41910d7d2eb0daf233621fe0b452
Signed-off-by: jinguiw <quic_jinguiw@quicinc.com>
---
 .../cam_sensor_utils/cam_sensor_util.c                 | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
index fd423ef3da0a..325e52e6a5a2 100644
--- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
+++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
@@ -395,10 +395,11 @@ static int32_t cam_sensor_handle_random_read(
 	struct cam_buf_io_cfg *io_cfg)
 {
 	struct i2c_settings_list *i2c_list;
-	int32_t rc = 0, cnt = 0;
+	int32_t rc = 0, cnt = 0, payload_count = 0;
 
+	payload_count = cmd_i2c_random_rd->header.count;
 	i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings,
-		cmd_i2c_random_rd->header.count);
+		payload_count);
 	if ((i2c_list == NULL) ||
 		(i2c_list->i2c_settings.reg_setting == NULL)) {
 		CAM_ERR(CAM_SENSOR,
@@ -413,7 +414,7 @@ static int32_t cam_sensor_handle_random_read(
 	} else {
 		*cmd_length_in_bytes = sizeof(struct i2c_rdwr_header) +
 			(sizeof(struct cam_cmd_read) *
-			(cmd_i2c_random_rd->header.count));
+			payload_count);
 		i2c_list->op_code = CAM_SENSOR_I2C_READ_RANDOM;
 		i2c_list->i2c_settings.addr_type =
 			cmd_i2c_random_rd->header.addr_type;
@@ -422,8 +423,7 @@ static int32_t cam_sensor_handle_random_read(
 		i2c_list->i2c_settings.size =
 			cmd_i2c_random_rd->header.count;
 
-		for (cnt = 0; cnt < (cmd_i2c_random_rd->header.count);
-			cnt++) {
+		for (cnt = 0; cnt < payload_count; cnt++) {
 			i2c_list->i2c_settings.reg_setting[cnt].reg_addr =
 				cmd_i2c_random_rd->data_read[cnt].reg_data;
 		}

From ba6bfdd6ee634e5b53c23c094d0a0194b278aaee Mon Sep 17 00:00:00 2001
From: Nirmal Abraham <quic_c_nabrah@quicinc.com>
Date: Wed, 26 Jun 2024 18:08:57 +0530
Subject: [PATCH 158/290] msm: camera: common: Add missing put_cpu_buf calls

Add cam_mem_put_cpu_buf calls in error scenarios to avoid
memory leak.

CRs-Fixed: 3866880
Change-Id: I26ee4c58ab88458d109b13a04cfcaea3502b31a3
Signed-off-by: Nirmal Abraham <quic_c_nabrah@quicinc.com>
---
 drivers/cam_isp/cam_isp_context.c                |  6 ++++--
 .../cam_actuator/cam_actuator_core.c             |  4 +++-
 .../cam_csiphy/cam_csiphy_core.c                 |  9 +++++++++
 .../cam_sensor_module/cam_flash/cam_flash_core.c | 16 ++++++++++++----
 drivers/cam_sensor_module/cam_ois/cam_ois_core.c |  5 +++--
 .../cam_sensor/cam_sensor_core.c                 |  4 +++-
 .../cam_sensor_utils/cam_sensor_util.c           |  2 +-
 7 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c
index da0a59be2353..b324b25e1a05 100644
--- a/drivers/cam_isp/cam_isp_context.c
+++ b/drivers/cam_isp/cam_isp_context.c
@@ -4791,8 +4791,10 @@ static int __cam_isp_ctx_config_dev_in_top_state(
 	if ((len < sizeof(struct cam_packet)) ||
 		((size_t)cmd->offset >= len - sizeof(struct cam_packet))) {
 		CAM_ERR(CAM_ISP, "invalid buff length: %zu or offset", len);
-		rc = -EINVAL;
-		goto free_req;
+		spin_lock_bh(&ctx->lock);
+		list_add_tail(&req->list, &ctx->free_req_list);
+		spin_unlock_bh(&ctx->lock);
+		return -EINVAL;
 	}
 
 	remain_len -= (size_t)cmd->offset;
diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c
index 6d3c7a50207b..39241c3e0f4b 100644
--- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c
+++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c
@@ -507,8 +507,10 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl,
 		/* Loop through multiple command buffers */
 		for (i = 0; i < csl_packet->num_cmd_buf; i++) {
 			rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]);
-			if (rc)
+			if (rc) {
+				cam_mem_put_cpu_buf(config.packet_handle);
 				return rc;
+			}
 
 			total_cmd_buf_in_bytes = cmd_desc[i].length;
 			if (!total_cmd_buf_in_bytes)
diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
index 59946e481246..2ec5799e7651 100644
--- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
+++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
@@ -379,6 +379,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		CAM_ERR(CAM_CSIPHY,
 			"Inval cam_packet strut size: %zu, len_of_buff: %zu",
 			 sizeof(struct cam_packet), len);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		rc = -EINVAL;
 		return rc;
 	}
@@ -390,6 +391,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	if (cam_packet_util_validate_packet(csl_packet,
 		remain_len)) {
 		CAM_ERR(CAM_CSIPHY, "Invalid packet params");
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		rc = -EINVAL;
 		return rc;
 	}
@@ -400,6 +402,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 			csl_packet->cmd_buf_offset / 4);
 	else {
 		CAM_ERR(CAM_CSIPHY, "num_cmd_buffers = %d", csl_packet->num_cmd_buf);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		rc = -EINVAL;
 		return rc;
 	}
@@ -407,6 +410,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	rc = cam_packet_util_validate_cmd_desc(cmd_desc);
 	if (rc) {
 		CAM_ERR(CAM_CSIPHY, "Invalid cmd desc ret: %d", rc);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		return rc;
 	}
 
@@ -415,6 +419,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	if (rc < 0) {
 		CAM_ERR(CAM_CSIPHY,
 			"Failed to get cmd buf Mem address : %d", rc);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		return rc;
 	}
 
@@ -422,6 +427,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		(cmd_desc->offset > (len - sizeof(struct cam_csiphy_info)))) {
 		CAM_ERR(CAM_CSIPHY,
 			"Not enough buffer provided for cam_cisphy_info");
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
+		cam_mem_put_cpu_buf(cmd_desc->mem_handle);
 		rc = -EINVAL;
 		return rc;
 	}
@@ -433,6 +440,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	index = cam_csiphy_get_instance_offset(csiphy_dev, cfg_dev->dev_handle);
 	if (index < 0 || index  >= csiphy_dev->session_max_device_support) {
 		CAM_ERR(CAM_CSIPHY, "index in invalid: %d", index);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		cam_mem_put_cpu_buf(cmd_desc->mem_handle);
 		return -EINVAL;
 	}
@@ -443,6 +451,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		CAM_ERR(CAM_CSIPHY,
 			"Wrong configuration lane_cnt: %u",
 			cam_cmd_csiphy_info->lane_cnt);
+		cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle);
 		cam_mem_put_cpu_buf(cmd_desc->mem_handle);
 		return rc;
 	}
diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c
index 029ec542d491..cbe33b043a51 100644
--- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c
+++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c
@@ -1065,9 +1065,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 		/* Loop through multiple command buffers */
 		for (i = 1; i < csl_packet->num_cmd_buf; i++) {
 			rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]);
-			if (rc)
+			if (rc) {
+				cam_mem_put_cpu_buf(config.packet_handle);
 				return rc;
-
+			}
 			total_cmd_buf_in_bytes = cmd_desc[i].length;
 			processed_cmd_buf_in_bytes = 0;
 			if (!total_cmd_buf_in_bytes)
@@ -1278,8 +1279,8 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 			rc = fctrl->func_tbl.apply_setting(fctrl, 1);
 			if (rc) {
 				CAM_ERR(CAM_FLASH, "cannot apply fire settings rc = %d", rc);
-				return rc;
 			}
+			cam_mem_put_cpu_buf(config.packet_handle);
 			return rc;
 		}
 		break;
@@ -1344,8 +1345,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 		goto update_req_mgr;
 	}
 	case CAM_FLASH_PACKET_OPCODE_STREAM_OFF: {
-		if (fctrl->streamoff_count > 0)
+		if (fctrl->streamoff_count > 0) {
+			cam_mem_put_cpu_buf(config.packet_handle);
 			return rc;
+		}
 
 		CAM_DBG(CAM_FLASH, "Received Stream off Settings");
 		i2c_data = &(fctrl->i2c_data);
@@ -1362,6 +1365,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 		if (rc) {
 			CAM_ERR(CAM_FLASH,
 			"Failed in parsing i2c Stream off packets");
+			cam_mem_put_cpu_buf(config.packet_handle);
 			return rc;
 		}
 		break;
@@ -1638,6 +1642,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 		cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr +
 			cmd_desc->offset);
 		if (!cmd_buf) {
+			cam_mem_put_cpu_buf(cmd_desc->mem_handle);
+			cam_mem_put_cpu_buf(config.packet_handle);
 			rc = -EINVAL;
 			return rc;
 		}
@@ -1654,6 +1660,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg)
 				CAM_WARN(CAM_FLASH,
 					"Rxed Flash fire ops without linking");
 				flash_data->cmn_attr.is_settings_valid = false;
+				cam_mem_put_cpu_buf(cmd_desc->mem_handle);
+				cam_mem_put_cpu_buf(config.packet_handle);
 				return -EINVAL;
 			}
 			if (remain_len < sizeof(struct cam_flash_set_on_off)) {
diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
index e62e00d88d27..45a63a9eb9cb 100644
--- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
+++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
@@ -544,9 +544,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		/* Loop through multiple command buffers */
 		for (i = 0; i < csl_packet->num_cmd_buf; i++) {
 			rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]);
-			if (rc)
+			if (rc) {
+				cam_mem_put_cpu_buf(dev_config.packet_handle);
 				return rc;
-
+			}
 			total_cmd_buf_in_bytes = cmd_desc[i].length;
 			if (!total_cmd_buf_in_bytes)
 				continue;
diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
index 999fec038324..a274928c94e3 100644
--- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
+++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c
@@ -556,8 +556,10 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl)
 
 	for (i = 0; i < pkt->num_cmd_buf; i++) {
 		rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]);
-		if (rc)
+		if (rc) {
+			cam_mem_put_cpu_buf(handle);
 			return rc;
+		}
 
 		if (!(cmd_desc[i].length))
 			continue;
diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
index 325e52e6a5a2..4e9fabc0d822 100644
--- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
+++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
@@ -316,12 +316,12 @@ static int32_t cam_sensor_get_io_buffer(
 			 (uint8_t *)buf_addr + io_cfg->offsets[0];
 		i2c_settings->read_buff_len =
 			buf_size - io_cfg->offsets[0];
+		cam_mem_put_cpu_buf(io_cfg->mem_handle[0]);
 	} else {
 		CAM_ERR(CAM_SENSOR, "Invalid direction: %d",
 			io_cfg->direction);
 		rc = -EINVAL;
 	}
-	cam_mem_put_cpu_buf(io_cfg->mem_handle[0]);
 	return rc;
 }
 

From 3b061e5b701448256a1748b73bc8c93cc39723d8 Mon Sep 17 00:00:00 2001
From: chengxue <quic_chengxue@quicinc.com>
Date: Tue, 8 Oct 2024 15:38:01 +0800
Subject: [PATCH 159/290] msm: camera: ois: Copy packet header in kernel

After getting the mapped buffer through cam_mem_get_cpu_buf()
in kernel, userspace is still able to access those buffers.
This change copy ois packet header in kernel to avoid TOCTOU
issue.

CRs-Fixed: 3885381
Change-Id: I185381f81a6a736a029b516dc7f99cce1cac7129
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
---
 .../cam_sensor_module/cam_ois/cam_ois_core.c  | 130 +++++++++---------
 drivers/cam_utils/cam_common_util.c           |  34 +++++
 drivers/cam_utils/cam_common_util.h           |  18 +++
 3 files changed, 115 insertions(+), 67 deletions(-)

diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
index 45a63a9eb9cb..d8766a225046 100644
--- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
+++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c
@@ -493,11 +493,13 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 	size_t                          pkt_len;
 	size_t                          remain_len = 0;
 	struct cam_packet              *csl_packet = NULL;
+	struct cam_packet              *csl_packet_u = NULL;
 	size_t                          len_of_buff = 0;
 	uint32_t                       *offset = NULL, *cmd_buf;
 	struct cam_ois_soc_private     *soc_private =
 		(struct cam_ois_soc_private *)o_ctrl->soc_info.soc_private;
 	struct cam_sensor_power_ctrl_t  *power_info = &soc_private->power_info;
+	size_t                           packet_size = 0;
 
 	ioctl_ctrl = (struct cam_control *)arg;
 	if (copy_from_user(&dev_config,
@@ -519,22 +521,36 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		CAM_ERR(CAM_OIS,
 			"Inval cam_packet strut size: %zu, len_of_buff: %zu",
 			 sizeof(struct cam_packet), pkt_len);
-		cam_mem_put_cpu_buf(dev_config.packet_handle);
-		return -EINVAL;
+		rc = -EINVAL;
+		goto put_ref;
 	}
 
 	remain_len -= (size_t)dev_config.offset;
-	csl_packet = (struct cam_packet *)
+	csl_packet_u = (struct cam_packet *)
 		(generic_pkt_addr + (uint32_t)dev_config.offset);
+	packet_size = csl_packet_u->header.size;
+	if (packet_size <= remain_len) {
+		rc = cam_common_mem_kdup((void **)&csl_packet,
+			csl_packet_u, packet_size);
+		if (rc) {
+			CAM_ERR(CAM_OIS, "Alloc and copy request %lld packet fail",
+				csl_packet_u->header.request_id);
+			goto put_ref;
+		}
+	} else {
+		CAM_ERR(CAM_OIS, "Invalid packet header size %u",
+			packet_size);
+		rc = -EINVAL;
+		goto put_ref;
+	}
 
 	if (cam_packet_util_validate_packet(csl_packet,
 		remain_len)) {
 		CAM_ERR(CAM_OIS, "Invalid packet params");
-		cam_mem_put_cpu_buf(dev_config.packet_handle);
-		return -EINVAL;
+		rc = -EINVAL;
+		goto end;
 	}
 
-
 	switch (csl_packet->header.op_code & 0xFFFFFF) {
 	case CAM_OIS_PACKET_OPCODE_INIT:
 		offset = (uint32_t *)&csl_packet->payload;
@@ -545,9 +561,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		for (i = 0; i < csl_packet->num_cmd_buf; i++) {
 			rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]);
 			if (rc) {
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return rc;
+				CAM_ERR(CAM_OIS, "Invalid cmd desc");
+				goto end;
 			}
+
 			total_cmd_buf_in_bytes = cmd_desc[i].length;
 			if (!total_cmd_buf_in_bytes)
 				continue;
@@ -557,15 +574,14 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			if (rc < 0) {
 				CAM_ERR(CAM_OIS, "Failed to get cpu buf : 0x%x",
 					cmd_desc[i].mem_handle);
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return rc;
+				goto end;
 			}
 			cmd_buf = (uint32_t *)generic_ptr;
 			if (!cmd_buf) {
 				CAM_ERR(CAM_OIS, "invalid cmd buf");
+				rc = -EINVAL;
 				cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return -EINVAL;
+				goto end;
 			}
 
 			if ((len_of_buff < sizeof(struct common_header)) ||
@@ -573,9 +589,9 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				sizeof(struct common_header)))) {
 				CAM_ERR(CAM_OIS,
 					"Invalid length for sensor cmd");
+				rc = -EINVAL;
 				cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return -EINVAL;
+				goto end;
 			}
 			remain_len = len_of_buff - cmd_desc[i].offset;
 			cmd_buf += cmd_desc[i].offset / sizeof(uint32_t);
@@ -588,9 +604,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				if (rc < 0) {
 					CAM_ERR(CAM_OIS,
 					"Failed in parsing slave info");
-					cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-					cam_mem_put_cpu_buf(dev_config.packet_handle);
-					return rc;
+					break;
 				}
 				break;
 			case CAMERA_SENSOR_CMD_TYPE_PWR_UP:
@@ -604,9 +618,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				if (rc) {
 					CAM_ERR(CAM_OIS,
 					"Failed: parse power settings");
-					cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-					cam_mem_put_cpu_buf(dev_config.packet_handle);
-					return rc;
+					break;
 				}
 				break;
 			default:
@@ -624,9 +636,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				if (rc < 0) {
 					CAM_ERR(CAM_OIS,
 					"init parsing failed: %d", rc);
-					cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-					cam_mem_put_cpu_buf(dev_config.packet_handle);
-					return rc;
+					break;
 				}
 			} else if ((o_ctrl->is_ois_calib != 0) &&
 				(o_ctrl->i2c_calib_data.is_settings_valid ==
@@ -643,22 +653,22 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				if (rc < 0) {
 					CAM_ERR(CAM_OIS,
 						"Calib parsing failed: %d", rc);
-					cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
-					cam_mem_put_cpu_buf(dev_config.packet_handle);
-					return rc;
+					break;
 				}
 			}
 			break;
 			}
 			cam_mem_put_cpu_buf(cmd_desc[i].mem_handle);
+
+			if (rc < 0)
+				goto end;
 		}
 
 		if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) {
 			rc = cam_ois_power_up(o_ctrl);
 			if (rc) {
 				CAM_ERR(CAM_OIS, " OIS Power up failed");
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return rc;
+				goto end;
 			}
 			o_ctrl->cam_ois_state = CAM_OIS_CONFIG;
 		}
@@ -715,8 +725,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			CAM_WARN(CAM_OIS,
 				"Not in right state to control OIS: %d",
 				o_ctrl->cam_ois_state);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		offset = (uint32_t *)&csl_packet->payload;
 		offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t));
@@ -729,23 +738,20 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			cmd_desc, 1, NULL);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = cam_ois_apply_settings(o_ctrl, i2c_reg_settings);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "Cannot apply mode settings");
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = delete_request(i2c_reg_settings);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS,
 				"Fail deleting Mode data: rc: %d", rc);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		break;
 	case CAM_OIS_PACKET_OPCODE_READ: {
@@ -757,16 +763,14 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			CAM_WARN(CAM_OIS,
 				"Not in right state to read OIS: %d",
 				o_ctrl->cam_ois_state);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		CAM_DBG(CAM_OIS, "number of I/O configs: %d:",
 			csl_packet->num_io_configs);
 		if (csl_packet->num_io_configs == 0) {
 			CAM_ERR(CAM_OIS, "No I/O configs to process");
 			rc = -EINVAL;
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		INIT_LIST_HEAD(&(i2c_read_settings.list_head));
@@ -779,8 +783,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		if (io_cfg == NULL) {
 			CAM_ERR(CAM_OIS, "I/O config is invalid(NULL)");
 			rc = -EINVAL;
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		offset = (uint32_t *)&csl_packet->payload;
@@ -793,8 +796,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			cmd_desc, 1, &io_cfg[0]);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "OIS read pkt parsing failed: %d", rc);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = cam_sensor_i2c_read_data(
@@ -803,8 +805,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "cannot read data rc: %d", rc);
 			delete_request(&i2c_read_settings);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		if (csl_packet->num_io_configs > 1) {
@@ -814,8 +815,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 				CAM_ERR(CAM_OIS,
 					"write qtimer failed rc: %d", rc);
 				delete_request(&i2c_read_settings);
-				cam_mem_put_cpu_buf(dev_config.packet_handle);
-				return rc;
+				goto end;
 			}
 		}
 
@@ -823,8 +823,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS,
 				"Failed in deleting the read settings");
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		break;
 	}
@@ -834,8 +833,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			CAM_ERR(CAM_OIS,
 				"Not in right state to write time to OIS: %d",
 				o_ctrl->cam_ois_state);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		offset = (uint32_t *)&csl_packet->payload;
 		offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t));
@@ -848,47 +846,45 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg)
 			cmd_desc, 1, NULL);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = cam_ois_update_time(i2c_reg_settings);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "Cannot update time");
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = cam_ois_apply_settings(o_ctrl, i2c_reg_settings);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS, "Cannot apply mode settings");
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 
 		rc = delete_request(i2c_reg_settings);
 		if (rc < 0) {
 			CAM_ERR(CAM_OIS,
 				"Fail deleting Mode data: rc: %d", rc);
-			cam_mem_put_cpu_buf(dev_config.packet_handle);
-			return rc;
+			goto end;
 		}
 		break;
 	}
 	default:
 		CAM_ERR(CAM_OIS, "Invalid Opcode: %d",
 			(csl_packet->header.op_code & 0xFFFFFF));
-		cam_mem_put_cpu_buf(dev_config.packet_handle);
-		return -EINVAL;
+		rc = -EINVAL;
+		goto end;
 	}
 
-	if (!rc) {
-		cam_mem_put_cpu_buf(dev_config.packet_handle);
-		return rc;
-	}
+	if (!rc)
+		goto end;
+
 pwr_dwn:
-	cam_mem_put_cpu_buf(dev_config.packet_handle);
 	cam_ois_power_down(o_ctrl);
+end:
+	cam_common_mem_free(csl_packet);
+put_ref:
+	cam_mem_put_cpu_buf(dev_config.packet_handle);
 	return rc;
 }
 
diff --git a/drivers/cam_utils/cam_common_util.c b/drivers/cam_utils/cam_common_util.c
index 23681509f490..c221741bdeff 100644
--- a/drivers/cam_utils/cam_common_util.c
+++ b/drivers/cam_utils/cam_common_util.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/string.h>
@@ -72,3 +73,36 @@ void cam_common_util_thread_switch_delay_detect(
 	}
 
 }
+
+int cam_common_mem_kdup(void **dst,
+	void *src, size_t size)
+{
+	gfp_t flag = GFP_KERNEL;
+
+	if (!src || !dst || !size) {
+		CAM_ERR(CAM_UTIL, "Invalid params src: %pK dst: %pK size: %u",
+			src, dst, size);
+		return -EINVAL;
+	}
+
+	if (!in_task())
+		flag = GFP_ATOMIC;
+
+	*dst = kzalloc(size, flag);
+	if (!*dst) {
+		CAM_ERR(CAM_UTIL, "Failed to allocate memory with size: %u", size);
+		return -ENOMEM;
+	}
+
+	memcpy(*dst, src, size);
+	CAM_DBG(CAM_UTIL, "Allocate and copy memory with size: %u", size);
+
+	return 0;
+}
+EXPORT_SYMBOL(cam_common_mem_kdup);
+
+void cam_common_mem_free(void *memory)
+{
+	kfree(memory);
+}
+EXPORT_SYMBOL(cam_common_mem_free);
diff --git a/drivers/cam_utils/cam_common_util.h b/drivers/cam_utils/cam_common_util.h
index 867aa5753f5a..8ef0c52f90d8 100644
--- a/drivers/cam_utils/cam_common_util.h
+++ b/drivers/cam_utils/cam_common_util.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_COMMON_UTIL_H_
@@ -85,4 +86,21 @@ uint32_t cam_common_util_remove_duplicate_arr(int32_t *array,
 void cam_common_util_thread_switch_delay_detect(const char *token,
 	ktime_t scheduled_time, uint32_t threshold);
 
+/**
+ * @brief:                 Memory alloc and copy
+ *
+ * @dst:                   Address of destination address of memory
+ * @src:                   Source address of memory
+ * @size:                  Length of memory
+ *
+ * @return                 0 if success in register non-zero if failes
+ */
+int cam_common_mem_kdup(void **dst, void *src, size_t size);
+
+/**
+ * @brief:                 Free the memory
+ *
+ * @memory:                Address of memory
+ */
+void cam_common_mem_free(void *memory);
 #endif /* _CAM_COMMON_UTIL_H_ */

From bca82b35630747e34cbf2a8f830d5ce6216f176c Mon Sep 17 00:00:00 2001
From: Vivek Yadav <viveyada@qti.qualcomm.com>
Date: Tue, 12 Aug 2025 10:58:23 +0530
Subject: [PATCH 160/290] msm: camera: isp: Fix potential illegal access in
 Acquire HW
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix potential illegal acquire_hw memory access due to following
scenario. Even though ioctl is synchronous, the kernel performs
1. copy_from_user(&api_version, ...) — reads just the version.
2. Allocates buffer based on version.
3. copy_from_user(acquire_ptr, ...) — reads the full structure.

If another thread modifies the user-space buffer (cmd->handle)
between steps 1 and 3, the kernel will
* Allocate a buffer for version 1.
* But read data formatted for version 1, by modifying api version v2.
* Call the  isp_ctx: acquire_hw_in_acquired.
* Now even though the allocated strructure version is v1, in
  acquire_hw_in_acquired call to api of version v2 would get invoked.
* Leading to OOB reads/writes.

CRs-Fixed: 4216838
Change-Id: I88d1c76438b56d6ccfa014aa440a536ac5bdd27a
Signed-off-by: Vivek Yadav <viveyada@qti.qualcomm.com>
(cherry picked from commit 55273537c3c23152bba518402a96a86918e3f56c)
---
 drivers/cam_core/cam_node.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/cam_core/cam_node.c b/drivers/cam_core/cam_node.c
index d27bcdd6bf0d..4561aecb6f7e 100644
--- a/drivers/cam_core/cam_node.c
+++ b/drivers/cam_core/cam_node.c
@@ -812,6 +812,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd)
 	}
 	case CAM_ACQUIRE_HW: {
 		uint32_t api_version;
+		uint32_t struct_version;
 		void *acquire_ptr = NULL;
 		size_t acquire_size;
 
@@ -846,6 +847,16 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd)
 		}
 
 		if (api_version == 1) {
+			struct_version =
+				((struct cam_acquire_hw_cmd_v1 *)acquire_ptr)->struct_version;
+			if (struct_version != api_version) {
+				CAM_ERR(CAM_CORE,
+					"Unmatched struct api version %u and struct version %u",
+					api_version, struct_version);
+				rc = -EINVAL;
+				goto acquire_free;
+			}
+
 			rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr);
 			if (rc) {
 				CAM_ERR(CAM_CORE,
@@ -853,6 +864,16 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd)
 				goto acquire_kfree;
 			}
 		} else if (api_version == 2) {
+			struct_version =
+				((struct cam_acquire_hw_cmd_v2 *)acquire_ptr)->struct_version;
+			if (struct_version != api_version) {
+				CAM_ERR(CAM_CORE,
+					"Unmatched struct api version %u and struct version %u",
+					api_version, struct_version);
+				rc = -EINVAL;
+				goto acquire_free;
+			}
+
 			rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr);
 			if (rc) {
 				CAM_ERR(CAM_CORE,

From 7e0e21453804d632bf99d20266e5eadbfd1a9a5b Mon Sep 17 00:00:00 2001
From: Ajith Rajana <rajana@qti.qualcomm.com>
Date: Fri, 5 Sep 2025 23:01:11 +0530
Subject: [PATCH 161/290] msm: camera: isp: Fix potential illegal access in
 Acquire HW. Fix for above

Change-Id: I524598236aec47f3e80ef0325326ee75a809b197
Signed-off-by: Ajith Rajana <rajana@qti.qualcomm.com>
---
 drivers/cam_core/cam_node.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/cam_core/cam_node.c b/drivers/cam_core/cam_node.c
index 4561aecb6f7e..f9fa98fe6c5c 100644
--- a/drivers/cam_core/cam_node.c
+++ b/drivers/cam_core/cam_node.c
@@ -854,7 +854,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd)
 					"Unmatched struct api version %u and struct version %u",
 					api_version, struct_version);
 				rc = -EINVAL;
-				goto acquire_free;
+				goto acquire_kfree;
 			}
 
 			rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr);
@@ -871,7 +871,7 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd)
 					"Unmatched struct api version %u and struct version %u",
 					api_version, struct_version);
 				rc = -EINVAL;
-				goto acquire_free;
+				goto acquire_kfree;
 			}
 
 			rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr);

From 318842dd8ec19515e471a5c322a37dc22f817074 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 10 Feb 2026 12:01:49 -0800
Subject: [PATCH 162/290] fw-api: CL 31620095 - update fw common interface
 files

Change-Id: I7fb665cf3818930ecc74abf538325fd1ae1b24cc
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 16 ++++++++++++++++
 fw/wmi_unified.h  | 31 +++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d8766e151ff8..a2b89b49d08b 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1587,6 +1587,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_channel,
+    WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param,
+    WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2186,6 +2188,7 @@ typedef enum {
     OP(WMI_NAN_LOCAL_SCHEDULE_CMDID) \
     OP(WMI_NAN_PEER_SCHEDULE_CMDID) \
     OP(WMI_NAN_PEER_PARAMS_CMDID) \
+    OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2545,6 +2548,7 @@ typedef enum {
     OP(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID) \
     OP(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID) \
     OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \
+    OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6358,6 +6362,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID);
 
+/* WMI Command for Energy management OEM cmd data */
+#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, wmi_energy_mgmt_oem_data_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8707,6 +8717,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, wmi_smd_roam_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_EVENTID);
 
+/* WMI Command for Energy management OEM cmd data */
+#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param, wmi_energy_mgmt_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index be88c0257646..26d6c7fc8df3 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1837,6 +1837,8 @@ typedef enum {
     WMI_ENERGY_MGMT_PUO_CONFIG_CMDID,
     /** WMI cmd used to control ECO mode config */
     WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID,
+    /** Command to Handle Energy Management OEM's opaque data */
+    WMI_ENERGY_MGMT_OEM_DATA_CMDID,
 
     /** WMI cmd used to set the SMD Roam config */
     WMI_SMD_ROAM_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SMD),
@@ -2827,6 +2829,8 @@ typedef enum {
      * used during SMD Roaming
      */
     WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID,
+
+    WMI_ENERGY_MGMT_OEM_DATA_EVENTID =WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT),
 } WMI_EVT_ID;
 
 /* defines for OEM message sub-types */
@@ -41652,6 +41656,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_NAN_LOCAL_SCHEDULE_CMDID);
         WMI_RETURN_STRING(WMI_NAN_PEER_SCHEDULE_CMDID);
         WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID);
+        WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -54084,6 +54089,32 @@ typedef struct {
     A_UINT32 config;
 } wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; */
+    A_UINT32 tlv_header;
+
+    /* content_type:
+     * This OEM-defined value specifies what kind of Energy Management
+     * data is present in the opaque "data" bytestream TLV.
+     */
+    A_UINT32 content_type;
+    /* num bytes to distinguish data bytes from alignment-padding bytes */
+    A_UINT32 num_bytes_valid;
+} wmi_energy_mgmt_oem_data_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; */
+    A_UINT32 tlv_header;
+
+    /* content_type:
+     * This OEM-defined value specifies what kind of Energy Management
+     * data is present in the opaque "data" bytestream TLV.
+     */
+    A_UINT32 content_type;
+    /* num bytes to distinguish data bytes from alignment-padding bytes */
+    A_UINT32 num_bytes_valid;
+} wmi_energy_mgmt_oem_data_event_fixed_param;
+
 
 /* WMI evt to indicate FW is ready */
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index fbc6fec5cc6c..4b0e15d275a1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1715
+#define __WMI_REVISION_ 1716
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 5d1f89f0279468e3f0fafa30b8d0c69cb12d0b97 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Feb 2026 12:01:47 -0800
Subject: [PATCH 163/290] fw-api: CL 31632679 - update fw common interface
 files

Change-Id: I2d56e071ea5aa71e5b3240317e5d195bce839d98
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 26d6c7fc8df3..ea4ba58fb404 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -18003,6 +18003,7 @@ typedef struct {
      * mlo_ieee_link_id_valid bit set.
      */
     A_UINT32 ieee_link_id;
+    A_UINT32 mlo_vdev_id;
 } wmi_vdev_start_mlo_params;
 
 /* this TLV structure used for passing mlo parameters on vdev stop */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4b0e15d275a1..6d8d9008cdf4 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1716
+#define __WMI_REVISION_ 1717
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From bb4cb8981822e98c5602392d6644bc1a8ff1ab8f Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Feb 2026 12:03:42 -0800
Subject: [PATCH 164/290] fw-api: CL 31633543 - update fw common interface
 files

Change-Id: I7761c49449f56087656de48c4fb6f91e3c6d8a96
CRs-Fixed: 3830439
---
 fw/htt.h | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index c5b9e0ac10fa..03cbc990b3fa 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -22165,7 +22165,10 @@ enum HTT_MSDU_QTYPE {
     HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */
     HTT_MSDU_QTYPE_HI_PRIO,        /* Specifies MSDUQ index used for high priority flow type */
     HTT_MSDU_QTYPE_LO_PRIO,        /* Specifies MSDUQ index used for low priority flow type */
-
+    HTT_MSDU_QTYPE_LATENCY_CRIT_2,
+    HTT_MSDU_QTYPE_LATENCY_CRIT_3,
+    HTT_MSDU_QTYPE_LATENCY_CRIT_4,
+    HTT_MSDU_QTYPE_LATENCY_CRIT_5,
 
     /* New MSDU_QTYPE should be added above this line */
     /*
@@ -22177,7 +22180,19 @@ enum HTT_MSDU_QTYPE {
      * it must regard the unexpected value as a default qtype value,
      * or ignore it.
      */
-    HTT_MSDU_QTYPE_MAX,
+    //HTT_MSDU_QTYPE_MAX,
+/*
+ * TEMPORARY HACK:
+ * The HTT_MSDU_QTYPE_MAX value cannot be modified until a few FW locations
+ * that assume the value of HTT_MSDU_QTYPE_MAX get updated.
+ * In the meantime, provide a temporary HTT_MSDU_QTYPE_MAX_TMP definition
+ * that reflects the extended number of queue types.
+ * After the FW has been updated, the HTT_MSDU_QTYPE_MAX value will also be
+ * updated to reflect the extended number of queue types, and then the
+ * HTT_MSDU_QTYPE_MAX_TMP definition will be removed.
+ */
+    HTT_MSDU_QTYPE_MAX_TMP, /* temporary hack - provide temporary new def */
+    HTT_MSDU_QTYPE_MAX = (HTT_MSDU_QTYPE_LO_PRIO+1), /* temporary hack - retain old value of HTT_MSDU_QTYPE_MAX */
     HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */
 };
 

From b965d2967dd3afe38cd5f8278c071829473c0ed0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Feb 2026 12:05:43 -0800
Subject: [PATCH 165/290] fw-api: CL 31634761 - update fw common interface
 files

Change-Id: I426f137479e44fd543290291671ae1b889f16e1d
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 6765dff1404d..043df2598a57 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -12479,7 +12479,10 @@ typedef struct {
      * tx_power_neg[9]: cnt of PPDUs with tx pwr < -9 dBm
      */
     A_UINT32 tx_power_neg[HTT_MAX_NEGATIVE_POWER_LEVEL];
-    /* Tx Power computed for TPC IE for Beacon and related frames, in dBm */
+    /*
+     * Tx Power computed for TPC IE for Beacon and related frames,
+     * in 0.25 dBm units
+     */
     A_UINT32 tpc_ie_power;
 } htt_stats_phy_tpc_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
@@ -16243,7 +16246,7 @@ typedef struct {
     union {
         struct {
             A_UINT32 freq  : 16, /* in MHz */
-                     power : 16; /* in dBm */
+                     power : 16; /* in 0.25 dBm signed */
         };
         A_UINT32 freq_power_pair;
     };
@@ -16336,7 +16339,7 @@ typedef struct {
     union {
         struct {
             A_INT32 oobe_limit_offset : 16,  /* in MHz */
-                    oobe_limit_psd    : 16;  /* in dBm / MHz */
+                    oobe_limit_psd    : 16;  /* in dBr */
         };
         A_UINT32 offset_mask_pair;
     } oobe_limit[HTT_STATS_REG_OOBE_MAX_BW];

From 10407f99704a6bdfc79a429564a9ace32f020a75 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Feb 2026 12:07:49 -0800
Subject: [PATCH 166/290] fw-api: CL 31636084 - update fw common interface
 files

Change-Id: Id723d0f94cd9c972584737a6d2c43daaf88467af
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 162 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h |   2 +-
 2 files changed, 163 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ea4ba58fb404..61d4a1b0e762 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -39873,6 +39873,8 @@ typedef struct {
         };
         A_UINT32 npca_capability;
     };
+    wmi_ppe_threshold uhr_ppet2G;
+    wmi_ppe_threshold uhr_ppet5G;
 } WMI_MAC_PHY_CAPABILITIES_EXT2;
 
 #define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \
@@ -39935,6 +39937,166 @@ typedef struct {
 #define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value)
 
+/* Bit 8: Partial BW DL MU-MIMO support */
+#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 8, 1)
+#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 8, 1, value)
+
+/* Bit 9: Partial BW UL MU-MIMO support */
+#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 9, 1)
+#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 9, 1, value)
+
+/* Bit 10: COBF support */
+#define WMI_UHRCAP_PHY_COBF_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 10, 1)
+#define WMI_UHRCAP_PHY_COBF_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 10, 1, value)
+
+/* Bit 11: COBF Joint Sounding Support */
+#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 11, 1)
+#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 11, 1, value)
+
+/* Bit 12: COSR Mode 1 Support */
+#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 12, 1)
+#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 12, 1, value)
+
+/* Bit 13: COSR Mode 2 Support */
+#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 13, 1)
+#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 13, 1, value)
+
+/* Bits 14-15: UEQM Tx Max NSS Tx Support */
+#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 14, 2)
+#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 14, 2, value)
+
+/* Bits 16-17:UEQM Rx Max NSS Rx Support */
+#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 16, 2)
+#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 16, 2, value)
+
+/* Bit 18: UEQM LT 242ToneRU support */
+#define WMI_UHRCAP_PHY_UEQM_LT_242TONERU_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 18, 1)
+#define WMI_UHRCAP_PHY_UEQM_LT_242TONERU_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 18, 1, value)
+
+/* Bit 19: DRU DBW 20 PWB 20 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_20_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 19, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_20_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 19, 1, value)
+
+/* Bit 20: DRU DBW 40 PWB 40 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_40_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 20, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_40_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 20, 1, value)
+
+/* Bit 21: DRU DBW 80 PWB 80 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 21, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 21, 1, value)
+
+/* Bit 22: DRU DBW 20 PWB 80 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 22, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 22, 1, value)
+
+/* Bit 23: DRU DBW 40 PWB 80 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 23, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 23, 1, value)
+
+/* Bit 24: DRU DBW 60 PWB 80 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_60_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 24, 1)
+#define WMI_UHRCAP_PHY_DRU_DBW_60_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 24, 1, value)
+
+/* Bit 25: DRU RRU HYBRID support */
+#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 25, 1)
+#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 25, 1, value)
+
+/* Bit 26: 2XLDPC Tx Support */
+#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 26, 1)
+#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 26, 1, value)
+
+/* Bit 27: 2XLDPC Rx Support */
+#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 27, 1)
+#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 27, 1, value)
+
+/* Bit 28: IM Pilots Tx Support */
+#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 28, 1)
+#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 28, 1, value)
+
+/* Bit 29: IM Pilots Rx Support */
+#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 29, 1)
+#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 29, 1, value)
+
+/* Bit 30: MCS 15 Support */
+#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 30, 1)
+#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 30, 1, value)
+
+/* Bit 31: Intermediate MCS Support */
+#define WMI_UHRCAP_PHY_INTERMEDIATE_MCS_SUPPORT_GET(uhr_cap_phy) \
+    WMI_GET_BITS(uhr_cap_phy[0], 31, 1)
+#define WMI_UHRCAP_PHY_INTERMEDIATE_MCS_SUPPORT_SET(uhr_cap_phy, value) \
+    WMI_SET_BITS(uhr_cap_phy[0], 31, 1, value)
+
+/*
+ * ToDo: Bits 32-63
+ */
+
+/*
+ * ToDo: Bits 64-95
+ */
+
+/*
+ * ToDO: Bits 96-127
+ */
+
+/*
+ * ToDo: Bits 128-159
+ */
+
+/*
+ * ToDo: Bits 160-191
+ */
+
+/*
+ * ToDo: Bits 192-223
+ */
+
+/*
+ * ToDo: Bits 224-255
+ */
+
 /****** End of 11BN UHR PHY Capabilities Information field ******/ /* } */
 
 /****** 11BN UHR MAC Capabilities Information field ******/ /* { */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 6d8d9008cdf4..5e15bc07cc4f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1717
+#define __WMI_REVISION_ 1718
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From a539b7b65e94539f7abc12088505c596ab5eb8ed Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 13 Feb 2026 12:06:41 -0800
Subject: [PATCH 167/290] fw-api: CL 31660856 - update fw common interface
 files

Change-Id: I6f5c6d898f56cc3fe5165b1884ed958c582cf428
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 25 +++++++++++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 61d4a1b0e762..5396d0351455 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -39817,6 +39817,16 @@ typedef struct {
     };
 } WMI_MAC_PHY_CAPABILITIES_EXT;
 
+/* WMI Maximum Tx/Rx NSS information */
+#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_SET(param, value) \
+    WMI_SET_BITS(param, 0, 4, value)
+#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_GET(dword) \
+    WMI_GET_BITS(dword, 0, 4)
+
+#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_SET(param, value) \
+    WMI_SET_BITS(param, 4, 4, value)
+#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_GET(dword) \
+    WMI_GET_BITS(dword, 4, 4)
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2 */
@@ -39875,6 +39885,21 @@ typedef struct {
     };
     wmi_ppe_threshold uhr_ppet2G;
     wmi_ppe_threshold uhr_ppet5G;
+
+    /* nss_info:
+     * Bits  3:0  - Maximum suported Tx NSS
+     * Bits  7:4  - Maximum suported Rx NSS
+     * Bits 31:8  - Reserved
+     */
+    union {
+        A_UINT32 nss_info;
+        struct {
+            A_UINT32
+                max_tx_nss: 4,
+                max_rx_nss: 4,
+                reserved2: 24;
+        };
+    };
 } WMI_MAC_PHY_CAPABILITIES_EXT2;
 
 #define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 5e15bc07cc4f..a53be073dbbe 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1718
+#define __WMI_REVISION_ 1719
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 535caccc4664738410850d2e8faa7479029b84f7 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 14 Feb 2026 12:02:08 -0800
Subject: [PATCH 168/290] fw-api: CL 31670248 - update fw common interface
 files

Change-Id: I2bc8edee0ba9b00a0cd2921ff32674d80556b4f4
CRs-Fixed: 3830439
---
 fw/htt.h | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 03cbc990b3fa..0bc94db7feb9 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -279,9 +279,10 @@
  * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO.
  * 3.150 Add htt_reg_write_selection definitions.
  * 3.151 Add HTT_H2T DAL_MODE_INFO def.
+ * 3.152 Add decap_type in htt_rx_peer_metadata_v1b.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 151
+#define HTT_CURRENT_VERSION_MINOR 152
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -21919,10 +21920,10 @@ PREPACK struct htt_rx_peer_metadata_v1a {
  *
  * The following diagram shows the format of the RX PEER METADATA V1B format.
  *
- * |31 29|28   26|25      22|21   14|   13  |12                  0|
- * |--------------------------------------------------------------|
- * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
- * |--------------------------------------------------------------|
+ * |31   |30 29|28   26|25      22|21   14|   13  |12                  0|
+ * |--------------------------------------------------------------------|
+ * |Rsvd2|DECAP|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
+ * |--------------------------------------------------------------------|
  */
 PREPACK struct htt_rx_peer_metadata_v1b {
     A_UINT32
@@ -21931,7 +21932,8 @@ PREPACK struct htt_rx_peer_metadata_v1b {
         vdev_id:         8,
         hw_link_id:      4,
         chip_id:         3,
-        reserved2:       3;
+        decap_type:      2,
+        reserved2:       1;
 } POSTPACK;
 
 #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S    0
@@ -21989,6 +21991,16 @@ PREPACK struct htt_rx_peer_metadata_v1b {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \
     } while (0)
 
+#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S 29
+#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M 0x60000000
+#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M) >> HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S)
+
+#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_SET(_var, _val) \
+    do {                                             \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE, _val);  \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S)); \
+    } while (0)
 
 /*
  * htt_rx_peer_metadata_v2 - HTT RX peer metadata version 2
@@ -22120,6 +22132,9 @@ extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 v
 extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_GET) (A_UINT32 var);
 extern void (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_SET) (A_UINT32 *var, A_UINT32 val);
 
+extern A_UINT32 (*HTT_RX_PEER_META_DATA_DECAP_TYPE_GET) (A_UINT32 var);
+extern void (*HTT_RX_PEER_META_DATA_DECAP_TYPE_SET) (A_UINT32 *var, A_UINT32 val);
+
 
 /*
  * In some systems, the host SW wants to specify priorities between

From 9fa99e78eedcb43c19fc7dbd3a44ae6b6a997ff8 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 14 Feb 2026 12:03:53 -0800
Subject: [PATCH 169/290] fw-api: CL 31670251 - update fw common interface
 files

Change-Id: I7fc0ab189b4b19e8c53d9337c8d704b99633b3b2
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 24 ++++++++++++++++++------
 fw/wmi_version.h  |  2 +-
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a2b89b49d08b..a1414b68c223 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -2598,10 +2598,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID);
  * Any new TLV addition in WMI_PEER_DELETE_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility.
  *
- * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 2 disconnection related
+ * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related
  * cmds:
  *     WMI_PEER_DELETE_CMDID,
- *     WMI_VDEV_STOP_CMDID
+ *     WMI_VDEV_STOP_CMDID,
+ *     WMI_VDEV_DOWN_CMDID
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID);
 
@@ -3914,17 +3915,27 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UP_CMDID);
  * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility.
  *
- * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 2 disconnection related
+ * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related
  * cmds:
  *     WMI_PEER_DELETE_CMDID,
- *     WMI_VDEV_STOP_CMDID
+ *     WMI_VDEV_STOP_CMDID,
+ *     WMI_VDEV_DOWN_CMDID
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOP_CMDID);
 
 /* Vdev down Cmd */
 #define WMITLV_TABLE_WMI_VDEV_DOWN_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
-
+/* NOTE:
+ * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as
+ * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility.
+ *
+ * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related
+ * cmds:
+ *     WMI_PEER_DELETE_CMDID,
+ *     WMI_VDEV_STOP_CMDID,
+ *     WMI_VDEV_DOWN_CMDID
+ */
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DOWN_CMDID);
 
 /* Vdev set param Cmd */
@@ -6273,7 +6284,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, peer_delete_mlo_params, WMITLV_SIZE_VAR) \
  \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, vdev_stop_mlo_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, vdev_stop_mlo_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, vdev_down_fixed_param, WMITLV_SIZE_FIX)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID);
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a53be073dbbe..b9650fdcabcf 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1719
+#define __WMI_REVISION_ 1720
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 083fef0100139b29bebe69b4b76c87671f04344e Mon Sep 17 00:00:00 2001
From: Ajit Vaishya <avaishya@qti.qualcomm.com>
Date: Tue, 20 Jan 2026 14:40:42 +0530
Subject: [PATCH 170/290] qcacld-3.0: Self rsn cap intersect with AP rsn cap

currently self rsn cap intersect with AP rsn cap IE
which is filed in bss desc, but while reading rsn cap
IE from bss desc is getting all Zero's, due to which
self cap also become Zero's.
Fix is read AP rsn cap from negotiated rsn cap of bss
desc which is populate properly and self rsn cap is
filled correctly.

Change-Id: Ia1d9c27e1f3a7528636ab78ebe973090a9ae6f1d
CRs-Fixed: 4423830
---
 core/mac/inc/sir_api.h          | 1 +
 core/sme/src/csr/csr_api_scan.c | 1 +
 core/sme/src/csr/csr_util.c     | 4 ++--
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/core/mac/inc/sir_api.h b/core/mac/inc/sir_api.h
index f13d7eda15bc..1f1ff23d47b4 100644
--- a/core/mac/inc/sir_api.h
+++ b/core/mac/inc/sir_api.h
@@ -786,6 +786,7 @@ struct bss_description {
 #if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD)
 	uint32_t is_single_pmk;
 #endif
+	uint16_t neg_rsn_caps;
 	/* Please keep the structure 4 bytes aligned above the ieFields */
 	uint32_t ieFields[1];
 };
diff --git a/core/sme/src/csr/csr_api_scan.c b/core/sme/src/csr/csr_api_scan.c
index 8ba4ef61b6a1..5ce7d5345138 100644
--- a/core/sme/src/csr/csr_api_scan.c
+++ b/core/sme/src/csr/csr_api_scan.c
@@ -2256,6 +2256,7 @@ static QDF_STATUS csr_fill_bss_from_scan_entry(struct mac_context *mac_ctx,
 
 	bss_desc->beaconInterval = scan_entry->bcn_int;
 	bss_desc->capabilityInfo = scan_entry->cap_info.value;
+	bss_desc->neg_rsn_caps = scan_entry->neg_sec_info.rsn_caps;
 
 	if (WLAN_REG_IS_5GHZ_CH_FREQ(scan_entry->channel.chan_freq) ||
 	    WLAN_REG_IS_6GHZ_CHAN_FREQ(scan_entry->channel.chan_freq))
diff --git a/core/sme/src/csr/csr_util.c b/core/sme/src/csr/csr_util.c
index ecd857bcd604..a92dee201977 100644
--- a/core/sme/src/csr/csr_util.c
+++ b/core/sme/src/csr/csr_util.c
@@ -2603,8 +2603,6 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId,
 	     (mac, pSirBssDesc, &local_ap_ie))))
 		return ie_len;
 
-	/* get AP RSN cap */
-	qdf_mem_copy(&rsn_cap, local_ap_ie->RSN.RSN_Cap, sizeof(rsn_cap));
 	if (!ap_ie && local_ap_ie)
 		/* locally allocated */
 		qdf_mem_free(local_ap_ie);
@@ -2624,6 +2622,8 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId,
 	}
 	self_rsn_cap = (uint16_t)rsn_val;
 
+	/* get AP RSN cap */
+	rsn_cap = pSirBssDesc->neg_rsn_caps;
 	/* If AP is capable then use self capability else set PMF as 0 */
 	if (rsn_cap & WLAN_CRYPTO_RSN_CAP_MFP_ENABLED &&
 	    pProfile->MFPCapable) {

From 745f4a5798e1de8f657df56c1ff8518b2d55256c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 19 Feb 2026 12:02:00 -0800
Subject: [PATCH 171/290] fw-api: CL 31710587 - update fw common interface
 files

Change-Id: Ibfdc8f828f31b790a77e732a36089c2596c8f327
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  7 +++++++
 fw/wmi_unified.h  | 19 +++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a1414b68c223..1c70049595d3 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1589,6 +1589,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_channel,
     WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param,
     WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2189,6 +2190,7 @@ typedef enum {
     OP(WMI_NAN_PEER_SCHEDULE_CMDID) \
     OP(WMI_NAN_PEER_PARAMS_CMDID) \
     OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \
+    OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -6380,6 +6382,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
 
+#define WMITLV_TABLE_WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, wmi_vdev_channel_hopping_schedule_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 5396d0351455..6cce48ae3de7 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -777,6 +777,9 @@ typedef enum {
     /** WMI cmd for UHR critical update */
     WMI_VDEV_UHR_CU_CMDID,
 
+    /** WMI cmd for Channel Hopping Schedule */
+    WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID,
+
 
     /* peer specific commands */
 
@@ -54804,6 +54807,22 @@ typedef struct {
      */
 } wmi_pdev_uhr_cu_event_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /* index of next channel in the channel_list tlvs to visit */
+    A_UINT32 next_channel_index;
+    /* dwell time in TUs to stay on each channel. 1 TU = 1024 usec */
+    A_UINT32 dwell_time_tu;
+    /* Target tsf at which this schedule should start */
+    A_UINT32 target_switch_time_tsf;
+
+    /* This fixed param TLV will be followed by the below TLVs
+     *   - A_UINT32 channel_list[num_chan]; // in MHz
+     */
+} wmi_vdev_channel_hopping_schedule_fixed_param;
 
 typedef enum {
     WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b9650fdcabcf..2c4052b21ff3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1720
+#define __WMI_REVISION_ 1721
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From dcd9c5d1becf7c29b55ccdc02c0dc1db63090915 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 20 Feb 2026 12:01:51 -0800
Subject: [PATCH 172/290] fw-api: CL 31721565 - update fw common interface
 files

Change-Id: I24e160de4e63407d05645ee8ace105bff4167236
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index a1c406b742dc..4e6c719274cd 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -984,7 +984,8 @@ typedef struct {
                      is_allow_comb_sched_cmd: 1,
                      is_abort_comb_sched_cmd: 1,
                      is_comb_sched_cmd_pending: 1,
-                     reserved3:     24;
+                     is_sched_cmd_combined: 1,
+                     reserved3:     23;
         };
     };
     /* Flag to indicate if the channel chosen is 320_1 / 320_2 */

From 444b82090cae9a6c6334aa3995527b0b2debcff0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 20 Feb 2026 12:05:22 -0800
Subject: [PATCH 173/290] fw-api: CL 31721572 - update fw common interface
 files

Change-Id: I33f14280a1bdf8f02b3ffd611382fca12127c158
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6cce48ae3de7..88432900e0f0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10511,6 +10511,9 @@ typedef enum {
      * adaptive early rx is disabled
      */
     WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_EXTRA_SLEEP_SLOP,
+
+    /* Set TAS mode after boot up */
+    WMI_PDEV_PARAM_SET_TAS_MODE,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2c4052b21ff3..b4307eb35ad4 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1721
+#define __WMI_REVISION_ 1722
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3ed66efd33f09e2d933cc35136e3744ed3816c17 Mon Sep 17 00:00:00 2001
From: Nilesh Laad <nlaad@qti.qualcomm.com>
Date: Mon, 9 Feb 2026 12:34:42 +0530
Subject: [PATCH 174/290] disp: msm: dp: handle panel_init for eDP case

Currently, panel_init is getting called redundantly from host_ready
and panel_ready for eDP, causing delay in display to come up.
Remove panel_init call from host_ready to reduce the delay.

Change-Id: I73d59e37df7b9d79f132b684bfb862a90935afd3
Signed-off-by: Nilesh Laad <nlaad@qti.qualcomm.com>
---
 msm/dp/dp_display.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/msm/dp/dp_display.c b/msm/dp/dp_display.c
index 2655f9d236d7..6d9bd658cb8f 100644
--- a/msm/dp/dp_display.c
+++ b/msm/dp/dp_display.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -1249,7 +1249,6 @@ static int dp_display_host_ready(struct dp_display_private *dp)
 	dp->ctrl->abort(dp->ctrl, false);
 
 	dp->aux->init(dp->aux, dp->parser->aux_cfg, skip_op);
-	dp->panel->init(dp->panel, skip_op);
 
 	dp_display_state_add(DP_STATE_READY);
 	/* log this as it results from user action of cable connection */

From 4bfc67b086ae46f1ccd3c39bbd143cb8a0df94d1 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 24 Feb 2026 12:01:53 -0800
Subject: [PATCH 175/290] fw-api: CL 31732804 - update fw common interface
 files

Change-Id: Ica4108d22e8fef4641499e6f103c21bcd4d13638
CRs-Fixed: 3830439
---
 fw/htt.h | 26 +++++++++-----------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 0bc94db7feb9..03bee116c50b 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -22180,6 +22180,9 @@ enum HTT_MSDU_QTYPE {
     HTT_MSDU_QTYPE_USER_SPECIFIED, /* Specifies MSDUQ index used for advertising changeable flow type */
     HTT_MSDU_QTYPE_HI_PRIO,        /* Specifies MSDUQ index used for high priority flow type */
     HTT_MSDU_QTYPE_LO_PRIO,        /* Specifies MSDUQ index used for low priority flow type */
+
+    HTT_MSDU_QTYPE_MAX, /* legacy limit (based on ROM compatibility) */
+
     HTT_MSDU_QTYPE_LATENCY_CRIT_2,
     HTT_MSDU_QTYPE_LATENCY_CRIT_3,
     HTT_MSDU_QTYPE_LATENCY_CRIT_4,
@@ -22187,27 +22190,16 @@ enum HTT_MSDU_QTYPE {
 
     /* New MSDU_QTYPE should be added above this line */
     /*
-     * Below QTYPE_MAX will increase if additional QTYPEs are defined
-     * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in
-     * any host/target message definitions.  The QTYPE_MAX value can
+     * Below QTYPE_MAX_EXT will increase if additional QTYPEs are defined
+     * in the future. Hence HTT_MSDU_QTYPE_MAX_EXT can't be used in
+     * any host/target message definitions.  The QTYPE_MAX_EXT value can
      * only be used internally within the host or within the target.
-     * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX
+     * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX_EXT
      * it must regard the unexpected value as a default qtype value,
      * or ignore it.
      */
-    //HTT_MSDU_QTYPE_MAX,
-/*
- * TEMPORARY HACK:
- * The HTT_MSDU_QTYPE_MAX value cannot be modified until a few FW locations
- * that assume the value of HTT_MSDU_QTYPE_MAX get updated.
- * In the meantime, provide a temporary HTT_MSDU_QTYPE_MAX_TMP definition
- * that reflects the extended number of queue types.
- * After the FW has been updated, the HTT_MSDU_QTYPE_MAX value will also be
- * updated to reflect the extended number of queue types, and then the
- * HTT_MSDU_QTYPE_MAX_TMP definition will be removed.
- */
-    HTT_MSDU_QTYPE_MAX_TMP, /* temporary hack - provide temporary new def */
-    HTT_MSDU_QTYPE_MAX = (HTT_MSDU_QTYPE_LO_PRIO+1), /* temporary hack - retain old value of HTT_MSDU_QTYPE_MAX */
+    HTT_MSDU_QTYPE_MAX_EXT,
+
     HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */
 };
 

From f3231d5e3f761e80658ba57725ddeea78aef9004 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 24 Feb 2026 12:03:42 -0800
Subject: [PATCH 176/290] fw-api: CL 31732805 - update fw common interface
 files

Change-Id: Ic8ca171d1ce232097e9664ca7de25240e7544b57
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  2 ++
 fw/wmi_tlv_defs.h |  7 +++++++
 fw/wmi_unified.h  | 31 +++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index cd76e2e6a5a5..2dd303ea0f86 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -764,6 +764,8 @@ typedef  enum  {
      * FW needs to disable the roam triggers except deauth roaming.
      */
     WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE = 493,
+    /* Indicates FW support for populating vdev operating param stats */
+    WMI_SERVICE_VDEV_OPERATING_PARAMS_EVENT_SUPPORT = 494,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 1c70049595d3..b968e80c46fb 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1590,6 +1590,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param,
     WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2551,6 +2552,7 @@ typedef enum {
     OP(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID) \
     OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \
     OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \
+    OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -8742,6 +8744,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_EVENTID);
 
+/* VDEV current operating params event */
+#define WMITLV_TABLE_WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, wmi_vdev_current_operating_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 88432900e0f0..475dcc6a333a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2163,6 +2163,8 @@ typedef enum {
     WMI_VDEV_UNIFIED_CONNECT_EVENTID,
     /** WMI event for unified disconnect */
     WMI_VDEV_UNIFIED_DISCONNECT_EVENTID,
+    /** WMI event for sending vdev operating params */
+    WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID,
 
     /* peer specific events */
     /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */
@@ -8750,6 +8752,14 @@ typedef struct {
     A_UINT32 sw_retry_th;   /* max retry count per AC base on ac_type for the vdev mentioned in vdev id*/
 } wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param;
 
+typedef enum {
+    /* Set when user forces the chainmask config */
+    WMI_FORCE_CHM_MODE_USER_FORCE      = 0,
+
+    /* Set when there is no user force */
+    WMI_FORCE_CHM_MODE_DEFAULT_CONFIG  = 1,
+} WMI_FORCE_CHM_MODE;
+
 typedef struct {
     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param */
     A_UINT32 tlv_header;
@@ -8792,6 +8802,7 @@ typedef struct {
     A_UINT32 fast_chain_selection;
     /* RSSI delta threshold to determine better chain, units: dB */
     A_UINT32 better_chain_rssi_threshold;
+    A_UINT32 force_mode; /* holds a WMI_FORCE_CHM_MODE enum value */
 } wmi_vdev_chainmask_config_cmd_fixed_param;
 
 /*
@@ -54956,6 +54967,26 @@ typedef struct {
     A_UINT32 status; /** wmi_smd_peer_setup_status_type */
 } wmi_smd_roam_peer_unified_setup_complete_event_fixed_param;
 
+/* vdev operating param flags */
+#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_BW     0x1
+#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_NSS    0x2
+#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_CHAINS 0x4
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param */
+    /* operating_param_flags: holds WMI_VDEV_OPERATING_PARAM_ values */
+    A_UINT32 operating_param_flags;
+    A_UINT32 vdev_id; /* ID of the vdev these data stats are from */
+    /* bw: current operating bandwidth (a wmi_channel_width enum value) */
+    A_UINT32 bw;
+    /* Current operating Tx and Rx NSS */
+    A_UINT32 tx_nss;
+    A_UINT32 rx_nss;
+    /* Current Tx and RX Chains of HW intersected with connection capability */
+    A_UINT32 tx_chains;
+    A_UINT32 rx_chains;
+} wmi_vdev_current_operating_param_event_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b4307eb35ad4..ae2e2c3b153d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1722
+#define __WMI_REVISION_ 1723
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 0fdee8362defb0cb09cce04dc22fe044cbfbf969 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 24 Feb 2026 12:05:50 -0800
Subject: [PATCH 177/290] fw-api: CL 31740103 - update fw common interface
 files

Change-Id: I032f7f06c00a0936b89bbe300fe3c5e317074e99
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  7 +++++++
 fw/wmi_unified.h  | 18 ++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index b968e80c46fb..e98502829dc8 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1591,6 +1591,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2192,6 +2193,7 @@ typedef enum {
     OP(WMI_NAN_PEER_PARAMS_CMDID) \
     OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \
     OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \
+    OP(WMI_TWT_ADD_CH_USAGE_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -6389,6 +6391,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID);
 
+/* WMI Command for start ch usage session */
+#define WMITLV_TABLE_WMI_TWT_ADD_CH_USAGE_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, wmi_ch_usage_add_dialog_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_TWT_ADD_CH_USAGE_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 475dcc6a333a..48fef9d4d3fd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1721,6 +1721,7 @@ typedef enum {
     WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID, /* XPAN TWT */
     WMI_VDEV_GET_TWT_SESSION_STATS_INFO_CMDID,
     WMI_TWT_VDEV_CONFIG_CMDID,
+    WMI_TWT_ADD_CH_USAGE_CMDID,
 
     /** WMI commands related to motion detection **/
     WMI_MOTION_DET_CONFIG_PARAM_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MOTION_DET),
@@ -41862,6 +41863,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_NAN_PEER_SCHEDULE_CMDID);
         WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID);
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
+        WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -43485,6 +43487,22 @@ typedef struct {
     A_UINT32 client_id_bitmask;
 } wmi_wlm_config_cmd_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    wmi_mac_addr peer_macaddr;
+    A_UINT32 responder_pm_mode;
+    A_UINT32 negotiation_type;
+    A_UINT32 twt_request;
+    A_UINT32 twt_setup_cmd;
+    A_UINT32 is_triggered;
+    A_UINT32 flow_type;
+    A_UINT32 wake_interval_exp;
+    A_UINT32 twt_protection;
+    A_UINT32 nominal_min_wake_duration;
+    A_UINT32 wake_interval_mantisa;
+} wmi_ch_usage_add_dialog_cmd_fixed_param;
+
 /* Broadcast TWT enable/disable for both REQUESTER and RESPONDER */
 #define TWT_EN_DIS_FLAGS_GET_BTWT(flag)         WMI_GET_BITS(flag, 0, 1)
 #define TWT_EN_DIS_FLAGS_SET_BTWT(flag, val)    WMI_SET_BITS(flag, 0, 1, val)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ae2e2c3b153d..6901e43f9523 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1723
+#define __WMI_REVISION_ 1724
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 069338b12768f4514935d6c22fb8c7f877e21599 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 26 Feb 2026 12:01:50 -0800
Subject: [PATCH 178/290] fw-api: CL 31823686 - update fw common interface
 files

Change-Id: I6b24fe0e677b2d52218101de33dfb7126044ebdd
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 16 ++++++++--------
 fw/wmi_version.h |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 48fef9d4d3fd..eb6f521eb0e0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -11609,7 +11609,7 @@ typedef enum {
 } MCAST_BCAST_RATE_ID;
 
 typedef struct {
-    MCAST_BCAST_RATE_ID rate_id;
+    A_UINT32 rate_id; /* MCAST_BCAST_RATE_ID */
     A_UINT32 rate;
 } mcast_bcast_rate;
 
@@ -20751,7 +20751,7 @@ typedef struct {
     /** requestor id that requested the VDEV start request */
     A_UINT32 requestor_id;
     /* Respose of Event type START/RESTART */
-    WMI_START_EVENT_PARAM resp_type;
+    A_UINT32 resp_type; /* WMI_START_EVENT_PARAM */
     /** status of the response */
     A_UINT32 status;
     /** Vdev chain mask */
@@ -29645,10 +29645,10 @@ typedef wmi_lpi_status wmi_lpi_staus;
 
 typedef struct
 {
-    A_UINT32       tlv_header;
-    wmi_lpi_status status;
+    A_UINT32 tlv_header;
+    A_UINT32 status; /* wmi_lpi_status */
     /** Scan requestor ID */
-    A_UINT32       scan_req_id;
+    A_UINT32 scan_req_id;
 }  wmi_lpi_status_event_fixed_param;
 
 typedef struct
@@ -38941,7 +38941,7 @@ typedef enum {
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param */
-    wmi_wlan_stats_id stats_id;
+    A_UINT32 stats_id; /* wmi_wlan_stats_id */
 } wmi_request_wlan_stats_cmd_fixed_param;
 
 typedef enum {
@@ -44337,7 +44337,7 @@ typedef enum {
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params */
     A_UINT32 pdev_id;   /* ID of pdev to which the scaling parameters are to be applied */
-    WMI_SPECTRAL_SCALING_FORMULA_ID formula_id; /* Represets the formula to be used */
+    A_UINT32 formula_id; /* WMI_SPECTRAL_SCALING_FORMULA_ID: Represents the formula to be used */
     A_UINT32 low_level_offset; /* low level offset for fine tuning the scaling factor based on RSSI and AGC gain */
     A_UINT32 high_level_offset; /* high level offset for fine tuning the scaling factor based on RSSI and AGC gain */
     A_UINT32 rssi_thr; /* RSSI threshold to be used to adjust the inband power of the given spectral report */
@@ -53896,7 +53896,7 @@ typedef struct {
 
 
 typedef struct {
-    wmi_channel_width width;
+    A_UINT32 width;             /* wmi_channel_width */
     A_UINT32 center_frequency0; /* Frequency value in MHz */
     A_UINT32 center_frequency1; /* Frequency value in MHz */
     A_UINT32 primary_frequency; /* Frequency value in MHz */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 6901e43f9523..1a4cb6a088db 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1724
+#define __WMI_REVISION_ 1725
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From a658a3e851edab72c2c2e823f7e0b8d6e9dcb00b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 26 Feb 2026 12:05:45 -0800
Subject: [PATCH 179/290] fw-api: CL 31823693 - update fw common interface
 files

Change-Id: Id33fe14e75f68143e9001cf77cb8d369dab673c2
CRs-Fixed: 3830439
---
 fw/htt.h       |  2 ++
 fw/htt_stats.h | 87 +++++++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 84 insertions(+), 5 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 03bee116c50b..87efcf7a49b3 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -919,6 +919,8 @@ typedef enum {
     HTT_STATS_DPD_HW_CAL_RESULTS_TAG                = 255, /* htt_stats_dpd_hw_cal_results_tlv */
     HTT_STATS_TX_PDEV_TXOP_DUR_TAG                  = 256, /* htt_stats_tx_pdev_txop_dur_tlv */
     HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG            = 257, /* htt_stats_sched_txq_combined_seq_state_tlv */
+    HTT_STATS_CTL_TAG                               = 258, /* htt_stats_ctl_tlv */
+    HTT_STATS_ENHANCED_CTL_TAG                      = 259, /* htt_stats_enhanced_ctl_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 043df2598a57..a20cd8759a36 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -916,12 +916,17 @@ enum htt_dbg_ext_stats_type {
      *     RESP Tags:
      *       - htt_stats_regdb_ctry_tlv
      *       - htt_stats_regdb_regdomain_tlv * n (based on config_param1)
-     * else if(subtype == HTT_STATS_REGULATORY_SUBTYPE_6GHZ):
+     * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_6GHZ):
      *     no params
      *     RESP Tags:
      *       - htt_stats_reg_6g_tlv
      *       - htt_stats_reg_6g_ch_power_info_tlv * n
      *       - htt_stats_reg_6g_oobe_tlv
+     * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_CTL):
+     *     no params
+     *     RESP Tags:
+     *       - htt_stats_ctl_tlv
+     *       - htt_stats_enhanced_ctl_tlv
      */
     HTT_DBG_EXT_STATS_REGULATORY = 83,
 
@@ -15957,6 +15962,7 @@ typedef struct {
 typedef enum {
     HTT_STATS_REGULATORY_SUBTYPE_REGDB = 0,
     HTT_STATS_REGULATORY_SUBTYPE_6GHZ  = 1,
+    HTT_STATS_REGULATORY_SUBTYPE_CTL   = 2,
     HTT_STATS_REGULATORY_SUBTYPE_MAX
 } htt_stats_regulatory_subtype_t;
 
@@ -16112,10 +16118,10 @@ typedef struct {
     A_UINT32      rd_type; /* enum htt_stats_regulatory_rd_type */
     union {
         struct {
-            A_UINT32 ctl_region : 8, /* enum RegdbCtl */
-                     cca_region : 8, /* enum CCA_REGION_MAP */
-                     dfs_region : 8, /* enum WMI_REG_DFS_REGION */
-                     rsvd       : 8;
+            A_UINT32 ctl_region       : 8, /* enum RegdbCtl */
+                     cca_region       : 8, /* enum CCA_REGION_MAP */
+                     dfs_region       : 8, /* enum WMI_REG_DFS_REGION */
+                     domain_ctl_index : 8;
         };
         A_UINT32 ctl_cca_dfs;
     };
@@ -16150,6 +16156,12 @@ typedef struct {
 #define HTT_STATS_REGDB_REGDOMAIN_SET_DFS_REGION(word,value) \
     HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
 
+#define HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) \
+    HTT_STATS_GET_FIELD(0xFF000000, 24, (word))
+#define HTT_STATS_REGDB_REGDOMAIN_SET_DOMAIN_CTL_INDEX(word,value) \
+    HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
+
+
 #define HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
 #define HTT_STATS_REGDB_REGDOMAIN_SET_NUM_RULES(word,value) \
@@ -16355,6 +16367,71 @@ typedef struct {
 #define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)];
+    union {
+        struct {
+            A_UINT32
+                /** To indicate Reg rule Index picked from Reg rules */
+                regRuleIndex:16,
+                /** To indicate Power rule Index picked from Reg rules */
+                powerRuleIndex:8,
+                reserved:8;
+        };
+        A_UINT32 ctl_args;
+    };
+} htt_stats_ctl_tlv;
+
+#define HTT_STATS_CTL_GET_REG_RULE_INDEX(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_CTL_SET_REG_RULE_INDEX(word,value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+#define HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) \
+    HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+#define HTT_STATS_CTL_SET_POWER_RULE_INDEX(word,value) \
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
+
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    union {
+        struct {
+            A_UINT32
+                /** To indicate enablement of enhanced CTL */
+                enhancedCtlEnable:1,
+                rsvd:7,
+                domainCtlIndex:8, /** Domain CTL Index */
+                array_gain_cap_ctlRegion:8, /** Array gain CapCTLregion */
+                exceptionCtlRegion:8; /** Exception CTL region */
+        };
+        A_UINT32 enhanced_ctl_args;
+    };
+} htt_stats_enhanced_ctl_tlv;
+
+#define HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) \
+    HTT_STATS_GET_FIELD(0x00000001, 0, (word))
+#define HTT_STATS_ENHANCED_CTL_SET_ENHANCED_CTL_ENABLE(word,value) \
+    HTT_STATS_SET_FIELD(0x00000001, 0, (word), (value))
+
+#define HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) \
+    HTT_STATS_GET_FIELD(0x0000FF00, 8, (word))
+#define HTT_STATS_ENHANCED_CTL_SET_DOMAIN_CTL_INDEX(word,value) \
+    HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value))
+
+#define HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) \
+    HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+#define HTT_STATS_ENHANCED_CTL_SET_ARRAY_GAIN_CAP_CTL_REGION(word,value) \
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
+
+#define HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) \
+    HTT_STATS_GET_FIELD(0xFF000000, 24, (word))
+#define HTT_STATS_ENHANCED_CTL_SET_EXCEPTION_CTL_REGION(word,value) \
+    HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
+
+
 /*======================= End Regulatory stats ==================== } */
 
 /*

From 88442b3fac28396ba1bd1cd8b89a922ef52e1ec0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 27 Feb 2026 12:02:06 -0800
Subject: [PATCH 180/290] fw-api: CL 31837430 - update fw common interface
 files

Change-Id: I986ca995c22f3f9af2cb781891c3161edc20606d
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_version.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 2dd303ea0f86..5f44def7f263 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -766,6 +766,7 @@ typedef  enum  {
     WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE = 493,
     /* Indicates FW support for populating vdev operating param stats */
     WMI_SERVICE_VDEV_OPERATING_PARAMS_EVENT_SUPPORT = 494,
+    WMI_SERVICE_SUPPORT_WOW_OLE_DAL = 495,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1a4cb6a088db..41ee1707ba12 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1725
+#define __WMI_REVISION_ 1726
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f73b7dc01af6859d130539ac84de07a81ad7d36b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 28 Feb 2026 12:04:34 -0800
Subject: [PATCH 181/290] fw-api: CL 31845524 - update fw common interface
 files

Change-Id: I5f6d9fc99446e7bfaf132f723898d9c9876c9e26
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 15 ++++++++++++
 fw/wmi_unified.h  | 62 ++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 76 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index e98502829dc8..396962c2b3d6 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1592,6 +1592,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2194,6 +2196,7 @@ typedef enum {
     OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \
     OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \
     OP(WMI_TWT_ADD_CH_USAGE_CMDID) \
+    OP(WMI_COEX_GET_POLICY_STATS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2555,6 +2558,7 @@ typedef enum {
     OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \
     OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \
     OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \
+    OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6396,6 +6400,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, wmi_ch_usage_add_dialog_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_TWT_ADD_CH_USAGE_CMDID);
 
+/* WMI Command to request CoEx Policy Stats data */
+#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, wmi_coex_policy_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8756,6 +8765,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, wmi_vdev_current_operating_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID);
 
+/* WMI Event to provide CoEx Policy Stats data */
+#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param, wmi_coex_policy_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index eb6f521eb0e0..558c2ef46b90 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1578,6 +1578,7 @@ typedef enum {
     WMI_TAS_POWER_HISTORY_CMDID,
     WMI_ESL_EGID_CMDID,
     WMI_COEX_MULTIPLE_CONFIG_CMDID,
+    WMI_COEX_GET_POLICY_STATS_CMDID,
 
     /**
      *  OBSS scan offload enable/disable commands
@@ -2667,6 +2668,7 @@ typedef enum {
     /** Dedicated BT Antenna Mode (DBAM) complete event */
     WMI_COEX_DBAM_COMPLETE_EVENTID,
     WMI_TAS_POWER_HISTORY_EVENTID,
+    WMI_COEX_GET_POLICY_STATS_EVENTID,
 
     /* LPI Event */
     WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI),
@@ -28259,9 +28261,66 @@ typedef enum WLAN_COEX_EVENT {
 
 typedef struct {
     A_UINT32 tlv_header;
-    A_UINT32 coex_profile_evt; //uses the enum values from WLAN_COEX_EVENT
+    A_UINT32 coex_profile_evt; /* uses the enum values from WLAN_COEX_EVENT */
 } wmi_coex_bt_activity_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header;
+} wmi_coex_policy_stats_cmd_fixed_param;
+
+#define WMI_COEX_POLICY_STATS_GET_BTC_STATE(coex_stats) \
+    WMI_GET_BITS(coex_stats, 0, 2)
+#define WMI_COEX_POLICY_STATS_SET_BTC_STATE(coex_stats, value) \
+    WMI_SET_BITS(coex_stats, 0, 2, value)
+
+#define WMI_COEX_POLICY_STATS_GET_UWB_STATE(coex_stats) \
+    WMI_GET_BITS(coex_stats, 2, 1)
+#define WMI_COEX_POLICY_STATS_SET_UWB_STATE(coex_stats, value) \
+    WMI_SET_BITS(coex_stats, 2, 1, value)
+
+#define WMI_COEX_POLICY_STATS_GET_MWS_STATE(coex_stats) \
+    WMI_GET_BITS(coex_stats, 3, 1)
+#define WMI_COEX_POLICY_STATS_SET_MWS_STATE(coex_stats, value) \
+    WMI_SET_BITS(coex_stats, 3, 1, value)
+
+#define WMI_COEX_POLICY_STATS_GET_OCS_ALGO_DC(coex_stats) \
+    WMI_GET_BITS(coex_stats, 8, 8)
+#define WMI_COEX_POLICY_STATS_SET_OCS_ALGO_DC(coex_stats, value) \
+    WMI_SET_BITS(coex_stats, 8, 8, value)
+
+#define WMI_COEX_POLICY_STATS_GET_OCS_NON_WLAN_DC(coex_stats) \
+    WMI_GET_BITS(coex_stats, 16, 8)
+#define WMI_COEX_POLICY_STATS_SET_OCS_NON_WLAN_DC(coex_stats, value) \
+    WMI_SET_BITS(coex_stats, 16, 8, value)
+
+typedef struct {
+    A_UINT32 tlv_header;
+    A_UINT32 mon_period; /* milliseconds units */
+    /* Following is the definition for bitfields within the coex_stats word:
+     * bits 1:0   --> Indicates BTC_STATE (0 - Freerun, 1 - OCS, 3 - Inactive).
+     * bit 2      --> Indicates UWB_STATE (0 - Inactive, 1 - Active conflict).
+     * bit 3      --> Indicates MWS_STATE (0 - Inactive, 1 - Active conflict).
+     * bits 15:8  --> Indicates percentage of the time coex chose OCS policy.
+     *                (Ranges from 0 to 100.)
+     * bits 23:16 --> Indicates percentage of the time DUT is off channel due
+     *                to OCS policy. (Ranges from 0 to 100.)
+     */
+    union {
+        A_UINT32 coex_stats;
+        struct {
+            A_UINT32 btc_state: 2,       /* bits 1:0 */
+                     uwb_state: 1,       /* bit 2 */
+                     mws_state: 1,       /* bit 3 */
+                     reserved1: 4,       /* bits 7:4 */
+                     ocs_algo_dc: 8,     /* bits 15:8 */
+                     ocs_non_wlan_dc: 8, /* bits 23:16 */
+                     reserved2: 8;       /* bits 31:24 */
+        };
+    };
+    A_UINT32 num_data_bytes;
+} wmi_coex_policy_stats_event_fixed_param;
+
+
 enum wmm_ac_downgrade_policy {
     WMM_AC_DOWNGRADE_DEPRIO,
     WMM_AC_DOWNGRADE_DROP,
@@ -41864,6 +41923,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID);
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
         WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID);
+        WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";

From 820bbc90d002a59dd4f6b4dbd3bdbc7fe42bf00b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 3 Mar 2026 12:02:09 -0800
Subject: [PATCH 182/290] fw-api: CL 31863503 - update fw common interface
 files

Change-Id: I036cd9e0fc2d47b4ae73168d069a031cd70fa647
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 28 ++++++++++++++--------------
 fw/wmi_version.h |  2 +-
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 558c2ef46b90..a25d59332a71 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -20624,46 +20624,46 @@ typedef enum {
 
 /* commands for 11ax TXBF capabilities */
 
-#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS((x,0,1)
+#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS(x,0,1)
 #define WMI_TXBF_CONF_11AX_SU_TX_BFER_SET(x,z)  WMI_SET_BITS(x,0,1,z)
 
-#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS((x,1,1)
+#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS(x,1,1)
 #define WMI_TXBF_CONF_11AX_SU_TX_BFEE_SET(x,z) WMI_SET_BITS(x,1,1,z)
 
-#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS((x,2,1)
+#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS(x,2,1)
 #define WMI_TXBF_CONF_11AX_MU_TX_BFER_SET(x,z)  WMI_SET_BITS(x,2,1,z)
 
-#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS((x,3,3)
+#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS(x,3,3)
 #define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,3,3,z)
 
-#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS((x,6,3)
+#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS(x,6,3)
 #define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,6,3,z)
 
-#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS((x,9,3)
+#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS(x,9,3)
 #define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_SET(x,z) WMI_SET_BITS(x,9,3,z)
 
-#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS((x,12,3)
+#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS(x,12,3)
 #define WMI_TXBF_CONF_11AX_NSTS_GT_80_SET(x,z) WMI_SET_BITS(x,12,3,z)
 
-#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS((x,15,3)
+#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS(x,15,3)
 #define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,15,3,z)
 
-#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS((x,18,3)
+#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS(x,18,3)
 #define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,18,3,z)
 
-#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,21,1)
+#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,21,1)
 #define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,21,1,z)
 
-#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,22,1)
+#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,22,1)
 #define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,22,1,z)
 
-#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS((x,23,1)
+#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS(x,23,1)
 #define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_SET(x,z) WMI_SET_BITS(x,23,1,z)
 
-#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS((x,24,1)
+#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS(x,24,1)
 #define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_SET(x,z) WMI_SET_BITS(x,24,1,z)
 
-#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS((x,25,1)
+#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS(x,25,1)
 #define WMI_TXBF_CONF_AX_FDBK_TRIG_SET(x,z) WMI_SET_BITS(x,25,1,z)
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 41ee1707ba12..50b7ed57ba48 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1726
+#define __WMI_REVISION_ 1727
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e043aef256c729a5ada023ce0525278bbc9b067c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 5 Mar 2026 12:01:52 -0800
Subject: [PATCH 183/290] fw-api: CL 31882288 - update fw common interface
 files

Change-Id: I5c64aca8f6bb122fc8a74a232f7954dc4f0dca4c
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  2 ++
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 22 ++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 5f44def7f263..08ea702c2428 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -767,6 +767,8 @@ typedef  enum  {
     /* Indicates FW support for populating vdev operating param stats */
     WMI_SERVICE_VDEV_OPERATING_PARAMS_EVENT_SUPPORT = 494,
     WMI_SERVICE_SUPPORT_WOW_OLE_DAL = 495,
+    /* Indicate FW support for PASSTHRU VDEV Channel Hopping Schedule */
+    WMI_SERVICE_PASSTHRU_VDEV_CHAN_HOP_SCHEDULE_SUPPORT = 496,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 396962c2b3d6..4292a1afc555 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1594,6 +1594,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -6392,7 +6393,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
 
 #define WMITLV_TABLE_WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, wmi_vdev_channel_hopping_schedule_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) /* DEPRECATED - POPULATE WITH ZERO ELEMS */ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_hopping_channel_params, channel_param_list, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID);
 
 /* WMI Command for start ch usage session */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a25d59332a71..a05d2f1da946 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -54913,9 +54913,31 @@ typedef struct {
 
     /* This fixed param TLV will be followed by the below TLVs
      *   - A_UINT32 channel_list[num_chan]; // in MHz
+     *     // DEPRECATED - POPULATE WITH ZERO ELEMS.
+     *     // Use channel_param_list instead.
+     *   - wmi_channel_hopping_channel_params channel_param_list[num_chan];
      */
 } wmi_vdev_channel_hopping_schedule_fixed_param;
 
+typedef enum {
+    /* Channel is designated for PASSTHRU VDEV */
+    WMI_CHANNEL_HOPPING_ROLE_PASSTHRU = 0,
+    /* Channel is designated for any other interfaces besides PASSTHRU VDEV */
+    WMI_CHANNEL_HOPPING_ROLE_NON_PASSTHRU,
+} wmi_channel_hopping_role;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params */
+    A_UINT32 tlv_header;
+    A_UINT32 chan_mhz; /* in MHz. Valid only when role is PASSTHRU */
+    /* bandwidth:
+     * Holds a wmi_channel_width enum value.
+     * Valid only when role is PASSTHRU.
+     */
+    A_UINT32 bandwidth;
+    A_UINT32 role; /* holds wmi_channel_hopping_role enum value */
+} wmi_channel_hopping_channel_params;
+
 typedef enum {
     WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1,
     WMI_SMD_ROAM_CONFIG_ROLE_TARGET_AP,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 50b7ed57ba48..33fe4382252c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1727
+#define __WMI_REVISION_ 1728
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9db1eb05c4e5f72b2578779c98d00deff52716c2 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 6 Mar 2026 12:01:47 -0800
Subject: [PATCH 184/290] fw-api: CL 31897484 - update fw common interface
 files

Change-Id: Iea1788c371bead966e53e4a057e6e8debefb38c1
CRs-Fixed: 3830439
---
 fw/htt.h | 55 ++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 13 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 87efcf7a49b3..344b93e2665a 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -280,9 +280,10 @@
  * 3.150 Add htt_reg_write_selection definitions.
  * 3.151 Add HTT_H2T DAL_MODE_INFO def.
  * 3.152 Add decap_type in htt_rx_peer_metadata_v1b.
+ * 3.153 Add passthru_pkt flag in rx_peer_metadata structs.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 152
+#define HTT_CURRENT_VERSION_MINOR 153
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -21830,10 +21831,12 @@ PREPACK struct htt_rx_peer_metadata_v1 {
  *
  * The following diagram shows the format of the RX PEER METADATA V1A format.
  *
- * |31 29|28   26|25           22|21   14|   13  |12                  0|
- * |-------------------------------------------------------------------|
- * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
- * |-------------------------------------------------------------------|
+ * |31   |29|28   26|25           22|21   14|   13  |12                  0|
+ * |----------------------------------------------------------------------|
+ * |Rsvd2|PT|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID|
+ * |----------------------------------------------------------------------|
+ * Where:
+ *     PT = passthrough packet
  */
 PREPACK struct htt_rx_peer_metadata_v1a {
     A_UINT32
@@ -21843,7 +21846,8 @@ PREPACK struct htt_rx_peer_metadata_v1a {
         logical_link_id: 4,
         chip_id:         3,
         qdata_refill:    1,
-        reserved2:       2;
+        passthru_pkt:    1,
+        reserved2:       1;
 } POSTPACK;
 
 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S    0
@@ -21912,6 +21916,17 @@ PREPACK struct htt_rx_peer_metadata_v1a {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)); \
     } while (0)
 
+#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S    30
+#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M    0x40000000
+#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S)
+
+#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_SET(_var, _val) \
+    do {                                             \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT, _val);  \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S)); \
+    } while (0)
+
 
 /**
  * @brief target -> RX PEER METADATA V1B format
@@ -22007,14 +22022,15 @@ PREPACK struct htt_rx_peer_metadata_v1b {
 /*
  * htt_rx_peer_metadata_v2 - HTT RX peer metadata version 2
  *
- * |31        21|20    13|12|11  9|8   6|  5  |4   0|
- * |------------+--------+--+-----+-----+-----+-----|
- * |  reserved  |peer    |Q | Log |VDEV | ML  |Peer |
- * |            |session |D |Link | ID  |Peer | ID  |
- * |            |ID      |R | ID  |     |Valid|     |
- * |------------+--------+--+-----+-----+-----+-----|
+ * |31     22|21|20    13|12|11  9|8   6|  5  |4   0|
+ * |---------+--+--------+--+-----+-----+-----+-----|
+ * |reserved |PT|peer    |Q | Log |VDEV | ML  |Peer |
+ * |         |  |session |D |Link | ID  |Peer | ID  |
+ * |         |  |ID      |R | ID  |     |Valid|     |
+ * |---------+--+--------+--+-----+-----+-----+-----|
  * Where:
  *     QDR = queue data refill
+ *     PT  = passthrough packet
  */
 PREPACK struct htt_rx_peer_metadata_v2 {
     A_UINT32
@@ -22024,7 +22040,8 @@ PREPACK struct htt_rx_peer_metadata_v2 {
         logical_link_id:  3,
         qdata_refill:     1,
         peer_session_id:  8,
-        reserved:        11;
+        passthru_pkt:     1,
+        reserved:        10;
 } POSTPACK;
 
 #define HTT_RX_PEER_META_DATA_V2_PEER_ID_S 0
@@ -22098,6 +22115,18 @@ PREPACK struct htt_rx_peer_metadata_v2 {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S)); \
     } while (0)
 
+#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S 21
+#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M 0x00200000
+
+#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M) >> \
+    HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S)
+#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT, _val); \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S)); \
+    } while (0)
+
 
 /* generic variables for masks and shifts for various fields */
 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S;

From f9c7f40c30744d74049c53031707bae5a12037ca Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 10 Mar 2026 18:04:14 -0700
Subject: [PATCH 185/290] fw-api: CL 31924680 - update fw common interface
 files

Change-Id: Id6106b9504b31adca72b5c0f60c1dec530920910
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  10 ++--
 fw/wmi_unified.h  | 124 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 3 files changed, 131 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 4292a1afc555..b2e104a485da 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1595,6 +1595,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params,
+    WMITLV_TAG_STRUC_wmi_uhr_rate_set,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -3139,7 +3140,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
 /* NOTE:
  * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID
  * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and
@@ -6284,7 +6286,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params,  WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
 /* WMI command for unified disconnect cmd */
@@ -6376,7 +6379,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \
     /*---*/ \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, key_install_fixed_param, WMITLV_SIZE_FIX)\
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
 
 /* WMI command for unified SMD Config cmd */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a05d2f1da946..854bd0991616 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2906,6 +2906,7 @@ typedef enum {
 #define WMI_CHAN_FLAG_NAN_DISABLED 19 /* Indicates that NAN operations are disabled on this channel */
 #define WMI_CHAN_FLAG_STA_DFS     20 /* Indicates if STA should process radar signals */
 #define WMI_CHAN_FLAG_ALLOW_EHT   21 /* EHT (11be) is allowed on this channel */
+#define WMI_CHAN_FLAG_ALLOW_UHR   22 /* UHR (11bn) is allowed on this channel */
 
 #define WMI_SET_CHANNEL_FLAG(pwmi_channel,flag) do { \
         (pwmi_channel)->info |=  ((A_UINT32) 1 << flag);      \
@@ -4148,6 +4149,14 @@ typedef struct {
         };
     };
 
+    /*
+     * UHR MAC Capabilities: total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits
+     * those bits actually are max mac capabilities = cap_mac_2g | cap_mac_5g
+     * The actual cap mac info per mac (2g/5g) in the TLV --
+     * WMI_MAC_PHY_CAPABILITIES_EXT2
+     */
+    A_UINT32 uhr_cap_mac_info[WMI_MAX_UHRCAP_MAC_SIZE];
+
     /* Followed by next TLVs:
      *     WMI_DMA_RING_CAPABILITIES          dma_ring_caps[];
      *     wmi_spectral_bin_scaling_params    wmi_bin_scaling_params[];
@@ -4174,6 +4183,7 @@ typedef struct {
      *         wifi_radar_ltf_length_capabilities[];
      *     wmi_wifi_radar_chain_capabilities
      *         wifi_radar_chain_capabilities[];
+     *     WMI_MAC_PHY_CAPABILITIES_EXT2      mac_phy_caps2[];
      */
 } wmi_service_ready_ext2_event_fixed_param;
 
@@ -18868,6 +18878,7 @@ typedef struct {
     A_UINT32 target_tsf_us_hi; /* bits 63:32 */
     A_UINT32 vdev_op_ul_nss; /* vdev operating uplink nss. 1 ~ n: 1ss ~ nss */
     A_UINT32 vdev_op_dl_nss; /* vdev operating downlink nss. 1 ~ n: 1ss ~ nss */
+    A_UINT32 uhr_ops; /* refer to WMI_UHR_OPS_XXX macros */
 
 /* The TLVs follows this structure:
  *     wmi_channel chan; <-- WMI channel
@@ -23025,6 +23036,19 @@ enum wmi_peer_new_assoc {
     WMI_PEER_NEW_ASSOC_MAX = 127
 };
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_uhr_rate_set */
+    /**
+     * B0-B3 indicates max NSS that supports mcs 0-7
+     * B4-B7 indicates max NSS that supports mcs 8-9
+     * B8-B11 indicates max NSS that supports mcs 10-11
+     * B12-B15 indicates max NSS that supports mcs 12-13
+     * B16-B31 reserved
+     */
+    A_UINT32 rx_mcs_set; /* Rx max NSS set */
+    A_UINT32 tx_mcs_set; /* Tx max NSS set */
+} wmi_uhr_rate_set;
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */
     /** peer MAC address */
@@ -23194,6 +23218,23 @@ typedef struct {
     /** Global SAM Peer ID, valid only if sam_peer_id_valid is set */
     A_UINT32 sam_peer_id;
 
+    /** peer_uhr_cap_mac:
+     * UHR mac capabilities from BSS beacon UHR cap IE,
+     * total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits
+     */
+    A_UINT32 peer_uhr_cap_mac[WMI_MAX_UHRCAP_MAC_SIZE];
+    /** peer_uhr_cap_phy:
+     * UHR phy capabilities from BSS beacon UHR cap IE,
+     * total WMI_MAX_UHRCAP_PHY_SIZE*A_UINT32 bits
+     */
+    A_UINT32 peer_uhr_cap_phy[WMI_MAX_UHRCAP_PHY_SIZE];
+    /** refer to WMI_UHR_OPS_XXX macros */
+    A_UINT32 peer_uhr_ops;
+    /** peer_uhr_ppet:
+     * UHR Packet Padding Extension (PPE) thresholds from BSS beacon UHR cap IE
+     */
+    wmi_ppe_threshold peer_uhr_ppet;
+
 /* Following this struct are the TLV's:
  *     A_UINT8 peer_legacy_rates[];
  *     A_UINT8 peer_ht_rates[];
@@ -23216,6 +23257,7 @@ typedef struct {
  *         Only mlo_enable flag required by MCC to decide MAC address
  *         to be used.
  *     wmi_peer_assoc_smd_params peer_assoc_smd_params;
+ *     wmi_uhr_rate_set peer_uhr_rates; <-- UHR capabilities of the peer
  */
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
@@ -41166,6 +41208,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         /* set peer to associated state. will cary all parameters
          * determined during assocication time */
         WMI_RETURN_STRING(WMI_PEER_ASSOC_CMDID);
+        /* peer assoc v2 cmd should be used for non-legacy targets */
+        WMI_RETURN_STRING(WMI_PEER_ASSOC_V2_CMDID);
         /* add a wds  (4 address ) entry. used only for testing
          * WDS feature on AP products */
         WMI_RETURN_STRING(WMI_PEER_ADD_WDS_ENTRY_CMDID);
@@ -48422,6 +48466,45 @@ typedef struct {
 /* Bit 7: reserved */
 /****** End of 11BE EHT Operation Parameters field ******/
 
+/****** 11BN UHR Operation Parameters field ******/
+/* Bit 0 UHR Operation Information Present */
+#define WMI_UHR_OPS_INFORMATION_PRESENT_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 0, 1)
+#define WMI_UHR_OPS_INFORMATION_PRESENT_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 0, 1, value)
+
+/* Bit 1 DPS Enabled */
+#define WMI_UHR_OPS_DPS_ENABLED_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 1, 1)
+#define WMI_UHR_OPS_DPS_ENABLED_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 1, 1, value)
+
+/* Bit 2 NPCA Enabled */
+#define WMI_UHR_OPS_NPCA_ENABLED_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 2, 1)
+#define WMI_UHR_OPS_NPCA_ENABLED_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 2, 1, value)
+
+/* Bit 3 DBE Enabled */
+#define WMI_UHR_OPS_DBE_ENABLED_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 3, 1)
+#define WMI_UHR_OPS_DBE_ENABLED_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 3, 1, value)
+
+/* Bit 4 P-EDCA Enabled */
+#define WMI_UHR_OPS_PEDCA_ENABLED_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 4, 1)
+#define WMI_UHR_OPS_PEDCA_ENABLED_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 4, 1, value)
+
+/* Bit 5~7 DBE Bandwidth */
+#define WMI_UHR_OPS_DBE_BANDWIDTH_GET(uhr_ops) \
+    WMI_GET_BITS(uhr_ops, 5, 3)
+#define WMI_UHR_OPS_DBE_BANDWIDTH_SET(uhr_ops, value) \
+    WMI_SET_BITS(uhr_ops, 5, 3, value)
+
+/* Bit 8~15: reserved */
+/****** End of 11BN UHR Operation Parameters field ******/
 
 typedef struct {
     /** TLV tag and len; tag equals
@@ -55050,7 +55133,46 @@ typedef struct {
     A_UINT32 peer_id;
     /*
      * Following this struct are the TLV's:
-     *     wmi_smd_roam_peer_tid_info smd_tid_info[], TLV per TID;
+     *     wmi_smd_roam_peer_tid_info smd_roam_peer_tid_info[]; <- TLV per TID
+     *     wmi_peer_create_cmd_fixed_param peer_create_fixed_param;
+     *     wmi_peer_create_mlo_params peer_create_mlo_params[];
+     *     wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_fixed_param;
+     *     A_UINT8 peer_assoc_peer_legacy_rates[];
+     *     A_UINT8 peer_assoc_peer_ht_rates[];
+     *     wmi_vht_rate_set peer_assoc_peer_vht_rates;
+     *     wmi_he_rate_set peer_assoc_peer_he_rates[];
+     *     wmi_peer_assoc_mlo_params peer_assoc_mlo_params[];
+     *     wmi_eht_rate_set peer_assoc_peer_eht_rates[];
+     *     wmi_peer_assoc_mlo_partner_link_params
+     *         peer_assoc_partner_link_params[];
+     *     wmi_peer_assoc_tid_to_link_map peer_assoc_peer_tid_to_link_map[];
+     *     wmi_peer_assoc_operating_mode_params
+     *         peer_assoc_operating_mode_params[];
+     *     wmi_peer_assoc_mgmt_mpduq_params peer_assoc_mgmt_mpduq_params[];
+     *     wmi_peer_assoc_mgmt_msduq_params peer_assoc_mgmt_msduq_params[];
+     *     wmi_peer_assoc_hol_msduq_params peer_assoc_hol_mdsuq_params[];
+     *     wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_v2_fixed_param;
+     *     A_UINT8 peer_assoc_v2_peer_legacy_rates[];
+     *     A_UINT8 peer_assoc_v2_peer_ht_rates[];
+     *     wmi_vht_rate_set peer_assoc_v2_peer_vht_rates;
+     *     wmi_he_rate_set peer_assoc_v2_peer_he_rates[];
+     *     wmi_peer_assoc_mlo_params peer_assoc_v2_mlo_params[];
+     *     wmi_eht_rate_set peer_assoc_v2_peer_eht_rates[];
+     *     wmi_peer_assoc_mlo_partner_link_params
+     *         peer_assoc_v2_partner_link_params[];
+     *     wmi_peer_assoc_tid_to_link_map peer_assoc_v2_peer_tid_to_link_map[];
+     *     wmi_peer_assoc_operating_mode_params
+     *         peer_assoc_v2_operating_mode_params[];
+     *     wmi_peer_assoc_mgmt_mpduq_params peer_assoc_v2_mgmt_mpduq_params[];
+     *     wmi_peer_assoc_mgmt_msduq_params peer_assoc_v2_mgmt_msduq_params[];
+     *     wmi_peer_assoc_hol_msduq_params peer_assoc_v2_hol_mdsuq_params[];
+     *     wmi_peer_uhr_npca_cap_params peer_assoc_v2_peer_npca_cap_params[];
+     *     wmi_peer_create_mlo_params peer_assoc_v2_create_mlo_params[];
+     *     wmi_peer_assoc_cfp_params peer_assoc_v2_cfp_params;
+     *     wmi_peer_assoc_smd_params peer_assoc_v2_smd_params;
+     *     wmi_vdev_install_key_cmd_fixed_param key_install_fixed_param;
+     *     A_UINT8 key_data[];
+     *     wmi_uhr_rate_set peer_uhr_rates[];
      */
 } wmi_smd_roam_peer_unified_setup_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 33fe4382252c..4acce54fe0b8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1728
+#define __WMI_REVISION_ 1729
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From af2c7743fa570e915453cde54f54be959a91dc6b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Mar 2026 18:01:46 -0700
Subject: [PATCH 186/290] fw-api: CL 31932286 - update fw common interface
 files

Change-Id: I605b82a645a6cae125cde029e900920ded490573
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   5 ++
 fw/wmi_tlv_defs.h |  14 ++-
 fw/wmi_unified.h  | 222 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 4 files changed, 237 insertions(+), 6 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 08ea702c2428..a49066f40abe 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -769,6 +769,11 @@ typedef  enum  {
     WMI_SERVICE_SUPPORT_WOW_OLE_DAL = 495,
     /* Indicate FW support for PASSTHRU VDEV Channel Hopping Schedule */
     WMI_SERVICE_PASSTHRU_VDEV_CHAN_HOP_SCHEDULE_SUPPORT = 496,
+    /*
+     * Indicates FW support for shared memory model to pass
+     * ongoing TBTT count downs to Host.
+     */
+    WMI_SERVICE_SHARED_MEM_MODEL_TBTT_COUNT_DOWN = 497,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index b2e104a485da..bc17569bcb89 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1596,6 +1596,9 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params,
     WMITLV_TAG_STRUC_wmi_uhr_rate_set,
+    WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config,
+    WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info,
+    WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2974,7 +2977,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \
-   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params,  WMITLV_SIZE_VAR)
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params,  WMITLV_SIZE_VAR) \
+   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_uhr_config, uhr_config,  WMITLV_SIZE_VAR)
 /* NOTE:
  * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
@@ -3892,7 +3896,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, wmi_vdev_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_txrx_streams, cfg_txrx_streams, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_mlo_params, mlo_params, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_tbtt_count_down_offset_info, offset_info, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CREATE_CMDID);
 
@@ -6453,7 +6458,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
 
 /* SERVICE_READY_EXT2 event */
 #define WMITLV_TABLE_WMI_SERVICE_READY_EXT2_EVENTID(id,op,buf,len) \
-     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_bin_scaling_params, wmi_bin_scaling_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT, mac_phy_caps, WMITLV_SIZE_VAR) \
@@ -6475,7 +6480,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_shared_mem_model_tbtt_count_down_config, shared_mem_model_tbtt_count_down_config, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
 
 #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 854bd0991616..89a4959bdc9b 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3936,6 +3936,76 @@ typedef enum {
     WMI_SET_BITS(sam_capability_2, 0, 12, value)
 /* End SAM related capabilities */
 
+
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config.*/
+    A_UINT32 tlv_header;
+    /* Indicates what are all the TBTT count down that FW supports */
+    union {
+        struct {
+            A_UINT32 csa                    :1,
+                     quiet                  :1,
+                     max_chan_switch_time   :1,
+                     eht_bpcc               :1,
+                     ttlm_max_switch_time   :1,
+                     ttlm_expected_duration :1,
+                     ml_reconfig            :1,
+                     uhr_epbcc              :1,
+                     uhr_params_update      :1,
+                     rsvd                   :23;
+        };
+        A_UINT32 config_1;
+    };
+
+} wmi_shared_mem_model_tbtt_count_down_config;
+
+/* wmi_shared_mem_model_tbtt_count_down_config GET/SET macros */
+#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_GET(config_1) \
+    WMI_GET_BITS(config_1, 0, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 0, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_GET(config_1) \
+    WMI_GET_BITS(config_1, 1, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 1, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_GET(config_1) \
+    WMI_GET_BITS(config_1, 2, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 2, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_GET(config_1) \
+    WMI_GET_BITS(config_1, 3, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 3, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_GET(config_1) \
+    WMI_GET_BITS(config_1, 4, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 4, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_GET(config_1) \
+    WMI_GET_BITS(config_1, 5, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 5, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_GET(config_1) \
+    WMI_GET_BITS(config_1, 6, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 6, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_GET(config_1) \
+    WMI_GET_BITS(config_1, 7, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 7, 1, value)
+
+#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_GET(config_1) \
+    WMI_GET_BITS(config_1, 8, 1)
+#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_SET(config_1, value) \
+    WMI_SET_BITS(config_1, 8, 1, value)
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/
 
@@ -4183,7 +4253,9 @@ typedef struct {
      *         wifi_radar_ltf_length_capabilities[];
      *     wmi_wifi_radar_chain_capabilities
      *         wifi_radar_chain_capabilities[];
-     *     WMI_MAC_PHY_CAPABILITIES_EXT2      mac_phy_caps2[];
+     *     WMI_MAC_PHY_CAPABILITIES_EXT2 mac_phy_caps2[];
+     *     wmi_shared_mem_model_tbtt_count_down_config
+     *         wmi_shared_mem_model_tbtt_count_down_config[];
      */
 } wmi_service_ready_ext2_event_fixed_param;
 
@@ -17824,6 +17896,34 @@ typedef struct {
 } wmi_vdev_start_smd_params;
 
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config*/
+    union {
+        struct {
+            A_UINT32 advance_notification_interval : 8,
+                     post_notification_interval : 8,
+                     critical_update_indication_interval : 8,
+                     reserved : 8;
+        };
+        A_UINT32 uhr_cu_intervals;
+    };
+} wmi_vdev_start_uhr_config;
+
+#define WMI_VDEV_START_UHR_GET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals) \
+    WMI_GET_BITS(uhr_cu_intervals, 0, 8)
+#define WMI_VDEV_START_UHR_SET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \
+    WMI_SET_BITS(uhr_cu_intervals, 0, 8, _val)
+
+#define WMI_VDEV_START_UHR_GET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals) \
+     WMI_GET_BITS(uhr_cu_intervals, 8, 8)
+#define WMI_VDEV_START_UHR_SET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \
+    WMI_SET_BITS(uhr_cu_intervals, 8, 8, _val)
+
+#define WMI_VDEV_START_UHR_GET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals) \
+    WMI_GET_BITS(uhr_cu_intervals, 16, 8)
+#define WMI_VDEV_START_UHR_SET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals, val)  \
+    WMI_SET_BITS(uhr_cu_intervals, 16, 8, _val)
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
@@ -18023,6 +18123,123 @@ typedef enum {
 } WMI_VDEV_CREATE_WFDR2_MODES;
 
 
+/*
+ * This TLV structure is used to pass the offsets of each TBTT count down,
+ * pertaining to advance notification of any BSS parameter change,
+ * in the host allocated DDR memory, to which FW should copy the
+ * current count down.
+ */
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag (WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info) and len */
+    /**
+     * host_addr_lsb - LSB 32 bits of Host DDR physical address
+     * host_addr_msb - MSB 32 bits of Host DDR physical address
+     */
+    A_UINT32 host_addr_lsb;
+    A_UINT32 host_addr_msb;
+    A_UINT32 size; /** Indicates the total bytes allocated for this VAP */
+    /**
+     * offsets should always start from 1 as 0th offset shall be reserved for
+     * flags.
+     * A_UINT32[0] = EHT CU | UHR CU
+     * So if the below offset infos contain zero, FW shall assume they are
+     * invalid.
+     */
+    /** offsets of CSA & QUIET count down */
+    union {
+        struct {
+            A_UINT32 csa   : 16,
+                     quiet : 16;
+        };
+        A_UINT32 offset_info_1;
+    };
+    /** offsets of EHT BPCC & ML-RECONFIG count down */
+    union {
+        struct {
+            A_UINT32 eht_bpcc : 16,
+                     reconfig : 16;
+        };
+        A_UINT32 offset_info_2;
+    };
+    /**
+     * offsets of TTLM Max Channel Switch Time &
+     * Expected Duration count down
+     */
+    union {
+        struct {
+            A_UINT32 ttlm_max_chan_switch_time : 16,
+                     ttlm_expected_duration    : 16;
+        };
+        A_UINT32 offset_info_3;
+    };
+    /** offsets of UHR Param Update count down & EBPCC */
+    union {
+        struct {
+            A_UINT32 uhr_param_update : 16,
+                     uhr_ebpcc        : 16;
+        };
+        A_UINT32 offset_info_4;
+    };
+    /** offsets of Max Channel Switch Timer */
+    union {
+        struct {
+            A_UINT32 max_chan_switch_time : 16,
+                     reserved_1           : 16;
+        };
+        A_UINT32 offset_info_5;
+    };
+} wmi_vdev_create_tbtt_count_down_offset_info;
+
+/* offsets of CSA & Quiet count down */
+#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_GET(offset_info_1) \
+    WMI_GET_BITS(offset_info_1, 0, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_SET(offset_info_1, value) \
+    WMI_SET_BITS(offset_info_1, 0, 16, value)
+
+#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_GET(offset_info_1) \
+    WMI_GET_BITS(offset_info_1, 16, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_SET(offset_info_1, value) \
+    WMI_SET_BITS(offset_info_1, 16, 16, value)
+
+/* offsets of EHT BPCC & ML-RECONFIG count down */
+#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_GET(offset_info_2) \
+    WMI_GET_BITS(offset_info_2, 0, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_SET(offset_info_2, value) \
+    WMI_SET_BITS(offset_info_2, 0, 16, value)
+
+#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_GET(offset_info_2) \
+    WMI_GET_BITS(offset_info_2, 16, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_SET(offset_info_2, value) \
+    WMI_SET_BITS(offset_info_2, 16, 16, value)
+
+/* offsets of TTLM Max Channel Switch Time & Expected Duration count down */
+#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_GET(offset_info_3) \
+    WMI_GET_BITS(offset_info_3, 0, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_SET(offset_info_3, value) \
+    WMI_SET_BITS(offset_info_3, 0, 16, value)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_GET(offset_info_3) \
+    WMI_GET_BITS(offset_info_3, 16, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_SET(offset_info_3, value) \
+    WMI_SET_BITS(offset_info_3, 16, 16, value)
+
+/* offsets of UHR Param Update count down & EBPCC */
+#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_GET(offset_info_4) \
+    WMI_GET_BITS(offset_info_4, 0, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_SET(offset_info_4, value) \
+    WMI_SET_BITS(offset_info_4, 0, 16, value)
+
+#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_GET(offset_info_4) \
+    WMI_GET_BITS(offset_info_4, 16, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_SET(offset_info_4, value) \
+    WMI_SET_BITS(offset_info_4, 16, 16, value)
+
+/* offsets of Max Channel Switch Time */
+#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_GET(offset_info_5) \
+    WMI_GET_BITS(offset_info_5, 0, 16)
+#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_SET(offset_info_5, value) \
+    WMI_SET_BITS(offset_info_5, 0, 16, value)
+
+
 /* this TLV structure used for pass mlo parameters on vdev start*/
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; */
@@ -18894,6 +19111,9 @@ typedef struct {
  *     wmi_dbw_chan_info dbw_chan_info
  *         optional TLV used for dbw_chan_info
  *     wmi_vdev_start_smd_params smd_params;
+ *         optional TLV used for SMD
+ *     wmi_vdev_start_uhr_config uhr_config_info
+ *         optional TLV used if VAP is 11BN
  */
 } wmi_vdev_start_request_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4acce54fe0b8..ae9f4a852839 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1729
+#define __WMI_REVISION_ 1730
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From bdcc35a82e5a1413a1bbcc7506554eb77b66a9c0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 11 Mar 2026 18:03:39 -0700
Subject: [PATCH 187/290] fw-api: CL 31933928 - update fw common interface
 files

Change-Id: Ib200ff27806734debc90d3bcb97b04f5867e5cde
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 89a4959bdc9b..a97ce1d7ff75 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -46561,6 +46561,7 @@ typedef enum {
     WMI_6GHZ_REG_PWRMODE_VLP = 2, /* VLP mode for AP and client products */
     WMI_6GHZ_REG_PWRMODE_SP_STA = 3, /* SP client mode for AP products */
     WMI_6GHZ_REG_PWRMODE_C2C = 4, /*C2C client mode for AP and client products*/
+    WMI_6GHZ_REG_PWRMODE_GVP = 5, /* GVP mode for AP and client products */
 
     WMI_6GHZ_REG_PWRMODE_MAX = 5
 } WMI_6GHZ_REG_PWRMODE_TYPE;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ae9f4a852839..0c75e1ddc159 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1730
+#define __WMI_REVISION_ 1731
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 08a0b88a370e7138eaf873f94cd24a0611db0c98 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 12 Mar 2026 18:02:05 -0700
Subject: [PATCH 188/290] fw-api: CL 31944819 - update fw common interface
 files

Change-Id: I86287099ac0d2c86cf39199d7e8ea01e1e21a50a
CRs-Fixed: 3830439
---
 fw/wlan_defs.h | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h
index fa31d27e763b..2e7a28ec2a7d 100755
--- a/fw/wlan_defs.h
+++ b/fw/wlan_defs.h
@@ -75,19 +75,6 @@
      */
     #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR
   #endif
-#else
-  /*
-   * For backwards compatibility, if CONFIG_160MHZ_SUPPORT is not defined,
-   * default it to 0, if this is either a host build or a Rome target build.
-   * This maintains the prior behavior for the host and Rome target builds.
-   */
-  #if defined(AR6320) || !defined(ATH_TARGET)
-    /*
-     * Set a flag to indicate that at the end of the file,
-     * CONFIG_160MHZ_SUPPORT should be set to 0.
-     */
-    #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR
-  #endif
 #endif
 
 #ifndef SUPPORT_11AX

From 609d3a69cb3cd05e21e87d8f71d4e893d45dfd4c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 12 Mar 2026 18:04:42 -0700
Subject: [PATCH 189/290] fw-api: CL 31945200 - update fw common interface
 files

Change-Id: I131c2ff996d2220562c71faf16813a5775b64b45
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 24 ++++++++++++++++++++++++
 fw/wmi_unified.h  | 28 ++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index bc17569bcb89..03c449cd2af0 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1200,6 +1200,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_ctrl_path_dfs_channel_stats_struct,
     WMITLV_TAG_STRUC_wmi_twt_ack_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_twt_caps_param,
+    WMITLV_TAG_STRUC_wmi_twt_caps_params = /* alias */
+        WMITLV_TAG_STRUC_wmi_twt_caps_param,
     WMITLV_TAG_STRUC_wmi_vdev_enable_disable_intra_bss_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_peer_enable_disable_intra_bss_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_aoa_phasedelta_evt_fixed_param,
@@ -1221,6 +1223,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_dbs_or_sbs_cap_ext,
     WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param,
     WMITLV_TAG_STRUC_cust_bdf_version_capabilities,
+    WMITLV_TAG_STRUC_wmi_cust_bdf_version_capabilities = /* alias */
+        WMITLV_TAG_STRUC_cust_bdf_version_capabilities,
     WMITLV_TAG_STRUC_wmi_pdev_fips_extend_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_fips_extend_cmd_init_params,
     WMITLV_TAG_STRUC_wmi_pdev_fips_extend_event_fixed_param,
@@ -1428,6 +1432,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_dcs_obss_int_t,
     WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param,
     WMITLV_TAG_STRUC_wmi_sar_flags,
+    WMITLV_TAG_STRUC_wmi_sar_flag_tlv_param = /* alias */
+        WMITLV_TAG_STRUC_wmi_sar_flags,
     WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_reg_chan_list_cc_event_ext2_fixed_param,
@@ -1458,7 +1464,11 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_scan_cache_result_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_scan_cache_info,
     WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES,
+    WMITLV_TAG_STRUC_WMI_POWER_BOOST_CAPABILITIES = /* alias */
+        WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES,
     WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES,
+    WMITLV_TAG_STRUC_WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES = /* alias */
+        WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES,
     WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_start_indication_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_fixed_param,
     WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param,
@@ -1599,6 +1609,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config,
     WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info,
     WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config,
+    WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2202,6 +2214,7 @@ typedef enum {
     OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \
     OP(WMI_TWT_ADD_CH_USAGE_CMDID) \
     OP(WMI_COEX_GET_POLICY_STATS_CMDID) \
+    OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2564,6 +2577,7 @@ typedef enum {
     OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \
     OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \
     OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \
+    OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6416,6 +6430,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_ADD_CH_USAGE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, wmi_coex_policy_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_CMDID);
 
+/* WMI command to set CUMAC chip ID cmd */
+#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, wmi_pdev_set_cumac_chip_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8783,6 +8802,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_EVENTID);
 
+/* WMI unified set CUMAC chip ID confirmation event */
+#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a97ce1d7ff75..412d1a7f4c25 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -630,6 +630,8 @@ typedef enum {
     WMI_PDEV_UHR_CU_CMDID,
     /** WMI cmd used to enable/disable and get power and data path stats */
     WMI_PDEV_POWER_DATAPATH_STATS_CMDID,
+    /** WMI cmd to get the CUMAC chip ID */
+    WMI_PDEV_SET_CUMAC_CHIP_CMDID,
 
     /* VDEV (virtual device) specific commands */
     /** vdev create */
@@ -2071,6 +2073,8 @@ typedef enum {
      */
     WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */
 
+    /** Event to indicate CUMAC Chip ID initialization completed to host */
+    WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID, /* 55 */
 
     /***
      *** add new WMI_PDEV EVENTID defs directly above here,
@@ -55410,6 +55414,30 @@ typedef struct {
     A_UINT32 status; /** wmi_smd_peer_setup_status_type */
 } wmi_smd_roam_peer_unified_setup_complete_event_fixed_param;
 
+
+typedef enum {
+    WMI_PDEV_SET_CUMAC_CHIP_ID_SUCCESS = 0,
+    WMI_PDEV_SET_CUMAC_CHIP_ID_FAILURE,
+} wmi_pdev_set_cumac_chip_id_status_type;
+
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_cumac_chip_id_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** global unique ID identifying pdev */
+    A_UINT32 pdev_id;
+    /** global unique ID identifying chip id of selected CUMAC chip */
+    A_UINT32 cumac_chip_id;
+} wmi_pdev_set_cumac_chip_id_cmd_fixed_param;
+
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** global unique ID identifying pdev */
+    A_UINT32 pdev_id;
+    A_UINT32 status; /** wmi_pdev_set_cumac_chip_id_status_type */
+} wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param;
+
+
 /* vdev operating param flags */
 #define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_BW     0x1
 #define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_NSS    0x2
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0c75e1ddc159..f41fefdad7e6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1731
+#define __WMI_REVISION_ 1732
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From d02a846c6ff307c5d1a9b2b70a17ff30ecb378ac Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 14 Mar 2026 18:06:21 -0700
Subject: [PATCH 190/290] fw-api: CL 31959202 - update fw common interface
 files

Change-Id: I5bcfb457b507822ea3fb134b214ed7e847d9d254
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  2 ++
 fw/wmi_tlv_defs.h |  5 ++-
 fw/wmi_unified.h  | 83 ++++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 89 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index a49066f40abe..69af1b7ebdff 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -774,6 +774,8 @@ typedef  enum  {
      * ongoing TBTT count downs to Host.
      */
     WMI_SERVICE_SHARED_MEM_MODEL_TBTT_COUNT_DOWN = 497,
+    /* Indicate FW support for IPI (Idle Power Indicate) stats collection */
+    WMI_SERVICE_IDLE_POWER_INDICATE_SUPPORT = 498,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 03c449cd2af0..a5a94c79fea3 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1611,6 +1611,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config,
     WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_iface_ipi_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -7137,7 +7138,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_ipi_stats, iface_ipi_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snr_histogram, WMITLV_SIZE_VAR)
 
 WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID);
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 412d1a7f4c25..6f79ecbf54f4 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5230,8 +5230,13 @@ typedef struct {
      *  Bits 28:26 - extension bits for specifing the format version of the
      *     rx peer metadata the target needs to use (to cover versions V2 and
      *     beyond).
+     *  Bit 29 - enable ipi_stats feature:
+     *      0 -> disable the feature
+     *      1 -> enable the feature
+     *     Refer to below WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET/SET
+     *     macros.
      *
-     *  Bits 31:29 - Reserved
+     *  Bits 31:30 - Reserved
      */
     A_UINT32 flags2;
     /** @brief host_service_flags - can be used by Host to indicate
@@ -5875,6 +5880,11 @@ typedef struct {
 #define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_SET(flags2, value) \
     WMI_SET_BITS(flags2, 26, 3, value)
 
+#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET(flags2) \
+    WMI_GET_BITS(flags2, 29, 1)
+#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_SET(flags2, value) \
+    WMI_SET_BITS(flags2, 29, 1, value)
+
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
     WMI_GET_BITS(host_service_flags, 0, 1)
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_SET(host_service_flags, val) \
@@ -12491,6 +12501,77 @@ typedef struct {
    A_UINT32 tot_err_tim_bcn;
 } wmi_iface_powersave_stats;
 
+
+#define WMI_IPI_STATS_SNR_LOWER_BOUND_GET(snr_config) \
+    WMI_GET_BITS(snr_config, 0, 8)
+#define WMI_IPI_STATS_SNR_LOWER_BOUND_SET(snr_config, value) \
+    WMI_SET_BITS(snr_config, 0, 8, value)
+#define WMI_IPI_STATS_SNR_UPPER_BOUND_GET(snr_config) \
+    WMI_GET_BITS(snr_config, 8, 8)
+#define WMI_IPI_STATS_SNR_UPPER_BOUND_SET(snr_config, value) \
+    WMI_SET_BITS(snr_config, 8, 8, value)
+#define WMI_IPI_STATS_SNR_STEP_GET(snr_config) \
+    WMI_GET_BITS(snr_config, 16, 8)
+#define WMI_IPI_STATS_SNR_STEP_SET(snr_config, value) \
+    WMI_SET_BITS(snr_config, 16, 8, value)
+#define WMI_IPI_STATS_SNR_NUM_BINS_GET(snr_config) \
+    WMI_GET_BITS(snr_config, 24, 8)
+#define WMI_IPI_STATS_SNR_NUM_BINS_SET(snr_config, value) \
+    WMI_SET_BITS(snr_config, 24, 8, value)
+
+/* 
+ * Signal to Noise Ration(SNR) is measured during idle periods and reported
+ * as a distribution across multiple bins
+ */
+typedef struct {
+   A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_ipi_stats */
+
+   /*
+    * Total time in microseconds spent on the channel during which
+    * these signal-to-noise measurements were collected
+    */
+   A_UINT32 meas_dur_us;
+
+   /* snr_config:
+    * Contains lower bound, upper bound, step value and total bins for the
+    * SNR measurements done.
+    * Firmware collects the SNR data into
+    *     (((upper_bound - lower_bound)/step) + out_of_bound_bins)
+    * bins and sends to host.
+    * lower_bound - Lower value of the SNR measurement range
+    * upper_bound - Upper value of the SNR measurement range
+    * step        - Each bin data range
+    * num_bins    - Number of bins calculated as per above formula,
+    *               represents the number of elements in TLV snr_histogram
+    * out_of_bound_bins(=2) - Number of bins to carry values below lower
+    *                         bound and above upper bound in corresponding bin,
+    *                         including lower and upper bound values
+    * E.g - 1. lower_bound = 0, upper_bound = 100 and step = 10
+    *          Firmware collects the SNR samples into ((100-0)/10)+2 = 12 bins
+    * E.g - 2. lower_bound = 10, upper_bound = 90 and step = 20
+    *          Firmware collects the SNR samples into ((90-10)/20)+2 = 6 bins
+    */
+   A_UINT32 snr_config;
+
+   /*
+    * This TLV is followed by a snr_histogram TLV containing a variable-length
+    * array of A_UINT32 to carry data from each bin.
+    * Bin[0] contains the number of samples with SNR < lower_bound dB
+    * Bin[1] contains the number of samples with SNR in range
+    *     [lower_bound, lower_bound + step) dB
+    * Bin[2] contains the number of samples with SNR in range
+    *     [lower_bound + step, lower_bound + 2*step) dB
+    * ...
+    * Bin[num_bins - 2] contains the number of samples with SNR in range
+    *     [upper_bound - step, upper_bound) dB
+    * Bin[num_bins - 1] contains the number of samples with
+    *     SNR >= upper_bound dB
+    *
+    *  A_UINT32 snr_histogram[num_bins]
+    */
+} wmi_iface_ipi_stats;
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ipa_link_stats */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f41fefdad7e6..b5767ce360dd 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1732
+#define __WMI_REVISION_ 1733
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 01e6e6cb2eb8861c346a3ca4d794bb4b2261f54a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 17 Mar 2026 18:05:31 -0700
Subject: [PATCH 191/290] fw-api: CL 31978468 - update fw common interface
 files

Change-Id: I9f25eaa8f2faeb9ec3b133d51f9874be745d222d
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 4e6c719274cd..2a10a2e45591 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -990,6 +990,21 @@ typedef struct {
     };
     /* Flag to indicate if the channel chosen is 320_1 / 320_2 */
     A_UINT32 chan_type_320mhz;
+
+    /*
+     * BIT [15 :  0] - obss_dur_us reports the remaining OBSS dur when
+     *                 this FES started OTA.
+     * BIT [16 : 16] - oprim indicates M/O primary FES.
+     * BIT [31 : 17] - reserved
+     */
+    union {
+        A_UINT32 reserved__oprim__obss_dur;
+        struct {
+            A_UINT32 obss_dur_us: 16,
+                     oprim:        1,
+                     reserved4:   15;
+        };
+    };
 } htt_ppdu_stats_common_tlv;
 
 #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M     0x000000ff

From 7b381e0bec64c3c37bd4f6ad5735f77babc49b45 Mon Sep 17 00:00:00 2001
From: Surya Prakash Sivaraj <suryapra@qti.qualcomm.com>
Date: Wed, 18 Mar 2026 13:25:34 +0530
Subject: [PATCH 192/290] qcacld-3.0: Reset SPMK cache before every connection

SPMK global cache in the vdev private is persistent
across connections. Therefore, in cross-ssid roaming
cases with different AKMs, SPMK in the global cache
will always be sent to the firmware in RSO start, even
for non-SAE connections. This causes roam failure.

Reset the spmk global cache for every new connection.

Change-Id: I03deefe16242ef79d0985a8c05881914e6f7af01
CRs-Fixed: 3310182
---
 core/mac/src/pe/lim/lim_api.c                      |  4 ++++
 core/mac/src/pe/lim/lim_process_sme_req_messages.c | 12 ++++++++++--
 core/sme/src/csr/csr_api_roam.c                    |  5 ++++-
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/core/mac/src/pe/lim/lim_api.c b/core/mac/src/pe/lim/lim_api.c
index 80ee8867c140..2e0f0511dc89 100644
--- a/core/mac/src/pe/lim/lim_api.c
+++ b/core/mac/src/pe/lim/lim_api.c
@@ -2631,6 +2631,10 @@ pe_roam_synch_callback(struct mac_context *mac_ctx,
 	lim_fill_ft_session(mac_ctx, bss_desc, ft_session_ptr,
 			    session_ptr, roam_sync_ind_ptr->phy_mode);
 	pe_update_crypto_params(mac_ctx, ft_session_ptr, roam_sync_ind_ptr);
+
+	/* Reset the SPMK global cache */
+	wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc,
+					     ft_session_ptr->vdev_id, false);
 	/* Next routine may update nss based on dot11Mode */
 	lim_ft_prepare_add_bss_req(mac_ctx, ft_session_ptr, bss_desc);
 	if (session_ptr->is11Rconnection)
diff --git a/core/mac/src/pe/lim/lim_process_sme_req_messages.c b/core/mac/src/pe/lim/lim_process_sme_req_messages.c
index 0f57abe3c224..f9eb195526dd 100644
--- a/core/mac/src/pe/lim/lim_process_sme_req_messages.c
+++ b/core/mac/src/pe/lim/lim_process_sme_req_messages.c
@@ -1604,6 +1604,14 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf)
 		session->connected_akm = sme_join_req->akm;
 		session->is_adaptive_11r_connection =
 				sme_join_req->is_adaptive_11r_connection;
+		/* Reset the SPMK global cache for non-SAE connection */
+		if (session->connected_akm != ANI_AKM_TYPE_SAE) {
+			wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc,
+							     session->vdev_id,
+							     false);
+			wlan_mlme_clear_sae_single_pmk_info(session->vdev,
+							    NULL);
+		}
 #ifdef FEATURE_WLAN_ESE
 		session->isESEconnection = sme_join_req->isESEconnection;
 #endif
@@ -1832,7 +1840,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf)
 			session->spectrumMgtEnabled = true;
 
 		session->isOSENConnection = sme_join_req->isOSENConnection;
-		pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d",
+		pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d akm %d",
 			 session->curr_op_freq, session->ch_width,
 			 session->ch_center_freq_seg0,
 			 session->ch_center_freq_seg1,
@@ -1843,7 +1851,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf)
 			 session->vht_config.su_beam_former,
 			 session->vht_config.su_beam_formee,
 			 session->vht_config.csnof_beamformer_antSup,
-			 session->isCiscoVendorAP);
+			 session->isCiscoVendorAP, session->connected_akm);
 
 		/* Issue LIM_MLM_JOIN_REQ to MLM */
 		status = lim_send_join_req(session, mlm_join_req);
diff --git a/core/sme/src/csr/csr_api_roam.c b/core/sme/src/csr/csr_api_roam.c
index 4484ed3c5ce8..cf719e8501a6 100644
--- a/core/sme/src/csr/csr_api_roam.c
+++ b/core/sme/src/csr/csr_api_roam.c
@@ -21461,12 +21461,15 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx,
 			mac_ctx->psoc);
 		mac_ctx->sme.set_connection_info_cb(false);
 
-		if (roam_synch_data->pmk_len)
+		if (roam_synch_data->pmk_len) {
+			mlme_debug("Received pmk in roam sync. Length: %d",
+				   roam_synch_data->pmk_len);
 			csr_check_and_set_sae_single_pmk_cap(
 						mac_ctx, session,
 						session_id,
 						roam_synch_data->pmk,
 						roam_synch_data->pmk_len);
+		}
 
 		if (ucfg_pkt_capture_get_pktcap_mode(mac_ctx->psoc))
 			ucfg_pkt_capture_record_channel(vdev);

From 2b22979de83e516a50de95e93312c7da9de31906 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 18 Mar 2026 18:06:31 -0700
Subject: [PATCH 193/290] fw-api: CL 31990638 - update fw common interface
 files

Change-Id: I82d9244c43afbdf1eadfaf0e77ae622e4d975de6
CRs-Fixed: 3830439
---
 fw/htt.h         | 55 +++++++++++++++++++++++++++++++++++++++++++++++-
 fw/htt_stats.h   | 38 ++++++++++++++++-----------------
 fw/wmi_unified.h | 21 +++++++++++++-----
 fw/wmi_version.h |  2 +-
 4 files changed, 90 insertions(+), 26 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 344b93e2665a..030a62cf081d 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -281,9 +281,10 @@
  * 3.151 Add HTT_H2T DAL_MODE_INFO def.
  * 3.152 Add decap_type in htt_rx_peer_metadata_v1b.
  * 3.153 Add passthru_pkt flag in rx_peer_metadata structs.
+ * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 153
+#define HTT_CURRENT_VERSION_MINOR 154
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -12577,6 +12578,7 @@ enum htt_t2h_msg_type {
     HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ               = 0x3d,
     HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP          = 0x3e,
     HTT_T2H_MSG_TYPE_HAPS                          = 0x3f,
+    HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP = 0x40,
 
 
     HTT_T2H_MSG_TYPE_TEST,
@@ -24730,5 +24732,56 @@ PREPACK struct htt_t2h_power_state_info {
     } while (0)
 
 
+/* MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP
+ *
+ * The following diagram shows the format of the peer delete all global vdev
+ * unmap message sent from the target to the host. This message is used to
+ * send unmap event to host after tid and msduq/mpduq cleanup of all peers
+ * associated to a vdev, in FW, host cleans up msduq/mpduq based on message.
+ *
+ * |31                    20|19      16|15              8|7               0|
+ * |------------------------+----------+-----------------+-----------------|
+ * |       reserved         |hw_link_id| global_vdev_id  |     msg type    |
+ * |-----------------------------------------------------------------------|
+ * @details
+ * struct htt_t2h_peer_del_all_global_vdev_id_unmap_t:
+ *
+ * The message is interpreted as follows:
+ * dword0 - b'7:0   - msg_type: This will be set to 0x40
+ *                    (HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP)
+ *          b'15:8  - global_vdev_id : global vdev id assigned by host
+ *          b'19:16 - hw_link_id : hw link id for which unmap is being sent
+ *          b'31:20 - reserved
+ */
+/* HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP */
+PREPACK struct htt_t2h_peer_del_all_global_vdev_id_unmap_t {
+    A_UINT32 msg_type:               8,  /* bits  7:0  */
+             global_vdev_id:         8,  /* bits 15:8  */
+             hw_link_id:             4,  /* bits 19:16 */
+             reserved:               12; /* bits 31:20 */
+} POSTPACK;
+
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M 0x0000FF00
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S 8
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_GET(_var) \
+    (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M) >> \
+     HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S)
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID, _val); \
+        ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S)); \
+    } while (0)
+
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M 0x000F0000
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S 16
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_GET(_var) \
+    (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M) >> \
+     HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S)
+#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID, _val); \
+        ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S)); \
+    } while (0)
+
 
 #endif
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index a20cd8759a36..55af6f6757ce 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -11956,7 +11956,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1
@@ -11966,7 +11966,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008
 #define HTT_STATS_PHY_RESET_XTALCAL_S 3
@@ -11976,7 +11976,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTALCAL_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4
@@ -11986,7 +11986,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5
@@ -11996,7 +11996,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6
@@ -12006,7 +12006,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7
@@ -12016,7 +12016,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8
@@ -12026,7 +12026,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9
@@ -12036,7 +12036,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10
@@ -12046,7 +12046,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL2G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11
@@ -12056,7 +12056,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL5G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12
@@ -12066,7 +12066,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL6G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000
 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13
@@ -12076,7 +12076,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL2G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000
 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14
@@ -12086,7 +12086,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL5G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000
 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15
@@ -12096,7 +12096,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL6G_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16
@@ -12106,7 +12106,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S)); \
     } while (0)
 
 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF
@@ -12117,7 +12117,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_GLUT_LINEARITY_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8
@@ -12127,7 +12127,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_PLUT_LINEARITY_S)); \
     } while (0)
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16
@@ -12137,7 +12137,7 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \
-        ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_WLANDRIVERMODE_S)); \
     } while (0)
 
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6f79ecbf54f4..0e2bc5235011 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -6526,6 +6526,10 @@ typedef struct {
 typedef struct {
     A_UINT32 tlv_header;    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tlv_buf_len_param */
     A_UINT32 buf_len;       /** Length of buf */
+/* NOTE:
+ * This struct cannot be expanded, due to being used as
+ * WMITLV_TAG_ARRAY_FIXED_STRUC in WMI_ROAM_INVOKE_CMDID.
+ */
     /**
      * Following this structure is the TLV byte stream of buf of length buf_len:
      * A_UINT8 buf[];
@@ -12519,7 +12523,7 @@ typedef struct {
 #define WMI_IPI_STATS_SNR_NUM_BINS_SET(snr_config, value) \
     WMI_SET_BITS(snr_config, 24, 8, value)
 
-/* 
+/*
  * Signal to Noise Ration(SNR) is measured during idle periods and reported
  * as a distribution across multiple bins
  */
@@ -18335,7 +18339,7 @@ typedef struct {
      * mlo_ieee_link_id_valid bit set.
      */
     A_UINT32 ieee_link_id;
-    A_UINT32 mlo_vdev_id;
+    A_UINT32 mlo_vdev_id; /* deprecated */
 } wmi_vdev_start_mlo_params;
 
 /* this TLV structure used for passing mlo parameters on vdev stop */
@@ -19181,6 +19185,13 @@ typedef struct {
     A_UINT32 vdev_op_ul_nss; /* vdev operating uplink nss. 1 ~ n: 1ss ~ nss */
     A_UINT32 vdev_op_dl_nss; /* vdev operating downlink nss. 1 ~ n: 1ss ~ nss */
     A_UINT32 uhr_ops; /* refer to WMI_UHR_OPS_XXX macros */
+    /*
+     * VDEV ID that will be assigned for both legacy and MLD VAPs.
+     * This will be configured to rx_meta_data in the AST entry.
+     * This information will then be used by host to achieve intra-bss
+     * forwarding for the Rx packets.
+     */
+    A_UINT32 global_vdev_id;
 
 /* The TLVs follows this structure:
  *     wmi_channel chan; <-- WMI channel
@@ -23727,15 +23738,15 @@ typedef struct {
      * FW will update the Noise Floor in dBr and send it to host
      * if this field is set then host will display NF value in dBr
      */
-    A_UINT32 nf_db_is_valid;
+    A_UINT32 nf_dbr_is_valid;
     /**
      * Noise Floor (NF) value in dBr. If the NF is not converged then
      * NF value is returned as 0 to host. Theoretical minimum NF value
      * is -101 dB for 20 MHz bandwidth and the max value can be 0.
      * PHY reports 0 incase of very high NF values.
-     * This field should be ignored unless the nf_db_is_valid flag is set.
+     * This field should be ignored unless the nf_dbr_is_valid flag is set.
      */
-    A_UINT32 noise_floor_in_db;
+    A_UINT32 noise_floor_in_dbr;
 
 /**
  * Following this structure is the optional TLV:
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b5767ce360dd..8d65648274f2 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1733
+#define __WMI_REVISION_ 1734
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ca1e7dffba8661789bb5f54c272d1d3749966716 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 19 Mar 2026 18:05:33 -0700
Subject: [PATCH 194/290] fw-api: CL 32000241 - update fw common interface
 files

Change-Id: I8ed96f582fd3fe21aa988fee7e09ee5c01ee3ca3
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 2 ++
 fw/wmi_version.h  | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 69af1b7ebdff..dcd795d1710f 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -776,6 +776,8 @@ typedef  enum  {
     WMI_SERVICE_SHARED_MEM_MODEL_TBTT_COUNT_DOWN = 497,
     /* Indicate FW support for IPI (Idle Power Indicate) stats collection */
     WMI_SERVICE_IDLE_POWER_INDICATE_SUPPORT = 498,
+    /* Indicates FW support to add Radar type and domain in WMI radar event */
+    WMI_SERVICE_RADAR_FLAGS_TYPE_SUPPORT = 499,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8d65648274f2..6227368a76e7 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1734
+#define __WMI_REVISION_ 1735
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From b2bc33ab7f76028b2f57fcd344f4b843521b6258 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 24 Mar 2026 18:02:12 -0700
Subject: [PATCH 195/290] fw-api: CL 32023116 - update fw common interface
 files

Change-Id: I41fd396e1c21471630e06770d2183b237cdc91ae
CRs-Fixed: 3830439
---
 fw/htt.h | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 166 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index 030a62cf081d..b6411c191bd6 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -282,9 +282,10 @@
  * 3.152 Add decap_type in htt_rx_peer_metadata_v1b.
  * 3.153 Add passthru_pkt flag in rx_peer_metadata structs.
  * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def.
+ * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 154
+#define HTT_CURRENT_VERSION_MINOR 155
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -6197,6 +6198,11 @@ enum htt_srng_ring_id {
  * dword28- b'0-31  - packet_type_enable_data_fpmo_flags_1 - filter bmap for
  *                    full pkt buffer each mode ctrl/data type/subtype for
  *                    fpmo mode
+ * dword29- b'0-31  - rdi_based_source_cfg
+ *                    Each bit maps to an RDI; if set, the corresponding
+ *                    ring ID is configured as a source buffer.
+ *                    Applies only to HTT_RXDMA_WBM_BUF0/1/2_RING.
+ * dword30- b'0-31  - wifi8 header length configurations.
  */
 PREPACK struct htt_rx_ring_selection_cfg_t {
     A_UINT32 msg_type:          8,
@@ -6280,6 +6286,21 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
      * Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING
      */
     A_UINT32 rdi_based_source_cfg;
+
+    A_UINT32 rxmon_fpmo_data_hdrlen    : 2,
+             rxmon_fpmo_ctrl_hdrlen    : 2,
+             rxmon_fpmo_mgmt_hdrlen    : 2,
+             rxmon_fp_data_hdrlen      : 2,
+             rxmon_fp_ctrl_hdrlen      : 2,
+             rxmon_fp_mgmt_hdrlen      : 2,
+             rxmon_mo_data_hdrlen      : 2,
+             rxmon_mo_ctrl_hdrlen      : 2,
+             rxmon_mo_mgmt_hdrlen      : 2,
+             rxmon_md_data_hdrlen      : 2,
+             rxmon_md_ctrl_hdrlen      : 2,
+             rxmon_md_mgmt_hdrlen      : 2,
+             rxmon_enable_hdr_per_ppdu : 1,
+             rxmon_rsvd                : 7;
 } POSTPACK;
 
 /**
@@ -6963,6 +6984,150 @@ enum htt_reg_write_selection {
      } while (0)
 
 
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M     0x00000003
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S     0
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M     0x0000000C
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S     2
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M     0x00000030
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S     4
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M     0x000000C0
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S     6
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M     0x00000300
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S     8
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M     0x00000C00
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S     10
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M     0x00003000
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S     12
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M     0x0000C000
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S     14
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M     0x00030000
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S     16
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M     0x000C0000
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S     18
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M     0x00300000
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S     20
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M     0x00C00000
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S     22
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)); \
+            } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M     0x01000000
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S     24
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)
+#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)); \
+            } while (0)
+
+
 /*
  * Subtype based MGMT frames enable bits.
  * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other

From ea9c5bd2bb067972733f29643870596ffa015c87 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 25 Mar 2026 18:02:45 -0700
Subject: [PATCH 196/290] fw-api: CL 32033412 - update fw common interface
 files

Change-Id: I4dbc1dfab508ea28659332c35126854e48b5efac
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 0e2bc5235011..f312fd43ee06 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19424,6 +19424,8 @@ typedef enum {
 #define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_FEATURE_BITMAP               0x10
 #define WMI_VDEV_OCE_ESP_FEATURE_BITMAP                                0x20
 #define WMI_VDEV_OCE_REASSOC_REJECT_FEATURE_BITMAP                     0x40
+/* Enable FILS Discovery frame transmission only for 6 GHz SAP */
+#define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_6G_ONLY_FEATURE_BITMAP       0x80
 
 /** 6 GHZ params **/
 /* Control to enable/disable beacon tx in non-HT duplicate */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 6227368a76e7..c35dbd4adf4e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1735
+#define __WMI_REVISION_ 1736
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 75a94a54989d072f6c0958a91387abd9e9d45377 Mon Sep 17 00:00:00 2001
From: Venkateswara Naralasetty <vnaralas@qti.qualcomm.com>
Date: Thu, 26 Mar 2026 10:10:15 +0530
Subject: [PATCH 197/290] fw-api: hw_headers: Add v1 e3r50 hw headers for
 wcn8750

Add v1 hw headers version e3r50 for wcn8750.

Change-Id: Ic36e49f262e447b136941dd252623097a26b648e
CRs-Fixed: 4480325
---
 hw/wcn8750/v1/HALcomdef.h                     |    39 +
 hw/wcn8750/v1/HALhwio.h                       |   291 +
 hw/wcn8750/v1/ack_report.h                    |    52 +
 hw/wcn8750/v1/boron_top_reg.h                 |    12 +
 hw/wcn8750/v1/buffer_addr_info.h              |    45 +
 hw/wcn8750/v1/ce_src_desc.h                   |   122 +
 hw/wcn8750/v1/ce_stat_desc.h                  |   115 +
 hw/wcn8750/v1/coex_rx_status.h                |   131 +
 hw/wcn8750/v1/coex_tx_req.h                   |   222 +
 hw/wcn8750/v1/coex_tx_status.h                |   117 +
 hw/wcn8750/v1/com_dtypes.h                    |   168 +
 hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h      |    94 +
 hw/wcn8750/v1/eht_sig_usr_ofdma_info.h        |   108 +
 hw/wcn8750/v1/eht_sig_usr_su_info.h           |    73 +
 hw/wcn8750/v1/expected_response.h             |   203 +
 hw/wcn8750/v1/he_sig_a_mu_dl_info.h           |   171 +
 hw/wcn8750/v1/he_sig_a_mu_ul_info.h           |   101 +
 hw/wcn8750/v1/he_sig_a_su_info.h              |   206 +
 hw/wcn8750/v1/he_sig_b1_mu_info.h             |    38 +
 hw/wcn8750/v1/he_sig_b2_mu_info.h             |    94 +
 hw/wcn8750/v1/he_sig_b2_ofdma_info.h          |    94 +
 hw/wcn8750/v1/ht_sig_info.h                   |   129 +
 hw/wcn8750/v1/l_sig_a_info.h                  |    80 +
 hw/wcn8750/v1/l_sig_b_info.h                  |    45 +
 hw/wcn8750/v1/macrx_abort_request_info.h      |    31 +
 hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h     |    77 +
 hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h       |    87 +
 hw/wcn8750/v1/mactx_eht_sig_usr_su.h          |    69 +
 hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h          |   132 +
 hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h          |    82 +
 hw/wcn8750/v1/mactx_he_sig_a_su.h             |   157 +
 hw/wcn8750/v1/mactx_he_sig_b1_mu.h            |    44 +
 hw/wcn8750/v1/mactx_he_sig_b2_mu.h            |    77 +
 hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h         |    77 +
 hw/wcn8750/v1/mactx_ht_sig.h                  |   102 +
 hw/wcn8750/v1/mactx_l_sig_a.h                 |    74 +
 hw/wcn8750/v1/mactx_l_sig_b.h                 |    49 +
 hw/wcn8750/v1/mactx_phy_desc.h                |   348 +
 hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h         |   122 +
 hw/wcn8750/v1/mactx_u_sig_eht_tb.h            |    97 +
 hw/wcn8750/v1/mactx_user_desc_common.h        |   482 +
 hw/wcn8750/v1/mactx_user_desc_per_user.h      |   285 +
 hw/wcn8750/v1/mactx_vht_sig_a.h               |   112 +
 hw/wcn8750/v1/mactx_vht_sig_b_mu160.h         |   182 +
 hw/wcn8750/v1/mactx_vht_sig_b_mu20.h          |    54 +
 hw/wcn8750/v1/mactx_vht_sig_b_mu40.h          |    67 +
 hw/wcn8750/v1/mactx_vht_sig_b_mu80.h          |   102 +
 hw/wcn8750/v1/mactx_vht_sig_b_su160.h         |   222 +
 hw/wcn8750/v1/mactx_vht_sig_b_su20.h          |    54 +
 hw/wcn8750/v1/mactx_vht_sig_b_su40.h          |    72 +
 hw/wcn8750/v1/mactx_vht_sig_b_su80.h          |   122 +
 hw/wcn8750/v1/mlo_sta_id_details.h            |    52 +
 hw/wcn8750/v1/mon_buffer_addr.h               |    75 +
 hw/wcn8750/v1/mon_destination_ring.h          |    94 +
 hw/wcn8750/v1/mon_drop.h                      |    61 +
 hw/wcn8750/v1/mon_ingress_ring.h              |    54 +
 hw/wcn8750/v1/msmhwiobase.h                   |   157 +
 hw/wcn8750/v1/msmhwioreg.h                    |    99 +
 hw/wcn8750/v1/no_ack_report.h                 |   108 +
 hw/wcn8750/v1/ofdma_trigger_details.h         |   944 ++
 hw/wcn8750/v1/pcu_ppdu_setup_init.h           |  2316 +++
 hw/wcn8750/v1/pdg_response.h                  |   510 +
 hw/wcn8750/v1/pdg_response_rate_setting.h     |   409 +
 hw/wcn8750/v1/pdg_tx_req.h                    |    89 +
 hw/wcn8750/v1/phyrx_abort_request_info.h      |    87 +
 hw/wcn8750/v1/phyrx_common_user_info.h        |   168 +
 hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h          |   132 +
 hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h          |    82 +
 hw/wcn8750/v1/phyrx_he_sig_a_su.h             |   157 +
 hw/wcn8750/v1/phyrx_he_sig_b1_mu.h            |    44 +
 hw/wcn8750/v1/phyrx_he_sig_b2_mu.h            |    77 +
 hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h         |    77 +
 hw/wcn8750/v1/phyrx_ht_sig.h                  |   102 +
 hw/wcn8750/v1/phyrx_l_sig_a.h                 |    74 +
 hw/wcn8750/v1/phyrx_l_sig_b.h                 |    49 +
 hw/wcn8750/v1/phyrx_location.h                |   332 +
 .../v1/phyrx_other_receive_info_ru_details.h  |    47 +
 hw/wcn8750/v1/phyrx_pkt_end.h                 |   427 +
 hw/wcn8750/v1/phyrx_pkt_end_info.h            |   450 +
 hw/wcn8750/v1/phyrx_rssi_legacy.h             |   806 +
 hw/wcn8750/v1/phyrx_user_info.h               |   202 +
 hw/wcn8750/v1/phyrx_vht_sig_a.h               |   112 +
 hw/wcn8750/v1/phytx_abort_request_info.h      |    38 +
 hw/wcn8750/v1/phytx_pkt_end.h                 |   243 +
 .../v1/phytx_ppdu_header_info_request.h       |    40 +
 hw/wcn8750/v1/receive_pkt_start_info.h        |    87 +
 hw/wcn8750/v1/receive_rssi_info.h             |   465 +
 hw/wcn8750/v1/receive_user_info.h             |   271 +
 hw/wcn8750/v1/received_response_user_15_8.h   |  1116 ++
 hw/wcn8750/v1/received_response_user_23_16.h  |  1116 ++
 hw/wcn8750/v1/received_response_user_31_24.h  |  1116 ++
 hw/wcn8750/v1/received_response_user_36_32.h  |   705 +
 hw/wcn8750/v1/received_response_user_7_0.h    |  1116 ++
 hw/wcn8750/v1/received_response_user_info.h   |   206 +
 hw/wcn8750/v1/received_trigger_info.h         |   142 +
 hw/wcn8750/v1/received_trigger_info_details.h |   193 +
 hw/wcn8750/v1/reo_destination_ring.h          |   305 +
 hw/wcn8750/v1/reo_destination_ring_with_pn.h  |   277 +
 hw/wcn8750/v1/reo_entrance_ring.h             |   321 +
 hw/wcn8750/v1/response_end_status.h           |   277 +
 hw/wcn8750/v1/response_start_status.h         |   112 +
 hw/wcn8750/v1/ru_allocation_160_info.h        |   115 +
 hw/wcn8750/v1/rx_attention.h                  |   376 +
 hw/wcn8750/v1/rx_flow_search_entry.h          |   213 +
 hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h        |   362 +
 hw/wcn8750/v1/rx_frame_bitmap_ack.h           |   236 +
 hw/wcn8750/v1/rx_frame_bitmap_req.h           |    75 +
 hw/wcn8750/v1/rx_location_info.h              |   453 +
 hw/wcn8750/v1/rx_mpdu_desc_info.h             |   101 +
 hw/wcn8750/v1/rx_mpdu_details.h               |   131 +
 hw/wcn8750/v1/rx_mpdu_end.h                   |   196 +
 hw/wcn8750/v1/rx_mpdu_ext_desc_info.h         |    52 +
 hw/wcn8750/v1/rx_mpdu_info.h                  |   972 ++
 hw/wcn8750/v1/rx_mpdu_link_ptr.h              |    40 +
 hw/wcn8750/v1/rx_mpdu_start.h                 |   712 +
 hw/wcn8750/v1/rx_msdu_desc_info.h             |   131 +
 hw/wcn8750/v1/rx_msdu_details.h               |   161 +
 hw/wcn8750/v1/rx_msdu_end.h                   |  1094 ++
 hw/wcn8750/v1/rx_msdu_ext_desc_info.h         |    59 +
 hw/wcn8750/v1/rx_msdu_link.h                  |  2051 +++
 hw/wcn8750/v1/rx_msdu_start.h                 |   306 +
 hw/wcn8750/v1/rx_ppdu_ack_report.h            |    54 +
 hw/wcn8750/v1/rx_ppdu_end_user_stats.h        |   679 +
 hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h    |   133 +
 hw/wcn8750/v1/rx_ppdu_no_ack_report.h         |    87 +
 hw/wcn8750/v1/rx_ppdu_start.h                 |    75 +
 hw/wcn8750/v1/rx_ppdu_start_user_info.h       |   207 +
 hw/wcn8750/v1/rx_preamble.h                   |    54 +
 hw/wcn8750/v1/rx_response_required_info.h     |   764 +
 .../v1/rx_rxpcu_classification_overview.h     |    94 +
 hw/wcn8750/v1/rx_start_param.h                |    47 +
 hw/wcn8750/v1/rx_timing_info.h                |    66 +
 hw/wcn8750/v1/rx_trig_info.h                  |    54 +
 hw/wcn8750/v1/rxpcu_early_rx_indication.h     |    61 +
 hw/wcn8750/v1/rxpcu_ppdu_end_info.h           |   925 ++
 hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h    |   320 +
 hw/wcn8750/v1/rxpt_classify_info.h            |   122 +
 hw/wcn8750/v1/seq_hwio.h                      |    41 +
 hw/wcn8750/v1/tcl_assist_cmd.h                |   411 +
 hw/wcn8750/v1/tcl_status_ring.h               |   129 +
 hw/wcn8750/v1/tlv_hdr.h                       |   634 +
 hw/wcn8750/v1/tlv_tag_def.h                   |  1976 +++
 hw/wcn8750/v1/tqm2sw_completion_ring.h        |   262 +
 hw/wcn8750/v1/tx_cbf_info.h                   |   454 +
 hw/wcn8750/v1/tx_fes_setup.h                  |   585 +
 hw/wcn8750/v1/tx_fes_status_1k_ba.h           |   313 +
 hw/wcn8750/v1/tx_fes_status_ack_or_ba.h       |   145 +
 hw/wcn8750/v1/tx_fes_status_end.h             |   602 +
 hw/wcn8750/v1/tx_fes_status_prot.h            |   156 +
 hw/wcn8750/v1/tx_fes_status_start.h           |   117 +
 hw/wcn8750/v1/tx_fes_status_start_ppdu.h      |   271 +
 hw/wcn8750/v1/tx_fes_status_start_prot.h      |   264 +
 hw/wcn8750/v1/tx_fes_status_user_ppdu.h       |   180 +
 hw/wcn8750/v1/tx_fes_status_user_response.h   |    79 +
 hw/wcn8750/v1/tx_flush_req.h                  |    61 +
 hw/wcn8750/v1/tx_mpdu_start.h                 |   299 +
 hw/wcn8750/v1/tx_msdu_extension.h             |   318 +
 hw/wcn8750/v1/tx_msdu_start.h                 |   250 +
 hw/wcn8750/v1/tx_peer_entry.h                 |   391 +
 hw/wcn8750/v1/tx_queue_extension.h            |   432 +
 hw/wcn8750/v1/tx_rate_stats_info.h            |   108 +
 hw/wcn8750/v1/tx_raw_or_native_frame_setup.h  |   285 +
 hw/wcn8750/v1/txpcu_buffer_basics.h           |    38 +
 hw/wcn8750/v1/txpcu_buffer_status.h           |    58 +
 hw/wcn8750/v1/txpcu_user_buffer_status.h      |    65 +
 hw/wcn8750/v1/u_sig_eht_su_mu_info.h          |   157 +
 hw/wcn8750/v1/u_sig_eht_tb_info.h             |   122 +
 hw/wcn8750/v1/unallocated_ru_160_info.h       |    45 +
 hw/wcn8750/v1/uniform_descriptor_header.h     |    45 +
 hw/wcn8750/v1/vht_sig_a_info.h                |   143 +
 hw/wcn8750/v1/vht_sig_b_mu160_info.h          |   241 +
 hw/wcn8750/v1/vht_sig_b_mu20_info.h           |    52 +
 hw/wcn8750/v1/vht_sig_b_mu40_info.h           |    80 +
 hw/wcn8750/v1/vht_sig_b_mu80_info.h           |   129 +
 hw/wcn8750/v1/vht_sig_b_su160_info.h          |   297 +
 hw/wcn8750/v1/vht_sig_b_su20_info.h           |    52 +
 hw/wcn8750/v1/vht_sig_b_su40_info.h           |    87 +
 hw/wcn8750/v1/vht_sig_b_su80_info.h           |   157 +
 hw/wcn8750/v1/wbm2sw_completion_ring_rx.h     |   289 +
 hw/wcn8750/v1/wbm_buffer_ring.h               |    40 +
 hw/wcn8750/v1/wbm_link_descriptor_ring.h      |    40 +
 hw/wcn8750/v1/wbm_release_ring.h              |   117 +
 hw/wcn8750/v1/wbm_release_ring_rx.h           |    75 +
 hw/wcn8750/v1/wbm_release_ring_tx.h           |    68 +
 hw/wcn8750/v1/wcss_seq_hwiobase.h             |   105 +
 hw/wcn8750/v1/wcss_seq_hwioreg_umac.h         | 13579 ++++++++++++++++
 hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h     |    15 +
 hw/wcn8750/v1/wcss_version.h                  |     6 +
 188 files changed, 59111 insertions(+)
 create mode 100644 hw/wcn8750/v1/HALcomdef.h
 create mode 100644 hw/wcn8750/v1/HALhwio.h
 create mode 100644 hw/wcn8750/v1/ack_report.h
 create mode 100644 hw/wcn8750/v1/boron_top_reg.h
 create mode 100644 hw/wcn8750/v1/buffer_addr_info.h
 create mode 100644 hw/wcn8750/v1/ce_src_desc.h
 create mode 100644 hw/wcn8750/v1/ce_stat_desc.h
 create mode 100644 hw/wcn8750/v1/coex_rx_status.h
 create mode 100644 hw/wcn8750/v1/coex_tx_req.h
 create mode 100644 hw/wcn8750/v1/coex_tx_status.h
 create mode 100644 hw/wcn8750/v1/com_dtypes.h
 create mode 100644 hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
 create mode 100644 hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
 create mode 100644 hw/wcn8750/v1/eht_sig_usr_su_info.h
 create mode 100644 hw/wcn8750/v1/expected_response.h
 create mode 100644 hw/wcn8750/v1/he_sig_a_mu_dl_info.h
 create mode 100644 hw/wcn8750/v1/he_sig_a_mu_ul_info.h
 create mode 100644 hw/wcn8750/v1/he_sig_a_su_info.h
 create mode 100644 hw/wcn8750/v1/he_sig_b1_mu_info.h
 create mode 100644 hw/wcn8750/v1/he_sig_b2_mu_info.h
 create mode 100644 hw/wcn8750/v1/he_sig_b2_ofdma_info.h
 create mode 100644 hw/wcn8750/v1/ht_sig_info.h
 create mode 100644 hw/wcn8750/v1/l_sig_a_info.h
 create mode 100644 hw/wcn8750/v1/l_sig_b_info.h
 create mode 100644 hw/wcn8750/v1/macrx_abort_request_info.h
 create mode 100644 hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
 create mode 100644 hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
 create mode 100644 hw/wcn8750/v1/mactx_eht_sig_usr_su.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_a_su.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_b1_mu.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_b2_mu.h
 create mode 100644 hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
 create mode 100644 hw/wcn8750/v1/mactx_ht_sig.h
 create mode 100644 hw/wcn8750/v1/mactx_l_sig_a.h
 create mode 100644 hw/wcn8750/v1/mactx_l_sig_b.h
 create mode 100644 hw/wcn8750/v1/mactx_phy_desc.h
 create mode 100644 hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
 create mode 100644 hw/wcn8750/v1/mactx_u_sig_eht_tb.h
 create mode 100644 hw/wcn8750/v1/mactx_user_desc_common.h
 create mode 100644 hw/wcn8750/v1/mactx_user_desc_per_user.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_a.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_su160.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_su20.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_su40.h
 create mode 100644 hw/wcn8750/v1/mactx_vht_sig_b_su80.h
 create mode 100644 hw/wcn8750/v1/mlo_sta_id_details.h
 create mode 100644 hw/wcn8750/v1/mon_buffer_addr.h
 create mode 100644 hw/wcn8750/v1/mon_destination_ring.h
 create mode 100644 hw/wcn8750/v1/mon_drop.h
 create mode 100644 hw/wcn8750/v1/mon_ingress_ring.h
 create mode 100644 hw/wcn8750/v1/msmhwiobase.h
 create mode 100644 hw/wcn8750/v1/msmhwioreg.h
 create mode 100644 hw/wcn8750/v1/no_ack_report.h
 create mode 100644 hw/wcn8750/v1/ofdma_trigger_details.h
 create mode 100644 hw/wcn8750/v1/pcu_ppdu_setup_init.h
 create mode 100644 hw/wcn8750/v1/pdg_response.h
 create mode 100644 hw/wcn8750/v1/pdg_response_rate_setting.h
 create mode 100644 hw/wcn8750/v1/pdg_tx_req.h
 create mode 100644 hw/wcn8750/v1/phyrx_abort_request_info.h
 create mode 100644 hw/wcn8750/v1/phyrx_common_user_info.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_a_su.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
 create mode 100644 hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
 create mode 100644 hw/wcn8750/v1/phyrx_ht_sig.h
 create mode 100644 hw/wcn8750/v1/phyrx_l_sig_a.h
 create mode 100644 hw/wcn8750/v1/phyrx_l_sig_b.h
 create mode 100644 hw/wcn8750/v1/phyrx_location.h
 create mode 100644 hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
 create mode 100644 hw/wcn8750/v1/phyrx_pkt_end.h
 create mode 100644 hw/wcn8750/v1/phyrx_pkt_end_info.h
 create mode 100644 hw/wcn8750/v1/phyrx_rssi_legacy.h
 create mode 100644 hw/wcn8750/v1/phyrx_user_info.h
 create mode 100644 hw/wcn8750/v1/phyrx_vht_sig_a.h
 create mode 100644 hw/wcn8750/v1/phytx_abort_request_info.h
 create mode 100644 hw/wcn8750/v1/phytx_pkt_end.h
 create mode 100644 hw/wcn8750/v1/phytx_ppdu_header_info_request.h
 create mode 100644 hw/wcn8750/v1/receive_pkt_start_info.h
 create mode 100644 hw/wcn8750/v1/receive_rssi_info.h
 create mode 100644 hw/wcn8750/v1/receive_user_info.h
 create mode 100644 hw/wcn8750/v1/received_response_user_15_8.h
 create mode 100644 hw/wcn8750/v1/received_response_user_23_16.h
 create mode 100644 hw/wcn8750/v1/received_response_user_31_24.h
 create mode 100644 hw/wcn8750/v1/received_response_user_36_32.h
 create mode 100644 hw/wcn8750/v1/received_response_user_7_0.h
 create mode 100644 hw/wcn8750/v1/received_response_user_info.h
 create mode 100644 hw/wcn8750/v1/received_trigger_info.h
 create mode 100644 hw/wcn8750/v1/received_trigger_info_details.h
 create mode 100644 hw/wcn8750/v1/reo_destination_ring.h
 create mode 100644 hw/wcn8750/v1/reo_destination_ring_with_pn.h
 create mode 100644 hw/wcn8750/v1/reo_entrance_ring.h
 create mode 100644 hw/wcn8750/v1/response_end_status.h
 create mode 100644 hw/wcn8750/v1/response_start_status.h
 create mode 100644 hw/wcn8750/v1/ru_allocation_160_info.h
 create mode 100644 hw/wcn8750/v1/rx_attention.h
 create mode 100644 hw/wcn8750/v1/rx_flow_search_entry.h
 create mode 100644 hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
 create mode 100644 hw/wcn8750/v1/rx_frame_bitmap_ack.h
 create mode 100644 hw/wcn8750/v1/rx_frame_bitmap_req.h
 create mode 100644 hw/wcn8750/v1/rx_location_info.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_desc_info.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_details.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_end.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_info.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_link_ptr.h
 create mode 100644 hw/wcn8750/v1/rx_mpdu_start.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_desc_info.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_details.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_end.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_ext_desc_info.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_link.h
 create mode 100644 hw/wcn8750/v1/rx_msdu_start.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_ack_report.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_end_user_stats.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_no_ack_report.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_start.h
 create mode 100644 hw/wcn8750/v1/rx_ppdu_start_user_info.h
 create mode 100644 hw/wcn8750/v1/rx_preamble.h
 create mode 100644 hw/wcn8750/v1/rx_response_required_info.h
 create mode 100644 hw/wcn8750/v1/rx_rxpcu_classification_overview.h
 create mode 100644 hw/wcn8750/v1/rx_start_param.h
 create mode 100644 hw/wcn8750/v1/rx_timing_info.h
 create mode 100644 hw/wcn8750/v1/rx_trig_info.h
 create mode 100644 hw/wcn8750/v1/rxpcu_early_rx_indication.h
 create mode 100644 hw/wcn8750/v1/rxpcu_ppdu_end_info.h
 create mode 100644 hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
 create mode 100644 hw/wcn8750/v1/rxpt_classify_info.h
 create mode 100644 hw/wcn8750/v1/seq_hwio.h
 create mode 100644 hw/wcn8750/v1/tcl_assist_cmd.h
 create mode 100644 hw/wcn8750/v1/tcl_status_ring.h
 create mode 100644 hw/wcn8750/v1/tlv_hdr.h
 create mode 100644 hw/wcn8750/v1/tlv_tag_def.h
 create mode 100644 hw/wcn8750/v1/tqm2sw_completion_ring.h
 create mode 100644 hw/wcn8750/v1/tx_cbf_info.h
 create mode 100644 hw/wcn8750/v1/tx_fes_setup.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_1k_ba.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_end.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_prot.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_start.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_start_ppdu.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_start_prot.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_user_ppdu.h
 create mode 100644 hw/wcn8750/v1/tx_fes_status_user_response.h
 create mode 100644 hw/wcn8750/v1/tx_flush_req.h
 create mode 100644 hw/wcn8750/v1/tx_mpdu_start.h
 create mode 100644 hw/wcn8750/v1/tx_msdu_extension.h
 create mode 100644 hw/wcn8750/v1/tx_msdu_start.h
 create mode 100644 hw/wcn8750/v1/tx_peer_entry.h
 create mode 100644 hw/wcn8750/v1/tx_queue_extension.h
 create mode 100644 hw/wcn8750/v1/tx_rate_stats_info.h
 create mode 100644 hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
 create mode 100644 hw/wcn8750/v1/txpcu_buffer_basics.h
 create mode 100644 hw/wcn8750/v1/txpcu_buffer_status.h
 create mode 100644 hw/wcn8750/v1/txpcu_user_buffer_status.h
 create mode 100644 hw/wcn8750/v1/u_sig_eht_su_mu_info.h
 create mode 100644 hw/wcn8750/v1/u_sig_eht_tb_info.h
 create mode 100644 hw/wcn8750/v1/unallocated_ru_160_info.h
 create mode 100644 hw/wcn8750/v1/uniform_descriptor_header.h
 create mode 100644 hw/wcn8750/v1/vht_sig_a_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_mu160_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_mu20_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_mu40_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_mu80_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_su160_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_su20_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_su40_info.h
 create mode 100644 hw/wcn8750/v1/vht_sig_b_su80_info.h
 create mode 100644 hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
 create mode 100644 hw/wcn8750/v1/wbm_buffer_ring.h
 create mode 100644 hw/wcn8750/v1/wbm_link_descriptor_ring.h
 create mode 100644 hw/wcn8750/v1/wbm_release_ring.h
 create mode 100644 hw/wcn8750/v1/wbm_release_ring_rx.h
 create mode 100644 hw/wcn8750/v1/wbm_release_ring_tx.h
 create mode 100644 hw/wcn8750/v1/wcss_seq_hwiobase.h
 create mode 100644 hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
 create mode 100644 hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
 create mode 100644 hw/wcn8750/v1/wcss_version.h

diff --git a/hw/wcn8750/v1/HALcomdef.h b/hw/wcn8750/v1/HALcomdef.h
new file mode 100644
index 000000000000..60ee92e6cd2e
--- /dev/null
+++ b/hw/wcn8750/v1/HALcomdef.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/hw/wcn8750/v1/HALhwio.h b/hw/wcn8750/v1/HALhwio.h
new file mode 100644
index 000000000000..059d69b1be87
--- /dev/null
+++ b/hw/wcn8750/v1/HALhwio.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  { \
+									static uint32   Readdata, Val_temp, Val; \
+									Readdata = HWIO_INX(base, hwiosym); \
+									Val_temp = Readdata & ~mask1 & ~mask2; \
+									Val = Val_temp | val1 | val2; \
+									HWIO_##hwiosym##_OUT(base, Val); \
+									}
+
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+											static uint32   Readdata, Val_temp, Val; \
+											Readdata = HWIO_INX(base, hwiosym); \
+											Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3; \
+											Val = Val_temp | val1 | val2 | val3; \
+											HWIO_##hwiosym##_OUT(base, Val); \
+											}
+
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+											static uint32   Readdata, Val_temp, Val; \
+											Readdata = HWIO_INX(base, hwiosym); \
+											Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3 & ~mask4; \
+											Val = Val_temp | val1 | val2 | val3 | val4; \
+											HWIO_##hwiosym##_OUT(base, Val); \
+											}
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask))
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/hw/wcn8750/v1/ack_report.h b/hw/wcn8750/v1/ack_report.h
new file mode 100644
index 000000000000..e78921b308fd
--- /dev/null
+++ b/hw/wcn8750/v1/ack_report.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t selfgen_response_reason                                 :  4,
+                      ax_trigger_type                                         :  4,
+                      sr_ppdu                                                 :  1,
+                      reserved                                                :  7,
+                      frame_control                                           : 16;
+#else
+             uint32_t frame_control                                           : 16,
+                      reserved                                                :  7,
+                      sr_ppdu                                                 :  1,
+                      ax_trigger_type                                         :  4,
+                      selfgen_response_reason                                 :  4;
+#endif
+};
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0
+
+#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
+#define ACK_REPORT_SR_PPDU_LSB                                                      8
+#define ACK_REPORT_SR_PPDU_MSB                                                      8
+#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100
+
+#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
+#define ACK_REPORT_RESERVED_LSB                                                     9
+#define ACK_REPORT_RESERVED_MSB                                                     15
+#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
+#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
+#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/boron_top_reg.h b/hw/wcn8750/v1/boron_top_reg.h
new file mode 100644
index 000000000000..306398284fe3
--- /dev/null
+++ b/hw/wcn8750/v1/boron_top_reg.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef BORON_TOP_REG_H
+#define BORON_TOP_REG_H
+
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
+
+#endif
diff --git a/hw/wcn8750/v1/buffer_addr_info.h b/hw/wcn8750/v1/buffer_addr_info.h
new file mode 100644
index 000000000000..d65375b54715
--- /dev/null
+++ b/hw/wcn8750/v1/buffer_addr_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t buffer_addr_39_32                                       :  8,
+                      return_buffer_manager                                   :  4,
+                      sw_buffer_cookie                                        : 20;
+#else
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      return_buffer_manager                                   :  4,
+                      buffer_addr_39_32                                       :  8;
+#endif
+};
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                                    0x00000000
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB                                       0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB                                       31
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK                                      0xffffffff
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                                   0x00000004
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB                                      0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB                                      7
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK                                     0x000000ff
+
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                               0x00000004
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                                  8
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                                  11
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                                 0x00000f00
+
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                                    0x00000004
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB                                       12
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB                                       31
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK                                      0xfffff000
+
+#endif
diff --git a/hw/wcn8750/v1/ce_src_desc.h b/hw/wcn8750/v1/ce_src_desc.h
new file mode 100644
index 000000000000..4ecaedcab2a7
--- /dev/null
+++ b/hw/wcn8750/v1/ce_src_desc.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t src_buffer_high                                         :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      ce_res_0                                                :  1,
+                      barrier_read                                            :  1,
+                      ce_res_1                                                :  2,
+                      length                                                  : 16;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_2                                                : 16;
+             uint32_t ce_res_3                                                : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t length                                                  : 16,
+                      ce_res_1                                                :  2,
+                      barrier_read                                            :  1,
+                      ce_res_0                                                :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      src_buffer_high                                         :  8;
+             uint32_t ce_res_2                                                : 16,
+                      fw_metadata                                             : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_3                                                : 20;
+#endif
+};
+
+#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET                                           0x00000000
+#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB                                              0
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB                                              31
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK                                             0xffffffff
+
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET                                          0x00000004
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB                                             0
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB                                             7
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK                                            0x000000ff
+
+#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET                                              0x00000004
+#define CE_SRC_DESC_TOEPLITZ_EN_LSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MASK                                                0x00000100
+
+#define CE_SRC_DESC_SRC_SWAP_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_SRC_SWAP_LSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MASK                                                   0x00000200
+
+#define CE_SRC_DESC_DEST_SWAP_OFFSET                                                0x00000004
+#define CE_SRC_DESC_DEST_SWAP_LSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MASK                                                  0x00000400
+
+#define CE_SRC_DESC_GATHER_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_GATHER_LSB                                                      11
+#define CE_SRC_DESC_GATHER_MSB                                                      11
+#define CE_SRC_DESC_GATHER_MASK                                                     0x00000800
+
+#define CE_SRC_DESC_CE_RES_0_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_0_LSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MASK                                                   0x00001000
+
+#define CE_SRC_DESC_BARRIER_READ_OFFSET                                             0x00000004
+#define CE_SRC_DESC_BARRIER_READ_LSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MASK                                               0x00002000
+
+#define CE_SRC_DESC_CE_RES_1_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_1_LSB                                                    14
+#define CE_SRC_DESC_CE_RES_1_MSB                                                    15
+#define CE_SRC_DESC_CE_RES_1_MASK                                                   0x0000c000
+
+#define CE_SRC_DESC_LENGTH_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_LENGTH_LSB                                                      16
+#define CE_SRC_DESC_LENGTH_MSB                                                      31
+#define CE_SRC_DESC_LENGTH_MASK                                                     0xffff0000
+
+#define CE_SRC_DESC_FW_METADATA_OFFSET                                              0x00000008
+#define CE_SRC_DESC_FW_METADATA_LSB                                                 0
+#define CE_SRC_DESC_FW_METADATA_MSB                                                 15
+#define CE_SRC_DESC_FW_METADATA_MASK                                                0x0000ffff
+
+#define CE_SRC_DESC_CE_RES_2_OFFSET                                                 0x00000008
+#define CE_SRC_DESC_CE_RES_2_LSB                                                    16
+#define CE_SRC_DESC_CE_RES_2_MSB                                                    31
+#define CE_SRC_DESC_CE_RES_2_MASK                                                   0xffff0000
+
+#define CE_SRC_DESC_CE_RES_3_OFFSET                                                 0x0000000c
+#define CE_SRC_DESC_CE_RES_3_LSB                                                    0
+#define CE_SRC_DESC_CE_RES_3_MSB                                                    19
+#define CE_SRC_DESC_CE_RES_3_MASK                                                   0x000fffff
+
+#define CE_SRC_DESC_RING_ID_OFFSET                                                  0x0000000c
+#define CE_SRC_DESC_RING_ID_LSB                                                     20
+#define CE_SRC_DESC_RING_ID_MSB                                                     27
+#define CE_SRC_DESC_RING_ID_MASK                                                    0x0ff00000
+
+#define CE_SRC_DESC_LOOPING_COUNT_OFFSET                                            0x0000000c
+#define CE_SRC_DESC_LOOPING_COUNT_LSB                                               28
+#define CE_SRC_DESC_LOOPING_COUNT_MSB                                               31
+#define CE_SRC_DESC_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/ce_stat_desc.h b/hw/wcn8750/v1/ce_stat_desc.h
new file mode 100644
index 000000000000..0b9f9a221215
--- /dev/null
+++ b/hw/wcn8750/v1/ce_stat_desc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ce_res_5                                                :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      barrier_read                                            :  1,
+                      ce_res_6                                                :  3,
+                      length                                                  : 16;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_7                                                :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t length                                                  : 16,
+                      ce_res_6                                                :  3,
+                      barrier_read                                            :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      ce_res_5                                                :  8;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_7                                                :  4,
+                      fw_metadata                                             : 16;
+#endif
+};
+
+#define CE_STAT_DESC_CE_RES_5_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_5_LSB                                                   0
+#define CE_STAT_DESC_CE_RES_5_MSB                                                   7
+#define CE_STAT_DESC_CE_RES_5_MASK                                                  0x000000ff
+
+#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET                                             0x00000000
+#define CE_STAT_DESC_TOEPLITZ_EN_LSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MASK                                               0x00000100
+
+#define CE_STAT_DESC_SRC_SWAP_OFFSET                                                0x00000000
+#define CE_STAT_DESC_SRC_SWAP_LSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MASK                                                  0x00000200
+
+#define CE_STAT_DESC_DEST_SWAP_OFFSET                                               0x00000000
+#define CE_STAT_DESC_DEST_SWAP_LSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MASK                                                 0x00000400
+
+#define CE_STAT_DESC_GATHER_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_GATHER_LSB                                                     11
+#define CE_STAT_DESC_GATHER_MSB                                                     11
+#define CE_STAT_DESC_GATHER_MASK                                                    0x00000800
+
+#define CE_STAT_DESC_BARRIER_READ_OFFSET                                            0x00000000
+#define CE_STAT_DESC_BARRIER_READ_LSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MASK                                              0x00001000
+
+#define CE_STAT_DESC_CE_RES_6_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_6_LSB                                                   13
+#define CE_STAT_DESC_CE_RES_6_MSB                                                   15
+#define CE_STAT_DESC_CE_RES_6_MASK                                                  0x0000e000
+
+#define CE_STAT_DESC_LENGTH_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_LENGTH_LSB                                                     16
+#define CE_STAT_DESC_LENGTH_MSB                                                     31
+#define CE_STAT_DESC_LENGTH_MASK                                                    0xffff0000
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET                                         0x00000004
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET                                         0x00000008
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_FW_METADATA_OFFSET                                             0x0000000c
+#define CE_STAT_DESC_FW_METADATA_LSB                                                0
+#define CE_STAT_DESC_FW_METADATA_MSB                                                15
+#define CE_STAT_DESC_FW_METADATA_MASK                                               0x0000ffff
+
+#define CE_STAT_DESC_CE_RES_7_OFFSET                                                0x0000000c
+#define CE_STAT_DESC_CE_RES_7_LSB                                                   16
+#define CE_STAT_DESC_CE_RES_7_MSB                                                   19
+#define CE_STAT_DESC_CE_RES_7_MASK                                                  0x000f0000
+
+#define CE_STAT_DESC_RING_ID_OFFSET                                                 0x0000000c
+#define CE_STAT_DESC_RING_ID_LSB                                                    20
+#define CE_STAT_DESC_RING_ID_MSB                                                    27
+#define CE_STAT_DESC_RING_ID_MASK                                                   0x0ff00000
+
+#define CE_STAT_DESC_LOOPING_COUNT_OFFSET                                           0x0000000c
+#define CE_STAT_DESC_LOOPING_COUNT_LSB                                              28
+#define CE_STAT_DESC_LOOPING_COUNT_MSB                                              31
+#define CE_STAT_DESC_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/coex_rx_status.h b/hw/wcn8750/v1/coex_rx_status.h
new file mode 100644
index 000000000000..7d9c6b4d2057
--- /dev/null
+++ b/hw/wcn8750/v1/coex_rx_status.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_RX_STATUS_H_
+#define _COEX_RX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_RX_STATUS 2
+
+#define NUM_OF_QWORDS_COEX_RX_STATUS 1
+
+struct coex_rx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_mac_frame_status                                     :  2,
+                      rx_with_tx_response                                     :  1,
+                      rx_rate                                                 :  5,
+                      rx_bw                                                   :  3,
+                      single_mpdu                                             :  1,
+                      filter_status                                           :  1,
+                      ampdu                                                   :  1,
+                      directed                                                :  1,
+                      reserved_0                                              :  1,
+                      rx_nss                                                  :  3,
+                      rx_rssi                                                 :  8,
+                      rx_type                                                 :  3,
+                      retry_bit_setting                                       :  1,
+                      more_data_bit_setting                                   :  1;
+             uint32_t remain_rx_packet_time                                   : 16,
+                      rx_remaining_fes_time                                   : 16;
+#else
+             uint32_t more_data_bit_setting                                   :  1,
+                      retry_bit_setting                                       :  1,
+                      rx_type                                                 :  3,
+                      rx_rssi                                                 :  8,
+                      rx_nss                                                  :  3,
+                      reserved_0                                              :  1,
+                      directed                                                :  1,
+                      ampdu                                                   :  1,
+                      filter_status                                           :  1,
+                      single_mpdu                                             :  1,
+                      rx_bw                                                   :  3,
+                      rx_rate                                                 :  5,
+                      rx_with_tx_response                                     :  1,
+                      rx_mac_frame_status                                     :  2;
+             uint32_t rx_remaining_fes_time                                   : 16,
+                      remain_rx_packet_time                                   : 16;
+#endif
+};
+
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB                                      0
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB                                      1
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK                                     0x0000000000000003
+
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET                                   0x0000000000000000
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK                                     0x0000000000000004
+
+#define COEX_RX_STATUS_RX_RATE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RATE_LSB                                                  3
+#define COEX_RX_STATUS_RX_RATE_MSB                                                  7
+#define COEX_RX_STATUS_RX_RATE_MASK                                                 0x00000000000000f8
+
+#define COEX_RX_STATUS_RX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_BW_LSB                                                    8
+#define COEX_RX_STATUS_RX_BW_MSB                                                    10
+#define COEX_RX_STATUS_RX_BW_MASK                                                   0x0000000000000700
+
+#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET                                           0x0000000000000000
+#define COEX_RX_STATUS_SINGLE_MPDU_LSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MASK                                             0x0000000000000800
+
+#define COEX_RX_STATUS_FILTER_STATUS_OFFSET                                         0x0000000000000000
+#define COEX_RX_STATUS_FILTER_STATUS_LSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MASK                                           0x0000000000001000
+
+#define COEX_RX_STATUS_AMPDU_OFFSET                                                 0x0000000000000000
+#define COEX_RX_STATUS_AMPDU_LSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MASK                                                   0x0000000000002000
+
+#define COEX_RX_STATUS_DIRECTED_OFFSET                                              0x0000000000000000
+#define COEX_RX_STATUS_DIRECTED_LSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MASK                                                0x0000000000004000
+
+#define COEX_RX_STATUS_RESERVED_0_OFFSET                                            0x0000000000000000
+#define COEX_RX_STATUS_RESERVED_0_LSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MASK                                              0x0000000000008000
+
+#define COEX_RX_STATUS_RX_NSS_OFFSET                                                0x0000000000000000
+#define COEX_RX_STATUS_RX_NSS_LSB                                                   16
+#define COEX_RX_STATUS_RX_NSS_MSB                                                   18
+#define COEX_RX_STATUS_RX_NSS_MASK                                                  0x0000000000070000
+
+#define COEX_RX_STATUS_RX_RSSI_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_RSSI_LSB                                                  19
+#define COEX_RX_STATUS_RX_RSSI_MSB                                                  26
+#define COEX_RX_STATUS_RX_RSSI_MASK                                                 0x0000000007f80000
+
+#define COEX_RX_STATUS_RX_TYPE_OFFSET                                               0x0000000000000000
+#define COEX_RX_STATUS_RX_TYPE_LSB                                                  27
+#define COEX_RX_STATUS_RX_TYPE_MSB                                                  29
+#define COEX_RX_STATUS_RX_TYPE_MASK                                                 0x0000000038000000
+
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET                                     0x0000000000000000
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK                                       0x0000000040000000
+
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK                                   0x0000000080000000
+
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB                                    32
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB                                    47
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK                                   0x0000ffff00000000
+
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET                                 0x0000000000000000
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB                                    48
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB                                    63
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK                                   0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/coex_tx_req.h b/hw/wcn8750/v1/coex_tx_req.h
new file mode 100644
index 000000000000..ed5b4c57bfd8
--- /dev/null
+++ b/hw/wcn8750/v1/coex_tx_req.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_REQ_H_
+#define _COEX_TX_REQ_H_
+
+#define NUM_OF_DWORDS_COEX_TX_REQ 6
+
+#define NUM_OF_QWORDS_COEX_TX_REQ 3
+
+struct coex_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      nss                                                     :  3,
+                      tx_chain_mask                                           :  8,
+                      bw                                                      :  3,
+                      reserved_0                                              :  2;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      reserved_1                                              :  2;
+             uint32_t tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8,
+                      wlan_request_duration                                   : 16;
+             uint32_t wlan_pkt_type                                           :  4,
+                      coex_tx_reason                                          :  2,
+                      response_frame_type                                     :  5,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_tx_priority                                        :  4,
+                      blackout_details_en                                     :  1,
+                      blackout_peek_duration                                  :  8,
+                      reserved_3a                                             :  5;
+             uint32_t frequency_channel_bonding_mask                          : 16,
+                      num_blackout_windows                                    :  8,
+                      reserved_4a                                             :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  2,
+                      bw                                                      :  3,
+                      tx_chain_mask                                           :  8,
+                      nss                                                     :  3,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8;
+             uint32_t reserved_1                                              :  2,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t wlan_request_duration                                   : 16,
+                      alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8;
+             uint32_t reserved_3a                                             :  5,
+                      blackout_peek_duration                                  :  8,
+                      blackout_details_en                                     :  1,
+                      coex_tx_priority                                        :  4,
+                      sch_tx_burst_ongoing                                    :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      response_frame_type                                     :  5,
+                      coex_tx_reason                                          :  2,
+                      wlan_pkt_type                                           :  4;
+             uint32_t reserved_4a                                             :  8,
+                      num_blackout_windows                                    :  8,
+                      frequency_channel_bonding_mask                          : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_REQ_TX_PWR_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_TX_PWR_LSB                                                      0
+#define COEX_TX_REQ_TX_PWR_MSB                                                      7
+#define COEX_TX_REQ_TX_PWR_MASK                                                     0x00000000000000ff
+
+#define COEX_TX_REQ_MIN_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_MIN_TX_PWR_LSB                                                  8
+#define COEX_TX_REQ_MIN_TX_PWR_MSB                                                  15
+#define COEX_TX_REQ_MIN_TX_PWR_MASK                                                 0x000000000000ff00
+
+#define COEX_TX_REQ_NSS_OFFSET                                                      0x0000000000000000
+#define COEX_TX_REQ_NSS_LSB                                                         16
+#define COEX_TX_REQ_NSS_MSB                                                         18
+#define COEX_TX_REQ_NSS_MASK                                                        0x0000000000070000
+
+#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET                                            0x0000000000000000
+#define COEX_TX_REQ_TX_CHAIN_MASK_LSB                                               19
+#define COEX_TX_REQ_TX_CHAIN_MASK_MSB                                               26
+#define COEX_TX_REQ_TX_CHAIN_MASK_MASK                                              0x0000000007f80000
+
+#define COEX_TX_REQ_BW_OFFSET                                                       0x0000000000000000
+#define COEX_TX_REQ_BW_LSB                                                          27
+#define COEX_TX_REQ_BW_MSB                                                          29
+#define COEX_TX_REQ_BW_MASK                                                         0x0000000038000000
+
+#define COEX_TX_REQ_RESERVED_0_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_0_LSB                                                  30
+#define COEX_TX_REQ_RESERVED_0_MSB                                                  31
+#define COEX_TX_REQ_RESERVED_0_MASK                                                 0x00000000c0000000
+
+#define COEX_TX_REQ_ALT_TX_PWR_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_PWR_LSB                                                  32
+#define COEX_TX_REQ_ALT_TX_PWR_MSB                                                  39
+#define COEX_TX_REQ_ALT_TX_PWR_MASK                                                 0x000000ff00000000
+
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET                                           0x0000000000000000
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB                                              40
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB                                              47
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK                                             0x0000ff0000000000
+
+#define COEX_TX_REQ_ALT_NSS_OFFSET                                                  0x0000000000000000
+#define COEX_TX_REQ_ALT_NSS_LSB                                                     48
+#define COEX_TX_REQ_ALT_NSS_MSB                                                     50
+#define COEX_TX_REQ_ALT_NSS_MASK                                                    0x0007000000000000
+
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET                                        0x0000000000000000
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB                                           51
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB                                           58
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK                                          0x07f8000000000000
+
+#define COEX_TX_REQ_ALT_BW_OFFSET                                                   0x0000000000000000
+#define COEX_TX_REQ_ALT_BW_LSB                                                      59
+#define COEX_TX_REQ_ALT_BW_MSB                                                      61
+#define COEX_TX_REQ_ALT_BW_MASK                                                     0x3800000000000000
+
+#define COEX_TX_REQ_RESERVED_1_OFFSET                                               0x0000000000000000
+#define COEX_TX_REQ_RESERVED_1_LSB                                                  62
+#define COEX_TX_REQ_RESERVED_1_MSB                                                  63
+#define COEX_TX_REQ_RESERVED_1_MASK                                                 0xc000000000000000
+
+#define COEX_TX_REQ_TX_PWR_1_OFFSET                                                 0x0000000000000008
+#define COEX_TX_REQ_TX_PWR_1_LSB                                                    0
+#define COEX_TX_REQ_TX_PWR_1_MSB                                                    7
+#define COEX_TX_REQ_TX_PWR_1_MASK                                                   0x00000000000000ff
+
+#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET                                             0x0000000000000008
+#define COEX_TX_REQ_ALT_TX_PWR_1_LSB                                                8
+#define COEX_TX_REQ_ALT_TX_PWR_1_MSB                                                15
+#define COEX_TX_REQ_ALT_TX_PWR_1_MASK                                               0x000000000000ff00
+
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET                                    0x0000000000000008
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB                                       16
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB                                       31
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK                                      0x00000000ffff0000
+
+#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET                                            0x0000000000000008
+#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB                                               32
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB                                               35
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK                                              0x0000000f00000000
+
+#define COEX_TX_REQ_COEX_TX_REASON_OFFSET                                           0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_REASON_LSB                                              36
+#define COEX_TX_REQ_COEX_TX_REASON_MSB                                              37
+#define COEX_TX_REQ_COEX_TX_REASON_MASK                                             0x0000003000000000
+
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB                                         38
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB                                         42
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK                                        0x000007c000000000
+
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET                        0x0000000000000008
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB                           43
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK                          0x0000080000000000
+
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET                       0x0000000000000008
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB                          44
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK                         0x0000100000000000
+
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET                                     0x0000000000000008
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB                                        45
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK                                       0x0000200000000000
+
+#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET                                         0x0000000000000008
+#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB                                            46
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB                                            49
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK                                           0x0003c00000000000
+
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET                                      0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB                                         50
+#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK                                        0x0004000000000000
+
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET                                   0x0000000000000008
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB                                      51
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB                                      58
+#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK                                     0x07f8000000000000
+
+#define COEX_TX_REQ_RESERVED_3A_OFFSET                                              0x0000000000000008
+#define COEX_TX_REQ_RESERVED_3A_LSB                                                 59
+#define COEX_TX_REQ_RESERVED_3A_MSB                                                 63
+#define COEX_TX_REQ_RESERVED_3A_MASK                                                0xf800000000000000
+
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET                           0x0000000000000010
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB                              0
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB                              15
+#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK                             0x000000000000ffff
+
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET                                     0x0000000000000010
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB                                        16
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB                                        23
+#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK                                       0x0000000000ff0000
+
+#define COEX_TX_REQ_RESERVED_4A_OFFSET                                              0x0000000000000010
+#define COEX_TX_REQ_RESERVED_4A_LSB                                                 24
+#define COEX_TX_REQ_RESERVED_4A_MSB                                                 31
+#define COEX_TX_REQ_RESERVED_4A_MASK                                                0x00000000ff000000
+
+#define COEX_TX_REQ_TLV64_PADDING_OFFSET                                            0x0000000000000010
+#define COEX_TX_REQ_TLV64_PADDING_LSB                                               32
+#define COEX_TX_REQ_TLV64_PADDING_MSB                                               63
+#define COEX_TX_REQ_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/coex_tx_status.h b/hw/wcn8750/v1/coex_tx_status.h
new file mode 100644
index 000000000000..c47c29c2a5ba
--- /dev/null
+++ b/hw/wcn8750/v1/coex_tx_status.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _COEX_TX_STATUS_H_
+#define _COEX_TX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_TX_STATUS 4
+
+#define NUM_OF_QWORDS_COEX_TX_STATUS 2
+
+struct coex_tx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  7,
+                      tx_bw                                                   :  3,
+                      tx_status_reason                                        :  3,
+                      tx_wait_ack                                             :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      current_tx_duration                                     : 16;
+             uint32_t next_rx_active_time                                     : 16,
+                      remaining_fes_time                                      : 16;
+             uint32_t tx_antenna_mask                                         :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      reserved_2                                              :  8;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t current_tx_duration                                     : 16,
+                      sch_tx_burst_ongoing                                    :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      tx_wait_ack                                             :  1,
+                      tx_status_reason                                        :  3,
+                      tx_bw                                                   :  3,
+                      reserved_0a                                             :  7;
+             uint32_t remaining_fes_time                                      : 16,
+                      next_rx_active_time                                     : 16;
+             uint32_t reserved_2                                              :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      tx_antenna_mask                                         :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define COEX_TX_STATUS_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_RESERVED_0A_LSB                                              0
+#define COEX_TX_STATUS_RESERVED_0A_MSB                                              6
+#define COEX_TX_STATUS_RESERVED_0A_MASK                                             0x000000000000007f
+
+#define COEX_TX_STATUS_TX_BW_OFFSET                                                 0x0000000000000000
+#define COEX_TX_STATUS_TX_BW_LSB                                                    7
+#define COEX_TX_STATUS_TX_BW_MSB                                                    9
+#define COEX_TX_STATUS_TX_BW_MASK                                                   0x0000000000000380
+
+#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET                                      0x0000000000000000
+#define COEX_TX_STATUS_TX_STATUS_REASON_LSB                                         10
+#define COEX_TX_STATUS_TX_STATUS_REASON_MSB                                         12
+#define COEX_TX_STATUS_TX_STATUS_REASON_MASK                                        0x0000000000001c00
+
+#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET                                           0x0000000000000000
+#define COEX_TX_STATUS_TX_WAIT_ACK_LSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MASK                                             0x0000000000002000
+
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK                                     0x0000000000004000
+
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET                                  0x0000000000000000
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK                                    0x0000000000008000
+
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB                                      16
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB                                      31
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK                                     0x00000000ffff0000
+
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET                                   0x0000000000000000
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB                                      32
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB                                      47
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK                                     0x0000ffff00000000
+
+#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET                                    0x0000000000000000
+#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB                                       48
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB                                       63
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK                                      0xffff000000000000
+
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET                                       0x0000000000000008
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB                                          0
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB                                          7
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK                                         0x00000000000000ff
+
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET                                     0x0000000000000008
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB                                        8
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB                                        15
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK                                       0x000000000000ff00
+
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET                                      0x0000000000000008
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB                                         16
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB                                         23
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK                                        0x0000000000ff0000
+
+#define COEX_TX_STATUS_RESERVED_2_OFFSET                                            0x0000000000000008
+#define COEX_TX_STATUS_RESERVED_2_LSB                                               24
+#define COEX_TX_STATUS_RESERVED_2_MSB                                               31
+#define COEX_TX_STATUS_RESERVED_2_MASK                                              0x00000000ff000000
+
+#define COEX_TX_STATUS_TLV64_PADDING_OFFSET                                         0x0000000000000008
+#define COEX_TX_STATUS_TLV64_PADDING_LSB                                            32
+#define COEX_TX_STATUS_TLV64_PADDING_MSB                                            63
+#define COEX_TX_STATUS_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/com_dtypes.h b/hw/wcn8750/v1/com_dtypes.h
new file mode 100644
index 000000000000..aa7bf7a51845
--- /dev/null
+++ b/hw/wcn8750/v1/com_dtypes.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE   1
+#define FALSE  0
+
+#define  ON   1
+#define  OFF  0
+
+#ifndef NULL
+  #define NULL  0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef  unsigned char      boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef  unsigned int  uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef  unsigned short     uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef  unsigned char      uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef  signed int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef  signed char        int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef  unsigned char      byte;
+#define  _BYTE_DEFINED
+#endif
+
+typedef  unsigned short     word;
+
+typedef  unsigned long      dword;
+
+typedef  unsigned char      uint1;
+
+typedef  unsigned short     uint2;
+
+typedef  unsigned long      uint4;
+
+typedef  signed char        int1;
+
+typedef  signed short       int2;
+
+typedef  long int           int4;
+
+typedef  signed long        sint31;
+
+typedef  signed short       sint15;
+
+typedef  signed char        sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+  #ifndef _INT64_DEFINED
+
+    typedef long long     int64;
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+
+    typedef  unsigned long long  uint64;
+    #define _UINT64_DEFINED
+  #endif
+#else
+
+  #if (defined __GNUC__)
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h b/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
new file mode 100644
index 000000000000..c9e20d75e648
--- /dev/null
+++ b/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      sta_coding                                              :  1,
+                      sta_spatial_config                                      :  6,
+                      reserved_0a                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0a                                             :  1,
+                      sta_spatial_config                                      :  6,
+                      sta_coding                                              :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET                                      0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB                                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB                                         10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK                                        0x000007ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET                                     0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB                                        11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB                                        14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK                                       0x00007800
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET                                  0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK                                    0x00008000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET                          0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB                             16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB                             21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK                            0x003f0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET                                 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK                                   0x00400000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                   0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                     0x00800000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET                           0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB                              24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB                              31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK                             0xff000000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB                         7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK                        0x000000ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB                         8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB                         15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK                        0x0000ff00
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB                         16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB                         23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK                        0x00ff0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB                         24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB                         31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK                        0xff000000
+
+#endif
diff --git a/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h b/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
new file mode 100644
index 000000000000..f2520cccfde9
--- /dev/null
+++ b/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  1,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET                                        0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB                                           0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB                                           10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK                                          0x000007ff
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET                                       0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB                                          11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB                                          14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK                                         0x00007800
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK                                     0x00008000
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET                                           0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB                                              16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB                                              19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK                                             0x000f0000
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET                                          0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK                                            0x00100000
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET                                    0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK                                      0x00200000
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK                                     0x00400000
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                     0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                       0x00800000
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET                             0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB                                24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB                                31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK                               0xff000000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB                           0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB                           7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK                          0x000000ff
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB                           8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB                           15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK                          0x0000ff00
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB                           16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB                           23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK                          0x00ff0000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB                           24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB                           31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK                          0xff000000
+
+#endif
diff --git a/hw/wcn8750/v1/eht_sig_usr_su_info.h b/hw/wcn8750/v1/eht_sig_usr_su_info.h
new file mode 100644
index 000000000000..208cb4de0539
--- /dev/null
+++ b/hw/wcn8750/v1/eht_sig_usr_su_info.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  9,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  9,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+#endif
+};
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET                                           0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB                                              0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB                                              10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK                                             0x000007ff
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET                                          0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB                                             11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB                                             14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK                                            0x00007800
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK                                        0x00008000
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET                                              0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB                                                 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB                                                 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK                                                0x000f0000
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET                                             0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK                                               0x00100000
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET                                       0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK                                         0x00200000
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB                                         22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB                                         30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK                                        0x7fc00000
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/expected_response.h b/hw/wcn8750/v1/expected_response.h
new file mode 100644
index 000000000000..0ef831133865
--- /dev/null
+++ b/hw/wcn8750/v1/expected_response.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _EXPECTED_RESPONSE_H_
+#define _EXPECTED_RESPONSE_H_
+
+#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
+
+#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
+
+struct expected_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t tx_ad2_47_32                                            : 16,
+                      expected_response_type                                  :  5,
+                      response_to_response                                    :  3,
+                      su_ba_user_number                                       :  1,
+                      response_info_part2_required                            :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      eht___reserved_g_0005_ndp_expected                                :  1,
+                      reserved_1                                              :  4;
+             uint32_t ndp_sta_partial_aid_2_8_0                               : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid1_8_0                                : 11;
+             uint32_t ast_index                                               : 16,
+                      capture_ack_ba_sounding                                 :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_320mhz                            :  1,
+                      reserved_3a                                             :  9;
+             uint32_t fcs                                                     :  9,
+                      expect_rx_with_blackout_details                         :  1,
+                      crc                                                     :  4,
+                      scrambler_seed                                          :  7,
+                      reserved_4b                                             : 11;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t reserved_1                                              :  4,
+                      eht___reserved_g_0005_ndp_expected                                :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      response_info_part2_required                            :  1,
+                      su_ba_user_number                                       :  1,
+                      response_to_response                                    :  3,
+                      expected_response_type                                  :  5,
+                      tx_ad2_47_32                                            : 16;
+             uint32_t ndp_sta_partial_aid1_8_0                                : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid_2_8_0                               : 11;
+             uint32_t reserved_3a                                             :  9,
+                      capture_sounding_1str_320mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_ack_ba_sounding                                 :  1,
+                      ast_index                                               : 16;
+             uint32_t reserved_4b                                             : 11,
+                      scrambler_seed                                          :  7,
+                      crc                                                     :  4,
+                      expect_rx_with_blackout_details                         :  1,
+                      fcs                                                     :  9;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET                                        0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB                                           0
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB                                           31
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK                                          0x00000000ffffffff
+
+#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET                                       0x0000000000000000
+#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB                                          32
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB                                          47
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK                                         0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET                             0x0000000000000000
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB                                48
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB                                52
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK                               0x001f000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET                               0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB                                  53
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB                                  55
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK                                 0x00e0000000000000
+
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET                                  0x0000000000000000
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB                                     56
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK                                    0x0100000000000000
+
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET                       0x0000000000000000
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB                          57
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK                         0x0200000000000000
+
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET                         0x0000000000000000
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB                            58
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK                           0x0400000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_1_OFFSET                                         0x0000000000000000
+#define EXPECTED_RESPONSE_RESERVED_1_LSB                                            60
+#define EXPECTED_RESPONSE_RESERVED_1_MSB                                            63
+#define EXPECTED_RESPONSE_RESERVED_1_MASK                                           0xf000000000000000
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET                          0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB                             0
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB                             10
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK                            0x00000000000007ff
+
+#define EXPECTED_RESPONSE_RESERVED_2_OFFSET                                         0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_2_LSB                                            11
+#define EXPECTED_RESPONSE_RESERVED_2_MSB                                            20
+#define EXPECTED_RESPONSE_RESERVED_2_MASK                                           0x00000000001ff800
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET                           0x0000000000000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB                              21
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB                              31
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK                             0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_AST_INDEX_OFFSET                                          0x0000000000000008
+#define EXPECTED_RESPONSE_AST_INDEX_LSB                                             32
+#define EXPECTED_RESPONSE_AST_INDEX_MSB                                             47
+#define EXPECTED_RESPONSE_AST_INDEX_MASK                                            0x0000ffff00000000
+
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET                            0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB                               48
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK                              0x0001000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB                           49
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK                          0x0002000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB                           50
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK                          0x0004000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET                        0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB                           51
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK                          0x0008000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB                          52
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK                         0x0010000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB                          53
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK                         0x0020000000000000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET                       0x0000000000000008
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB                          54
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK                         0x0040000000000000
+
+#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET                                        0x0000000000000008
+#define EXPECTED_RESPONSE_RESERVED_3A_LSB                                           55
+#define EXPECTED_RESPONSE_RESERVED_3A_MSB                                           63
+#define EXPECTED_RESPONSE_RESERVED_3A_MASK                                          0xff80000000000000
+
+#define EXPECTED_RESPONSE_FCS_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_FCS_LSB                                                   0
+#define EXPECTED_RESPONSE_FCS_MSB                                                   8
+#define EXPECTED_RESPONSE_FCS_MASK                                                  0x00000000000001ff
+
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                    0x0000000000000010
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                       9
+#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                      0x0000000000000200
+
+#define EXPECTED_RESPONSE_CRC_OFFSET                                                0x0000000000000010
+#define EXPECTED_RESPONSE_CRC_LSB                                                   10
+#define EXPECTED_RESPONSE_CRC_MSB                                                   13
+#define EXPECTED_RESPONSE_CRC_MASK                                                  0x0000000000003c00
+
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET                                     0x0000000000000010
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB                                        14
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB                                        20
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK                                       0x00000000001fc000
+
+#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET                                        0x0000000000000010
+#define EXPECTED_RESPONSE_RESERVED_4B_LSB                                           21
+#define EXPECTED_RESPONSE_RESERVED_4B_MSB                                           31
+#define EXPECTED_RESPONSE_RESERVED_4B_MASK                                          0x00000000ffe00000
+
+#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET                                      0x0000000000000010
+#define EXPECTED_RESPONSE_TLV64_PADDING_LSB                                         32
+#define EXPECTED_RESPONSE_TLV64_PADDING_MSB                                         63
+#define EXPECTED_RESPONSE_TLV64_PADDING_MASK                                        0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_a_mu_dl_info.h b/hw/wcn8750/v1/he_sig_a_mu_dl_info.h
new file mode 100644
index 000000000000..84571eb65d3b
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_a_mu_dl_info.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t dl_ul_flag                                              :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dcm_of_sig_b                                            :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  3,
+                      num_sig_b_symbols                                       :  4,
+                      comp_mode_sig_b                                         :  1,
+                      cp_ltf_size                                             :  2,
+                      doppler_indication                                      :  1,
+                      reserved_0a                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  1,
+                      num_ltf_symbols                                         :  3,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0a                                             :  6,
+                      doppler_indication                                      :  1,
+                      cp_ltf_size                                             :  2,
+                      comp_mode_sig_b                                         :  1,
+                      num_sig_b_symbols                                       :  4,
+                      transmit_bw                                             :  3,
+                      spatial_reuse                                           :  4,
+                      bss_color_id                                            :  6,
+                      dcm_of_sig_b                                            :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dl_ul_flag                                              :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET                                       0x00000000
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK                                         0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB                                        1
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB                                        3
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK                                       0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK                                       0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB                                        5
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB                                        10
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK                                       0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB                                       11
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB                                       14
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK                                      0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB                                         15
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB                                         17
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK                                        0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET                                0x00000000
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB                                   18
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB                                   21
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK                                  0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET                                  0x00000000
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK                                    0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB                                         23
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB                                         24
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK                                        0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET                               0x00000000
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK                                 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB                                         31
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK                                        0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET                                  0x00000004
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB                                     8
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB                                     10
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK                                    0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                0x00000004
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK                                  0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_STBC_LSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MASK                                               0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB                           13
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB                           14
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK                          0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                   0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_DL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_DL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_DL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_DL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_DL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_a_mu_ul_info.h b/hw/wcn8750/v1/he_sig_a_mu_ul_info.h
new file mode 100644
index 000000000000..e2d0ad73a66c
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_a_mu_ul_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           : 16,
+                      reserved_0a                                             :  1,
+                      transmit_bw                                             :  2,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  9,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      transmit_bw                                             :  2,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           : 16,
+                      bss_color_id                                            :  6,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      reserved_1a                                             :  9,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_a_su_info.h b/hw/wcn8750/v1/he_sig_a_su_info.h
new file mode 100644
index 000000000000..e4be3671016e
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_a_su_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      beam_change                                             :  1,
+                      dl_ul_flag                                              :  1,
+                      transmit_mcs                                            :  4,
+                      dcm                                                     :  1,
+                      bss_color_id                                            :  6,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  2,
+                      cp_ltf_size                                             :  2,
+                      nsts                                                    :  3,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      coding                                                  :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      txbf                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      reserved_1a                                             :  1,
+                      doppler_indication                                      :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      nsts                                                    :  3,
+                      cp_ltf_size                                             :  2,
+                      transmit_bw                                             :  2,
+                      spatial_reuse                                           :  4,
+                      reserved_0a                                             :  1,
+                      bss_color_id                                            :  6,
+                      dcm                                                     :  1,
+                      transmit_mcs                                            :  4,
+                      dl_ul_flag                                              :  1,
+                      beam_change                                             :  1,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      doppler_indication                                      :  1,
+                      reserved_1a                                             :  1,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      txbf                                                    :  1,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      coding                                                  :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET                                   0x00000000
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK                                     0x00000001
+
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK                                           0x00000002
+
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET                                          0x00000000
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK                                            0x00000004
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB                                           3
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB                                           6
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK                                          0x00000078
+
+#define HE_SIG_A_SU_INFO_DCM_OFFSET                                                 0x00000000
+#define HE_SIG_A_SU_INFO_DCM_LSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MASK                                                   0x00000080
+
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB                                           8
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB                                           13
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK                                          0x00003f00
+
+#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET                                       0x00000000
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB                                          15
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB                                          18
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK                                         0x00078000
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB                                            19
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB                                            20
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK                                           0x00180000
+
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB                                            21
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB                                            22
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK                                           0x00600000
+
+#define HE_SIG_A_SU_INFO_NSTS_OFFSET                                                0x00000000
+#define HE_SIG_A_SU_INFO_NSTS_LSB                                                   23
+#define HE_SIG_A_SU_INFO_NSTS_MSB                                                   25
+#define HE_SIG_A_SU_INFO_NSTS_MASK                                                  0x03800000
+
+#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB                                            26
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB                                            31
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK                                           0xfc000000
+
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET                                       0x00000004
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB                                          0
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB                                          6
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK                                         0x0000007f
+
+#define HE_SIG_A_SU_INFO_CODING_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_CODING_LSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MASK                                                0x00000080
+
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                   0x00000004
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK                                     0x00000100
+
+#define HE_SIG_A_SU_INFO_STBC_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_STBC_LSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MASK                                                  0x00000200
+
+#define HE_SIG_A_SU_INFO_TXBF_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TXBF_LSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MASK                                                  0x00000400
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB                              11
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB                              12
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK                             0x00001800
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                    0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                      0x00002000
+
+#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET                                         0x00000004
+#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET                                  0x00000004
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK                                    0x00008000
+
+#define HE_SIG_A_SU_INFO_CRC_OFFSET                                                 0x00000004
+#define HE_SIG_A_SU_INFO_CRC_LSB                                                    16
+#define HE_SIG_A_SU_INFO_CRC_MSB                                                    19
+#define HE_SIG_A_SU_INFO_CRC_MASK                                                   0x000f0000
+
+#define HE_SIG_A_SU_INFO_TAIL_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TAIL_LSB                                                   20
+#define HE_SIG_A_SU_INFO_TAIL_MSB                                                   25
+#define HE_SIG_A_SU_INFO_TAIL_MASK                                                  0x03f00000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK                                   0x04000000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB                                    27
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB                                    29
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK                                   0x38000000
+
+#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_RX_NDP_LSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MASK                                                0x40000000
+
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                             0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_b1_mu_info.h b/hw/wcn8750/v1/he_sig_b1_mu_info.h
new file mode 100644
index 000000000000..a248c3dc67b3
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_b1_mu_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation                                           :  8,
+                      reserved_0                                              : 23,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 23,
+                      ru_allocation                                           :  8;
+#endif
+};
+
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
+
+#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
+#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
+
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_b2_mu_info.h b/hw/wcn8750/v1/he_sig_b2_mu_info.h
new file mode 100644
index 000000000000..83d6f3bc843f
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_b2_mu_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
+
+struct he_sig_b2_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_spatial_config                                      :  4,
+                      sta_mcs                                                 :  4,
+                      reserved_set_to_1                                       :  1,
+                      sta_coding                                              :  1,
+                      reserved_0a                                             :  7,
+                      nsts                                                    :  3,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      nsts                                                    :  3,
+                      reserved_0a                                             :  7,
+                      sta_coding                                              :  1,
+                      reserved_set_to_1                                       :  1,
+                      sta_mcs                                                 :  4,
+                      sta_spatial_config                                      :  4,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
+#define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
+#define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
+#define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
+
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
+
+#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
+#define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
+#define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
+#define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
+
+#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
+#define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
+
+#define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
+#define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
+#define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
+#define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
+
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
+#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
+
+#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
+#define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
+#define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
+#define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
+
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/he_sig_b2_ofdma_info.h b/hw/wcn8750/v1/he_sig_b2_ofdma_info.h
new file mode 100644
index 000000000000..6357d216eb3a
--- /dev/null
+++ b/hw/wcn8750/v1/he_sig_b2_ofdma_info.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
+
+struct he_sig_b2_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      nsts                                                    :  3,
+                      txbf                                                    :  1,
+                      sta_mcs                                                 :  4,
+                      sta_dcm                                                 :  1,
+                      sta_coding                                              :  1,
+                      reserved_0                                              : 10,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 10,
+                      sta_coding                                              :  1,
+                      sta_dcm                                                 :  1,
+                      sta_mcs                                                 :  4,
+                      txbf                                                    :  1,
+                      nsts                                                    :  3,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET                                          0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB                                             0
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB                                             10
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK                                            0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB                                               11
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB                                               13
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK                                              0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK                                              0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB                                            18
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK                                           0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK                                           0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK                                        0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB                                         21
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB                                         30
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK                                        0x7fe00000
+
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET                                      0x00000004
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB                                         0
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB                                         7
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK                                        0x000000ff
+
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET                                         0x00000004
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB                                            8
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK                                           0x0000ff00
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET                                     0x00000004
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB                                        16
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB                                        31
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/ht_sig_info.h b/hw/wcn8750/v1/ht_sig_info.h
new file mode 100644
index 000000000000..d6a4a719e6e2
--- /dev/null
+++ b/hw/wcn8750/v1/ht_sig_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mcs                                                     :  7,
+                      cbw                                                     :  1,
+                      length                                                  : 16,
+                      reserved_0                                              :  8;
+             uint32_t smoothing                                               :  1,
+                      not_sounding                                            :  1,
+                      ht_reserved                                             :  1,
+                      aggregation                                             :  1,
+                      stbc                                                    :  2,
+                      fec_coding                                              :  1,
+                      short_gi                                                :  1,
+                      num_ext_sp_str                                          :  2,
+                      crc                                                     :  8,
+                      signal_tail                                             :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      length                                                  : 16,
+                      cbw                                                     :  1,
+                      mcs                                                     :  7;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      signal_tail                                             :  6,
+                      crc                                                     :  8,
+                      num_ext_sp_str                                          :  2,
+                      short_gi                                                :  1,
+                      fec_coding                                              :  1,
+                      stbc                                                    :  2,
+                      aggregation                                             :  1,
+                      ht_reserved                                             :  1,
+                      not_sounding                                            :  1,
+                      smoothing                                               :  1;
+#endif
+};
+
+#define HT_SIG_INFO_MCS_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_MCS_LSB                                                         0
+#define HT_SIG_INFO_MCS_MSB                                                         6
+#define HT_SIG_INFO_MCS_MASK                                                        0x0000007f
+
+#define HT_SIG_INFO_CBW_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_CBW_LSB                                                         7
+#define HT_SIG_INFO_CBW_MSB                                                         7
+#define HT_SIG_INFO_CBW_MASK                                                        0x00000080
+
+#define HT_SIG_INFO_LENGTH_OFFSET                                                   0x00000000
+#define HT_SIG_INFO_LENGTH_LSB                                                      8
+#define HT_SIG_INFO_LENGTH_MSB                                                      23
+#define HT_SIG_INFO_LENGTH_MASK                                                     0x00ffff00
+
+#define HT_SIG_INFO_RESERVED_0_OFFSET                                               0x00000000
+#define HT_SIG_INFO_RESERVED_0_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_0_MSB                                                  31
+#define HT_SIG_INFO_RESERVED_0_MASK                                                 0xff000000
+
+#define HT_SIG_INFO_SMOOTHING_OFFSET                                                0x00000004
+#define HT_SIG_INFO_SMOOTHING_LSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MASK                                                  0x00000001
+
+#define HT_SIG_INFO_NOT_SOUNDING_OFFSET                                             0x00000004
+#define HT_SIG_INFO_NOT_SOUNDING_LSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MASK                                               0x00000002
+
+#define HT_SIG_INFO_HT_RESERVED_OFFSET                                              0x00000004
+#define HT_SIG_INFO_HT_RESERVED_LSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MASK                                                0x00000004
+
+#define HT_SIG_INFO_AGGREGATION_OFFSET                                              0x00000004
+#define HT_SIG_INFO_AGGREGATION_LSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MASK                                                0x00000008
+
+#define HT_SIG_INFO_STBC_OFFSET                                                     0x00000004
+#define HT_SIG_INFO_STBC_LSB                                                        4
+#define HT_SIG_INFO_STBC_MSB                                                        5
+#define HT_SIG_INFO_STBC_MASK                                                       0x00000030
+
+#define HT_SIG_INFO_FEC_CODING_OFFSET                                               0x00000004
+#define HT_SIG_INFO_FEC_CODING_LSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MASK                                                 0x00000040
+
+#define HT_SIG_INFO_SHORT_GI_OFFSET                                                 0x00000004
+#define HT_SIG_INFO_SHORT_GI_LSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MASK                                                   0x00000080
+
+#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET                                           0x00000004
+#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB                                              8
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB                                              9
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK                                             0x00000300
+
+#define HT_SIG_INFO_CRC_OFFSET                                                      0x00000004
+#define HT_SIG_INFO_CRC_LSB                                                         10
+#define HT_SIG_INFO_CRC_MSB                                                         17
+#define HT_SIG_INFO_CRC_MASK                                                        0x0003fc00
+
+#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET                                              0x00000004
+#define HT_SIG_INFO_SIGNAL_TAIL_LSB                                                 18
+#define HT_SIG_INFO_SIGNAL_TAIL_MSB                                                 23
+#define HT_SIG_INFO_SIGNAL_TAIL_MASK                                                0x00fc0000
+
+#define HT_SIG_INFO_RESERVED_1_OFFSET                                               0x00000004
+#define HT_SIG_INFO_RESERVED_1_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_1_MSB                                                  30
+#define HT_SIG_INFO_RESERVED_1_MASK                                                 0x7f000000
+
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                                0x00000004
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                  0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/l_sig_a_info.h b/hw/wcn8750/v1/l_sig_a_info.h
new file mode 100644
index 000000000000..6da0725dfee7
--- /dev/null
+++ b/hw/wcn8750/v1/l_sig_a_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      lsig_reserved                                           :  1,
+                      length                                                  : 12,
+                      parity                                                  :  1,
+                      tail                                                    :  6,
+                      pkt_type                                                :  4,
+                      captured_implicit_sounding                              :  1,
+                      reserved                                                :  2,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                :  2,
+                      captured_implicit_sounding                              :  1,
+                      pkt_type                                                :  4,
+                      tail                                                    :  6,
+                      parity                                                  :  1,
+                      length                                                  : 12,
+                      lsig_reserved                                           :  1,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_A_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_RATE_LSB                                                       0
+#define L_SIG_A_INFO_RATE_MSB                                                       3
+#define L_SIG_A_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET                                           0x00000000
+#define L_SIG_A_INFO_LSIG_RESERVED_LSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MASK                                             0x00000010
+
+#define L_SIG_A_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_LENGTH_LSB                                                     5
+#define L_SIG_A_INFO_LENGTH_MSB                                                     16
+#define L_SIG_A_INFO_LENGTH_MASK                                                    0x0001ffe0
+
+#define L_SIG_A_INFO_PARITY_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_PARITY_LSB                                                     17
+#define L_SIG_A_INFO_PARITY_MSB                                                     17
+#define L_SIG_A_INFO_PARITY_MASK                                                    0x00020000
+
+#define L_SIG_A_INFO_TAIL_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_TAIL_LSB                                                       18
+#define L_SIG_A_INFO_TAIL_MSB                                                       23
+#define L_SIG_A_INFO_TAIL_MASK                                                      0x00fc0000
+
+#define L_SIG_A_INFO_PKT_TYPE_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_PKT_TYPE_LSB                                                   24
+#define L_SIG_A_INFO_PKT_TYPE_MSB                                                   27
+#define L_SIG_A_INFO_PKT_TYPE_MASK                                                  0x0f000000
+
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET                              0x00000000
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK                                0x10000000
+
+#define L_SIG_A_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_RESERVED_LSB                                                   29
+#define L_SIG_A_INFO_RESERVED_MSB                                                   30
+#define L_SIG_A_INFO_RESERVED_MASK                                                  0x60000000
+
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/l_sig_b_info.h b/hw/wcn8750/v1/l_sig_b_info.h
new file mode 100644
index 000000000000..f2052702e2de
--- /dev/null
+++ b/hw/wcn8750/v1/l_sig_b_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      length                                                  : 12,
+                      reserved                                                : 15,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                : 15,
+                      length                                                  : 12,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_B_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_B_INFO_RATE_LSB                                                       0
+#define L_SIG_B_INFO_RATE_MSB                                                       3
+#define L_SIG_B_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_B_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_B_INFO_LENGTH_LSB                                                     4
+#define L_SIG_B_INFO_LENGTH_MSB                                                     15
+#define L_SIG_B_INFO_LENGTH_MASK                                                    0x0000fff0
+
+#define L_SIG_B_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_B_INFO_RESERVED_LSB                                                   16
+#define L_SIG_B_INFO_RESERVED_MSB                                                   30
+#define L_SIG_B_INFO_RESERVED_MASK                                                  0x7fff0000
+
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/macrx_abort_request_info.h b/hw/wcn8750/v1/macrx_abort_request_info.h
new file mode 100644
index 000000000000..038f4038fa59
--- /dev/null
+++ b/hw/wcn8750/v1/macrx_abort_request_info.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t macrx_abort_reason                                      :  8,
+                      reserved_0                                              :  8;
+#else
+             uint16_t reserved_0                                              :  8,
+                      macrx_abort_reason                                      :  8;
+#endif
+};
+
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET                          0x00000000
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB                             0
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB                             7
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK                            0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     8
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x0000ff00
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h b/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
new file mode 100644
index 000000000000..f29ca356a223
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
+#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
+
+#include "eht_sig_usr_mu_mimo_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
+
+struct mactx_eht_sig_usr_mu_mimo {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#else
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h b/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
new file mode 100644
index 000000000000..24bf6691978d
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
+#define _MACTX_EHT_SIG_USR_OFDMA_H_
+
+#include "eht_sig_usr_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
+
+struct mactx_eht_sig_usr_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#else
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET  0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB     0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB     10
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK    0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB    11
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB    14
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK   0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET     0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB        16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB        19
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK       0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK      0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_su.h b/hw/wcn8750/v1/mactx_eht_sig_usr_su.h
new file mode 100644
index 000000000000..1fb82723c1ff
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_eht_sig_usr_su.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_EHT_SIG_USR_SU_H_
+#define _MACTX_EHT_SIG_USR_SU_H_
+
+#include "eht_sig_usr_su_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
+
+#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
+
+struct mactx_eht_sig_usr_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET        0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB           0
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB           10
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK          0x00000000000007ff
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET       0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB          11
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB          14
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK         0x0000000000007800
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK     0x0000000000008000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET           0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB              16
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB              19
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK             0x00000000000f0000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET          0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK            0x0000000000100000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET    0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK      0x0000000000200000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB      22
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB      30
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK     0x000000007fc00000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB                                      32
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB                                      63
+#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h b/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..438f3af6f9e7
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_DL_H_
+#define _MACTX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
+
+struct mactx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h b/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..96d2b912665a
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_MU_UL_H_
+#define _MACTX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
+
+struct mactx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_su.h b/hw/wcn8750/v1/mactx_he_sig_a_su.h
new file mode 100644
index 000000000000..e51241d26559
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_A_SU_H_
+#define _MACTX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
+
+struct mactx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_b1_mu.h b/hw/wcn8750/v1/mactx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..700528af2048
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B1_MU_H_
+#define _MACTX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
+
+struct mactx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_b2_mu.h b/hw/wcn8750/v1/mactx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..ccc1c593fed6
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_MU_H_
+#define _MACTX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
+
+struct mactx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h b/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..afc3c4b22841
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
+#define _MACTX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
+
+struct mactx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_ht_sig.h b/hw/wcn8750/v1/mactx_ht_sig.h
new file mode 100644
index 000000000000..ec28824c590f
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_HT_SIG_H_
+#define _MACTX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_MACTX_HT_SIG 2
+
+#define NUM_OF_QWORDS_MACTX_HT_SIG 1
+
+struct mactx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#endif
+};
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_l_sig_a.h b/hw/wcn8750/v1/mactx_l_sig_a.h
new file mode 100644
index 000000000000..061e46e28a2c
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_A_H_
+#define _MACTX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
+
+struct mactx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_l_sig_b.h b/hw/wcn8750/v1/mactx_l_sig_b.h
new file mode 100644
index 000000000000..6d533acef675
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_L_SIG_B_H_
+#define _MACTX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
+
+struct mactx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define MACTX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define MACTX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define MACTX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_phy_desc.h b/hw/wcn8750/v1/mactx_phy_desc.h
new file mode 100644
index 000000000000..ee4ccdf65c28
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_phy_desc.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_PHY_DESC_H_
+#define _MACTX_PHY_DESC_H_
+
+#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
+
+#define NUM_OF_QWORDS_MACTX_PHY_DESC 2
+
+struct mactx_phy_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             : 16,
+                      bf_type                                                 :  2,
+                      wait_sifs                                               :  2,
+                      dot11b_preamble_type                                    :  1,
+                      pkt_type                                                :  4,
+                      su_or_mu                                                :  2,
+                      mu_type                                                 :  1,
+                      bandwidth                                               :  3,
+                      channel_capture                                         :  1;
+             uint32_t mcs                                                     :  5,
+                      global_ofdma_mimo_enable                                :  1,
+                      stbc                                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8,
+                      measure_power                                           :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      back_to_back_transmission_expected                      :  1,
+                      heavy_clip_nss                                          :  3,
+                      txbf_per_packet_no_csd_no_walsh                         :  1;
+             uint32_t ndp                                                     :  3,
+                      ul_flag                                                 :  1,
+                      triggered                                               :  1,
+                      ap_pkt_bw                                               :  3,
+                      ru_position_start                                       :  8,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      tlv_source                                              :  1,
+                      reserved_2a                                             :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_2b                                             :  2,
+                      clpc_enable                                             :  1,
+                      mu_ndp                                                  :  1,
+                      response_expected                                       :  1;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_chain_mask_valid                                     :  1,
+                      ant_sel_valid                                           :  1,
+                      ant_sel                                                 :  1,
+                      cp_setting                                              :  2,
+                      he_ppdu_subtype                                         :  2,
+                      active_channel                                          :  3,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      ltf_size                                                :  2,
+                      ru_size_updated_v2                                      :  4,
+                      reserved_3c                                             :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+#else
+             uint32_t channel_capture                                         :  1,
+                      bandwidth                                               :  3,
+                      mu_type                                                 :  1,
+                      su_or_mu                                                :  2,
+                      pkt_type                                                :  4,
+                      dot11b_preamble_type                                    :  1,
+                      wait_sifs                                               :  2,
+                      bf_type                                                 :  2,
+                      reserved_0a                                             : 16;
+             uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
+                      heavy_clip_nss                                          :  3,
+                      back_to_back_transmission_expected                      :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      measure_power                                           :  1,
+                      tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      dot11ax_su_extended                                     :  1,
+                      stbc                                                    :  1,
+                      global_ofdma_mimo_enable                                :  1,
+                      mcs                                                     :  5;
+             uint32_t response_expected                                       :  1,
+                      mu_ndp                                                  :  1,
+                      clpc_enable                                             :  1,
+                      reserved_2b                                             :  2,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  1,
+                      tlv_source                                              :  1,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      ru_position_start                                       :  8,
+                      ap_pkt_bw                                               :  3,
+                      triggered                                               :  1,
+                      ul_flag                                                 :  1,
+                      ndp                                                     :  3;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_3c                                             :  1,
+                      ru_size_updated_v2                                      :  4,
+                      ltf_size                                                :  2,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      active_channel                                          :  3,
+                      he_ppdu_subtype                                         :  2,
+                      cp_setting                                              :  2,
+                      ant_sel                                                 :  1,
+                      ant_sel_valid                                           :  1,
+                      rx_chain_mask_valid                                     :  1,
+                      rx_chain_mask                                           :  8;
+#endif
+};
+
+#define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
+#define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
+#define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x000000000000ffff
+
+#define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
+#define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
+#define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x0000000000030000
+
+#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
+#define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
+#define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x00000000000c0000
+
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x0000000000000000
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x0000000000100000
+
+#define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
+#define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
+#define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x0000000001e00000
+
+#define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x0000000000000000
+#define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
+#define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
+#define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x0000000006000000
+
+#define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x0000000000000000
+#define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x0000000008000000
+
+#define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x0000000000000000
+#define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
+#define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
+#define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x0000000070000000
+
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x0000000080000000
+
+#define MACTX_PHY_DESC_MCS_OFFSET                                                   0x0000000000000000
+#define MACTX_PHY_DESC_MCS_LSB                                                      32
+#define MACTX_PHY_DESC_MCS_MSB                                                      36
+#define MACTX_PHY_DESC_MCS_MASK                                                     0x0000001f00000000
+
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x0000000000000000
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 37
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x0000002000000000
+
+#define MACTX_PHY_DESC_STBC_OFFSET                                                  0x0000000000000000
+#define MACTX_PHY_DESC_STBC_LSB                                                     38
+#define MACTX_PHY_DESC_STBC_MSB                                                     38
+#define MACTX_PHY_DESC_STBC_MASK                                                    0x0000004000000000
+
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      39
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x0000008000000000
+
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x0000000000000000
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           40
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x0000010000000000
+
+#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            41
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            48
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe0000000000
+
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x0000000000000000
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          49
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          56
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe000000000000
+
+#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x0000000000000000
+#define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            57
+#define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x0200000000000000
+
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x0000000000000000
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        58
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x0400000000000000
+
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x0000000000000000
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       59
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x0800000000000000
+
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x0000000000000000
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           60
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           62
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x7000000000000000
+
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x0000000000000000
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          63
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x8000000000000000
+
+#define MACTX_PHY_DESC_NDP_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NDP_LSB                                                      0
+#define MACTX_PHY_DESC_NDP_MSB                                                      2
+#define MACTX_PHY_DESC_NDP_MASK                                                     0x0000000000000007
+
+#define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_UL_FLAG_LSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MSB                                                  3
+#define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x0000000000000008
+
+#define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_TRIGGERED_LSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MSB                                                4
+#define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x0000000000000010
+
+#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x0000000000000008
+#define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                5
+#define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                7
+#define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x00000000000000e0
+
+#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        8
+#define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        15
+#define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x000000000000ff00
+
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x0000000000000008
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              16
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              18
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x0000000000070000
+
+#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               19
+#define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x0000000000080000
+
+#define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2A_LSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x0000000000100000
+
+#define MACTX_PHY_DESC_NSS_OFFSET                                                   0x0000000000000008
+#define MACTX_PHY_DESC_NSS_LSB                                                      21
+#define MACTX_PHY_DESC_NSS_MSB                                                      23
+#define MACTX_PHY_DESC_NSS_MASK                                                     0x0000000000e00000
+
+#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
+#define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
+#define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x0000000007000000
+
+#define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
+#define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
+#define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x0000000018000000
+
+#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x0000000020000000
+
+#define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x0000000000000008
+#define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x0000000040000000
+
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x0000000000000008
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x0000000080000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            32
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            39
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff00000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000000000008
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      40
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x0000010000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            41
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x0000020000000000
+
+#define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000000000008
+#define MACTX_PHY_DESC_ANT_SEL_LSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MSB                                                  42
+#define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x0000040000000000
+
+#define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000000000008
+#define MACTX_PHY_DESC_CP_SETTING_LSB                                               43
+#define MACTX_PHY_DESC_CP_SETTING_MSB                                               44
+#define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x0000180000000000
+
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000000000008
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          45
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          46
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x0000600000000000
+
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000000000008
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           47
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           49
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x0003800000000000
+
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000000000008
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           50
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x0004000000000000
+
+#define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000000000008
+#define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 51
+#define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 52
+#define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x0018000000000000
+
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000000000008
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       53
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       56
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e0000000000000
+
+#define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000000000008
+#define MACTX_PHY_DESC_RESERVED_3C_LSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MSB                                              57
+#define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x0200000000000000
+
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000000000008
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          58
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          63
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h b/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
new file mode 100644
index 000000000000..f46583e4c7ee
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
+#define _MACTX_U_SIG_EHT_SU_MU_H_
+
+#include "u_sig_eht_su_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
+
+struct mactx_u_sig_eht_su_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#else
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB    0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK   0x0000000000000007
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB    3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB    5
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK   0x0000000000000038
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET  0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK    0x0000000000000040
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB   7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB   12
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK  0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB  13
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB  19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB   20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB   24
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK  0x0000000001f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK   0x0000000002000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB    26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB    31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK   0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB    34
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK   0x0000000400000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB    40
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK   0x0000010000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET         0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB            48
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB            51
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK           0x000f000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB           52
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB           57
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK          0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB    59
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB    61
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK   0x3800000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB         62
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK        0x4000000000000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_u_sig_eht_tb.h b/hw/wcn8750/v1/mactx_u_sig_eht_tb.h
new file mode 100644
index 000000000000..5e57312a9da2
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_u_sig_eht_tb.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_U_SIG_EHT_TB_H_
+#define _MACTX_U_SIG_EHT_TB_H_
+
+#include "u_sig_eht_tb_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
+
+#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
+
+struct mactx_u_sig_eht_tb {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#else
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB          0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK         0x0000000000000007
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB          3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB          5
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK         0x0000000000000038
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET        0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK          0x0000000000000040
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB         7
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB         12
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK        0x0000000000001f80
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB        13
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB        19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK       0x00000000000fe000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB         20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB         25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK        0x0000000003f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB          26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB          31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK         0x00000000fc000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB          34
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK         0x0000000400000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET     0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB        35
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB        42
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK       0x000007f800000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET      0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB         43
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB         47
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK        0x0000f80000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET               0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB                  48
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB                  51
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK                 0x000f000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET              0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB                 52
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB                 57
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK                0x03f0000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET       0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB          58
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB          62
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK         0x7c00000000000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_user_desc_common.h b/hw/wcn8750/v1/mactx_user_desc_common.h
new file mode 100644
index 000000000000..04124271bbc9
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_user_desc_common.h
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_COMMON_H_
+#define _MACTX_USER_DESC_COMMON_H_
+
+#include "unallocated_ru_160_info.h"
+#include "ru_allocation_160_info.h"
+#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8
+
+struct mactx_user_desc_common {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      reserved_0b                                             :  5,
+                      ltf_size                                                :  2,
+                      reserved_0c                                             :  3,
+                      he_stf_long                                             :  1,
+                      reserved_0d                                             :  7,
+                      num_users_he_sigb_band0                                 :  8;
+             uint32_t num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  5,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1b                                             : 16;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      reserved                                                :  2,
+                      he_sigb_dcm                                             :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_compression                                     :  1,
+                      reserved_2c                                             : 15;
+             uint32_t he_sigb_0_mcs                                           :  3,
+                      reserved_3a                                             : 13,
+                      num_he_sigb_sym                                         :  5,
+                      center_ru_0                                             :  1,
+                      center_ru_1                                             :  1,
+                      reserved_3b                                             :  1,
+                      ftm_en                                                  :  1,
+                      pe_nss                                                  :  3,
+                      pe_ltf_size                                             :  2,
+                      pe_content                                              :  1,
+                      pe_chain_csd_en                                         :  1;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t num_data_symbols                                        : 16,
+                      ndp_ru_tone_set_index                                   :  7,
+                      ndp_feedback_status                                     :  1,
+                      doppler_indication                                      :  1,
+                      reserved_14a                                            :  7;
+             uint32_t spatial_reuse                                           : 16,
+                      distributed_ru                                          :  1,
+                      dru_spreading_bw                                        :  2,
+                      reserved_15a                                            : 13;
+#else
+             uint32_t num_users_he_sigb_band0                                 :  8,
+                      reserved_0d                                             :  7,
+                      he_stf_long                                             :  1,
+                      reserved_0c                                             :  3,
+                      ltf_size                                                :  2,
+                      reserved_0b                                             :  5,
+                      num_users                                               :  6;
+             uint32_t reserved_1b                                             : 16,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1a                                             :  5,
+                      num_ltf_symbols                                         :  3;
+             uint32_t reserved_2c                                             : 15,
+                      he_sigb_compression                                     :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_dcm                                             :  1,
+                      reserved                                                :  2,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t pe_chain_csd_en                                         :  1,
+                      pe_content                                              :  1,
+                      pe_ltf_size                                             :  2,
+                      pe_nss                                                  :  3,
+                      ftm_en                                                  :  1,
+                      reserved_3b                                             :  1,
+                      center_ru_1                                             :  1,
+                      center_ru_0                                             :  1,
+                      num_he_sigb_sym                                         :  5,
+                      reserved_3a                                             : 13,
+                      he_sigb_0_mcs                                           :  3;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t reserved_14a                                            :  7,
+                      doppler_indication                                      :  1,
+                      ndp_feedback_status                                     :  1,
+                      ndp_ru_tone_set_index                                   :  7,
+                      num_data_symbols                                        : 16;
+             uint32_t reserved_15a                                            : 13,
+                      dru_spreading_bw                                        :  2,
+                      distributed_ru                                          :  1,
+                      spatial_reuse                                           : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB                                        0
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB                                        5
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK                                       0x000000000000003f
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB                                      6
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB                                      10
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK                                     0x00000000000007c0
+
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET                                      0x0000000000000000
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB                                         11
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB                                         12
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK                                        0x0000000000001800
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB                                      13
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK                                     0x000000000000e000
+
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK                                     0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK                                     0x0000000000fe0000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB                          24
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB                          31
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK                         0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB                                  32
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB                                  34
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK                                 0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB                                      39
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK                                     0x000000f800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB                          40
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB                          47
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK                         0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET                                   0x0000000000000000
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB                                      48
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB                                      63
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK                                     0xffff000000000000
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET                     0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB                        0
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB                        1
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK                       0x0000000000000003
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                0x0000000000000004
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET                              0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB                                 3
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB                                 5
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK                                0x0000000000000038
+
+#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET                                      0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_LSB                                         6
+#define MACTX_USER_DESC_COMMON_RESERVED_MSB                                         7
+#define MACTX_USER_DESC_COMMON_RESERVED_MASK                                        0x00000000000000c0
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK                                     0x0000000000000100
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB                                      9
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK                                     0x000000000000fe00
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK                             0x0000000000010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB                                      31
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK                                     0x00000000fffe0000
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB                                    32
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB                                    34
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK                                   0x0000000700000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB                                      35
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB                                      47
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK                                     0x0000fff800000000
+
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB                                  48
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB                                  52
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK                                 0x001f000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB                                      53
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK                                     0x0020000000000000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB                                      54
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK                                     0x0040000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB                                      55
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK                                     0x0080000000000000
+
+#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_FTM_EN_LSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MSB                                           56
+#define MACTX_USER_DESC_COMMON_FTM_EN_MASK                                          0x0100000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET                                        0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_NSS_LSB                                           57
+#define MACTX_USER_DESC_COMMON_PE_NSS_MSB                                           59
+#define MACTX_USER_DESC_COMMON_PE_NSS_MASK                                          0x0e00000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB                                      60
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB                                      61
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK                                     0x3000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB                                       62
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK                                      0x4000000000000000
+
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB                                  63
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK                                 0x8000000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET        0x0000000000000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET        0x0000000000000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK          0x0000000000fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET        0x0000000000000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK          0x00000000fffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET        0x0000000000000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB           50
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB           63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK          0xfffc000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB      0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB      7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK     0x00000000000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB      8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB      15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK     0x000000000000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB      16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB      23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK     0x0000000000ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB      24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB      31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK     0x00000000ff000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB      32
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB      39
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK     0x000000ff00000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB      40
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB      47
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK     0x0000ff0000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB      48
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB      55
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK     0x00ff000000000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET   0x0000000000000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB      56
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB      63
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK     0xff00000000000000
+
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB                                 0
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB                                 15
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK                                0x000000000000ffff
+
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET                         0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB                            16
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB                            22
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK                           0x00000000007f0000
+
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET                           0x0000000000000038
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK                             0x0000000000800000
+
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET                            0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK                              0x0000000001000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB                                     25
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB                                     31
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK                                    0x00000000fe000000
+
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET                                 0x0000000000000038
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB                                    32
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB                                    47
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK                                   0x0000ffff00000000
+
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET                                0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB                                   48
+#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK                                  0x0001000000000000
+
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET                              0x0000000000000038
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB                                 49
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB                                 50
+#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK                                0x0006000000000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET                                  0x0000000000000038
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB                                     51
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB                                     63
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK                                    0xfff8000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_user_desc_per_user.h b/hw/wcn8750/v1/mactx_user_desc_per_user.h
new file mode 100644
index 000000000000..a68b50d9d639
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_user_desc_per_user.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_USER_DESC_PER_USER_H_
+#define _MACTX_USER_DESC_PER_USER_H_
+
+#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6
+
+#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3
+
+struct mactx_user_desc_per_user {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t psdu_length                                             : 24,
+                      reserved_0a                                             :  8;
+             uint32_t ru_start_index                                          :  8,
+                      ru_size                                                 :  4,
+                      reserved_1b                                             :  4,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_1c                                             :  1,
+                      mcs                                                     :  5,
+                      dcm                                                     :  1,
+                      reserved_1d                                             :  2;
+             uint32_t fec_type                                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      user_bf_type                                            :  2,
+                      a_factor_ldpc2x                                         :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      cw_len_2x                                               :  2,
+                      reserved_2b                                             :  1,
+                      drop_user_cbf                                           :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      cw_len_1x                                               :  2,
+                      ldpc1x_used                                             :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_2x_codeword                                        :  1,
+                      reserved_2d                                             :  5;
+             uint32_t sw_peer_id                                              : 16,
+                      per_user_subband_mask                                   : 16;
+             uint32_t ldpc_num_avbits                                         : 27,
+                      reserved_4a                                             :  5;
+             uint32_t num_cw_1x                                               : 16,
+                      num_cw_2x                                               : 16;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      psdu_length                                             : 24;
+             uint32_t reserved_1d                                             :  2,
+                      dcm                                                     :  1,
+                      mcs                                                     :  5,
+                      reserved_1c                                             :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      reserved_1b                                             :  4,
+                      ru_size                                                 :  4,
+                      ru_start_index                                          :  8;
+             uint32_t reserved_2d                                             :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ldpc2x_used                                             :  1,
+                      ldpc1x_used                                             :  1,
+                      cw_len_1x                                               :  2,
+                      extra_sym_ldpc1x                                        :  1,
+                      a_factor_ldpc1x                                         :  2,
+                      drop_user_cbf                                           :  1,
+                      reserved_2b                                             :  1,
+                      cw_len_2x                                               :  2,
+                      extra_sym_ldpc2x                                        :  1,
+                      a_factor_ldpc2x                                         :  2,
+                      user_bf_type                                            :  2,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      fec_type                                                :  1;
+             uint32_t per_user_subband_mask                                   : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_4a                                             :  5,
+                      ldpc_num_avbits                                         : 27;
+             uint32_t num_cw_2x                                               : 16,
+                      num_cw_1x                                               : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB                                    0
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK                                   0x0000000000ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB                                    24
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK                                   0x00000000ff000000
+
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET                              0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB                                 32
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB                                 39
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK                                0x000000ff00000000
+
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET                                     0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB                                        40
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB                                        43
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK                                       0x00000f0000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB                                    44
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB                                    47
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK                                   0x0000f00000000000
+
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET                       0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB                          48
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK                         0x0001000000000000
+
+#define MACTX_USER_DESC_PER_USER_NSS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_NSS_LSB                                            49
+#define MACTX_USER_DESC_PER_USER_NSS_MSB                                            51
+#define MACTX_USER_DESC_PER_USER_NSS_MASK                                           0x000e000000000000
+
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET                               0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB                                  52
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB                                  54
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK                                 0x0070000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB                                    55
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK                                   0x0080000000000000
+
+#define MACTX_USER_DESC_PER_USER_MCS_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_MCS_LSB                                            56
+#define MACTX_USER_DESC_PER_USER_MCS_MSB                                            60
+#define MACTX_USER_DESC_PER_USER_MCS_MASK                                           0x1f00000000000000
+
+#define MACTX_USER_DESC_PER_USER_DCM_OFFSET                                         0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_DCM_LSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MSB                                            61
+#define MACTX_USER_DESC_PER_USER_DCM_MASK                                           0x2000000000000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET                                 0x0000000000000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB                                    62
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB                                    63
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK                                   0xc000000000000000
+
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET                                    0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK                                      0x0000000000000001
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK                                   0x0000000000000002
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB                                      2
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB                                      3
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK                                     0x000000000000000c
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB                                      4
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB                                      5
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK                                     0x0000000000000030
+
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB                                      6
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB                                      7
+#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK                                     0x00000000000000c0
+
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET                                0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB                                   8
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB                                   9
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK                                  0x0000000000000300
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB                                10
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB                                11
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK                               0x0000000000000c00
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB                               12
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK                              0x0000000000001000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB                                      13
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB                                      14
+#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK                                     0x0000000000006000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK                                   0x0000000000008000
+
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET                               0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK                                 0x0000000000010000
+
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET                             0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB                                17
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB                                18
+#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK                               0x0000000000060000
+
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB                               19
+#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK                              0x0000000000080000
+
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET                                   0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB                                      20
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB                                      21
+#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK                                     0x0000000000300000
+
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB                                    22
+#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK                                   0x0000000000400000
+
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK                                   0x0000000000800000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET                           0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK                             0x0000000001000000
+
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET                          0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK                            0x0000000002000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET                            0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB                               26
+#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK                              0x0000000004000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET                                 0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET                                  0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB                                     32
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB                                     47
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK                                    0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET                       0x0000000000000008
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB                          48
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB                          63
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK                         0xffff000000000000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET                             0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB                                0
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB                                26
+#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK                               0x0000000007ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB                                    27
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK                                   0x00000000f8000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB                                      32
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB                                      47
+#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK                                     0x0000ffff00000000
+
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET                                   0x0000000000000010
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB                                      48
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB                                      63
+#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_a.h b/hw/wcn8750/v1/mactx_vht_sig_a.h
new file mode 100644
index 000000000000..6dec145785d6
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_A_H_
+#define _MACTX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
+
+struct mactx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h b/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
new file mode 100644
index 000000000000..b66278da930b
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU160_H_
+#define _MACTX_VHT_SIG_B_MU160_H_
+
+#include "vht_sig_b_mu160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
+
+struct mactx_vht_sig_b_mu160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#else
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB         18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK        0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET         0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB            19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB            22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK           0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK    0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK    0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK    0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB  50
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB     51
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB     54
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK    0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB     63
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK    0xe000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h b/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
new file mode 100644
index 000000000000..95feca30eaa3
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU20_H_
+#define _MACTX_VHT_SIG_B_MU20_H_
+
+#include "vht_sig_b_mu20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
+
+struct mactx_vht_sig_b_mu20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB           15
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK          0x000000000000ffff
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB              16
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB              19
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK             0x00000000000f0000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB   26
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB   28
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK  0x000000001c000000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h b/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
new file mode 100644
index 000000000000..c770db089203
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU40_H_
+#define _MACTX_VHT_SIG_B_MU40_H_
+
+#include "vht_sig_b_mu40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
+
+struct mactx_vht_sig_b_mu40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#else
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB              17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB              20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK             0x00000000001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB       27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB       28
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK      0x0000000018000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB      48
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0001ffff00000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB         49
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB         52
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK        0x001e000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB       59
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK      0xf800000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h b/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
new file mode 100644
index 000000000000..9e39d240b618
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_MU80_H_
+#define _MACTX_VHT_SIG_B_MU80_H_
+
+#include "vht_sig_b_mu80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
+
+struct mactx_vht_sig_b_mu80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#else
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET           0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB              19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB              22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK             0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK      0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK      0xe000000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK      0x0000000000780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK  0x00000000e0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB    50
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB       51
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB       54
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK      0x0078000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB       63
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK      0xe000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su160.h b/hw/wcn8750/v1/mactx_vht_sig_b_su160.h
new file mode 100644
index 000000000000..01bc54e5ab89
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_su160.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU160_H_
+#define _MACTX_VHT_SIG_B_SU160_H_
+
+#include "vht_sig_b_su160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
+
+struct mactx_vht_sig_b_su160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#else
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB         20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK        0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB  21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB  22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK          0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK        0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET  0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET  0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK    0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB  32
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB  52
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB    55
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB    60
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB     61
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB     62
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK    0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB  63
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su20.h b/hw/wcn8750/v1/mactx_vht_sig_b_su20.h
new file mode 100644
index 000000000000..c297cc0785e3
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_su20.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU20_H_
+#define _MACTX_VHT_SIG_B_SU20_H_
+
+#include "vht_sig_b_su20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
+
+struct mactx_vht_sig_b_su20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK          0x000000000001ffff
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB    17
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB    19
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK   0x00000000000e0000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK            0x0000000003f00000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB         26
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK        0x000000007c000000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET                                   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB                                      32
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB                                      63
+#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su40.h b/hw/wcn8750/v1/mactx_vht_sig_b_su40.h
new file mode 100644
index 000000000000..002d72c430ca
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_su40.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU40_H_
+#define _MACTX_VHT_SIG_B_SU40_H_
+
+#include "vht_sig_b_su40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
+
+struct mactx_vht_sig_b_su40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#else
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK          0x000000000007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB    19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB    20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK            0x0000000007e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET      0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB         27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK        0x0000000078000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB      32
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB      50
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0007ffff00000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB        53
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB        58
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e0000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB    59
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB    62
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK   0x7800000000000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB      63
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK     0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su80.h b/hw/wcn8750/v1/mactx_vht_sig_b_su80.h
new file mode 100644
index 000000000000..b15646f03f4a
--- /dev/null
+++ b/hw/wcn8750/v1/mactx_vht_sig_b_su80.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MACTX_VHT_SIG_B_SU80_H_
+#define _MACTX_VHT_SIG_B_SU80_H_
+
+#include "vht_sig_b_su80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
+
+#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
+
+struct mactx_vht_sig_b_su80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#else
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB           20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK          0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB    21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB    22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK   0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK            0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET        0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK          0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET    0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK   0x8000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x00000000001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x000000001f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK      0x0000000060000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK   0x0000000080000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB    32
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB    52
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x001fffff00000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB      55
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB      60
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f80000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB       61
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB       62
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK      0x6000000000000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB    63
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK   0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mlo_sta_id_details.h b/hw/wcn8750/v1/mlo_sta_id_details.h
new file mode 100644
index 000000000000..952056890206
--- /dev/null
+++ b/hw/wcn8750/v1/mlo_sta_id_details.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MLO_STA_ID_DETAILS_H_
+#define _MLO_STA_ID_DETAILS_H_
+
+#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
+
+struct mlo_sta_id_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t nstr_mlo_sta_id                                         : 10,
+                      block_self_ml_sync                                      :  1,
+                      block_partner_ml_sync                                   :  1,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      reserved_0a                                             :  3;
+#else
+             uint16_t reserved_0a                                             :  3,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      block_partner_ml_sync                                   :  1,
+                      block_self_ml_sync                                      :  1,
+                      nstr_mlo_sta_id                                         : 10;
+#endif
+};
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET                                   0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB                                      0
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB                                      9
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK                                     0x000003ff
+
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET                                0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK                                  0x00000400
+
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK                               0x00000800
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK                               0x00001000
+
+#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET                                       0x00000000
+#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB                                          13
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB                                          15
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK                                         0x0000e000
+
+#endif
diff --git a/hw/wcn8750/v1/mon_buffer_addr.h b/hw/wcn8750/v1/mon_buffer_addr.h
new file mode 100644
index 000000000000..8cb6f5fd57b9
--- /dev/null
+++ b/hw/wcn8750/v1/mon_buffer_addr.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_BUFFER_ADDR_H_
+#define _MON_BUFFER_ADDR_H_
+
+#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
+
+#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
+
+struct mon_buffer_addr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t dma_length                                              : 12,
+                      reserved_2a                                             :  4,
+                      msdu_continuation                                       :  1,
+                      truncated                                               :  1,
+                      reserved_2b                                             : 14;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reserved_2b                                             : 14,
+                      truncated                                               :  1,
+                      msdu_continuation                                       :  1,
+                      reserved_2a                                             :  4,
+                      dma_length                                              : 12;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET                                0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB                                   0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB                                   31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK                                  0x00000000ffffffff
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET                               0x0000000000000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB                                  32
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB                                  63
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK                                 0xffffffff00000000
+
+#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET                                           0x0000000000000008
+#define MON_BUFFER_ADDR_DMA_LENGTH_LSB                                              0
+#define MON_BUFFER_ADDR_DMA_LENGTH_MSB                                              11
+#define MON_BUFFER_ADDR_DMA_LENGTH_MASK                                             0x0000000000000fff
+
+#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2A_LSB                                             12
+#define MON_BUFFER_ADDR_RESERVED_2A_MSB                                             15
+#define MON_BUFFER_ADDR_RESERVED_2A_MASK                                            0x000000000000f000
+
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET                                    0x0000000000000008
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK                                      0x0000000000010000
+
+#define MON_BUFFER_ADDR_TRUNCATED_OFFSET                                            0x0000000000000008
+#define MON_BUFFER_ADDR_TRUNCATED_LSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MASK                                              0x0000000000020000
+
+#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET                                          0x0000000000000008
+#define MON_BUFFER_ADDR_RESERVED_2B_LSB                                             18
+#define MON_BUFFER_ADDR_RESERVED_2B_MSB                                             31
+#define MON_BUFFER_ADDR_RESERVED_2B_MASK                                            0x00000000fffc0000
+
+#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET                                        0x0000000000000008
+#define MON_BUFFER_ADDR_TLV64_PADDING_LSB                                           32
+#define MON_BUFFER_ADDR_TLV64_PADDING_MSB                                           63
+#define MON_BUFFER_ADDR_TLV64_PADDING_MASK                                          0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/mon_destination_ring.h b/hw/wcn8750/v1/mon_destination_ring.h
new file mode 100644
index 000000000000..1f373b585fd5
--- /dev/null
+++ b/hw/wcn8750/v1/mon_destination_ring.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DESTINATION_RING_H_
+#define _MON_DESTINATION_RING_H_
+
+#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
+
+struct mon_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t end_offset                                              : 12,
+                      reserved_3a                                             :  2,
+                      link_info                                               :  2,
+                      end_reason                                              :  2,
+                      initiator                                               :  1,
+                      empty_descriptor                                        :  1,
+                      pkt_buffer_cnt                                          :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t looping_count                                           :  4,
+                      pkt_buffer_cnt                                          :  8,
+                      empty_descriptor                                        :  1,
+                      initiator                                               :  1,
+                      end_reason                                              :  2,
+                      link_info                                               :  2,
+                      reserved_3a                                             :  2,
+                      end_offset                                              : 12;
+#endif
+};
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET                         0x00000000
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB                            0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB                            31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK                           0xffffffff
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET                        0x00000004
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB                           0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB                           31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK                          0xffffffff
+
+#define MON_DESTINATION_RING_PPDU_ID_OFFSET                                         0x00000008
+#define MON_DESTINATION_RING_PPDU_ID_LSB                                            0
+#define MON_DESTINATION_RING_PPDU_ID_MSB                                            31
+#define MON_DESTINATION_RING_PPDU_ID_MASK                                           0xffffffff
+
+#define MON_DESTINATION_RING_END_OFFSET_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_OFFSET_LSB                                         0
+#define MON_DESTINATION_RING_END_OFFSET_MSB                                         11
+#define MON_DESTINATION_RING_END_OFFSET_MASK                                        0x00000fff
+
+#define MON_DESTINATION_RING_RESERVED_3A_OFFSET                                     0x0000000c
+#define MON_DESTINATION_RING_RESERVED_3A_LSB                                        12
+#define MON_DESTINATION_RING_RESERVED_3A_MSB                                        13
+#define MON_DESTINATION_RING_RESERVED_3A_MASK                                       0x00003000
+
+#define MON_DESTINATION_RING_LINK_INFO_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_LINK_INFO_LSB                                          14
+#define MON_DESTINATION_RING_LINK_INFO_MSB                                          15
+#define MON_DESTINATION_RING_LINK_INFO_MASK                                         0x0000c000
+
+#define MON_DESTINATION_RING_END_REASON_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_REASON_LSB                                         16
+#define MON_DESTINATION_RING_END_REASON_MSB                                         17
+#define MON_DESTINATION_RING_END_REASON_MASK                                        0x00030000
+
+#define MON_DESTINATION_RING_INITIATOR_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_INITIATOR_LSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MASK                                         0x00040000
+
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET                                0x0000000c
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK                                  0x00080000
+
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET                                  0x0000000c
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB                                     20
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB                                     27
+#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK                                    0x0ff00000
+
+#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000000c
+#define MON_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define MON_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define MON_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/mon_drop.h b/hw/wcn8750/v1/mon_drop.h
new file mode 100644
index 000000000000..d1135ecd0dc2
--- /dev/null
+++ b/hw/wcn8750/v1/mon_drop.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_DROP_H_
+#define _MON_DROP_H_
+
+#define NUM_OF_DWORDS_MON_DROP 2
+
+#define NUM_OF_QWORDS_MON_DROP 1
+
+struct mon_drop {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t ppdu_drop_cnt                                           : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      tlv_drop_cnt                                            : 10,
+                      end_of_ppdu_seen                                        :  1,
+                      reserved_1a                                             :  1;
+#else
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t reserved_1a                                             :  1,
+                      end_of_ppdu_seen                                        :  1,
+                      tlv_drop_cnt                                            : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      ppdu_drop_cnt                                           : 10;
+#endif
+};
+
+#define MON_DROP_PPDU_ID_OFFSET                                                     0x0000000000000000
+#define MON_DROP_PPDU_ID_LSB                                                        0
+#define MON_DROP_PPDU_ID_MSB                                                        31
+#define MON_DROP_PPDU_ID_MASK                                                       0x00000000ffffffff
+
+#define MON_DROP_PPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_PPDU_DROP_CNT_LSB                                                  32
+#define MON_DROP_PPDU_DROP_CNT_MSB                                                  41
+#define MON_DROP_PPDU_DROP_CNT_MASK                                                 0x000003ff00000000
+
+#define MON_DROP_MPDU_DROP_CNT_OFFSET                                               0x0000000000000000
+#define MON_DROP_MPDU_DROP_CNT_LSB                                                  42
+#define MON_DROP_MPDU_DROP_CNT_MSB                                                  51
+#define MON_DROP_MPDU_DROP_CNT_MASK                                                 0x000ffc0000000000
+
+#define MON_DROP_TLV_DROP_CNT_OFFSET                                                0x0000000000000000
+#define MON_DROP_TLV_DROP_CNT_LSB                                                   52
+#define MON_DROP_TLV_DROP_CNT_MSB                                                   61
+#define MON_DROP_TLV_DROP_CNT_MASK                                                  0x3ff0000000000000
+
+#define MON_DROP_END_OF_PPDU_SEEN_OFFSET                                            0x0000000000000000
+#define MON_DROP_END_OF_PPDU_SEEN_LSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MSB                                               62
+#define MON_DROP_END_OF_PPDU_SEEN_MASK                                              0x4000000000000000
+
+#define MON_DROP_RESERVED_1A_OFFSET                                                 0x0000000000000000
+#define MON_DROP_RESERVED_1A_LSB                                                    63
+#define MON_DROP_RESERVED_1A_MSB                                                    63
+#define MON_DROP_RESERVED_1A_MASK                                                   0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/mon_ingress_ring.h b/hw/wcn8750/v1/mon_ingress_ring.h
new file mode 100644
index 000000000000..76f4e80417e0
--- /dev/null
+++ b/hw/wcn8750/v1/mon_ingress_ring.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _MON_INGRESS_RING_H_
+#define _MON_INGRESS_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_MON_INGRESS_RING 4
+
+struct mon_ingress_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#endif
+};
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB              0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB             0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB             7
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB         8
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB         11
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB              12
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET                               0x00000008
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB                                  0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB                                  31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK                                 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET                              0x0000000c
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB                                 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB                                 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK                                0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/msmhwiobase.h b/hw/wcn8750/v1/msmhwiobase.h
new file mode 100644
index 000000000000..613be3cf2136
--- /dev/null
+++ b/hw/wcn8750/v1/msmhwiobase.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef MSMHWIOBASE_H
+#define MSMHWIOBASE_H
+
+#define HOST_WCSS_WCSS_BASE                                                0x0
+#define HOST_WCSS_WCSS_BASE_SIZE                                    0x00d00000
+#define HOST_WCSS_WCSS_BASE_PHYS                                    0x00000000
+
+#define HOST_HZ_AUXSSAUXSS_SWI_BASE                                  0x1900000
+#define HOST_HZ_AUXSSAUXSS_SWI_BASE_SIZE                            0x00007000
+#define HOST_HZ_AUXSSAUXSS_SWI_BASE_PHYS                            0x01900000
+
+#define HOST_WLAN_HZ_ZEALIS_AON_BASE                                 0x1907000
+#define HOST_WLAN_HZ_ZEALIS_AON_BASE_SIZE                           0x00019000
+#define HOST_WLAN_HZ_ZEALIS_AON_BASE_PHYS                           0x01907000
+
+#define HOST_TLMM_BASE                                               0x1a00000
+#define HOST_TLMM_BASE_SIZE                                         0x00100000
+#define HOST_TLMM_BASE_PHYS                                         0x01a00000
+
+#define HOST_CORE_TOP_CSR_BASE                                       0x1b00000
+#define HOST_CORE_TOP_CSR_BASE_SIZE                                 0x0003f000
+#define HOST_CORE_TOP_CSR_BASE_PHYS                                 0x01b00000
+
+#define QUPV3_QUPV3_ID_3_BASE                                        0x1b40000
+#define QUPV3_QUPV3_ID_3_BASE_SIZE                                  0x00040000
+#define QUPV3_QUPV3_ID_3_BASE_PHYS                                  0x01b40000
+
+#define HOST_SOC_WFSS_CE_REG_BASE                                    0x1b80000
+#define HOST_SOC_WFSS_CE_REG_BASE_SIZE                              0x0001c000
+#define HOST_SOC_WFSS_CE_REG_BASE_PHYS                              0x01b80000
+
+#define HOST_WL_TLMM_BASE                                            0x1bc0000
+#define HOST_WL_TLMM_BASE_SIZE                                      0x00020000
+#define HOST_WL_TLMM_BASE_PHYS                                      0x01bc0000
+
+#define HOST_TSENS_SROT_BASE                                         0x1bf0000
+#define HOST_TSENS_SROT_BASE_SIZE                                   0x00001000
+#define HOST_TSENS_SROT_BASE_PHYS                                   0x01bf0000
+
+#define HOST_TSENS_TM_BASE                                           0x1bf1000
+#define HOST_TSENS_TM_BASE_SIZE                                     0x00001000
+#define HOST_TSENS_TM_BASE_PHYS                                     0x01bf1000
+
+#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE                            0x1c00000
+#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_SIZE                      0x00080000
+#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_PHYS                      0x01c00000
+
+#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE                           0x1c80000
+#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_SIZE                     0x0007fffd
+#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_PHYS                     0x01c80000
+
+#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE              0x1d00000
+#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_SIZE        0x00100000
+#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_PHYS        0x01d00000
+
+#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE                              0x1e00000
+#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_SIZE                        0x00020000
+#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_PHYS                        0x01e00000
+
+#define HOST_SECURITY_CONTROL_WLAN_BASE                              0x1e20000
+#define HOST_SECURITY_CONTROL_WLAN_BASE_SIZE                        0x00008000
+#define HOST_SECURITY_CONTROL_WLAN_BASE_PHYS                        0x01e20000
+
+#define HOST_EDPD_CAL_ACC_BASE                                       0x1e28000
+#define HOST_EDPD_CAL_ACC_BASE_SIZE                                 0x00003000
+#define HOST_EDPD_CAL_ACC_BASE_PHYS                                 0x01e28000
+
+#define HOST_CPR_CX_CPR3_BASE                                        0x1e30000
+#define HOST_CPR_CX_CPR3_BASE_SIZE                                  0x00004000
+#define HOST_CPR_CX_CPR3_BASE_PHYS                                  0x01e30000
+
+#define HOST_CPR_MX_CPR3_BASE                                        0x1e34000
+#define HOST_CPR_MX_CPR3_BASE_SIZE                                  0x00004000
+#define HOST_CPR_MX_CPR3_BASE_PHYS                                  0x01e34000
+
+#define HOST_WCSS_IE_BASE                                            0x1e38000
+#define HOST_WCSS_IE_BASE_SIZE                                      0x00001000
+#define HOST_WCSS_IE_BASE_PHYS                                      0x01e38000
+
+#define HOST_GCC_GCC_BASE                                            0x1e40000
+#define HOST_GCC_GCC_BASE_SIZE                                      0x0000048c
+#define HOST_GCC_GCC_BASE_PHYS                                      0x01e40000
+
+#define HOST_PCNOC_0_BUS_TIMEOUT_BASE                                0x1e60000
+#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_PHYS                          0x01e60000
+
+#define HOST_PCNOC_1_BUS_TIMEOUT_BASE                                0x1e61000
+#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_PHYS                          0x01e61000
+
+#define HOST_PCNOC_2_BUS_TIMEOUT_BASE                                0x1e62000
+#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_PHYS                          0x01e62000
+
+#define HOST_PCNOC_3_BUS_TIMEOUT_BASE                                0x1e63000
+#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_PHYS                          0x01e63000
+
+#define HOST_PCNOC_4_BUS_TIMEOUT_BASE                                0x1e64000
+#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_PHYS                          0x01e64000
+
+#define HOST_PCNOC_5_BUS_TIMEOUT_BASE                                0x1e65000
+#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_SIZE                          0x00001000
+#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_PHYS                          0x01e65000
+
+#define HOST_RRI_PREFETCH_REG_BASE                                   0x1e70000
+#define HOST_RRI_PREFETCH_REG_BASE_SIZE                             0x00010000
+#define HOST_RRI_PREFETCH_REG_BASE_PHYS                             0x01e70000
+
+#define HOST_SYSTEM_NOC_BASE                                         0x1e80000
+#define HOST_SYSTEM_NOC_BASE_SIZE                                   0x0000a000
+#define HOST_SYSTEM_NOC_BASE_PHYS                                   0x01e80000
+
+#define HOST_PC_NOC_BASE                                             0x1f00000
+#define HOST_PC_NOC_BASE_SIZE                                       0x00003880
+#define HOST_PC_NOC_BASE_PHYS                                       0x01f00000
+
+#define HOST_WLAON_WL_AON_REG_BASE                                   0x1f80000
+#define HOST_WLAON_WL_AON_REG_BASE_SIZE                             0x000007f0
+#define HOST_WLAON_WL_AON_REG_BASE_PHYS                             0x01f80000
+
+#define HOST_SYSPM_SYSPM_REG_BASE                                    0x1f82000
+#define HOST_SYSPM_SYSPM_REG_BASE_SIZE                              0x00001000
+#define HOST_SYSPM_SYSPM_REG_BASE_PHYS                              0x01f82000
+
+#define HOST_PMU_WLAN_PMU_TOP_BASE                                   0x1f88000
+#define HOST_PMU_WLAN_PMU_TOP_BASE_SIZE                             0x00000400
+#define HOST_PMU_WLAN_PMU_TOP_BASE_PHYS                             0x01f88000
+
+#define HOST_PMU_NOC_BASE                                            0x1f8a000
+#define HOST_PMU_NOC_BASE_SIZE                                      0x00000180
+#define HOST_PMU_NOC_BASE_PHYS                                      0x01f8a000
+
+#define HOST_BOOT_ROM                                                0x1200000
+#define HOST_BOOT_ROM_SIZE                                          0x00004800
+#define HOST_BOOT_ROM_PHYS                                          0x01200000
+
+#define HOST_SYSTEM_IRAM                                             0x1400000
+#define HOST_SYSTEM_IRAM_SIZE                                       0x00020000
+#define HOST_SYSTEM_IRAM_PHYS                                       0x01400000
+
+#define HOST_ZEALIS_SRAM                                             0x28c0000
+#define HOST_ZEALIS_SRAM_SIZE                                       0x00040000
+#define HOST_ZEALIS_SRAM_PHYS                                       0x028c0000
+
+#define HOST_PCIE_ATU_REGION                                         0x4000000
+#define HOST_PCIE_ATU_REGION_SIZE                                   0x40000000
+#define HOST_PCIE_ATU_REGION_PHYS                                   0x04000000
+
+#endif
diff --git a/hw/wcn8750/v1/msmhwioreg.h b/hw/wcn8750/v1/msmhwioreg.h
new file mode 100644
index 000000000000..2d9c5ac5a7db
--- /dev/null
+++ b/hw/wcn8750/v1/msmhwioreg.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __MSMHWIOREG_H__
+#define __MSMHWIOREG_H__
+
+#include "msmhwiobase.h"
+
+#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (HOST_SOC_WFSS_CE_REG_BASE      + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                         0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                  8
+#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (HOST_SOC_WFSS_CE_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x0)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN                    \
+                in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x4)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN                    \
+                in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                  8
+#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (HOST_SOC_WFSS_CE_REG_BASE      + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x0)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN                    \
+                in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                           0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x4)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN                    \
+                in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                    8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x400)
+#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (HOST_SOC_WFSS_CE_REG_BASE      + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x0)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN                    \
+                in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                           0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x4)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN                    \
+                in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)            \
+                in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)            \
+                out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                    8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                           0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x58)
+
+
+#endif
diff --git a/hw/wcn8750/v1/no_ack_report.h b/hw/wcn8750/v1/no_ack_report.h
new file mode 100644
index 000000000000..5f9660801de6
--- /dev/null
+++ b/hw/wcn8750/v1/no_ack_report.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_ack_transmit_reason                                  :  4,
+                      macrx_abort_reason                                      :  4,
+                      phyrx_abort_reason                                      :  8,
+                      frame_control                                           : 16;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      sr_ppdu_during_obss                                     :  1,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      reserved_1                                              :  3;
+             uint32_t pre_bt_broadcast_status_details                         : 12,
+                      first_bt_broadcast_status_details                       : 12,
+                      reserved_2                                              :  8;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_3                                              : 20;
+#else
+             uint32_t frame_control                                           : 16,
+                      phyrx_abort_reason                                      :  8,
+                      macrx_abort_reason                                      :  4,
+                      no_ack_transmit_reason                                  :  4;
+             uint32_t reserved_1                                              :  3,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      sr_ppdu_during_obss                                     :  1,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t reserved_2                                              :  8,
+                      first_bt_broadcast_status_details                       : 12,
+                      pre_bt_broadcast_status_details                         : 12;
+             uint32_t reserved_3                                              : 20,
+                      second_bt_broadcast_status_details                      : 12;
+#endif
+};
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET                                 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB                                    0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB                                    3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK                                   0x0000000f
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB                                        4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB                                        7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK                                       0x000000f0
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB                                        8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB                                        15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK                                       0x0000ff00
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET                                          0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB                                             16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB                                             31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK                                            0xffff0000
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET                                       0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB                                          0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB                                          23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK                                         0x00ffffff
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET                                    0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK                                      0x01000000
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET                     0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB                        25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB                        28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK                       0x1e000000
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET                                             0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB                                                29
+#define NO_ACK_REPORT_RESERVED_1_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_1_MASK                                               0xe0000000
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                        0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                           0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                           11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                          0x00000fff
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                      0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                         12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                         23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                        0x00fff000
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET                                             0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB                                                24
+#define NO_ACK_REPORT_RESERVED_2_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_2_MASK                                               0xff000000
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET                     0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                        0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                        11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                       0x00000fff
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET                                             0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB                                                12
+#define NO_ACK_REPORT_RESERVED_3_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_3_MASK                                               0xfffff000
+
+#endif
diff --git a/hw/wcn8750/v1/ofdma_trigger_details.h b/hw/wcn8750/v1/ofdma_trigger_details.h
new file mode 100644
index 000000000000..8ad80d76b0ee
--- /dev/null
+++ b/hw/wcn8750/v1/ofdma_trigger_details.h
@@ -0,0 +1,944 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _OFDMA_TRIGGER_DETAILS_H_
+#define _OFDMA_TRIGGER_DETAILS_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26
+
+#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13
+
+struct ofdma_trigger_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ax_trigger_source                                       :  1,
+                      rx_trigger_frame_user_source                            :  2,
+                      received_bandwidth                                      :  3,
+                      txop_duration_all_ones                                  :  1,
+                      eht_trigger_response                                    :  1,
+                      pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      rxpcu_pcie_l0_req_duration                              :  8;
+             uint32_t he_trigger_ul_ppdu_length                               :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_reserved                                     :  1,
+                      bss_color                                               :  6;
+             uint32_t trigger_type                                            :  4,
+                      lsig_response_length                                    : 12,
+                      cascade_indication                                      :  1,
+                      carrier_sense                                           :  1,
+                      bandwidth                                               :  2,
+                      cp_ltf_size                                             :  2,
+                      mu_mimo_ltf_mode                                        :  1,
+                      number_of_ltfs                                          :  3,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ap_tx_power_lsb_part                                    :  4;
+             uint32_t ap_tx_power_msb_part                                    :  2,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      spatial_reuse                                           : 16,
+                      doppler                                                 :  1,
+                      he_siga_reserved                                        :  9,
+                      reserved_3b                                             :  1;
+             uint32_t aid12                                                   : 12,
+                      ru_allocation                                           :  9,
+                      mcs                                                     :  4,
+                      dcm                                                     :  1,
+                      start_spatial_stream                                    :  3,
+                      number_of_spatial_stream                                :  3;
+             uint32_t target_rssi                                             :  7,
+                      coding_type                                             :  1,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      tid_aggregation_limit                                   :  3,
+                      reserved_5b                                             :  1,
+                      prefered_ac                                             :  2,
+                      bar_control_ack_policy                                  :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_reserved                                    :  9,
+                      bar_control_tid_info                                    :  4;
+             uint32_t nr0_per_tid_info_reserved                               : 12,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr1_per_tid_info_reserved                               : 12,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr2_per_tid_info_reserved                               : 12,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr3_per_tid_info_reserved                               : 12,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr4_per_tid_info_reserved                               : 12,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr5_per_tid_info_reserved                               : 12,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr6_per_tid_info_reserved                               : 12,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr7_per_tid_info_reserved                               : 12,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t fb_segment_retransmission_bitmap                        :  8,
+                      reserved_14a                                            :  2,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_duration_field                                       : 16,
+                      scrambler_seed                                          :  7,
+                      rx_chain_mask_type                                      :  1;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t sw_peer_id                                              : 16,
+                      response_tx_duration                                    : 16;
+             uint32_t __reserved_g_0005_trigger_subtype                                 :  4,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      reserved_18a                                            :  1,
+                      qos_null_only_response_tx                               :  1;
+             uint32_t tbr_trigger_sound_sac                                   : 16,
+                      reserved_19a                                            :  8,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19b                                            :  3;
+             uint32_t eht_special_aid12                                       : 12,
+                      phy_version                                             :  3,
+                      bandwidth_ext                                           :  2,
+                      eht_spatial_reuse                                       :  8,
+                      u_sig_reserved1                                         :  7;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t __reserved_g_0086                                                 :  1,
+                      __reserved_g_0074                                       :  4,
+                      blackout_details_en                                     :  1,
+                      uhr_trig_response                                       :  1,
+                      mcs_ext                                                 :  1,
+                      dso_primary20_index_select                              :  4,
+                      dso_icf_reception                                       :  1,
+                      dru_spreading_bw                                        :  2,
+                      dru_indication_per_80mhz                                :  4,
+                      coding_type_ext                                         :  1,
+                      pad_duration                                            :  5,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_22a                                            :  6;
+             uint32_t dso_cca_puncture_pattern                                : 16,
+                      dso_freq_subband_channel_bonding_mask                   : 16;
+             uint32_t __reserved_g_0034                                       :  1,
+                      enable_steering                                         :  1,
+                      q2q_mba                                                 :  1,
+                      reserved_24a                                            : 29;
+             uint32_t reserved_25a                                            : 32;
+#else
+             uint32_t rxpcu_pcie_l0_req_duration                              :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8,
+                      eht_trigger_response                                    :  1,
+                      txop_duration_all_ones                                  :  1,
+                      received_bandwidth                                      :  3,
+                      rx_trigger_frame_user_source                            :  2,
+                      ax_trigger_source                                       :  1;
+             uint32_t bss_color                                               :  6,
+                      he_trigger_reserved                                     :  1,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_ul_ppdu_length                               :  5;
+             uint32_t ap_tx_power_lsb_part                                    :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      number_of_ltfs                                          :  3,
+                      mu_mimo_ltf_mode                                        :  1,
+                      cp_ltf_size                                             :  2,
+                      bandwidth                                               :  2,
+                      carrier_sense                                           :  1,
+                      cascade_indication                                      :  1,
+                      lsig_response_length                                    : 12,
+                      trigger_type                                            :  4;
+             uint32_t reserved_3b                                             :  1,
+                      he_siga_reserved                                        :  9,
+                      doppler                                                 :  1,
+                      spatial_reuse                                           : 16,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      ap_tx_power_msb_part                                    :  2;
+             uint32_t number_of_spatial_stream                                :  3,
+                      start_spatial_stream                                    :  3,
+                      dcm                                                     :  1,
+                      mcs                                                     :  4,
+                      ru_allocation                                           :  9,
+                      aid12                                                   : 12;
+             uint32_t bar_control_tid_info                                    :  4,
+                      bar_control_reserved                                    :  9,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_ack_policy                                  :  1,
+                      prefered_ac                                             :  2,
+                      reserved_5b                                             :  1,
+                      tid_aggregation_limit                                   :  3,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      coding_type                                             :  1,
+                      target_rssi                                             :  7;
+             uint32_t nr0_start_seq_ctrl_start_seq_number                     : 12,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_per_tid_info_reserved                               : 12;
+             uint32_t nr1_start_seq_ctrl_start_seq_number                     : 12,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_per_tid_info_reserved                               : 12;
+             uint32_t nr2_start_seq_ctrl_start_seq_number                     : 12,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_per_tid_info_reserved                               : 12;
+             uint32_t nr3_start_seq_ctrl_start_seq_number                     : 12,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_per_tid_info_reserved                               : 12;
+             uint32_t nr4_start_seq_ctrl_start_seq_number                     : 12,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_per_tid_info_reserved                               : 12;
+             uint32_t nr5_start_seq_ctrl_start_seq_number                     : 12,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_per_tid_info_reserved                               : 12;
+             uint32_t nr6_start_seq_ctrl_start_seq_number                     : 12,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_per_tid_info_reserved                               : 12;
+             uint32_t nr7_start_seq_ctrl_start_seq_number                     : 12,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_per_tid_info_reserved                               : 12;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_14a                                            :  2,
+                      fb_segment_retransmission_bitmap                        :  8;
+             uint32_t rx_chain_mask_type                                      :  1,
+                      scrambler_seed                                          :  7,
+                      rx_duration_field                                       : 16,
+                      rx_chain_mask                                           :  8;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t response_tx_duration                                    : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t qos_null_only_response_tx                               :  1,
+                      reserved_18a                                            :  1,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      __reserved_g_0005_trigger_subtype                                 :  4;
+             uint32_t reserved_19b                                            :  3,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19a                                            :  8,
+                      tbr_trigger_sound_sac                                   : 16;
+             uint32_t u_sig_reserved1                                         :  7,
+                      eht_spatial_reuse                                       :  8,
+                      bandwidth_ext                                           :  2,
+                      phy_version                                             :  3,
+                      eht_special_aid12                                       : 12;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+             uint32_t reserved_22a                                            :  6,
+                      ects_as_tb_ppdu                                         :  1,
+                      pad_duration                                            :  5,
+                      coding_type_ext                                         :  1,
+                      dru_indication_per_80mhz                                :  4,
+                      dru_spreading_bw                                        :  2,
+                      dso_icf_reception                                       :  1,
+                      dso_primary20_index_select                              :  4,
+                      mcs_ext                                                 :  1,
+                      uhr_trig_response                                       :  1,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0074                                       :  4,
+                      __reserved_g_0086                                                 :  1;
+             uint32_t dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_cca_puncture_pattern                                : 16;
+             uint32_t reserved_24a                                            : 29,
+                      q2q_mba                                                 :  1,
+                      enable_steering                                         :  1,
+                      __reserved_g_0034                                       :  1;
+             uint32_t reserved_25a                                            : 32;
+#endif
+};
+
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK                                0x0000000000000001
+
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET                   0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB                      1
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB                      2
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK                     0x0000000000000006
+
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET                             0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB                                3
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB                                5
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK                               0x0000000000000038
+
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK                           0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET                           0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK                             0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET                                  0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB                                     8
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB                                     15
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK                                    0x000000000000ff00
+
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB                                         16
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB                                         23
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK                                        0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET                     0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB                        24
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB                        31
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK                       0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB                         36
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK                        0x0000001f00000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET                       0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB                          37
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB                          44
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK                         0x00001fe000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET                         0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB                            45
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB                            49
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK                           0x0003e00000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB                         50
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB                         54
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK                        0x007c000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET                              0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB                                 55
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB                                 56
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK                                0x0180000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET                            0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB                               57
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK                              0x0200000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET                                      0x0000000000000000
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB                                         58
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB                                         63
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK                                        0xfc00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET                                   0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB                                      0
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB                                      3
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK                                     0x000000000000000f
+
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB                              4
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB                              15
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK                             0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET                             0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK                               0x0000000000010000
+
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK                                    0x0000000000020000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET                                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB                                         18
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB                                         19
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK                                        0x00000000000c0000
+
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB                                       20
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB                                       21
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK                                      0x0000000000300000
+
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK                                 0x0000000000400000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET                                 0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB                                    23
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB                                    25
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK                                   0x0000000003800000
+
+#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET                                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_STBC_LSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MASK                                             0x0000000004000000
+
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET                              0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK                                0x0000000008000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB                              28
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK                             0x00000000f0000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET                           0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB                              32
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB                              33
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK                             0x0000000300000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET                      0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB                         34
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB                         35
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK                        0x0000000c00000000
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                  36
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                 0x0000001000000000
+
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET                                  0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB                                     37
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB                                     52
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK                                    0x001fffe000000000
+
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET                                        0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB                                           53
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK                                          0x0020000000000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET                               0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB                                  54
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB                                  62
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK                                 0x7fc0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET                                    0x0000000000000008
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB                                       63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK                                      0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET                                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_AID12_LSB                                             0
+#define OFDMA_TRIGGER_DETAILS_AID12_MSB                                             11
+#define OFDMA_TRIGGER_DETAILS_AID12_MASK                                            0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET                                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB                                     12
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB                                     20
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK                                    0x00000000001ff000
+
+#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MCS_LSB                                               21
+#define OFDMA_TRIGGER_DETAILS_MCS_MSB                                               24
+#define OFDMA_TRIGGER_DETAILS_MCS_MASK                                              0x0000000001e00000
+
+#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET                                            0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_DCM_LSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MASK                                              0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB                              26
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB                              28
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK                             0x000000001c000000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET                       0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB                          29
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB                          31
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK                         0x00000000e0000000
+
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB                                       32
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB                                       38
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK                                      0x0000007f00000000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB                                       39
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK                                      0x0000008000000000
+
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB                            40
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB                            41
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK                           0x0000030000000000
+
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB                             42
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB                             44
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK                            0x00001c0000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB                                       45
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK                                      0x0000200000000000
+
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET                                    0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB                                       46
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB                                       47
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK                                      0x0000c00000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET                         0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB                            48
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK                           0x0001000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET                          0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB                             49
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK                            0x0002000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET                  0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB                     50
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK                    0x0004000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB                              51
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB                              59
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK                             0x0ff8000000000000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET                           0x0000000000000010
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB                              60
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK                             0xf000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB                         32
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB                         43
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB                        44
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB                        47
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
+
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET               0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB                  0
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB                  7
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK                 0x00000000000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET                                   0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB                                      8
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB                                      9
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK                                     0x0000000000000300
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                   10
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                   15
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                  0x000000000000fc00
+
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET                        0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB                           16
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB                           31
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK                          0x00000000ffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET                                  0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB                                     32
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB                                     39
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK                                    0x000000ff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET                              0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB                                 40
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB                                 55
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK                                0x00ffff0000000000
+
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET                                 0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB                                    56
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB                                    62
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK                                   0x7f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET                             0x0000000000000038
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB                                63
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK                               0x8000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET          0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB             0
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB             9
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK            0x00000000000003ff
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK         0x0000000000000400
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK      0x0000000000000800
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET    0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK      0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET              0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB                 13
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB                 15
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK                0x000000000000e000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET                       0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB                          16
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB                          23
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK                         0x0000000000ff0000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB                              24
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK                             0x00000000ff000000
+
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET                                     0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB                                        32
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB                                        47
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK                                       0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET                           0x0000000000000040
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB                              48
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB                              63
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK                             0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET                  0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB                     4
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB                     15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK                    0x000000000000fff0
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB                  16
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB                  24
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK                 0x0000000001ff0000
+
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET                                        0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB                                           25
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB                                           27
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK                                          0x000000000e000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET               0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB                  28
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB                  29
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK                 0x0000000030000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK                                     0x0000000040000000
+
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET                      0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK                        0x0000000080000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET                          0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB                             32
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB                             47
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK                            0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB                                      48
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB                                      55
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK                                     0x00ff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET                                0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB                                   56
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB                                   60
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK                                  0x1f00000000000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET                                   0x0000000000000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB                                      61
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK                                     0xe000000000000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB                                 11
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK                                0x0000000000000fff
+
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET                                    0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB                                       12
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB                                       14
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK                                      0x0000000000007000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET                                  0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB                                     15
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB                                     16
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK                                    0x0000000000018000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET                              0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB                                 17
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB                                 24
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK                                0x0000000001fe0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET                                0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB                                   31
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK                                  0x00000000fe000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET            0x0000000000000050
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB               32
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB               63
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK              0xffffffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET                            0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB                               5
+#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK                              0x0000000000000020
+
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB                                 6
+#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK                                0x0000000000000040
+
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET                                        0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB                                           7
+#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK                                          0x0000000000000080
+
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET                     0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB                        8
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB                        11
+#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK                       0x0000000000000f00
+
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET                              0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB                                 12
+#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK                                0x0000000000001000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET                               0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB                                  13
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB                                  14
+#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK                                 0x0000000000006000
+
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB                          15
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB                          18
+#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK                         0x0000000000078000
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB                                   19
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK                                  0x0000000000080000
+
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB                                      20
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB                                      24
+#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK                                     0x0000000001f00000
+
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET                                0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB                                   25
+#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK                                  0x0000000002000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET                                   0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB                                      26
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK                                     0x00000000fc000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET                       0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB                          32
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB                          47
+#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK                         0x0000ffff00000000
+
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET          0x0000000000000058
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB             48
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB             63
+#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK            0xffff000000000000
+
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET                                0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB                                   1
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB                                   1
+#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK                                  0x0000000000000002
+
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET                                        0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB                                           2
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB                                           2
+#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK                                          0x0000000000000004
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB                                      3
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK                                     0x00000000fffffff8
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET                                   0x0000000000000060
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB                                      32
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB                                      63
+#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/pcu_ppdu_setup_init.h b/hw/wcn8750/v1/pcu_ppdu_setup_init.h
new file mode 100644
index 000000000000..f623a25ba4d4
--- /dev/null
+++ b/hw/wcn8750/v1/pcu_ppdu_setup_init.h
@@ -0,0 +1,2316 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PCU_PPDU_SETUP_INIT_H_
+#define _PCU_PPDU_SETUP_INIT_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58
+
+#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29
+
+struct pcu_ppdu_setup_init {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t medium_prot_type                                        :  3,
+                      response_type                                           :  5,
+                      response_info_part2_required                            :  1,
+                      response_to_response                                    :  3,
+                      mba_user_order                                          :  2,
+                      expected_mba_size                                       : 11,
+                      required_ul_mu_resp_user_count                          :  6,
+                      transmitted_bssid_check_en                              :  1;
+             uint32_t mprot_required_bw1                                      :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw320                                    :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      update_timestamp_64                                     :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_32_upper                               :  1,
+                      reserved_1a                                             : 13;
+             uint32_t insert_timestamp_offset_0                               : 16,
+                      insert_timestamp_offset_1                               : 16;
+             uint32_t max_bw40_try_count                                      :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw320_try_count                                     :  4,
+                      insert_wur_timestamp_offset                             :  6,
+                      update_wur_timestamp                                    :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      insert_wur_fcs                                          :  1,
+                      q2q_trigger                                             :  1,
+                      reserved_3b                                             :  2;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_hw_response_tx_duration                             : 16,
+                      r2r_rx_duration_field                                   : 16;
+             uint32_t r2r_group_id                                            :  6,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_sta_partial_aid                                     : 11,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_set_required_response_time                          :  1,
+                      reserved_29a                                            :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      r2r_bw40_active_channel                                 :  3;
+             uint32_t r2r_bw80_active_channel                                 :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw320                                               :  3,
+                      tx_with_blackout_details                                :  1,
+                      expect_rx_with_blackout_details                         :  1;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t mu_response_expected_bitmap_36_32                       :  5,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_expected_response_sta_count                          :  6,
+                      transmit_includes_multidestination                      :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      insert_current_tx_start_timing_info                     :  1,
+                      tx_start_transmit_time_byte_offset                      : 12;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad1_47_32                              : 16,
+                      protection_frame_ad2_15_0                               : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t dynamic_medium_prot_threshold                           : 24,
+                      dynamic_medium_prot_type                                :  1,
+                      reserved_54a                                            :  7;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad3_47_32                              : 16,
+                      protection_frame_ad4_15_0                               : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#else
+             uint32_t transmitted_bssid_check_en                              :  1,
+                      required_ul_mu_resp_user_count                          :  6,
+                      expected_mba_size                                       : 11,
+                      mba_user_order                                          :  2,
+                      response_to_response                                    :  3,
+                      response_info_part2_required                            :  1,
+                      response_type                                           :  5,
+                      medium_prot_type                                        :  3;
+             uint32_t reserved_1a                                             : 13,
+                      update_timestamp_32_upper                               :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_64                                     :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      mprot_required_bw320                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw1                                      :  1;
+             uint32_t insert_timestamp_offset_1                               : 16,
+                      insert_timestamp_offset_0                               : 16;
+             uint32_t reserved_3b                                             :  2,
+                      q2q_trigger                                             :  1,
+                      insert_wur_fcs                                          :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      update_wur_timestamp                                    :  1,
+                      insert_wur_timestamp_offset                             :  6,
+                      max_bw320_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw40_try_count                                      :  4;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_rx_duration_field                                   : 16,
+                      r2r_hw_response_tx_duration                             : 16;
+             uint32_t r2r_bw40_active_channel                                 :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      reserved_29a                                            :  3,
+                      r2r_set_required_response_time                          :  1,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_sta_partial_aid                                     : 11,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_group_id                                            :  6;
+             uint32_t expect_rx_with_blackout_details                         :  1,
+                      tx_with_blackout_details                                :  1,
+                      r2r_bw320                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw80_active_channel                                 :  3;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t tx_start_transmit_time_byte_offset                      : 12,
+                      insert_current_tx_start_timing_info                     :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      transmit_includes_multidestination                      :  1,
+                      mu_expected_response_sta_count                          :  6,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_response_expected_bitmap_36_32                       :  5;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad2_15_0                               : 16,
+                      protection_frame_ad1_47_32                              : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t reserved_54a                                            :  7,
+                      dynamic_medium_prot_type                                :  1,
+                      dynamic_medium_prot_threshold                           : 24;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad4_15_0                               : 16,
+                      protection_frame_ad3_47_32                              : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#endif
+};
+
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB                                    0
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB                                    2
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK                                   0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET                                    0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB                                       3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB                                       7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK                                      0x00000000000000f8
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK                       0x0000000000000100
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB                                9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB                                11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK                               0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB                                      12
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB                                      13
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK                                     0x0000000000003000
+
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB                                   14
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB                                   24
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK                                  0x0000000001ffc000
+
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB                      25
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB                      30
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK                     0x000000007e000000
+
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET                       0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK                         0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB                                  32
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK                                 0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB                                 33
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK                                0x0000000200000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB                                 34
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK                                0x0000000400000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB                                 35
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK                                0x0000000800000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB                                36
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK                               0x0000001000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB                                37
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK                               0x0000002000000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET                             0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB                                38
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK                               0x0000004000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET                                 0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB                                    39
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK                                   0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB                                   40
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK                                  0x0000010000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB                                   41
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK                                  0x0000020000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET                                0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB                                   42
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK                                  0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB                                  43
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK                                 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB                                  44
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK                                 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET                               0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB                                  45
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK                                 0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET                                   0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB                                      46
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK                                     0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET                     0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB                        47
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK                       0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET                              0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB                                 48
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK                                0x0001000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB                           49
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK                          0x0002000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET                        0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB                           50
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK                          0x0004000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB                                         51
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK                                        0xfff8000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB                           15
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK                          0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET                        0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB                           16
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB                           31
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB                                  32
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB                                  35
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK                                 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET                               0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB                                  36
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB                                  39
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK                                 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB                                 40
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB                                 43
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK                                0x00000f0000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB                                 44
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB                                 47
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK                                0x0000f00000000000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET                              0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB                                 48
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB                                 51
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK                                0x000f000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB                         52
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB                         57
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK                        0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET                             0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB                                58
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK                               0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET                       0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB                          59
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK                         0x0800000000000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET                                   0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB                                      60
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK                                     0x1000000000000000
+
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET                                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB                                         61
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB                                         61
+#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK                                        0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET                                      0x0000000000000008
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB                                         62
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB                                         63
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK                                        0xc000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET  0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET     0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET    0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET         0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET   0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET      0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET       0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET       0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET   0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET  0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET          0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET     0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET  0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET  0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET     0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB        57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB        60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK       0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET    0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB       61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK      0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB            62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK           0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET         0x0000000000000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB            63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK           0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK     0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET      0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK        0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK         0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET  0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB     35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK    0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET          0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB             36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB             38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK            0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK     0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET       0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB          40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB          47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK         0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET   0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB      48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB      55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK     0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB    4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK   0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB     5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK    0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET          0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK            0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB        14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK       0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET     0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK       0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK   0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK    0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB     45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK    0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB  50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB  52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET  0x0000000000000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB     59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB     63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK    0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK    0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK  0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET  0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK    0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET  0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET     0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK       0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET    0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK      0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET         0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK           0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET   0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB      32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB      39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK     0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB  40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB  47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET      0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB         48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB         50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK        0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET       0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB          59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB          61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK         0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB     3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK    0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK            0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK     0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET       0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK         0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET   0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK     0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB    36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK   0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET  0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB     37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK    0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET          0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB             40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB             41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK            0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB        42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB        46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK       0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET     0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB        55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK       0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB    56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK   0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK    0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK    0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK    0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB     42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK    0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB   43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB   45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK  0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET  0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB     52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB     57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK    0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET    0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET   0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET        0x0000000000000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET     0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET         0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET      0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET  0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET         0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET    0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET    0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK      0x000000001e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET   0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK     0x0000000020000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK          0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET        0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK          0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET  0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB     32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK    0x000000ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET     0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB        48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB        50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK       0x0007000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET      0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB         59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB         61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK        0x3800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK   0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK           0x0000000000000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK    0x0000000000000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET      0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK        0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET  0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK    0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB   32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB   36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK  0x0000001f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB    37
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB    39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK   0x000000e000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET         0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB            40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB            41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK           0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB       42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB       46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK      0x00007c0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET    0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB       48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB       55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK      0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB   56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB   63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK  0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK   0x0000000000000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK   0x0000000000002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK   0x00000000f8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB    42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK   0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB  43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB  45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB    52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB    57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK   0x03f0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET    0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB       57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB       60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK      0x1e00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET   0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB      61
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK     0x2000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB           62
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK          0x4000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET        0x0000000000000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB           63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK          0x8000000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK    0x00000000000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET     0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK       0x0000000000070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK        0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB    35
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK   0x0000000f00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET         0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB            36
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB            38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK           0x0000007000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB     39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK    0x0000008000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET      0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB         40
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB         47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK        0x0000ff0000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET  0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB     48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB     55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK    0x00ff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB  56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB  63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB   4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB    5
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK   0x00000000000000e0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET         0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK           0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB       14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK      0x0000000000007c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET    0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK      0x0000000000ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK  0x00000000ff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB    32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK   0x0000000100000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB    45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK   0x0000200000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB    59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB    63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK   0xf800000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK   0x0000000000000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK   0x0000000003f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET                      0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB                         0
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB                         15
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK                        0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET                            0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB                               16
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB                               31
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK                              0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB                                        32
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB                                        37
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK                                       0x0000003f00000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB                             38
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB                             41
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK                            0x000003c000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET                              0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB                                 42
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB                                 52
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK                                0x001ffc0000000000
+
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET                0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB                   53
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK                  0x0020000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET                   0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB                      54
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK                     0x0040000000000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET                                     0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB                                        55
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB                                        57
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK                                       0x0380000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB                             58
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB                             60
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK                            0x1c00000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET                          0x00000000000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB                             61
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB                             63
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK                            0xe000000000000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET                          0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB                             0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB                             2
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK                            0x0000000000000007
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB                            3
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB                            5
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK                           0x0000000000000038
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB                            6
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB                            8
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK                           0x00000000000001c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB                            9
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB                            11
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK                           0x0000000000000e00
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB                                            12
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB                                            14
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK                                           0x0000000000007000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB                                            15
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB                                            17
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK                                           0x0000000000038000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET                                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB                                            18
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB                                            20
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK                                           0x00000000001c0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB                                           21
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB                                           23
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK                                          0x0000000000e00000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB                                           24
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB                                           26
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK                                          0x0000000007000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET                                        0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB                                           27
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB                                           29
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK                                          0x0000000038000000
+
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET                         0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB                            30
+#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK                           0x0000000040000000
+
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET                  0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB                     31
+#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK                    0x0000000080000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET                 0x00000000000000c0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB                    32
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB                    63
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK                   0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET                0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB                   0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB                   4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK                  0x000000000000001f
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB                      5
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB                      10
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK                     0x00000000000007e0
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET                   0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB                      11
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB                      16
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK                     0x000000000001f800
+
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK                 0x0000000000020000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET                 0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK                   0x0000000000040000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET              0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK                0x0000000000080000
+
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET               0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB                  20
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB                  31
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK                 0x00000000fff00000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET                        0x00000000000000c8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET                        0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET                       0x00000000000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK                         0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET                    0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB                       0
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB                       23
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK                      0x0000000000ffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET                         0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK                           0x0000000001000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET                                     0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB                                        25
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB                                        31
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK                                       0x00000000fe000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET                        0x00000000000000d8
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB                           32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB                           63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK                          0xffffffff00000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK                         0x000000000000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET                        0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK                          0x00000000ffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET                       0x00000000000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB                          32
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB                          63
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK                         0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/pdg_response.h b/hw/wcn8750/v1/pdg_response.h
new file mode 100644
index 000000000000..d94c69ff2645
--- /dev/null
+++ b/hw/wcn8750/v1/pdg_response.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_H_
+#define _PDG_RESPONSE_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE 14
+
+#define NUM_OF_QWORDS_PDG_RESPONSE 7
+
+struct pdg_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t hw_response_tx_duration                                 : 16,
+                      rx_duration_field                                       : 16;
+             uint32_t punctured_response_transmission                         :  1,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      scrambler_seed_override                                 :  2,
+                      response_density_valid                                  :  1,
+                      response_density                                        :  5,
+                      more_data                                               :  1,
+                      duration_indication                                     :  1,
+                      blackout_details_en                                     :  1,
+                      cfp_protected_resp                                      :  1,
+                      bandwidth                                               :  3;
+             uint32_t ack_id                                                  : 16,
+                      block_ack_bitmap                                        : 16;
+             uint32_t response_frame_type                                     :  4,
+                      ack_id_ext                                              : 10,
+                      ftm_en                                                  :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 11;
+             uint32_t ndp_ba_start_seq_ctrl                                   : 12,
+                      active_channel                                          :  3,
+                      txop_duration_all_ones                                  :  1,
+                      frame_length                                            : 16;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      q2q_mba                                                 :  1,
+                      reserved_12a                                            :  6;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t rx_duration_field                                       : 16,
+                      hw_response_tx_duration                                 : 16;
+             uint32_t bandwidth                                               :  3,
+                      cfp_protected_resp                                      :  1,
+                      blackout_details_en                                     :  1,
+                      duration_indication                                     :  1,
+                      more_data                                               :  1,
+                      response_density                                        :  5,
+                      response_density_valid                                  :  1,
+                      scrambler_seed_override                                 :  2,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      punctured_response_transmission                         :  1;
+             uint32_t block_ack_bitmap                                        : 16,
+                      ack_id                                                  : 16;
+             uint32_t sta_partial_aid                                         : 11,
+                      group_id                                                :  6,
+                      ftm_en                                                  :  1,
+                      ack_id_ext                                              : 10,
+                      response_frame_type                                     :  4;
+             uint32_t frame_length                                            : 16,
+                      txop_duration_all_ones                                  :  1,
+                      active_channel                                          :  3,
+                      ndp_ba_start_seq_ctrl                                   : 12;
+             uint32_t reserved_12a                                            :  6,
+                      q2q_mba                                                 :  1,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET                       0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB               1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB               24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK              0x0000000001fffffe
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET                          0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB                             25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB                             28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK                            0x000000001e000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET                         0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK                           0x0000000020000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK                                0x0000000040000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET                              0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK                                0x0000000080000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET                        0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB                           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB                           39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK                          0x000000ff00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET                    0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB                       40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB                       47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK                      0x0000ff0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET                           0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB                              48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB                              50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK                             0x0007000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB                    51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB                    58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK                   0x07f8000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET                            0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB                               59
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB                               61
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK                              0x3800000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET                 0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB                    62
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK                   0x4000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET                0x0000000000000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB                   63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK                  0x8000000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB                          3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK                         0x000000000000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB                                  4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB                                  6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK                                 0x0000000000000070
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK                          0x0000000000000080
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET                            0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB                               8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB                               15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK                              0x000000000000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET                        0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB                           16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB                           23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK                          0x0000000000ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET                     0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB                        24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB                        31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK                       0x00000000ff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB                         32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB                         36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK                        0x0000001f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET                       0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB                          37
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB                          39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK                         0x000000e000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET                               0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB                                  40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB                                  41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK                                 0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB                             42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB                             46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK                            0x00007c0000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET                  0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB                     47
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK                    0x0000800000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET                          0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB                             48
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB                             55
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK                            0x00ff000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET                      0x0000000000000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB                         56
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB                         63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK                        0xff00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK                         0x0000000000000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB                 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB                 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK                0x000000000000007e
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET             0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB                7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB                10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK               0x0000000000000780
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB                  11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB                  12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK                 0x0000000000001800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK                         0x0000000000002000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK          0x0000000000004000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK                 0x0000000000008000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET      0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB         16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB         17
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK        0x0000000000030000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET                    0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB                       18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB                       20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK                      0x00000000001c0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK                  0x0000000000200000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB                  22
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB                  23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK                 0x0000000000c00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET              0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK                0x0000000001000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET           0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK             0x0000000002000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK                  0x0000000004000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB                          27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB                          31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK                         0x00000000f8000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET        0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB           32
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB           35
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK          0x0000000f00000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET               0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB                  36
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB                  39
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK                 0x000000f000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET                0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB                   40
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB                   41
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK                  0x0000030000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB                          42
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK                         0x0000040000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET                     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB                        43
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB                        45
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK                       0x0000380000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET                   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB                      46
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB                      50
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK                     0x0007c00000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET     0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB        51
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK       0x0008000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET                       0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB                          52
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB                          57
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK                         0x03f0000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET   0x0000000000000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB      58
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB      63
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK     0xfc00000000000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB    13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB    15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK   0x000000000000e000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET            0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB               16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB               27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK              0x000000000fff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET        0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB           28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB           31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK          0x00000000f0000000
+
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET                                 0x0000000000000018
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB                                    32
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB                                    47
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK                                   0x0000ffff00000000
+
+#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET                                       0x0000000000000018
+#define PDG_RESPONSE_RX_DURATION_FIELD_LSB                                          48
+#define PDG_RESPONSE_RX_DURATION_FIELD_MSB                                          63
+#define PDG_RESPONSE_RX_DURATION_FIELD_MASK                                         0xffff000000000000
+
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET                         0x0000000000000020
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK                           0x0000000000000001
+
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                        0x0000000000000020
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB                           1
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB                           16
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK                          0x000000000001fffe
+
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET                                 0x0000000000000020
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB                                    17
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB                                    18
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK                                   0x0000000000060000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET                                  0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK                                    0x0000000000080000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_LSB                                           20
+#define PDG_RESPONSE_RESPONSE_DENSITY_MSB                                           24
+#define PDG_RESPONSE_RESPONSE_DENSITY_MASK                                          0x0000000001f00000
+
+#define PDG_RESPONSE_MORE_DATA_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_MORE_DATA_LSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MASK                                                 0x0000000002000000
+
+#define PDG_RESPONSE_DURATION_INDICATION_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_DURATION_INDICATION_LSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MASK                                       0x0000000004000000
+
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET                                     0x0000000000000020
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB                                        27
+#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK                                       0x0000000008000000
+
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET                                      0x0000000000000020
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB                                         28
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB                                         28
+#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK                                        0x0000000010000000
+
+#define PDG_RESPONSE_BANDWIDTH_OFFSET                                               0x0000000000000020
+#define PDG_RESPONSE_BANDWIDTH_LSB                                                  29
+#define PDG_RESPONSE_BANDWIDTH_MSB                                                  31
+#define PDG_RESPONSE_BANDWIDTH_MASK                                                 0x00000000e0000000
+
+#define PDG_RESPONSE_ACK_ID_OFFSET                                                  0x0000000000000020
+#define PDG_RESPONSE_ACK_ID_LSB                                                     32
+#define PDG_RESPONSE_ACK_ID_MSB                                                     47
+#define PDG_RESPONSE_ACK_ID_MASK                                                    0x0000ffff00000000
+
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET                                        0x0000000000000020
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB                                           48
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB                                           63
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK                                          0xffff000000000000
+
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET                                     0x0000000000000028
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB                                        0
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB                                        3
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK                                       0x000000000000000f
+
+#define PDG_RESPONSE_ACK_ID_EXT_OFFSET                                              0x0000000000000028
+#define PDG_RESPONSE_ACK_ID_EXT_LSB                                                 4
+#define PDG_RESPONSE_ACK_ID_EXT_MSB                                                 13
+#define PDG_RESPONSE_ACK_ID_EXT_MASK                                                0x0000000000003ff0
+
+#define PDG_RESPONSE_FTM_EN_OFFSET                                                  0x0000000000000028
+#define PDG_RESPONSE_FTM_EN_LSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MASK                                                    0x0000000000004000
+
+#define PDG_RESPONSE_GROUP_ID_OFFSET                                                0x0000000000000028
+#define PDG_RESPONSE_GROUP_ID_LSB                                                   15
+#define PDG_RESPONSE_GROUP_ID_MSB                                                   20
+#define PDG_RESPONSE_GROUP_ID_MASK                                                  0x00000000001f8000
+
+#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET                                         0x0000000000000028
+#define PDG_RESPONSE_STA_PARTIAL_AID_LSB                                            21
+#define PDG_RESPONSE_STA_PARTIAL_AID_MSB                                            31
+#define PDG_RESPONSE_STA_PARTIAL_AID_MASK                                           0x00000000ffe00000
+
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET                                   0x0000000000000028
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB                                      32
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB                                      43
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK                                     0x00000fff00000000
+
+#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET                                          0x0000000000000028
+#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB                                             44
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB                                             46
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK                                            0x0000700000000000
+
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET                                  0x0000000000000028
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB                                     47
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK                                    0x0000800000000000
+
+#define PDG_RESPONSE_FRAME_LENGTH_OFFSET                                            0x0000000000000028
+#define PDG_RESPONSE_FRAME_LENGTH_LSB                                               48
+#define PDG_RESPONSE_FRAME_LENGTH_MSB                                               63
+#define PDG_RESPONSE_FRAME_LENGTH_MASK                                              0xffff000000000000
+
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET                              0x0000000000000030
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB                                 0
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB                                 3
+#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK                                0x000000000000000f
+
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                   0x0000000000000030
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB                      4
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB                      19
+#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK                     0x00000000000ffff0
+
+#define PDG_RESPONSE_PAD_DURATION_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_PAD_DURATION_LSB                                               20
+#define PDG_RESPONSE_PAD_DURATION_MSB                                               24
+#define PDG_RESPONSE_PAD_DURATION_MASK                                              0x0000000001f00000
+
+#define PDG_RESPONSE_Q2Q_MBA_OFFSET                                                 0x0000000000000030
+#define PDG_RESPONSE_Q2Q_MBA_LSB                                                    25
+#define PDG_RESPONSE_Q2Q_MBA_MSB                                                    25
+#define PDG_RESPONSE_Q2Q_MBA_MASK                                                   0x0000000002000000
+
+#define PDG_RESPONSE_RESERVED_12A_OFFSET                                            0x0000000000000030
+#define PDG_RESPONSE_RESERVED_12A_LSB                                               26
+#define PDG_RESPONSE_RESERVED_12A_MSB                                               31
+#define PDG_RESPONSE_RESERVED_12A_MASK                                              0x00000000fc000000
+
+#define PDG_RESPONSE_TLV64_PADDING_OFFSET                                           0x0000000000000030
+#define PDG_RESPONSE_TLV64_PADDING_LSB                                              32
+#define PDG_RESPONSE_TLV64_PADDING_MSB                                              63
+#define PDG_RESPONSE_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/pdg_response_rate_setting.h b/hw/wcn8750/v1/pdg_response_rate_setting.h
new file mode 100644
index 000000000000..eb123386f2bf
--- /dev/null
+++ b/hw/wcn8750/v1/pdg_response_rate_setting.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  1,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      pkt_type                                                :  4,
+                      smoothing                                               :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      stf_ltf_3db_boost                                       :  1,
+                      force_extra_symbol                                      :  1;
+             uint32_t reserved_2a                                             :  4,
+                      nss                                                     :  3,
+                      dpd_enable                                              :  1,
+                      tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_chain_mask                                           :  8;
+             uint32_t alt_rate_mcs                                            :  5,
+                      reserved_3a                                             :  3,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      ldpc_2x_codeword                                        :  1,
+                      tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8;
+             uint32_t aggregation                                             :  1,
+                      dot11ax_bss_color_id                                    :  6,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_4a                                             :  5;
+             uint32_t dot11ax_ext_ru_start_index                              :  4,
+                      dot11ax_ext_ru_size                                     :  4,
+                      eht_duplicate_mode                                      :  2,
+                      he_sigb_dcm                                             :  1,
+                      he_sigb_0_mcs                                           :  3,
+                      num_he_sigb_sym                                         :  5,
+                      required_response_time_source                           :  1,
+                      reserved_5a                                             :  6,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t required_response_time                                  : 12,
+                      dot11be_params_placeholder                              :  4;
+#else
+             uint32_t stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      smoothing                                               :  1,
+                      pkt_type                                                :  4,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      reserved_0a                                             :  1;
+             uint32_t force_extra_symbol                                      :  1,
+                      stf_ltf_3db_boost                                       :  1,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t tx_chain_mask                                           :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8,
+                      dpd_enable                                              :  1,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  4;
+             uint32_t alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8,
+                      ldpc_2x_codeword                                        :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      reserved_3a                                             :  3,
+                      alt_rate_mcs                                            :  5;
+             uint32_t reserved_4a                                             :  5,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_bss_color_id                                    :  6,
+                      aggregation                                             :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_5a                                             :  6,
+                      required_response_time_source                           :  1,
+                      num_he_sigb_sym                                         :  5,
+                      he_sigb_0_mcs                                           :  3,
+                      he_sigb_dcm                                             :  1,
+                      eht_duplicate_mode                                      :  2,
+                      dot11ax_ext_ru_size                                     :  4,
+                      dot11ax_ext_ru_start_index                              :  4;
+             uint32_t dot11be_params_placeholder                              :  4,
+                      required_response_time                                  : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET                                0x00000008
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB                                   3
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK                                  0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  4
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000001f
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   5
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000e0
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      14
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00007c00
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET                           0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB                              15
+#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK                             0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/pdg_tx_req.h b/hw/wcn8750/v1/pdg_tx_req.h
new file mode 100644
index 000000000000..6baf640807da
--- /dev/null
+++ b/hw/wcn8750/v1/pdg_tx_req.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PDG_TX_REQ_H_
+#define _PDG_TX_REQ_H_
+
+#define NUM_OF_DWORDS_PDG_TX_REQ 2
+
+#define NUM_OF_QWORDS_PDG_TX_REQ 1
+
+struct pdg_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_reason                                               :  2,
+                      use_puncture_pattern                                    :  2,
+                      req_bw                                                  :  3,
+                      puncture_pattern_number                                 :  6,
+                      reserved_0b                                             :  1,
+                      req_paprd                                               :  1,
+                      duration_field_boundary_valid                           :  1,
+                      duration_field_boundary                                 : 16;
+             uint32_t puncture_subband_mask                                   : 16,
+                      reserved_0c                                             : 16;
+#else
+             uint32_t duration_field_boundary                                 : 16,
+                      duration_field_boundary_valid                           :  1,
+                      req_paprd                                               :  1,
+                      reserved_0b                                             :  1,
+                      puncture_pattern_number                                 :  6,
+                      req_bw                                                  :  3,
+                      use_puncture_pattern                                    :  2,
+                      tx_reason                                               :  2;
+             uint32_t reserved_0c                                             : 16,
+                      puncture_subband_mask                                   : 16;
+#endif
+};
+
+#define PDG_TX_REQ_TX_REASON_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_TX_REASON_LSB                                                    0
+#define PDG_TX_REQ_TX_REASON_MSB                                                    1
+#define PDG_TX_REQ_TX_REASON_MASK                                                   0x0000000000000003
+
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET                                      0x0000000000000000
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB                                         2
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB                                         3
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK                                        0x000000000000000c
+
+#define PDG_TX_REQ_REQ_BW_OFFSET                                                    0x0000000000000000
+#define PDG_TX_REQ_REQ_BW_LSB                                                       4
+#define PDG_TX_REQ_REQ_BW_MSB                                                       6
+#define PDG_TX_REQ_REQ_BW_MASK                                                      0x0000000000000070
+
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB                                      7
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB                                      12
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK                                     0x0000000000001f80
+
+#define PDG_TX_REQ_RESERVED_0B_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0B_LSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MASK                                                 0x0000000000002000
+
+#define PDG_TX_REQ_REQ_PAPRD_OFFSET                                                 0x0000000000000000
+#define PDG_TX_REQ_REQ_PAPRD_LSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MASK                                                   0x0000000000004000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET                             0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK                               0x0000000000008000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET                                   0x0000000000000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB                                      16
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB                                      31
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK                                     0x00000000ffff0000
+
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET                                     0x0000000000000000
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB                                        32
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB                                        47
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK                                       0x0000ffff00000000
+
+#define PDG_TX_REQ_RESERVED_0C_OFFSET                                               0x0000000000000000
+#define PDG_TX_REQ_RESERVED_0C_LSB                                                  48
+#define PDG_TX_REQ_RESERVED_0C_MSB                                                  63
+#define PDG_TX_REQ_RESERVED_0C_MASK                                                 0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_abort_request_info.h b/hw/wcn8750/v1/phyrx_abort_request_info.h
new file mode 100644
index 000000000000..1f3bf4b817b9
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_abort_request_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phyrx_abort_reason                                      :  8,
+                      phy_enters_nap_state                                    :  1,
+                      phy_enters_defer_state                                  :  1,
+                      gain_change_by_main                                     :  1,
+                      gain_change_by_bt                                       :  1,
+                      main_tx_indication                                      :  1,
+                      bt_tx_indication                                        :  1,
+                      concurrent_mode                                         :  1,
+                      reserved_0                                              :  1,
+                      receive_duration                                        : 16;
+#else
+             uint32_t receive_duration                                        : 16,
+                      reserved_0                                              :  1,
+                      concurrent_mode                                         :  1,
+                      bt_tx_indication                                        :  1,
+                      main_tx_indication                                      :  1,
+                      gain_change_by_bt                                       :  1,
+                      gain_change_by_main                                     :  1,
+                      phy_enters_defer_state                                  :  1,
+                      phy_enters_nap_state                                    :  1,
+                      phyrx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB                             0
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB                             7
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET                        0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK                          0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET                      0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK                        0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET                         0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK                           0x00000400
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET                           0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK                             0x00000800
+
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK                            0x00001000
+
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK                              0x00002000
+
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET                             0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK                               0x00004000
+
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x00008000
+
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB                               16
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB                               31
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK                              0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_common_user_info.h b/hw/wcn8750/v1/phyrx_common_user_info.h
new file mode 100644
index 000000000000..e73d1ab47ee7
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_common_user_info.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
+
+#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
+
+struct phyrx_common_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t receive_duration                                        : 16,
+                      reserved_0a                                             : 16;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      eht___reserved_g_0005_ndp                                         :  1,
+                      reserved_1a                                             :  8,
+                      obss_nav_update_enable                                  :  1,
+                      obss_nav_value                                          : 16;
+             uint32_t eht_or_uhr_ppdu_type                                    :  2,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      txop_duration                                           :  7,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      spatial_reuse                                           :  4,
+                      rx_ndp                                                  :  1,
+                      dot11bn_su_elr                                          :  1,
+                      reserved_2a                                             :  6;
+             uint32_t eht_duplicate                                           :  2,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      doppler_indication                                      :  1,
+                      sta_id                                                  : 11,
+                      puncture_bitmap                                         : 16;
+#else
+             uint32_t reserved_0a                                             : 16,
+                      receive_duration                                        : 16;
+             uint32_t obss_nav_value                                          : 16,
+                      obss_nav_update_enable                                  :  1,
+                      reserved_1a                                             :  8,
+                      eht___reserved_g_0005_ndp                                         :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t reserved_2a                                             :  6,
+                      dot11bn_su_elr                                          :  1,
+                      rx_ndp                                                  :  1,
+                      spatial_reuse                                           :  4,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      txop_duration                                           :  7,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      eht_or_uhr_ppdu_type                                    :  2;
+             uint32_t puncture_bitmap                                         : 16,
+                      sta_id                                                  : 11,
+                      doppler_indication                                      :  1,
+                      eht_or_uhr_sig_cmn_field_type                           :  2,
+                      eht_duplicate                                           :  2;
+#endif
+};
+
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET                              0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB                                 0
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB                                 15
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK                                0x000000000000ffff
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB                                      16
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK                                     0x00000000ffff0000
+
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET               0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                  32
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                  37
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                 0x0000003f00000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB                                      39
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB                                      46
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK                                     0x00007f8000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET                        0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB                           47
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK                          0x0000800000000000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET                                0x0000000000000000
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB                                   48
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB                                   63
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK                                  0xffff000000000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET                          0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB                             0
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB                             1
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK                            0x0000000000000003
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET                                  0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB                                     2
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB                                     7
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK                                    0x00000000000000fc
+
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK                                      0x0000000000000100
+
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB                                    9
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB                                    15
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK                                   0x000000000000fe00
+
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET                                    0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB                                       16
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB                                       17
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK                                      0x0000000000030000
+
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET                                      0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB                                         18
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB                                         19
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK                                        0x00000000000c0000
+
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB                                    20
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB                                    23
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK                                   0x0000000000f00000
+
+#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK                                          0x0000000001000000
+
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET                                0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB                                   25
+#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK                                  0x0000000002000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET                                   0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB                                      26
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK                                     0x00000000fc000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET                                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB                                    32
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB                                    33
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK                                   0x0000000300000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET                 0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB                    34
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB                    35
+#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK                   0x0000000c00000000
+
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET                            0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB                               36
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK                              0x0000001000000000
+
+#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET                                        0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_STA_ID_LSB                                           37
+#define PHYRX_COMMON_USER_INFO_STA_ID_MSB                                           47
+#define PHYRX_COMMON_USER_INFO_STA_ID_MASK                                          0x0000ffe000000000
+
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET                               0x0000000000000008
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB                                  48
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB                                  63
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h b/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..da4f1691b9f7
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
+
+struct phyrx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x000000000000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x0000000000000010
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x00000000000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x0000000000007800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000000038000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x0000000001800000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      39
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x0000008000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  40
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  42
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             44
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x0000100000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h b/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..ff9cf72a7237
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
+
+struct phyrx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000000000000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00000000007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x0000000000800000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x0000000003000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    32
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    38
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      39
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      47
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff8000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              48
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              51
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             52
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             57
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      58
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      62
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c00000000000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_su.h b/hw/wcn8750/v1/phyrx_he_sig_a_su.h
new file mode 100644
index 000000000000..abca58673a90
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_a_su.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
+
+struct phyrx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x0000000000000001
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x0000000000000002
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x0000000000000004
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x0000000000000078
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x0000000000000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x0000000000003f00
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x0000000000004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x0000000000078000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x0000000000180000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x0000000000600000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x0000000003800000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0x00000000fc000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          32
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          38
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f00000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 39
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x0000008000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      40
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x0000010000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   41
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x0000020000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   42
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x0000040000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            46
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x0000400000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     47
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x0000800000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    48
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    51
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   52
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   57
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f0000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    58
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x0400000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    59
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    61
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x3800000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 62
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x4000000000000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h b/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..ae784469331b
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x00000000000000ff
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x000000007fffff00
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB                                        32
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB                                        63
+#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h b/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..6035ecffde5d
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x0000000000007800
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x000000000fe00000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x0000000070000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           32
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           39
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              40
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              47
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x0000000000000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          48
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          63
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h b/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..126a9559e155
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
+
+#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x00000000000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x0000000000003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x0000000000004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x0000000000078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x0000000000080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x0000000000100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x000000007fe00000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     32
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     39
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff00000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        40
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        47
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff0000000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    48
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    63
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_ht_sig.h b/hw/wcn8750/v1/phyrx_ht_sig.h
new file mode 100644
index 000000000000..4dd90653d431
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_ht_sig.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
+
+struct phyrx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#endif
+};
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x000000000000007f
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x0000000000000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x0000000000ffff00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0x00000000ff000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        32
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x0000000100000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     33
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x0000000200000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      34
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x0000000400000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      35
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x0000000800000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB                             36
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB                             37
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x0000003000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       38
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x0000004000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         39
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x0000008000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   40
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   41
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x0000030000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB                              42
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB                              49
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc0000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      50
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      55
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       56
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       62
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f00000000000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x0000000000000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        63
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_l_sig_a.h b/hw/wcn8750/v1/phyrx_l_sig_a.h
new file mode 100644
index 000000000000..2e70822f5d06
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_l_sig_a.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x0000000000000010
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x000000000001ffe0
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x0000000000020000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x0000000000fc0000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x000000000f000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x0000000010000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x0000000060000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_A_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_A_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_A_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_l_sig_b.h b/hw/wcn8750/v1/phyrx_l_sig_b.h
new file mode 100644
index 000000000000..461edd24dd4e
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_l_sig_b.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
+
+#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x000000000000000f
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x000000000000fff0
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x000000007fff0000
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x0000000000000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x0000000080000000
+
+#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET                                          0x0000000000000000
+#define PHYRX_L_SIG_B_TLV64_PADDING_LSB                                             32
+#define PHYRX_L_SIG_B_TLV64_PADDING_MSB                                             63
+#define PHYRX_L_SIG_B_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_location.h b/hw/wcn8750/v1/phyrx_location.h
new file mode 100644
index 000000000000..15a8413e304a
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_location.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_LOCATION_H_
+#define _PHYRX_LOCATION_H_
+
+#include "rx_location_info.h"
+#define NUM_OF_DWORDS_PHYRX_LOCATION 28
+
+#define NUM_OF_QWORDS_PHYRX_LOCATION 14
+
+struct phyrx_location {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_location_info                                          rx_location_info_details;
+#else
+             struct   rx_location_info                                          rx_location_info_details;
+#endif
+};
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET       0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK         0x0000000000000001
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET             0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK               0x0000000000000002
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET                   0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB                      4
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB                      7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK                     0x00000000000000f0
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET                  0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB                     8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK                    0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET            0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET              0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB                 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB                 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK                0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET     0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB        32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB        39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK       0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET    0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB       40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK      0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK                 0x00ff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET               0x0000000000000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB                  56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB                  63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK                 0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK   0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB    39
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK   0x000000ff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET                   0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB                      40
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK                     0x0000ff0000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB                  48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB                  51
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK                 0x000f000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET               0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB                  52
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB                  55
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK                 0x00f0000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET                 0x0000000000000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB                    56
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK                   0xff00000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET          0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB             0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB             15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK            0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET            0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK              0x0000000000ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB                     24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK                    0x00000000ff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET                  0x0000000000000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK                    0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET            0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB               0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB               31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK              0x00000000ffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET                    0x0000000000000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK                      0xffffffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK                    0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB                     16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK                    0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB                     32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB                     47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK                    0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET                  0x0000000000000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB                     48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB                     63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK                    0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET           0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB              0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB              7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK             0x00000000000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET       0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB          8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB          15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK         0x000000000000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET             0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB                16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB                31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK               0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET                    0x0000000000000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET                    0x0000000000000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK                      0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK                      0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB                       32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB                       47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK                      0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET                    0x0000000000000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB                       48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB                       63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK                      0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET                   0x0000000000000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET                   0x0000000000000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET                   0x0000000000000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET                   0x0000000000000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB                      32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB                      47
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK                     0x0000ffff00000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET                   0x0000000000000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB                      48
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB                      63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK                     0xffff000000000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK                     0x000000000000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET                   0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK                     0x00000000ffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET                 0x0000000000000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB                    32
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB                    63
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h b/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 000000000000..a6090f721e1d
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
+
+#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
+
+struct phyrx_other_receive_info_ru_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB                0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB                31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK               0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET             0x0000000000000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB                32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB                63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK               0xffffffff00000000
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET                            0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB                               0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB                               31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK                              0x00000000ffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET                    0x0000000000000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB                       32
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB                       63
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK                      0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_pkt_end.h b/hw/wcn8750/v1/phyrx_pkt_end.h
new file mode 100644
index 000000000000..1d1675edc0e1
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_pkt_end.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+
+#include "phyrx_pkt_end_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END 24
+
+#define NUM_OF_QWORDS_PHYRX_PKT_END 12
+
+struct phyrx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#else
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#endif
+};
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET                 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK                   0x0000000000000002
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET                   0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK                     0x0000000000000004
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET                     0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK                       0x0000000000000008
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK                           0x0000000000000010
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET            0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK              0x0000000000000020
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB                            6
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB                            7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK                           0x00000000000000c0
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET                           0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB                              8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB                              15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK                             0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET                         0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB                            16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB                            31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK                           0x00000000ffff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET     0x0000000000000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB        54
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB        63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK       0xffc0000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET                  0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB                     0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB                     31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK                    0x00000000ffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET                 0x0000000000000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB                    32
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB                    63
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK                   0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_pkt_end_info.h b/hw/wcn8750/v1/phyrx_pkt_end_info.h
new file mode 100644
index 000000000000..a21edc94d24e
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_pkt_end_info.h
@@ -0,0 +1,450 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+
+#include "receive_rssi_info.h"
+#include "rx_timing_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
+
+struct phyrx_pkt_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0001                                        :  1,
+                      location_info_valid                                     :  1,
+                      timing_info_valid                                       :  1,
+                      rssi_info_valid                                         :  1,
+                      reserved_0a                                             :  1,
+                      frameless_frame_received                                :  1,
+                      reserved_0b                                             :  2,
+                      rssi_comb                                               :  8,
+                      reserved_0c                                             : 16;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#else
+             uint32_t reserved_0c                                             : 16,
+                      rssi_comb                                               :  8,
+                      reserved_0b                                             :  2,
+                      frameless_frame_received                                :  1,
+                      reserved_0a                                             :  1,
+                      rssi_info_valid                                         :  1,
+                      timing_info_valid                                       :  1,
+                      location_info_valid                                     :  1,
+                      __reserved_g_0001                                        :  1;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#endif
+};
+
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET                               0x00000000
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK                                 0x00000002
+
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET                                 0x00000000
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK                                   0x00000004
+
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET                                   0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK                                     0x00000008
+
+#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK                                         0x00000010
+
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET                          0x00000000
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK                            0x00000020
+
+#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB                                          6
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB                                          7
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK                                         0x000000c0
+
+#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET                                         0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB                                            8
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB                                            15
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK                                           0x0000ff00
+
+#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB                                          16
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB                                          31
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK                                         0xffff0000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET   0x00000004
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET   0x00000008
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET   0x0000000c
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET   0x00000010
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET      0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB         0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB         11
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK        0x00000fff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET         0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB            12
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB            21
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK           0x003ff000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET                   0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB                      22
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB                      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK                     0xffc00000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET    0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET   0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET    0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET   0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET    0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET   0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET    0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET   0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET    0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET   0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET    0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET   0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET    0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET   0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET    0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET   0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET                                0x00000058
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB                                   0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB                                   31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK                                  0xffffffff
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET                               0x0000005c
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB                                  0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB                                  31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_rssi_legacy.h b/hw/wcn8750/v1/phyrx_rssi_legacy.h
new file mode 100644
index 000000000000..820ced6212ca
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_rssi_legacy.h
@@ -0,0 +1,806 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+
+#include "receive_rssi_info.h"
+#include "receive_pkt_start_info.h"
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
+
+#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21
+
+struct phyrx_rssi_legacy {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t rssi_comb_ppdu                                          :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_for_trigger_resp                                   :  8;
+#else
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8;
+             uint32_t rssi_for_trigger_resp                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_comb_ppdu                                          :  8;
+#endif
+};
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET                0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB                   0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB                   3
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK                  0x000000000000000f
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET            0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK              0x0000000000000010
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET             0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB                5
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x00000000000000e0
+
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET             PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB                PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK               PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK                   0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET                   0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB                      16
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB                      31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK                     0x00000000ffff0000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET     0x0000000000000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB        32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB        63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET    0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB       0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB       31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK      0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB         32
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB         39
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB          40
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK         0x0000010000000000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET                   0x0000000000000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB                      41
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB                      63
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK                     0xfffffe0000000000
+
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET                                   0x0000000000000010
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB                                      0
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB                                      31
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK                                     0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET                                        0x0000000000000010
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK                                          0x00000000ffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET                                        0x0000000000000018
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB                                           32
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB                                           63
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK                                          0xffffffff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET            0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET      0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET     0x0000000000000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET         0x0000000000000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET            0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET      0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET     0x0000000000000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET         0x0000000000000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET            0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET      0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET     0x0000000000000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET         0x0000000000000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK              0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET            0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK              0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK        0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK       0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET      0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB         32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB         39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK        0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB    40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB    47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK   0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB    48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB    55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK   0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET     0x0000000000000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB        56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB        63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK       0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK           0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK           0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK           0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK           0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB            32
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB            39
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK           0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB            40
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB            47
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK           0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB            48
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB            55
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK           0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET         0x0000000000000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB            56
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB            63
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK           0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET       0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET    0x0000000000000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET       0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET    0x0000000000000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET       0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET    0x0000000000000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK         0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET       0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK         0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK   0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK  0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB    32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB    39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK   0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB   56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB   63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK  0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK      0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK      0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK      0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK      0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB       32
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB       39
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK      0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB       40
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB       47
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK      0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB       48
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB       55
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK      0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET    0x0000000000000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB       56
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB       63
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK      0xff00000000000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET                                      0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB                                         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB                                         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK                                        0x00000000000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET                                          0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB                                             8
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB                                             15
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK                                            0x000000000000ff00
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET                           0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB                              16
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB                              23
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK                             0x0000000000ff0000
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET                               0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB                                  24
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB                                  31
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK                                 0x00000000ff000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET                                     0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB                                        32
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB                                        39
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK                                       0x000000ff00000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB                                 40
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB                                 47
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK                                0x0000ff0000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET                             0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB                                48
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB                                55
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK                               0x00ff000000000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET                              0x00000000000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB                                 56
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB                                 63
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_user_info.h b/hw/wcn8750/v1/phyrx_user_info.h
new file mode 100644
index 000000000000..d3dc8b6b2414
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
+
+#define NUM_OF_QWORDS_PHYRX_USER_INFO 4
+
+struct phyrx_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB                   0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB                   15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK                  0x000000000000ffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET                  0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB                     16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB                     23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK                    0x0000000000ff0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB                      24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB                      27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK                     0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET                       0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                         0x0000000010000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB                29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB                31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK               0x00000000e0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET                   0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB                      32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB                      36
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK                     0x0000001f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                           38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                          0x0000006000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET             0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB                40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB                47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK               0x0000ff0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET          0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB             48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB             50
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK            0x0007000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET                0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB                   51
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK                  0x00f8000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET        0x0000000000000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB           63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK          0xff00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET   0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK     0x0000000000000001
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK                  0x0000000000000002
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB                     2
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB                     3
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK                    0x000000000000000c
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB                     4
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB                     5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK                    0x0000000000000030
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET                  0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB                     6
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB                     7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK                    0x00000000000000c0
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                           8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                           10
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                          0x0000000000000700
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET              0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB                 11
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB                 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK                0x0000000000003800
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET                    0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK                      0x0000000000004000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET                       0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                         0x0000000000008000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB                  16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB                  19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK                 0x00000000000f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB                  20
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB                  23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK                 0x0000000000f00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB                  24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB                  27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK                 0x000000000f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET               0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB                  28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB                  31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK                 0x00000000f0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB           32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB           37
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK          0x0000003f00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB                   38
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB                   39
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK                  0x000000c000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB           40
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB           45
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK          0x00003f0000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB                   46
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB                   47
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK                  0x0000c00000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB           48
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB           53
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK          0x003f000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB                   54
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB                   55
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK                  0x00c0000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET        0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB           56
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB           61
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK          0x3f00000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET                0x0000000000000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB                   62
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB                   63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK                  0xc000000000000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET          0x0000000000000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK            0xffffffff00000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK            0x00000000ffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET          0x0000000000000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB             32
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB             63
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/phyrx_vht_sig_a.h b/hw/wcn8750/v1/phyrx_vht_sig_a.h
new file mode 100644
index 000000000000..e47f0e35adeb
--- /dev/null
+++ b/hw/wcn8750/v1/phyrx_vht_sig_a.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
+
+struct phyrx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x0000000000000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x0000000000000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x0000000000000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x00000000000003f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x00000000003ffc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x0000000000400000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x0000000000800000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0x00000000ff000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 32
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 33
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x0000000300000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               34
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x0000000400000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          35
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x0000000800000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        36
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        39
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 40
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x0000010000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            41
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x0000020000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        42
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        49
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc0000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       50
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       55
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 56
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 62
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f00000000000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  63
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/phytx_abort_request_info.h b/hw/wcn8750/v1/phytx_abort_request_info.h
new file mode 100644
index 000000000000..e4800f6a2d97
--- /dev/null
+++ b/hw/wcn8750/v1/phytx_abort_request_info.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t phytx_abort_reason                                      :  8,
+                      user_number                                             :  6,
+                      reserved                                                :  2;
+#else
+             uint16_t reserved                                                :  2,
+                      user_number                                             :  6,
+                      phytx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB                             0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB                             7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET                                 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB                                    8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB                                    13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK                                   0x00003f00
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET                                    0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB                                       14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB                                       15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK                                      0x0000c000
+
+#endif
diff --git a/hw/wcn8750/v1/phytx_pkt_end.h b/hw/wcn8750/v1/phytx_pkt_end.h
new file mode 100644
index 000000000000..55911ea9edb3
--- /dev/null
+++ b/hw/wcn8750/v1/phytx_pkt_end.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PKT_END_H_
+#define _PHYTX_PKT_END_H_
+
+#define NUM_OF_WORDS_PHYTX_PKT_END 28
+
+#define NUM_OF_DWORDS_PHYTX_PKT_END 14
+
+struct phytx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t tx_group_delay                                          : 12,
+                      timing_status                                           :  2,
+                      phyrx_entered_nap_state                                 :  1,
+                      dpdtrain_done                                           :  1;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t beamform_masked_user_bitmap_36_32                       :  5,
+                      reserved_23                                             : 11;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#else
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t dpdtrain_done                                           :  1,
+                      phyrx_entered_nap_state                                 :  1,
+                      timing_status                                           :  2,
+                      tx_group_delay                                          : 12;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t reserved_23                                             : 11,
+                      beamform_masked_user_bitmap_36_32                       :  5;
+             uint16_t reserved_26                                             : 16;
+             uint16_t reserved_27                                             : 16;
+#endif
+};
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET                          0x00000000
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB                             0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB                             15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK                            0x0000ffff
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET                         0x00000002
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB                            0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB                            15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK                           0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET                            0x00000004
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB                               0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB                               15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK                              0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET                           0x00000006
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB                              0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB                              15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK                             0x0000ffff
+
+#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET                                         0x00000008
+#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB                                            11
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK                                           0x00000fff
+
+#define PHYTX_PKT_END_TIMING_STATUS_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_TIMING_STATUS_LSB                                             12
+#define PHYTX_PKT_END_TIMING_STATUS_MSB                                             13
+#define PHYTX_PKT_END_TIMING_STATUS_MASK                                            0x00003000
+
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET                                0x00000008
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK                                  0x00004000
+
+#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK                                            0x00008000
+
+#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET                                         0x0000000a
+#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB                                            15
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK                                           0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET                                  0x0000000c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB                                     0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB                                     15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK                                    0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET                                 0x0000000e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET                                 0x00000010
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET                                 0x00000012
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET                                0x00000014
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET                                0x00000016
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET                                0x00000018
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET                                0x0000001a
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET                                 0x0000001c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET                                0x0000001e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET                                0x00000020
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET                                0x00000022
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET                                0x00000024
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET                              0x00000026
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB                                 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB                                 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK                                0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET                             0x00000028
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET                             0x0000002a
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET                             0x0000002c
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                       0x0000002e
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                          0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                          15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                         0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                      0x00000030
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                         15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                        0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                      0x00000032
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                         4
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                        0x0000001f
+
+#define PHYTX_PKT_END_RESERVED_23_OFFSET                                            0x00000032
+#define PHYTX_PKT_END_RESERVED_23_LSB                                               5
+#define PHYTX_PKT_END_RESERVED_23_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_23_MASK                                              0x0000ffe0
+
+#define PHYTX_PKT_END_RESERVED_26_OFFSET                                            0x00000034
+#define PHYTX_PKT_END_RESERVED_26_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_26_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_26_MASK                                              0x0000ffff
+
+#define PHYTX_PKT_END_RESERVED_27_OFFSET                                            0x00000036
+#define PHYTX_PKT_END_RESERVED_27_LSB                                               0
+#define PHYTX_PKT_END_RESERVED_27_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_27_MASK                                              0x0000ffff
+
+#endif
diff --git a/hw/wcn8750/v1/phytx_ppdu_header_info_request.h b/hw/wcn8750/v1/phytx_ppdu_header_info_request.h
new file mode 100644
index 000000000000..7fbecae41236
--- /dev/null
+++ b/hw/wcn8750/v1/phytx_ppdu_header_info_request.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+
+#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
+
+#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
+
+struct phytx_ppdu_header_info_request {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t request_type                                            :  5,
+                      reserved                                                : 11;
+             uint16_t tlv32_padding                                           : 16;
+#else
+             uint16_t reserved                                                : 11,
+                      request_type                                            :  5;
+             uint16_t tlv32_padding                                           : 16;
+#endif
+};
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET                          0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB                             0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB                             4
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK                            0x0000001f
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET                              0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB                                 5
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB                                 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK                                0x0000ffe0
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET                         0x00000002
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB                            0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB                            15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK                           0x0000ffff
+
+#endif
diff --git a/hw/wcn8750/v1/receive_pkt_start_info.h b/hw/wcn8750/v1/receive_pkt_start_info.h
new file mode 100644
index 000000000000..7f7c81449a15
--- /dev/null
+++ b/hw/wcn8750/v1/receive_pkt_start_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_PKT_START_INFO_H_
+#define _RECEIVE_PKT_START_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
+
+struct receive_pkt_start_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reception_type                                          :  4,
+                      rx_chain_mask_type                                      :  1,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask                                           :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t preamble_time_to_rxframe                                :  8,
+                      standalone_sniffer_mode                                 :  1,
+                      reserved_3a                                             : 23;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      rx_chain_mask                                           :  8,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask_type                                      :  1,
+                      reception_type                                          :  4;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t reserved_3a                                             : 23,
+                      standalone_sniffer_mode                                 :  1,
+                      preamble_time_to_rxframe                                :  8;
+#endif
+};
+
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET                                0x00000000
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB                                   0
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB                                   3
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK                                  0x0000000f
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET                            0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK                              0x00000010
+
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET                             0x00000000
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB                                5
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB                                7
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK                               0x000000e0
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET                                 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB                                    8
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB                                    15
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK                                   0x0000ff00
+
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET                                   0x00000000
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB                                      16
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB                                      31
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK                                     0xffff0000
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET                     0x00000004
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB                        0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB                        31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK                       0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET                    0x00000008
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB                       0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB                       31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK                      0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET                      0x0000000c
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB                         0
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB                         7
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK                        0x000000ff
+
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET                       0x0000000c
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK                         0x00000100
+
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB                                      9
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB                                      31
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK                                     0xfffffe00
+
+#endif
diff --git a/hw/wcn8750/v1/receive_rssi_info.h b/hw/wcn8750/v1/receive_rssi_info.h
new file mode 100644
index 000000000000..9aaa98217d99
--- /dev/null
+++ b/hw/wcn8750/v1/receive_rssi_info.h
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_pri20_chain0                                       :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext40_high20_chain0                                :  8;
+             uint32_t rssi_ext80_low20_chain0                                 :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_high20_chain0                                :  8;
+             uint32_t rssi_ext160_0_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_3_chain0                                    :  8;
+             uint32_t rssi_ext160_4_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_7_chain0                                    :  8;
+             uint32_t rssi_pri20_chain1                                       :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext40_high20_chain1                                :  8;
+             uint32_t rssi_ext80_low20_chain1                                 :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_high20_chain1                                :  8;
+             uint32_t rssi_ext160_0_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_3_chain1                                    :  8;
+             uint32_t rssi_ext160_4_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_7_chain1                                    :  8;
+             uint32_t rssi_pri20_chain2                                       :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext40_high20_chain2                                :  8;
+             uint32_t rssi_ext80_low20_chain2                                 :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_high20_chain2                                :  8;
+             uint32_t rssi_ext160_0_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_3_chain2                                    :  8;
+             uint32_t rssi_ext160_4_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_7_chain2                                    :  8;
+             uint32_t rssi_pri20_chain3                                       :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext40_high20_chain3                                :  8;
+             uint32_t rssi_ext80_low20_chain3                                 :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_high20_chain3                                :  8;
+             uint32_t rssi_ext160_0_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_3_chain3                                    :  8;
+             uint32_t rssi_ext160_4_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_7_chain3                                    :  8;
+#else
+             uint32_t rssi_ext40_high20_chain0                                :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_pri20_chain0                                       :  8;
+             uint32_t rssi_ext80_high20_chain0                                :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_low20_chain0                                 :  8;
+             uint32_t rssi_ext160_3_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_0_chain0                                    :  8;
+             uint32_t rssi_ext160_7_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_4_chain0                                    :  8;
+             uint32_t rssi_ext40_high20_chain1                                :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_pri20_chain1                                       :  8;
+             uint32_t rssi_ext80_high20_chain1                                :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_low20_chain1                                 :  8;
+             uint32_t rssi_ext160_3_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_0_chain1                                    :  8;
+             uint32_t rssi_ext160_7_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_4_chain1                                    :  8;
+             uint32_t rssi_ext40_high20_chain2                                :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_pri20_chain2                                       :  8;
+             uint32_t rssi_ext80_high20_chain2                                :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_low20_chain2                                 :  8;
+             uint32_t rssi_ext160_3_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_0_chain2                                    :  8;
+             uint32_t rssi_ext160_7_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_4_chain2                                    :  8;
+             uint32_t rssi_ext40_high20_chain3                                :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_pri20_chain3                                       :  8;
+             uint32_t rssi_ext80_high20_chain3                                :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_low20_chain3                                 :  8;
+             uint32_t rssi_ext160_3_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_0_chain3                                    :  8;
+             uint32_t rssi_ext160_7_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_4_chain3                                    :  8;
+#endif
+};
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET                            0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET                           0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET                            0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET                           0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET                            0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET                           0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET                            0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET                           0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET                            0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET                           0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET                            0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET                           0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET                            0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET                           0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET                            0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET                           0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK                                 0xff000000
+
+#endif
diff --git a/hw/wcn8750/v1/receive_user_info.h b/hw/wcn8750/v1/receive_user_info.h
new file mode 100644
index 000000000000..23daabab5dc8
--- /dev/null
+++ b/hw/wcn8750/v1/receive_user_info.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
+
+struct receive_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      stbc                                                    :  1,
+                      reception_type                                          :  3;
+             uint32_t rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      __reserved_g_0004                                          :  1,
+                      mimo_ss_bitmap                                          :  8,
+                      receive_bandwidth                                       :  3,
+                      reserved_1b                                             :  5,
+                      dl_ofdma_user_index                                     :  8;
+             uint32_t dl_ofdma_content_channel                                :  1,
+                      reserved_2a                                             :  1,
+                      qam_diff1                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff3                                               :  2,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      sta_dcm                                                 :  1,
+                      ldpc                                                    :  1,
+                      ru_type_80_0                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_3                                            :  4;
+             uint32_t ru_start_index_80_0                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3d                                             :  2;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#else
+             uint32_t reception_type                                          :  3,
+                      stbc                                                    :  1,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t dl_ofdma_user_index                                     :  8,
+                      reserved_1b                                             :  5,
+                      receive_bandwidth                                       :  3,
+                      mimo_ss_bitmap                                          :  8,
+                      __reserved_g_0004                                          :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5;
+             uint32_t ru_type_80_3                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_0                                            :  4,
+                      ldpc                                                    :  1,
+                      sta_dcm                                                 :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      qam_diff3                                               :  2,
+                      qam_diff2                                               :  2,
+                      qam_diff1                                               :  2,
+                      reserved_2a                                             :  1,
+                      dl_ofdma_content_channel                                :  1;
+             uint32_t reserved_3d                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_0                                     :  6;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#endif
+};
+
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
+#define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
+#define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
+#define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
+
+#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
+#define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
+#define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
+#define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
+
+#define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
+#define RECEIVE_USER_INFO_STBC_LSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
+
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
+
+#define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
+#define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
+#define RECEIVE_USER_INFO_RATE_MCS_MSB                                              4
+#define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000001f
+
+#define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
+#define RECEIVE_USER_INFO_SGI_LSB                                                   5
+#define RECEIVE_USER_INFO_SGI_MSB                                                   6
+#define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000060
+
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
+
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
+
+#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
+#define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
+
+#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
+#define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x00000002
+
+#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF1_LSB                                             2
+#define RECEIVE_USER_INFO_QAM_DIFF1_MSB                                             3
+#define RECEIVE_USER_INFO_QAM_DIFF1_MASK                                            0x0000000c
+
+#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF2_LSB                                             4
+#define RECEIVE_USER_INFO_QAM_DIFF2_MSB                                             5
+#define RECEIVE_USER_INFO_QAM_DIFF2_MASK                                            0x00000030
+
+#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET                                          0x00000008
+#define RECEIVE_USER_INFO_QAM_DIFF3_LSB                                             6
+#define RECEIVE_USER_INFO_QAM_DIFF3_MSB                                             7
+#define RECEIVE_USER_INFO_QAM_DIFF3_MASK                                            0x000000c0
+
+#define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
+#define RECEIVE_USER_INFO_NSS_LSB                                                   8
+#define RECEIVE_USER_INFO_NSS_MSB                                                   10
+#define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
+
+#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
+#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
+
+#define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
+#define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
+
+#define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
+#define RECEIVE_USER_INFO_LDPC_LSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
+
+#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
+#define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
+
+#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
+#define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
+#define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
+
+#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
+#define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
+
+#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
+#define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
+#define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_15_8.h b/hw/wcn8750/v1/received_response_user_15_8.h
new file mode 100644
index 000000000000..6cf8117ff02f
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_15_8.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_15_8_H_
+#define _RECEIVED_RESPONSE_USER_15_8_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32
+
+struct received_response_user_15_8 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#else
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET     0x0000000000000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET     0x0000000000000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB        48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB        63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK       0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET    0x0000000000000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET    0x0000000000000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET    0x0000000000000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET    0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET    0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET    0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB       48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB       63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK      0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_23_16.h b/hw/wcn8750/v1/received_response_user_23_16.h
new file mode 100644
index 000000000000..ff56f4d96472
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_23_16.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_23_16_H_
+#define _RECEIVED_RESPONSE_USER_23_16_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32
+
+struct received_response_user_23_16 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#else
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_31_24.h b/hw/wcn8750/v1/received_response_user_31_24.h
new file mode 100644
index 000000000000..aaa90838daa9
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_31_24.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_31_24_H_
+#define _RECEIVED_RESPONSE_USER_31_24_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32
+
+struct received_response_user_31_24 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#else
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET   0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET   0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET   0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_36_32.h b/hw/wcn8750/v1/received_response_user_36_32.h
new file mode 100644
index 000000000000..3f33fdab635e
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_36_32.h
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
+#define _RECEIVED_RESPONSE_USER_36_32_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20
+
+struct received_response_user_36_32 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#else
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET   0x0000000000000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET   0x0000000000000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET   0x0000000000000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET   0x0000000000000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET   0x0000000000000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB      48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB      63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK     0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_7_0.h b/hw/wcn8750/v1/received_response_user_7_0.h
new file mode 100644
index 000000000000..f785aca46840
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_7_0.h
@@ -0,0 +1,1116 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_7_0_H_
+#define _RECEIVED_RESPONSE_USER_7_0_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64
+
+#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32
+
+struct received_response_user_7_0 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#else
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET      0x0000000000000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET      0x0000000000000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET      0x0000000000000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET      0x0000000000000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET      0x0000000000000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET      0x00000000000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET      0x00000000000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB  54
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB  62
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK  0x00000000ffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET      0x00000000000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB         48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB         63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK        0xffff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_response_user_info.h b/hw/wcn8750/v1/received_response_user_info.h
new file mode 100644
index 000000000000..3c3faf119635
--- /dev/null
+++ b/hw/wcn8750/v1/received_response_user_info.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_fcs_pass_count                                     : 12,
+                      mpdu_fcs_fail_count                                     : 12,
+                      qosnull_frame_count                                     :  4,
+                      reserved_0a                                             :  3,
+                      user_info_valid                                         :  1;
+             uint32_t null_delimiter_count                                    : 22,
+                      reserved_1a                                             :  9,
+                      ht_control_valid                                        :  1;
+             uint32_t ht_control                                              : 32;
+             uint32_t qos_control_valid                                       : 16,
+                      eosp                                                    : 16;
+             uint32_t qos_control_15_8_tid_0                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_3                                  :  8;
+             uint32_t qos_control_15_8_tid_4                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_7                                  :  8;
+             uint32_t qos_control_15_8_tid_8                                  :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_11                                 :  8;
+             uint32_t qos_control_15_8_tid_12                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_15                                 :  8;
+#else
+             uint32_t user_info_valid                                         :  1,
+                      reserved_0a                                             :  3,
+                      qosnull_frame_count                                     :  4,
+                      mpdu_fcs_fail_count                                     : 12,
+                      mpdu_fcs_pass_count                                     : 12;
+             uint32_t ht_control_valid                                        :  1,
+                      reserved_1a                                             :  9,
+                      null_delimiter_count                                    : 22;
+             uint32_t ht_control                                              : 32;
+             uint32_t eosp                                                    : 16,
+                      qos_control_valid                                       : 16;
+             uint32_t qos_control_15_8_tid_3                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_0                                  :  8;
+             uint32_t qos_control_15_8_tid_7                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_4                                  :  8;
+             uint32_t qos_control_15_8_tid_11                                 :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_8                                  :  8;
+             uint32_t qos_control_15_8_tid_15                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_12                                 :  8;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_trigger_info.h b/hw/wcn8750/v1/received_trigger_info.h
new file mode 100644
index 000000000000..ff464f4e3bb5
--- /dev/null
+++ b/hw/wcn8750/v1/received_trigger_info.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_H_
+#define _RECEIVED_TRIGGER_INFO_H_
+
+#include "received_trigger_info_details.h"
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
+
+#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
+
+struct received_trigger_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_trigger_info_details                             received_trigger_details;
+#else
+             struct   received_trigger_info_details                             received_trigger_details;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET          0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB             0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB             3
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK            0x000000000000000f
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK       0x0000000000000010
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB          5
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB          8
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK         0x00000000000001e0
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET   0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK     0x0000000000400000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK       0x0000000000800000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK   0x0000000001000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET     0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB        29
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB        30
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK       0x0000000060000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB              32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB              47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK             0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET  0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB     48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB     59
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK    0x0fff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB              61
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK             0x2000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET       0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB          62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK         0x4000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET           0x0000000000000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK             0x8000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET         0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB            0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB            15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK           0x000000000000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB              16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK             0x00000000ffff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET            0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB               32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB               47
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK              0x0000ffff00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET           0x0000000000000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB              62
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK             0xc000000000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET            0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB               0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB               31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK              0x00000000ffffffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET           0x0000000000000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB              40
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB              63
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK             0xffffff0000000000
+
+#endif
diff --git a/hw/wcn8750/v1/received_trigger_info_details.h b/hw/wcn8750/v1/received_trigger_info_details.h
new file mode 100644
index 000000000000..ae169bca026b
--- /dev/null
+++ b/hw/wcn8750/v1/received_trigger_info_details.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t trigger_type                                            :  4,
+                      ax_trigger_source                                       :  1,
+                      ax_trigger_type                                         :  4,
+                      trigger_source_sta_full_aid                             : 13,
+                      frame_control_valid                                     :  1,
+                      qos_control_valid                                       :  1,
+                      he_control_info_valid                                   :  1,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      txop_sharing_mode                                       :  2,
+                      tid_aggregation_limit_is_zero                           :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      lsig_response_length                                    : 12,
+                      __reserved_g_0086                                                 :  1,
+                      scsid_valid                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      reserved_1a                                             :  1;
+             uint32_t frame_control                                           : 16,
+                      qos_control                                             : 16;
+             uint32_t sw_peer_id                                              : 16,
+                      txop_sharing_allocation_duration                        :  9,
+                      __reserved_g_0074                                       :  4,
+                      __reserved_g_0034                                       :  1,
+                      reserved_3a                                             :  2;
+             uint32_t he_control                                              : 32;
+             uint32_t txop_sharing_duration_from_durid                        :  1,
+                      frame_durationid_lower_4                                :  4,
+                      frame_durationid_upper_3                                :  3,
+                      reserved_5a                                             : 24;
+#else
+             uint32_t tid_aggregation_limit_is_zero                           :  1,
+                      txop_sharing_mode                                       :  2,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      he_control_info_valid                                   :  1,
+                      qos_control_valid                                       :  1,
+                      frame_control_valid                                     :  1,
+                      trigger_source_sta_full_aid                             : 13,
+                      ax_trigger_type                                         :  4,
+                      ax_trigger_source                                       :  1,
+                      trigger_type                                            :  4;
+             uint32_t reserved_1a                                             :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      scsid_valid                                             :  1,
+                      __reserved_g_0086                                                 :  1,
+                      lsig_response_length                                    : 12,
+                      phy_ppdu_id                                             : 16;
+             uint32_t qos_control                                             : 16,
+                      frame_control                                           : 16;
+             uint32_t reserved_3a                                             :  2,
+                      __reserved_g_0034                                       :  1,
+                      __reserved_g_0074                                       :  4,
+                      txop_sharing_allocation_duration                        :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t he_control                                              : 32;
+             uint32_t reserved_5a                                             : 24,
+                      frame_durationid_upper_3                                :  3,
+                      frame_durationid_lower_4                                :  4,
+                      txop_sharing_duration_from_durid                        :  1;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET                           0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB                              0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB                              3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK                             0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK                        0x00000010
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET                        0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB                           5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB                           8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK                          0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB               9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB               21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK              0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET                    0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK                      0x00400000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK                        0x00800000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET                  0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK                    0x01000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB                         29
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB                         30
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK                        0x60000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET          0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK            0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB                               0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB                               15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK                              0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                   0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB                      16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB                      27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK                     0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB                               29
+#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK                              0x20000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET                        0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB                           30
+#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK                          0x40000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK                              0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET                          0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB                             0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB                             15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK                            0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET                            0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK                              0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET                             0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB                                15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK                               0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET       0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB          16
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB          24
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK         0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET                            0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB                               30
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK                              0xc0000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET                             0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB                                31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK                               0xffffffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET       0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB          0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK         0x00000001
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB                  1
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB                  4
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK                 0x0000001e
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET               0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB                  5
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB                  7
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK                 0x000000e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET                            0x00000014
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB                               8
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK                              0xffffff00
+
+#endif
diff --git a/hw/wcn8750/v1/reo_destination_ring.h b/hw/wcn8750/v1/reo_destination_ring.h
new file mode 100644
index 000000000000..5147635121c1
--- /dev/null
+++ b/hw/wcn8750/v1/reo_destination_ring.h
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
+
+struct reo_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB               0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB               7
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK              0x000000ff
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET         0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK           0x00000100
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET        0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK          0x00000200
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK              0x00000400
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET             0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK               0x00000800
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                0x00002000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET    0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK      0x00004000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                 15
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                 26
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                0x07ff8000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK  0x08000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                   0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                      28
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                      31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                     0xf0000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET        0x0000000c
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB           0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB           31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK          0xffffffff
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET                           0x00000014
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB                              0
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB                              2
+#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK                             0x00000007
+
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB                           3
+#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK                          0x00000008
+
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET                               0x00000014
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB                                  4
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB                                  5
+#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK                                 0x00000030
+
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB                                   6
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB                                   10
+#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK                                  0x000007c0
+
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB                                   11
+#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK                                  0x00000800
+
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET                                0x00000014
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB                                   12
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB                                   31
+#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK                                  0xfffff000
+
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET                            0x00000018
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB                               0
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB                               3
+#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK                              0x0000000f
+
+#define REO_DESTINATION_RING_RESERVED_6A_OFFSET                                     0x00000018
+#define REO_DESTINATION_RING_RESERVED_6A_LSB                                        4
+#define REO_DESTINATION_RING_RESERVED_6A_MSB                                        31
+#define REO_DESTINATION_RING_RESERVED_6A_MASK                                       0xfffffff0
+
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK                              0x00000001
+
+#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB                                    1
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB                                    2
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK                                   0x00000006
+
+#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET                                  0x0000001c
+#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB                                     3
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB                                     7
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK                                    0x000000f8
+
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB                            8
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB                            11
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK                           0x00000f00
+
+#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET                                    0x0000001c
+#define REO_DESTINATION_RING_SW_EXCEPTION_LSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MASK                                      0x00001000
+
+#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET                                     0x0000001c
+#define REO_DESTINATION_RING_SRC_LINK_ID_LSB                                        13
+#define REO_DESTINATION_RING_SRC_LINK_ID_MSB                                        15
+#define REO_DESTINATION_RING_SRC_LINK_ID_MASK                                       0x0000e000
+
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB                   16
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB                   19
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK                  0x000f0000
+
+#define REO_DESTINATION_RING_RING_ID_OFFSET                                         0x0000001c
+#define REO_DESTINATION_RING_RING_ID_LSB                                            20
+#define REO_DESTINATION_RING_RING_ID_MSB                                            27
+#define REO_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
+
+#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000001c
+#define REO_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define REO_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define REO_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/reo_destination_ring_with_pn.h b/hw/wcn8750/v1/reo_destination_ring_with_pn.h
new file mode 100644
index 000000000000..b486a8658388
--- /dev/null
+++ b/hw/wcn8750/v1/reo_destination_ring_with_pn.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_DESTINATION_RING_WITH_PN_H_
+#define _REO_DESTINATION_RING_WITH_PN_H_
+
+#include "rx_msdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
+
+struct reo_destination_ring_with_pn {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t msdu_count                                              :  8,
+                      prev_pn_23_0                                            : 24;
+             uint32_t prev_pn_47_24                                           : 24,
+                      prev_pn_127_48_info                                     :  2,
+                      reserved_3a                                             :  6;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t release_source_module                                   :  3,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_delink_error                                        :  1,
+                      sw_buffer_cookie                                        : 20;
+             uint32_t msdu_link_desc_index                                    :  4,
+                      reserved_6a                                             : 28;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_virt_addr_or_addr_info;
+             uint32_t prev_pn_23_0                                            : 24,
+                      msdu_count                                              :  8;
+             uint32_t reserved_3a                                             :  6,
+                      prev_pn_127_48_info                                     :  2,
+                      prev_pn_47_24                                           : 24;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      reo_delink_error                                        :  1,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t reserved_6a                                             : 28,
+                      msdu_link_desc_index                                    :  4;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET                              0x00000008
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB                                 0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB                                 7
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK                                0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET                            0x00000008
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB                               8
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB                               31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK                              0xffffff00
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET                           0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB                              0
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB                              23
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK                             0x00ffffff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET                     0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB                        24
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB                        25
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK                       0x03000000
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET                             0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB                                26
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK                               0xfc000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB      3
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB      16
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK     0x0001fff8
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK       0x00020000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK     0x00040000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK     0x00080000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET    0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK      0x00100000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK  0x00800000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK           0x01000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK           0x02000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK       0x04000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB     27
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB     28
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK    0x18000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB     29
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB     30
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK    0x60000000
+
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET                   0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB                      0
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB                      2
+#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK                     0x00000007
+
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET                0x00000014
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB                   3
+#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK                  0x00000008
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET                       0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB                          4
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB                          5
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK                         0x00000030
+
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB                           6
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB                           10
+#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK                          0x000007c0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB                           11
+#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK                          0x00000800
+
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET                        0x00000014
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB                           12
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB                           31
+#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET                    0x00000018
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB                       3
+#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK                      0x0000000f
+
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET                             0x00000018
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB                                4
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB                                31
+#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK                               0xfffffff0
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET                    0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK                      0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB                            1
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB                            2
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK                           0x00000006
+
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET                          0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB                             3
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB                             7
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK                            0x000000f8
+
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB                    8
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB                    11
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK                   0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK                              0x00001000
+
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET                             0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB                                13
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB                                15
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK                               0x0000e000
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET        0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB           16
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB           19
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK          0x000f0000
+
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB                                    20
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB                                    27
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK                                   0x0ff00000
+
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET                           0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB                              28
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB                              31
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/reo_entrance_ring.h b/hw/wcn8750/v1/reo_entrance_ring.h
new file mode 100644
index 000000000000..17a68d08ce25
--- /dev/null
+++ b/hw/wcn8750/v1/reo_entrance_ring.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+
+#include "rx_mpdu_details.h"
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12
+
+struct reo_entrance_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_preamble_timestamp                                   : 32;
+             uint32_t reserved_7a                                             :  8,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reo_destination_indication                              :  5,
+                      frameless_bar                                           :  1,
+                      reserved_7b                                             :  4;
+             uint32_t rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      mpdu_fragment_number                                    :  4,
+                      sw_exception                                            :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_destination_ring                           :  5,
+                      mpdu_sequence_number                                    : 12,
+                      no_ack                                                  :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      src_link_id                                             :  3,
+                      reserved_9a                                             :  5,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t receive_queue_number                                    : 16,
+                      fw_reorder_push_reason                                  :  2,
+                      fw_reorder_error_code                                   :  5,
+                      reo_bypass                                              :  1,
+                      reserved_10a                                            :  8;
+             uint32_t phy_lmac_latency                                        : 16,
+                      reserved_15a                                            :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_preamble_timestamp                                   : 32;
+             uint32_t reserved_7b                                             :  4,
+                      frameless_bar                                           :  1,
+                      reo_destination_indication                              :  5,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reserved_7a                                             :  8;
+             uint32_t no_ack                                                  :  1,
+                      mpdu_sequence_number                                    : 12,
+                      sw_exception_destination_ring                           :  5,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception                                            :  1,
+                      mpdu_fragment_number                                    :  4,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      reserved_9a                                             :  5,
+                      src_link_id                                             :  3,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_10a                                            :  8,
+                      reo_bypass                                              :  1,
+                      fw_reorder_error_code                                   :  5,
+                      fw_reorder_push_reason                                  :  2,
+                      receive_queue_number                                    : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            :  4,
+                      phy_lmac_latency                                        : 16;
+#endif
+};
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000
+
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET                              0x00000018
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB                                 0
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB                                 31
+#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK                                0xffffffff
+
+#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7A_LSB                                           0
+#define REO_ENTRANCE_RING_RESERVED_7A_MSB                                           7
+#define REO_ENTRANCE_RING_RESERVED_7A_MASK                                          0x000000ff
+
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET                            0x0000001c
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB                               8
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB                               21
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK                              0x003fff00
+
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET                         0x0000001c
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB                            22
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB                            26
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK                           0x07c00000
+
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET                                      0x0000001c
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK                                        0x08000000
+
+#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7B_LSB                                           28
+#define REO_ENTRANCE_RING_RESERVED_7B_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_7B_MASK                                          0xf0000000
+
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET                                  0x00000020
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB                                     0
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB                                     1
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK                                    0x00000003
+
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET                                   0x00000020
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB                                      2
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB                                      6
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK                                     0x0000007c
+
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB                                  7
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB                                  10
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK                                 0x00000780
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET                                       0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK                                         0x00000800
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET                           0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK                             0x00001000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET                0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK                  0x00002000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET                      0x00000020
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB                         14
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB                         18
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK                        0x0007c000
+
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET                               0x00000020
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB                                  19
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB                                  30
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK                                 0x7ff80000
+
+#define REO_ENTRANCE_RING_NO_ACK_OFFSET                                             0x00000020
+#define REO_ENTRANCE_RING_NO_ACK_LSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MSB                                                31
+#define REO_ENTRANCE_RING_NO_ACK_MASK                                               0x80000000
+
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB                                           0
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB                                           15
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB                                           16
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB                                           18
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK                                          0x00070000
+
+#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET                                        0x00000024
+#define REO_ENTRANCE_RING_RESERVED_9A_LSB                                           19
+#define REO_ENTRANCE_RING_RESERVED_9A_MSB                                           23
+#define REO_ENTRANCE_RING_RESERVED_9A_MASK                                          0x00f80000
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                       0x00000024
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                          24
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                          31
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                         0xff000000
+
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET                               0x00000028
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB                                  0
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB                                  15
+#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK                                 0x0000ffff
+
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET                             0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB                                16
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB                                17
+#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK                               0x00030000
+
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET                              0x00000028
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB                                 18
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB                                 22
+#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK                                0x007c0000
+
+#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET                                         0x00000028
+#define REO_ENTRANCE_RING_REO_BYPASS_LSB                                            23
+#define REO_ENTRANCE_RING_REO_BYPASS_MSB                                            23
+#define REO_ENTRANCE_RING_REO_BYPASS_MASK                                           0x00800000
+
+#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET                                       0x00000028
+#define REO_ENTRANCE_RING_RESERVED_10A_LSB                                          24
+#define REO_ENTRANCE_RING_RESERVED_10A_MSB                                          31
+#define REO_ENTRANCE_RING_RESERVED_10A_MASK                                         0xff000000
+
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET                                   0x0000002c
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB                                      0
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB                                      15
+#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK                                     0x0000ffff
+
+#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET                                       0x0000002c
+#define REO_ENTRANCE_RING_RESERVED_15A_LSB                                          16
+#define REO_ENTRANCE_RING_RESERVED_15A_MSB                                          19
+#define REO_ENTRANCE_RING_RESERVED_15A_MASK                                         0x000f0000
+
+#define REO_ENTRANCE_RING_RING_ID_OFFSET                                            0x0000002c
+#define REO_ENTRANCE_RING_RING_ID_LSB                                               20
+#define REO_ENTRANCE_RING_RING_ID_MSB                                               27
+#define REO_ENTRANCE_RING_RING_ID_MASK                                              0x0ff00000
+
+#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET                                      0x0000002c
+#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB                                         28
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB                                         31
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK                                        0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/response_end_status.h b/hw/wcn8750/v1/response_end_status.h
new file mode 100644
index 000000000000..20f72c890ffe
--- /dev/null
+++ b/hw/wcn8750/v1/response_end_status.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_END_STATUS_H_
+#define _RESPONSE_END_STATUS_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
+
+#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5
+
+struct response_end_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0072                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      response_transmit_status                                :  4,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      generated_response                                      :  3,
+                      mba_user_count                                          :  7,
+                      mba_fake_bitmap_count                                   :  7,
+                      coex_based_tx_bw                                        :  3,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0086                                                 :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8;
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      reserved_2b                                             : 10,
+                      only_null_delim_sent                                    :  1,
+                      brp_info_valid                                          :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0051                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0030                                       :  1;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t mu_response_bitmap_36_32                                :  5,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mic_overwritten                                         :  1,
+                      trig_resp_cmd_found                                     :  1,
+                      reserved_4a                                             : 21;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      __reserved_g_0005                                                 :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      reserved_20a                                            : 13;
+#else
+             uint32_t __reserved_g_0086                                                 :  1,
+                      trig_response_related                                   :  1,
+                      coex_based_tx_bw                                        :  3,
+                      mba_fake_bitmap_count                                   :  7,
+                      mba_user_count                                          :  7,
+                      generated_response                                      :  3,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      response_transmit_status                                :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0072                                       :  1;
+             uint32_t cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t __reserved_g_0030                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0051                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0067                                       :  1,
+                      brp_info_valid                                          :  1,
+                      only_null_delim_sent                                    :  1,
+                      reserved_2b                                             : 10,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t reserved_4a                                             : 21,
+                      trig_resp_cmd_found                                     :  1,
+                      mic_overwritten                                         :  1,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mu_response_bitmap_36_32                                :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t reserved_20a                                            : 13,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      addr3_47_32                                             : 16;
+#endif
+};
+
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                      0x0000000000000008
+
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB                            4
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB                            7
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK                           0x00000000000000f0
+
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK                           0x0000000000000100
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000000000200
+
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET                               0x0000000000000000
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB                                  10
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB                                  12
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK                                 0x0000000000001c00
+
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET                                   0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB                                      13
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB                                      19
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK                                     0x00000000000fe000
+
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB                               20
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB                               26
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK                              0x0000000007f00000
+
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET                                 0x0000000000000000
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB                                    27
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB                                    29
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK                                   0x0000000038000000
+
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK                              0x0000000040000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET     0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB        40
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB        45
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK       0x00003f0000000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET        0x0000000000000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB           46
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB           47
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK          0x0000c00000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET                         0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB                            48
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB                            55
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK                           0x00ff000000000000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET                            0x0000000000000000
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB                               56
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB                               63
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK                              0xff00000000000000
+
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB                                0
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB                                8
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK                               0x00000000000001ff
+
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET                           0x0000000000000008
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB                              9
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB                              10
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK                             0x0000000000000600
+
+#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET                                      0x0000000000000008
+#define RESPONSE_END_STATUS_RESERVED_2B_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_2B_MSB                                         20
+#define RESPONSE_END_STATUS_RESERVED_2B_MASK                                        0x00000000001ff800
+
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET                             0x0000000000000008
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK                               0x0000000000200000
+
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET                                   0x0000000000000008
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK                                     0x0000000000400000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET                          0x0000000000000008
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB                             32
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB                             63
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK                            0xffffffff00000000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET                         0x0000000000000010
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB                            0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB                            4
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK                           0x000000000000001f
+
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET               0x0000000000000010
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB                  5
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB                  8
+#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK                 0x00000000000001e0
+
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET                                  0x0000000000000010
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB                                     9
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB                                     9
+#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK                                    0x0000000000000200
+
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET                              0x0000000000000010
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB                                 10
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB                                 10
+#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK                                0x0000000000000400
+
+#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET                                      0x0000000000000010
+#define RESPONSE_END_STATUS_RESERVED_4A_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_4A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_4A_MASK                                        0x00000000fffff800
+
+#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET                                       0x0000000000000010
+#define RESPONSE_END_STATUS_ADDR1_31_0_LSB                                          32
+#define RESPONSE_END_STATUS_ADDR1_31_0_MSB                                          63
+#define RESPONSE_END_STATUS_ADDR1_31_0_MASK                                         0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR1_47_32_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR1_47_32_MSB                                         15
+#define RESPONSE_END_STATUS_ADDR1_47_32_MASK                                        0x000000000000ffff
+
+#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET                                       0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_15_0_LSB                                          16
+#define RESPONSE_END_STATUS_ADDR2_15_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR2_15_0_MASK                                         0x00000000ffff0000
+
+#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET                                      0x0000000000000018
+#define RESPONSE_END_STATUS_ADDR2_47_16_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR2_47_16_MSB                                         63
+#define RESPONSE_END_STATUS_ADDR2_47_16_MASK                                        0xffffffff00000000
+
+#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET                                       0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_31_0_LSB                                          0
+#define RESPONSE_END_STATUS_ADDR3_31_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR3_31_0_MASK                                         0x00000000ffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET                                      0x0000000000000020
+#define RESPONSE_END_STATUS_ADDR3_47_32_LSB                                         32
+#define RESPONSE_END_STATUS_ADDR3_47_32_MSB                                         47
+#define RESPONSE_END_STATUS_ADDR3_47_32_MASK                                        0x0000ffff00000000
+
+#define RESPONSE_END_STATUS_SECURE_OFFSET                                           0x0000000000000020
+#define RESPONSE_END_STATUS_SECURE_LSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MSB                                              49
+#define RESPONSE_END_STATUS_SECURE_MASK                                             0x0002000000000000
+
+#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET                                     0x0000000000000020
+#define RESPONSE_END_STATUS_RESERVED_20A_LSB                                        51
+#define RESPONSE_END_STATUS_RESERVED_20A_MSB                                        63
+#define RESPONSE_END_STATUS_RESERVED_20A_MASK                                       0xfff8000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/response_start_status.h b/hw/wcn8750/v1/response_start_status.h
new file mode 100644
index 000000000000..0a3090f219fe
--- /dev/null
+++ b/hw/wcn8750/v1/response_start_status.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RESPONSE_START_STATUS_H_
+#define _RESPONSE_START_STATUS_H_
+
+#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
+
+#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
+
+struct response_start_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t generated_response                                      :  3,
+                      __reserved_g_0012                                                  :  2,
+                      trig_response_related                                   :  1,
+                      response_sta_count                                      :  7,
+                      mba_for_cfp_ba                                          :  1,
+                      mba_for_cfp_ack                                         :  1,
+                      ects_response_type                                      :  2,
+                      eba_response_type                                       :  2,
+                      cfp_mba                                                 :  1,
+                      mba_for_ll_ack                                          :  1,
+                      mba_for_ll_ba                                           :  1,
+                      reserved                                                : 10;
+             uint32_t phy_ppdu_id                                             : 16,
+                      sw_peer_id                                              : 16;
+#else
+             uint32_t reserved                                                : 10,
+                      mba_for_ll_ba                                           :  1,
+                      mba_for_ll_ack                                          :  1,
+                      cfp_mba                                                 :  1,
+                      eba_response_type                                       :  2,
+                      ects_response_type                                      :  2,
+                      mba_for_cfp_ack                                         :  1,
+                      mba_for_cfp_ba                                          :  1,
+                      response_sta_count                                      :  7,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0012                                                  :  2,
+                      generated_response                                      :  3;
+             uint32_t sw_peer_id                                              : 16,
+                      phy_ppdu_id                                             : 16;
+#endif
+};
+
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB                                0
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB                                2
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK                               0x0000000000000007
+
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET                          0x0000000000000000
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK                            0x0000000000000020
+
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB                                6
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB                                12
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK                               0x0000000000001fc0
+
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET                                 0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB                                    13
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB                                    13
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK                                   0x0000000000002000
+
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET                                0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB                                   14
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB                                   14
+#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK                                  0x0000000000004000
+
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET                             0x0000000000000000
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB                                15
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB                                16
+#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK                               0x0000000000018000
+
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET                              0x0000000000000000
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB                                 17
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB                                 18
+#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK                                0x0000000000060000
+
+#define RESPONSE_START_STATUS_CFP_MBA_OFFSET                                        0x0000000000000000
+#define RESPONSE_START_STATUS_CFP_MBA_LSB                                           19
+#define RESPONSE_START_STATUS_CFP_MBA_MSB                                           19
+#define RESPONSE_START_STATUS_CFP_MBA_MASK                                          0x0000000000080000
+
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET                                 0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB                                    20
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB                                    20
+#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK                                   0x0000000000100000
+
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET                                  0x0000000000000000
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB                                     21
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB                                     21
+#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK                                    0x0000000000200000
+
+#define RESPONSE_START_STATUS_RESERVED_OFFSET                                       0x0000000000000000
+#define RESPONSE_START_STATUS_RESERVED_LSB                                          22
+#define RESPONSE_START_STATUS_RESERVED_MSB                                          31
+#define RESPONSE_START_STATUS_RESERVED_MASK                                         0x00000000ffc00000
+
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET                                    0x0000000000000000
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB                                       32
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB                                       47
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK                                      0x0000ffff00000000
+
+#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET                                     0x0000000000000000
+#define RESPONSE_START_STATUS_SW_PEER_ID_LSB                                        48
+#define RESPONSE_START_STATUS_SW_PEER_ID_MSB                                        63
+#define RESPONSE_START_STATUS_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/ru_allocation_160_info.h b/hw/wcn8750/v1/ru_allocation_160_info.h
new file mode 100644
index 000000000000..57d51dc44f8a
--- /dev/null
+++ b/hw/wcn8750/v1/ru_allocation_160_info.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation_band0_0                                   :  9,
+                      ru_allocation_band0_1                                   :  9,
+                      reserved_0a                                             :  6,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      ru_allocations_23_subband80_mask                        :  4;
+             uint32_t ru_allocation_band0_2                                   :  9,
+                      ru_allocation_band0_3                                   :  9,
+                      reserved_1a                                             : 14;
+             uint32_t ru_allocation_band1_0                                   :  9,
+                      ru_allocation_band1_1                                   :  9,
+                      reserved_2a                                             : 14;
+             uint32_t ru_allocation_band1_2                                   :  9,
+                      ru_allocation_band1_3                                   :  9,
+                      reserved_3a                                             : 14;
+#else
+             uint32_t ru_allocations_23_subband80_mask                        :  4,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      reserved_0a                                             :  6,
+                      ru_allocation_band0_1                                   :  9,
+                      ru_allocation_band0_0                                   :  9;
+             uint32_t reserved_1a                                             : 14,
+                      ru_allocation_band0_3                                   :  9,
+                      ru_allocation_band0_2                                   :  9;
+             uint32_t reserved_2a                                             : 14,
+                      ru_allocation_band1_1                                   :  9,
+                      ru_allocation_band1_0                                   :  9;
+             uint32_t reserved_3a                                             : 14,
+                      ru_allocation_band1_3                                   :  9,
+                      ru_allocation_band1_2                                   :  9;
+#endif
+};
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_attention.h b/hw/wcn8750/v1/rx_attention.h
new file mode 100644
index 000000000000..cac7c2fb52c3
--- /dev/null
+++ b/hw/wcn8750/v1/rx_attention.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+
+#define NUM_OF_DWORDS_RX_ATTENTION 4
+
+#define NUM_OF_QWORDS_RX_ATTENTION 2
+
+struct rx_attention {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_1a                                             :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      cce_match                                               :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      reserved_1b                                             :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      wifi_parser_error                                       :  1,
+                      amsdu_parser_error                                      :  1,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      msdu_limit_error                                        :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      sa_is_valid                                             :  1,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_2                                              : 17,
+                      msdu_done                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      reserved_1b                                             :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      cce_match                                               :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_1a                                             :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_2                                              : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      sa_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      msdu_limit_error                                        :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      amsdu_parser_error                                      :  1,
+                      wifi_parser_error                                       :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000000000000000
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x0000000000000003
+
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK                                         0x00000000000001fc
+
+#define RX_ATTENTION_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_RESERVED_0_LSB                                                 9
+#define RX_ATTENTION_RESERVED_0_MSB                                                 15
+#define RX_ATTENTION_RESERVED_0_MASK                                                0x000000000000fe00
+
+#define RX_ATTENTION_PHY_PPDU_ID_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_PHY_PPDU_ID_LSB                                                16
+#define RX_ATTENTION_PHY_PPDU_ID_MSB                                                31
+#define RX_ATTENTION_PHY_PPDU_ID_MASK                                               0x00000000ffff0000
+
+#define RX_ATTENTION_FIRST_MPDU_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_FIRST_MPDU_LSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MSB                                                 32
+#define RX_ATTENTION_FIRST_MPDU_MASK                                                0x0000000100000000
+
+#define RX_ATTENTION_RESERVED_1A_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1A_LSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MSB                                                33
+#define RX_ATTENTION_RESERVED_1A_MASK                                               0x0000000200000000
+
+#define RX_ATTENTION_MCAST_BCAST_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_MCAST_BCAST_LSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MSB                                                34
+#define RX_ATTENTION_MCAST_BCAST_MASK                                               0x0000000400000000
+
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB                                        35
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK                                       0x0000000800000000
+
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET                                       0x0000000000000000
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB                                          36
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK                                         0x0000001000000000
+
+#define RX_ATTENTION_POWER_MGMT_OFFSET                                              0x0000000000000000
+#define RX_ATTENTION_POWER_MGMT_LSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MSB                                                 37
+#define RX_ATTENTION_POWER_MGMT_MASK                                                0x0000002000000000
+
+#define RX_ATTENTION_NON_QOS_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_NON_QOS_LSB                                                    38
+#define RX_ATTENTION_NON_QOS_MSB                                                    38
+#define RX_ATTENTION_NON_QOS_MASK                                                   0x0000004000000000
+
+#define RX_ATTENTION_NULL_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_NULL_DATA_LSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MSB                                                  39
+#define RX_ATTENTION_NULL_DATA_MASK                                                 0x0000008000000000
+
+#define RX_ATTENTION_MGMT_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MGMT_TYPE_LSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MSB                                                  40
+#define RX_ATTENTION_MGMT_TYPE_MASK                                                 0x0000010000000000
+
+#define RX_ATTENTION_CTRL_TYPE_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CTRL_TYPE_LSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MSB                                                  41
+#define RX_ATTENTION_CTRL_TYPE_MASK                                                 0x0000020000000000
+
+#define RX_ATTENTION_MORE_DATA_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_MORE_DATA_LSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MSB                                                  42
+#define RX_ATTENTION_MORE_DATA_MASK                                                 0x0000040000000000
+
+#define RX_ATTENTION_EOSP_OFFSET                                                    0x0000000000000000
+#define RX_ATTENTION_EOSP_LSB                                                       43
+#define RX_ATTENTION_EOSP_MSB                                                       43
+#define RX_ATTENTION_EOSP_MASK                                                      0x0000080000000000
+
+#define RX_ATTENTION_A_MSDU_ERROR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_A_MSDU_ERROR_LSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MSB                                               44
+#define RX_ATTENTION_A_MSDU_ERROR_MASK                                              0x0000100000000000
+
+#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET                                           0x0000000000000000
+#define RX_ATTENTION_FRAGMENT_FLAG_LSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MSB                                              45
+#define RX_ATTENTION_FRAGMENT_FLAG_MASK                                             0x0000200000000000
+
+#define RX_ATTENTION_ORDER_OFFSET                                                   0x0000000000000000
+#define RX_ATTENTION_ORDER_LSB                                                      46
+#define RX_ATTENTION_ORDER_MSB                                                      46
+#define RX_ATTENTION_ORDER_MASK                                                     0x0000400000000000
+
+#define RX_ATTENTION_CCE_MATCH_OFFSET                                               0x0000000000000000
+#define RX_ATTENTION_CCE_MATCH_LSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MSB                                                  47
+#define RX_ATTENTION_CCE_MATCH_MASK                                                 0x0000800000000000
+
+#define RX_ATTENTION_OVERFLOW_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_OVERFLOW_ERR_LSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MSB                                               48
+#define RX_ATTENTION_OVERFLOW_ERR_MASK                                              0x0001000000000000
+
+#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB                                            49
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK                                           0x0002000000000000
+
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET                                     0x0000000000000000
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB                                        50
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK                                       0x0004000000000000
+
+#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB                                             51
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK                                            0x0008000000000000
+
+#define RX_ATTENTION_SA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_SA_IDX_INVALID_LSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MSB                                             52
+#define RX_ATTENTION_SA_IDX_INVALID_MASK                                            0x0010000000000000
+
+#define RX_ATTENTION_DA_IDX_INVALID_OFFSET                                          0x0000000000000000
+#define RX_ATTENTION_DA_IDX_INVALID_LSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MSB                                             53
+#define RX_ATTENTION_DA_IDX_INVALID_MASK                                            0x0020000000000000
+
+#define RX_ATTENTION_RESERVED_1B_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_RESERVED_1B_LSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MSB                                                54
+#define RX_ATTENTION_RESERVED_1B_MASK                                               0x0040000000000000
+
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET                                    0x0000000000000000
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB                                       55
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK                                      0x0080000000000000
+
+#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET                                        0x0000000000000000
+#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB                                           56
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK                                          0x0100000000000000
+
+#define RX_ATTENTION_DIRECTED_OFFSET                                                0x0000000000000000
+#define RX_ATTENTION_DIRECTED_LSB                                                   57
+#define RX_ATTENTION_DIRECTED_MSB                                                   57
+#define RX_ATTENTION_DIRECTED_MASK                                                  0x0200000000000000
+
+#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_BUFFER_FRAGMENT_LSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MSB                                            58
+#define RX_ATTENTION_BUFFER_FRAGMENT_MASK                                           0x0400000000000000
+
+#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET                                         0x0000000000000000
+#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB                                            59
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK                                           0x0800000000000000
+
+#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET                                            0x0000000000000000
+#define RX_ATTENTION_TKIP_MIC_ERR_LSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MSB                                               60
+#define RX_ATTENTION_TKIP_MIC_ERR_MASK                                              0x1000000000000000
+
+#define RX_ATTENTION_DECRYPT_ERR_OFFSET                                             0x0000000000000000
+#define RX_ATTENTION_DECRYPT_ERR_LSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MSB                                                61
+#define RX_ATTENTION_DECRYPT_ERR_MASK                                               0x2000000000000000
+
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET                                   0x0000000000000000
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB                                      62
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK                                     0x4000000000000000
+
+#define RX_ATTENTION_FCS_ERR_OFFSET                                                 0x0000000000000000
+#define RX_ATTENTION_FCS_ERR_LSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MSB                                                    63
+#define RX_ATTENTION_FCS_ERR_MASK                                                   0x8000000000000000
+
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK                                          0x0000000000000001
+
+#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_FLOW_IDX_INVALID_LSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MASK                                          0x0000000000000002
+
+#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET                                       0x0000000000000008
+#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK                                         0x0000000000000004
+
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET                                      0x0000000000000008
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK                                        0x0000000000000008
+
+#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK                                            0x0000000000000010
+
+#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET                                          0x0000000000000008
+#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK                                            0x0000000000000020
+
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET                                        0x0000000000000008
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK                                          0x0000000000000040
+
+#define RX_ATTENTION_DA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_DA_IS_VALID_LSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MASK                                               0x0000000000000080
+
+#define RX_ATTENTION_DA_IS_MCBC_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_DA_IS_MCBC_LSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MASK                                                0x0000000000000100
+
+#define RX_ATTENTION_SA_IS_VALID_OFFSET                                             0x0000000000000008
+#define RX_ATTENTION_SA_IS_VALID_LSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MASK                                               0x0000000000000200
+
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET                                     0x0000000000000008
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB                                        10
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB                                        12
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK                                       0x0000000000001c00
+
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET                                   0x0000000000000008
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK                                     0x0000000000002000
+
+#define RX_ATTENTION_RESERVED_2_OFFSET                                              0x0000000000000008
+#define RX_ATTENTION_RESERVED_2_LSB                                                 14
+#define RX_ATTENTION_RESERVED_2_MSB                                                 30
+#define RX_ATTENTION_RESERVED_2_MASK                                                0x000000007fffc000
+
+#define RX_ATTENTION_MSDU_DONE_OFFSET                                               0x0000000000000008
+#define RX_ATTENTION_MSDU_DONE_LSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MASK                                                 0x0000000080000000
+
+#define RX_ATTENTION_TLV64_PADDING_OFFSET                                           0x0000000000000008
+#define RX_ATTENTION_TLV64_PADDING_LSB                                              32
+#define RX_ATTENTION_TLV64_PADDING_MSB                                              63
+#define RX_ATTENTION_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_flow_search_entry.h b/hw/wcn8750/v1/rx_flow_search_entry.h
new file mode 100644
index 000000000000..25f1f81c439f
--- /dev/null
+++ b/hw/wcn8750/v1/rx_flow_search_entry.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t src_port                                                : 16,
+                      dest_port                                               : 16;
+             uint32_t l4_protocol                                             :  8,
+                      valid                                                   :  1,
+                      reserved_9                                              :  4,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      use_ppe                                                 :  1,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1,
+                      reo_destination_handler                                 :  2;
+             uint32_t metadata                                                : 32;
+             uint32_t aggregation_count                                       :  7,
+                      lro_eligible                                            :  1,
+                      msdu_count                                              : 24;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length_pmac1                              : 16,
+                      cumulative_ip_length                                    : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#else
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t dest_port                                               : 16,
+                      src_port                                                : 16;
+             uint32_t reo_destination_handler                                 :  2,
+                      msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      use_ppe                                                 :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_9                                              :  4,
+                      valid                                                   :  1,
+                      l4_protocol                                             :  8;
+             uint32_t metadata                                                : 32;
+             uint32_t msdu_count                                              : 24,
+                      lro_eligible                                            :  1,
+                      aggregation_count                                       :  7;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length                                    : 16,
+                      cumulative_ip_length_pmac1                              : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#endif
+};
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET                                   0x00000000
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET                                    0x00000004
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET                                    0x00000008
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET                                     0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB                                        31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK                                       0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET                                  0x00000010
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB                                     0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB                                     31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK                                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET                                   0x00000014
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET                                   0x00000018
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET                                    0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET                                        0x00000020
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB                                           15
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK                                          0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET                                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB                                          16
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK                                         0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET                                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB                                        7
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK                                       0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET                                           0x00000024
+#define RX_FLOW_SEARCH_ENTRY_VALID_LSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MASK                                             0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET                                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB                                         9
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB                                         12
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK                                        0x00001e00
+
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET                                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB                                       13
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB                                       21
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK                                      0x003fe000
+
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET                                  0x00000024
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK                                    0x00400000
+
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET                                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK                                           0x00800000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB                         24
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB                         28
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK                        0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET                                       0x00000024
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK                                         0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB                            30
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB                            31
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK                           0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET                                        0x00000028
+#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB                                           31
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK                                          0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET                               0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB                                  0
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB                                  6
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK                                 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET                                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK                                      0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET                                      0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB                                         8
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB                                         31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK                                        0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET                                 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB                                    0
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB                                    31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK                                   0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET                                       0x00000034
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB                                          0
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK                                         0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET                      0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB                         15
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK                        0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET                            0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB                               16
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB                               31
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK                              0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET                             0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB                                0
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB                                31
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK                               0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h b/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
new file mode 100644
index 000000000000..a43548b14a07
--- /dev/null
+++ b/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
+#define _RX_FRAME_1K_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38
+
+#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19
+
+struct rx_frame_1k_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  5,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0b                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0c                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      reserved_1a                                             : 20;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#else
+             uint32_t reserved_0c                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0b                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0a                                             :  5;
+             uint32_t reserved_1a                                             : 20,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#endif
+};
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB                                      4
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK                                     0x000000000000001f
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                   5
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                   6
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                  0x0000000000000060
+
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                             7
+#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                            0x0000000000000080
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB                                      8
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB                                      9
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK                                     0x0000000000000300
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET                                        0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB                                           10
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB                                           13
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK                                          0x0000000000003c00
+
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB                                     14
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB                                     26
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK                                    0x0000000007ffc000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB                                      27
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK                                     0x00000000f8000000
+
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB                                       41
+#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK                                      0x000003ff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                          0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                             42
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                            0x0000040000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                           0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                              43
+#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                             0x0000080000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB                                      44
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB                                      63
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK                                     0xfffff00000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB                                       0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB                                       31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK                                      0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET                                   0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB                                      32
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB                                      47
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK                                     0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET                                    0x0000000000000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB                                       48
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB                                       63
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK                                      0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET                                   0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK                                     0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET                                    0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB                                       32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB                                       47
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK                                      0x0000ffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET                                     0x0000000000000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB                                        48
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB                                        63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK                                       0xffff000000000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                             0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                            0x0000000000000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                               32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                               63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                              0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                            0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                               0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                               31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                              0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                           0x0000000000000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                              32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                              63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                             0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                          0x0000000000000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                          0x0000000000000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET                          0x0000000000000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET                          0x0000000000000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET                          0x0000000000000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET                          0x0000000000000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET                          0x0000000000000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET                          0x0000000000000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET                          0x0000000000000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET                          0x0000000000000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET                          0x0000000000000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET                          0x0000000000000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET                          0x0000000000000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB                             32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB                             63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK                            0xffffffff00000000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET                          0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK                            0x00000000ffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET                         0x0000000000000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB                            32
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB                            63
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK                           0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_frame_bitmap_ack.h b/hw/wcn8750/v1/rx_frame_bitmap_ack.h
new file mode 100644
index 000000000000..0b68486b038e
--- /dev/null
+++ b/hw/wcn8750/v1/rx_frame_bitmap_ack.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_ACK_H_
+#define _RX_FRAME_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7
+
+struct rx_frame_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_bitmap_available                                     :  1,
+                      explicit_ack                                            :  1,
+                      explict_ack_type                                        :  3,
+                      ba_bitmap_size                                          :  2,
+                      gen_mlo_notification                                    :  1,
+                      reserved_0a                                             :  2,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0b                                             :  5;
+             uint32_t mlo_sta_id                                              : 10,
+                      ba_size_1024_allowed                                    :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_32_allowed                                      :  1,
+                      reserved_1a                                             : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#else
+             uint32_t reserved_0b                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0a                                             :  2,
+                      gen_mlo_notification                                    :  1,
+                      ba_bitmap_size                                          :  2,
+                      explict_ack_type                                        :  3,
+                      explicit_ack                                            :  1,
+                      no_bitmap_available                                     :  1;
+             uint32_t reserved_1a                                             : 16,
+                      ba_size_32_allowed                                      :  1,
+                      ba_size_64_allowed                                      :  1,
+                      ba_size_128_allowed                                     :  1,
+                      ba_size_256_allowed                                     :  1,
+                      ba_size_512_allowed                                     :  1,
+                      ba_size_1024_allowed                                    :  1,
+                      mlo_sta_id                                              : 10;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK                                0x0000000000000001
+
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK                                       0x0000000000000002
+
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET                                 0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB                                    2
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB                                    4
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK                                   0x000000000000001c
+
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                   0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                      5
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                      6
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                     0x0000000000000060
+
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB                                7
+#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK                               0x0000000000000080
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB                                         8
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB                                         9
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK                                        0x0000000000000300
+
+#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET                                           0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_TID_LSB                                              10
+#define RX_FRAME_BITMAP_ACK_BA_TID_MSB                                              13
+#define RX_FRAME_BITMAP_ACK_BA_TID_MASK                                             0x0000000000003c00
+
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET                                     0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB                                        14
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB                                        26
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK                                       0x0000000007ffc000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB                                         27
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK                                        0x00000000f8000000
+
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB                                          41
+#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK                                         0x000003ff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB                                42
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK                               0x0000040000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB                                 43
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK                                0x0000080000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB                                 44
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK                                0x0000100000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET                              0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB                                 45
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK                                0x0000200000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB                                  46
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK                                 0x0000400000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET                               0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB                                  47
+#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK                                 0x0000800000000000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB                                         48
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB                                         63
+#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB                                          0
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB                                          31
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK                                         0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET                                      0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB                                         32
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB                                         47
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK                                        0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET                                       0x0000000000000008
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB                                          48
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB                                          63
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK                                         0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET                                      0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB                                         0
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK                                        0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET                                       0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB                                          32
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB                                          47
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK                                         0x0000ffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET                                        0x0000000000000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB                                           48
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB                                           63
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK                                          0xffff000000000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                                0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                   0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                   31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                               0x0000000000000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                                  32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                                  63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                                 0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                               0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                                  0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                                  31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                                 0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                              0x0000000000000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                                 32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                                 63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                                0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                             0x0000000000000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                               0xffffffff00000000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                               0x00000000ffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                             0x0000000000000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                                32
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                                63
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                               0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_frame_bitmap_req.h b/hw/wcn8750/v1/rx_frame_bitmap_req.h
new file mode 100644
index 000000000000..24f8ddd1c57c
--- /dev/null
+++ b/hw/wcn8750/v1/rx_frame_bitmap_req.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_FRAME_BITMAP_REQ_H_
+#define _RX_FRAME_BITMAP_REQ_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2
+
+#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1
+
+struct rx_frame_bitmap_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t explicit_user_request                                   :  1,
+                      user_request_type                                       :  1,
+                      user_number                                             :  6,
+                      sw_peer_id                                              : 16,
+                      tid_specific_request                                    :  1,
+                      requested_tid                                           :  4,
+                      reserved_0                                              :  3;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0                                              :  3,
+                      requested_tid                                           :  4,
+                      tid_specific_request                                    :  1,
+                      sw_peer_id                                              : 16,
+                      user_number                                             :  6,
+                      user_request_type                                       :  1,
+                      explicit_user_request                                   :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET                            0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK                              0x0000000000000001
+
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET                                0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK                                  0x0000000000000002
+
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET                                      0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB                                         2
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB                                         7
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK                                        0x00000000000000fc
+
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB                                          8
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB                                          23
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK                                         0x0000000000ffff00
+
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET                             0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK                               0x0000000001000000
+
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB                                       25
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB                                       28
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK                                      0x000000001e000000
+
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET                                       0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB                                          29
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB                                          31
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK                                         0x00000000e0000000
+
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET                                    0x0000000000000000
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB                                       32
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB                                       63
+#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK                                      0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_location_info.h b/hw/wcn8750/v1/rx_location_info.h
new file mode 100644
index 000000000000..cfd6a734f511
--- /dev/null
+++ b/hw/wcn8750/v1/rx_location_info.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
+
+struct rx_location_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_location_info_valid                                  :  1,
+                      rtt_hw_ifft_mode                                        :  1,
+                      __reserved_g_0083                                           :  2,
+                      reserved_0                                              :  4,
+                      rtt_num_fac                                             :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_streams                                         :  8;
+             uint32_t rtt_first_selected_chain                                :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_cir_status                                          :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_che_buffer_pointer_high8                            :  8,
+                      reserved_3                                              :  8,
+                      rtt_pkt_bw_vht                                          :  4,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_mcs_rate                                            :  8;
+             uint32_t rtt_cfo_measurement                                     : 16,
+                      rtt_preamble_type                                       :  8,
+                      rtt_gi_type                                             :  8;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain0                                             : 16,
+                      gain_chain1                                             : 16;
+             uint32_t gain_chain2                                             : 16,
+                      gain_chain3                                             : 16;
+             uint32_t gain_report_status                                      :  8,
+                      rtt_timing_backoff_sel                                  :  8,
+                      rtt_fac_combined                                        : 16;
+             uint32_t rtt_fac_0                                               : 16,
+                      rtt_fac_1                                               : 16;
+             uint32_t rtt_fac_2                                               : 16,
+                      rtt_fac_3                                               : 16;
+             uint32_t rtt_fac_4                                               : 16,
+                      rtt_fac_5                                               : 16;
+             uint32_t rtt_fac_6                                               : 16,
+                      rtt_fac_7                                               : 16;
+             uint32_t rtt_fac_8                                               : 16,
+                      rtt_fac_9                                               : 16;
+             uint32_t rtt_fac_10                                              : 16,
+                      rtt_fac_11                                              : 16;
+             uint32_t rtt_fac_12                                              : 16,
+                      rtt_fac_13                                              : 16;
+             uint32_t rtt_fac_14                                              : 16,
+                      rtt_fac_15                                              : 16;
+             uint32_t rtt_fac_16                                              : 16,
+                      rtt_fac_17                                              : 16;
+             uint32_t rtt_fac_18                                              : 16,
+                      rtt_fac_19                                              : 16;
+             uint32_t rtt_fac_20                                              : 16,
+                      rtt_fac_21                                              : 16;
+             uint32_t rtt_fac_22                                              : 16,
+                      rtt_fac_23                                              : 16;
+             uint32_t rtt_fac_24                                              : 16,
+                      rtt_fac_25                                              : 16;
+             uint32_t rtt_fac_26                                              : 16,
+                      rtt_fac_27                                              : 16;
+             uint32_t rtt_fac_28                                              : 16,
+                      rtt_fac_29                                              : 16;
+             uint32_t rtt_fac_30                                              : 16,
+                      rtt_fac_31                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#else
+             uint32_t rtt_num_streams                                         :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_fac                                             :  8,
+                      reserved_0                                              :  4,
+                      __reserved_g_0083                                           :  2,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rx_location_info_valid                                  :  1;
+             uint32_t rtt_cir_status                                          :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_first_selected_chain                                :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_mcs_rate                                            :  8,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_pkt_bw_vht                                          :  4,
+                      reserved_3                                              :  8,
+                      rtt_che_buffer_pointer_high8                            :  8;
+             uint32_t rtt_gi_type                                             :  8,
+                      rtt_preamble_type                                       :  8,
+                      rtt_cfo_measurement                                     : 16;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain1                                             : 16,
+                      gain_chain0                                             : 16;
+             uint32_t gain_chain3                                             : 16,
+                      gain_chain2                                             : 16;
+             uint32_t rtt_fac_combined                                        : 16,
+                      rtt_timing_backoff_sel                                  :  8,
+                      gain_report_status                                      :  8;
+             uint32_t rtt_fac_1                                               : 16,
+                      rtt_fac_0                                               : 16;
+             uint32_t rtt_fac_3                                               : 16,
+                      rtt_fac_2                                               : 16;
+             uint32_t rtt_fac_5                                               : 16,
+                      rtt_fac_4                                               : 16;
+             uint32_t rtt_fac_7                                               : 16,
+                      rtt_fac_6                                               : 16;
+             uint32_t rtt_fac_9                                               : 16,
+                      rtt_fac_8                                               : 16;
+             uint32_t rtt_fac_11                                              : 16,
+                      rtt_fac_10                                              : 16;
+             uint32_t rtt_fac_13                                              : 16,
+                      rtt_fac_12                                              : 16;
+             uint32_t rtt_fac_15                                              : 16,
+                      rtt_fac_14                                              : 16;
+             uint32_t rtt_fac_17                                              : 16,
+                      rtt_fac_16                                              : 16;
+             uint32_t rtt_fac_19                                              : 16,
+                      rtt_fac_18                                              : 16;
+             uint32_t rtt_fac_21                                              : 16,
+                      rtt_fac_20                                              : 16;
+             uint32_t rtt_fac_23                                              : 16,
+                      rtt_fac_22                                              : 16;
+             uint32_t rtt_fac_25                                              : 16,
+                      rtt_fac_24                                              : 16;
+             uint32_t rtt_fac_27                                              : 16,
+                      rtt_fac_26                                              : 16;
+             uint32_t rtt_fac_29                                              : 16,
+                      rtt_fac_28                                              : 16;
+             uint32_t rtt_fac_31                                              : 16,
+                      rtt_fac_30                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#endif
+};
+
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET                              0x00000000
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK                                0x00000001
+
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET                                    0x00000000
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK                                      0x00000002
+
+#define RX_LOCATION_INFO_RESERVED_0_OFFSET                                          0x00000000
+#define RX_LOCATION_INFO_RESERVED_0_LSB                                             4
+#define RX_LOCATION_INFO_RESERVED_0_MSB                                             7
+#define RX_LOCATION_INFO_RESERVED_0_MASK                                            0x000000f0
+
+#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET                                         0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB                                            8
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB                                            15
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK                                           0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET                                   0x00000000
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB                                      16
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB                                      23
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET                                     0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB                                        24
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB                                        31
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK                                       0xff000000
+
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET                            0x00000004
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB                               0
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB                               7
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK                              0x000000ff
+
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET                           0x00000004
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB                              8
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB                              15
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK                             0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB                                         16
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB                                         23
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK                                        0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB                                         24
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB                                         31
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK                                        0xff000000
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET                        0x00000008
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB                           31
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK                          0xffffffff
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET                        0x0000000c
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB                           7
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK                          0x000000ff
+
+#define RX_LOCATION_INFO_RESERVED_3_OFFSET                                          0x0000000c
+#define RX_LOCATION_INFO_RESERVED_3_LSB                                             8
+#define RX_LOCATION_INFO_RESERVED_3_MSB                                             15
+#define RX_LOCATION_INFO_RESERVED_3_MASK                                            0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB                                         16
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB                                         19
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK                                        0x000f0000
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB                                         20
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB                                         23
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK                                        0x00f00000
+
+#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET                                        0x0000000c
+#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB                                           24
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB                                           31
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK                                          0xff000000
+
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET                                 0x00000010
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB                                    0
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB                                    15
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK                                   0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET                                   0x00000010
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB                                      16
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB                                      23
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET                                         0x00000010
+#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB                                            24
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB                                            31
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK                                           0xff000000
+
+#define RX_LOCATION_INFO_RX_START_TS_OFFSET                                         0x00000014
+#define RX_LOCATION_INFO_RX_START_TS_LSB                                            0
+#define RX_LOCATION_INFO_RX_START_TS_MSB                                            31
+#define RX_LOCATION_INFO_RX_START_TS_MASK                                           0xffffffff
+
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET                                   0x00000018
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB                                      0
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB                                      31
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK                                     0xffffffff
+
+#define RX_LOCATION_INFO_RX_END_TS_OFFSET                                           0x0000001c
+#define RX_LOCATION_INFO_RX_END_TS_LSB                                              0
+#define RX_LOCATION_INFO_RX_END_TS_MSB                                              31
+#define RX_LOCATION_INFO_RX_END_TS_MASK                                             0xffffffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET                                  0x00000028
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB                                     0
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB                                     7
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK                                    0x000000ff
+
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET                              0x00000028
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB                                 8
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB                                 15
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK                                0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET                                    0x00000028
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB                                       16
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB                                       31
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK                                      0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_0_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_0_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_0_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_1_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_1_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_1_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_2_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_2_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_2_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_3_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_3_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_3_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_4_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_4_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_4_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_5_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_5_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_5_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_6_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_6_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_6_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_7_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_7_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_7_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_8_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_8_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_8_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_9_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_9_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_9_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_10_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_10_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_10_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_11_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_11_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_11_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_12_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_12_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_12_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_13_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_13_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_13_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_14_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_14_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_14_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_15_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_15_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_15_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_16_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_16_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_16_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_17_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_17_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_17_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_18_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_18_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_18_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_19_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_19_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_19_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_20_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_20_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_20_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_21_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_21_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_21_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_22_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_22_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_22_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_23_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_23_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_23_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_24_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_24_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_24_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_25_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_25_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_25_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_26_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_26_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_26_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_27_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_27_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_27_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_28_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_28_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_28_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_29_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_29_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_29_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_30_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_30_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_30_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_31_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_31_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_31_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RESERVED_27A_OFFSET                                        0x0000006c
+#define RX_LOCATION_INFO_RESERVED_27A_LSB                                           0
+#define RX_LOCATION_INFO_RESERVED_27A_MSB                                           31
+#define RX_LOCATION_INFO_RESERVED_27A_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_desc_info.h b/hw/wcn8750/v1/rx_mpdu_desc_info.h
new file mode 100644
index 000000000000..30f538fb1228
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_desc_info.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_count                                              :  8,
+                      fragment_flag                                           :  1,
+                      mpdu_retry_bit                                          :  1,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      raw_mpdu                                                :  1,
+                      more_fragment_flag                                      :  1,
+                      src_info                                                : 12,
+                      mpdu_qos_control_valid                                  :  1,
+                      tid                                                     :  4;
+             uint32_t peer_meta_data                                          : 32;
+#else
+             uint32_t tid                                                     :  4,
+                      mpdu_qos_control_valid                                  :  1,
+                      src_info                                                : 12,
+                      more_fragment_flag                                      :  1,
+                      raw_mpdu                                                :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      mpdu_retry_bit                                          :  1,
+                      fragment_flag                                           :  1,
+                      msdu_count                                              :  8;
+             uint32_t peer_meta_data                                          : 32;
+#endif
+};
+
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
+
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
+
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
+
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
+
+#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
+#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
+
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
+
+#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
+
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
+
+#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_SRC_INFO_LSB                                              15
+#define RX_MPDU_DESC_INFO_SRC_INFO_MSB                                              26
+#define RX_MPDU_DESC_INFO_SRC_INFO_MASK                                             0x07ff8000
+
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
+
+#define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
+#define RX_MPDU_DESC_INFO_TID_LSB                                                   28
+#define RX_MPDU_DESC_INFO_TID_MSB                                                   31
+#define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
+
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_details.h b/hw/wcn8750/v1/rx_mpdu_details.h
new file mode 100644
index 000000000000..d2d96a0a9996
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_details.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+
+#include "rx_mpdu_ext_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6
+
+struct rx_mpdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_mpdu_ext_desc_info                                     rx_mpdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB               0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB              0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB              7
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB               12
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                    0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                    7
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK                   0x000000ff
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET              0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK                0x00000100
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET             0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK               0x00000200
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK                   0x00000400
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET                  0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                    0x00000800
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                     0x00002000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET         0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK           0x00004000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                      15
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                      26
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                     0x07ff8000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET     0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK       0x08000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                        0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                           28
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                           31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                          0xf0000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET             0x0000000c
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB                0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB                31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK               0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET                0x00000010
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB                   0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB                   31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK                  0xffffffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET               0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB                  0
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB                  15
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK                 0x0000ffff
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET         0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB            16
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB            17
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK           0x00030000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET   0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB      18
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB      21
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK     0x003c0000
+
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET            0x00000014
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB               22
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB               31
+#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK              0xffc00000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_end.h b/hw/wcn8750/v1/rx_mpdu_end.h
new file mode 100644
index 000000000000..dc54ea129fdd
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_end.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_END 4
+
+#define NUM_OF_QWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_1a                                             :  9,
+                      cfp_mic_err                                             :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      overflow_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      fcs_err                                                 :  1,
+                      msdu_length_err                                         :  1,
+                      reserved1c                                              :  6,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      ifcs_present                                            :  1;
+             uint32_t mpdu_crc_ok_intermediate_fcs                            :  1,
+                      mpdu_length_intermediate_fcs                            : 14,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      rxpcu_mgmt_sequence_nr                                  : 16;
+             uint32_t __reserved_g_0002                                       : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t ifcs_present                                            :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved1c                                              :  6,
+                      msdu_length_err                                         :  1,
+                      fcs_err                                                 :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      cfp_mic_err                                             :  1,
+                      reserved_1a                                             :  9;
+             uint32_t rxpcu_mgmt_sequence_nr                                  : 16,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      mpdu_length_intermediate_fcs                            : 14,
+                      mpdu_crc_ok_intermediate_fcs                            :  1;
+             uint32_t __reserved_g_0002                                       : 32;
+#endif
+};
+
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MPDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED_0_LSB                                                  9
+#define RX_MPDU_END_RESERVED_0_MSB                                                  15
+#define RX_MPDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MPDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MPDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MPDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MPDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_RESERVED_1A_LSB                                                 32
+#define RX_MPDU_END_RESERVED_1A_MSB                                                 40
+#define RX_MPDU_END_RESERVED_1A_MASK                                                0x000001ff00000000
+
+#define RX_MPDU_END_CFP_MIC_ERR_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_CFP_MIC_ERR_LSB                                                 41
+#define RX_MPDU_END_CFP_MIC_ERR_MSB                                                 41
+#define RX_MPDU_END_CFP_MIC_ERR_MASK                                                0x0000020000000000
+
+#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET                                           0x0000000000000000
+#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB                                              42
+#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB                                              42
+#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK                                             0x0000040000000000
+
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET                                  0x0000000000000000
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB                                     43
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK                                    0x0000080000000000
+
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000000
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        44
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000100000000000
+
+#define RX_MPDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_OVERFLOW_ERR_LSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MSB                                                45
+#define RX_MPDU_END_OVERFLOW_ERR_MASK                                               0x0000200000000000
+
+#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB                                             46
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000400000000000
+
+#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_TKIP_MIC_ERR_LSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MSB                                                47
+#define RX_MPDU_END_TKIP_MIC_ERR_MASK                                               0x0000800000000000
+
+#define RX_MPDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000000
+#define RX_MPDU_END_DECRYPT_ERR_LSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MSB                                                 48
+#define RX_MPDU_END_DECRYPT_ERR_MASK                                                0x0001000000000000
+
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       49
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0002000000000000
+
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                             0x0000000000000000
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB                                50
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK                               0x0004000000000000
+
+#define RX_MPDU_END_FCS_ERR_OFFSET                                                  0x0000000000000000
+#define RX_MPDU_END_FCS_ERR_LSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MSB                                                     51
+#define RX_MPDU_END_FCS_ERR_MASK                                                    0x0008000000000000
+
+#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000000
+#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB                                             52
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK                                            0x0010000000000000
+
+#define RX_MPDU_END_RESERVED1C_OFFSET                                               0x0000000000000000
+#define RX_MPDU_END_RESERVED1C_LSB                                                  53
+#define RX_MPDU_END_RESERVED1C_MSB                                                  58
+#define RX_MPDU_END_RESERVED1C_MASK                                                 0x07e0000000000000
+
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000000
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB                                         59
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB                                         61
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK                                        0x3800000000000000
+
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000000
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       62
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x4000000000000000
+
+#define RX_MPDU_END_IFCS_PRESENT_OFFSET                                             0x0000000000000000
+#define RX_MPDU_END_IFCS_PRESENT_LSB                                                63
+#define RX_MPDU_END_IFCS_PRESENT_MSB                                                63
+#define RX_MPDU_END_IFCS_PRESENT_MASK                                               0x8000000000000000
+
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB                                0
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB                                0
+#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK                               0x0000000000000001
+
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB                                1
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB                                14
+#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK                               0x0000000000007ffe
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET                             0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK                               0x0000000000008000
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET                                   0x0000000000000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB                                      16
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB                                      31
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK                                     0x00000000ffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h b/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
new file mode 100644
index 000000000000..83f4df333c88
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_EXT_DESC_INFO_H_
+#define _RX_MPDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2
+
+struct rx_mpdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      pn_127_48_info                                          :  2,
+                      msdu_link_desc_index                                    :  4,
+                      reserved_1a                                             : 10;
+#else
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t reserved_1a                                             : 10,
+                      msdu_link_desc_index                                    :  4,
+                      pn_127_48_info                                          :  2,
+                      pn_47_32                                                : 16;
+#endif
+};
+
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET                                        0x00000000
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB                                           0
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB                                           31
+#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK                                          0xffffffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET                                       0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB                                          0
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB                                          15
+#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK                                         0x0000ffff
+
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET                                 0x00000004
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB                                    16
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB                                    17
+#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK                                   0x00030000
+
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET                           0x00000004
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB                              18
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB                              21
+#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK                             0x003c0000
+
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET                                    0x00000004
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB                                       22
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB                                       31
+#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK                                      0xffc00000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_info.h b/hw/wcn8750/v1/rx_mpdu_info.h
new file mode 100644
index 000000000000..d76b47b7a712
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_info.h
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+
+#include "rxpt_classify_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_INFO 30
+
+struct rx_mpdu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t epd_en                                                  :  1,
+                      all_frames_shall_be_encrypted                           :  1,
+                      encrypt_type                                            :  4,
+                      wep_key_width_for_variable_key                          :  2,
+                      __reserved_g_0003                                                :  2,
+                      bssid_hit                                               :  1,
+                      bssid_number                                            :  4,
+                      tid                                                     :  4,
+                      reserved_7a                                             : 13;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      receive_queue_number                                    : 16,
+                      pre_delim_err_warning                                   :  1,
+                      first_delim_err                                         :  1,
+                      reserved_2a                                             :  6;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_frame_control_valid                                :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_fragment_number                                    :  4,
+                      more_fragment_flag                                      :  1,
+                      protected_cbf_cqi                                       :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      encrypted                                               :  1,
+                      mpdu_retry                                              :  1,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t ast_index                                               : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      ndp_frame                                               :  1,
+                      phy_err                                                 :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      protocol_version_err                                    :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      __reserved_g_0086                                                 :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t key_id_octet                                            :  8,
+                      new_peer_entry                                          :  1,
+                      decrypt_needed                                          :  1,
+                      decap_type                                              :  2,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      pre_delim_count                                         : 12,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      raw_mpdu                                                :  1,
+                      reserved_12                                             :  1;
+             uint32_t mpdu_length                                             : 14,
+                      first_mpdu                                              :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      u_apsd_trigger                                          :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      amsdu_present                                           :  1,
+                      reserved_13                                             :  1;
+             uint32_t mpdu_frame_control_field                                : 16,
+                      mpdu_duration_field                                     : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad1_47_32                                      : 16,
+                      mac_addr_ad2_15_0                                       : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mac_addr_ad3_47_32                                      : 16,
+                      mpdu_sequence_control_field                             : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mac_addr_ad4_47_32                                      : 16,
+                      mpdu_qos_control_field                                  : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t vdev_id                                                 :  8,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      src_info                                                : 12,
+                      smr_frame                                               :  1,
+                      __reserved_g_0029                                       :  1;
+             uint32_t __reserved_g_0060                                       : 32;
+             uint32_t __reserved_g_0057                                       : 16,
+                      __reserved_g_0059                                       : 16;
+             uint32_t __reserved_g_0056                                       : 32;
+             uint32_t authorized_to_send_wds                                  :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      rx_misc_config                                          :  3,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      multi_link_ds_addr_fromtods_00_raw_en                   :  1,
+                      multi_link_ds_addr_fromtods_non00_raw_en                :  1,
+                      multi_link_ds_addr_ad3_valid                            :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      multi_link_ds_addr_mgmt_en                              :  1,
+                      multi_link_ds_addr_ctrl_en                              :  1,
+                      reserved_27a                                            :  5;
+             uint32_t multi_link_ds_addr_ad3_31_0                             : 32;
+             uint32_t multi_link_ds_addr_ad3_47_32                            : 16,
+                      cfp_mic_err                                             :  1,
+                      cfp_pn_chk_err                                          :  1,
+                      reserved_29a                                            : 14;
+#else
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t reserved_7a                                             : 13,
+                      tid                                                     :  4,
+                      bssid_number                                            :  4,
+                      bssid_hit                                               :  1,
+                      __reserved_g_0003                                                :  2,
+                      wep_key_width_for_variable_key                          :  2,
+                      encrypt_type                                            :  4,
+                      all_frames_shall_be_encrypted                           :  1,
+                      epd_en                                                  :  1;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             :  6,
+                      first_delim_err                                         :  1,
+                      pre_delim_err_warning                                   :  1,
+                      receive_queue_number                                    : 16,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      mpdu_retry                                              :  1,
+                      encrypted                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      protected_cbf_cqi                                       :  1,
+                      more_fragment_flag                                      :  1,
+                      mpdu_fragment_number                                    :  4,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mpdu_frame_control_valid                                :  1;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      ast_index                                               : 16;
+             uint32_t phy_ppdu_id                                             : 16,
+                      __reserved_g_0086                                                 :  1,
+                      __reserved_g_0005                                                 :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      protocol_version_err                                    :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      phy_err                                                 :  1,
+                      ndp_frame                                               :  1,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_12                                             :  1,
+                      raw_mpdu                                                :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      pre_delim_count                                         : 12,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      decap_type                                              :  2,
+                      decrypt_needed                                          :  1,
+                      new_peer_entry                                          :  1,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_13                                             :  1,
+                      amsdu_present                                           :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      u_apsd_trigger                                          :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      first_mpdu                                              :  1,
+                      mpdu_length                                             : 14;
+             uint32_t mpdu_duration_field                                     : 16,
+                      mpdu_frame_control_field                                : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad2_15_0                                       : 16,
+                      mac_addr_ad1_47_32                                      : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mpdu_sequence_control_field                             : 16,
+                      mac_addr_ad3_47_32                                      : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mpdu_qos_control_field                                  : 16,
+                      mac_addr_ad4_47_32                                      : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t __reserved_g_0029                                       :  1,
+                      smr_frame                                               :  1,
+                      src_info                                                : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      vdev_id                                                 :  8;
+             uint32_t __reserved_g_0060                                       : 32;
+             uint32_t __reserved_g_0059                                       : 16,
+                      __reserved_g_0057                                       : 16;
+             uint32_t __reserved_g_0056                                       : 32;
+             uint32_t reserved_27a                                            :  5,
+                      multi_link_ds_addr_ctrl_en                              :  1,
+                      multi_link_ds_addr_mgmt_en                              :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_ds_addr_ad3_valid                            :  1,
+                      multi_link_ds_addr_fromtods_non00_raw_en                :  1,
+                      multi_link_ds_addr_fromtods_00_raw_en                   :  1,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      rx_misc_config                                          :  3,
+                      fromtods_11_fnf_check_dis                               :  1,
+                      fromtods_10_fnf_check_dis                               :  1,
+                      fromtods_01_fnf_check_dis                               :  1,
+                      fromtods_00_fnf_check_dis                               :  1,
+                      disallow_mcbc_da_in_unicast_mpdu                        :  1,
+                      authorized_to_send_wds                                  :  1;
+             uint32_t multi_link_ds_addr_ad3_31_0                             : 32;
+             uint32_t reserved_29a                                            : 14,
+                      cfp_pn_chk_err                                          :  1,
+                      cfp_mic_err                                             :  1,
+                      multi_link_ds_addr_ad3_47_32                            : 16;
+#endif
+};
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET   0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB      0
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB      4
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK     0x0000001f
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET             0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB                5
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB                6
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK               0x00000060
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET    0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK      0x00000080
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK    0x00000100
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK    0x00000200
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET        0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK          0x00000400
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB    11
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB    13
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK   0x00003800
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK         0x00020000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK         0x00040000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK              0x00080000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET                      0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK                        0x00100000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET           0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK             0x00200000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK              0x00400000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET                  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB                     23
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB                     31
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK                    0xff800000
+
+#define RX_MPDU_INFO_EPD_EN_OFFSET                                                  0x00000004
+#define RX_MPDU_INFO_EPD_EN_LSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MASK                                                    0x00000001
+
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET                           0x00000004
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK                             0x00000002
+
+#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB                                               2
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB                                               5
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK                                              0x0000003c
+
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET                          0x00000004
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB                             6
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB                             7
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK                            0x000000c0
+
+#define RX_MPDU_INFO_BSSID_HIT_OFFSET                                               0x00000004
+#define RX_MPDU_INFO_BSSID_HIT_LSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MASK                                                 0x00000400
+
+#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_BSSID_NUMBER_LSB                                               11
+#define RX_MPDU_INFO_BSSID_NUMBER_MSB                                               14
+#define RX_MPDU_INFO_BSSID_NUMBER_MASK                                              0x00007800
+
+#define RX_MPDU_INFO_TID_OFFSET                                                     0x00000004
+#define RX_MPDU_INFO_TID_LSB                                                        15
+#define RX_MPDU_INFO_TID_MSB                                                        18
+#define RX_MPDU_INFO_TID_MASK                                                       0x00078000
+
+#define RX_MPDU_INFO_RESERVED_7A_OFFSET                                             0x00000004
+#define RX_MPDU_INFO_RESERVED_7A_LSB                                                19
+#define RX_MPDU_INFO_RESERVED_7A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_7A_MASK                                               0xfff80000
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                             0x00000008
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                                0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                                31
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                            0x0000000c
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                               0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                               7
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                              0x000000ff
+
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x0000000c
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB                                       8
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB                                       23
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK                                      0x00ffff00
+
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET                                   0x0000000c
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK                                     0x01000000
+
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET                                         0x0000000c
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK                                           0x02000000
+
+#define RX_MPDU_INFO_RESERVED_2A_OFFSET                                             0x0000000c
+#define RX_MPDU_INFO_RESERVED_2A_LSB                                                26
+#define RX_MPDU_INFO_RESERVED_2A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_2A_MASK                                               0xfc000000
+
+#define RX_MPDU_INFO_PN_31_0_OFFSET                                                 0x00000010
+#define RX_MPDU_INFO_PN_31_0_LSB                                                    0
+#define RX_MPDU_INFO_PN_31_0_MSB                                                    31
+#define RX_MPDU_INFO_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_MPDU_INFO_PN_63_32_OFFSET                                                0x00000014
+#define RX_MPDU_INFO_PN_63_32_LSB                                                   0
+#define RX_MPDU_INFO_PN_63_32_MSB                                                   31
+#define RX_MPDU_INFO_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_95_64_OFFSET                                                0x00000018
+#define RX_MPDU_INFO_PN_95_64_LSB                                                   0
+#define RX_MPDU_INFO_PN_95_64_MSB                                                   31
+#define RX_MPDU_INFO_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_127_96_OFFSET                                               0x0000001c
+#define RX_MPDU_INFO_PN_127_96_LSB                                                  0
+#define RX_MPDU_INFO_PN_127_96_MSB                                                  31
+#define RX_MPDU_INFO_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET                                0x00000020
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK                                  0x00000001
+
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET                                     0x00000020
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK                                       0x00000002
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK                                        0x00000004
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK                                        0x00000008
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK                                        0x00000010
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK                                        0x00000020
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK                               0x00000040
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                                  0x00000020
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK                                    0x00000080
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET                                   0x00000020
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK                                     0x00000100
+
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK                               0x00000200
+
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB                                       10
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB                                       13
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK                                      0x00003c00
+
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK                                        0x00004000
+
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET                                       0x00000020
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB                                          15
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB                                          15
+#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK                                         0x00008000
+
+#define RX_MPDU_INFO_FR_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_FR_DS_LSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MASK                                                     0x00010000
+
+#define RX_MPDU_INFO_TO_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_TO_DS_LSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MASK                                                     0x00020000
+
+#define RX_MPDU_INFO_ENCRYPTED_OFFSET                                               0x00000020
+#define RX_MPDU_INFO_ENCRYPTED_LSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MASK                                                 0x00040000
+
+#define RX_MPDU_INFO_MPDU_RETRY_OFFSET                                              0x00000020
+#define RX_MPDU_INFO_MPDU_RETRY_LSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MASK                                                0x00080000
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB                                       20
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB                                       31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK                                      0xfff00000
+
+#define RX_MPDU_INFO_PEER_META_DATA_OFFSET                                          0x00000024
+#define RX_MPDU_INFO_PEER_META_DATA_LSB                                             0
+#define RX_MPDU_INFO_PEER_META_DATA_MSB                                             31
+#define RX_MPDU_INFO_PEER_META_DATA_MASK                                            0xffffffff
+
+#define RX_MPDU_INFO_AST_INDEX_OFFSET                                               0x00000028
+#define RX_MPDU_INFO_AST_INDEX_LSB                                                  0
+#define RX_MPDU_INFO_AST_INDEX_MSB                                                  15
+#define RX_MPDU_INFO_AST_INDEX_MASK                                                 0x0000ffff
+
+#define RX_MPDU_INFO_SW_PEER_ID_OFFSET                                              0x00000028
+#define RX_MPDU_INFO_SW_PEER_ID_LSB                                                 16
+#define RX_MPDU_INFO_SW_PEER_ID_MSB                                                 31
+#define RX_MPDU_INFO_SW_PEER_ID_MASK                                                0xffff0000
+
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000002c
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x00000003
+
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET                                       0x0000002c
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK                                         0x000001fc
+
+#define RX_MPDU_INFO_NDP_FRAME_OFFSET                                               0x0000002c
+#define RX_MPDU_INFO_NDP_FRAME_LSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MASK                                                 0x00000200
+
+#define RX_MPDU_INFO_PHY_ERR_OFFSET                                                 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_LSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MASK                                                   0x00000400
+
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET                              0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK                                0x00000800
+
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET                                    0x0000002c
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK                                      0x00001000
+
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET                                  0x0000002c
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK                                    0x00002000
+
+#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET                                             0x0000002c
+#define RX_MPDU_INFO_PHY_PPDU_ID_LSB                                                16
+#define RX_MPDU_INFO_PHY_PPDU_ID_MSB                                                31
+#define RX_MPDU_INFO_PHY_PPDU_ID_MASK                                               0xffff0000
+
+#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET                                            0x00000030
+#define RX_MPDU_INFO_KEY_ID_OCTET_LSB                                               0
+#define RX_MPDU_INFO_KEY_ID_OCTET_MSB                                               7
+#define RX_MPDU_INFO_KEY_ID_OCTET_MASK                                              0x000000ff
+
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK                                            0x00000100
+
+#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK                                            0x00000200
+
+#define RX_MPDU_INFO_DECAP_TYPE_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_DECAP_TYPE_LSB                                                 10
+#define RX_MPDU_INFO_DECAP_TYPE_MSB                                                 11
+#define RX_MPDU_INFO_DECAP_TYPE_MASK                                                0x00000c00
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK                              0x00001000
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK                              0x00002000
+
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK                                    0x00004000
+
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK                                    0x00008000
+
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET                                         0x00000030
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB                                            16
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB                                            27
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK                                           0x0fff0000
+
+#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_AMPDU_FLAG_LSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MASK                                                0x10000000
+
+#define RX_MPDU_INFO_BAR_FRAME_OFFSET                                               0x00000030
+#define RX_MPDU_INFO_BAR_FRAME_LSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MASK                                                 0x20000000
+
+#define RX_MPDU_INFO_RAW_MPDU_OFFSET                                                0x00000030
+#define RX_MPDU_INFO_RAW_MPDU_LSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MASK                                                  0x40000000
+
+#define RX_MPDU_INFO_RESERVED_12_OFFSET                                             0x00000030
+#define RX_MPDU_INFO_RESERVED_12_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MPDU_LENGTH_LSB                                                0
+#define RX_MPDU_INFO_MPDU_LENGTH_MSB                                                13
+#define RX_MPDU_INFO_MPDU_LENGTH_MASK                                               0x00003fff
+
+#define RX_MPDU_INFO_FIRST_MPDU_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_FIRST_MPDU_LSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MASK                                                0x00004000
+
+#define RX_MPDU_INFO_MCAST_BCAST_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MCAST_BCAST_LSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MASK                                               0x00008000
+
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET                                     0x00000034
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK                                       0x00010000
+
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET                                       0x00000034
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK                                         0x00020000
+
+#define RX_MPDU_INFO_POWER_MGMT_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_POWER_MGMT_LSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MASK                                                0x00040000
+
+#define RX_MPDU_INFO_NON_QOS_OFFSET                                                 0x00000034
+#define RX_MPDU_INFO_NON_QOS_LSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MASK                                                   0x00080000
+
+#define RX_MPDU_INFO_NULL_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_NULL_DATA_LSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MASK                                                 0x00100000
+
+#define RX_MPDU_INFO_MGMT_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MGMT_TYPE_LSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MASK                                                 0x00200000
+
+#define RX_MPDU_INFO_CTRL_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_CTRL_TYPE_LSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MASK                                                 0x00400000
+
+#define RX_MPDU_INFO_MORE_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MORE_DATA_LSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MASK                                                 0x00800000
+
+#define RX_MPDU_INFO_EOSP_OFFSET                                                    0x00000034
+#define RX_MPDU_INFO_EOSP_LSB                                                       24
+#define RX_MPDU_INFO_EOSP_MSB                                                       24
+#define RX_MPDU_INFO_EOSP_MASK                                                      0x01000000
+
+#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK                                             0x02000000
+
+#define RX_MPDU_INFO_ORDER_OFFSET                                                   0x00000034
+#define RX_MPDU_INFO_ORDER_LSB                                                      26
+#define RX_MPDU_INFO_ORDER_MSB                                                      26
+#define RX_MPDU_INFO_ORDER_MASK                                                     0x04000000
+
+#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET                                          0x00000034
+#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK                                            0x08000000
+
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET                                        0x00000034
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK                                          0x10000000
+
+#define RX_MPDU_INFO_DIRECTED_OFFSET                                                0x00000034
+#define RX_MPDU_INFO_DIRECTED_LSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MASK                                                  0x20000000
+
+#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_AMSDU_PRESENT_LSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MASK                                             0x40000000
+
+#define RX_MPDU_INFO_RESERVED_13_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_RESERVED_13_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET                                0x00000038
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB                                   15
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK                                  0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET                                     0x00000038
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB                                        16
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB                                        31
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK                                       0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET                                       0x0000003c
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET                                      0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET                                       0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB                                          16
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK                                         0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET                                      0x00000044
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB                                         31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK                                        0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET                                       0x00000048
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET                                      0x0000004c
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET                             0x0000004c
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB                                16
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB                                31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK                               0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET                                       0x00000050
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET                                      0x00000054
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET                                  0x00000054
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB                                     16
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB                                     31
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK                                    0xffff0000
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET                                   0x00000058
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB                                      0
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB                                      31
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK                                     0xffffffff
+
+#define RX_MPDU_INFO_VDEV_ID_OFFSET                                                 0x0000005c
+#define RX_MPDU_INFO_VDEV_ID_LSB                                                    0
+#define RX_MPDU_INFO_VDEV_ID_MSB                                                    7
+#define RX_MPDU_INFO_VDEV_ID_MASK                                                   0x000000ff
+
+#define RX_MPDU_INFO_SERVICE_CODE_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_SERVICE_CODE_LSB                                               8
+#define RX_MPDU_INFO_SERVICE_CODE_MSB                                               16
+#define RX_MPDU_INFO_SERVICE_CODE_MASK                                              0x0001ff00
+
+#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET                                          0x0000005c
+#define RX_MPDU_INFO_PRIORITY_VALID_LSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_SRC_INFO_OFFSET                                                0x0000005c
+#define RX_MPDU_INFO_SRC_INFO_LSB                                                   18
+#define RX_MPDU_INFO_SRC_INFO_MSB                                                   29
+#define RX_MPDU_INFO_SRC_INFO_MASK                                                  0x3ffc0000
+
+#define RX_MPDU_INFO_SMR_FRAME_OFFSET                                               0x0000005c
+#define RX_MPDU_INFO_SMR_FRAME_LSB                                                  30
+#define RX_MPDU_INFO_SMR_FRAME_MSB                                                  30
+#define RX_MPDU_INFO_SMR_FRAME_MASK                                                 0x40000000
+
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK                                    0x00000001
+
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET                        0x0000006c
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB                           1
+#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK                          0x00000002
+
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB                                  2
+#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK                                 0x00000004
+
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB                                  3
+#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK                                 0x00000008
+
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB                                  4
+#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK                                 0x00000010
+
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET                               0x0000006c
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB                                  5
+#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK                                 0x00000020
+
+#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET                                          0x0000006c
+#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB                                             6
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB                                             8
+#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK                                            0x000001c0
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB                                     9
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB                                     10
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK                                    0x00000600
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB                                     11
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB                                     12
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK                                    0x00001800
+
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB                                     13
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB                                     14
+#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK                                    0x00006000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB                      15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB                      15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK                     0x00008000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET                0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB                   16
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB                   16
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK                  0x00010000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET                            0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB                               17
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB                               17
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK                              0x00020000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                   0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                      18
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                     0x00040000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                          0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                             19
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                            0x00080000
+
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                           0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                              20
+#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                             0x00100000
+
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB                                       21
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB                                       22
+#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK                                      0x00600000
+
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET                                    0x0000006c
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB                                       23
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB                                       24
+#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK                                      0x01800000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET                              0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB                                 25
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB                                 25
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK                                0x02000000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET                              0x0000006c
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB                                 26
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB                                 26
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK                                0x04000000
+
+#define RX_MPDU_INFO_RESERVED_27A_OFFSET                                            0x0000006c
+#define RX_MPDU_INFO_RESERVED_27A_LSB                                               27
+#define RX_MPDU_INFO_RESERVED_27A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_27A_MASK                                              0xf8000000
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET                             0x00000070
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB                                0
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB                                31
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET                            0x00000074
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB                               0
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB                               15
+#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK                              0x0000ffff
+
+#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET                                             0x00000074
+#define RX_MPDU_INFO_CFP_MIC_ERR_LSB                                                16
+#define RX_MPDU_INFO_CFP_MIC_ERR_MSB                                                16
+#define RX_MPDU_INFO_CFP_MIC_ERR_MASK                                               0x00010000
+
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET                                          0x00000074
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB                                             17
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB                                             17
+#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_RESERVED_29A_OFFSET                                            0x00000074
+#define RX_MPDU_INFO_RESERVED_29A_LSB                                               18
+#define RX_MPDU_INFO_RESERVED_29A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_29A_MASK                                              0xfffc0000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_link_ptr.h b/hw/wcn8750/v1/rx_mpdu_link_ptr.h
new file mode 100644
index 000000000000..e9d7e83a92cc
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_link_ptr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#else
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#endif
+};
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB              0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB             0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB             7
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB         8
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB         11
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB              12
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_mpdu_start.h b/hw/wcn8750/v1/rx_mpdu_start.h
new file mode 100644
index 000000000000..fc5029dc2da3
--- /dev/null
+++ b/hw/wcn8750/v1/rx_mpdu_start.h
@@ -0,0 +1,712 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+
+#include "rx_mpdu_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_START 30
+
+#define NUM_OF_QWORDS_RX_MPDU_START 15
+
+struct rx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#else
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#endif
+};
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK  0x0000000000100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET                            0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB                               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK                              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET     0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK       0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB                         34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB                         37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK                        0x0000003c00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET    0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB       39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK      0x000000c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET                         0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB                            42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK                           0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET                      0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB                         43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB                         46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK                        0x0000780000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET                               0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB                                  47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB                                  50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK                                 0x0007800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET                       0x0000000000000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB                          51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK                         0xfff8000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB         39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET              0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB                 40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK                0x00ffff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET             0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB                56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK               0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET                   0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB                      57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK                     0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET                       0x0000000000000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB                          58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK                         0xfc00000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET                           0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB                              0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB                              31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK                             0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET                          0x0000000000000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB                             32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB                             63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK                            0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET                          0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB                             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB                             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK                            0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET                         0x0000000000000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB                            32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB                            63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK                           0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET          0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK            0x0000000000000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET               0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK                 0x0000000000000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK                  0x0000000000000004
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK                  0x0000000000000008
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK                  0x0000000000000010
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK                  0x0000000000000020
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK         0x0000000000000040
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET            0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK              0x0000000000000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK               0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET       0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK         0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB                 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB                 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK                0x0000000000003c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET                0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK                  0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET                 0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB                    15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB                    15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK                   0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK                               0x0000000000010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET                             0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK                               0x0000000000020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET                         0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK                           0x0000000000040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET                        0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK                          0x0000000000080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET              0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB                 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB                 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK                0x00000000fff00000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET                    0x0000000000000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB                       32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB                       63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK                      0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB                            0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB                            15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK                           0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET                        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB                           16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB                           31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK                          0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET     0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB        32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB        33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK       0x0000000300000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET                 0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB                    34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB                    40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK                   0x000001fc00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET                         0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB                            41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK                           0x0000020000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET                           0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB                              42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK                             0x0000040000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET        0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB           43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK          0x0000080000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET              0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB                 44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK                0x0000100000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET            0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK              0x0000200000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET                       0x0000000000000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK                         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET                      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB                         7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK                        0x00000000000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK                      0x0000000000000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK                      0x0000000000000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB                           10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB                           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK                          0x0000000000000c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK        0x0000000000001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET      0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK        0x0000000000002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK              0x0000000000004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET            0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK              0x0000000000008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET                   0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB                      16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB                      27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK                     0x000000000fff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK                          0x0000000010000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK                           0x0000000020000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK                            0x0000000040000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK                         0x0000000080000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB                          32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB                          45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK                         0x00003fff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB                           46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK                          0x0000400000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB                          47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK                         0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET               0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB                  48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK                 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET                 0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB                    49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK                   0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET                        0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB                           50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK                          0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET                           0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB                              51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK                             0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB                            52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK                           0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB                            53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK                           0x0020000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB                            54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK                           0x0040000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET                         0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB                            55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK                           0x0080000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET                              0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB                                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK                                0x0100000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB                        57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK                       0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET                             0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB                                58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK                               0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET                    0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB                       59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK                      0x0800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET                  0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB                     60
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK                    0x1000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET                          0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK                            0x2000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET                     0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB                        62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK                       0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET                       0x0000000000000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB                          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK                         0x8000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET          0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB             15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK            0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET               0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB                  31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK                 0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET                 0x0000000000000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB                    32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB                    63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK                   0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK                  0x000000000000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET                 0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB                    16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK                   0x00000000ffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET                0x0000000000000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB                   63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK                  0xffffffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET                 0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET                0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET       0x0000000000000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB          63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK         0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET                 0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK                   0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET                0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB                   32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB                   47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK                  0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET            0x0000000000000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB               48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB               63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK              0xffff000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET             0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB                0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB                31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK               0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET                           0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB                              32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB                              39
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK                             0x000000ff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET                      0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB                         40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB                         48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK                        0x0001ff0000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET                    0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK                      0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET                          0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB                             50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB                             61
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK                            0x3ffc000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET                         0x0000000000000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB                            62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB                            62
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK                           0x4000000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB               32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK              0x0000000100000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET  0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB     33
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK    0x0000000200000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB            34
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK           0x0000000400000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB            35
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK           0x0000000800000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB            36
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK           0x0000001000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET         0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB            37
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK           0x0000002000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET                    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB                       38
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB                       40
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK                      0x000001c000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB               41
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB               42
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK              0x0000060000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB               43
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB               44
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK              0x0000180000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET            0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB               45
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB               46
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK              0x0000600000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET      0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB         49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB         49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK        0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET    0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB       51
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK      0x0008000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET     0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB        52
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK       0x0010000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB                 53
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB                 54
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK                0x0060000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET              0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB                 55
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB                 56
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK                0x0180000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET        0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB           57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB           57
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK          0x0200000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET        0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB           58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB           58
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK          0x0400000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET                      0x0000000000000068
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB                         59
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK                        0xf800000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET       0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK         0x00000000ffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET      0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB         32
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB         47
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK        0x0000ffff00000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET                       0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB                          48
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK                         0x0001000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET                    0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB                       49
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK                      0x0002000000000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET                      0x0000000000000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB                         50
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB                         63
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK                        0xfffc000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_desc_info.h b/hw/wcn8750/v1/rx_msdu_desc_info.h
new file mode 100644
index 000000000000..88569b653b64
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_desc_info.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
+
+struct rx_msdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t first_msdu_in_mpdu_flag                                 :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      msdu_continuation                                       :  1,
+                      msdu_length                                             : 14,
+                      msdu_drop                                               :  1,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding_msb                                   :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      decap_format                                            :  2,
+                      __reserved_g_0015                                       :  1;
+#else
+             uint32_t __reserved_g_0015                                       :  1,
+                      decap_format                                            :  2,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      l3_header_padding_msb                                   :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      msdu_drop                                               :  1,
+                      msdu_length                                             : 14,
+                      msdu_continuation                                       :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      first_msdu_in_mpdu_flag                                 :  1;
+#endif
+};
+
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET                            0x00000000
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK                              0x00000001
+
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET                             0x00000000
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK                               0x00000002
+
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET                                  0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK                                    0x00000004
+
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB                                           3
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB                                           16
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK                                          0x0001fff8
+
+#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK                                            0x00020000
+
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK                                          0x00040000
+
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK                                          0x00080000
+
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET                                         0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK                                           0x00100000
+
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET                              0x00000000
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK                                0x00200000
+
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET                                0x00000000
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK                                  0x00400000
+
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET                                     0x00000000
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK                                       0x00800000
+
+#define RX_MSDU_DESC_INFO_FR_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_FR_DS_LSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MASK                                                0x01000000
+
+#define RX_MSDU_DESC_INFO_TO_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_TO_DS_LSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MASK                                                0x02000000
+
+#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK                                            0x04000000
+
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB                                          27
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB                                          28
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK                                         0x18000000
+
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB                                          29
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB                                          30
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK                                         0x60000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_details.h b/hw/wcn8750/v1/rx_msdu_details.h
new file mode 100644
index 000000000000..0b763a473ce6
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_details.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_ext_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB               0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB              0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB              7
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB               12
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET    0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK      0x00000001
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET     0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK       0x00000002
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET          0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK            0x00000004
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB                   3
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB                   16
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK                  0x0001fff8
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                    0x00020000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK                  0x00040000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK                  0x00080000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET                 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK                   0x00100000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK        0x00200000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET        0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK          0x00400000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK               0x00800000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                        0x01000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                        0x02000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                    0x04000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB                  27
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB                  28
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK                 0x18000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB                   29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB                   31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK                  0xe0000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB                  29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET           0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB              5
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB              13
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK             0x00003fe0
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET         0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK           0x00004000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB               15
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB               26
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK              0x07ff8000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB               27
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB               29
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK              0x38000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB               30
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB               31
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK              0xc0000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_end.h b/hw/wcn8750/v1/rx_msdu_end.h
new file mode 100644
index 000000000000..b05c9896b09a
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_end.h
@@ -0,0 +1,1094 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_END 32
+
+#define NUM_OF_QWORDS_RX_MSDU_END 16
+
+struct rx_msdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ip_hdr_chksum                                           : 16,
+                      reported_mpdu_length                                    : 14,
+                      reserved_1a                                             :  2;
+             uint32_t reserved_2a                                             :  8,
+                      cce_super_rule                                          :  6,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cumulative_l3_checksum                                  : 16;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t da_offset                                               :  6,
+                      sa_offset                                               :  6,
+                      da_offset_valid                                         :  1,
+                      sa_offset_valid                                         :  1,
+                      reserved_5a                                             :  2,
+                      l3_type                                                 : 16;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t tcp_flag                                                :  9,
+                      lro_eligible                                            :  1,
+                      reserved_9a                                             :  6,
+                      window_size                                             : 16;
+             uint32_t sa_sw_peer_id                                           : 16,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      to_ds                                                   :  1,
+                      tid                                                     :  4,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding                                       :  2,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail_copy                                     :  1;
+             uint32_t sa_idx                                                  : 16,
+                      da_idx_or_sw_peer_id                                    : 16;
+             uint32_t msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      flow_idx                                                : 20,
+                      use_ppe                                                 :  1,
+                      __reserved_g_0003                                                :  2,
+                      vlan_ctag_stripped                                      :  1,
+                      vlan_stag_stripped                                      :  1,
+                      fragment_flag                                           :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t cce_metadata                                            : 16,
+                      tcp_udp_chksum                                          : 16;
+             uint32_t aggregation_count                                       :  8,
+                      flow_aggregation_continuation                           :  1,
+                      fisa_timeout                                            :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      msdu_limit_error                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      cce_match                                               :  1,
+                      amsdu_parser_error                                      :  1,
+                      cumulative_ip_length                                    : 16;
+             uint32_t key_id_octet                                            :  8,
+                      reserved_16a                                            : 24;
+             uint32_t reserved_17a                                            :  6,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      multicast_echo                                          :  1,
+                      wds_learning_event                                      :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      __reserved_g_0015                                       :  1,
+                      reserved_17b                                            :  8;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  6,
+                      msdu_done_copy                                          :  1;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t reserved_28a                                            : 16,
+                      sa_15_0                                                 : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_30a                                            :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      reserved_30b                                            :  1,
+                      order                                                   :  1,
+                      wifi_parser_error                                       :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t reserved_31a                                            : 10,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      ifcs_present                                            :  1,
+                      reserved_31b                                            : 16,
+                      msdu_done                                               :  1;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1a                                             :  2,
+                      reported_mpdu_length                                    : 14,
+                      ip_hdr_chksum                                           : 16;
+             uint32_t cumulative_l3_checksum                                  : 16,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_super_rule                                          :  6,
+                      reserved_2a                                             :  8;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             :  2,
+                      sa_offset_valid                                         :  1,
+                      da_offset_valid                                         :  1,
+                      sa_offset                                               :  6,
+                      da_offset                                               :  6;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t window_size                                             : 16,
+                      reserved_9a                                             :  6,
+                      lro_eligible                                            :  1,
+                      tcp_flag                                                :  9;
+             uint32_t ip_chksum_fail_copy                                     :  1,
+                      fr_ds                                                   :  1,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      l3_header_padding                                       :  2,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      tid                                                     :  4,
+                      to_ds                                                   :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      sa_sw_peer_id                                           : 16;
+             uint32_t da_idx_or_sw_peer_id                                    : 16,
+                      sa_idx                                                  : 16;
+             uint32_t fragment_flag                                           :  1,
+                      vlan_stag_stripped                                      :  1,
+                      vlan_ctag_stripped                                      :  1,
+                      __reserved_g_0003                                                :  2,
+                      use_ppe                                                 :  1,
+                      flow_idx                                                : 20,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t tcp_udp_chksum                                          : 16,
+                      cce_metadata                                            : 16;
+             uint32_t cumulative_ip_length                                    : 16,
+                      amsdu_parser_error                                      :  1,
+                      cce_match                                               :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      msdu_limit_error                                        :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      fisa_timeout                                            :  1,
+                      flow_aggregation_continuation                           :  1,
+                      aggregation_count                                       :  8;
+             uint32_t reserved_16a                                            : 24,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_17b                                            :  8,
+                      __reserved_g_0015                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_learning_event                                      :  1,
+                      multicast_echo                                          :  1,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_17a                                            :  6;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t msdu_done_copy                                          :  1,
+                      mimo_ss_bitmap                                          :  6,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t sa_15_0                                                 : 16,
+                      reserved_28a                                            : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      wifi_parser_error                                       :  1,
+                      order                                                   :  1,
+                      reserved_30b                                            :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_30a                                            :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_31b                                            : 16,
+                      ifcs_present                                            :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved_31a                                            : 10;
+#endif
+};
+
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x0000000000000000
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x0000000000000003
+
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x0000000000000000
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK                                          0x00000000000001fc
+
+#define RX_MSDU_END_RESERVED_0_OFFSET                                               0x0000000000000000
+#define RX_MSDU_END_RESERVED_0_LSB                                                  9
+#define RX_MSDU_END_RESERVED_0_MSB                                                  15
+#define RX_MSDU_END_RESERVED_0_MASK                                                 0x000000000000fe00
+
+#define RX_MSDU_END_PHY_PPDU_ID_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MSDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MSDU_END_PHY_PPDU_ID_MASK                                                0x00000000ffff0000
+
+#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET                                            0x0000000000000000
+#define RX_MSDU_END_IP_HDR_CHKSUM_LSB                                               32
+#define RX_MSDU_END_IP_HDR_CHKSUM_MSB                                               47
+#define RX_MSDU_END_IP_HDR_CHKSUM_MASK                                              0x0000ffff00000000
+
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET                                     0x0000000000000000
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB                                        48
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB                                        61
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK                                       0x3fff000000000000
+
+#define RX_MSDU_END_RESERVED_1A_OFFSET                                              0x0000000000000000
+#define RX_MSDU_END_RESERVED_1A_LSB                                                 62
+#define RX_MSDU_END_RESERVED_1A_MSB                                                 63
+#define RX_MSDU_END_RESERVED_1A_MASK                                                0xc000000000000000
+
+#define RX_MSDU_END_RESERVED_2A_OFFSET                                              0x0000000000000008
+#define RX_MSDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MSDU_END_RESERVED_2A_MSB                                                 7
+#define RX_MSDU_END_RESERVED_2A_MASK                                                0x00000000000000ff
+
+#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET                                           0x0000000000000008
+#define RX_MSDU_END_CCE_SUPER_RULE_LSB                                              8
+#define RX_MSDU_END_CCE_SUPER_RULE_MSB                                              13
+#define RX_MSDU_END_CCE_SUPER_RULE_MASK                                             0x0000000000003f00
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET                           0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK                             0x0000000000004000
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET                            0x0000000000000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK                              0x0000000000008000
+
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET                                   0x0000000000000008
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB                                      16
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB                                      31
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK                                     0x00000000ffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET                                     0x0000000000000008
+#define RX_MSDU_END_RULE_INDICATION_31_0_LSB                                        32
+#define RX_MSDU_END_RULE_INDICATION_31_0_MSB                                        63
+#define RX_MSDU_END_RULE_INDICATION_31_0_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET                                         0x0000000000000010
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB                                            0
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB                                            31
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK                                           0x00000000ffffffff
+
+#define RX_MSDU_END_DA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_LSB                                                   32
+#define RX_MSDU_END_DA_OFFSET_MSB                                                   37
+#define RX_MSDU_END_DA_OFFSET_MASK                                                  0x0000003f00000000
+
+#define RX_MSDU_END_SA_OFFSET_OFFSET                                                0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_LSB                                                   38
+#define RX_MSDU_END_SA_OFFSET_MSB                                                   43
+#define RX_MSDU_END_SA_OFFSET_MASK                                                  0x00000fc000000000
+
+#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_DA_OFFSET_VALID_LSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MSB                                             44
+#define RX_MSDU_END_DA_OFFSET_VALID_MASK                                            0x0000100000000000
+
+#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET                                          0x0000000000000010
+#define RX_MSDU_END_SA_OFFSET_VALID_LSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MSB                                             45
+#define RX_MSDU_END_SA_OFFSET_VALID_MASK                                            0x0000200000000000
+
+#define RX_MSDU_END_RESERVED_5A_OFFSET                                              0x0000000000000010
+#define RX_MSDU_END_RESERVED_5A_LSB                                                 46
+#define RX_MSDU_END_RESERVED_5A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_5A_MASK                                                0x0000c00000000000
+
+#define RX_MSDU_END_L3_TYPE_OFFSET                                                  0x0000000000000010
+#define RX_MSDU_END_L3_TYPE_LSB                                                     48
+#define RX_MSDU_END_L3_TYPE_MSB                                                     63
+#define RX_MSDU_END_L3_TYPE_MASK                                                    0xffff000000000000
+
+#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET                                    0x0000000000000018
+#define RX_MSDU_END_RULE_INDICATION_63_32_LSB                                       0
+#define RX_MSDU_END_RULE_INDICATION_63_32_MSB                                       31
+#define RX_MSDU_END_RULE_INDICATION_63_32_MASK                                      0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET                                           0x0000000000000018
+#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB                                              32
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB                                              63
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET                                           0x0000000000000020
+#define RX_MSDU_END_TCP_ACK_NUMBER_LSB                                              0
+#define RX_MSDU_END_TCP_ACK_NUMBER_MSB                                              31
+#define RX_MSDU_END_TCP_ACK_NUMBER_MASK                                             0x00000000ffffffff
+
+#define RX_MSDU_END_TCP_FLAG_OFFSET                                                 0x0000000000000020
+#define RX_MSDU_END_TCP_FLAG_LSB                                                    32
+#define RX_MSDU_END_TCP_FLAG_MSB                                                    40
+#define RX_MSDU_END_TCP_FLAG_MASK                                                   0x000001ff00000000
+
+#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET                                             0x0000000000000020
+#define RX_MSDU_END_LRO_ELIGIBLE_LSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MSB                                                41
+#define RX_MSDU_END_LRO_ELIGIBLE_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_RESERVED_9A_LSB                                                 42
+#define RX_MSDU_END_RESERVED_9A_MSB                                                 47
+#define RX_MSDU_END_RESERVED_9A_MASK                                                0x0000fc0000000000
+
+#define RX_MSDU_END_WINDOW_SIZE_OFFSET                                              0x0000000000000020
+#define RX_MSDU_END_WINDOW_SIZE_LSB                                                 48
+#define RX_MSDU_END_WINDOW_SIZE_MSB                                                 63
+#define RX_MSDU_END_WINDOW_SIZE_MASK                                                0xffff000000000000
+
+#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET                                            0x0000000000000028
+#define RX_MSDU_END_SA_SW_PEER_ID_LSB                                               0
+#define RX_MSDU_END_SA_SW_PEER_ID_MSB                                               15
+#define RX_MSDU_END_SA_SW_PEER_ID_MASK                                              0x000000000000ffff
+
+#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK                                             0x0000000000010000
+
+#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET                                           0x0000000000000028
+#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK                                             0x0000000000020000
+
+#define RX_MSDU_END_TO_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_TO_DS_LSB                                                       18
+#define RX_MSDU_END_TO_DS_MSB                                                       18
+#define RX_MSDU_END_TO_DS_MASK                                                      0x0000000000040000
+
+#define RX_MSDU_END_TID_OFFSET                                                      0x0000000000000028
+#define RX_MSDU_END_TID_LSB                                                         19
+#define RX_MSDU_END_TID_MSB                                                         22
+#define RX_MSDU_END_TID_MASK                                                        0x0000000000780000
+
+#define RX_MSDU_END_SA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_SA_IS_VALID_LSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MASK                                                0x0000000000800000
+
+#define RX_MSDU_END_DA_IS_VALID_OFFSET                                              0x0000000000000028
+#define RX_MSDU_END_DA_IS_VALID_LSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MASK                                                0x0000000001000000
+
+#define RX_MSDU_END_DA_IS_MCBC_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_DA_IS_MCBC_LSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MASK                                                 0x0000000002000000
+
+#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET                                        0x0000000000000028
+#define RX_MSDU_END_L3_HEADER_PADDING_LSB                                           26
+#define RX_MSDU_END_L3_HEADER_PADDING_MSB                                           27
+#define RX_MSDU_END_L3_HEADER_PADDING_MASK                                          0x000000000c000000
+
+#define RX_MSDU_END_FIRST_MSDU_OFFSET                                               0x0000000000000028
+#define RX_MSDU_END_FIRST_MSDU_LSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MASK                                                 0x0000000010000000
+
+#define RX_MSDU_END_LAST_MSDU_OFFSET                                                0x0000000000000028
+#define RX_MSDU_END_LAST_MSDU_LSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MASK                                                  0x0000000020000000
+
+#define RX_MSDU_END_FR_DS_OFFSET                                                    0x0000000000000028
+#define RX_MSDU_END_FR_DS_LSB                                                       30
+#define RX_MSDU_END_FR_DS_MSB                                                       30
+#define RX_MSDU_END_FR_DS_MASK                                                      0x0000000040000000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET                                      0x0000000000000028
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK                                        0x0000000080000000
+
+#define RX_MSDU_END_SA_IDX_OFFSET                                                   0x0000000000000028
+#define RX_MSDU_END_SA_IDX_LSB                                                      32
+#define RX_MSDU_END_SA_IDX_MSB                                                      47
+#define RX_MSDU_END_SA_IDX_MASK                                                     0x0000ffff00000000
+
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET                                     0x0000000000000028
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB                                        48
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB                                        63
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_MSDU_DROP_OFFSET                                                0x0000000000000030
+#define RX_MSDU_END_MSDU_DROP_LSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MASK                                                  0x0000000000000001
+
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET                               0x0000000000000030
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB                                  1
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB                                  5
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK                                 0x000000000000003e
+
+#define RX_MSDU_END_FLOW_IDX_OFFSET                                                 0x0000000000000030
+#define RX_MSDU_END_FLOW_IDX_LSB                                                    6
+#define RX_MSDU_END_FLOW_IDX_MSB                                                    25
+#define RX_MSDU_END_FLOW_IDX_MASK                                                   0x0000000003ffffc0
+
+#define RX_MSDU_END_USE_PPE_OFFSET                                                  0x0000000000000030
+#define RX_MSDU_END_USE_PPE_LSB                                                     26
+#define RX_MSDU_END_USE_PPE_MSB                                                     26
+#define RX_MSDU_END_USE_PPE_MASK                                                    0x0000000004000000
+
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK                                         0x0000000020000000
+
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET                                       0x0000000000000030
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK                                         0x0000000040000000
+
+#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET                                            0x0000000000000030
+#define RX_MSDU_END_FRAGMENT_FLAG_LSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MASK                                              0x0000000080000000
+
+#define RX_MSDU_END_FSE_METADATA_OFFSET                                             0x0000000000000030
+#define RX_MSDU_END_FSE_METADATA_LSB                                                32
+#define RX_MSDU_END_FSE_METADATA_MSB                                                63
+#define RX_MSDU_END_FSE_METADATA_MASK                                               0xffffffff00000000
+
+#define RX_MSDU_END_CCE_METADATA_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_CCE_METADATA_LSB                                                0
+#define RX_MSDU_END_CCE_METADATA_MSB                                                15
+#define RX_MSDU_END_CCE_METADATA_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET                                           0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB                                              16
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB                                              31
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK                                             0x00000000ffff0000
+
+#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET                                        0x0000000000000038
+#define RX_MSDU_END_AGGREGATION_COUNT_LSB                                           32
+#define RX_MSDU_END_AGGREGATION_COUNT_MSB                                           39
+#define RX_MSDU_END_AGGREGATION_COUNT_MASK                                          0x000000ff00000000
+
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET                            0x0000000000000038
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB                               40
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK                              0x0000010000000000
+
+#define RX_MSDU_END_FISA_TIMEOUT_OFFSET                                             0x0000000000000038
+#define RX_MSDU_END_FISA_TIMEOUT_LSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MSB                                                41
+#define RX_MSDU_END_FISA_TIMEOUT_MASK                                               0x0000020000000000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET                                 0x0000000000000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB                                    42
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK                                   0x0000040000000000
+
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB                                            43
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK                                           0x0000080000000000
+
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB                                            44
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK                                           0x0000100000000000
+
+#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET                                         0x0000000000000038
+#define RX_MSDU_END_FLOW_IDX_INVALID_LSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MSB                                            45
+#define RX_MSDU_END_FLOW_IDX_INVALID_MASK                                           0x0000200000000000
+
+#define RX_MSDU_END_CCE_MATCH_OFFSET                                                0x0000000000000038
+#define RX_MSDU_END_CCE_MATCH_LSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MSB                                                   46
+#define RX_MSDU_END_CCE_MATCH_MASK                                                  0x0000400000000000
+
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET                                       0x0000000000000038
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB                                          47
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK                                         0x0000800000000000
+
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET                                     0x0000000000000038
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB                                        48
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB                                        63
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK                                       0xffff000000000000
+
+#define RX_MSDU_END_KEY_ID_OCTET_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_KEY_ID_OCTET_LSB                                                0
+#define RX_MSDU_END_KEY_ID_OCTET_MSB                                                7
+#define RX_MSDU_END_KEY_ID_OCTET_MASK                                               0x00000000000000ff
+
+#define RX_MSDU_END_RESERVED_16A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_16A_LSB                                                8
+#define RX_MSDU_END_RESERVED_16A_MSB                                                31
+#define RX_MSDU_END_RESERVED_16A_MASK                                               0x00000000ffffff00
+
+#define RX_MSDU_END_RESERVED_17A_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17A_LSB                                                32
+#define RX_MSDU_END_RESERVED_17A_MSB                                                37
+#define RX_MSDU_END_RESERVED_17A_MASK                                               0x0000003f00000000
+
+#define RX_MSDU_END_SERVICE_CODE_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_SERVICE_CODE_LSB                                                38
+#define RX_MSDU_END_SERVICE_CODE_MSB                                                46
+#define RX_MSDU_END_SERVICE_CODE_MASK                                               0x00007fc000000000
+
+#define RX_MSDU_END_PRIORITY_VALID_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_PRIORITY_VALID_LSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MSB                                              47
+#define RX_MSDU_END_PRIORITY_VALID_MASK                                             0x0000800000000000
+
+#define RX_MSDU_END_INTRA_BSS_OFFSET                                                0x0000000000000040
+#define RX_MSDU_END_INTRA_BSS_LSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MSB                                                   48
+#define RX_MSDU_END_INTRA_BSS_MASK                                                  0x0001000000000000
+
+#define RX_MSDU_END_DEST_CHIP_ID_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_DEST_CHIP_ID_LSB                                                49
+#define RX_MSDU_END_DEST_CHIP_ID_MSB                                                50
+#define RX_MSDU_END_DEST_CHIP_ID_MASK                                               0x0006000000000000
+
+#define RX_MSDU_END_MULTICAST_ECHO_OFFSET                                           0x0000000000000040
+#define RX_MSDU_END_MULTICAST_ECHO_LSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MSB                                              51
+#define RX_MSDU_END_MULTICAST_ECHO_MASK                                             0x0008000000000000
+
+#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET                                       0x0000000000000040
+#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB                                          52
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK                                         0x0010000000000000
+
+#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET                                        0x0000000000000040
+#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB                                           53
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK                                          0x0020000000000000
+
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET                                     0x0000000000000040
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB                                        54
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_RESERVED_17B_OFFSET                                             0x0000000000000040
+#define RX_MSDU_END_RESERVED_17B_LSB                                                56
+#define RX_MSDU_END_RESERVED_17B_MSB                                                63
+#define RX_MSDU_END_RESERVED_17B_MASK                                               0xff00000000000000
+
+#define RX_MSDU_END_MSDU_LENGTH_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_LENGTH_LSB                                                 0
+#define RX_MSDU_END_MSDU_LENGTH_MSB                                                 13
+#define RX_MSDU_END_MSDU_LENGTH_MASK                                                0x0000000000003fff
+
+#define RX_MSDU_END_STBC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_STBC_LSB                                                        14
+#define RX_MSDU_END_STBC_MSB                                                        14
+#define RX_MSDU_END_STBC_MASK                                                       0x0000000000004000
+
+#define RX_MSDU_END_IPSEC_ESP_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_IPSEC_ESP_LSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MASK                                                  0x0000000000008000
+
+#define RX_MSDU_END_L3_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L3_OFFSET_LSB                                                   16
+#define RX_MSDU_END_L3_OFFSET_MSB                                                   22
+#define RX_MSDU_END_L3_OFFSET_MASK                                                  0x00000000007f0000
+
+#define RX_MSDU_END_IPSEC_AH_OFFSET                                                 0x0000000000000048
+#define RX_MSDU_END_IPSEC_AH_LSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MASK                                                   0x0000000000800000
+
+#define RX_MSDU_END_L4_OFFSET_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_L4_OFFSET_LSB                                                   24
+#define RX_MSDU_END_L4_OFFSET_MSB                                                   31
+#define RX_MSDU_END_L4_OFFSET_MASK                                                  0x00000000ff000000
+
+#define RX_MSDU_END_MSDU_NUMBER_OFFSET                                              0x0000000000000048
+#define RX_MSDU_END_MSDU_NUMBER_LSB                                                 32
+#define RX_MSDU_END_MSDU_NUMBER_MSB                                                 39
+#define RX_MSDU_END_MSDU_NUMBER_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_END_DECAP_FORMAT_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_DECAP_FORMAT_LSB                                                40
+#define RX_MSDU_END_DECAP_FORMAT_MSB                                                41
+#define RX_MSDU_END_DECAP_FORMAT_MASK                                               0x0000030000000000
+
+#define RX_MSDU_END_IPV4_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV4_PROTO_LSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MSB                                                  42
+#define RX_MSDU_END_IPV4_PROTO_MASK                                                 0x0000040000000000
+
+#define RX_MSDU_END_IPV6_PROTO_OFFSET                                               0x0000000000000048
+#define RX_MSDU_END_IPV6_PROTO_LSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MSB                                                  43
+#define RX_MSDU_END_IPV6_PROTO_MASK                                                 0x0000080000000000
+
+#define RX_MSDU_END_TCP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_TCP_PROTO_LSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MSB                                                   44
+#define RX_MSDU_END_TCP_PROTO_MASK                                                  0x0000100000000000
+
+#define RX_MSDU_END_UDP_PROTO_OFFSET                                                0x0000000000000048
+#define RX_MSDU_END_UDP_PROTO_LSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MSB                                                   45
+#define RX_MSDU_END_UDP_PROTO_MASK                                                  0x0000200000000000
+
+#define RX_MSDU_END_IP_FRAG_OFFSET                                                  0x0000000000000048
+#define RX_MSDU_END_IP_FRAG_LSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MSB                                                     46
+#define RX_MSDU_END_IP_FRAG_MASK                                                    0x0000400000000000
+
+#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET                                             0x0000000000000048
+#define RX_MSDU_END_TCP_ONLY_ACK_LSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MSB                                                47
+#define RX_MSDU_END_TCP_ONLY_ACK_MASK                                               0x0000800000000000
+
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB                                           48
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK                                          0x0001000000000000
+
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET                                        0x0000000000000048
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB                                           49
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB                                           50
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK                                          0x0006000000000000
+
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET                                    0x0000000000000048
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB                                       51
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK                                      0x0008000000000000
+
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB                                        52
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK                                       0x0010000000000000
+
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB                                        53
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK                                       0x0020000000000000
+
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET                                     0x0000000000000048
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB                                        54
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK                                       0x0040000000000000
+
+#define RX_MSDU_END_LDPC_OFFSET                                                     0x0000000000000048
+#define RX_MSDU_END_LDPC_LSB                                                        55
+#define RX_MSDU_END_LDPC_MSB                                                        55
+#define RX_MSDU_END_LDPC_MASK                                                       0x0080000000000000
+
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                             0x0000000000000048
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                                56
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                                63
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                               0xff00000000000000
+
+#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_CTAG_CI_LSB                                                0
+#define RX_MSDU_END_VLAN_CTAG_CI_MSB                                                15
+#define RX_MSDU_END_VLAN_CTAG_CI_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_VLAN_STAG_CI_OFFSET                                             0x0000000000000050
+#define RX_MSDU_END_VLAN_STAG_CI_LSB                                                16
+#define RX_MSDU_END_VLAN_STAG_CI_MSB                                                31
+#define RX_MSDU_END_VLAN_STAG_CI_MASK                                               0x00000000ffff0000
+
+#define RX_MSDU_END_PEER_META_DATA_OFFSET                                           0x0000000000000050
+#define RX_MSDU_END_PEER_META_DATA_LSB                                              32
+#define RX_MSDU_END_PEER_META_DATA_MSB                                              63
+#define RX_MSDU_END_PEER_META_DATA_MASK                                             0xffffffff00000000
+
+#define RX_MSDU_END_USER_RSSI_OFFSET                                                0x0000000000000058
+#define RX_MSDU_END_USER_RSSI_LSB                                                   0
+#define RX_MSDU_END_USER_RSSI_MSB                                                   7
+#define RX_MSDU_END_USER_RSSI_MASK                                                  0x00000000000000ff
+
+#define RX_MSDU_END_PKT_TYPE_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_PKT_TYPE_LSB                                                    8
+#define RX_MSDU_END_PKT_TYPE_MSB                                                    11
+#define RX_MSDU_END_PKT_TYPE_MASK                                                   0x0000000000000f00
+
+#define RX_MSDU_END_SGI_OFFSET                                                      0x0000000000000058
+#define RX_MSDU_END_SGI_LSB                                                         12
+#define RX_MSDU_END_SGI_MSB                                                         13
+#define RX_MSDU_END_SGI_MASK                                                        0x0000000000003000
+
+#define RX_MSDU_END_RATE_MCS_OFFSET                                                 0x0000000000000058
+#define RX_MSDU_END_RATE_MCS_LSB                                                    14
+#define RX_MSDU_END_RATE_MCS_MSB                                                    18
+#define RX_MSDU_END_RATE_MCS_MASK                                                   0x000000000007c000
+
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET                                        0x0000000000000058
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB                                           19
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB                                           21
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK                                          0x0000000000380000
+
+#define RX_MSDU_END_RECEPTION_TYPE_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_RECEPTION_TYPE_LSB                                              22
+#define RX_MSDU_END_RECEPTION_TYPE_MSB                                              24
+#define RX_MSDU_END_RECEPTION_TYPE_MASK                                             0x0000000001c00000
+
+#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MIMO_SS_BITMAP_LSB                                              25
+#define RX_MSDU_END_MIMO_SS_BITMAP_MSB                                              30
+#define RX_MSDU_END_MIMO_SS_BITMAP_MASK                                             0x000000007e000000
+
+#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET                                           0x0000000000000058
+#define RX_MSDU_END_MSDU_DONE_COPY_LSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MASK                                             0x0000000080000000
+
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET                                         0x0000000000000058
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB                                            32
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB                                            63
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET                               0x0000000000000060
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB                                  0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB                                  31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK                                 0x00000000ffffffff
+
+#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET                                         0x0000000000000060
+#define RX_MSDU_END_SW_PHY_META_DATA_LSB                                            32
+#define RX_MSDU_END_SW_PHY_META_DATA_MSB                                            63
+#define RX_MSDU_END_SW_PHY_META_DATA_MASK                                           0xffffffff00000000
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET                                0x0000000000000068
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB                                   0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB                                   31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK                                  0x00000000ffffffff
+
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET                                     0x0000000000000068
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB                                        32
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB                                        63
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK                                       0xffffffff00000000
+
+#define RX_MSDU_END_RESERVED_28A_OFFSET                                             0x0000000000000070
+#define RX_MSDU_END_RESERVED_28A_LSB                                                0
+#define RX_MSDU_END_RESERVED_28A_MSB                                                15
+#define RX_MSDU_END_RESERVED_28A_MASK                                               0x000000000000ffff
+
+#define RX_MSDU_END_SA_15_0_OFFSET                                                  0x0000000000000070
+#define RX_MSDU_END_SA_15_0_LSB                                                     16
+#define RX_MSDU_END_SA_15_0_MSB                                                     31
+#define RX_MSDU_END_SA_15_0_MASK                                                    0x00000000ffff0000
+
+#define RX_MSDU_END_SA_47_16_OFFSET                                                 0x0000000000000070
+#define RX_MSDU_END_SA_47_16_LSB                                                    32
+#define RX_MSDU_END_SA_47_16_MSB                                                    63
+#define RX_MSDU_END_SA_47_16_MASK                                                   0xffffffff00000000
+
+#define RX_MSDU_END_FIRST_MPDU_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_FIRST_MPDU_LSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MASK                                                 0x0000000000000001
+
+#define RX_MSDU_END_RESERVED_30A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30A_LSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MASK                                               0x0000000000000002
+
+#define RX_MSDU_END_MCAST_BCAST_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_MCAST_BCAST_LSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MASK                                                0x0000000000000004
+
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK                                        0x0000000000000008
+
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK                                          0x0000000000000010
+
+#define RX_MSDU_END_POWER_MGMT_OFFSET                                               0x0000000000000078
+#define RX_MSDU_END_POWER_MGMT_LSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MASK                                                 0x0000000000000020
+
+#define RX_MSDU_END_NON_QOS_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_NON_QOS_LSB                                                     6
+#define RX_MSDU_END_NON_QOS_MSB                                                     6
+#define RX_MSDU_END_NON_QOS_MASK                                                    0x0000000000000040
+
+#define RX_MSDU_END_NULL_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_NULL_DATA_LSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MASK                                                  0x0000000000000080
+
+#define RX_MSDU_END_MGMT_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MGMT_TYPE_LSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MASK                                                  0x0000000000000100
+
+#define RX_MSDU_END_CTRL_TYPE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_CTRL_TYPE_LSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MASK                                                  0x0000000000000200
+
+#define RX_MSDU_END_MORE_DATA_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MORE_DATA_LSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MASK                                                  0x0000000000000400
+
+#define RX_MSDU_END_EOSP_OFFSET                                                     0x0000000000000078
+#define RX_MSDU_END_EOSP_LSB                                                        11
+#define RX_MSDU_END_EOSP_MSB                                                        11
+#define RX_MSDU_END_EOSP_MASK                                                       0x0000000000000800
+
+#define RX_MSDU_END_A_MSDU_ERROR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_A_MSDU_ERROR_LSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MASK                                               0x0000000000001000
+
+#define RX_MSDU_END_RESERVED_30B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_30B_LSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MASK                                               0x0000000000002000
+
+#define RX_MSDU_END_ORDER_OFFSET                                                    0x0000000000000078
+#define RX_MSDU_END_ORDER_LSB                                                       14
+#define RX_MSDU_END_ORDER_MSB                                                       14
+#define RX_MSDU_END_ORDER_MASK                                                      0x0000000000004000
+
+#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET                                        0x0000000000000078
+#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK                                          0x0000000000008000
+
+#define RX_MSDU_END_OVERFLOW_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_OVERFLOW_ERR_LSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MASK                                               0x0000000000010000
+
+#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK                                            0x0000000000020000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK                                        0x0000000000040000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK                                             0x0000000000080000
+
+#define RX_MSDU_END_SA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_SA_IDX_INVALID_LSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MASK                                             0x0000000000100000
+
+#define RX_MSDU_END_DA_IDX_INVALID_OFFSET                                           0x0000000000000078
+#define RX_MSDU_END_DA_IDX_INVALID_LSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MASK                                             0x0000000000200000
+
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK                                        0x0000000000400000
+
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x0000000000000078
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x0000000000800000
+
+#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET                                         0x0000000000000078
+#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK                                           0x0000000001000000
+
+#define RX_MSDU_END_DIRECTED_OFFSET                                                 0x0000000000000078
+#define RX_MSDU_END_DIRECTED_LSB                                                    25
+#define RX_MSDU_END_DIRECTED_MSB                                                    25
+#define RX_MSDU_END_DIRECTED_MASK                                                   0x0000000002000000
+
+#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_BUFFER_FRAGMENT_LSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MASK                                            0x0000000004000000
+
+#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x0000000000000078
+#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK                                            0x0000000008000000
+
+#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_TKIP_MIC_ERR_LSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MASK                                               0x0000000010000000
+
+#define RX_MSDU_END_DECRYPT_ERR_OFFSET                                              0x0000000000000078
+#define RX_MSDU_END_DECRYPT_ERR_LSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MASK                                                0x0000000020000000
+
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x0000000040000000
+
+#define RX_MSDU_END_FCS_ERR_OFFSET                                                  0x0000000000000078
+#define RX_MSDU_END_FCS_ERR_LSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MASK                                                    0x0000000080000000
+
+#define RX_MSDU_END_RESERVED_31A_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31A_LSB                                                32
+#define RX_MSDU_END_RESERVED_31A_MSB                                                41
+#define RX_MSDU_END_RESERVED_31A_MASK                                               0x000003ff00000000
+
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000000000000078
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB                                         42
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB                                         44
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK                                        0x00001c0000000000
+
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000000000000078
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       45
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x0000200000000000
+
+#define RX_MSDU_END_IFCS_PRESENT_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_IFCS_PRESENT_LSB                                                46
+#define RX_MSDU_END_IFCS_PRESENT_MSB                                                46
+#define RX_MSDU_END_IFCS_PRESENT_MASK                                               0x0000400000000000
+
+#define RX_MSDU_END_RESERVED_31B_OFFSET                                             0x0000000000000078
+#define RX_MSDU_END_RESERVED_31B_LSB                                                47
+#define RX_MSDU_END_RESERVED_31B_MSB                                                62
+#define RX_MSDU_END_RESERVED_31B_MASK                                               0x7fff800000000000
+
+#define RX_MSDU_END_MSDU_DONE_OFFSET                                                0x0000000000000078
+#define RX_MSDU_END_MSDU_DONE_LSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MSB                                                   63
+#define RX_MSDU_END_MSDU_DONE_MASK                                                  0x8000000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_ext_desc_info.h b/hw/wcn8750/v1/rx_msdu_ext_desc_info.h
new file mode 100644
index 000000000000..70bda69ddfec
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_ext_desc_info.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_EXT_DESC_INFO_H_
+#define _RX_MSDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
+
+struct rx_msdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      data_offset                                             : 12,
+                      src_link_id                                             :  3,
+                      reserved_0a                                             :  2;
+#else
+             uint32_t reserved_0a                                             :  2,
+                      src_link_id                                             :  3,
+                      data_offset                                             : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET                     0x00000000
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB                        0
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB                        4
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK                       0x0000001f
+
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET                                   0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB                                      5
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB                                      13
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK                                     0x00003fe0
+
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET                                 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK                                   0x00004000
+
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB                                       15
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB                                       26
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK                                      0x07ff8000
+
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB                                       27
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB                                       29
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK                                      0x38000000
+
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB                                       30
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB                                       31
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK                                      0xc0000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_link.h b/hw/wcn8750/v1/rx_msdu_link.h
new file mode 100644
index 000000000000..c54357dae2ef
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_link.h
@@ -0,0 +1,2051 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+#define NUM_OF_DWORDS_RX_MSDU_LINK 64
+
+struct rx_msdu_link {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+             struct   rx_msdu_details                                           msdu_6;
+             struct   rx_msdu_details                                           msdu_7;
+             struct   rx_msdu_details                                           msdu_8;
+             struct   rx_msdu_details                                           msdu_9;
+             struct   rx_msdu_details                                           msdu_10;
+             struct   rx_msdu_details                                           msdu_11;
+             struct   rx_msdu_details                                           msdu_12;
+             struct   rx_msdu_details                                           msdu_13;
+             struct   rx_msdu_details                                           msdu_14;
+#endif
+};
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET          0x00000004
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB             0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK            0xffffffff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET         0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB            0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB            7
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK           0x000000ff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET     0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB        8
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB        11
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK       0x00000f00
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET          0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB             12
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK            0xfffff000
+
+#define RX_MSDU_LINK_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_MSDU_LINK_RESERVED_3A_LSB                                                0
+#define RX_MSDU_LINK_RESERVED_3A_MSB                                                31
+#define RX_MSDU_LINK_RESERVED_3A_MASK                                               0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000010
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000014
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000018
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000001c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000020
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000024
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000030
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000034
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000040
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000044
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000050
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000054
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000060
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000064
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000070
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000074
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000080
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000084
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000088
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000008c
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000090
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000094
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000098
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000009c
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x000000a0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x000000a4
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x000000a8
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x000000ac
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000b0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000b4
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000b8
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000bc
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000c0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000c4
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000c8
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000cc
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000d0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000d4
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000d8
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000dc
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000e0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000e4
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000e8
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000ec
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET       0x000000f0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB          0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET      0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB         0
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB         7
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET  0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB     8
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB     11
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK    0x00000f00
+
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET       0x000000f4
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB          12
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB          31
+#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK         0xfffff000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x000000f8
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET      0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB         5
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB         13
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK        0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET    0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB       14
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK      0x00004000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB          15
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB          26
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK         0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB          27
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB          29
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK         0x38000000
+
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET       0x000000fc
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB          30
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB          31
+#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK         0xc0000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_msdu_start.h b/hw/wcn8750/v1/rx_msdu_start.h
new file mode 100644
index 000000000000..e1e99c027c85
--- /dev/null
+++ b/hw/wcn8750/v1/rx_msdu_start.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_START 10
+
+#define NUM_OF_QWORDS_RX_MSDU_START 5
+
+struct rx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      rate_mcs                                                :  5,
+                      reserved_0                                              :  2,
+                      phy_ppdu_id                                             : 16;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      reserved_5a                                             :  4,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  2,
+                      rate_mcs                                                :  5,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t mimo_ss_bitmap                                          :  8,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      reserved_5a                                             :  4,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+#endif
+};
+
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x0000000000000000
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x0000000000000003
+
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x0000000000000000
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x00000000000001fc
+
+#define RX_MSDU_START_RATE_MCS_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_RATE_MCS_LSB                                                  9
+#define RX_MSDU_START_RATE_MCS_MSB                                                  13
+#define RX_MSDU_START_RATE_MCS_MASK                                                 0x0000000000003e00
+
+#define RX_MSDU_START_RESERVED_0_OFFSET                                             0x0000000000000000
+#define RX_MSDU_START_RESERVED_0_LSB                                                14
+#define RX_MSDU_START_RESERVED_0_MSB                                                15
+#define RX_MSDU_START_RESERVED_0_MASK                                               0x000000000000c000
+
+#define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
+#define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
+#define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0x00000000ffff0000
+
+#define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x0000000000000000
+#define RX_MSDU_START_MSDU_LENGTH_LSB                                               32
+#define RX_MSDU_START_MSDU_LENGTH_MSB                                               45
+#define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff00000000
+
+#define RX_MSDU_START_STBC_OFFSET                                                   0x0000000000000000
+#define RX_MSDU_START_STBC_LSB                                                      46
+#define RX_MSDU_START_STBC_MSB                                                      46
+#define RX_MSDU_START_STBC_MASK                                                     0x0000400000000000
+
+#define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_IPSEC_ESP_LSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MSB                                                 47
+#define RX_MSDU_START_IPSEC_ESP_MASK                                                0x0000800000000000
+
+#define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L3_OFFSET_LSB                                                 48
+#define RX_MSDU_START_L3_OFFSET_MSB                                                 54
+#define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f000000000000
+
+#define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x0000000000000000
+#define RX_MSDU_START_IPSEC_AH_LSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MSB                                                  55
+#define RX_MSDU_START_IPSEC_AH_MASK                                                 0x0080000000000000
+
+#define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x0000000000000000
+#define RX_MSDU_START_L4_OFFSET_LSB                                                 56
+#define RX_MSDU_START_L4_OFFSET_MSB                                                 63
+#define RX_MSDU_START_L4_OFFSET_MASK                                                0xff00000000000000
+
+#define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x0000000000000008
+#define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
+#define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
+#define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x00000000000000ff
+
+#define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
+#define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
+#define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x0000000000000300
+
+#define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV4_PROTO_LSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MASK                                               0x0000000000000400
+
+#define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x0000000000000008
+#define RX_MSDU_START_IPV6_PROTO_LSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MASK                                               0x0000000000000800
+
+#define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_TCP_PROTO_LSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MASK                                                0x0000000000001000
+
+#define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x0000000000000008
+#define RX_MSDU_START_UDP_PROTO_LSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MASK                                                0x0000000000002000
+
+#define RX_MSDU_START_IP_FRAG_OFFSET                                                0x0000000000000008
+#define RX_MSDU_START_IP_FRAG_LSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MASK                                                  0x0000000000004000
+
+#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x0000000000000008
+#define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x0000000000008000
+
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x0000000000010000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x0000000000060000
+
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x0000000000000008
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x0000000000080000
+
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x0000000000100000
+
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x0000000000200000
+
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x0000000000400000
+
+#define RX_MSDU_START_LDPC_OFFSET                                                   0x0000000000000008
+#define RX_MSDU_START_LDPC_LSB                                                      23
+#define RX_MSDU_START_LDPC_MSB                                                      23
+#define RX_MSDU_START_LDPC_MASK                                                     0x0000000000800000
+
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x0000000000000008
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0x00000000ff000000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000000000008
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      32
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      63
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff00000000
+
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x0000000000000010
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_USER_RSSI_OFFSET                                              0x0000000000000010
+#define RX_MSDU_START_USER_RSSI_LSB                                                 32
+#define RX_MSDU_START_USER_RSSI_MSB                                                 39
+#define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff00000000
+
+#define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x0000000000000010
+#define RX_MSDU_START_PKT_TYPE_LSB                                                  40
+#define RX_MSDU_START_PKT_TYPE_MSB                                                  43
+#define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f0000000000
+
+#define RX_MSDU_START_SGI_OFFSET                                                    0x0000000000000010
+#define RX_MSDU_START_SGI_LSB                                                       44
+#define RX_MSDU_START_SGI_MSB                                                       45
+#define RX_MSDU_START_SGI_MASK                                                      0x0000300000000000
+
+#define RX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define RX_MSDU_START_RESERVED_5A_LSB                                               46
+#define RX_MSDU_START_RESERVED_5A_MSB                                               49
+#define RX_MSDU_START_RESERVED_5A_MASK                                              0x0003c00000000000
+
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x0000000000000010
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         50
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         52
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c000000000000
+
+#define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_RECEPTION_TYPE_LSB                                            53
+#define RX_MSDU_START_RECEPTION_TYPE_MSB                                            55
+#define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e0000000000000
+
+#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x0000000000000010
+#define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            56
+#define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            63
+#define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff00000000000000
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000020
+#define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
+#define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
+#define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0x00000000ffffffff
+
+#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              32
+#define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              47
+#define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff00000000
+
+#define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x0000000000000020
+#define RX_MSDU_START_VLAN_STAG_CI_LSB                                              48
+#define RX_MSDU_START_VLAN_STAG_CI_MSB                                              63
+#define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_ack_report.h b/hw/wcn8750/v1/rx_ppdu_ack_report.h
new file mode 100644
index 000000000000..345b14ea4255
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_ack_report.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_ACK_REPORT_H_
+#define _RX_PPDU_ACK_REPORT_H_
+
+#include "ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2
+
+#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1
+
+struct rx_ppdu_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             struct   ack_report                                                ack_report_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB           0
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB           3
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK          0x000000000000000f
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET                0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB                   4
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB                   7
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK                  0x00000000000000f0
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET                        0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK                          0x0000000000000100
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET                       0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB                          9
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB                          15
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK                         0x000000000000fe00
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET                  0x0000000000000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB                     16
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB                     31
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK                    0x00000000ffff0000
+
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET                                     0x0000000000000000
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB                                        32
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB                                        63
+#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_end_user_stats.h b/hw/wcn8750/v1/rx_ppdu_end_user_stats.h
new file mode 100644
index 000000000000..51db8f35a6ab
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_end_user_stats.h
@@ -0,0 +1,679 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15
+
+struct rx_ppdu_end_user_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t sta_full_aid                                            : 13,
+                      mcs                                                     :  5,
+                      nss                                                     :  3,
+                      expected_response_ack_or_ba                             :  1,
+                      reserved_1a                                             : 10;
+             uint32_t sw_peer_id                                              : 16,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      fw2rxdma1_buf_source_used                               :  1;
+             uint32_t mpdu_cnt_fcs_ok                                         : 11,
+                      frame_control_info_valid                                :  1,
+                      qos_control_info_valid                                  :  1,
+                      ht_control_info_valid                                   :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_null_valid                              :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      reserved_3a                                             :  1,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3b                                             :  7;
+             uint32_t ast_index                                               : 16,
+                      frame_control_field                                     : 16;
+             uint32_t first_data_seq_ctrl                                     : 16,
+                      qos_control_field                                       : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t udp_msdu_count                                          : 16,
+                      tcp_msdu_count                                          : 16;
+             uint32_t other_msdu_count                                        : 16,
+                      tcp_ack_msdu_count                                      : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_bitmap                            : 16,
+                      received_qos_data_tid_eosp_bitmap                       : 16;
+             uint32_t qosctrl_15_8_tid0                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid3                                       :  8;
+             uint32_t qosctrl_15_8_tid4                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid7                                       :  8;
+             uint32_t qosctrl_15_8_tid8                                       :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid11                                      :  8;
+             uint32_t qosctrl_15_8_tid12                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid15                                      :  8;
+             uint32_t mpdu_ok_byte_count                                      : 25,
+                      ampdu_delim_ok_count_6_0                                :  7;
+             uint32_t ampdu_delim_err_count                                   : 25,
+                      ampdu_delim_ok_count_13_7                               :  7;
+             uint32_t mpdu_err_byte_count                                     : 25,
+                      ampdu_delim_ok_count_20_14                              :  7;
+             uint32_t non_consecutive_delimiter_err                           : 16,
+                      retried_msdu_count                                      : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      frame_control_info_null_valid                           :  1,
+                      frame_control_field_null                                : 16,
+                      retried_mpdu_count                                      : 11,
+                      reserved_23a                                            :  3;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_24a                                            :  4,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mcast_bcast                                             :  1,
+                      frame_control_field_mgmt_ctrl                           : 16;
+             uint32_t user_ppdu_len                                           : 24,
+                      reserved_25a                                            :  8;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t mac_addr_ad2_47_32                                      : 16,
+                      amsdu_msdu_count                                        : 16;
+             uint32_t non_amsdu_msdu_count                                    : 16,
+                      ucast_msdu_count                                        : 16;
+             uint32_t bcast_msdu_count                                        : 16,
+                      mcast_bcast_msdu_count                                  : 16;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t reserved_1a                                             : 10,
+                      expected_response_ack_or_ba                             :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5,
+                      sta_full_aid                                            : 13;
+             uint32_t fw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma2_buf_source_used                               :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      fw2rxdma0_buf_source_used                               :  1,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_3b                                             :  7,
+                      ht_control_field_pkt_type                               :  4,
+                      reserved_3a                                             :  1,
+                      rxdma2fwreo_1_ring_used                                 :  1,
+                      rxdma2fwreo_0_ring_used                                 :  1,
+                      rxdma2fw1_ring_used                                     :  1,
+                      rxdma2fw0_ring_used                                     :  1,
+                      ht_control_info_null_valid                              :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_valid                                   :  1,
+                      qos_control_info_valid                                  :  1,
+                      frame_control_info_valid                                :  1,
+                      mpdu_cnt_fcs_ok                                         : 11;
+             uint32_t frame_control_field                                     : 16,
+                      ast_index                                               : 16;
+             uint32_t qos_control_field                                       : 16,
+                      first_data_seq_ctrl                                     : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t tcp_msdu_count                                          : 16,
+                      udp_msdu_count                                          : 16;
+             uint32_t tcp_ack_msdu_count                                      : 16,
+                      other_msdu_count                                        : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_eosp_bitmap                       : 16,
+                      received_qos_data_tid_bitmap                            : 16;
+             uint32_t qosctrl_15_8_tid3                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid0                                       :  8;
+             uint32_t qosctrl_15_8_tid7                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid4                                       :  8;
+             uint32_t qosctrl_15_8_tid11                                      :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid8                                       :  8;
+             uint32_t qosctrl_15_8_tid15                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid12                                      :  8;
+             uint32_t ampdu_delim_ok_count_6_0                                :  7,
+                      mpdu_ok_byte_count                                      : 25;
+             uint32_t ampdu_delim_ok_count_13_7                               :  7,
+                      ampdu_delim_err_count                                   : 25;
+             uint32_t ampdu_delim_ok_count_20_14                              :  7,
+                      mpdu_err_byte_count                                     : 25;
+             uint32_t retried_msdu_count                                      : 16,
+                      non_consecutive_delimiter_err                           : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t reserved_23a                                            :  3,
+                      retried_mpdu_count                                      : 11,
+                      frame_control_field_null                                : 16,
+                      frame_control_info_null_valid                           :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t frame_control_field_mgmt_ctrl                           : 16,
+                      mcast_bcast                                             :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      reserved_24a                                            :  4,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_25a                                            :  8,
+                      user_ppdu_len                                           : 24;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t amsdu_msdu_count                                        : 16,
+                      mac_addr_ad2_47_32                                      : 16;
+             uint32_t ucast_msdu_count                                        : 16,
+                      non_amsdu_msdu_count                                    : 16;
+             uint32_t mcast_bcast_msdu_count                                  : 16,
+                      bcast_msdu_count                                        : 16;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK  0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB          9
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB          15
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK         0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET      0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB         16
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB         31
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK        0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET                                  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB                                     32
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB                                     44
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK                                    0x00001fff00000000
+
+#define RX_PPDU_END_USER_STATS_MCS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_MCS_LSB                                              45
+#define RX_PPDU_END_USER_STATS_MCS_MSB                                              49
+#define RX_PPDU_END_USER_STATS_MCS_MASK                                             0x0003e00000000000
+
+#define RX_PPDU_END_USER_STATS_NSS_OFFSET                                           0x0000000000000000
+#define RX_PPDU_END_USER_STATS_NSS_LSB                                              50
+#define RX_PPDU_END_USER_STATS_NSS_MSB                                              52
+#define RX_PPDU_END_USER_STATS_NSS_MASK                                             0x001c000000000000
+
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB                      53
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK                     0x0020000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET                                   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB                                      54
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK                                     0xffc0000000000000
+
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET                                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB                                       0
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB                                       15
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK                                      0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET                              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB                                 16
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB                                 26
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK                                0x0000000007ff0000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000008000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB                        28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK                       0x0000000010000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000020000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB                        30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK                       0x0000000040000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB                        31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK                       0x0000000080000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET                               0x0000000000000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB                                  32
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB                                  42
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK                                 0x000007ff00000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB                         43
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK                        0x0000080000000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET                        0x0000000000000008
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB                           44
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK                          0x0000100000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET                         0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB                            45
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK                           0x0000200000000000
+
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET              0x0000000000000008
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB                 46
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK                0x0000400000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET                    0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB                       47
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK                      0x0000800000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB                              48
+#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK                             0x0001000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET                           0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB                              49
+#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK                             0x0002000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB                          50
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK                         0x0004000000000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET                       0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB                          51
+#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK                         0x0008000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB                                      52
+#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK                                     0x0010000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB                        53
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB                        56
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK                       0x01e0000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET                                   0x0000000000000008
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB                                      57
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB                                      63
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK                                     0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET                                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB                                        0
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB                                        15
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK                                       0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB                              16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB                              31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK                             0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET                           0x0000000000000010
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB                              32
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB                              47
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK                             0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET                             0x0000000000000010
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK                               0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET                              0x0000000000000018
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB                                 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB                                 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET                            0x0000000000000018
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB                               32
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB                               63
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK                              0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET                           0x0000000000000020
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB                              0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB                              31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK                             0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB                                   32
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB                                   47
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK                                  0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET                                0x0000000000000020
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB                                   48
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB                                   63
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK                                  0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET                              0x0000000000000028
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB                                 0
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB                                 15
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK                                0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET                            0x0000000000000028
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET                     0x0000000000000028
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB                        32
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB                        63
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET                  0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB                     0
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB                     15
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK                    0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB                16
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB                31
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK               0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB                                48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB                                55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK                               0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET                             0x0000000000000030
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB                                56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB                                63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK                               0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK                               0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK                               0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB                                23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK                               0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB                                24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK                               0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB                                32
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB                                39
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK                               0x000000ff00000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET                             0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB                                40
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB                                47
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK                               0x0000ff0000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB                               48
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB                               55
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK                              0x00ff000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET                            0x0000000000000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB                               56
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB                               63
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK                              0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB                               0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB                               7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK                              0x00000000000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB                               8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB                               15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK                              0x000000000000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB                               16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB                               23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK                              0x0000000000ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB                               24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB                               31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK                              0x00000000ff000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET                            0x0000000000000040
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB                               32
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB                               56
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK                              0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET                      0x0000000000000040
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB                         57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB                         63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK                        0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET                         0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB                            0
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB                            24
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK                           0x0000000001ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET                     0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB                        25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB                        31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK                       0x00000000fe000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET                           0x0000000000000048
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB                              32
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB                              56
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK                             0x01ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET                    0x0000000000000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB                       57
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB                       63
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK                      0xfe00000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET                 0x0000000000000050
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB                    0
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB                    15
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK                   0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET                            0x0000000000000050
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK                              0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET                         0x0000000000000050
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB                            32
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB                            63
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK                           0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB                    0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB                    31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK                   0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                   0x0000000000000058
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                      32
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                     0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET                 0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB                    33
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK                   0x0000000200000000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET                      0x0000000000000058
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB                         34
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB                         49
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK                        0x0003fffc00000000
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET                            0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB                               50
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB                               60
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK                              0x1ffc000000000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET                                  0x0000000000000058
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB                                     61
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK                                    0xe000000000000000
+
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                    0
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                    1
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                   0x0000000000000003
+
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET                             0x0000000000000060
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB                                2
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB                                8
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK                               0x00000000000001fc
+
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB                                     9
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB                                     12
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK                                    0x0000000000001e00
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK              0x0000000000002000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET                            0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK                              0x0000000000004000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET                                   0x0000000000000060
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK                                     0x0000000000008000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB                    16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB                    31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK                   0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET                                 0x0000000000000060
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB                                    32
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB                                    55
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK                                   0x00ffffff00000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET                                  0x0000000000000060
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB                                     56
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB                                     63
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK                                    0xff00000000000000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET                             0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB                                0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB                                31
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK                               0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET                            0x0000000000000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB                               32
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB                               47
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK                              0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET                              0x0000000000000068
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB                                 48
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB                                 63
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK                                0xffff000000000000
+
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET                          0x0000000000000070
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB                             0
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB                             15
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK                            0x000000000000ffff
+
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB                                 16
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB                                 31
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK                                0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET                              0x0000000000000070
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB                                 32
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB                                 47
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK                                0x0000ffff00000000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET                        0x0000000000000070
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB                           48
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB                           63
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK                          0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h b/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 000000000000..0a11202db481
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
+
+#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4
+
+struct rx_ppdu_end_user_stats_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      reserved_7a                                             : 31;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t reserved_7a                                             : 31,
+                      corrupted_due_to_fifo_delay                             :  1;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET   0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB      9
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB      15
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK     0x000000000000fe00
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET  0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB     16
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB     31
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK    0x00000000ffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET                       0x0000000000000000
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB                          32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB                          63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK                         0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET                      0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB                         0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB                         31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK                        0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET                     0x0000000000000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET                     0x0000000000000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB                        32
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB                        63
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK                       0xffffffff00000000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET                     0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK                       0x00000000ffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                  32
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                 0x0000000100000000
+
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET                               0x0000000000000018
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB                                  33
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB                                  63
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK                                 0xfffffffe00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_no_ack_report.h b/hw/wcn8750/v1/rx_ppdu_no_ack_report.h
new file mode 100644
index 000000000000..d9c54c04df32
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_no_ack_report.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_NO_ACK_REPORT_H_
+#define _RX_PPDU_NO_ACK_REPORT_H_
+
+#include "no_ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
+
+#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2
+
+struct rx_ppdu_no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   no_ack_report                                             no_ack_report_details;
+#else
+             struct   no_ack_report                                             no_ack_report_details;
+#endif
+};
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET   0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB      0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB      3
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK     0x000000000000000f
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB          4
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB          7
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK         0x00000000000000f0
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET       0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB          8
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB          15
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK         0x000000000000ff00
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET            0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB               16
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB               31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK              0x00000000ffff0000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET         0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB            32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB            55
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK           0x00ffffff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET      0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB         56
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK        0x0100000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET               0x0000000000000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB                  61
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK                 0xe000000000000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB                  24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK                 0x00000000ff000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET               0x0000000000000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB                  44
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB                  63
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK                 0xfffff00000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_start.h b/hw/wcn8750/v1/rx_ppdu_start.h
new file mode 100644
index 000000000000..19765eb4409b
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_start.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+
+#define NUM_OF_DWORDS_RX_PPDU_START 6
+
+#define NUM_OF_QWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      preamble_time_to_rxframe                                :  8,
+                      reserved_0a                                             :  8;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      preamble_time_to_rxframe                                :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PPDU_START_PHY_PPDU_ID_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_PHY_PPDU_ID_LSB                                               0
+#define RX_PPDU_START_PHY_PPDU_ID_MSB                                               15
+#define RX_PPDU_START_PHY_PPDU_ID_MASK                                              0x000000000000ffff
+
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET                               0x0000000000000000
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB                                  16
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB                                  23
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK                                 0x0000000000ff0000
+
+#define RX_PPDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define RX_PPDU_START_RESERVED_0A_LSB                                               24
+#define RX_PPDU_START_RESERVED_0A_MSB                                               31
+#define RX_PPDU_START_RESERVED_0A_MASK                                              0x00000000ff000000
+
+#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET                                       0x0000000000000000
+#define RX_PPDU_START_SW_PHY_META_DATA_LSB                                          32
+#define RX_PPDU_START_SW_PHY_META_DATA_MSB                                          63
+#define RX_PPDU_START_SW_PHY_META_DATA_MASK                                         0xffffffff00000000
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0x00000000ffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000000000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                32
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                63
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff00000000
+
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET                               0x0000000000000010
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB                                  0
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB                                  31
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK                                 0x00000000ffffffff
+
+#define RX_PPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000010
+#define RX_PPDU_START_TLV64_PADDING_LSB                                             32
+#define RX_PPDU_START_TLV64_PADDING_MSB                                             63
+#define RX_PPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_ppdu_start_user_info.h b/hw/wcn8750/v1/rx_ppdu_start_user_info.h
new file mode 100644
index 000000000000..16d3bb33edb4
--- /dev/null
+++ b/hw/wcn8750/v1/rx_ppdu_start_user_info.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8
+
+#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4
+
+struct rx_ppdu_start_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB           0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB           15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK          0x000000000000ffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET          0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB             16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB             23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK            0x0000000000ff0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB              24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB              27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK             0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET               0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                 0x0000000010000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB        29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB        31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK       0x00000000e0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET           0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB              32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB              36
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK             0x0000001f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                   38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                  0x0000006000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET     0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB        40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB        47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK       0x0000ff0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET  0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB     48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB     50
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK    0x0007000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET        0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB           51
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK          0x00f8000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB   63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK  0xff00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK          0x0000000000000002
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB             2
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB             3
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK            0x000000000000000c
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB             4
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB             5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK            0x0000000000000030
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET          0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB             6
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB             7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK            0x00000000000000c0
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                   8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                   10
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                  0x0000000000000700
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET      0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB         11
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB         13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK        0x0000000000003800
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET            0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK              0x0000000000004000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET               0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                 0x0000000000008000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB          16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB          19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK         0x00000000000f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB          20
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB          23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK         0x0000000000f00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB          24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB          27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK         0x000000000f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET       0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB          28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB          31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK         0x00000000f0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB   32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB   37
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK  0x0000003f00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB           38
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB           39
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK          0x000000c000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB   40
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB   45
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK  0x00003f0000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB           46
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB           47
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK          0x0000c00000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB   48
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB   53
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK  0x003f000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB           54
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB           55
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK          0x00c0000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB   56
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB   61
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK  0x3f00000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET   0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB      62
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB      62
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK     0x4000000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET        0x0000000000000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB           63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB           63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK          0x8000000000000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET  0x0000000000000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK    0xffffffff00000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK    0x00000000ffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET  0x0000000000000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB     32
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB     63
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK    0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_preamble.h b/hw/wcn8750/v1/rx_preamble.h
new file mode 100644
index 000000000000..807463753865
--- /dev/null
+++ b/hw/wcn8750/v1/rx_preamble.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_PREAMBLE_H_
+#define _RX_PREAMBLE_H_
+
+#define NUM_OF_DWORDS_RX_PREAMBLE 2
+
+#define NUM_OF_QWORDS_RX_PREAMBLE 1
+
+struct rx_preamble {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      pkt_type                                                :  4,
+                      direction                                               :  1,
+                      reserved_0a                                             : 21;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 21,
+                      direction                                               :  1,
+                      pkt_type                                                :  4,
+                      num_users                                               :  6;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_PREAMBLE_NUM_USERS_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_NUM_USERS_LSB                                                   0
+#define RX_PREAMBLE_NUM_USERS_MSB                                                   5
+#define RX_PREAMBLE_NUM_USERS_MASK                                                  0x000000000000003f
+
+#define RX_PREAMBLE_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define RX_PREAMBLE_PKT_TYPE_LSB                                                    6
+#define RX_PREAMBLE_PKT_TYPE_MSB                                                    9
+#define RX_PREAMBLE_PKT_TYPE_MASK                                                   0x00000000000003c0
+
+#define RX_PREAMBLE_DIRECTION_OFFSET                                                0x0000000000000000
+#define RX_PREAMBLE_DIRECTION_LSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MASK                                                  0x0000000000000400
+
+#define RX_PREAMBLE_RESERVED_0A_OFFSET                                              0x0000000000000000
+#define RX_PREAMBLE_RESERVED_0A_LSB                                                 11
+#define RX_PREAMBLE_RESERVED_0A_MSB                                                 31
+#define RX_PREAMBLE_RESERVED_0A_MASK                                                0x00000000fffff800
+
+#define RX_PREAMBLE_TLV64_PADDING_OFFSET                                            0x0000000000000000
+#define RX_PREAMBLE_TLV64_PADDING_LSB                                               32
+#define RX_PREAMBLE_TLV64_PADDING_MSB                                               63
+#define RX_PREAMBLE_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_response_required_info.h b/hw/wcn8750/v1/rx_response_required_info.h
new file mode 100644
index 000000000000..e6ee112bb1ac
--- /dev/null
+++ b/hw/wcn8750/v1/rx_response_required_info.h
@@ -0,0 +1,764 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
+#define _RX_RESPONSE_REQUIRED_INFO_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16
+
+#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8
+
+struct rx_response_required_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      su_or_uplink_mu_reception                               :  1,
+                      trigger_frame_received                                  :  1,
+                      __reserved_g_0012                                                  :  2,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      mac_security                                            :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2;
+             uint32_t general_frame_control                                   : 16,
+                      second_frame_control                                    : 16;
+             uint32_t duration                                                : 16,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      sgi                                                     :  2,
+                      stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      ampdu                                                   :  1,
+                      rts_ta_grp_bit                                          :  1;
+             uint32_t ctrl_frame_soliciting_resp                              :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      service_dynamic                                         :  1,
+                      m_pkt                                                   :  1,
+                      sta_partial_aid                                         : 12,
+                      group_id                                                :  6,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      response_indication                                     :  2,
+                      ndp_indication                                          :  1,
+                      ndp_frame_type                                          :  3,
+                      second_frame_control_valid                              :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      vht_ack                                                 :  1;
+             uint32_t sta_aid                                                 : 11,
+                      interference                                            :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      ll_traffic_indication                                   :  1,
+                      reserved_4a                                             :  2,
+                      ack_id_ext                                              : 10,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             uint32_t response_sta_count                                      :  7,
+                      __reserved_g_0086                                                 :  1,
+                      blackout_details_en                                     :  1,
+                      reserved                                                :  2,
+                      ht_vht_sig_cbw                                          :  3,
+                      cts_cbw                                                 :  3,
+                      response_ack_count                                      :  7,
+                      response_assoc_ack_count                                :  7,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t response_ba32_count                                     :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba256_count                                    :  7,
+                      multi_tid                                               :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      emlsr_main_tlv_if                                       :  1;
+             uint32_t sw_response_frame_length                                : 16,
+                      response_ba512_count                                    :  7,
+                      response_ba1024_count                                   :  7,
+                      reserved_7a                                             :  2;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      ftm_fields_valid                                        :  1,
+                      ftm_pe_nss                                              :  3,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_content                                          :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_chain_csd_en                                     :  1;
+             uint32_t dot11ax_response_rate_source                            :  8,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      sw_peer_id                                              : 16;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      force_extra_symbol                                      :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      reserved_13a                                            :  3,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t he_a_control_response_time                              : 12,
+                      reserved_after_struct16                                 :  4;
+             uint32_t dso_primary20_index_select                              :  4,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      pad_duration                                            :  5,
+                      q2q_mba                                                 :  1,
+                      reserved_15a                                            :  6;
+#else
+             uint32_t wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      mac_security                                            :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      __reserved_g_0012                                                  :  2,
+                      trigger_frame_received                                  :  1,
+                      su_or_uplink_mu_reception                               :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t second_frame_control                                    : 16,
+                      general_frame_control                                   : 16;
+             uint32_t rts_ta_grp_bit                                          :  1,
+                      ampdu                                                   :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      duration                                                : 16;
+             uint32_t vht_ack                                                 :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      second_frame_control_valid                              :  1,
+                      ndp_frame_type                                          :  3,
+                      ndp_indication                                          :  1,
+                      response_indication                                     :  2,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 12,
+                      m_pkt                                                   :  1,
+                      service_dynamic                                         :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      ctrl_frame_soliciting_resp                              :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      ack_id_ext                                              : 10,
+                      reserved_4a                                             :  2,
+                      ll_traffic_indication                                   :  1,
+                      ects_as_tb_ppdu                                         :  1,
+                      interference                                            :  1,
+                      sta_aid                                                 : 11;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      response_assoc_ack_count                                :  7,
+                      response_ack_count                                      :  7,
+                      cts_cbw                                                 :  3,
+                      ht_vht_sig_cbw                                          :  3,
+                      reserved                                                :  2,
+                      blackout_details_en                                     :  1,
+                      __reserved_g_0086                                                 :  1,
+                      response_sta_count                                      :  7;
+             uint32_t emlsr_main_tlv_if                                       :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      multi_tid                                               :  1,
+                      response_ba256_count                                    :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba32_count                                     :  7;
+             uint32_t reserved_7a                                             :  2,
+                      response_ba1024_count                                   :  7,
+                      response_ba512_count                                    :  7,
+                      sw_response_frame_length                                : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ftm_pe_chain_csd_en                                     :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_content                                          :  1,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_nss                                              :  3,
+                      ftm_fields_valid                                        :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t sw_peer_id                                              : 16,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      dot11ax_response_rate_source                            :  8;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_13a                                            :  3,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      force_extra_symbol                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_after_struct16                                 :  4,
+                      he_a_control_response_time                              : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t reserved_15a                                            :  6,
+                      q2q_mba                                                 :  1,
+                      pad_duration                                            :  5,
+                      dso_freq_subband_channel_bonding_mask                   : 16,
+                      dso_primary20_index_select                              :  4;
+#endif
+};
+
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET                                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK                                  0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK                    0x0000000000010000
+
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK                       0x0000000000020000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET                               0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK                                 0x0000000000400000
+
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK                     0x0000000000800000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK                        0x0000000001000000
+
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET                   0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK                     0x0000000002000000
+
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET                0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK                  0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                     0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK                       0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET                                  0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB                                     30
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB                                     31
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK                                    0x00000000c0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET                      0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB                         32
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB                         47
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK                        0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET                       0x0000000000000000
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB                          63
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK                         0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB                                      0
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB                                      15
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK                                     0x000000000000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB                                      16
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB                                      19
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK                                     0x00000000000f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK                          0x0000000000100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB                                      21
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB                                      25
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK                                     0x0000000003e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET                                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB                                           26
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB                                           27
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK                                          0x000000000c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK                                         0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET                                       0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB                                          29
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK                                         0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB                                         30
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK                                        0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK                               0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK                   0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET                0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB                               34
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK                              0x0000000400000000
+
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET                                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB                                         35
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK                                        0x0000000800000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET                            0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB                               36
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB                               47
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK                              0x0000fff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET                                   0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB                                      48
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB                                      53
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK                                     0x003f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET                         0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB                            54
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK                           0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET                        0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB                           55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB                           56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK                          0x0180000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB                                57
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK                               0x0200000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET                             0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB                                58
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB                                60
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK                               0x1c00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET                 0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB                    61
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK                   0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET                      0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB                         62
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK                        0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB                                       63
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK                                      0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB                                       0
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB                                       10
+#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK                                      0x00000000000007ff
+
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET                               0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB                                  11
+#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK                                 0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET                            0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB                               12
+#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK                              0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET                      0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB                         13
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB                         13
+#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK                        0x0000000000002000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB                                   14
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK                                  0x000000000000c000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET                                 0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB                                    25
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK                                   0x0000000003ff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB                                       26
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB                                       28
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK                                      0x000000001c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET                                0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB                                   29
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK                                  0x00000000e0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB                            32
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB                            38
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK                           0x0000007f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET                        0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB                           40
+#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK                          0x0000010000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET                                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB                                      41
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB                                      42
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK                                     0x0000060000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET                             0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB                                43
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB                                45
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK                               0x0000380000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET                                    0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB                                       46
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB                                       48
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK                                      0x0001c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET                         0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB                            55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK                           0x00fe000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET                   0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB                      56
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB                      62
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK                     0x7f00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET                     0x0000000000000010
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB                        63
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK                       0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB                           0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB                           6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK                          0x000000000000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET                        0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB                           7
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB                           13
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK                          0x0000000000003f80
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB                          14
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB                          20
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK                         0x00000000001fc000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB                          21
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB                          27
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK                         0x000000000fe00000
+
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET                                  0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK                                    0x0000000010000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                  0x0000000020000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET                         0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK                           0x0000000040000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET                          0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK                            0x0000000080000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                   0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                      32
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                      47
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                     0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET                       0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB                          48
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB                          54
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK                         0x007f000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET                      0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB                         55
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB                         61
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK                        0x3f80000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET                                0x0000000000000018
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB                                   62
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB                                   63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK                                  0xc000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB                                    0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK                                   0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET                                0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB                                   32
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB                                   47
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK                                  0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET                                 0x0000000000000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB                                    48
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB                                    63
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK                                   0xffff000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET                                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK                                  0x00000000ffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET         0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB            32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK           0x0000000100000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                   33
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                  0x0000000200000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET              0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                 34
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                 39
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                0x000000fc00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                40
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                43
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK               0x00000f0000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                   0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                      44
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                      45
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                     0x0000300000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                  0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                     46
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                     47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                    0x0000c00000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET                    0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB                       48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK                      0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET                       0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB                          49
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK                         0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB           50
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK          0x0004000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  51
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  54
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0078000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB                              55
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK                             0x0080000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET                                 0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB                                    56
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB                                    58
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK                                   0x0700000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET                            0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB                               59
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB                               60
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK                              0x1800000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET                             0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB                                61
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK                               0x2000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET                           0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB                              62
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK                             0x4000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET                        0x0000000000000028
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB                           63
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK                          0x8000000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB                  0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB                  7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK                 0x00000000000000ff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB              8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB              15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK             0x000000000000ff00
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET                                 0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK                                   0x00000000ffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                    0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                       32
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                       47
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                      0x0000ffff00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB                              48
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK                             0x0001000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB                            49
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK                           0x0002000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB                            50
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB                            51
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK                           0x000c000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET                         0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB                            52
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK                           0x0010000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET                           0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB                              53
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK                             0x0020000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET                            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB                               54
+#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK                              0x0040000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET                               0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB                                  55
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB                                  57
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK                                 0x0380000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x0000000000000030
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               58
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               63
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc00000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x00000000000003ff
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x0000000000000400
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x0000000000000800
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x0000000000001000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x000000000000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB                    16
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB                    27
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK                   0x000000000fff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET                    0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB                       28
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB                       31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK                      0x00000000f0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET                 0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB                    32
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB                    35
+#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK                   0x0000000f00000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET      0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB         36
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB         51
+#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK        0x000ffff000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB                                  52
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB                                  56
+#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK                                 0x01f0000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET                                    0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB                                       57
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB                                       57
+#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK                                      0x0200000000000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET                               0x0000000000000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB                                  58
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB                                  63
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK                                 0xfc00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_rxpcu_classification_overview.h b/hw/wcn8750/v1/rx_rxpcu_classification_overview.h
new file mode 100644
index 000000000000..92489a5f5b2d
--- /dev/null
+++ b/hw/wcn8750/v1/rx_rxpcu_classification_overview.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t filter_pass_mpdus                                       :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      phyrx_abort_received                                    :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      phyrx_abort_received                                    :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      filter_pass_mpdus                                       :  1;
+#endif
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET                   0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK                     0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET            0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK              0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK                  0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK           0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET                 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK                   0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK            0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK                  0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET      0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK        0x00000080
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET                          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB                             9
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB                             15
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK                            0x0000fe00
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET                         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB                            16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB                            31
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK                           0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_start_param.h b/hw/wcn8750/v1/rx_start_param.h
new file mode 100644
index 000000000000..bb2b87e3cc97
--- /dev/null
+++ b/hw/wcn8750/v1/rx_start_param.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_START_PARAM_H_
+#define _RX_START_PARAM_H_
+
+#define NUM_OF_DWORDS_RX_START_PARAM 2
+
+#define NUM_OF_QWORDS_RX_START_PARAM 1
+
+struct rx_start_param {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      reserved_0a                                             : 12,
+                      remaining_rx_time                                       : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t remaining_rx_time                                       : 16,
+                      reserved_0a                                             : 12,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RX_START_PARAM_PKT_TYPE_OFFSET                                              0x0000000000000000
+#define RX_START_PARAM_PKT_TYPE_LSB                                                 0
+#define RX_START_PARAM_PKT_TYPE_MSB                                                 3
+#define RX_START_PARAM_PKT_TYPE_MASK                                                0x000000000000000f
+
+#define RX_START_PARAM_RESERVED_0A_OFFSET                                           0x0000000000000000
+#define RX_START_PARAM_RESERVED_0A_LSB                                              4
+#define RX_START_PARAM_RESERVED_0A_MSB                                              15
+#define RX_START_PARAM_RESERVED_0A_MASK                                             0x000000000000fff0
+
+#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET                                     0x0000000000000000
+#define RX_START_PARAM_REMAINING_RX_TIME_LSB                                        16
+#define RX_START_PARAM_REMAINING_RX_TIME_MSB                                        31
+#define RX_START_PARAM_REMAINING_RX_TIME_MASK                                       0x00000000ffff0000
+
+#define RX_START_PARAM_TLV64_PADDING_OFFSET                                         0x0000000000000000
+#define RX_START_PARAM_TLV64_PADDING_LSB                                            32
+#define RX_START_PARAM_TLV64_PADDING_MSB                                            63
+#define RX_START_PARAM_TLV64_PADDING_MASK                                           0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_timing_info.h b/hw/wcn8750/v1/rx_timing_info.h
new file mode 100644
index 000000000000..ea6780e25c55
--- /dev/null
+++ b/hw/wcn8750/v1/rx_timing_info.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TIMING_INFO_H_
+#define _RX_TIMING_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TIMING_INFO 5
+
+struct rx_timing_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t residual_phase_offset                                   : 12,
+                      sub_usec_ts_rx_end                                      : 10,
+                      reserved                                                : 10;
+#else
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t reserved                                                : 10,
+                      sub_usec_ts_rx_end                                      : 10,
+                      residual_phase_offset                                   : 12;
+#endif
+};
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET                              0x00000000
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET                              0x00000004
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET                              0x00000008
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET                              0x0000000c
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                                 0x00000010
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB                                    0
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB                                    11
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK                                   0x00000fff
+
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET                                    0x00000010
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB                                       12
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB                                       21
+#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK                                      0x003ff000
+
+#define RX_TIMING_INFO_RESERVED_OFFSET                                              0x00000010
+#define RX_TIMING_INFO_RESERVED_LSB                                                 22
+#define RX_TIMING_INFO_RESERVED_MSB                                                 31
+#define RX_TIMING_INFO_RESERVED_MASK                                                0xffc00000
+
+#endif
diff --git a/hw/wcn8750/v1/rx_trig_info.h b/hw/wcn8750/v1/rx_trig_info.h
new file mode 100644
index 000000000000..b6b074118bea
--- /dev/null
+++ b/hw/wcn8750/v1/rx_trig_info.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RX_TRIG_INFO_H_
+#define _RX_TRIG_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TRIG_INFO 2
+
+#define NUM_OF_QWORDS_RX_TRIG_INFO 1
+
+struct rx_trig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_trigger_frame_type                                   :  2,
+                      trigger_resp_type                                       :  3,
+                      reserved_0                                              : 27;
+             uint32_t ppdu_duration                                           : 16,
+                      unique_destination_id                                   : 16;
+#else
+             uint32_t reserved_0                                              : 27,
+                      trigger_resp_type                                       :  3,
+                      rx_trigger_frame_type                                   :  2;
+             uint32_t unique_destination_id                                   : 16,
+                      ppdu_duration                                           : 16;
+#endif
+};
+
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB                                      0
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB                                      1
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK                                     0x0000000000000003
+
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET                                       0x0000000000000000
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB                                          2
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB                                          4
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK                                         0x000000000000001c
+
+#define RX_TRIG_INFO_RESERVED_0_OFFSET                                              0x0000000000000000
+#define RX_TRIG_INFO_RESERVED_0_LSB                                                 5
+#define RX_TRIG_INFO_RESERVED_0_MSB                                                 31
+#define RX_TRIG_INFO_RESERVED_0_MASK                                                0x00000000ffffffe0
+
+#define RX_TRIG_INFO_PPDU_DURATION_OFFSET                                           0x0000000000000000
+#define RX_TRIG_INFO_PPDU_DURATION_LSB                                              32
+#define RX_TRIG_INFO_PPDU_DURATION_MSB                                              47
+#define RX_TRIG_INFO_PPDU_DURATION_MASK                                             0x0000ffff00000000
+
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET                                   0x0000000000000000
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB                                      48
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB                                      63
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK                                     0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/rxpcu_early_rx_indication.h b/hw/wcn8750/v1/rxpcu_early_rx_indication.h
new file mode 100644
index 000000000000..d2dc464cf1cf
--- /dev/null
+++ b/hw/wcn8750/v1/rxpcu_early_rx_indication.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_EARLY_RX_INDICATION_H_
+#define _RXPCU_EARLY_RX_INDICATION_H_
+
+#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2
+
+#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1
+
+struct rxpcu_early_rx_indication {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      reserved_0a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             : 18,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB                                      0
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB                                      3
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK                                     0x000000000000000f
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK                          0x0000000000000010
+
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET                                   0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB                                      5
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB                                      9
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK                                     0x00000000000003e0
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  10
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  13
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0000000000003c00
+
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET                                0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB                                   14
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB                                   31
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK                                  0x00000000ffffc000
+
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET                              0x0000000000000000
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB                                 32
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB                                 63
+#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK                                0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rxpcu_ppdu_end_info.h b/hw/wcn8750/v1/rxpcu_ppdu_end_info.h
new file mode 100644
index 000000000000..c97ad08c26a4
--- /dev/null
+++ b/hw/wcn8750/v1/rxpcu_ppdu_end_info.h
@@ -0,0 +1,925 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+#include "rxpcu_ppdu_end_layout_info.h"
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32
+
+#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16
+
+struct rxpcu_ppdu_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t rx_antenna                                              : 24,
+                      tx_ht_vht_ack                                           :  1,
+                      unsupported_mu_nc                                       :  1,
+                      otp_txbf_disable                                        :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      coex_wan_tx_after_start_of_rx_ratid1                    :  1;
+             uint32_t coex_bt_tx_from_start_of_rx                             :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      __reserved_g_0012                                                  :  2,
+                      dialog_token                                            :  8,
+                      follow_up_dialog_token                                  :  8,
+                      bb_captured_channel                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_timeout                                     :  1,
+                      __reserved_g_0054                                       :  1,
+                      __reserved_g_0058                                       :  1;
+             uint32_t before_mpdu_count_passing_fcs                           : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      reserved_4                                              :  2;
+             uint32_t after_mpdu_count_failing_fcs                            : 10,
+                      reserved_5                                              : 22;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t bb_length                                               : 16,
+                      bb_data                                                 :  1,
+                      reserved_8                                              :  3,
+                      first_bt_broadcast_status_details                       : 12;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      reserved_9                                              :  8;
+             uint32_t ast_index                                               : 16,
+                      ast_index_valid                                         :  1,
+                      reserved_10                                             :  3,
+                      second_bt_broadcast_status_details                      : 12;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint16_t pre_bt_broadcast_status_details                         : 12,
+                      reserved_12a                                            :  4;
+             uint32_t non_qos_sn_info_valid                                   :  1,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      rts_or_trig_prot_type                                   :  2,
+                      reserved_13a                                            :  2,
+                      non_qos_sn_highest                                      : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_lowest_retry_setting                         :  1;
+             uint32_t qos_sn_1_info_valid                                     :  1,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_tid                                            :  4,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_lowest_retry_setting                           :  1;
+             uint32_t qos_sn_2_info_valid                                     :  1,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_tid                                            :  4,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_lowest_retry_setting                           :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      qos_sn_1_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_peer_addr_15_0                         : 16;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t coex_tracker2_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      reserved_30a                                            : 22;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#else
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t coex_wan_tx_after_start_of_rx_ratid1                    :  1,
+                      coex_wan_tx_from_start_of_rx_ratid1                     :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      otp_txbf_disable                                        :  1,
+                      unsupported_mu_nc                                       :  1,
+                      tx_ht_vht_ack                                           :  1,
+                      rx_antenna                                              : 24;
+             uint32_t __reserved_g_0058                                       :  1,
+                      __reserved_g_0054                                       :  1,
+                      bb_captured_timeout                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_channel                                     :  1,
+                      follow_up_dialog_token                                  :  8,
+                      dialog_token                                            :  8,
+                      __reserved_g_0012                                                  :  2,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_bt_tx_from_start_of_rx                             :  1;
+             uint32_t reserved_4                                              :  2,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      before_mpdu_count_passing_fcs                           : 10;
+             uint32_t reserved_5                                              : 22,
+                      after_mpdu_count_failing_fcs                            : 10;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t first_bt_broadcast_status_details                       : 12,
+                      reserved_8                                              :  3,
+                      bb_data                                                 :  1,
+                      bb_length                                               : 16;
+             uint32_t reserved_9                                              :  8,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_10                                             :  3,
+                      ast_index_valid                                         :  1,
+                      ast_index                                               : 16;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             uint32_t reserved_12a                                            :  4,
+                      pre_bt_broadcast_status_details                         : 12;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint32_t non_qos_sn_lowest_retry_setting                         :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_highest                                      : 12,
+                      reserved_13a                                            :  2,
+                      rts_or_trig_prot_type                                   :  2,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      non_qos_sn_info_valid                                   :  1;
+             uint32_t qos_sn_1_lowest_retry_setting                           :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_tid                                            :  4,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_info_valid                                     :  1;
+             uint32_t qos_sn_2_lowest_retry_setting                           :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_tid                                            :  4,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_info_valid                                     :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t rts_or_trig_prot_peer_addr_15_0                         : 16,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_1_more_frag_state                                :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t reserved_30a                                            : 22,
+                      coex_tracker6_tx_after_start_of_rx                      :  1,
+                      coex_tracker6_tx_from_start_of_rx                       :  1,
+                      coex_tracker5_tx_after_start_of_rx                      :  1,
+                      coex_tracker5_tx_from_start_of_rx                       :  1,
+                      coex_tracker4_tx_after_start_of_rx                      :  1,
+                      coex_tracker4_tx_from_start_of_rx                       :  1,
+                      coex_tracker3_tx_after_start_of_rx                      :  1,
+                      coex_tracker3_tx_from_start_of_rx                       :  1,
+                      coex_tracker2_tx_after_start_of_rx                      :  1,
+                      coex_tracker2_tx_from_start_of_rx                       :  1;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB                               0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB                               31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK                              0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET                            0x0000000000000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB                               32
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB                               63
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK                              0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET                                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB                                          0
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB                                          23
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK                                         0x0000000000ffffff
+
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET                                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK                                      0x0000000001000000
+
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET                                0x0000000000000008
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK                                  0x0000000002000000
+
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET                                 0x0000000000000008
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK                                   0x0000000004000000
+
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK                             0x0000000008000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK                     0x0000000020000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB                 30
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK                0x0000000040000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET             0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB                31
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK               0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET                      0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB                         32
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK                        0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB                        33
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB                        34
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK                       0x0000000400000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB                       35
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK                      0x0000000800000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET                    0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB                       36
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK                      0x0000001000000000
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET                   0x0000000000000008
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB                      37
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK                     0x0000002000000000
+
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET                       0x0000000000000008
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB                          38
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK                         0x0000004000000000
+
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET                                     0x0000000000000008
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB                                        41
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB                                        48
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK                                       0x0001fe0000000000
+
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET                           0x0000000000000008
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB                              49
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB                              56
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK                             0x01fe000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB                                 57
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK                                0x0200000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET                               0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB                                  58
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB                                  60
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK                                 0x1c00000000000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET                              0x0000000000000008
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB                                 61
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK                                0x2000000000000000
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB                       0
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB                       9
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK                      0x00000000000003ff
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET                    0x0000000000000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB                       10
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB                       19
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK                      0x00000000000ffc00
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB                        20
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB                        29
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK                       0x000000003ff00000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB                                          30
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK                                         0x00000000c0000000
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET                     0x0000000000000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB                        32
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB                        41
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK                       0x000003ff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET                                       0x0000000000000010
+#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB                                          42
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK                                         0xfffffc0000000000
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB                           0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB                           31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK                          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET                        0x0000000000000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB                           32
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB                           63
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK                          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET                                        0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB                                           0
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB                                           15
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET                                          0x0000000000000020
+#define RXPCU_PPDU_END_INFO_BB_DATA_LSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MASK                                            0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB                                          17
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB                                          19
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK                                         0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                0x0000000000000020
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                   20
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                   31
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                  0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET                                 0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB                                    32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB                                    55
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK                                   0x00ffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET                                       0x0000000000000020
+#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB                                          56
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB                                          63
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK                                         0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET                                        0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB                                           0
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB                                           15
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK                                          0x000000000000ffff
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET                                  0x0000000000000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK                                    0x0000000000010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET                                      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB                                         17
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB                                         19
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK                                        0x00000000000e0000
+
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET               0x0000000000000028
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                  20
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                  31
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                 0x00000000fff00000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB  43
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB   45
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK  0x0000200000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB    46
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK   0x0000400000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         47
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB   48
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB   63
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK  0xffff000000000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000000000000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         8
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         15
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                     16
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                     27
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                    0x000000000fff0000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB                                        28
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK                                       0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB                               32
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK                              0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET                       0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB                          33
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK                         0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET                            0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB                               34
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB                               35
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK                              0x0000000c00000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET                                     0x0000000000000030
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB                                        36
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB                                        37
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK                                       0x0000003000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET                               0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB                                  38
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB                                  49
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK                                 0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET                 0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB                    50
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK                   0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET                                0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB                                   51
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB                                   62
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK                                  0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET                  0x0000000000000030
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB                     63
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK                    0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK                                0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK                                       0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB                                        2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB                                        5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK                                       0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB                                    6
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB                                    17
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK                                   0x000000000003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK                     0x0000000000040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB                                     19
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB                                     30
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK                                    0x000000007ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK                      0x0000000080000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET                              0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB                                 32
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK                                0x0000000100000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB                                        33
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK                                       0x0000000200000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET                                     0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB                                        34
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB                                        37
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK                                       0x0000003c00000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET                                 0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB                                    38
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB                                    49
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK                                   0x0003ffc000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET                   0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB                      50
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK                     0x0004000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET                                  0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB                                     51
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB                                     62
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK                                    0x7ff8000000000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET                    0x0000000000000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB                       63
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK                      0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB    0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB    1
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK   0x0000000000000003
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB        2
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB        7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK       0x00000000000000fc
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB        8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB        13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK       0x0000000000003f00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET      0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB         14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB         19
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK        0x00000000000fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET   0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB      20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB      25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK     0x0000000003f00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB    32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB    37
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK   0x0000003f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB  50
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB  55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET     0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB        56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB        62
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK       0x7f00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET        0x0000000000000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK          0x8000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB           28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK          0x00000000f0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET        0x0000000000000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB           60
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK          0xf000000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB   0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB   6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK  0x000000000000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB   7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB   13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK  0x0000000000003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB           29
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK          0x00000000e0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET        0x0000000000000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB           57
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK          0xfe00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET   0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB      0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB      7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK     0x00000000000000ff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB  16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB  23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET    0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB       24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB       31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK      0x00000000ff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET     0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB        40
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB        47
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK       0x0000ff0000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET        0x0000000000000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB           56
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK          0xff00000000000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB           0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK          0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET        0x0000000000000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB           32
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB           63
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK          0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                      0x0000000000000068
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                        0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK                           0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB                             2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB                             5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK                            0x000000000000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK                           0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET                          0x0000000000000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB                             7
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB                             10
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK                            0x0000000000000780
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET                         0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK                           0x0000000000000800
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET                        0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB                           12
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB                           15
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK                          0x000000000000f000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET                  0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB                     16
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB                     31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK                    0x00000000ffff0000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET                 0x0000000000000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB                    32
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB                    63
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK                   0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB                                0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB                                31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK                               0x00000000ffffffff
+
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET                             0x0000000000000070
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB                                32
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB                                63
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK                               0xffffffff00000000
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB                   0
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK                  0x0000000000000001
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB                  1
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK                 0x0000000000000002
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB                   2
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK                  0x0000000000000004
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB                  3
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK                 0x0000000000000008
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB                   4
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK                  0x0000000000000010
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB                  5
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK                 0x0000000000000020
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB                   6
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK                  0x0000000000000040
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB                  7
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK                 0x0000000000000080
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET                0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB                   8
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK                  0x0000000000000100
+
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB                  9
+#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK                 0x0000000000000200
+
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET                                     0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB                                        10
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK                                       0x00000000fffffc00
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET                               0x0000000000000078
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB                                  32
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB                                  63
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h b/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
new file mode 100644
index 000000000000..9d54e91522ec
--- /dev/null
+++ b/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
+#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
+
+struct rxpcu_ppdu_end_layout_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_legacy_offset                                      :  2,
+                      l_sig_a_offset                                          :  6,
+                      l_sig_b_offset                                          :  6,
+                      ht_sig_offset                                           :  6,
+                      vht_sig_a_offset                                        :  6,
+                      repeat_l_sig_a_offset                                   :  6;
+             uint32_t he_sig_a_su_offset                                      :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      generic_u_sig_offset                                    :  6,
+                      rssi_ht_offset                                          :  7,
+                      reserved_1a                                             :  1;
+             uint32_t vht_sig_b_su20_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su160_offset                                  :  7,
+                      reserved_2a                                             :  4;
+             uint32_t vht_sig_b_mu20_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      reserved_3a                                             :  4;
+             uint32_t he_sig_b1_mu_offset                                     :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      first_generic_eht_sig_offset                            :  7,
+                      multiple_generic_eht_sig_included                       :  1,
+                      reserved_4a                                             :  3;
+             uint32_t common_user_info_offset                                 :  7,
+                      first_debug_info_offset                                 :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_other_receive_info_included                    :  1,
+                      reserved_5a                                             :  7;
+             uint32_t data_done_offset                                        :  8,
+                      generated_cbf_details_offset                            :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      location_offset                                         :  8;
+             uint32_t __reserved_g_0011                                       :  8,
+                      pkt_end_offset                                          :  8,
+                      abort_request_ack_offset                                :  8,
+                      reserved_7a                                             :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#else
+             uint32_t repeat_l_sig_a_offset                                   :  6,
+                      vht_sig_a_offset                                        :  6,
+                      ht_sig_offset                                           :  6,
+                      l_sig_b_offset                                          :  6,
+                      l_sig_a_offset                                          :  6,
+                      rssi_legacy_offset                                      :  2;
+             uint32_t reserved_1a                                             :  1,
+                      rssi_ht_offset                                          :  7,
+                      generic_u_sig_offset                                    :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_su_offset                                      :  6;
+             uint32_t reserved_2a                                             :  4,
+                      vht_sig_b_su160_offset                                  :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su20_offset                                   :  7;
+             uint32_t reserved_3a                                             :  4,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu20_offset                                   :  7;
+             uint32_t reserved_4a                                             :  3,
+                      multiple_generic_eht_sig_included                       :  1,
+                      first_generic_eht_sig_offset                            :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b1_mu_offset                                     :  7;
+             uint32_t reserved_5a                                             :  7,
+                      multiple_other_receive_info_included                    :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_debug_info_offset                                 :  8,
+                      common_user_info_offset                                 :  7;
+             uint32_t location_offset                                         :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      generated_cbf_details_offset                            :  8,
+                      data_done_offset                                        :  8;
+             uint32_t reserved_7a                                             :  8,
+                      abort_request_ack_offset                                :  8,
+                      pkt_end_offset                                          :  8,
+                      __reserved_g_0011                                       :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET                        0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB                           1
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK                          0x00000003
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB                               2
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB                               7
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK                              0x000000fc
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB                               13
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK                              0x00003f00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET                             0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB                                14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB                                19
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK                               0x000fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET                          0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB                             20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB                             25
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK                            0x03f00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET                     0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB                        26
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB                        31
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK                       0xfc000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET                        0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB                           5
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK                          0x0000003f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB                        11
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK                       0x00000fc0
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB                        12
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB                        17
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK                       0x0003f000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET                      0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB                         18
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK                        0x00fc0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET                            0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB                               24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB                               30
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK                              0x7f000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET                               0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK                                 0x80000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET                    0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET                               0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET                               0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB                          0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB                          6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK                         0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB                          7
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB                          13
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK                         0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB                       14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB                       20
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK                      0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET              0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB                 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB                 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK                0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET         0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK           0x10000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET                               0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB                                  29
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK                                 0xe0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB                      0
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB                      6
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK                     0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB                      7
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB                      14
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK                     0x00007f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET              0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK                0x00008000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET           0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB              16
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB              23
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK             0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET      0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK        0x01000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET                               0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB                                  25
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK                                 0xfe000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET                          0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB                             0
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB                             7
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK                            0x000000ff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET              0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB                 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK                0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET                      0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB                         16
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK                        0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET                           0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB                              24
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB                              31
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK                             0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET                            0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB                               15
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK                              0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET                  0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB                     16
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB                     23
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK                    0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET                               0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB                                  24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK                                 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET                               0x00000020
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK                                 0xffffffff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET                               0x00000024
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/rxpt_classify_info.h b/hw/wcn8750/v1/rxpt_classify_info.h
new file mode 100644
index 000000000000..7fc572ae2474
--- /dev/null
+++ b/hw/wcn8750/v1/rxpt_classify_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      lmac_peer_id_msb                                        :  2,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_1000                                   :  1,
+                      rxdma0_source_ring_selection                            :  3,
+                      rxdma0_destination_ring_selection                       :  3,
+                      mcast_echo_drop_enable                                  :  1,
+                      wds_learning_detect_en                                  :  1,
+                      intrabss_check_en                                       :  1,
+                      use_ppe                                                 :  1,
+                      ppe_routing_enable                                      :  1,
+                      cce_source_sel_en                                       :  1,
+                      reserved_0b                                             :  9;
+#else
+             uint32_t reserved_0b                                             :  9,
+                      cce_source_sel_en                                       :  1,
+                      ppe_routing_enable                                      :  1,
+                      use_ppe                                                 :  1,
+                      intrabss_check_en                                       :  1,
+                      wds_learning_detect_en                                  :  1,
+                      mcast_echo_drop_enable                                  :  1,
+                      rxdma0_destination_ring_selection                       :  3,
+                      rxdma0_source_ring_selection                            :  3,
+                      pkt_selection_fp_1000                                   :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      lmac_peer_id_msb                                        :  2,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET                        0x00000000
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB                           0
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB                           4
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK                          0x0000001f
+
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET                                  0x00000000
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB                                     5
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB                                     6
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK                                    0x00000060
+
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET                         0x00000000
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK                           0x00000080
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK                         0x00000100
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK                         0x00000200
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET                             0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK                               0x00000400
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB                         11
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB                         13
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK                        0x00003800
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB                    14
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB                    16
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK                   0x0001c000
+
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK                              0x00020000
+
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK                              0x00040000
+
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK                                   0x00080000
+
+#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET                                           0x00000000
+#define RXPT_CLASSIFY_INFO_USE_PPE_LSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MASK                                             0x00100000
+
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET                                0x00000000
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK                                  0x00200000
+
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK                                   0x00400000
+
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB                                          23
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB                                          31
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK                                         0xff800000
+
+#endif
diff --git a/hw/wcn8750/v1/seq_hwio.h b/hw/wcn8750/v1/seq_hwio.h
new file mode 100644
index 000000000000..69111d08d535
--- /dev/null
+++ b/hw/wcn8750/v1/seq_hwio.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/hw/wcn8750/v1/tcl_assist_cmd.h b/hw/wcn8750/v1/tcl_assist_cmd.h
new file mode 100644
index 000000000000..f7a5bd5287cb
--- /dev/null
+++ b/hw/wcn8750/v1/tcl_assist_cmd.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_ASSIST_CMD_H_
+#define _TCL_ASSIST_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16
+
+struct tcl_assist_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t buf_or_ext_desc_type                                    :  1,
+                      bank_id                                                 :  6,
+                      vdev_id                                                 :  8,
+                      data_length                                             : 14,
+                      to_fw_tqm                                               :  2,
+                      reserved_2a                                             :  1;
+             uint32_t reserved_3a                                             : 25,
+                      metadata_length                                         :  7;
+             uint32_t txpt_classify_info_index                                :  8,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_override                             :  1,
+                      flow_override_enable                                    :  1,
+                      flow_select                                             :  1,
+                      hlos_tid                                                :  4,
+                      hlos_tid_overwrite                                      :  1,
+                      tos_tc_value                                            :  8,
+                      reserved_4a                                             :  3;
+             uint32_t reserved_5a                                             : 16,
+                      l3_type                                                 : 16;
+             uint32_t l4_protocol                                             :  8,
+                      l4_port                                                 : 16,
+                      l4_port_type                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      da_is_bcast                                             :  1,
+                      reserved_6a                                             :  5;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t ip_da_or_sa                                             :  1,
+                      encap_length_change                                     :  6,
+                      encap_length_decrease                                   :  1,
+                      encap_length_override                                   :  1,
+                      type_or_length                                          :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      msdu_color                                              :  2,
+                      tx_notify_frame                                         :  3,
+                      tqm_no_drop                                             :  1,
+                      reserved_11a                                            : 12,
+                      l3_checksum_enable                                      :  1,
+                      l4_checksum_enable                                      :  1;
+             uint32_t buffer_timestamp                                        : 19,
+                      buffer_timestamp_valid                                  :  1,
+                      s_vlan_tag_present                                      :  1,
+                      c_vlan_tag_present                                      :  1,
+                      wmac_hdr_len                                            :  7,
+                      reserved_12a                                            :  3;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t reserved_2a                                             :  1,
+                      to_fw_tqm                                               :  2,
+                      data_length                                             : 14,
+                      vdev_id                                                 :  8,
+                      bank_id                                                 :  6,
+                      buf_or_ext_desc_type                                    :  1;
+             uint32_t metadata_length                                         :  7,
+                      reserved_3a                                             : 25;
+             uint32_t reserved_4a                                             :  3,
+                      tos_tc_value                                            :  8,
+                      hlos_tid_overwrite                                      :  1,
+                      hlos_tid                                                :  4,
+                      flow_select                                             :  1,
+                      flow_override_enable                                    :  1,
+                      txpt_classify_info_override                             :  1,
+                      txpt_classify_info_sel                                  :  5,
+                      txpt_classify_info_index                                :  8;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             : 16;
+             uint32_t reserved_6a                                             :  5,
+                      da_is_bcast                                             :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      l4_port_type                                            :  1,
+                      l4_port                                                 : 16,
+                      l4_protocol                                             :  8;
+             uint32_t ip_address_31_0                                         : 32;
+             uint32_t ip_address_63_32                                        : 32;
+             uint32_t ip_address_95_64                                        : 32;
+             uint32_t ip_address_127_96                                       : 32;
+             uint32_t l4_checksum_enable                                      :  1,
+                      l3_checksum_enable                                      :  1,
+                      reserved_11a                                            : 12,
+                      tqm_no_drop                                             :  1,
+                      tx_notify_frame                                         :  3,
+                      msdu_color                                              :  2,
+                      snap_oui_not_zero_and_not_f8                            :  1,
+                      snap_oui_zero_or_f8                                     :  1,
+                      type_or_length                                          :  1,
+                      encap_length_override                                   :  1,
+                      encap_length_decrease                                   :  1,
+                      encap_length_change                                     :  6,
+                      ip_da_or_sa                                             :  1;
+             uint32_t reserved_12a                                            :  3,
+                      wmac_hdr_len                                            :  7,
+                      c_vlan_tag_present                                      :  1,
+                      s_vlan_tag_present                                      :  1,
+                      buffer_timestamp_valid                                  :  1,
+                      buffer_timestamp                                        : 19;
+             uint32_t tcl_cmd_number                                          : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_15a                                            : 20;
+#endif
+};
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                        0x00000000
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                           0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                          0xffffffff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                       0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                          0
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                          7
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                         0x000000ff
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                   0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                      8
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                      11
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                     0x00000f00
+
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                        0x00000004
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                           12
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                           31
+#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                          0xfffff000
+
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                  0x00000008
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                     0
+#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                    0x00000001
+
+#define TCL_ASSIST_CMD_BANK_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_BANK_ID_LSB                                                  1
+#define TCL_ASSIST_CMD_BANK_ID_MSB                                                  6
+#define TCL_ASSIST_CMD_BANK_ID_MASK                                                 0x0000007e
+
+#define TCL_ASSIST_CMD_VDEV_ID_OFFSET                                               0x00000008
+#define TCL_ASSIST_CMD_VDEV_ID_LSB                                                  7
+#define TCL_ASSIST_CMD_VDEV_ID_MSB                                                  14
+#define TCL_ASSIST_CMD_VDEV_ID_MASK                                                 0x00007f80
+
+#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_DATA_LENGTH_LSB                                              15
+#define TCL_ASSIST_CMD_DATA_LENGTH_MSB                                              28
+#define TCL_ASSIST_CMD_DATA_LENGTH_MASK                                             0x1fff8000
+
+#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET                                             0x00000008
+#define TCL_ASSIST_CMD_TO_FW_TQM_LSB                                                29
+#define TCL_ASSIST_CMD_TO_FW_TQM_MSB                                                30
+#define TCL_ASSIST_CMD_TO_FW_TQM_MASK                                               0x60000000
+
+#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET                                           0x00000008
+#define TCL_ASSIST_CMD_RESERVED_2A_LSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_2A_MASK                                             0x80000000
+
+#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET                                           0x0000000c
+#define TCL_ASSIST_CMD_RESERVED_3A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_3A_MSB                                              24
+#define TCL_ASSIST_CMD_RESERVED_3A_MASK                                             0x01ffffff
+
+#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET                                       0x0000000c
+#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB                                          25
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB                                          31
+#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK                                         0xfe000000
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET                              0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB                                 0
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB                                 7
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK                                0x000000ff
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET                                0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB                                   8
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB                                   12
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK                                  0x00001f00
+
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET                           0x00000010
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB                              13
+#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK                             0x00002000
+
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                  0x00000010
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB                                     14
+#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK                                    0x00004000
+
+#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_FLOW_SELECT_LSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MSB                                              15
+#define TCL_ASSIST_CMD_FLOW_SELECT_MASK                                             0x00008000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OFFSET                                              0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_LSB                                                 16
+#define TCL_ASSIST_CMD_HLOS_TID_MSB                                                 19
+#define TCL_ASSIST_CMD_HLOS_TID_MASK                                                0x000f0000
+
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET                                    0x00000010
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB                                       20
+#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET                                          0x00000010
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB                                             21
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB                                             28
+#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK                                            0x1fe00000
+
+#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET                                           0x00000010
+#define TCL_ASSIST_CMD_RESERVED_4A_LSB                                              29
+#define TCL_ASSIST_CMD_RESERVED_4A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_4A_MASK                                             0xe0000000
+
+#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET                                           0x00000014
+#define TCL_ASSIST_CMD_RESERVED_5A_LSB                                              0
+#define TCL_ASSIST_CMD_RESERVED_5A_MSB                                              15
+#define TCL_ASSIST_CMD_RESERVED_5A_MASK                                             0x0000ffff
+
+#define TCL_ASSIST_CMD_L3_TYPE_OFFSET                                               0x00000014
+#define TCL_ASSIST_CMD_L3_TYPE_LSB                                                  16
+#define TCL_ASSIST_CMD_L3_TYPE_MSB                                                  31
+#define TCL_ASSIST_CMD_L3_TYPE_MASK                                                 0xffff0000
+
+#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB                                              0
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB                                              7
+#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK                                             0x000000ff
+
+#define TCL_ASSIST_CMD_L4_PORT_OFFSET                                               0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_LSB                                                  8
+#define TCL_ASSIST_CMD_L4_PORT_MSB                                                  23
+#define TCL_ASSIST_CMD_L4_PORT_MASK                                                 0x00ffff00
+
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET                                          0x00000018
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB                                             24
+#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK                                            0x01000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET                                     0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB                                        25
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK                                       0x02000000
+
+#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB                                              26
+#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK                                             0x04000000
+
+#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET                                           0x00000018
+#define TCL_ASSIST_CMD_RESERVED_6A_LSB                                              27
+#define TCL_ASSIST_CMD_RESERVED_6A_MSB                                              31
+#define TCL_ASSIST_CMD_RESERVED_6A_MASK                                             0xf8000000
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET                                       0x0000001c
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB                                          0
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB                                          31
+#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK                                         0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET                                      0x00000020
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET                                      0x00000024
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB                                         0
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB                                         31
+#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK                                        0xffffffff
+
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET                                     0x00000028
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB                                        0
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB                                        31
+#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK                                       0xffffffff
+
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB                                              0
+#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK                                             0x00000001
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB                                      1
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB                                      6
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK                                     0x0000007e
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB                                    7
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK                                   0x00000080
+
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET                                 0x0000002c
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB                                    8
+#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK                                   0x00000100
+
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET                                        0x0000002c
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB                                           9
+#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK                                          0x00000200
+
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET                                   0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB                                      10
+#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK                                     0x00000400
+
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET                          0x0000002c
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB                             11
+#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK                            0x00000800
+
+#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET                                            0x0000002c
+#define TCL_ASSIST_CMD_MSDU_COLOR_LSB                                               12
+#define TCL_ASSIST_CMD_MSDU_COLOR_MSB                                               13
+#define TCL_ASSIST_CMD_MSDU_COLOR_MASK                                              0x00003000
+
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET                                       0x0000002c
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB                                          14
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB                                          16
+#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK                                         0x0001c000
+
+#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET                                           0x0000002c
+#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB                                              17
+#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK                                             0x00020000
+
+#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET                                          0x0000002c
+#define TCL_ASSIST_CMD_RESERVED_11A_LSB                                             18
+#define TCL_ASSIST_CMD_RESERVED_11A_MSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_11A_MASK                                            0x3ffc0000
+
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB                                       30
+#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK                                      0x40000000
+
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET                                    0x0000002c
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB                                       31
+#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK                                      0x80000000
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET                                      0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB                                         0
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB                                         18
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK                                        0x0007ffff
+
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                0x00000030
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB                                   19
+#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK                                  0x00080000
+
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB                                       20
+#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK                                      0x00100000
+
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET                                    0x00000030
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB                                       21
+#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK                                      0x00200000
+
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB                                             22
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB                                             28
+#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK                                            0x1fc00000
+
+#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET                                          0x00000030
+#define TCL_ASSIST_CMD_RESERVED_12A_LSB                                             29
+#define TCL_ASSIST_CMD_RESERVED_12A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_12A_MASK                                            0xe0000000
+
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET                                        0x00000034
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB                                           0
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB                                           31
+#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK                                          0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET                                          0x00000038
+#define TCL_ASSIST_CMD_RESERVED_14A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_14A_MSB                                             31
+#define TCL_ASSIST_CMD_RESERVED_14A_MASK                                            0xffffffff
+
+#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET                                          0x0000003c
+#define TCL_ASSIST_CMD_RESERVED_15A_LSB                                             0
+#define TCL_ASSIST_CMD_RESERVED_15A_MSB                                             19
+#define TCL_ASSIST_CMD_RESERVED_15A_MASK                                            0x000fffff
+
+#define TCL_ASSIST_CMD_RING_ID_OFFSET                                               0x0000003c
+#define TCL_ASSIST_CMD_RING_ID_LSB                                                  20
+#define TCL_ASSIST_CMD_RING_ID_MSB                                                  27
+#define TCL_ASSIST_CMD_RING_ID_MASK                                                 0x0ff00000
+
+#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET                                         0x0000003c
+#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB                                            28
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB                                            31
+#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK                                           0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/tcl_status_ring.h b/hw/wcn8750/v1/tcl_status_ring.h
new file mode 100644
index 000000000000..5a24217c95d5
--- /dev/null
+++ b/hw/wcn8750/v1/tcl_status_ring.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t gse_ctrl                                                :  4,
+                      ase_fse_sel                                             :  1,
+                      cache_op_res                                            :  2,
+                      index_search_en                                         :  1,
+                      msdu_cnt_n                                              : 24;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t hash_indx_val                                           : 20,
+                      cache_set_num                                           :  4,
+                      reserved_5a                                             :  8;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t msdu_cnt_n                                              : 24,
+                      index_search_en                                         :  1,
+                      cache_op_res                                            :  2,
+                      ase_fse_sel                                             :  1,
+                      gse_ctrl                                                :  4;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             :  8,
+                      cache_set_num                                           :  4,
+                      hash_indx_val                                           : 20;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_STATUS_RING_GSE_CTRL_OFFSET                                             0x00000000
+#define TCL_STATUS_RING_GSE_CTRL_LSB                                                0
+#define TCL_STATUS_RING_GSE_CTRL_MSB                                                3
+#define TCL_STATUS_RING_GSE_CTRL_MASK                                               0x0000000f
+
+#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET                                          0x00000000
+#define TCL_STATUS_RING_ASE_FSE_SEL_LSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MASK                                            0x00000010
+
+#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET                                         0x00000000
+#define TCL_STATUS_RING_CACHE_OP_RES_LSB                                            5
+#define TCL_STATUS_RING_CACHE_OP_RES_MSB                                            6
+#define TCL_STATUS_RING_CACHE_OP_RES_MASK                                           0x00000060
+
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET                                      0x00000000
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK                                        0x00000080
+
+#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET                                           0x00000000
+#define TCL_STATUS_RING_MSDU_CNT_N_LSB                                              8
+#define TCL_STATUS_RING_MSDU_CNT_N_MSB                                              31
+#define TCL_STATUS_RING_MSDU_CNT_N_MASK                                             0xffffff00
+
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET                                      0x00000004
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET                                      0x00000008
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET                                   0x0000000c
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB                                      0
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB                                      31
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK                                     0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET                                  0x00000010
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB                                     0
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB                                     31
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK                                    0xffffffff
+
+#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_HASH_INDX_VAL_LSB                                           0
+#define TCL_STATUS_RING_HASH_INDX_VAL_MSB                                           19
+#define TCL_STATUS_RING_HASH_INDX_VAL_MASK                                          0x000fffff
+
+#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_CACHE_SET_NUM_LSB                                           20
+#define TCL_STATUS_RING_CACHE_SET_NUM_MSB                                           23
+#define TCL_STATUS_RING_CACHE_SET_NUM_MASK                                          0x00f00000
+
+#define TCL_STATUS_RING_RESERVED_5A_OFFSET                                          0x00000014
+#define TCL_STATUS_RING_RESERVED_5A_LSB                                             24
+#define TCL_STATUS_RING_RESERVED_5A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_5A_MASK                                            0xff000000
+
+#define TCL_STATUS_RING_RESERVED_6A_OFFSET                                          0x00000018
+#define TCL_STATUS_RING_RESERVED_6A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_6A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_6A_MASK                                            0xffffffff
+
+#define TCL_STATUS_RING_RESERVED_7A_OFFSET                                          0x0000001c
+#define TCL_STATUS_RING_RESERVED_7A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_7A_MSB                                             19
+#define TCL_STATUS_RING_RESERVED_7A_MASK                                            0x000fffff
+
+#define TCL_STATUS_RING_RING_ID_OFFSET                                              0x0000001c
+#define TCL_STATUS_RING_RING_ID_LSB                                                 20
+#define TCL_STATUS_RING_RING_ID_MSB                                                 27
+#define TCL_STATUS_RING_RING_ID_MASK                                                0x0ff00000
+
+#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET                                        0x0000001c
+#define TCL_STATUS_RING_LOOPING_COUNT_LSB                                           28
+#define TCL_STATUS_RING_LOOPING_COUNT_MSB                                           31
+#define TCL_STATUS_RING_LOOPING_COUNT_MASK                                          0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/tlv_hdr.h b/hw/wcn8750/v1/tlv_hdr.h
new file mode 100644
index 000000000000..a2defe7be508
--- /dev/null
+++ b/hw/wcn8750/v1/tlv_hdr.h
@@ -0,0 +1,634 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+
+#define _TLV_USERID_WIDTH_      6
+
+#define _TLV_MRV_EN_LEN_WIDTH_  9
+#define _TLV_MRV_DIS_LEN_WIDTH_ 12
+
+#define _TLV_DATA_WIDTH_        32
+#define _TLV_64_DATA_WIDTH_     64
+#define _TLV_CDATA_WIDTH_       32
+#define _TLV_77_DATA_WIDTH_     77
+#define _TLV_CDATA_77_WIDTH_    64
+
+#define _TLV_TAG_WIDTH_         10
+#define _TLV_CTAG_WIDTH_        6
+
+struct tlv_mlo_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6;
+#else
+           uint32_t             tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_usr_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_mac_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved_0a     :   6,
+                                dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint64_t             pad_65to76_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                pad_65to76_bit      :   12;
+           uint64_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1,
+                                tlv_reserved_0a     :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_77_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_52  :   52;
+           uint64_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to128_bit     :   51;
+#else
+           uint64_t             pad_77to128_bit     :   51,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint64_t             tlv_cdata_lower_52  :   52,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+#endif
+};
+
+struct tlv_mlo_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mlo_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_mac_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+#else
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+#endif
+};
+
+struct tlv_usr_c_77_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_20  :   20;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             tlv_cdata_upper_12  :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+           uint32_t             pad_96to128_bit     :   32;
+#else
+           uint32_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             pad_77to96_bit      :   20,
+                                tlv_compression     :   1,
+                                tlv_cdata_upper_12  :   12;
+           uint32_t             pad_96to128_bit     :   32;
+#endif
+};
+
+struct tlv_usr_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_reserved        :   32;
+#else
+           uint64_t             tlv_reserved        :   32,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6,
+                                pad_32to64_bit      :   32;
+#else
+           uint64_t             pad_32to64_bit      :   32,
+                                tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to95_bit      :   19;
+#else
+           uint32_t             pad_77to95_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_77_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+           uint32_t             dso_subband0        :   1,
+                                dso_subband1        :   1,
+                                dso_subband2        :   1,
+                                dso_subband3        :   1,
+                                tlv_reserved_1a     :   4,
+                                npca_m_prim         :   1,
+                                npca_o_prim         :   1,
+                                tlv_reserved_1b     :   2,
+                                fbw                 :   1,
+                                tlv_reserved_1c     :   19;
+           uint32_t             pad_64to75_bit      :   12,
+                                tlv_compression     :   1,
+                                pad_77to96_bit      :   19;
+#else
+           uint32_t             pad_77to96_bit      :   19,
+                                tlv_compression     :   1,
+                                pad_64to75_bit      :   12;
+           uint32_t             tlv_reserved_1c     :   19,
+                                fbw                 :   1,
+                                tlv_reserved_1b     :   2,
+                                npca_o_prim         :   1,
+                                npca_m_prim         :   1,
+                                tlv_reserved_1a     :   4,
+                                dso_subband3        :   1,
+                                dso_subband2        :   1,
+                                dso_subband1        :   1,
+                                dso_subband0        :   1;
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_;
+#endif
+};
+
+struct tlv_usr_c_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata           :   _TLV_CDATA_WIDTH_,
+                                pad_44to64_bit      :   20;
+#else
+           uint64_t             tlv_cdata_lower_20  :   20,
+                                pad_44to64_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+#endif
+};
+
+#endif
diff --git a/hw/wcn8750/v1/tlv_tag_def.h b/hw/wcn8750/v1/tlv_tag_def.h
new file mode 100644
index 000000000000..8189c6ec5601
--- /dev/null
+++ b/hw/wcn8750/v1/tlv_tag_def.h
@@ -0,0 +1,1976 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum tlv_tag_def {
+  WIFIMACTX_CBF_START_E                                    = 0  ,
+  WIFIPHYRX_DATA_E                                         = 1  ,
+  WIFIPHYRX_CBF_DATA_RESP_E                                = 2  ,
+  WIFIPHYRX_ABORT_REQUEST_E                                = 3  ,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E                      = 4  ,
+  WIFIMACTX_DATA_RESP_E                                    = 5  ,
+  WIFIMACTX_CBF_DATA_E                                     = 6  ,
+  WIFIMACTX_CBF_DONE_E                                     = 7  ,
+  WIFIPHYRX_LMR_DATA_RESP_E                                = 8  ,
+  WIFIRXPCU_TO_UCODE_START_E                               = 9  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E             = 10  ,
+  WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E                      = 11  ,
+  WIFIRXPCU_TO_UCODE_FCS_STATUS_E                          = 12  ,
+  WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E                      = 13  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E           = 14  ,
+  WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E                    = 15  ,
+  WIFIRXPCU_TO_UCODE_END_E                                 = 16  ,
+  WIFIPHYRX_RSSI_LEGACY_20MHZ_E                            = 17  ,
+  WIFIPHYRX_NC_ABORT_REQUEST_E                             = 18  ,
+  WIFIPHYRX_PKT_END_20MHZ_E                                = 19  ,
+  WIFIPHYRX_NC_DATA_E                                      = 20  ,
+  WIFIMACRX_CBF_READ_REQUEST_E                             = 64  ,
+  WIFIMACRX_CBF_DATA_REQUEST_E                             = 65  ,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E                         = 66  ,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E                       = 67  ,
+  WIFIMACRX_NDP_TIMEOUT_E                                  = 68  ,
+  WIFIMACRX_ABORT_ACK_E                                    = 69  ,
+  WIFIMACRX_REQ_IMPLICIT_FB_E                              = 70  ,
+  WIFIMACRX_CHAIN_MASK_E                                   = 71  ,
+  WIFIMACRX_NAP_USER_E                                     = 72  ,
+  WIFIMACRX_ABORT_REQUEST_E                                = 73  ,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E                        = 74  ,
+  WIFIPHYTX_ABORT_ACK_E                                    = 75  ,
+  WIFIPHYTX_ABORT_REQUEST_E                                = 76  ,
+  WIFIPHYTX_PKT_END_E                                      = 77  ,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E                     = 78  ,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E                            = 79  ,
+  WIFIPHYTX_DATA_REQUEST_E                                 = 80  ,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E                           = 81  ,
+  WIFIPHYTX_NAP_ACK_E                                      = 82  ,
+  WIFIPHYTX_NAP_DONE_E                                     = 83  ,
+  WIFIPHYTX_OFF_ACK_E                                      = 84  ,
+  WIFIPHYTX_ON_ACK_E                                       = 85  ,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                                = 86  ,
+  WIFIPHYTX_DEBUG16_E                                      = 87  ,
+  WIFIMACTX_ABORT_REQUEST_E                                = 88  ,
+  WIFIMACTX_ABORT_ACK_E                                    = 89  ,
+  WIFIMACTX_PKT_END_E                                      = 90  ,
+  WIFIMACTX_PRE_PHY_DESC_E                                 = 91  ,
+  WIFIMACTX_BF_PARAMS_COMMON_E                             = 92  ,
+  WIFIMACTX_BF_PARAMS_PER_USER_E                           = 93  ,
+  WIFIMACTX_PREFETCH_CV_E                                  = 94  ,
+  WIFIMACTX_USER_DESC_COMMON_E                             = 95  ,
+  WIFIMACTX_USER_DESC_PER_USER_E                           = 96  ,
+  WIFIEXAMPLE_USER_TLV_16_E                                = 97  ,
+  WIFIEXAMPLE_TLV_16_E                                     = 98  ,
+  WIFIMACTX_PHY_OFF_E                                      = 99  ,
+  WIFIMACTX_PHY_ON_E                                       = 100  ,
+  WIFIMACTX_SYNTH_OFF_E                                    = 101  ,
+  WIFIMACTX_EXPECT_CBF_COMMON_E                            = 102  ,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E                          = 103  ,
+  WIFIMACTX_PHY_DESC_E                                     = 104  ,
+  WIFIMACTX_L_SIG_A_E                                      = 105  ,
+  WIFIMACTX_L_SIG_B_E                                      = 106  ,
+  WIFIMACTX_HT_SIG_E                                       = 107  ,
+  WIFIMACTX_VHT_SIG_A_E                                    = 108  ,
+  WIFIMACTX_VHT_SIG_B_SU20_E                               = 109  ,
+  WIFIMACTX_VHT_SIG_B_SU40_E                               = 110  ,
+  WIFIMACTX_VHT_SIG_B_SU80_E                               = 111  ,
+  WIFIMACTX_VHT_SIG_B_SU160_E                              = 112  ,
+  WIFIMACTX_VHT_SIG_B_MU20_E                               = 113  ,
+  WIFIMACTX_VHT_SIG_B_MU40_E                               = 114  ,
+  WIFIMACTX_VHT_SIG_B_MU80_E                               = 115  ,
+  WIFIMACTX_VHT_SIG_B_MU160_E                              = 116  ,
+  WIFIMACTX_SERVICE_E                                      = 117  ,
+  WIFIMACTX_HE_SIG_A_SU_E                                  = 118  ,
+  WIFIMACTX_HE_SIG_A_MU_DL_E                               = 119  ,
+  WIFIMACTX_HE_SIG_A_MU_UL_E                               = 120  ,
+  WIFIMACTX_HE_SIG_B1_MU_E                                 = 121  ,
+  WIFIMACTX_HE_SIG_B2_MU_E                                 = 122  ,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E                              = 123  ,
+  WIFIMACTX_DELETE_CV_E                                    = 124  ,
+  WIFIMACTX_MU_UPLINK_COMMON_E                             = 125  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E                         = 126  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E                          = 127  ,
+  WIFIMACTX_PHY_NAP_E                                      = 128  ,
+  WIFIMACTX_DEBUG_E                                        = 129  ,
+  WIFIPHYRX_ABORT_ACK_E                                    = 130  ,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E                        = 131  ,
+  WIFIPHYRX_RSSI_LEGACY_E                                  = 132  ,
+  WIFIPHYRX_RSSI_HT_E                                      = 133  ,
+  WIFIPHYRX_USER_INFO_E                                    = 134  ,
+  WIFIPHYRX_PKT_END_E                                      = 135  ,
+  WIFIPHYRX_DEBUG_E                                        = 136  ,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E                            = 137  ,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E                           = 138  ,
+  WIFIPHYRX_L_SIG_A_E                                      = 139  ,
+  WIFIPHYRX_L_SIG_B_E                                      = 140  ,
+  WIFIPHYRX_HT_SIG_E                                       = 141  ,
+  WIFIPHYRX_VHT_SIG_A_E                                    = 142  ,
+  WIFIPHYRX_VHT_SIG_B_SU20_E                               = 143  ,
+  WIFIPHYRX_VHT_SIG_B_SU40_E                               = 144  ,
+  WIFIPHYRX_VHT_SIG_B_SU80_E                               = 145  ,
+  WIFIPHYRX_VHT_SIG_B_SU160_E                              = 146  ,
+  WIFIPHYRX_VHT_SIG_B_MU20_E                               = 147  ,
+  WIFIPHYRX_VHT_SIG_B_MU40_E                               = 148  ,
+  WIFIPHYRX_VHT_SIG_B_MU80_E                               = 149  ,
+  WIFIPHYRX_VHT_SIG_B_MU160_E                              = 150  ,
+  WIFIPHYRX_HE_SIG_A_SU_E                                  = 151  ,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E                               = 152  ,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E                               = 153  ,
+  WIFIPHYRX_HE_SIG_B1_MU_E                                 = 154  ,
+  WIFIPHYRX_HE_SIG_B2_MU_E                                 = 155  ,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E                              = 156  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E                           = 157  ,
+  WIFIPHYRX_COMMON_USER_INFO_E                             = 158  ,
+  WIFIPHYRX_DATA_DONE_E                                    = 159  ,
+  WIFICOEX_TX_REQ_E                                        = 160  ,
+  WIFIDUMMY_E                                              = 161  ,
+  WIFIEXAMPLE_TLV_32_NAME_E                                = 162  ,
+  WIFIMPDU_LIMIT_E                                         = 163  ,
+  WIFINA_LENGTH_END_E                                      = 164  ,
+  WIFIOLE_BUF_STATUS_E                                     = 165  ,
+  WIFIPCU_PPDU_SETUP_DONE_E                                = 166  ,
+  WIFIPCU_PPDU_SETUP_END_E                                 = 167  ,
+  WIFIPCU_PPDU_SETUP_INIT_E                                = 168  ,
+  WIFIPCU_PPDU_SETUP_START_E                               = 169  ,
+  WIFIPDG_FES_SETUP_E                                      = 170  ,
+  WIFIPDG_RESPONSE_E                                       = 171  ,
+  WIFIPDG_TX_REQ_E                                         = 172  ,
+  WIFISCH_WAIT_INSTR_E                                     = 173  ,
+  WIFIMACTX_SWITCH_TO_MAIN_E                               = 174  ,
+  WIFIPHYTX_LINK_STATE_E                                   = 175  ,
+  WIFIAUX_PPDU_END_E                                       = 176  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E                           = 177  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E                    = 178  ,
+  WIFITQM_GEN_MPDUS_E                                      = 179  ,
+  WIFITQM_GEN_MPDUS_STATUS_E                               = 180  ,
+  WIFITQM_REMOVE_MPDU_E                                    = 181  ,
+  WIFITQM_REMOVE_MPDU_STATUS_E                             = 182  ,
+  WIFITQM_REMOVE_MSDU_E                                    = 183  ,
+  WIFITQM_REMOVE_MSDU_STATUS_E                             = 184  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E                           = 185  ,
+  WIFITQM_WRITE_CMD_E                                      = 186  ,
+  WIFIOFDMA_TRIGGER_DETAILS_E                              = 187  ,
+  WIFITX_DATA_E                                            = 188  ,
+  WIFITX_FES_SETUP_E                                       = 189  ,
+  WIFIRX_PACKET_E                                          = 190  ,
+  WIFIEXPECTED_RESPONSE_E                                  = 191  ,
+  WIFITX_MPDU_END_E                                        = 192  ,
+  WIFITX_MPDU_START_E                                      = 193  ,
+  WIFITX_MSDU_END_E                                        = 194  ,
+  WIFITX_MSDU_START_E                                      = 195  ,
+  WIFITX_SW_MODE_SETUP_E                                   = 196  ,
+  WIFITXPCU_BUFFER_STATUS_E                                = 197  ,
+  WIFITXPCU_USER_BUFFER_STATUS_E                           = 198  ,
+  WIFIDATA_TO_TIME_CONFIG_E                                = 199  ,
+  WIFIEXAMPLE_USER_TLV_32_E                                = 200  ,
+  WIFIMPDU_INFO_E                                          = 201  ,
+  WIFIPDG_USER_SETUP_E                                     = 202  ,
+  WIFITX_11AH_SETUP_E                                      = 203  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E                     = 204  ,
+  WIFITX_PEER_ENTRY_E                                      = 205  ,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E                       = 206  ,
+  WIFIEXAMPLE_USER_TLV_44_E                                = 207  ,
+  WIFITX_FLUSH_E                                           = 208  ,
+  WIFITX_FLUSH_REQ_E                                       = 209  ,
+  WIFITQM_WRITE_CMD_STATUS_E                               = 210  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E                           = 211  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_E                            = 212  ,
+  WIFIEXAMPLE_USER_CTLV_44_E                               = 213  ,
+  WIFITX_FES_STATUS_START_E                                = 214  ,
+  WIFITX_FES_STATUS_USER_PPDU_E                            = 215  ,
+  WIFITX_FES_STATUS_USER_RESPONSE_E                        = 216  ,
+  WIFITX_FES_STATUS_END_E                                  = 217  ,
+  WIFIRX_TRIG_INFO_E                                       = 218  ,
+  WIFIRXPCU_TX_SETUP_CLEAR_E                               = 219  ,
+  WIFIRX_FRAME_BITMAP_REQ_E                                = 220  ,
+  WIFIRX_FRAME_BITMAP_ACK_E                                = 221  ,
+  WIFICOEX_RX_STATUS_E                                     = 222  ,
+  WIFIRX_START_PARAM_E                                     = 223  ,
+  WIFIRX_PPDU_START_E                                      = 224  ,
+  WIFIRX_PPDU_END_E                                        = 225  ,
+  WIFIRX_MPDU_START_E                                      = 226  ,
+  WIFIRX_MPDU_END_E                                        = 227  ,
+  WIFIRX_MSDU_START_E                                      = 228  ,
+  WIFIRX_MSDU_END_E                                        = 229  ,
+  WIFIRX_ATTENTION_E                                       = 230  ,
+  WIFIRECEIVED_RESPONSE_INFO_E                             = 231  ,
+  WIFIRX_PHY_SLEEP_E                                       = 232  ,
+  WIFIRX_HEADER_E                                          = 233  ,
+  WIFIRX_PEER_ENTRY_E                                      = 234  ,
+  WIFIRX_FLUSH_E                                           = 235  ,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E                          = 236  ,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E                           = 237  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E                    = 238  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E                     = 239  ,
+  WIFITX_CBF_INFO_E                                        = 240  ,
+  WIFIPCU_PPDU_SETUP_USER_E                                = 241  ,
+  WIFIRX_MPDU_PCU_START_E                                  = 242  ,
+  WIFIRX_PM_INFO_E                                         = 243  ,
+  WIFIRX_USER_PPDU_END_E                                   = 244  ,
+  WIFIRX_PRE_PPDU_START_E                                  = 245  ,
+  WIFIRX_PREAMBLE_E                                        = 246  ,
+  WIFITX_FES_SETUP_COMPLETE_E                              = 247  ,
+  WIFITX_LAST_MPDU_FETCHED_E                               = 248  ,
+  WIFITXDMA_STOP_REQUEST_E                                 = 249  ,
+  WIFIRXPCU_SETUP_E                                        = 250  ,
+  WIFIRXPCU_USER_SETUP_E                                   = 251  ,
+  WIFITX_FES_STATUS_ACK_OR_BA_E                            = 252  ,
+  WIFITQM_ACKED_MPDU_E                                     = 253  ,
+  WIFICOEX_TX_RESP_E                                       = 254  ,
+  WIFICOEX_TX_STATUS_E                                     = 255  ,
+  WIFIMACTX_COEX_PHY_CTRL_E                                = 256  ,
+  WIFICOEX_STATUS_BROADCAST_E                              = 257  ,
+  WIFIRESPONSE_START_STATUS_E                              = 258  ,
+  WIFIRESPONSE_END_STATUS_E                                = 259  ,
+  WIFICRYPTO_STATUS_E                                      = 260  ,
+  WIFIRECEIVED_TRIGGER_INFO_E                              = 261  ,
+  WIFICOEX_TX_STOP_CTRL_E                                  = 262  ,
+  WIFIRX_PPDU_ACK_REPORT_E                                 = 263  ,
+  WIFIRX_PPDU_NO_ACK_REPORT_E                              = 264  ,
+  WIFISCH_COEX_STATUS_E                                    = 265  ,
+  WIFISCHEDULER_COMMAND_STATUS_E                           = 266  ,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E               = 267  ,
+  WIFITX_FES_STATUS_PROT_E                                 = 268  ,
+  WIFITX_FES_STATUS_START_PPDU_E                           = 269  ,
+  WIFITX_FES_STATUS_START_PROT_E                           = 270  ,
+  WIFITXPCU_PHYTX_DEBUG32_E                                = 271  ,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E                  = 272  ,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E                         = 273  ,
+  WIFIWHO_ANCHOR_OFFSET_E                                  = 274  ,
+  WIFIWHO_ANCHOR_VALUE_E                                   = 275  ,
+  WIFIWHO_CCE_INFO_E                                       = 276  ,
+  WIFIWHO_COMMIT_E                                         = 277  ,
+  WIFIWHO_COMMIT_DONE_E                                    = 278  ,
+  WIFIWHO_FLUSH_E                                          = 279  ,
+  WIFIWHO_L2_LLC_E                                         = 280  ,
+  WIFIWHO_L2_PAYLOAD_E                                     = 281  ,
+  WIFIWHO_L3_CHECKSUM_E                                    = 282  ,
+  WIFIWHO_L3_INFO_E                                        = 283  ,
+  WIFIWHO_L4_CHECKSUM_E                                    = 284  ,
+  WIFIWHO_L4_INFO_E                                        = 285  ,
+  WIFIWHO_MSDU_E                                           = 286  ,
+  WIFIWHO_MSDU_MISC_E                                      = 287  ,
+  WIFIWHO_PACKET_DATA_E                                    = 288  ,
+  WIFIWHO_PACKET_HDR_E                                     = 289  ,
+  WIFIWHO_PPDU_END_E                                       = 290  ,
+  WIFIWHO_PPDU_START_E                                     = 291  ,
+  WIFIWHO_TSO_E                                            = 292  ,
+  WIFIWHO_WMAC_HEADER_PV0_E                                = 293  ,
+  WIFIWHO_WMAC_HEADER_PV1_E                                = 294  ,
+  WIFIWHO_WMAC_IV_E                                        = 295  ,
+  WIFIMPDU_INFO_END_E                                      = 296  ,
+  WIFIMPDU_INFO_BITMAP_E                                   = 297  ,
+  WIFITX_QUEUE_EXTENSION_E                                 = 298  ,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E                  = 299  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E                    = 300  ,
+  WIFITQM_ACKED_MPDU_STATUS_E                              = 301  ,
+  WIFITQM_ADD_MSDU_STATUS_E                                = 302  ,
+  WIFITQM_LIST_GEN_DONE_E                                  = 303  ,
+  WIFIWHO_TERMINATE_E                                      = 304  ,
+  WIFITX_LAST_MPDU_END_E                                   = 305  ,
+  WIFITX_CV_DATA_E                                         = 306  ,
+  WIFIPPDU_TX_END_E                                        = 307  ,
+  WIFIPROT_TX_END_E                                        = 308  ,
+  WIFIMPDU_INFO_GLOBAL_END_E                               = 309  ,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E                           = 310  ,
+  WIFIRX_PPDU_END_USER_STATS_E                             = 311  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E                         = 312  ,
+  WIFIREO_GET_QUEUE_STATS_E                                = 313  ,
+  WIFIREO_FLUSH_QUEUE_E                                    = 314  ,
+  WIFIREO_FLUSH_CACHE_E                                    = 315  ,
+  WIFIREO_UNBLOCK_CACHE_E                                  = 316  ,
+  WIFIREO_GET_QUEUE_STATS_STATUS_E                         = 317  ,
+  WIFIREO_FLUSH_QUEUE_STATUS_E                             = 318  ,
+  WIFIREO_FLUSH_CACHE_STATUS_E                             = 319  ,
+  WIFIREO_UNBLOCK_CACHE_STATUS_E                           = 320  ,
+  WIFITQM_FLUSH_CACHE_E                                    = 321  ,
+  WIFITQM_UNBLOCK_CACHE_E                                  = 322  ,
+  WIFITQM_FLUSH_CACHE_STATUS_E                             = 323  ,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E                           = 324  ,
+  WIFIRX_PPDU_END_STATUS_DONE_E                            = 325  ,
+  WIFIRX_STATUS_BUFFER_DONE_E                              = 326  ,
+  WIFISCHEDULER_MLO_SW_MSG_STATUS_E                        = 327  ,
+  WIFISCHEDULER_TXOP_DURATION_TRIGGER_E                    = 328  ,
+  WIFITX_DATA_SYNC_E                                       = 329  ,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E                         = 330  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_E                             = 331  ,
+  WIFITQM_SYNC_CMD_E                                       = 332  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E                      = 333  ,
+  WIFITQM_SYNC_CMD_STATUS_E                                = 334  ,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E             = 335  ,
+  WIFITCC_TQM_WRAPPER_CMD_E                                = 336  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_E                             = 337  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E                      = 338  ,
+  WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E            = 339  ,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E          = 340  ,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E                           = 341  ,
+  WIFIRX_PPDU_START_USER_INFO_E                            = 342  ,
+  WIFIRX_RING_MASK_E                                       = 343  ,
+  WIFICOEX_MAC_NAP_E                                       = 344  ,
+  WIFIRXPCU_PPDU_END_INFO_E                                = 345  ,
+  WIFIWHO_MESH_CONTROL_E                                   = 346  ,
+  WIFIPDG_SW_MODE_BW_START_E                               = 347  ,
+  WIFIPDG_SW_MODE_BW_END_E                                 = 348  ,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E                           = 349  ,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E                           = 350  ,
+  WIFISCHEDULER_END_E                                      = 351  ,
+  WIFIRX_PPDU_START_DROPPED_E                              = 352  ,
+  WIFIRX_PPDU_END_DROPPED_E                                = 353  ,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E                    = 354  ,
+  WIFIRX_MPDU_START_DROPPED_E                              = 355  ,
+  WIFIRX_MSDU_START_DROPPED_E                              = 356  ,
+  WIFIRX_MSDU_END_DROPPED_E                                = 357  ,
+  WIFIRX_MPDU_END_DROPPED_E                                = 358  ,
+  WIFIRX_ATTENTION_DROPPED_E                               = 359  ,
+  WIFITXPCU_USER_SETUP_E                                   = 360  ,
+  WIFIRXPCU_USER_SETUP_EXT_E                               = 361  ,
+  WIFICMD_PART_0_END_E                                     = 362  ,
+  WIFIMACTX_SYNTH_ON_E                                     = 363  ,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E                         = 364  ,
+  WIFITQM_MPDU_GLOBAL_START_E                              = 365  ,
+  WIFIEXAMPLE_TLV_32_E                                     = 366  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E                            = 367  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E                      = 368  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E                     = 369  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E               = 370  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_E                            = 371  ,
+  WIFITQM_2_SCH_MPDU_AVAILABLE_E                           = 372  ,
+  WIFIPDG_TRIG_RESPONSE_E                                  = 373  ,
+  WIFITRIGGER_RESPONSE_TX_DONE_E                           = 374  ,
+  WIFIABORT_FROM_PHYRX_DETAILS_E                           = 375  ,
+  WIFISCH_TQM_CMD_WRAPPER_E                                = 376  ,
+  WIFIMPDUS_AVAILABLE_E                                    = 377  ,
+  WIFIRECEIVED_RESPONSE_INFO_PART2_E                       = 378  ,
+  WIFIPHYRX_TX_START_TIMING_E                              = 379  ,
+  WIFITXPCU_PREAMBLE_DONE_E                                = 380  ,
+  WIFINDP_PREAMBLE_DONE_E                                  = 381  ,
+  WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E                       = 382  ,
+  WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E                      = 383  ,
+  WIFIMACTX_CLEAR_PREV_TX_INFO_E                           = 384  ,
+  WIFITX_PUNCTURE_SETUP_E                                  = 385  ,
+  WIFIR2R_STATUS_END_E                                     = 386  ,
+  WIFIMACTX_PREFETCH_CV_COMMON_E                           = 387  ,
+  WIFIEND_OF_FLUSH_MARKER_E                                = 388  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PUNC_E                        = 389  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E                    = 390  ,
+  WIFIRECEIVED_RESPONSE_USER_7_0_E                         = 391  ,
+  WIFIRECEIVED_RESPONSE_USER_15_8_E                        = 392  ,
+  WIFIRECEIVED_RESPONSE_USER_23_16_E                       = 393  ,
+  WIFIRECEIVED_RESPONSE_USER_31_24_E                       = 394  ,
+  WIFIRECEIVED_RESPONSE_USER_36_32_E                       = 395  ,
+  WIFITX_LOOPBACK_SETUP_E                                  = 396  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E                = 397  ,
+  WIFISCH_WAIT_INSTR_TX_PATH_E                             = 398  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E                    = 399  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E             = 400  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E               = 401  ,
+  WIFITX_WUR_DATA_E                                        = 402  ,
+  WIFIRX_PPDU_END_START_E                                  = 403  ,
+  WIFIRX_PPDU_END_MIDDLE_E                                 = 404  ,
+  WIFIRX_PPDU_END_LAST_E                                   = 405  ,
+  WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E                   = 406  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E              = 407  ,
+  WIFISRP_INFO_E                                           = 408  ,
+  WIFIOBSS_SR_INFO_E                                       = 409  ,
+  WIFISCHEDULER_SW_MSG_STATUS_E                            = 410  ,
+  WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E                  = 411  ,
+  WIFIRXPCU_SETUP_COMPLETE_E                               = 412  ,
+  WIFIMACTX_MCC_SWITCH_E                                   = 413  ,
+  WIFIMACTX_MCC_SWITCH_BACK_E                              = 414  ,
+  WIFIPHYTX_MCC_SWITCH_ACK_E                               = 415  ,
+  WIFIPHYTX_MCC_SWITCH_BACK_ACK_E                          = 416  ,
+  WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E                         = 417  ,
+  WIFILMR_TX_END_E                                         = 418  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E            = 419  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E              = 420  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E              = 421  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E          = 422  ,
+  WIFISCH_TLV_WRAPPER_E                                    = 423  ,
+  WIFISCHEDULER_STATUS_WRAPPER_E                           = 424  ,
+  WIFIMPDU_INFO_6X_E                                       = 425  ,
+  WIFIMACTX___RESERVED_G_0013                              = 426  ,
+  WIFIMACTX_U_SIG_EHT_SU_MU_E                              = 427  ,
+  WIFIMACTX_U_SIG_EHT_TB_E                                 = 428  ,
+  WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E                          = 429  ,
+  WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E                          = 430  ,
+  WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E                          = 431  ,
+  WIFIPHYRX_U_SIG_EHT_SU_MU_E                              = 432  ,
+  WIFIPHYRX_U_SIG_EHT_TB_E                                 = 433  ,
+  WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E                          = 434  ,
+  WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                      = 435  ,
+  WIFITX_PUNCTURE_6PATTERNS_SETUP_E                        = 436  ,
+  WIFIMACRX_LMR_READ_REQUEST_E                             = 437  ,
+  WIFIMACRX_LMR_DATA_REQUEST_E                             = 438  ,
+  WIFIPHYRX_LMR_TRANSFER_DONE_E                            = 439  ,
+  WIFIPHYRX_LMR_TRANSFER_ABORT_E                           = 440  ,
+  WIFIPHYRX_LMR_READ_REQUEST_ACK_E                         = 441  ,
+  WIFIMACRX_SECURE_LTF_SEQ_PTR_E                           = 442  ,
+  WIFIPHYRX_USER_INFO_MU_UL_E                              = 443  ,
+  WIFIMPDU_QUEUE_OVERVIEW_E                                = 444  ,
+  WIFISCHEDULER_NAV_INFO_E                                 = 445  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E                = 446  ,
+  WIFILMR_PEER_ENTRY_E                                     = 447  ,
+  WIFILMR_MPDU_START_E                                     = 448  ,
+  WIFILMR_DATA_E                                           = 449  ,
+  WIFILMR_MPDU_END_E                                       = 450  ,
+  WIFIREO_GET_QUEUE_1K_STATS_STATUS_E                      = 451  ,
+  WIFIRX_FRAME_1K_BITMAP_ACK_E                             = 452  ,
+  WIFITX_FES_STATUS_1K_BA_E                                = 453  ,
+  WIFITQM_ACKED_1K_MPDU_E                                  = 454  ,
+  WIFIMACRX_INBSS_OBSS_IND_E                               = 455  ,
+  WIFIPHYRX_LOCATION_E                                     = 456  ,
+  WIFIMLO_TX_NOTIFICATION_SU_E                             = 457  ,
+  WIFIMLO_TX_NOTIFICATION_MU_E                             = 458  ,
+  WIFIMLO_TX_REQ_SU_E                                      = 459  ,
+  WIFIMLO_TX_REQ_MU_E                                      = 460  ,
+  WIFIMLO_TX_RESP_E                                        = 461  ,
+  WIFIMLO_RX_NOTIFICATION_E                                = 462  ,
+  WIFIMLO_BKOFF_TRUNC_REQ_E                                = 463  ,
+  WIFIMLO_TBTT_NOTIFICATION_E                              = 464  ,
+  WIFIMLO_MESSAGE_E                                        = 465  ,
+  WIFIMLO_TS_SYNC_MSG_E                                    = 466  ,
+  WIFIMLO_FES_SETUP_E                                      = 467  ,
+  WIFIMLO_PDG_FES_SETUP_SU_E                               = 468  ,
+  WIFIMLO_PDG_FES_SETUP_MU_E                               = 469  ,
+  WIFIMPDU_INFO_1K_BITMAP_E                                = 470  ,
+  WIFIMON_BUFFER_ADDR_E                                    = 471  ,
+  WIFITX_FRAG_STATE_E                                      = 472  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E             = 473  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E              = 474  ,
+  WIFIMACTX_EHT_SIG_USR_OFDMA_E                            = 475  ,
+  WIFIMACTX_U_SIG_UHR_SU_MU_E                              = 476  ,
+  WIFIMACTX_U_SIG_UHR_TB_E                                 = 477  ,
+  WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E                     = 478  ,
+  WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E                     = 479  ,
+  WIFITX_MSDU_COMPONENT_DETAILS_TLV_E                      = 480  ,
+  WIFIPHYRX_EHT_SIG_USR_OFDMA_E                            = 481  ,
+  WIFISCHEDULER_IU_TEMPLATE_ID_E                           = 482  ,
+  WIFIPHYRX_PKT_END_PART1_E                                = 483  ,
+  WIFIMACTX_EXPECT_NDP_RECEPTION_E                         = 484  ,
+  WIFIMACTX_SECURE_LTF_SEQ_PTR_E                           = 485  ,
+  WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E                    = 486  ,
+  WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E                         = 487  ,
+  WIFIPHYRX___RESERVED_G_0014                              = 488  ,
+  WIFIPHYTX_LOCATION_E                                     = 489  ,
+  WIFIPHYTX___RESERVED_G_0014                              = 490  ,
+  WIFIMPDU_LENGTH_STRUCTS_START_E                          = 491  ,
+  WIFIMACTX_EHT_SIG_USR_SU_E                               = 492  ,
+  WIFIMACTX_EHT_SIG_USR_MU_MIMO_E                          = 493  ,
+  WIFIPHYRX_EHT_SIG_USR_SU_E                               = 494  ,
+  WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E                          = 495  ,
+  WIFIPHYRX_GENERIC_U_SIG_E                                = 496  ,
+  WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E                       = 497  ,
+  WIFIOVERWRITE_RESP_START_E                               = 498  ,
+  WIFIOVERWRITE_RESP_PREAMBLE_INFO_E                       = 499  ,
+  WIFIOVERWRITE_RESP_FRAME_INFO_E                          = 500  ,
+  WIFIOVERWRITE_RESP_END_E                                 = 501  ,
+  WIFIRXPCU_EARLY_RX_INDICATION_E                          = 502  ,
+  WIFIMON_DROP_E                                           = 503  ,
+  WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E                       = 504  ,
+  WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E                   = 505  ,
+  WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E                     = 506  ,
+  WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E                   = 507  ,
+  WIFIMACTX_PREFETCH_CV_DMA_E                              = 508  ,
+  WIFIMACTX_PREFETCH_CV_PER_USER_E                         = 509  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E          = 510  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E                      = 511  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E                    = 512  ,
+  WIFIRANGING_USER_DETAILS_E                               = 513  ,
+  WIFIPHYTX_CV_CORR_STATUS_E                               = 514  ,
+  WIFIPHYTX_CV_CORR_COMMON_E                               = 515  ,
+  WIFIPHYTX_CV_CORR_USER_E                                 = 516  ,
+  WIFIMACTX_CV_CORR_COMMON_E                               = 517  ,
+  WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E                       = 518  ,
+  WIFIBW_PUNCTURE_EVAL_WRAPPER_E                           = 519  ,
+  WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E                      = 520  ,
+  WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E                      = 521  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E                      = 522  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E                  = 523  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT2_E                        = 524  ,
+  WIFIFW2SW_MON_E                                          = 525  ,
+  WIFIWSI_DIRECT_MESSAGE_E                                 = 526  ,
+  WIFIMACTX_EMLSR_PRE_SWITCH_E                             = 527  ,
+  WIFIMACTX_EMLSR_SWITCH_E                                 = 528  ,
+  WIFIMACTX_EMLSR_SWITCH_BACK_E                            = 529  ,
+  WIFIPHYTX_EMLSR_SWITCH_ACK_E                             = 530  ,
+  WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E                        = 531  ,
+  WIFIEAD_COMMAND_E                                        = 532  ,
+  WIFIEAD_LEGACY_STATUS_CONTROL_E                          = 533  ,
+  WIFIEAD_LEGACY_INTERRUPT_CONTROL_E                       = 534  ,
+  WIFITPI_TX_INITIALIZATION_CONFIG_E                       = 535  ,
+  WIFITPI_ENABLE_RESPONSE_TIMEOUT_E                        = 536  ,
+  WIFITPI_LEGACY_STATUS_CONTROL_E                          = 537  ,
+  WIFITPI_LEGACY_INTERRUPT_CONTROL_E                       = 538  ,
+  WIFITPI_MPDU_START_E                                     = 539  ,
+  WIFITPI_MPDU_CONTINUATION_E                              = 540  ,
+  WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E               = 541  ,
+  WIFITPI_SEND_TLV_TO_PHYTX_E                              = 542  ,
+  WIFITPI_TX_START_TIME_ARRIVED_E                          = 543  ,
+  WIFITPI_STATUS_E                                         = 544  ,
+  WIFITPI_ERROR_STATUS_E                                   = 545  ,
+  WIFITPI_TIMESTAMP_STATUS_E                               = 546  ,
+  WIFIRPI_SEND_TLV_TO_PHYRX_E                              = 547  ,
+  WIFIRPI_LEGACY_STATUS_CONTROL_E                          = 548  ,
+  WIFIRPI_LEGACY_INTERRUPT_CONTROL_E                       = 549  ,
+  WIFIRPI_STATUS_E                                         = 550  ,
+  WIFIRPI_ERROR_STATUS_E                                   = 551  ,
+  WIFIRPI_TIMESTAMP_STATUS_E                               = 552  ,
+  WIFIRPI_RX_FRAME_UPDATE_STATUS_E                         = 553  ,
+  WIFITCC_PUSH_TRANSMIT_COMMAND_E                          = 554  ,
+  WIFITCC_TLV_FETCH_E                                      = 555  ,
+  WIFITCC_LEGACY_STATUS_CONTROL_E                          = 556  ,
+  WIFITCC_LEGACY_INTERRUPT_CONTROL_E                       = 557  ,
+  WIFITCC_STATUS_E                                         = 558  ,
+  WIFITCC_ERROR_STATUS_E                                   = 559  ,
+  WIFITCC_TIMESTAMP_STATUS_E                               = 560  ,
+  WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E                      = 561  ,
+  WIFITCC_SCHEDULER_CMD_E                                  = 562  ,
+  WIFITCC_BURST_CMD_AVAILABLE_E                            = 563  ,
+  WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E                    = 564  ,
+  WIFIEAD_RING_AIR_TIME_REFERENCE_E                        = 565  ,
+  WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E                        = 566  ,
+  WIFIRPI_WRITE_INFO_TO_EXT_MEM_E                          = 567  ,
+  WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E                        = 568  ,
+  WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E                        = 569  ,
+  WIFITPI_SEND_CBF_DATA_TO_PHYTX_E                         = 570  ,
+  WIFITPI_SEND_CTLV_44_TO_PHYTX_E                          = 571  ,
+  WIFITCC_FES_END_MESSAGE_E                                = 572  ,
+  WIFITPI_TX_FRAME_UPDATE_STATUS_E                         = 573  ,
+  WIFITPI_DISABLE_RESPONSE_TIMEOUT_E                       = 574  ,
+  WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E                   = 575  ,
+  WIFIEAD_MSDU_STATUS_START_E                              = 576  ,
+  WIFIEAD_MSDU_STATUS_DETAILS_E                            = 577  ,
+  WIFIMACTX_UHR_SIG_USR_SU_E                               = 578  ,
+  WIFIMACTX_UHR_SIG_USR_MU_MIMO_E                          = 579  ,
+  WIFIMACTX_UHR_SIG_USR_OFDMA_E                            = 580  ,
+  WIFIMACTX_ELR_SIG_UHR_SU_E                               = 581  ,
+  WIFICOEX_BLACKOUT_DETAILS_E                              = 582  ,
+  WIFIPEER_BLACKOUT_DETAILS_E                              = 583  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E             = 584  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_E                           = 585  ,
+  WIFIHDR_CTRL_PROT_MPDU_START_E                           = 586  ,
+  WIFIHDR_CTRL_PROT_DATA_E                                 = 587  ,
+  WIFIHDR_CTRL_PROT_MPDU_END_E                             = 588  ,
+  WIFIHDR_CTRL_PROT_MIC_STATUS_E                           = 589  ,
+  WIFIHDR_CTRL_PROT_PEER_INFO_E                            = 590  ,
+  WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E                      = 591  ,
+  WIFIMACTX_U_SIG_UHR_ELR_SU_E                             = 592  ,
+  WIFIMACTX_U_SIG_UHR_COBF_E                               = 593  ,
+  WIFIMACTX_UHR_SIG_USR_COBF_E                             = 594  ,
+  WIFISPARE_REUSE_TAG_0_E                                  = 595  ,
+  WIFISPARE_REUSE_TAG_1_E                                  = 596  ,
+  WIFISPARE_REUSE_TAG_2_E                                  = 597  ,
+  WIFISPARE_REUSE_TAG_3_E                                  = 598  ,
+  WIFISPARE_REUSE_TAG_4_E                                  = 599  ,
+  WIFISPARE_REUSE_TAG_5_E                                  = 600  ,
+  WIFISPARE_REUSE_TAG_6_E                                  = 601  ,
+  WIFISPARE_REUSE_TAG_7_E                                  = 602  ,
+  WIFISPARE_REUSE_TAG_8_E                                  = 603  ,
+  WIFISPARE_REUSE_TAG_9_E                                  = 604  ,
+  WIFISPARE_REUSE_TAG_10_E                                 = 605  ,
+  WIFISPARE_REUSE_TAG_11_E                                 = 606  ,
+  WIFISPARE_REUSE_TAG_12_E                                 = 607  ,
+  WIFISPARE_REUSE_TAG_13_E                                 = 608  ,
+  WIFISPARE_REUSE_TAG_14_E                                 = 609  ,
+  WIFISPARE_REUSE_TAG_15_E                                 = 610  ,
+  WIFISPARE_REUSE_TAG_16_E                                 = 611  ,
+  WIFISPARE_REUSE_TAG_17_E                                 = 612  ,
+  WIFISPARE_REUSE_TAG_18_E                                 = 613  ,
+  WIFISPARE_REUSE_TAG_19_E                                 = 614  ,
+  WIFISPARE_REUSE_TAG_20_E                                 = 615  ,
+  WIFISPARE_REUSE_TAG_21_E                                 = 616  ,
+  WIFISPARE_REUSE_TAG_22_E                                 = 617  ,
+  WIFISPARE_REUSE_TAG_23_E                                 = 618  ,
+  WIFISPARE_REUSE_TAG_24_E                                 = 619  ,
+  WIFISPARE_REUSE_TAG_25_E                                 = 620  ,
+  WIFISPARE_REUSE_TAG_26_E                                 = 621  ,
+  WIFISPARE_REUSE_TAG_27_E                                 = 622  ,
+  WIFISPARE_REUSE_TAG_28_E                                 = 623  ,
+  WIFISPARE_REUSE_TAG_29_E                                 = 624  ,
+  WIFISPARE_REUSE_TAG_30_E                                 = 625  ,
+  WIFISPARE_REUSE_TAG_31_E                                 = 626  ,
+  WIFISPARE_REUSE_TAG_32_E                                 = 627  ,
+  WIFISPARE_REUSE_TAG_33_E                                 = 628  ,
+  WIFISPARE_REUSE_TAG_34_E                                 = 629  ,
+  WIFISPARE_REUSE_TAG_35_E                                 = 630  ,
+  WIFISPARE_REUSE_TAG_36_E                                 = 631  ,
+  WIFISPARE_REUSE_TAG_37_E                                 = 632  ,
+  WIFISPARE_REUSE_TAG_38_E                                 = 633  ,
+  WIFISPARE_REUSE_TAG_39_E                                 = 634  ,
+  WIFISPARE_REUSE_TAG_40_E                                 = 635  ,
+  WIFISPARE_REUSE_TAG_41_E                                 = 636  ,
+  WIFISPARE_REUSE_TAG_42_E                                 = 637  ,
+  WIFISPARE_REUSE_TAG_43_E                                 = 638  ,
+  WIFISPARE_REUSE_TAG_44_E                                 = 639  ,
+  WIFISPARE_REUSE_TAG_45_E                                 = 640  ,
+  WIFISPARE_REUSE_TAG_46_E                                 = 641  ,
+  WIFISPARE_REUSE_TAG_47_E                                 = 642  ,
+  WIFISPARE_REUSE_TAG_48_E                                 = 643  ,
+  WIFISPARE_REUSE_TAG_49_E                                 = 644  ,
+  WIFISPARE_REUSE_TAG_50_E                                 = 645  ,
+  WIFISPARE_REUSE_TAG_51_E                                 = 646  ,
+  WIFISPARE_REUSE_TAG_52_E                                 = 647  ,
+  WIFISPARE_REUSE_TAG_53_E                                 = 648  ,
+  WIFISPARE_REUSE_TAG_54_E                                 = 649  ,
+  WIFISPARE_REUSE_TAG_55_E                                 = 650  ,
+  WIFISPARE_REUSE_TAG_56_E                                 = 651  ,
+  WIFISPARE_REUSE_TAG_57_E                                 = 652  ,
+  WIFISPARE_REUSE_TAG_58_E                                 = 653  ,
+  WIFISPARE_REUSE_TAG_59_E                                 = 654  ,
+  WIFISPARE_REUSE_TAG_60_E                                 = 655  ,
+  WIFISPARE_REUSE_TAG_61_E                                 = 656  ,
+  WIFISPARE_REUSE_TAG_62_E                                 = 657  ,
+  WIFISPARE_REUSE_TAG_63_E                                 = 658  ,
+  WIFISPARE_REUSE_TAG_64_E                                 = 659  ,
+  WIFISPARE_REUSE_TAG_65_E                                 = 660  ,
+  WIFISPARE_REUSE_TAG_66_E                                 = 661  ,
+  WIFISPARE_REUSE_TAG_67_E                                 = 662  ,
+  WIFISPARE_REUSE_TAG_68_E                                 = 663  ,
+  WIFISPARE_REUSE_TAG_69_E                                 = 664  ,
+  WIFISPARE_REUSE_TAG_70_E                                 = 665  ,
+  WIFISPARE_REUSE_TAG_71_E                                 = 666  ,
+  WIFISPARE_REUSE_TAG_72_E                                 = 667  ,
+  WIFISPARE_REUSE_TAG_73_E                                 = 668  ,
+  WIFISPARE_REUSE_TAG_74_E                                 = 669  ,
+  WIFISPARE_REUSE_TAG_75_E                                 = 670  ,
+  WIFISPARE_REUSE_TAG_76_E                                 = 671  ,
+  WIFISPARE_REUSE_TAG_77_E                                 = 672  ,
+  WIFISPARE_REUSE_TAG_78_E                                 = 673  ,
+  WIFISPARE_REUSE_TAG_79_E                                 = 674  ,
+  WIFISPARE_REUSE_TAG_80_E                                 = 675  ,
+  WIFISPARE_REUSE_TAG_81_E                                 = 676  ,
+  WIFISPARE_REUSE_TAG_82_E                                 = 677  ,
+  WIFISPARE_REUSE_TAG_83_E                                 = 678  ,
+  WIFISPARE_REUSE_TAG_84_E                                 = 679  ,
+  WIFISPARE_REUSE_TAG_85_E                                 = 680  ,
+  WIFISPARE_REUSE_TAG_86_E                                 = 681  ,
+  WIFISPARE_REUSE_TAG_87_E                                 = 682  ,
+  WIFISPARE_REUSE_TAG_88_E                                 = 683  ,
+  WIFISPARE_REUSE_TAG_89_E                                 = 684  ,
+  WIFISPARE_REUSE_TAG_90_E                                 = 685  ,
+  WIFISPARE_REUSE_TAG_91_E                                 = 686  ,
+  WIFISPARE_REUSE_TAG_92_E                                 = 687  ,
+  WIFISPARE_REUSE_TAG_93_E                                 = 688  ,
+  WIFISPARE_REUSE_TAG_94_E                                 = 689  ,
+  WIFISPARE_REUSE_TAG_95_E                                 = 690  ,
+  WIFISPARE_REUSE_TAG_96_E                                 = 691  ,
+  WIFISPARE_REUSE_TAG_97_E                                 = 692  ,
+  WIFISPARE_REUSE_TAG_98_E                                 = 693  ,
+  WIFISPARE_REUSE_TAG_99_E                                 = 694  ,
+  WIFISPARE_REUSE_TAG_100_E                                = 695  ,
+  WIFISPARE_REUSE_TAG_101_E                                = 696  ,
+  WIFISPARE_REUSE_TAG_102_E                                = 697  ,
+  WIFISPARE_REUSE_TAG_103_E                                = 698  ,
+  WIFISPARE_REUSE_TAG_104_E                                = 699  ,
+  WIFISPARE_REUSE_TAG_105_E                                = 700  ,
+  WIFISPARE_REUSE_TAG_106_E                                = 701  ,
+  WIFISPARE_REUSE_TAG_107_E                                = 702  ,
+  WIFISPARE_REUSE_TAG_108_E                                = 703  ,
+  WIFISPARE_REUSE_TAG_109_E                                = 704  ,
+  WIFISPARE_REUSE_TAG_110_E                                = 705  ,
+  WIFISPARE_REUSE_TAG_111_E                                = 706  ,
+  WIFISPARE_REUSE_TAG_112_E                                = 707  ,
+  WIFISPARE_REUSE_TAG_113_E                                = 708  ,
+  WIFISPARE_REUSE_TAG_114_E                                = 709  ,
+  WIFISPARE_REUSE_TAG_115_E                                = 710  ,
+  WIFISPARE_REUSE_TAG_116_E                                = 711  ,
+  WIFISPARE_REUSE_TAG_117_E                                = 712  ,
+  WIFISPARE_REUSE_TAG_118_E                                = 713  ,
+  WIFISPARE_REUSE_TAG_119_E                                = 714  ,
+  WIFISPARE_REUSE_TAG_120_E                                = 715  ,
+  WIFISPARE_REUSE_TAG_121_E                                = 716  ,
+  WIFISPARE_REUSE_TAG_122_E                                = 717  ,
+  WIFISPARE_REUSE_TAG_123_E                                = 718  ,
+  WIFISPARE_REUSE_TAG_124_E                                = 719  ,
+  WIFISPARE_REUSE_TAG_125_E                                = 720  ,
+  WIFISPARE_REUSE_TAG_126_E                                = 721  ,
+  WIFISPARE_REUSE_TAG_127_E                                = 722  ,
+  WIFISPARE_REUSE_TAG_128_E                                = 723  ,
+  WIFISPARE_REUSE_TAG_129_E                                = 724  ,
+  WIFISPARE_REUSE_TAG_130_E                                = 725  ,
+  WIFISPARE_REUSE_TAG_131_E                                = 726  ,
+  WIFISPARE_REUSE_TAG_132_E                                = 727  ,
+  WIFISPARE_REUSE_TAG_133_E                                = 728  ,
+  WIFISPARE_REUSE_TAG_134_E                                = 729  ,
+  WIFISPARE_REUSE_TAG_135_E                                = 730  ,
+  WIFISPARE_REUSE_TAG_136_E                                = 731  ,
+  WIFISPARE_REUSE_TAG_137_E                                = 732  ,
+  WIFISPARE_REUSE_TAG_138_E                                = 733  ,
+  WIFISPARE_REUSE_TAG_139_E                                = 734  ,
+  WIFISPARE_REUSE_TAG_140_E                                = 735  ,
+  WIFISPARE_REUSE_TAG_141_E                                = 736  ,
+  WIFISPARE_REUSE_TAG_142_E                                = 737  ,
+  WIFISPARE_REUSE_TAG_143_E                                = 738  ,
+  WIFISPARE_REUSE_TAG_144_E                                = 739  ,
+  WIFISPARE_REUSE_TAG_145_E                                = 740  ,
+  WIFISPARE_REUSE_TAG_146_E                                = 741  ,
+  WIFISPARE_REUSE_TAG_147_E                                = 742  ,
+  WIFISPARE_REUSE_TAG_148_E                                = 743  ,
+  WIFISPARE_REUSE_TAG_149_E                                = 744  ,
+  WIFISPARE_REUSE_TAG_150_E                                = 745  ,
+  WIFISPARE_REUSE_TAG_151_E                                = 746  ,
+  WIFISPARE_REUSE_TAG_152_E                                = 747  ,
+  WIFISPARE_REUSE_TAG_153_E                                = 748  ,
+  WIFISPARE_REUSE_TAG_154_E                                = 749  ,
+  WIFISPARE_REUSE_TAG_155_E                                = 750  ,
+  WIFISPARE_REUSE_TAG_156_E                                = 751  ,
+  WIFISPARE_REUSE_TAG_157_E                                = 752  ,
+  WIFISPARE_REUSE_TAG_158_E                                = 753  ,
+  WIFISPARE_REUSE_TAG_159_E                                = 754  ,
+  WIFISPARE_REUSE_TAG_160_E                                = 755  ,
+  WIFISPARE_REUSE_TAG_161_E                                = 756  ,
+  WIFISPARE_REUSE_TAG_162_E                                = 757  ,
+  WIFISPARE_REUSE_TAG_163_E                                = 758  ,
+  WIFISPARE_REUSE_TAG_164_E                                = 759  ,
+  WIFISPARE_REUSE_TAG_165_E                                = 760  ,
+  WIFISPARE_REUSE_TAG_166_E                                = 761  ,
+  WIFISPARE_REUSE_TAG_167_E                                = 762  ,
+  WIFISPARE_REUSE_TAG_168_E                                = 763  ,
+  WIFISPARE_REUSE_TAG_169_E                                = 764  ,
+  WIFISPARE_REUSE_TAG_170_E                                = 765  ,
+  WIFISPARE_REUSE_TAG_171_E                                = 766  ,
+  WIFISPARE_REUSE_TAG_172_E                                = 767  ,
+  WIFISPARE_REUSE_TAG_173_E                                = 768  ,
+  WIFISPARE_REUSE_TAG_174_E                                = 769  ,
+  WIFISPARE_REUSE_TAG_175_E                                = 770  ,
+  WIFISPARE_REUSE_TAG_176_E                                = 771  ,
+  WIFISPARE_REUSE_TAG_177_E                                = 772  ,
+  WIFISPARE_REUSE_TAG_178_E                                = 773  ,
+  WIFISPARE_REUSE_TAG_179_E                                = 774  ,
+  WIFISPARE_REUSE_TAG_180_E                                = 775  ,
+  WIFISPARE_REUSE_TAG_181_E                                = 776  ,
+  WIFISPARE_REUSE_TAG_182_E                                = 777  ,
+  WIFISPARE_REUSE_TAG_183_E                                = 778  ,
+  WIFISPARE_REUSE_TAG_184_E                                = 779  ,
+  WIFISPARE_REUSE_TAG_185_E                                = 780  ,
+  WIFISPARE_REUSE_TAG_186_E                                = 781  ,
+  WIFISPARE_REUSE_TAG_187_E                                = 782  ,
+  WIFISPARE_REUSE_TAG_188_E                                = 783  ,
+  WIFISPARE_REUSE_TAG_189_E                                = 784  ,
+  WIFISPARE_REUSE_TAG_190_E                                = 785  ,
+  WIFISPARE_REUSE_TAG_191_E                                = 786  ,
+  WIFISPARE_REUSE_TAG_192_E                                = 787  ,
+  WIFISPARE_REUSE_TAG_193_E                                = 788  ,
+  WIFISPARE_REUSE_TAG_194_E                                = 789  ,
+  WIFISPARE_REUSE_TAG_195_E                                = 790  ,
+  WIFISPARE_REUSE_TAG_196_E                                = 791  ,
+  WIFISPARE_REUSE_TAG_197_E                                = 792  ,
+  WIFISPARE_REUSE_TAG_198_E                                = 793  ,
+  WIFISPARE_REUSE_TAG_199_E                                = 794  ,
+  WIFISPARE_REUSE_TAG_200_E                                = 795  ,
+  WIFISPARE_REUSE_TAG_201_E                                = 796  ,
+  WIFISPARE_REUSE_TAG_202_E                                = 797  ,
+  WIFISPARE_REUSE_TAG_203_E                                = 798  ,
+  WIFISPARE_REUSE_TAG_204_E                                = 799  ,
+  WIFISPARE_REUSE_TAG_205_E                                = 800  ,
+  WIFISPARE_REUSE_TAG_206_E                                = 801  ,
+  WIFISPARE_REUSE_TAG_207_E                                = 802  ,
+  WIFISPARE_REUSE_TAG_208_E                                = 803  ,
+  WIFISPARE_REUSE_TAG_209_E                                = 804  ,
+  WIFISPARE_REUSE_TAG_210_E                                = 805  ,
+  WIFISPARE_REUSE_TAG_211_E                                = 806  ,
+  WIFISPARE_REUSE_TAG_212_E                                = 807  ,
+  WIFISPARE_REUSE_TAG_213_E                                = 808  ,
+  WIFISPARE_REUSE_TAG_214_E                                = 809  ,
+  WIFISPARE_REUSE_TAG_215_E                                = 810  ,
+  WIFISPARE_REUSE_TAG_216_E                                = 811  ,
+  WIFISPARE_REUSE_TAG_217_E                                = 812  ,
+  WIFISPARE_REUSE_TAG_218_E                                = 813  ,
+  WIFISPARE_REUSE_TAG_219_E                                = 814  ,
+  WIFISPARE_REUSE_TAG_220_E                                = 815  ,
+  WIFISPARE_REUSE_TAG_221_E                                = 816  ,
+  WIFISPARE_REUSE_TAG_222_E                                = 817  ,
+  WIFISPARE_REUSE_TAG_223_E                                = 818  ,
+  WIFISPARE_REUSE_TAG_224_E                                = 819  ,
+  WIFISPARE_REUSE_TAG_225_E                                = 820  ,
+  WIFISPARE_REUSE_TAG_226_E                                = 821  ,
+  WIFISPARE_REUSE_TAG_227_E                                = 822  ,
+  WIFISPARE_REUSE_TAG_228_E                                = 823  ,
+  WIFISPARE_REUSE_TAG_229_E                                = 824  ,
+  WIFISPARE_REUSE_TAG_230_E                                = 825  ,
+  WIFISPARE_REUSE_TAG_231_E                                = 826  ,
+  WIFISPARE_REUSE_TAG_232_E                                = 827  ,
+  WIFISPARE_REUSE_TAG_233_E                                = 828  ,
+  WIFISPARE_REUSE_TAG_234_E                                = 829  ,
+  WIFISPARE_REUSE_TAG_235_E                                = 830  ,
+  WIFISPARE_REUSE_TAG_236_E                                = 831  ,
+  WIFISPARE_REUSE_TAG_237_E                                = 832  ,
+  WIFISPARE_REUSE_TAG_238_E                                = 833  ,
+  WIFISPARE_REUSE_TAG_239_E                                = 834  ,
+  WIFISPARE_REUSE_TAG_240_E                                = 835  ,
+  WIFISPARE_REUSE_TAG_241_E                                = 836  ,
+  WIFISPARE_REUSE_TAG_242_E                                = 837  ,
+  WIFISPARE_REUSE_TAG_243_E                                = 838  ,
+  WIFISPARE_REUSE_TAG_244_E                                = 839  ,
+  WIFISPARE_REUSE_TAG_245_E                                = 840  ,
+  WIFISPARE_REUSE_TAG_246_E                                = 841  ,
+  WIFISPARE_REUSE_TAG_247_E                                = 842  ,
+  WIFISPARE_REUSE_TAG_248_E                                = 843  ,
+  WIFISPARE_REUSE_TAG_249_E                                = 844  ,
+  WIFISPARE_REUSE_TAG_250_E                                = 845  ,
+  WIFISPARE_REUSE_TAG_251_E                                = 846  ,
+  WIFISPARE_REUSE_TAG_252_E                                = 847  ,
+  WIFISPARE_REUSE_TAG_253_E                                = 848  ,
+  WIFISPARE_REUSE_TAG_254_E                                = 849  ,
+  WIFISPARE_REUSE_TAG_255_E                                = 850  ,
+  WIFISPARE_REUSE_TAG_256_E                                = 851  ,
+  WIFISPARE_REUSE_TAG_257_E                                = 852  ,
+  WIFISPARE_REUSE_TAG_258_E                                = 853  ,
+  WIFISPARE_REUSE_TAG_259_E                                = 854  ,
+  WIFISPARE_REUSE_TAG_260_E                                = 855  ,
+  WIFISPARE_REUSE_TAG_261_E                                = 856  ,
+  WIFISPARE_REUSE_TAG_262_E                                = 857  ,
+  WIFISPARE_REUSE_TAG_263_E                                = 858  ,
+  WIFISPARE_REUSE_TAG_264_E                                = 859  ,
+  WIFISPARE_REUSE_TAG_265_E                                = 860  ,
+  WIFISPARE_REUSE_TAG_266_E                                = 861  ,
+  WIFISPARE_REUSE_TAG_267_E                                = 862  ,
+  WIFISPARE_REUSE_TAG_268_E                                = 863  ,
+  WIFISPARE_REUSE_TAG_269_E                                = 864  ,
+  WIFISPARE_REUSE_TAG_270_E                                = 865  ,
+  WIFISPARE_REUSE_TAG_271_E                                = 866  ,
+  WIFISPARE_REUSE_TAG_272_E                                = 867  ,
+  WIFISPARE_REUSE_TAG_273_E                                = 868  ,
+  WIFISPARE_REUSE_TAG_274_E                                = 869  ,
+  WIFISPARE_REUSE_TAG_275_E                                = 870  ,
+  WIFISPARE_REUSE_TAG_276_E                                = 871  ,
+  WIFISPARE_REUSE_TAG_277_E                                = 872  ,
+  WIFISPARE_REUSE_TAG_278_E                                = 873  ,
+  WIFISPARE_REUSE_TAG_279_E                                = 874  ,
+  WIFISPARE_REUSE_TAG_280_E                                = 875  ,
+  WIFISPARE_REUSE_TAG_281_E                                = 876  ,
+  WIFISPARE_REUSE_TAG_282_E                                = 877  ,
+  WIFISPARE_REUSE_TAG_283_E                                = 878  ,
+  WIFISPARE_REUSE_TAG_284_E                                = 879  ,
+  WIFISPARE_REUSE_TAG_285_E                                = 880  ,
+  WIFISPARE_REUSE_TAG_286_E                                = 881  ,
+  WIFISPARE_REUSE_TAG_287_E                                = 882  ,
+  WIFISPARE_REUSE_TAG_288_E                                = 883  ,
+  WIFISPARE_REUSE_TAG_289_E                                = 884  ,
+  WIFISPARE_REUSE_TAG_290_E                                = 885  ,
+  WIFISPARE_REUSE_TAG_291_E                                = 886  ,
+  WIFISPARE_REUSE_TAG_292_E                                = 887  ,
+  WIFISPARE_REUSE_TAG_293_E                                = 888  ,
+  WIFISPARE_REUSE_TAG_294_E                                = 889  ,
+  WIFISPARE_REUSE_TAG_295_E                                = 890  ,
+  WIFISPARE_REUSE_TAG_296_E                                = 891  ,
+  WIFISPARE_REUSE_TAG_297_E                                = 892  ,
+  WIFISPARE_REUSE_TAG_298_E                                = 893  ,
+  WIFISPARE_REUSE_TAG_299_E                                = 894  ,
+  WIFISPARE_REUSE_TAG_300_E                                = 895  ,
+  WIFISPARE_REUSE_TAG_301_E                                = 896  ,
+  WIFISPARE_REUSE_TAG_302_E                                = 897  ,
+  WIFISPARE_REUSE_TAG_303_E                                = 898  ,
+  WIFISPARE_REUSE_TAG_304_E                                = 899  ,
+  WIFISPARE_REUSE_TAG_305_E                                = 900  ,
+  WIFISPARE_REUSE_TAG_306_E                                = 901  ,
+  WIFISPARE_REUSE_TAG_307_E                                = 902  ,
+  WIFISPARE_REUSE_TAG_308_E                                = 903  ,
+  WIFISPARE_REUSE_TAG_309_E                                = 904  ,
+  WIFISPARE_REUSE_TAG_310_E                                = 905  ,
+  WIFISPARE_REUSE_TAG_311_E                                = 906  ,
+  WIFISPARE_REUSE_TAG_312_E                                = 907  ,
+  WIFISPARE_REUSE_TAG_313_E                                = 908  ,
+  WIFISPARE_REUSE_TAG_314_E                                = 909  ,
+  WIFISPARE_REUSE_TAG_315_E                                = 910  ,
+  WIFISPARE_REUSE_TAG_316_E                                = 911  ,
+  WIFISPARE_REUSE_TAG_317_E                                = 912  ,
+  WIFISPARE_REUSE_TAG_318_E                                = 913  ,
+  WIFISPARE_REUSE_TAG_319_E                                = 914  ,
+  WIFISPARE_REUSE_TAG_320_E                                = 915  ,
+  WIFISPARE_REUSE_TAG_321_E                                = 916  ,
+  WIFISPARE_REUSE_TAG_322_E                                = 917  ,
+  WIFISPARE_REUSE_TAG_323_E                                = 918  ,
+  WIFISPARE_REUSE_TAG_324_E                                = 919  ,
+  WIFISPARE_REUSE_TAG_325_E                                = 920  ,
+  WIFISPARE_REUSE_TAG_326_E                                = 921  ,
+  WIFISPARE_REUSE_TAG_327_E                                = 922  ,
+  WIFISPARE_REUSE_TAG_328_E                                = 923  ,
+  WIFISPARE_REUSE_TAG_329_E                                = 924  ,
+  WIFISPARE_REUSE_TAG_330_E                                = 925  ,
+  WIFISPARE_REUSE_TAG_331_E                                = 926  ,
+  WIFISPARE_REUSE_TAG_332_E                                = 927  ,
+  WIFISPARE_REUSE_TAG_333_E                                = 928  ,
+  WIFISPARE_REUSE_TAG_334_E                                = 929  ,
+  WIFISPARE_REUSE_TAG_335_E                                = 930  ,
+  WIFISPARE_REUSE_TAG_336_E                                = 931  ,
+  WIFISPARE_REUSE_TAG_337_E                                = 932  ,
+  WIFISPARE_REUSE_TAG_338_E                                = 933  ,
+  WIFISPARE_REUSE_TAG_339_E                                = 934  ,
+  WIFISPARE_REUSE_TAG_340_E                                = 935  ,
+  WIFISPARE_REUSE_TAG_341_E                                = 936  ,
+  WIFISPARE_REUSE_TAG_342_E                                = 937  ,
+  WIFISPARE_REUSE_TAG_343_E                                = 938  ,
+  WIFISPARE_REUSE_TAG_344_E                                = 939  ,
+  WIFISPARE_REUSE_TAG_345_E                                = 940  ,
+  WIFISPARE_REUSE_TAG_346_E                                = 941  ,
+  WIFISPARE_REUSE_TAG_347_E                                = 942  ,
+  WIFISPARE_REUSE_TAG_348_E                                = 943  ,
+  WIFISPARE_REUSE_TAG_349_E                                = 944  ,
+  WIFISPARE_REUSE_TAG_350_E                                = 945  ,
+  WIFISPARE_REUSE_TAG_351_E                                = 946  ,
+  WIFISPARE_REUSE_TAG_352_E                                = 947  ,
+  WIFISPARE_REUSE_TAG_353_E                                = 948  ,
+  WIFISPARE_REUSE_TAG_354_E                                = 949  ,
+  WIFISPARE_REUSE_TAG_355_E                                = 950  ,
+  WIFISPARE_REUSE_TAG_356_E                                = 951  ,
+  WIFISPARE_REUSE_TAG_357_E                                = 952  ,
+  WIFISPARE_REUSE_TAG_358_E                                = 953  ,
+  WIFISPARE_REUSE_TAG_359_E                                = 954  ,
+  WIFISPARE_REUSE_TAG_360_E                                = 955  ,
+  WIFISPARE_REUSE_TAG_361_E                                = 956  ,
+  WIFISPARE_REUSE_TAG_362_E                                = 957  ,
+  WIFISPARE_REUSE_TAG_363_E                                = 958  ,
+  WIFISPARE_REUSE_TAG_364_E                                = 959  ,
+  WIFISPARE_REUSE_TAG_365_E                                = 960  ,
+  WIFISPARE_REUSE_TAG_366_E                                = 961  ,
+  WIFISPARE_REUSE_TAG_367_E                                = 962  ,
+  WIFISPARE_REUSE_TAG_368_E                                = 963  ,
+  WIFISPARE_REUSE_TAG_369_E                                = 964  ,
+  WIFISPARE_REUSE_TAG_370_E                                = 965  ,
+  WIFISPARE_REUSE_TAG_371_E                                = 966  ,
+  WIFISPARE_REUSE_TAG_372_E                                = 967  ,
+  WIFISPARE_REUSE_TAG_373_E                                = 968  ,
+  WIFISPARE_REUSE_TAG_374_E                                = 969  ,
+  WIFISPARE_REUSE_TAG_375_E                                = 970  ,
+  WIFISPARE_REUSE_TAG_376_E                                = 971  ,
+  WIFISPARE_REUSE_TAG_377_E                                = 972  ,
+  WIFISPARE_REUSE_TAG_378_E                                = 973  ,
+  WIFISPARE_REUSE_TAG_379_E                                = 974  ,
+  WIFISPARE_REUSE_TAG_380_E                                = 975  ,
+  WIFISPARE_REUSE_TAG_381_E                                = 976  ,
+  WIFISPARE_REUSE_TAG_382_E                                = 977  ,
+  WIFISPARE_REUSE_TAG_383_E                                = 978  ,
+  WIFISPARE_REUSE_TAG_384_E                                = 979  ,
+  WIFISPARE_REUSE_TAG_385_E                                = 980  ,
+  WIFISPARE_REUSE_TAG_386_E                                = 981  ,
+  WIFISPARE_REUSE_TAG_387_E                                = 982  ,
+  WIFISPARE_REUSE_TAG_388_E                                = 983  ,
+  WIFISPARE_REUSE_TAG_389_E                                = 984  ,
+  WIFISPARE_REUSE_TAG_390_E                                = 985  ,
+  WIFISPARE_REUSE_TAG_391_E                                = 986  ,
+  WIFISPARE_REUSE_TAG_392_E                                = 987  ,
+  WIFISPARE_REUSE_TAG_393_E                                = 988  ,
+  WIFISPARE_REUSE_TAG_394_E                                = 989  ,
+  WIFISPARE_REUSE_TAG_395_E                                = 990  ,
+  WIFISPARE_REUSE_TAG_396_E                                = 991  ,
+  WIFISPARE_REUSE_TAG_397_E                                = 992  ,
+  WIFISPARE_REUSE_TAG_398_E                                = 993  ,
+  WIFISPARE_REUSE_TAG_399_E                                = 994  ,
+  WIFISPARE_REUSE_TAG_400_E                                = 995  ,
+  WIFISPARE_REUSE_TAG_401_E                                = 996  ,
+  WIFISPARE_REUSE_TAG_402_E                                = 997  ,
+  WIFISPARE_REUSE_TAG_403_E                                = 998  ,
+  WIFISPARE_REUSE_TAG_404_E                                = 999  ,
+  WIFISPARE_REUSE_TAG_405_E                                = 1000  ,
+  WIFISPARE_REUSE_TAG_406_E                                = 1001  ,
+  WIFISPARE_REUSE_TAG_407_E                                = 1002  ,
+  WIFISPARE_REUSE_TAG_408_E                                = 1003  ,
+  WIFISPARE_REUSE_TAG_409_E                                = 1004  ,
+  WIFISPARE_REUSE_TAG_410_E                                = 1005  ,
+  WIFISPARE_REUSE_TAG_411_E                                = 1006  ,
+  WIFISPARE_REUSE_TAG_412_E                                = 1007  ,
+  WIFISPARE_REUSE_TAG_413_E                                = 1008  ,
+  WIFISPARE_REUSE_TAG_414_E                                = 1009  ,
+  WIFISPARE_REUSE_TAG_415_E                                = 1010  ,
+  WIFISPARE_REUSE_TAG_416_E                                = 1011  ,
+  WIFISPARE_REUSE_TAG_417_E                                = 1012  ,
+  WIFISPARE_REUSE_TAG_418_E                                = 1013  ,
+  WIFISPARE_REUSE_TAG_419_E                                = 1014  ,
+  WIFISPARE_REUSE_TAG_420_E                                = 1015  ,
+  WIFISPARE_REUSE_TAG_421_E                                = 1016  ,
+  WIFISPARE_REUSE_TAG_422_E                                = 1017  ,
+  WIFISPARE_REUSE_TAG_423_E                                = 1018  ,
+  WIFISPARE_REUSE_TAG_424_E                                = 1019  ,
+  WIFISPARE_REUSE_TAG_425_E                                = 1020  ,
+  WIFISPARE_REUSE_TAG_426_E                                = 1021
+} tlv_tag_def__e;
+
+typedef enum {
+  WIFI_EXT_PHYRX_DATA_E                                    = 1  ,
+  WIFI_EXT_PHYRX_ABORT_REQUEST_E                           = 3  ,
+  WIFI_EXT_MACTX_DATA_RESP_E                               = 5  ,
+  WIFI_EXT_MACTX_CBF_DONE_E                                = 7  ,
+  WIFI_EXT_RXPCU_TO_UCODE_START_E                          = 9  ,
+  WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E                 = 11  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E                 = 13  ,
+  WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E               = 15  ,
+  WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E                       = 17  ,
+  WIFI_EXT_PHYRX_PKT_END_20MHZ_E                           = 19  ,
+  WIFI_EXT_MACRX_CBF_DATA_REQUEST_E                        = 65  ,
+  WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E                  = 67  ,
+  WIFI_EXT_MACRX_ABORT_ACK_E                               = 69  ,
+  WIFI_EXT_MACRX_CHAIN_MASK_E                              = 71  ,
+  WIFI_EXT_MACRX_ABORT_REQUEST_E                           = 73  ,
+  WIFI_EXT_PHYTX_ABORT_ACK_E                               = 75  ,
+  WIFI_EXT_PHYTX_PKT_END_E                                 = 77  ,
+  WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E                       = 79  ,
+  WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E                      = 81  ,
+  WIFI_EXT_PHYTX_NAP_DONE_E                                = 83  ,
+  WIFI_EXT_PHYTX_ON_ACK_E                                  = 85  ,
+  WIFI_EXT_PHYTX_DEBUG16_E                                 = 87  ,
+  WIFI_EXT_MACTX_ABORT_ACK_E                               = 89  ,
+  WIFI_EXT_MACTX_PRE_PHY_DESC_E                            = 91  ,
+  WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E                      = 93  ,
+  WIFI_EXT_MACTX_USER_DESC_COMMON_E                        = 95  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_16_E                           = 97  ,
+  WIFI_EXT_MACTX_PHY_OFF_E                                 = 99  ,
+  WIFI_EXT_MACTX_SYNTH_OFF_E                               = 101  ,
+  WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E                     = 103  ,
+  WIFI_EXT_MACTX_L_SIG_A_E                                 = 105  ,
+  WIFI_EXT_MACTX_HT_SIG_E                                  = 107  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU20_E                          = 109  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_SU80_E                          = 111  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU20_E                          = 113  ,
+  WIFI_EXT_MACTX_VHT_SIG_B_MU80_E                          = 115  ,
+  WIFI_EXT_MACTX_SERVICE_E                                 = 117  ,
+  WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E                          = 119  ,
+  WIFI_EXT_MACTX_HE_SIG_B1_MU_E                            = 121  ,
+  WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E                         = 123  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_E                        = 125  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E                     = 127  ,
+  WIFI_EXT_MACTX_DEBUG_E                                   = 129  ,
+  WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E                   = 131  ,
+  WIFI_EXT_PHYRX_RSSI_HT_E                                 = 133  ,
+  WIFI_EXT_PHYRX_PKT_END_E                                 = 135  ,
+  WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E                       = 137  ,
+  WIFI_EXT_PHYRX_L_SIG_A_E                                 = 139  ,
+  WIFI_EXT_PHYRX_HT_SIG_E                                  = 141  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E                          = 143  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E                          = 145  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E                          = 147  ,
+  WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E                          = 149  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_SU_E                             = 151  ,
+  WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E                          = 153  ,
+  WIFI_EXT_PHYRX_HE_SIG_B2_MU_E                            = 155  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E                      = 157  ,
+  WIFI_EXT_PHYRX_DATA_DONE_E                               = 159  ,
+  WIFI_EXT_DUMMY_E                                         = 161  ,
+  WIFI_EXT_MPDU_LIMIT_E                                    = 163  ,
+  WIFI_EXT_OLE_BUF_STATUS_E                                = 165  ,
+  WIFI_EXT_PCU_PPDU_SETUP_END_E                            = 167  ,
+  WIFI_EXT_PCU_PPDU_SETUP_START_E                          = 169  ,
+  WIFI_EXT_PDG_RESPONSE_E                                  = 171  ,
+  WIFI_EXT_SCH_WAIT_INSTR_E                                = 173  ,
+  WIFI_EXT_PHYTX_LINK_STATE_E                              = 175  ,
+  WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E                      = 177  ,
+  WIFI_EXT_TQM_GEN_MPDUS_E                                 = 179  ,
+  WIFI_EXT_TQM_REMOVE_MPDU_E                               = 181  ,
+  WIFI_EXT_TQM_REMOVE_MSDU_E                               = 183  ,
+  WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E                      = 185  ,
+  WIFI_EXT_OFDMA_TRIGGER_DETAILS_E                         = 187  ,
+  WIFI_EXT_TX_FES_SETUP_E                                  = 189  ,
+  WIFI_EXT_EXPECTED_RESPONSE_E                             = 191  ,
+  WIFI_EXT_TX_MPDU_START_E                                 = 193  ,
+  WIFI_EXT_TX_MSDU_START_E                                 = 195  ,
+  WIFI_EXT_TXPCU_BUFFER_STATUS_E                           = 197  ,
+  WIFI_EXT_DATA_TO_TIME_CONFIG_E                           = 199  ,
+  WIFI_EXT_MPDU_INFO_E                                     = 201  ,
+  WIFI_EXT_TX_11AH_SETUP_E                                 = 203  ,
+  WIFI_EXT_TX_PEER_ENTRY_E                                 = 205  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_44_E                           = 207  ,
+  WIFI_EXT_TX_FLUSH_REQ_E                                  = 209  ,
+  WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E                      = 211  ,
+  WIFI_EXT_EXAMPLE_USER_CTLV_44_E                          = 213  ,
+  WIFI_EXT_TX_FES_STATUS_USER_PPDU_E                       = 215  ,
+  WIFI_EXT_TX_FES_STATUS_END_E                             = 217  ,
+  WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E                          = 219  ,
+  WIFI_EXT_RX_FRAME_BITMAP_ACK_E                           = 221  ,
+  WIFI_EXT_RX_START_PARAM_E                                = 223  ,
+  WIFI_EXT_RX_PPDU_END_E                                   = 225  ,
+  WIFI_EXT_RX_MPDU_END_E                                   = 227  ,
+  WIFI_EXT_RX_MSDU_END_E                                   = 229  ,
+  WIFI_EXT_RECEIVED_RESPONSE_INFO_E                        = 231  ,
+  WIFI_EXT_RX_HEADER_E                                     = 233  ,
+  WIFI_EXT_RX_FLUSH_E                                      = 235  ,
+  WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E                      = 237  ,
+  WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E                = 239  ,
+  WIFI_EXT_PCU_PPDU_SETUP_USER_E                           = 241  ,
+  WIFI_EXT_RX_PM_INFO_E                                    = 243  ,
+  WIFI_EXT_RX_PRE_PPDU_START_E                             = 245  ,
+  WIFI_EXT_TX_FES_SETUP_COMPLETE_E                         = 247  ,
+  WIFI_EXT_TXDMA_STOP_REQUEST_E                            = 249  ,
+  WIFI_EXT_RXPCU_USER_SETUP_E                              = 251  ,
+  WIFI_EXT_TQM_ACKED_MPDU_E                                = 253  ,
+  WIFI_EXT_COEX_TX_STATUS_E                                = 255  ,
+  WIFI_EXT_COEX_STATUS_BROADCAST_E                         = 257  ,
+  WIFI_EXT_RESPONSE_END_STATUS_E                           = 259  ,
+  WIFI_EXT_RECEIVED_TRIGGER_INFO_E                         = 261  ,
+  WIFI_EXT_RX_PPDU_ACK_REPORT_E                            = 263  ,
+  WIFI_EXT_SCH_COEX_STATUS_E                               = 265  ,
+  WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E          = 267  ,
+  WIFI_EXT_TX_FES_STATUS_START_PPDU_E                      = 269  ,
+  WIFI_EXT_TXPCU_PHYTX_DEBUG32_E                           = 271  ,
+  WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E                    = 273  ,
+  WIFI_EXT_WHO_ANCHOR_VALUE_E                              = 275  ,
+  WIFI_EXT_WHO_COMMIT_E                                    = 277  ,
+  WIFI_EXT_WHO_FLUSH_E                                     = 279  ,
+  WIFI_EXT_WHO_L2_PAYLOAD_E                                = 281  ,
+  WIFI_EXT_WHO_L3_INFO_E                                   = 283  ,
+  WIFI_EXT_WHO_L4_INFO_E                                   = 285  ,
+  WIFI_EXT_WHO_MSDU_MISC_E                                 = 287  ,
+  WIFI_EXT_WHO_PACKET_HDR_E                                = 289  ,
+  WIFI_EXT_WHO_PPDU_START_E                                = 291  ,
+  WIFI_EXT_WHO_WMAC_HEADER_PV0_E                           = 293  ,
+  WIFI_EXT_WHO_WMAC_IV_E                                   = 295  ,
+  WIFI_EXT_MPDU_INFO_BITMAP_E                              = 297  ,
+  WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E             = 299  ,
+  WIFI_EXT_TQM_ACKED_MPDU_STATUS_E                         = 301  ,
+  WIFI_EXT_TQM_LIST_GEN_DONE_E                             = 303  ,
+  WIFI_EXT_TX_LAST_MPDU_END_E                              = 305  ,
+  WIFI_EXT_PPDU_TX_END_E                                   = 307  ,
+  WIFI_EXT_MPDU_INFO_GLOBAL_END_E                          = 309  ,
+  WIFI_EXT_RX_PPDU_END_USER_STATS_E                        = 311  ,
+  WIFI_EXT_REO_GET_QUEUE_STATS_E                           = 313  ,
+  WIFI_EXT_REO_FLUSH_CACHE_E                               = 315  ,
+  WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E                    = 317  ,
+  WIFI_EXT_REO_FLUSH_CACHE_STATUS_E                        = 319  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_E                               = 321  ,
+  WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E                        = 323  ,
+  WIFI_EXT_RX_PPDU_END_STATUS_DONE_E                       = 325  ,
+  WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E                   = 327  ,
+  WIFI_EXT_TX_DATA_SYNC_E                                  = 329  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E                        = 331  ,
+  WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E                 = 333  ,
+  WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E        = 335  ,
+  WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E                        = 337  ,
+  WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E       = 339  ,
+  WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E                      = 341  ,
+  WIFI_EXT_RX_RING_MASK_E                                  = 343  ,
+  WIFI_EXT_RXPCU_PPDU_END_INFO_E                           = 345  ,
+  WIFI_EXT_PDG_SW_MODE_BW_START_E                          = 347  ,
+  WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E                      = 349  ,
+  WIFI_EXT_SCHEDULER_END_E                                 = 351  ,
+  WIFI_EXT_RX_PPDU_END_DROPPED_E                           = 353  ,
+  WIFI_EXT_RX_MPDU_START_DROPPED_E                         = 355  ,
+  WIFI_EXT_RX_MSDU_END_DROPPED_E                           = 357  ,
+  WIFI_EXT_RX_ATTENTION_DROPPED_E                          = 359  ,
+  WIFI_EXT_RXPCU_USER_SETUP_EXT_E                          = 361  ,
+  WIFI_EXT_MACTX_SYNTH_ON_E                                = 363  ,
+  WIFI_EXT_TQM_MPDU_GLOBAL_START_E                         = 365  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E                       = 367  ,
+  WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E                = 369  ,
+  WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E                       = 371  ,
+  WIFI_EXT_PDG_TRIG_RESPONSE_E                             = 373  ,
+  WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E                      = 375  ,
+  WIFI_EXT_MPDUS_AVAILABLE_E                               = 377  ,
+  WIFI_EXT_PHYRX_TX_START_TIMING_E                         = 379  ,
+  WIFI_EXT_NDP_PREAMBLE_DONE_E                             = 381  ,
+  WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E                 = 383  ,
+  WIFI_EXT_TX_PUNCTURE_SETUP_E                             = 385  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E                      = 387  ,
+  WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E                   = 389  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E                    = 391  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E                  = 393  ,
+  WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E                  = 395  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E           = 397  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E               = 399  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E          = 401  ,
+  WIFI_EXT_RX_PPDU_END_START_E                             = 403  ,
+  WIFI_EXT_RX_PPDU_END_LAST_E                              = 405  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E         = 407  ,
+  WIFI_EXT_OBSS_SR_INFO_E                                  = 409  ,
+  WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E             = 411  ,
+  WIFI_EXT_MACTX_MCC_SWITCH_E                              = 413  ,
+  WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E                          = 415  ,
+  WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E                    = 417  ,
+  WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E       = 419  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E         = 421  ,
+  WIFI_EXT_SCH_TLV_WRAPPER_E                               = 423  ,
+  WIFI_EXT_MPDU_INFO_6X_E                                  = 425  ,
+  WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E                         = 427  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E                     = 429  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E                     = 431  ,
+  WIFI_EXT_PHYRX_U_SIG_EHT_TB_E                            = 433  ,
+  WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                 = 435  ,
+  WIFI_EXT_MACRX_LMR_READ_REQUEST_E                        = 437  ,
+  WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E                       = 439  ,
+  WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E                    = 441  ,
+  WIFI_EXT_PHYRX_USER_INFO_MU_UL_E                         = 443  ,
+  WIFI_EXT_SCHEDULER_NAV_INFO_E                            = 445  ,
+  WIFI_EXT_LMR_PEER_ENTRY_E                                = 447  ,
+  WIFI_EXT_LMR_DATA_E                                      = 449  ,
+  WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E                 = 451  ,
+  WIFI_EXT_TX_FES_STATUS_1K_BA_E                           = 453  ,
+  WIFI_EXT_MACRX_INBSS_OBSS_IND_E                          = 455  ,
+  WIFI_EXT_MLO_TX_NOTIFICATION_SU_E                        = 457  ,
+  WIFI_EXT_MLO_TX_REQ_SU_E                                 = 459  ,
+  WIFI_EXT_MLO_TX_RESP_E                                   = 461  ,
+  WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E                           = 463  ,
+  WIFI_EXT_MLO_MESSAGE_E                                   = 465  ,
+  WIFI_EXT_MLO_FES_SETUP_E                                 = 467  ,
+  WIFI_EXT_MLO_PDG_FES_SETUP_MU_E                          = 469  ,
+  WIFI_EXT_MON_BUFFER_ADDR_E                               = 471  ,
+  WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E        = 473  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E                       = 475  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_TB_E                            = 477  ,
+  WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E                = 479  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E                       = 481  ,
+  WIFI_EXT_PHYRX_PKT_END_PART1_E                           = 483  ,
+  WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E                      = 485  ,
+  WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E                    = 487  ,
+  WIFI_EXT_PHYTX_LOCATION_E                                = 489  ,
+  WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E                     = 491  ,
+  WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E                     = 493  ,
+  WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E                     = 495  ,
+  WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E                  = 497  ,
+  WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E                  = 499  ,
+  WIFI_EXT_OVERWRITE_RESP_END_E                            = 501  ,
+  WIFI_EXT_MON_DROP_E                                      = 503  ,
+  WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E              = 505  ,
+  WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E              = 507  ,
+  WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E                    = 509  ,
+  WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E                 = 511  ,
+  WIFI_EXT_RANGING_USER_DETAILS_E                          = 513  ,
+  WIFI_EXT_PHYTX_CV_CORR_COMMON_E                          = 515  ,
+  WIFI_EXT_MACTX_CV_CORR_COMMON_E                          = 517  ,
+  WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E                      = 519  ,
+  WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E                 = 521  ,
+  WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E             = 523  ,
+  WIFI_EXT_FW2SW_MON_E                                     = 525  ,
+  WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E                        = 527  ,
+  WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E                       = 529  ,
+  WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E                   = 531  ,
+  WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E                     = 533  ,
+  WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E                  = 535  ,
+  WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E                     = 537  ,
+  WIFI_EXT_TPI_MPDU_START_E                                = 539  ,
+  WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E          = 541  ,
+  WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E                     = 543  ,
+  WIFI_EXT_TPI_ERROR_STATUS_E                              = 545  ,
+  WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E                         = 547  ,
+  WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E                  = 549  ,
+  WIFI_EXT_RPI_ERROR_STATUS_E                              = 551  ,
+  WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E                    = 553  ,
+  WIFI_EXT_TCC_TLV_FETCH_E                                 = 555  ,
+  WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E                  = 557  ,
+  WIFI_EXT_TCC_ERROR_STATUS_E                              = 559  ,
+  WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E                 = 561  ,
+  WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E                       = 563  ,
+  WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E                   = 565  ,
+  WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E                     = 567  ,
+  WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E                   = 569  ,
+  WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E                     = 571  ,
+  WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E                    = 573  ,
+  WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E              = 575  ,
+  WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E                       = 577  ,
+  WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E                     = 579  ,
+  WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E                          = 581  ,
+  WIFI_EXT_PEER_BLACKOUT_DETAILS_E                         = 583  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E                      = 585  ,
+  WIFI_EXT_HDR_CTRL_PROT_DATA_E                            = 587  ,
+  WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E                      = 589  ,
+  WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E                 = 591  ,
+  WIFI_EXT_MACTX_U_SIG_UHR_COBF_E                          = 593  ,
+  WIFI_EXT_SPARE_REUSE_TAG_0_E                             = 595  ,
+  WIFI_EXT_SPARE_REUSE_TAG_2_E                             = 597  ,
+  WIFI_EXT_SPARE_REUSE_TAG_4_E                             = 599  ,
+  WIFI_EXT_SPARE_REUSE_TAG_6_E                             = 601  ,
+  WIFI_EXT_SPARE_REUSE_TAG_8_E                             = 603  ,
+  WIFI_EXT_SPARE_REUSE_TAG_10_E                            = 605  ,
+  WIFI_EXT_SPARE_REUSE_TAG_12_E                            = 607  ,
+  WIFI_EXT_SPARE_REUSE_TAG_14_E                            = 609  ,
+  WIFI_EXT_SPARE_REUSE_TAG_16_E                            = 611  ,
+  WIFI_EXT_SPARE_REUSE_TAG_18_E                            = 613  ,
+  WIFI_EXT_SPARE_REUSE_TAG_20_E                            = 615  ,
+  WIFI_EXT_SPARE_REUSE_TAG_22_E                            = 617  ,
+  WIFI_EXT_SPARE_REUSE_TAG_24_E                            = 619  ,
+  WIFI_EXT_SPARE_REUSE_TAG_26_E                            = 621  ,
+  WIFI_EXT_SPARE_REUSE_TAG_28_E                            = 623  ,
+  WIFI_EXT_SPARE_REUSE_TAG_30_E                            = 625  ,
+  WIFI_EXT_SPARE_REUSE_TAG_32_E                            = 627  ,
+  WIFI_EXT_SPARE_REUSE_TAG_34_E                            = 629  ,
+  WIFI_EXT_SPARE_REUSE_TAG_36_E                            = 631  ,
+  WIFI_EXT_SPARE_REUSE_TAG_38_E                            = 633  ,
+  WIFI_EXT_SPARE_REUSE_TAG_40_E                            = 635  ,
+  WIFI_EXT_SPARE_REUSE_TAG_42_E                            = 637  ,
+  WIFI_EXT_SPARE_REUSE_TAG_44_E                            = 639  ,
+  WIFI_EXT_SPARE_REUSE_TAG_46_E                            = 641  ,
+  WIFI_EXT_SPARE_REUSE_TAG_48_E                            = 643  ,
+  WIFI_EXT_SPARE_REUSE_TAG_50_E                            = 645  ,
+  WIFI_EXT_SPARE_REUSE_TAG_52_E                            = 647  ,
+  WIFI_EXT_SPARE_REUSE_TAG_54_E                            = 649  ,
+  WIFI_EXT_SPARE_REUSE_TAG_56_E                            = 651  ,
+  WIFI_EXT_SPARE_REUSE_TAG_58_E                            = 653  ,
+  WIFI_EXT_SPARE_REUSE_TAG_60_E                            = 655  ,
+  WIFI_EXT_SPARE_REUSE_TAG_62_E                            = 657  ,
+  WIFI_EXT_SPARE_REUSE_TAG_64_E                            = 659  ,
+  WIFI_EXT_SPARE_REUSE_TAG_66_E                            = 661  ,
+  WIFI_EXT_SPARE_REUSE_TAG_68_E                            = 663  ,
+  WIFI_EXT_SPARE_REUSE_TAG_70_E                            = 665  ,
+  WIFI_EXT_SPARE_REUSE_TAG_72_E                            = 667  ,
+  WIFI_EXT_SPARE_REUSE_TAG_74_E                            = 669  ,
+  WIFI_EXT_SPARE_REUSE_TAG_76_E                            = 671  ,
+  WIFI_EXT_SPARE_REUSE_TAG_78_E                            = 673  ,
+  WIFI_EXT_SPARE_REUSE_TAG_80_E                            = 675  ,
+  WIFI_EXT_SPARE_REUSE_TAG_82_E                            = 677  ,
+  WIFI_EXT_SPARE_REUSE_TAG_84_E                            = 679  ,
+  WIFI_EXT_SPARE_REUSE_TAG_86_E                            = 681  ,
+  WIFI_EXT_SPARE_REUSE_TAG_88_E                            = 683  ,
+  WIFI_EXT_SPARE_REUSE_TAG_90_E                            = 685  ,
+  WIFI_EXT_SPARE_REUSE_TAG_92_E                            = 687  ,
+  WIFI_EXT_SPARE_REUSE_TAG_94_E                            = 689  ,
+  WIFI_EXT_SPARE_REUSE_TAG_96_E                            = 691  ,
+  WIFI_EXT_SPARE_REUSE_TAG_98_E                            = 693  ,
+  WIFI_EXT_SPARE_REUSE_TAG_100_E                           = 695  ,
+  WIFI_EXT_SPARE_REUSE_TAG_102_E                           = 697  ,
+  WIFI_EXT_SPARE_REUSE_TAG_104_E                           = 699  ,
+  WIFI_EXT_SPARE_REUSE_TAG_106_E                           = 701  ,
+  WIFI_EXT_SPARE_REUSE_TAG_108_E                           = 703  ,
+  WIFI_EXT_SPARE_REUSE_TAG_110_E                           = 705  ,
+  WIFI_EXT_SPARE_REUSE_TAG_112_E                           = 707  ,
+  WIFI_EXT_SPARE_REUSE_TAG_114_E                           = 709  ,
+  WIFI_EXT_SPARE_REUSE_TAG_116_E                           = 711  ,
+  WIFI_EXT_SPARE_REUSE_TAG_118_E                           = 713  ,
+  WIFI_EXT_SPARE_REUSE_TAG_120_E                           = 715  ,
+  WIFI_EXT_SPARE_REUSE_TAG_122_E                           = 717  ,
+  WIFI_EXT_SPARE_REUSE_TAG_124_E                           = 719  ,
+  WIFI_EXT_SPARE_REUSE_TAG_126_E                           = 721  ,
+  WIFI_EXT_SPARE_REUSE_TAG_128_E                           = 723  ,
+  WIFI_EXT_SPARE_REUSE_TAG_130_E                           = 725  ,
+  WIFI_EXT_SPARE_REUSE_TAG_132_E                           = 727  ,
+  WIFI_EXT_SPARE_REUSE_TAG_134_E                           = 729  ,
+  WIFI_EXT_SPARE_REUSE_TAG_136_E                           = 731  ,
+  WIFI_EXT_SPARE_REUSE_TAG_138_E                           = 733  ,
+  WIFI_EXT_SPARE_REUSE_TAG_140_E                           = 735  ,
+  WIFI_EXT_SPARE_REUSE_TAG_142_E                           = 737  ,
+  WIFI_EXT_SPARE_REUSE_TAG_144_E                           = 739  ,
+  WIFI_EXT_SPARE_REUSE_TAG_146_E                           = 741  ,
+  WIFI_EXT_SPARE_REUSE_TAG_148_E                           = 743  ,
+  WIFI_EXT_SPARE_REUSE_TAG_150_E                           = 745  ,
+  WIFI_EXT_SPARE_REUSE_TAG_152_E                           = 747  ,
+  WIFI_EXT_SPARE_REUSE_TAG_154_E                           = 749  ,
+  WIFI_EXT_SPARE_REUSE_TAG_156_E                           = 751  ,
+  WIFI_EXT_SPARE_REUSE_TAG_158_E                           = 753  ,
+  WIFI_EXT_SPARE_REUSE_TAG_160_E                           = 755  ,
+  WIFI_EXT_SPARE_REUSE_TAG_162_E                           = 757  ,
+  WIFI_EXT_SPARE_REUSE_TAG_164_E                           = 759  ,
+  WIFI_EXT_SPARE_REUSE_TAG_166_E                           = 761  ,
+  WIFI_EXT_SPARE_REUSE_TAG_168_E                           = 763  ,
+  WIFI_EXT_SPARE_REUSE_TAG_170_E                           = 765  ,
+  WIFI_EXT_SPARE_REUSE_TAG_172_E                           = 767  ,
+  WIFI_EXT_SPARE_REUSE_TAG_174_E                           = 769  ,
+  WIFI_EXT_SPARE_REUSE_TAG_176_E                           = 771  ,
+  WIFI_EXT_SPARE_REUSE_TAG_178_E                           = 773  ,
+  WIFI_EXT_SPARE_REUSE_TAG_180_E                           = 775  ,
+  WIFI_EXT_SPARE_REUSE_TAG_182_E                           = 777  ,
+  WIFI_EXT_SPARE_REUSE_TAG_184_E                           = 779  ,
+  WIFI_EXT_SPARE_REUSE_TAG_186_E                           = 781  ,
+  WIFI_EXT_SPARE_REUSE_TAG_188_E                           = 783  ,
+  WIFI_EXT_SPARE_REUSE_TAG_190_E                           = 785  ,
+  WIFI_EXT_SPARE_REUSE_TAG_192_E                           = 787  ,
+  WIFI_EXT_SPARE_REUSE_TAG_194_E                           = 789  ,
+  WIFI_EXT_SPARE_REUSE_TAG_196_E                           = 791  ,
+  WIFI_EXT_SPARE_REUSE_TAG_198_E                           = 793  ,
+  WIFI_EXT_SPARE_REUSE_TAG_200_E                           = 795  ,
+  WIFI_EXT_SPARE_REUSE_TAG_202_E                           = 797  ,
+  WIFI_EXT_SPARE_REUSE_TAG_204_E                           = 799  ,
+  WIFI_EXT_SPARE_REUSE_TAG_206_E                           = 801  ,
+  WIFI_EXT_SPARE_REUSE_TAG_208_E                           = 803  ,
+  WIFI_EXT_SPARE_REUSE_TAG_210_E                           = 805  ,
+  WIFI_EXT_SPARE_REUSE_TAG_212_E                           = 807  ,
+  WIFI_EXT_SPARE_REUSE_TAG_214_E                           = 809  ,
+  WIFI_EXT_SPARE_REUSE_TAG_216_E                           = 811  ,
+  WIFI_EXT_SPARE_REUSE_TAG_218_E                           = 813  ,
+  WIFI_EXT_SPARE_REUSE_TAG_220_E                           = 815  ,
+  WIFI_EXT_SPARE_REUSE_TAG_222_E                           = 817  ,
+  WIFI_EXT_SPARE_REUSE_TAG_224_E                           = 819  ,
+  WIFI_EXT_SPARE_REUSE_TAG_226_E                           = 821  ,
+  WIFI_EXT_SPARE_REUSE_TAG_228_E                           = 823  ,
+  WIFI_EXT_SPARE_REUSE_TAG_230_E                           = 825  ,
+  WIFI_EXT_SPARE_REUSE_TAG_232_E                           = 827  ,
+  WIFI_EXT_SPARE_REUSE_TAG_234_E                           = 829  ,
+  WIFI_EXT_SPARE_REUSE_TAG_236_E                           = 831  ,
+  WIFI_EXT_SPARE_REUSE_TAG_238_E                           = 833  ,
+  WIFI_EXT_SPARE_REUSE_TAG_240_E                           = 835  ,
+  WIFI_EXT_SPARE_REUSE_TAG_242_E                           = 837  ,
+  WIFI_EXT_SPARE_REUSE_TAG_244_E                           = 839  ,
+  WIFI_EXT_SPARE_REUSE_TAG_246_E                           = 841  ,
+  WIFI_EXT_SPARE_REUSE_TAG_248_E                           = 843  ,
+  WIFI_EXT_SPARE_REUSE_TAG_250_E                           = 845  ,
+  WIFI_EXT_SPARE_REUSE_TAG_252_E                           = 847  ,
+  WIFI_EXT_SPARE_REUSE_TAG_254_E                           = 849  ,
+  WIFI_EXT_SPARE_REUSE_TAG_256_E                           = 851  ,
+  WIFI_EXT_SPARE_REUSE_TAG_258_E                           = 853  ,
+  WIFI_EXT_SPARE_REUSE_TAG_260_E                           = 855  ,
+  WIFI_EXT_SPARE_REUSE_TAG_262_E                           = 857  ,
+  WIFI_EXT_SPARE_REUSE_TAG_264_E                           = 859  ,
+  WIFI_EXT_SPARE_REUSE_TAG_266_E                           = 861  ,
+  WIFI_EXT_SPARE_REUSE_TAG_268_E                           = 863  ,
+  WIFI_EXT_SPARE_REUSE_TAG_270_E                           = 865  ,
+  WIFI_EXT_SPARE_REUSE_TAG_272_E                           = 867  ,
+  WIFI_EXT_SPARE_REUSE_TAG_274_E                           = 869  ,
+  WIFI_EXT_SPARE_REUSE_TAG_276_E                           = 871  ,
+  WIFI_EXT_SPARE_REUSE_TAG_278_E                           = 873  ,
+  WIFI_EXT_SPARE_REUSE_TAG_280_E                           = 875  ,
+  WIFI_EXT_SPARE_REUSE_TAG_282_E                           = 877  ,
+  WIFI_EXT_SPARE_REUSE_TAG_284_E                           = 879  ,
+  WIFI_EXT_SPARE_REUSE_TAG_286_E                           = 881  ,
+  WIFI_EXT_SPARE_REUSE_TAG_288_E                           = 883  ,
+  WIFI_EXT_SPARE_REUSE_TAG_290_E                           = 885  ,
+  WIFI_EXT_SPARE_REUSE_TAG_292_E                           = 887  ,
+  WIFI_EXT_SPARE_REUSE_TAG_294_E                           = 889  ,
+  WIFI_EXT_SPARE_REUSE_TAG_296_E                           = 891  ,
+  WIFI_EXT_SPARE_REUSE_TAG_298_E                           = 893  ,
+  WIFI_EXT_SPARE_REUSE_TAG_300_E                           = 895  ,
+  WIFI_EXT_SPARE_REUSE_TAG_302_E                           = 897  ,
+  WIFI_EXT_SPARE_REUSE_TAG_304_E                           = 899  ,
+  WIFI_EXT_SPARE_REUSE_TAG_306_E                           = 901  ,
+  WIFI_EXT_SPARE_REUSE_TAG_308_E                           = 903  ,
+  WIFI_EXT_SPARE_REUSE_TAG_310_E                           = 905  ,
+  WIFI_EXT_SPARE_REUSE_TAG_312_E                           = 907  ,
+  WIFI_EXT_SPARE_REUSE_TAG_314_E                           = 909  ,
+  WIFI_EXT_SPARE_REUSE_TAG_316_E                           = 911  ,
+  WIFI_EXT_SPARE_REUSE_TAG_318_E                           = 913  ,
+  WIFI_EXT_SPARE_REUSE_TAG_320_E                           = 915  ,
+  WIFI_EXT_SPARE_REUSE_TAG_322_E                           = 917  ,
+  WIFI_EXT_SPARE_REUSE_TAG_324_E                           = 919  ,
+  WIFI_EXT_SPARE_REUSE_TAG_326_E                           = 921  ,
+  WIFI_EXT_SPARE_REUSE_TAG_328_E                           = 923  ,
+  WIFI_EXT_SPARE_REUSE_TAG_330_E                           = 925  ,
+  WIFI_EXT_SPARE_REUSE_TAG_332_E                           = 927  ,
+  WIFI_EXT_SPARE_REUSE_TAG_334_E                           = 929  ,
+  WIFI_EXT_SPARE_REUSE_TAG_336_E                           = 931  ,
+  WIFI_EXT_SPARE_REUSE_TAG_338_E                           = 933  ,
+  WIFI_EXT_SPARE_REUSE_TAG_340_E                           = 935  ,
+  WIFI_EXT_SPARE_REUSE_TAG_342_E                           = 937  ,
+  WIFI_EXT_SPARE_REUSE_TAG_344_E                           = 939  ,
+  WIFI_EXT_SPARE_REUSE_TAG_346_E                           = 941  ,
+  WIFI_EXT_SPARE_REUSE_TAG_348_E                           = 943  ,
+  WIFI_EXT_SPARE_REUSE_TAG_350_E                           = 945  ,
+  WIFI_EXT_SPARE_REUSE_TAG_352_E                           = 947  ,
+  WIFI_EXT_SPARE_REUSE_TAG_354_E                           = 949  ,
+  WIFI_EXT_SPARE_REUSE_TAG_356_E                           = 951  ,
+  WIFI_EXT_SPARE_REUSE_TAG_358_E                           = 953  ,
+  WIFI_EXT_SPARE_REUSE_TAG_360_E                           = 955  ,
+  WIFI_EXT_SPARE_REUSE_TAG_362_E                           = 957  ,
+  WIFI_EXT_SPARE_REUSE_TAG_364_E                           = 959  ,
+  WIFI_EXT_SPARE_REUSE_TAG_366_E                           = 961  ,
+  WIFI_EXT_SPARE_REUSE_TAG_368_E                           = 963  ,
+  WIFI_EXT_SPARE_REUSE_TAG_370_E                           = 965  ,
+  WIFI_EXT_SPARE_REUSE_TAG_372_E                           = 967  ,
+  WIFI_EXT_SPARE_REUSE_TAG_374_E                           = 969  ,
+  WIFI_EXT_SPARE_REUSE_TAG_376_E                           = 971  ,
+  WIFI_EXT_SPARE_REUSE_TAG_378_E                           = 973  ,
+  WIFI_EXT_SPARE_REUSE_TAG_380_E                           = 975  ,
+  WIFI_EXT_SPARE_REUSE_TAG_382_E                           = 977  ,
+  WIFI_EXT_SPARE_REUSE_TAG_384_E                           = 979  ,
+  WIFI_EXT_SPARE_REUSE_TAG_386_E                           = 981  ,
+  WIFI_EXT_SPARE_REUSE_TAG_388_E                           = 983  ,
+  WIFI_EXT_SPARE_REUSE_TAG_390_E                           = 985  ,
+  WIFI_EXT_SPARE_REUSE_TAG_392_E                           = 987  ,
+  WIFI_EXT_SPARE_REUSE_TAG_394_E                           = 989  ,
+  WIFI_EXT_SPARE_REUSE_TAG_396_E                           = 991  ,
+  WIFI_EXT_SPARE_REUSE_TAG_398_E                           = 993  ,
+  WIFI_EXT_SPARE_REUSE_TAG_400_E                           = 995  ,
+  WIFI_EXT_SPARE_REUSE_TAG_402_E                           = 997  ,
+  WIFI_EXT_SPARE_REUSE_TAG_404_E                           = 999  ,
+  WIFI_EXT_SPARE_REUSE_TAG_406_E                           = 1001  ,
+  WIFI_EXT_SPARE_REUSE_TAG_408_E                           = 1003  ,
+  WIFI_EXT_SPARE_REUSE_TAG_410_E                           = 1005  ,
+  WIFI_EXT_SPARE_REUSE_TAG_412_E                           = 1007  ,
+  WIFI_EXT_SPARE_REUSE_TAG_414_E                           = 1009  ,
+  WIFI_EXT_SPARE_REUSE_TAG_416_E                           = 1011  ,
+  WIFI_EXT_SPARE_REUSE_TAG_418_E                           = 1013  ,
+  WIFI_EXT_SPARE_REUSE_TAG_420_E                           = 1015  ,
+  WIFI_EXT_SPARE_REUSE_TAG_422_E                           = 1017  ,
+  WIFI_EXT_SPARE_REUSE_TAG_424_E                           = 1019  ,
+  WIFI_EXT_SPARE_REUSE_TAG_426_E                           = 1021
+} ext_tlv_tag_def__e;
+
+typedef enum {
+  WIFI_N_EXT_MACTX_CBF_START_E                             = 0  ,
+  WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E                         = 2  ,
+  WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E               = 4  ,
+  WIFI_N_EXT_MACTX_CBF_DATA_E                              = 6  ,
+  WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E                         = 8  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E      = 10  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E                   = 12  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E    = 14  ,
+  WIFI_N_EXT_RXPCU_TO_UCODE_END_E                          = 16  ,
+  WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E                      = 18  ,
+  WIFI_N_EXT_PHYRX_NC_DATA_E                               = 20  ,
+  WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E                      = 64  ,
+  WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E                  = 66  ,
+  WIFI_N_EXT_MACRX_NDP_TIMEOUT_E                           = 68  ,
+  WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E                       = 70  ,
+  WIFI_N_EXT_MACRX_NAP_USER_E                              = 72  ,
+  WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E                 = 74  ,
+  WIFI_N_EXT_PHYTX_ABORT_REQUEST_E                         = 76  ,
+  WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E              = 78  ,
+  WIFI_N_EXT_PHYTX_DATA_REQUEST_E                          = 80  ,
+  WIFI_N_EXT_PHYTX_NAP_ACK_E                               = 82  ,
+  WIFI_N_EXT_PHYTX_OFF_ACK_E                               = 84  ,
+  WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E                         = 86  ,
+  WIFI_N_EXT_MACTX_ABORT_REQUEST_E                         = 88  ,
+  WIFI_N_EXT_MACTX_PKT_END_E                               = 90  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E                      = 92  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_E                           = 94  ,
+  WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E                    = 96  ,
+  WIFI_N_EXT_EXAMPLE_TLV_16_E                              = 98  ,
+  WIFI_N_EXT_MACTX_PHY_ON_E                                = 100  ,
+  WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E                     = 102  ,
+  WIFI_N_EXT_MACTX_PHY_DESC_E                              = 104  ,
+  WIFI_N_EXT_MACTX_L_SIG_B_E                               = 106  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_A_E                             = 108  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E                        = 110  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E                       = 112  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E                        = 114  ,
+  WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E                       = 116  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_SU_E                           = 118  ,
+  WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E                        = 120  ,
+  WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E                          = 122  ,
+  WIFI_N_EXT_MACTX_DELETE_CV_E                             = 124  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E                  = 126  ,
+  WIFI_N_EXT_MACTX_PHY_NAP_E                               = 128  ,
+  WIFI_N_EXT_PHYRX_ABORT_ACK_E                             = 130  ,
+  WIFI_N_EXT_PHYRX_RSSI_LEGACY_E                           = 132  ,
+  WIFI_N_EXT_PHYRX_USER_INFO_E                             = 134  ,
+  WIFI_N_EXT_PHYRX_DEBUG_E                                 = 136  ,
+  WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E                    = 138  ,
+  WIFI_N_EXT_PHYRX_L_SIG_B_E                               = 140  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_A_E                             = 142  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E                        = 144  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E                       = 146  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E                        = 148  ,
+  WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E                       = 150  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E                        = 152  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E                          = 154  ,
+  WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E                       = 156  ,
+  WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E                      = 158  ,
+  WIFI_N_EXT_COEX_TX_REQ_E                                 = 160  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E                         = 162  ,
+  WIFI_N_EXT_NA_LENGTH_END_E                               = 164  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E                         = 166  ,
+  WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E                         = 168  ,
+  WIFI_N_EXT_PDG_FES_SETUP_E                               = 170  ,
+  WIFI_N_EXT_PDG_TX_REQ_E                                  = 172  ,
+  WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E                        = 174  ,
+  WIFI_N_EXT_AUX_PPDU_END_E                                = 176  ,
+  WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E             = 178  ,
+  WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E                        = 180  ,
+  WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E                      = 182  ,
+  WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E                      = 184  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_E                               = 186  ,
+  WIFI_N_EXT_TX_DATA_E                                     = 188  ,
+  WIFI_N_EXT_RX_PACKET_E                                   = 190  ,
+  WIFI_N_EXT_TX_MPDU_END_E                                 = 192  ,
+  WIFI_N_EXT_TX_MSDU_END_E                                 = 194  ,
+  WIFI_N_EXT_TX_SW_MODE_SETUP_E                            = 196  ,
+  WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E                    = 198  ,
+  WIFI_N_EXT_EXAMPLE_USER_TLV_32_E                         = 200  ,
+  WIFI_N_EXT_PDG_USER_SETUP_E                              = 202  ,
+  WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E              = 204  ,
+  WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E                = 206  ,
+  WIFI_N_EXT_TX_FLUSH_E                                    = 208  ,
+  WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E                        = 210  ,
+  WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E                     = 212  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_E                         = 214  ,
+  WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E                 = 216  ,
+  WIFI_N_EXT_RX_TRIG_INFO_E                                = 218  ,
+  WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E                         = 220  ,
+  WIFI_N_EXT_COEX_RX_STATUS_E                              = 222  ,
+  WIFI_N_EXT_RX_PPDU_START_E                               = 224  ,
+  WIFI_N_EXT_RX_MPDU_START_E                               = 226  ,
+  WIFI_N_EXT_RX_MSDU_START_E                               = 228  ,
+  WIFI_N_EXT_RX_ATTENTION_E                                = 230  ,
+  WIFI_N_EXT_RX_PHY_SLEEP_E                                = 232  ,
+  WIFI_N_EXT_RX_PEER_ENTRY_E                               = 234  ,
+  WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E                   = 236  ,
+  WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E             = 238  ,
+  WIFI_N_EXT_TX_CBF_INFO_E                                 = 240  ,
+  WIFI_N_EXT_RX_MPDU_PCU_START_E                           = 242  ,
+  WIFI_N_EXT_RX_USER_PPDU_END_E                            = 244  ,
+  WIFI_N_EXT_RX_PREAMBLE_E                                 = 246  ,
+  WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E                        = 248  ,
+  WIFI_N_EXT_RXPCU_SETUP_E                                 = 250  ,
+  WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E                     = 252  ,
+  WIFI_N_EXT_COEX_TX_RESP_E                                = 254  ,
+  WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E                         = 256  ,
+  WIFI_N_EXT_RESPONSE_START_STATUS_E                       = 258  ,
+  WIFI_N_EXT_CRYPTO_STATUS_E                               = 260  ,
+  WIFI_N_EXT_COEX_TX_STOP_CTRL_E                           = 262  ,
+  WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E                       = 264  ,
+  WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E                    = 266  ,
+  WIFI_N_EXT_TX_FES_STATUS_PROT_E                          = 268  ,
+  WIFI_N_EXT_TX_FES_STATUS_START_PROT_E                    = 270  ,
+  WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E           = 272  ,
+  WIFI_N_EXT_WHO_ANCHOR_OFFSET_E                           = 274  ,
+  WIFI_N_EXT_WHO_CCE_INFO_E                                = 276  ,
+  WIFI_N_EXT_WHO_COMMIT_DONE_E                             = 278  ,
+  WIFI_N_EXT_WHO_L2_LLC_E                                  = 280  ,
+  WIFI_N_EXT_WHO_L3_CHECKSUM_E                             = 282  ,
+  WIFI_N_EXT_WHO_L4_CHECKSUM_E                             = 284  ,
+  WIFI_N_EXT_WHO_MSDU_E                                    = 286  ,
+  WIFI_N_EXT_WHO_PACKET_DATA_E                             = 288  ,
+  WIFI_N_EXT_WHO_PPDU_END_E                                = 290  ,
+  WIFI_N_EXT_WHO_TSO_E                                     = 292  ,
+  WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E                         = 294  ,
+  WIFI_N_EXT_MPDU_INFO_END_E                               = 296  ,
+  WIFI_N_EXT_TX_QUEUE_EXTENSION_E                          = 298  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E             = 300  ,
+  WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E                         = 302  ,
+  WIFI_N_EXT_WHO_TERMINATE_E                               = 304  ,
+  WIFI_N_EXT_TX_CV_DATA_E                                  = 306  ,
+  WIFI_N_EXT_PROT_TX_END_E                                 = 308  ,
+  WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E                    = 310  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E                  = 312  ,
+  WIFI_N_EXT_REO_FLUSH_QUEUE_E                             = 314  ,
+  WIFI_N_EXT_REO_UNBLOCK_CACHE_E                           = 316  ,
+  WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E                      = 318  ,
+  WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E                    = 320  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_E                           = 322  ,
+  WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E                    = 324  ,
+  WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E                       = 326  ,
+  WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E             = 328  ,
+  WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E                  = 330  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_E                                = 332  ,
+  WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E                         = 334  ,
+  WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E                         = 336  ,
+  WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E               = 338  ,
+  WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E   = 340  ,
+  WIFI_N_EXT_RX_PPDU_START_USER_INFO_E                     = 342  ,
+  WIFI_N_EXT_COEX_MAC_NAP_E                                = 344  ,
+  WIFI_N_EXT_WHO_MESH_CONTROL_E                            = 346  ,
+  WIFI_N_EXT_PDG_SW_MODE_BW_END_E                          = 348  ,
+  WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E                    = 350  ,
+  WIFI_N_EXT_RX_PPDU_START_DROPPED_E                       = 352  ,
+  WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E             = 354  ,
+  WIFI_N_EXT_RX_MSDU_START_DROPPED_E                       = 356  ,
+  WIFI_N_EXT_RX_MPDU_END_DROPPED_E                         = 358  ,
+  WIFI_N_EXT_TXPCU_USER_SETUP_E                            = 360  ,
+  WIFI_N_EXT_CMD_PART_0_END_E                              = 362  ,
+  WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E                  = 364  ,
+  WIFI_N_EXT_EXAMPLE_TLV_32_E                              = 366  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E               = 368  ,
+  WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E        = 370  ,
+  WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E                    = 372  ,
+  WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E                    = 374  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E                         = 376  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E                = 378  ,
+  WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E                         = 380  ,
+  WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E                = 382  ,
+  WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E                    = 384  ,
+  WIFI_N_EXT_R2R_STATUS_END_E                              = 386  ,
+  WIFI_N_EXT_END_OF_FLUSH_MARKER_E                         = 388  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E             = 390  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E                 = 392  ,
+  WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E                = 394  ,
+  WIFI_N_EXT_TX_LOOPBACK_SETUP_E                           = 396  ,
+  WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E                      = 398  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E      = 400  ,
+  WIFI_N_EXT_TX_WUR_DATA_E                                 = 402  ,
+  WIFI_N_EXT_RX_PPDU_END_MIDDLE_E                          = 404  ,
+  WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E            = 406  ,
+  WIFI_N_EXT_SRP_INFO_E                                    = 408  ,
+  WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E                     = 410  ,
+  WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E                        = 412  ,
+  WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E                       = 414  ,
+  WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E                   = 416  ,
+  WIFI_N_EXT_LMR_TX_END_E                                  = 418  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E       = 420  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E   = 422  ,
+  WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E                    = 424  ,
+  WIFI_N_EXT_MACTX___RESERVED_G_0013                       = 426  ,
+  WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E                          = 428  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E                   = 430  ,
+  WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E                       = 432  ,
+  WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E                   = 434  ,
+  WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E                 = 436  ,
+  WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E                      = 438  ,
+  WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E                    = 440  ,
+  WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E                    = 442  ,
+  WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E                         = 444  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E         = 446  ,
+  WIFI_N_EXT_LMR_MPDU_START_E                              = 448  ,
+  WIFI_N_EXT_LMR_MPDU_END_E                                = 450  ,
+  WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E                      = 452  ,
+  WIFI_N_EXT_TQM_ACKED_1K_MPDU_E                           = 454  ,
+  WIFI_N_EXT_PHYRX_LOCATION_E                              = 456  ,
+  WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E                      = 458  ,
+  WIFI_N_EXT_MLO_TX_REQ_MU_E                               = 460  ,
+  WIFI_N_EXT_MLO_RX_NOTIFICATION_E                         = 462  ,
+  WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E                       = 464  ,
+  WIFI_N_EXT_MLO_TS_SYNC_MSG_E                             = 466  ,
+  WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E                        = 468  ,
+  WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E                         = 470  ,
+  WIFI_N_EXT_TX_FRAG_STATE_E                               = 472  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E       = 474  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E                       = 476  ,
+  WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E              = 478  ,
+  WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E               = 480  ,
+  WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E                    = 482  ,
+  WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E                  = 484  ,
+  WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E             = 486  ,
+  WIFI_N_EXT_PHYRX___RESERVED_G_0014                       = 488  ,
+  WIFI_N_EXT_PHYTX___RESERVED_G_0014                       = 490  ,
+  WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E                        = 492  ,
+  WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E                        = 494  ,
+  WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E                         = 496  ,
+  WIFI_N_EXT_OVERWRITE_RESP_START_E                        = 498  ,
+  WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E                   = 500  ,
+  WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E                   = 502  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E                = 504  ,
+  WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E              = 506  ,
+  WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E                       = 508  ,
+  WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E   = 510  ,
+  WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E             = 512  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E                        = 514  ,
+  WIFI_N_EXT_PHYTX_CV_CORR_USER_E                          = 516  ,
+  WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E                = 518  ,
+  WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E               = 520  ,
+  WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E               = 522  ,
+  WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E                 = 524  ,
+  WIFI_N_EXT_WSI_DIRECT_MESSAGE_E                          = 526  ,
+  WIFI_N_EXT_MACTX_EMLSR_SWITCH_E                          = 528  ,
+  WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E                      = 530  ,
+  WIFI_N_EXT_EAD_COMMAND_E                                 = 532  ,
+  WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E                = 534  ,
+  WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E                 = 536  ,
+  WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E                = 538  ,
+  WIFI_N_EXT_TPI_MPDU_CONTINUATION_E                       = 540  ,
+  WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E                       = 542  ,
+  WIFI_N_EXT_TPI_STATUS_E                                  = 544  ,
+  WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E                        = 546  ,
+  WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E                   = 548  ,
+  WIFI_N_EXT_RPI_STATUS_E                                  = 550  ,
+  WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E                        = 552  ,
+  WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E                   = 554  ,
+  WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E                   = 556  ,
+  WIFI_N_EXT_TCC_STATUS_E                                  = 558  ,
+  WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E                        = 560  ,
+  WIFI_N_EXT_TCC_SCHEDULER_CMD_E                           = 562  ,
+  WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E             = 564  ,
+  WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E                 = 566  ,
+  WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E                 = 568  ,
+  WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E                  = 570  ,
+  WIFI_N_EXT_TCC_FES_END_MESSAGE_E                         = 572  ,
+  WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E                = 574  ,
+  WIFI_N_EXT_EAD_MSDU_STATUS_START_E                       = 576  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E                        = 578  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E                     = 580  ,
+  WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E                       = 582  ,
+  WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E      = 584  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E                    = 586  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E                      = 588  ,
+  WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E                     = 590  ,
+  WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E                      = 592  ,
+  WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E                      = 594  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_1_E                           = 596  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_3_E                           = 598  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_5_E                           = 600  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_7_E                           = 602  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_9_E                           = 604  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_11_E                          = 606  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_13_E                          = 608  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_15_E                          = 610  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_17_E                          = 612  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_19_E                          = 614  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_21_E                          = 616  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_23_E                          = 618  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_25_E                          = 620  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_27_E                          = 622  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_29_E                          = 624  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_31_E                          = 626  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_33_E                          = 628  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_35_E                          = 630  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_37_E                          = 632  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_39_E                          = 634  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_41_E                          = 636  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_43_E                          = 638  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_45_E                          = 640  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_47_E                          = 642  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_49_E                          = 644  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_51_E                          = 646  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_53_E                          = 648  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_55_E                          = 650  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_57_E                          = 652  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_59_E                          = 654  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_61_E                          = 656  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_63_E                          = 658  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_65_E                          = 660  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_67_E                          = 662  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_69_E                          = 664  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_71_E                          = 666  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_73_E                          = 668  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_75_E                          = 670  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_77_E                          = 672  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_79_E                          = 674  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_81_E                          = 676  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_83_E                          = 678  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_85_E                          = 680  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_87_E                          = 682  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_89_E                          = 684  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_91_E                          = 686  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_93_E                          = 688  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_95_E                          = 690  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_97_E                          = 692  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_99_E                          = 694  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_101_E                         = 696  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_103_E                         = 698  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_105_E                         = 700  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_107_E                         = 702  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_109_E                         = 704  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_111_E                         = 706  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_113_E                         = 708  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_115_E                         = 710  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_117_E                         = 712  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_119_E                         = 714  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_121_E                         = 716  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_123_E                         = 718  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_125_E                         = 720  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_127_E                         = 722  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_129_E                         = 724  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_131_E                         = 726  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_133_E                         = 728  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_135_E                         = 730  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_137_E                         = 732  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_139_E                         = 734  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_141_E                         = 736  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_143_E                         = 738  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_145_E                         = 740  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_147_E                         = 742  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_149_E                         = 744  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_151_E                         = 746  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_153_E                         = 748  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_155_E                         = 750  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_157_E                         = 752  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_159_E                         = 754  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_161_E                         = 756  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_163_E                         = 758  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_165_E                         = 760  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_167_E                         = 762  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_169_E                         = 764  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_171_E                         = 766  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_173_E                         = 768  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_175_E                         = 770  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_177_E                         = 772  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_179_E                         = 774  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_181_E                         = 776  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_183_E                         = 778  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_185_E                         = 780  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_187_E                         = 782  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_189_E                         = 784  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_191_E                         = 786  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_193_E                         = 788  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_195_E                         = 790  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_197_E                         = 792  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_199_E                         = 794  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_201_E                         = 796  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_203_E                         = 798  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_205_E                         = 800  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_207_E                         = 802  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_209_E                         = 804  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_211_E                         = 806  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_213_E                         = 808  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_215_E                         = 810  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_217_E                         = 812  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_219_E                         = 814  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_221_E                         = 816  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_223_E                         = 818  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_225_E                         = 820  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_227_E                         = 822  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_229_E                         = 824  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_231_E                         = 826  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_233_E                         = 828  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_235_E                         = 830  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_237_E                         = 832  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_239_E                         = 834  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_241_E                         = 836  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_243_E                         = 838  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_245_E                         = 840  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_247_E                         = 842  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_249_E                         = 844  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_251_E                         = 846  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_253_E                         = 848  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_255_E                         = 850  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_257_E                         = 852  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_259_E                         = 854  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_261_E                         = 856  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_263_E                         = 858  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_265_E                         = 860  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_267_E                         = 862  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_269_E                         = 864  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_271_E                         = 866  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_273_E                         = 868  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_275_E                         = 870  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_277_E                         = 872  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_279_E                         = 874  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_281_E                         = 876  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_283_E                         = 878  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_285_E                         = 880  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_287_E                         = 882  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_289_E                         = 884  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_291_E                         = 886  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_293_E                         = 888  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_295_E                         = 890  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_297_E                         = 892  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_299_E                         = 894  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_301_E                         = 896  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_303_E                         = 898  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_305_E                         = 900  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_307_E                         = 902  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_309_E                         = 904  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_311_E                         = 906  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_313_E                         = 908  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_315_E                         = 910  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_317_E                         = 912  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_319_E                         = 914  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_321_E                         = 916  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_323_E                         = 918  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_325_E                         = 920  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_327_E                         = 922  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_329_E                         = 924  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_331_E                         = 926  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_333_E                         = 928  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_335_E                         = 930  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_337_E                         = 932  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_339_E                         = 934  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_341_E                         = 936  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_343_E                         = 938  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_345_E                         = 940  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_347_E                         = 942  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_349_E                         = 944  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_351_E                         = 946  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_353_E                         = 948  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_355_E                         = 950  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_357_E                         = 952  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_359_E                         = 954  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_361_E                         = 956  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_363_E                         = 958  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_365_E                         = 960  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_367_E                         = 962  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_369_E                         = 964  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_371_E                         = 966  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_373_E                         = 968  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_375_E                         = 970  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_377_E                         = 972  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_379_E                         = 974  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_381_E                         = 976  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_383_E                         = 978  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_385_E                         = 980  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_387_E                         = 982  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_389_E                         = 984  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_391_E                         = 986  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_393_E                         = 988  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_395_E                         = 990  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_397_E                         = 992  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_399_E                         = 994  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_401_E                         = 996  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_403_E                         = 998  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_405_E                         = 1000  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_407_E                         = 1002  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_409_E                         = 1004  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_411_E                         = 1006  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_413_E                         = 1008  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_415_E                         = 1010  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_417_E                         = 1012  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_419_E                         = 1014  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_421_E                         = 1016  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_423_E                         = 1018  ,
+  WIFI_N_EXT_SPARE_REUSE_TAG_425_E                         = 1020
+} non_ext_tlv_tag_def__e;
+
+#endif
diff --git a/hw/wcn8750/v1/tqm2sw_completion_ring.h b/hw/wcn8750/v1/tqm2sw_completion_ring.h
new file mode 100644
index 000000000000..f67deea1f6a1
--- /dev/null
+++ b/hw/wcn8750/v1/tqm2sw_completion_ring.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TQM2SW_COMPLETION_RING_H_
+#define _TQM2SW_COMPLETION_RING_H_
+
+#include "tx_rate_stats_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8
+
+struct tqm2sw_completion_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      cookie_conversion_status                                :  1,
+                      tqm_completion_error                                    :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_desc_virt_addr_or_addr_info;
+             uint32_t tqm_completion_error                                    :  1,
+                      cookie_conversion_status                                :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB                            0
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB                            2
+#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK                           0x00000007
+
+#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET                                      0x00000008
+#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB                                         3
+#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK                                        0x00000008
+
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET                                   0x00000008
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB                                      4
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB                                      5
+#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK                                     0x00000030
+
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET                           0x00000008
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB                              6
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB                              8
+#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK                             0x000001c0
+
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB                            9
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB                            12
+#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK                           0x00001e00
+
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB                               13
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB                               16
+#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK                              0x0001e000
+
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET                            0x00000008
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB                               17
+#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK                              0x00020000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET                         0x00000008
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB                            18
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB                            29
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK                           0x3ffc0000
+
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET                      0x00000008
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB                         30
+#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK                        0x40000000
+
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET                          0x00000008
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB                             31
+#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK                            0x80000000
+
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET                             0x0000000c
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB                                0
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB                                23
+#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK                               0x00ffffff
+
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET                                0x0000000c
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB                                   24
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB                                   30
+#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK                                  0x7f000000
+
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET                      0x0000000c
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB                         31
+#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK                        0x80000000
+
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET                                0x00000010
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB                                   0
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB                                   7
+#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK                                  0x000000ff
+
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET                                    0x00000010
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB                                       8
+#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK                                      0x00000100
+
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET                                     0x00000010
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB                                        9
+#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK                                       0x00000200
+
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET                            0x00000010
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB                               10
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB                               12
+#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK                              0x00001c00
+
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET                              0x00000010
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB                                 13
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB                                 31
+#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK                                0xffffe000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET        0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB           0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK          0x00000001
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB                        1
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB                        3
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK                       0x0000000e
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET               0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                  4
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                  7
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                 0x000000f0
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB                      8
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK                     0x00000100
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                   0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB                      9
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK                     0x00000200
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB                       10
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB                       11
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK                      0x00000c00
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB                       12
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB                       16
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK                      0x0001f000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET         0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB            17
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB            19
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK           0x000e0000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET              0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                 20
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                0x00100000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB                        21
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB                        24
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK                       0x01e00000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET                     0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB                        25
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB                        28
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK                       0x1e000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                    0x00000014
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB                       29
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB                       31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK                      0xe0000000
+
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET           0x00000018
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB              0
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB              31
+#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK             0xffffffff
+
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET                                    0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB                                       0
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB                                       15
+#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK                                      0x0000ffff
+
+#define TQM2SW_COMPLETION_RING_TID_OFFSET                                           0x0000001c
+#define TQM2SW_COMPLETION_RING_TID_LSB                                              16
+#define TQM2SW_COMPLETION_RING_TID_MSB                                              19
+#define TQM2SW_COMPLETION_RING_TID_MASK                                             0x000f0000
+
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET                        0x0000001c
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB                           20
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB                           27
+#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK                          0x0ff00000
+
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET                                 0x0000001c
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB                                    28
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB                                    31
+#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK                                   0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_cbf_info.h b/hw/wcn8750/v1/tx_cbf_info.h
new file mode 100644
index 000000000000..772b09d7b2a1
--- /dev/null
+++ b/hw/wcn8750/v1/tx_cbf_info.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_CBF_INFO_H_
+#define _TX_CBF_INFO_H_
+
+#define NUM_OF_DWORDS_TX_CBF_INFO 16
+
+#define NUM_OF_QWORDS_TX_CBF_INFO 8
+
+struct tx_cbf_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sw_peer_id                                              : 16,
+                      pre_cbf_duration                                        : 16;
+             uint32_t brpoll_info_valid                                       :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      bandwidth                                               :  3,
+                      brpoll_info                                             :  8,
+                      cbf_response_table_base_index                           :  8,
+                      peer_index                                              :  3,
+                      pkt_type                                                :  4,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t trigger_brpoll_common_info_15_0                         : 16,
+                      trigger_brpoll_common_info_31_16                        : 16;
+             uint32_t trigger_brpoll_user_info_15_0                           : 16,
+                      trigger_brpoll_user_info_31_16                          : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      sta_partial_aid                                         : 11,
+                      __reserved_g_0086                                                 :  1,
+                      reserved_8a                                             :  3,
+                      cbf_resp_pwr_mgmt                                       :  1;
+             uint32_t group_id                                                :  6,
+                      rssi_comb                                               :  8,
+                      reserved_9a                                             :  2,
+                      vht_ndpa_sta_info                                       : 16;
+             uint32_t he_eht_sta_info_15_0                                    : 16,
+                      he_eht_sta_info_31_16                                   : 16;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_11a                                            :  8;
+             uint32_t sw_response_frame_length                                : 16,
+                      sw_response_tlv_from_crypto                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2,
+                      __reserved_g_0005                                                 :  1,
+                      secure                                                  :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      emlsr_main_tlv_if                                       :  1,
+                      reserved_12a                                            :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      npda_info_11be_valid                                    :  1,
+                      eht_duplicate_mode                                      :  2,
+                      reserved_13a                                            : 11;
+             uint32_t eht_sta_info_39_32                                      :  8,
+                      unassociated___reserved_g_0005_peer                               :  1,
+                      reserved_14a                                            : 23;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t pre_cbf_duration                                        : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      pkt_type                                                :  4,
+                      peer_index                                              :  3,
+                      cbf_response_table_base_index                           :  8,
+                      brpoll_info                                             :  8,
+                      bandwidth                                               :  3,
+                      dot11ax_su_extended                                     :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      brpoll_info_valid                                       :  1;
+             uint32_t trigger_brpoll_common_info_31_16                        : 16,
+                      trigger_brpoll_common_info_15_0                         : 16;
+             uint32_t trigger_brpoll_user_info_31_16                          : 16,
+                      trigger_brpoll_user_info_15_0                           : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t cbf_resp_pwr_mgmt                                       :  1,
+                      reserved_8a                                             :  3,
+                      __reserved_g_0086                                                 :  1,
+                      sta_partial_aid                                         : 11,
+                      addr3_47_32                                             : 16;
+             uint32_t vht_ndpa_sta_info                                       : 16,
+                      reserved_9a                                             :  2,
+                      rssi_comb                                               :  8,
+                      group_id                                                :  6;
+             uint32_t he_eht_sta_info_31_16                                   : 16,
+                      he_eht_sta_info_15_0                                    : 16;
+             uint32_t reserved_11a                                            :  8,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_12a                                            :  1,
+                      emlsr_main_tlv_if                                       :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      secure                                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      sw_response_frame_length                                : 16;
+             uint32_t reserved_13a                                            : 11,
+                      eht_duplicate_mode                                      :  2,
+                      npda_info_11be_valid                                    :  1,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_14a                                            : 23,
+                      unassociated___reserved_g_0005_peer                               :  1,
+                      eht_sta_info_39_32                                      :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_CBF_INFO_SW_PEER_ID_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_SW_PEER_ID_LSB                                                  0
+#define TX_CBF_INFO_SW_PEER_ID_MSB                                                  15
+#define TX_CBF_INFO_SW_PEER_ID_MASK                                                 0x000000000000ffff
+
+#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET                                         0x0000000000000000
+#define TX_CBF_INFO_PRE_CBF_DURATION_LSB                                            16
+#define TX_CBF_INFO_PRE_CBF_DURATION_MSB                                            31
+#define TX_CBF_INFO_PRE_CBF_DURATION_MASK                                           0x00000000ffff0000
+
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET                                        0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB                                           32
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK                                          0x0000000100000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET                                0x0000000000000000
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB                                   33
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK                                  0x0000000200000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB                                        34
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK                                       0x0000000400000000
+
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET                                     0x0000000000000000
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB                                        35
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK                                       0x0000000800000000
+
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET                                      0x0000000000000000
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB                                         36
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK                                        0x0000001000000000
+
+#define TX_CBF_INFO_BANDWIDTH_OFFSET                                                0x0000000000000000
+#define TX_CBF_INFO_BANDWIDTH_LSB                                                   37
+#define TX_CBF_INFO_BANDWIDTH_MSB                                                   39
+#define TX_CBF_INFO_BANDWIDTH_MASK                                                  0x000000e000000000
+
+#define TX_CBF_INFO_BRPOLL_INFO_OFFSET                                              0x0000000000000000
+#define TX_CBF_INFO_BRPOLL_INFO_LSB                                                 40
+#define TX_CBF_INFO_BRPOLL_INFO_MSB                                                 47
+#define TX_CBF_INFO_BRPOLL_INFO_MASK                                                0x0000ff0000000000
+
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET                            0x0000000000000000
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB                               48
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB                               55
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK                              0x00ff000000000000
+
+#define TX_CBF_INFO_PEER_INDEX_OFFSET                                               0x0000000000000000
+#define TX_CBF_INFO_PEER_INDEX_LSB                                                  56
+#define TX_CBF_INFO_PEER_INDEX_MSB                                                  58
+#define TX_CBF_INFO_PEER_INDEX_MASK                                                 0x0700000000000000
+
+#define TX_CBF_INFO_PKT_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_CBF_INFO_PKT_TYPE_LSB                                                    59
+#define TX_CBF_INFO_PKT_TYPE_MSB                                                    62
+#define TX_CBF_INFO_PKT_TYPE_MASK                                                   0x7800000000000000
+
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET                                   0x0000000000000000
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB                                      63
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK                                     0x8000000000000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET                          0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB                             0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB                             15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK                            0x000000000000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET                         0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB                            16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB                            31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK                           0x00000000ffff0000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET                            0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB                               32
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB                               47
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK                              0x0000ffff00000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET                           0x0000000000000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB                              48
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB                              63
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK                             0xffff000000000000
+
+#define TX_CBF_INFO_ADDR1_31_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR1_31_0_LSB                                                  0
+#define TX_CBF_INFO_ADDR1_31_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR1_31_0_MASK                                                 0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR1_47_32_OFFSET                                              0x0000000000000010
+#define TX_CBF_INFO_ADDR1_47_32_LSB                                                 32
+#define TX_CBF_INFO_ADDR1_47_32_MSB                                                 47
+#define TX_CBF_INFO_ADDR1_47_32_MASK                                                0x0000ffff00000000
+
+#define TX_CBF_INFO_ADDR2_15_0_OFFSET                                               0x0000000000000010
+#define TX_CBF_INFO_ADDR2_15_0_LSB                                                  48
+#define TX_CBF_INFO_ADDR2_15_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR2_15_0_MASK                                                 0xffff000000000000
+
+#define TX_CBF_INFO_ADDR2_47_16_OFFSET                                              0x0000000000000018
+#define TX_CBF_INFO_ADDR2_47_16_LSB                                                 0
+#define TX_CBF_INFO_ADDR2_47_16_MSB                                                 31
+#define TX_CBF_INFO_ADDR2_47_16_MASK                                                0x00000000ffffffff
+
+#define TX_CBF_INFO_ADDR3_31_0_OFFSET                                               0x0000000000000018
+#define TX_CBF_INFO_ADDR3_31_0_LSB                                                  32
+#define TX_CBF_INFO_ADDR3_31_0_MSB                                                  63
+#define TX_CBF_INFO_ADDR3_31_0_MASK                                                 0xffffffff00000000
+
+#define TX_CBF_INFO_ADDR3_47_32_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_ADDR3_47_32_LSB                                                 0
+#define TX_CBF_INFO_ADDR3_47_32_MSB                                                 15
+#define TX_CBF_INFO_ADDR3_47_32_MASK                                                0x000000000000ffff
+
+#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET                                          0x0000000000000020
+#define TX_CBF_INFO_STA_PARTIAL_AID_LSB                                             16
+#define TX_CBF_INFO_STA_PARTIAL_AID_MSB                                             26
+#define TX_CBF_INFO_STA_PARTIAL_AID_MASK                                            0x0000000007ff0000
+
+#define TX_CBF_INFO_RESERVED_8A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_8A_LSB                                                 28
+#define TX_CBF_INFO_RESERVED_8A_MSB                                                 30
+#define TX_CBF_INFO_RESERVED_8A_MASK                                                0x0000000070000000
+
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK                                          0x0000000080000000
+
+#define TX_CBF_INFO_GROUP_ID_OFFSET                                                 0x0000000000000020
+#define TX_CBF_INFO_GROUP_ID_LSB                                                    32
+#define TX_CBF_INFO_GROUP_ID_MSB                                                    37
+#define TX_CBF_INFO_GROUP_ID_MASK                                                   0x0000003f00000000
+
+#define TX_CBF_INFO_RSSI_COMB_OFFSET                                                0x0000000000000020
+#define TX_CBF_INFO_RSSI_COMB_LSB                                                   38
+#define TX_CBF_INFO_RSSI_COMB_MSB                                                   45
+#define TX_CBF_INFO_RSSI_COMB_MASK                                                  0x00003fc000000000
+
+#define TX_CBF_INFO_RESERVED_9A_OFFSET                                              0x0000000000000020
+#define TX_CBF_INFO_RESERVED_9A_LSB                                                 46
+#define TX_CBF_INFO_RESERVED_9A_MSB                                                 47
+#define TX_CBF_INFO_RESERVED_9A_MASK                                                0x0000c00000000000
+
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET                                        0x0000000000000020
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB                                           48
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB                                           63
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK                                          0xffff000000000000
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB                                        0
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB                                        15
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK                                       0x000000000000ffff
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET                                    0x0000000000000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB                                       16
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB                                       31
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK                                      0x00000000ffff0000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB                          32
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK                         0x0000000100000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                              0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                                 33
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                                0x0000000200000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET                            0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                               34
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                               39
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                              0x000000fc00000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET                           0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                              40
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                              43
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK                             0x00000f0000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                                 0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                                    44
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                                    45
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                                   0x0000300000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                                0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                                   46
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                                   47
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                                  0x0000c00000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET                                  0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB                                     48
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK                                    0x0001000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET                                     0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB                                        49
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK                                       0x0002000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET                      0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB                         50
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK                        0x0004000000000000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET                             0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                                51
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                                54
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                               0x0078000000000000
+
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET                                       0x0000000000000028
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB                                          55
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK                                         0x0080000000000000
+
+#define TX_CBF_INFO_RESERVED_11A_OFFSET                                             0x0000000000000028
+#define TX_CBF_INFO_RESERVED_11A_LSB                                                56
+#define TX_CBF_INFO_RESERVED_11A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_11A_MASK                                               0xff00000000000000
+
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                                 0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                                    0
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                                    15
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                                   0x000000000000ffff
+
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                              0x0000000000000030
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                                0x0000000000010000
+
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                                   0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK                                     0x0000000000020000
+
+#define TX_CBF_INFO_WAIT_SIFS_OFFSET                                                0x0000000000000030
+#define TX_CBF_INFO_WAIT_SIFS_LSB                                                   18
+#define TX_CBF_INFO_WAIT_SIFS_MSB                                                   19
+#define TX_CBF_INFO_WAIT_SIFS_MASK                                                  0x00000000000c0000
+
+#define TX_CBF_INFO_SECURE_OFFSET                                                   0x0000000000000030
+#define TX_CBF_INFO_SECURE_LSB                                                      21
+#define TX_CBF_INFO_SECURE_MSB                                                      21
+#define TX_CBF_INFO_SECURE_MASK                                                     0x0000000000200000
+
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET                                        0x0000000000000030
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK                                          0x0000000001000000
+
+#define TX_CBF_INFO_RESERVED_12A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_12A_LSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MASK                                               0x0000000002000000
+
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                          0x0000000000000030
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                             26
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                             31
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                            0x00000000fc000000
+
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                                  0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                                     32
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                                     47
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                                    0x0000ffff00000000
+
+#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET                                         0x0000000000000030
+#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB                                            48
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK                                           0x0001000000000000
+
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB                                          49
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK                                         0x0002000000000000
+
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET                                     0x0000000000000030
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB                                        50
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK                                       0x0004000000000000
+
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET                                       0x0000000000000030
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB                                          51
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB                                          52
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK                                         0x0018000000000000
+
+#define TX_CBF_INFO_RESERVED_13A_OFFSET                                             0x0000000000000030
+#define TX_CBF_INFO_RESERVED_13A_LSB                                                53
+#define TX_CBF_INFO_RESERVED_13A_MSB                                                63
+#define TX_CBF_INFO_RESERVED_13A_MASK                                               0xffe0000000000000
+
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET                                       0x0000000000000038
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB                                          0
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB                                          7
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK                                         0x00000000000000ff
+
+#define TX_CBF_INFO_RESERVED_14A_OFFSET                                             0x0000000000000038
+#define TX_CBF_INFO_RESERVED_14A_LSB                                                9
+#define TX_CBF_INFO_RESERVED_14A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_14A_MASK                                               0x00000000fffffe00
+
+#define TX_CBF_INFO_TLV64_PADDING_OFFSET                                            0x0000000000000038
+#define TX_CBF_INFO_TLV64_PADDING_LSB                                               32
+#define TX_CBF_INFO_TLV64_PADDING_MSB                                               63
+#define TX_CBF_INFO_TLV64_PADDING_MASK                                              0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_setup.h b/hw/wcn8750/v1/tx_fes_setup.h
new file mode 100644
index 000000000000..360e373b8019
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_setup.h
@@ -0,0 +1,585 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_SETUP_H_
+#define _TX_FES_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_FES_SETUP 10
+
+#define NUM_OF_QWORDS_TX_FES_SETUP 5
+
+struct tx_fes_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t fes_in_11ax_trigger_response_config                     :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      __reserved_g_0005                                                 :  1,
+                      expect_i2r_lmr                                          :  1,
+                      transmit_start_reason                                   :  3,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      puncture_from_all_allowed_modes                         :  1,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      number_of_users                                         :  6,
+                      mu_type                                                 :  1,
+                      ofdma_triggered_response                                :  1,
+                      response_to_response_cmd                                :  1;
+             uint32_t schedule_try                                            :  4,
+                      reserved_2a                                             :  1,
+                      subband_antenna_selection_en                            :  1,
+                      txbf                                                    :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      ignore_bw_available                                     :  1,
+                      ignore_tbtt                                             :  1,
+                      static_bandwidth                                        :  3,
+                      set_txop_duration_all_ones                              :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      bw_restricted_frames_embedded                           :  1,
+                      ast_index                                               : 16;
+             uint32_t cv_id                                                   :  8,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      rxpcu_setup_complete_present                            :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      mu_ndp                                                  :  1,
+                      bf_type                                                 :  2,
+                      cbf_nc_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nr_index                                            :  3,
+                      secure___reserved_g_0005_ista                                     :  1,
+                      ndpa                                                    :  1,
+                      wait_sifs                                               :  2,
+                      cbf_feedback_type_mask                                  :  1,
+                      cbf_feedback_type                                       :  1;
+             uint32_t cbf_sounding_token                                      :  6,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_bw_mask                                             :  1,
+                      cbf_bw                                                  :  3,
+                      use_static_bw                                           :  1,
+                      coex_nack_count                                         :  5,
+                      sch_tx_burst_ongoing                                    :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      ndp_frame                                               :  3,
+                      optimal_bw_retry_count                                  :  4,
+                      fes_continuation_ratio_threshold                        :  5;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t tb___reserved_g_0005                                              :  1,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      min_cts2self_count                                      :  4,
+                      max_cts2self_count                                      :  4,
+                      wifi_radar_enable                                       :  1,
+                      reserved_6a                                             :  1,
+                      wait_for_chksum_done                                    :  1,
+                      txrx_self_test_enable                                   :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      secure___reserved_g_0005_rsta                                     :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      last_command_in_burst                                   :  1,
+                      retain_peer_blackout_details                            :  1,
+                      enable_hw_qos_null                                      :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t monitor_override_sta_36_32                              :  5,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      __reserved_g_0086                                                 :  1,
+                      __reserved_g_0081                                       :  1,
+                      __reserved_g_0084                                            :  2,
+                      __reserved_g_0074                                       :  4,
+                      cfp_protected_fes                                       :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      multiple_triggers_indication                            :  1,
+                      cmf_uif_length                                          :  4,
+                      npca_switching_cts2self_duration                        :  8,
+                      reserved_8a                                             :  3;
+             uint32_t fw2sw_info                                              : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t response_to_response_cmd                                :  1,
+                      ofdma_triggered_response                                :  1,
+                      mu_type                                                 :  1,
+                      number_of_users                                         :  6,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      puncture_from_all_allowed_modes                         :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      transmit_start_reason                                   :  3,
+                      expect_i2r_lmr                                          :  1,
+                      __reserved_g_0005                                                 :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      fes_in_11ax_trigger_response_config                     :  1;
+             uint32_t ast_index                                               : 16,
+                      bw_restricted_frames_embedded                           :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      set_txop_duration_all_ones                              :  1,
+                      static_bandwidth                                        :  3,
+                      ignore_tbtt                                             :  1,
+                      ignore_bw_available                                     :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      txbf                                                    :  1,
+                      subband_antenna_selection_en                            :  1,
+                      reserved_2a                                             :  1,
+                      schedule_try                                            :  4;
+             uint32_t cbf_feedback_type                                       :  1,
+                      cbf_feedback_type_mask                                  :  1,
+                      wait_sifs                                               :  2,
+                      ndpa                                                    :  1,
+                      secure___reserved_g_0005_ista                                     :  1,
+                      cbf_nr_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nc_index_mask                                       :  1,
+                      bf_type                                                 :  2,
+                      mu_ndp                                                  :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      rxpcu_setup_complete_present                            :  1,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      cv_id                                                   :  8;
+             uint32_t fes_continuation_ratio_threshold                        :  5,
+                      optimal_bw_retry_count                                  :  4,
+                      ndp_frame                                               :  3,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_nack_count                                         :  5,
+                      use_static_bw                                           :  1,
+                      cbf_bw                                                  :  3,
+                      cbf_bw_mask                                             :  1,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_sounding_token                                      :  6;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t enable_hw_qos_null                                      :  1,
+                      retain_peer_blackout_details                            :  1,
+                      last_command_in_burst                                   :  1,
+                      hip_edca_mini_contention_gap                            :  8,
+                      hip_edca_prot_required                                  :  1,
+                      hip_edca_prot_enable                                    :  1,
+                      secure___reserved_g_0005_rsta                                     :  1,
+                      rtt_self_cal_enable                                     :  1,
+                      txrx_self_test_enable                                   :  1,
+                      wait_for_chksum_done                                    :  1,
+                      reserved_6a                                             :  1,
+                      wifi_radar_enable                                       :  1,
+                      max_cts2self_count                                      :  4,
+                      min_cts2self_count                                      :  4,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      tb___reserved_g_0005                                              :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t reserved_8a                                             :  3,
+                      npca_switching_cts2self_duration                        :  8,
+                      cmf_uif_length                                          :  4,
+                      multiple_triggers_indication                            :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      cfp_protected_fes                                       :  1,
+                      __reserved_g_0074                                       :  4,
+                      __reserved_g_0084                                            :  2,
+                      __reserved_g_0081                                       :  1,
+                      __reserved_g_0086                                                 :  1,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      monitor_override_sta_36_32                              :  5;
+             uint32_t fw2sw_info                                              : 32;
+#endif
+};
+
+#define TX_FES_SETUP_SCHEDULE_ID_OFFSET                                             0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_ID_LSB                                                0
+#define TX_FES_SETUP_SCHEDULE_ID_MSB                                                31
+#define TX_FES_SETUP_SCHEDULE_ID_MASK                                               0x00000000ffffffff
+
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                     0x0000000000000000
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                        32
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                       0x0000000100000000
+
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000000
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB                             33
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB                             36
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK                            0x0000001e00000000
+
+#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET                                          0x0000000000000000
+#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB                                             38
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK                                            0x0000004000000000
+
+#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET                                   0x0000000000000000
+#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB                                      39
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB                                      41
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK                                     0x0000038000000000
+
+#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB                                           42
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK                                          0x0000040000000000
+
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB                                   43
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK                                  0x0000080000000000
+
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                            44
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                           0x0000100000000000
+
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET                               0x0000000000000000
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB                                  45
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK                                 0x0000200000000000
+
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                           0x0000000000000000
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                              46
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                             0x0000400000000000
+
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET                         0x0000000000000000
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB                            47
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK                           0x0000800000000000
+
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET                                    0x0000000000000000
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB                                       48
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB                                       52
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK                                      0x001f000000000000
+
+#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET                                        0x0000000000000000
+#define TX_FES_SETUP_FES_CONTROL_MODE_LSB                                           53
+#define TX_FES_SETUP_FES_CONTROL_MODE_MSB                                           54
+#define TX_FES_SETUP_FES_CONTROL_MODE_MASK                                          0x0060000000000000
+
+#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET                                         0x0000000000000000
+#define TX_FES_SETUP_NUMBER_OF_USERS_LSB                                            55
+#define TX_FES_SETUP_NUMBER_OF_USERS_MSB                                            60
+#define TX_FES_SETUP_NUMBER_OF_USERS_MASK                                           0x1f80000000000000
+
+#define TX_FES_SETUP_MU_TYPE_OFFSET                                                 0x0000000000000000
+#define TX_FES_SETUP_MU_TYPE_LSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MSB                                                    61
+#define TX_FES_SETUP_MU_TYPE_MASK                                                   0x2000000000000000
+
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB                                   62
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK                                  0x4000000000000000
+
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET                                0x0000000000000000
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB                                   63
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK                                  0x8000000000000000
+
+#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_SCHEDULE_TRY_LSB                                               0
+#define TX_FES_SETUP_SCHEDULE_TRY_MSB                                               3
+#define TX_FES_SETUP_SCHEDULE_TRY_MASK                                              0x000000000000000f
+
+#define TX_FES_SETUP_RESERVED_2A_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_RESERVED_2A_LSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MSB                                                4
+#define TX_FES_SETUP_RESERVED_2A_MASK                                               0x0000000000000010
+
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB                               5
+#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK                              0x0000000000000020
+
+#define TX_FES_SETUP_TXBF_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_TXBF_LSB                                                       6
+#define TX_FES_SETUP_TXBF_MSB                                                       6
+#define TX_FES_SETUP_TXBF_MASK                                                      0x0000000000000040
+
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK                              0x0000000000000080
+
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET                                     0x0000000000000008
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK                                       0x0000000000000100
+
+#define TX_FES_SETUP_IGNORE_TBTT_OFFSET                                             0x0000000000000008
+#define TX_FES_SETUP_IGNORE_TBTT_LSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MASK                                               0x0000000000000200
+
+#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET                                        0x0000000000000008
+#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB                                           10
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB                                           12
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK                                          0x0000000000001c00
+
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET                              0x0000000000000008
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK                                0x0000000000002000
+
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK                              0x0000000000004000
+
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK                             0x0000000000008000
+
+#define TX_FES_SETUP_AST_INDEX_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_AST_INDEX_LSB                                                  16
+#define TX_FES_SETUP_AST_INDEX_MSB                                                  31
+#define TX_FES_SETUP_AST_INDEX_MASK                                                 0x00000000ffff0000
+
+#define TX_FES_SETUP_CV_ID_OFFSET                                                   0x0000000000000008
+#define TX_FES_SETUP_CV_ID_LSB                                                      32
+#define TX_FES_SETUP_CV_ID_MSB                                                      39
+#define TX_FES_SETUP_CV_ID_MASK                                                     0x000000ff00000000
+
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET                        0x0000000000000008
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB                           40
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB                           41
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK                          0x0000030000000000
+
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET                            0x0000000000000008
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB                               42
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK                              0x0000040000000000
+
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET                           0x0000000000000008
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB                              43
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB                              46
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK                             0x0000780000000000
+
+#define TX_FES_SETUP_MU_NDP_OFFSET                                                  0x0000000000000008
+#define TX_FES_SETUP_MU_NDP_LSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MSB                                                     47
+#define TX_FES_SETUP_MU_NDP_MASK                                                    0x0000800000000000
+
+#define TX_FES_SETUP_BF_TYPE_OFFSET                                                 0x0000000000000008
+#define TX_FES_SETUP_BF_TYPE_LSB                                                    48
+#define TX_FES_SETUP_BF_TYPE_MSB                                                    49
+#define TX_FES_SETUP_BF_TYPE_MASK                                                   0x0003000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB                                          50
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK                                         0x0004000000000000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NC_INDEX_LSB                                               51
+#define TX_FES_SETUP_CBF_NC_INDEX_MSB                                               53
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK                                              0x0038000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB                                          54
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK                                         0x0040000000000000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET                                            0x0000000000000008
+#define TX_FES_SETUP_CBF_NR_INDEX_LSB                                               55
+#define TX_FES_SETUP_CBF_NR_INDEX_MSB                                               57
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK                                              0x0380000000000000
+
+#define TX_FES_SETUP_NDPA_OFFSET                                                    0x0000000000000008
+#define TX_FES_SETUP_NDPA_LSB                                                       59
+#define TX_FES_SETUP_NDPA_MSB                                                       59
+#define TX_FES_SETUP_NDPA_MASK                                                      0x0800000000000000
+
+#define TX_FES_SETUP_WAIT_SIFS_OFFSET                                               0x0000000000000008
+#define TX_FES_SETUP_WAIT_SIFS_LSB                                                  60
+#define TX_FES_SETUP_WAIT_SIFS_MSB                                                  61
+#define TX_FES_SETUP_WAIT_SIFS_MASK                                                 0x3000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET                                  0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB                                     62
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK                                    0x4000000000000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET                                       0x0000000000000008
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB                                          63
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK                                         0x8000000000000000
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET                                      0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB                                         0
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB                                         5
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK                                        0x000000000000003f
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET                                 0x0000000000000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK                                   0x0000000000000040
+
+#define TX_FES_SETUP_CBF_BW_MASK_OFFSET                                             0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_MASK_LSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MASK                                               0x0000000000000080
+
+#define TX_FES_SETUP_CBF_BW_OFFSET                                                  0x0000000000000010
+#define TX_FES_SETUP_CBF_BW_LSB                                                     8
+#define TX_FES_SETUP_CBF_BW_MSB                                                     10
+#define TX_FES_SETUP_CBF_BW_MASK                                                    0x0000000000000700
+
+#define TX_FES_SETUP_USE_STATIC_BW_OFFSET                                           0x0000000000000010
+#define TX_FES_SETUP_USE_STATIC_BW_LSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MASK                                             0x0000000000000800
+
+#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET                                         0x0000000000000010
+#define TX_FES_SETUP_COEX_NACK_COUNT_LSB                                            12
+#define TX_FES_SETUP_COEX_NACK_COUNT_MSB                                            16
+#define TX_FES_SETUP_COEX_NACK_COUNT_MASK                                           0x000000000001f000
+
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET                                    0x0000000000000010
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK                                      0x0000000000020000
+
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET                           0x0000000000000010
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK                             0x0000000000040000
+
+#define TX_FES_SETUP_NDP_FRAME_OFFSET                                               0x0000000000000010
+#define TX_FES_SETUP_NDP_FRAME_LSB                                                  20
+#define TX_FES_SETUP_NDP_FRAME_MSB                                                  22
+#define TX_FES_SETUP_NDP_FRAME_MASK                                                 0x0000000000700000
+
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET                                  0x0000000000000010
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB                                     23
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB                                     26
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK                                    0x0000000007800000
+
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET                        0x0000000000000010
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB                           27
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB                           31
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK                          0x00000000f8000000
+
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET                                     0x0000000000000010
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB                                        32
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB                                        63
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK                                       0xffffffff00000000
+
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB                                         5
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB                                         8
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK                                        0x00000000000001e0
+
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB                                         9
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB                                         12
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK                                        0x0000000000001e00
+
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET                                       0x0000000000000018
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK                                         0x0000000000002000
+
+#define TX_FES_SETUP_RESERVED_6A_OFFSET                                             0x0000000000000018
+#define TX_FES_SETUP_RESERVED_6A_LSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MASK                                               0x0000000000004000
+
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK                                      0x0000000000008000
+
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB                                      16
+#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK                                     0x0000000000010000
+
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET                                     0x0000000000000018
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB                                        17
+#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK                                       0x0000000000020000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET                                    0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB                                       19
+#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK                                      0x0000000000080000
+
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET                                  0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB                                     20
+#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK                                    0x0000000000100000
+
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB                               21
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB                               28
+#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK                              0x000000001fe00000
+
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET                                   0x0000000000000018
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB                                      29
+#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK                                     0x0000000020000000
+
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET                            0x0000000000000018
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB                               30
+#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK                              0x0000000040000000
+
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET                                      0x0000000000000018
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK                                        0x0000000080000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET                               0x0000000000000018
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB                                  32
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB                                  63
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK                                 0xffffffff00000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET                              0x0000000000000020
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB                                 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB                                 4
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK                                0x000000000000001f
+
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET                         0x0000000000000020
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK                           0x0000000000000020
+
+#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET                                       0x0000000000000020
+#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB                                          14
+#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB                                          14
+#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK                                         0x0000000000004000
+
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                          0x0000000000000020
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                             15
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                             15
+#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                            0x0000000000008000
+
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET                            0x0000000000000020
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB                               16
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB                               16
+#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK                              0x0000000000010000
+
+#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET                                          0x0000000000000020
+#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB                                             17
+#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB                                             20
+#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK                                            0x00000000001e0000
+
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET                        0x0000000000000020
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB                           21
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB                           28
+#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK                          0x000000001fe00000
+
+#define TX_FES_SETUP_RESERVED_8A_OFFSET                                             0x0000000000000020
+#define TX_FES_SETUP_RESERVED_8A_LSB                                                29
+#define TX_FES_SETUP_RESERVED_8A_MSB                                                31
+#define TX_FES_SETUP_RESERVED_8A_MASK                                               0x00000000e0000000
+
+#define TX_FES_SETUP_FW2SW_INFO_OFFSET                                              0x0000000000000020
+#define TX_FES_SETUP_FW2SW_INFO_LSB                                                 32
+#define TX_FES_SETUP_FW2SW_INFO_MSB                                                 63
+#define TX_FES_SETUP_FW2SW_INFO_MASK                                                0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_1k_ba.h b/hw/wcn8750/v1/tx_fes_status_1k_ba.h
new file mode 100644
index 000000000000..4409dc03ac03
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_1k_ba.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_1K_BA_H_
+#define _TX_FES_STATUS_1K_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17
+
+struct tx_fes_status_1k_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#endif
+};
+
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK                                 0x0000000000000001
+
+#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK                                            0x0000000000000002
+
+#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_1K_BA_BA_TID_LSB                                              2
+#define TX_FES_STATUS_1K_BA_BA_TID_MSB                                              5
+#define TX_FES_STATUS_1K_BA_BA_TID_MASK                                             0x000000000000003c
+
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK                               0x0000000000000040
+
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK                                   0x0000000000000080
+
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB                                      8
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB                                      15
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK                                     0x000000000000ff00
+
+#define TX_FES_STATUS_1K_BA_SSN_OFFSET                                              0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SSN_LSB                                                 16
+#define TX_FES_STATUS_1K_BA_SSN_MSB                                                 27
+#define TX_FES_STATUS_1K_BA_SSN_MASK                                                0x000000000fff0000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB                                         28
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB                                         31
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK                                        0x00000000f0000000
+
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB                                          32
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB                                          47
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK                                         0x0000ffff00000000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB                                         48
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB                                         63
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK                                        0xffff000000000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB                                      0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB                                      31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK                                     0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB                                     32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB                                     63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK                                    0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET                                  0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB                                     0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB                                     31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK                                    0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB                                    32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB                                    63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK                                   0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET                                0x0000000000000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET                                0x0000000000000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET                                0x0000000000000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET                                0x0000000000000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET                                0x0000000000000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET                                0x0000000000000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET                                0x0000000000000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET                                0x0000000000000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET                                0x0000000000000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET                                0x0000000000000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET                                0x0000000000000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB                                   32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB                                   63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK                                  0xffffffff00000000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET                                0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK                                  0x00000000ffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET                               0x0000000000000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB                                  32
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB                                  63
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h b/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
new file mode 100644
index 000000000000..678c639141ba
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
+#define _TX_FES_STATUS_ACK_OR_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5
+
+struct tx_fes_status_ack_or_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#endif
+};
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK                             0x0000000000000001
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK                                        0x0000000000000002
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB                                          2
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB                                          5
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK                                         0x000000000000003c
+
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK                           0x0000000000000040
+
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK                               0x0000000000000080
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB                                  8
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB                                  15
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK                                 0x000000000000ff00
+
+#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB                                             16
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB                                             27
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK                                            0x000000000fff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB                                     28
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB                                     31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK                                    0x00000000f0000000
+
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET                                   0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB                                      32
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB                                      47
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK                                     0x0000ffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET                                  0x0000000000000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB                                     48
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB                                     63
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK                                    0xffff000000000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB                                  0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB                                  31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET                              0x0000000000000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB                                 32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB                                 63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK                                0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB                                 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB                                 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK                                0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET                             0x0000000000000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB                                32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB                                63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK                               0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET                            0x0000000000000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK                              0xffffffff00000000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK                              0x00000000ffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET                            0x0000000000000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB                               32
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB                               63
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK                              0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_end.h b/hw/wcn8750/v1/tx_fes_status_end.h
new file mode 100644
index 000000000000..f1ac77424029
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_end.h
@@ -0,0 +1,602 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_END_H_
+#define _TX_FES_STATUS_END_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_END 12
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_END 6
+
+struct tx_fes_status_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0052                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0035                                       :  1,
+                      __reserved_g_0036                                       :  1,
+                      __reserved_g_0032                                       :  1,
+                      __reserved_g_0033                                       :  1,
+                      __reserved_g_0072                                       :  1,
+                      __reserved_g_0073                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0066                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0063                                       :  1,
+                      global_data_underflow_warning                           :  1,
+                      global_fes_transmit_result                              :  4,
+                      cbf_bw_received_valid                                   :  1,
+                      cbf_bw_received                                         :  3,
+                      actual_received_ack_type                                :  4,
+                      sta_response_count                                      :  6,
+                      more_data_received                                      :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_after_struct16                                 :  4,
+                      brp_info_valid                                          :  1,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      reserved_1a                                             :  5,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      only_null_delim_sent                                    :  1;
+             uint32_t terminate___reserved_g_0005_sequence                              :  1,
+                      unsolicited_erts_tx                                     :  1,
+                      ects_response_type                                      :  2,
+                      eba_response_type                                       :  2,
+                      response_type                                           :  5,
+                      r2r_end_status_to_follow                                :  1,
+                      service_cbw                                             :  3,
+                      __reserved_g_0039                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0017                                       :  1,
+                      __reserved_g_0018                                       :  1,
+                      __reserved_g_0030                                       :  1,
+                      __reserved_g_0031                                       :  1,
+                      reserved_2c                                             : 11;
+             uint32_t beamform_masked_user_bitmap_15_0                        : 16,
+                      beamform_masked_user_bitmap_31_16                       : 16;
+             uint32_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8,
+                      highest_achieved_data_null_ratio                        :  5,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      pdg_mpdu_ready                                          :  1;
+             uint32_t pdg_mpdu_count                                          : 16,
+                      pdg_est_mpdu_tx_count                                   : 16;
+             uint32_t pdg_overview_length                                     : 24,
+                      txop_duration                                           :  7,
+                      pdg_dropped_mpdu_warning                                :  1;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      fec_type                                                :  1,
+                      stbc                                                    :  1,
+                      num_data_symbols                                        : 16,
+                      ru_size                                                 :  4,
+                      reserved_17a                                            :  4;
+             uint32_t num_ltf_symbols                                         :  3,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      reserved_18a                                            :  5,
+                      dcm                                                     :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      reserved_18b                                            :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8;
+             uint32_t __reserved_g_0005_active_user_map                                 : 16,
+                      __reserved_g_0005_sent_dummy_tx                                   :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0037                                       :  1,
+                      __reserved_g_0038                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0070                                       :  1,
+                      cv_corr_status                                          :  8;
+             uint32_t current_tx_duration                                     : 16,
+                      reserved_21a                                            :  4,
+                      hw_qos_null_bitmap                                      :  8,
+                      hw_qos_null_setup_missing                               :  1,
+                      interference                                            :  1,
+                      reserved_21b                                            :  2;
+             uint32_t reserved_22b                                            :  4,
+                      __reserved_g_0027                                       :  1,
+                      __reserved_g_0028                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0050                                       :  1,
+                      __reserved_g_0025                                       :  1,
+                      __reserved_g_0026                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0048                                       :  1,
+                      __reserved_g_0023                                       :  1,
+                      __reserved_g_0024                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0021                                       :  1,
+                      __reserved_g_0022                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0044                                       :  1,
+                      __reserved_g_0019                                       :  1,
+                      __reserved_g_0020                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0042                                       :  1,
+                      coex_signaling_status                                   :  8;
+#else
+             uint32_t more_data_received                                      :  1,
+                      sta_response_count                                      :  6,
+                      actual_received_ack_type                                :  4,
+                      cbf_bw_received                                         :  3,
+                      cbf_bw_received_valid                                   :  1,
+                      global_fes_transmit_result                              :  4,
+                      global_data_underflow_warning                           :  1,
+                      __reserved_g_0063                                       :  1,
+                      __reserved_g_0062                                       :  1,
+                      __reserved_g_0066                                       :  1,
+                      __reserved_g_0065                                       :  1,
+                      __reserved_g_0073                                       :  1,
+                      __reserved_g_0072                                       :  1,
+                      __reserved_g_0033                                       :  1,
+                      __reserved_g_0032                                       :  1,
+                      __reserved_g_0036                                       :  1,
+                      __reserved_g_0035                                       :  1,
+                      __reserved_g_0053                                       :  1,
+                      __reserved_g_0052                                       :  1;
+             uint32_t only_null_delim_sent                                    :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      reserved_1a                                             :  5,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      brp_info_valid                                          :  1,
+                      reserved_after_struct16                                 :  4;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t reserved_2c                                             : 11,
+                      __reserved_g_0031                                       :  1,
+                      __reserved_g_0030                                       :  1,
+                      __reserved_g_0018                                       :  1,
+                      __reserved_g_0017                                       :  1,
+                      __reserved_g_0040                                       :  1,
+                      __reserved_g_0039                                       :  1,
+                      service_cbw                                             :  3,
+                      r2r_end_status_to_follow                                :  1,
+                      response_type                                           :  5,
+                      eba_response_type                                       :  2,
+                      ects_response_type                                      :  2,
+                      unsolicited_erts_tx                                     :  1,
+                      terminate___reserved_g_0005_sequence                              :  1;
+             uint32_t beamform_masked_user_bitmap_31_16                       : 16,
+                      beamform_masked_user_bitmap_15_0                        : 16;
+             uint32_t pdg_mpdu_ready                                          :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      highest_achieved_data_null_ratio                        :  5,
+                      cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             uint32_t pdg_est_mpdu_tx_count                                   : 16,
+                      pdg_mpdu_count                                          : 16;
+             uint32_t pdg_dropped_mpdu_warning                                :  1,
+                      txop_duration                                           :  7,
+                      pdg_overview_length                                     : 24;
+             uint32_t reserved_17a                                            :  4,
+                      ru_size                                                 :  4,
+                      num_data_symbols                                        : 16,
+                      stbc                                                    :  1,
+                      fec_type                                                :  1,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      reserved_18b                                            :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      dcm                                                     :  1,
+                      reserved_18a                                            :  5,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      num_ltf_symbols                                         :  3;
+             uint32_t cv_corr_status                                          :  8,
+                      __reserved_g_0070                                       :  1,
+                      __reserved_g_0069                                       :  1,
+                      __reserved_g_0038                                       :  1,
+                      __reserved_g_0037                                       :  1,
+                      __reserved_g_0068                                       :  1,
+                      __reserved_g_0067                                       :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      __reserved_g_0005_sent_dummy_tx                                   :  1,
+                      __reserved_g_0005_active_user_map                                 : 16;
+             uint32_t reserved_21b                                            :  2,
+                      interference                                            :  1,
+                      hw_qos_null_setup_missing                               :  1,
+                      hw_qos_null_bitmap                                      :  8,
+                      reserved_21a                                            :  4,
+                      current_tx_duration                                     : 16;
+             uint32_t coex_signaling_status                                   :  8,
+                      __reserved_g_0042                                       :  1,
+                      __reserved_g_0041                                       :  1,
+                      __reserved_g_0020                                       :  1,
+                      __reserved_g_0019                                       :  1,
+                      __reserved_g_0044                                       :  1,
+                      __reserved_g_0043                                       :  1,
+                      __reserved_g_0022                                       :  1,
+                      __reserved_g_0021                                       :  1,
+                      __reserved_g_0046                                       :  1,
+                      __reserved_g_0045                                       :  1,
+                      __reserved_g_0024                                       :  1,
+                      __reserved_g_0023                                       :  1,
+                      __reserved_g_0048                                       :  1,
+                      __reserved_g_0047                                       :  1,
+                      __reserved_g_0026                                       :  1,
+                      __reserved_g_0025                                       :  1,
+                      __reserved_g_0050                                       :  1,
+                      __reserved_g_0049                                       :  1,
+                      __reserved_g_0028                                       :  1,
+                      __reserved_g_0027                                       :  1,
+                      reserved_22b                                            :  4;
+#endif
+};
+
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                        0x0000000000001000
+
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB                            13
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB                            16
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK                           0x000000000001e000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK                                0x0000000000020000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB                                       18
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB                                       20
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK                                      0x00000000001c0000
+
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB                              21
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB                              24
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK                             0x0000000001e00000
+
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB                                    25
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB                                    30
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK                                   0x000000007e000000
+
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB   32
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB   39
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK  0x000000ff00000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET       0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB          40
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB          45
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK         0x00003f0000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET          0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB             46
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB             47
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK            0x0000c00000000000
+
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB                               48
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB                               51
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK                              0x000f000000000000
+
+#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB                                        52
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK                                       0x0010000000000000
+
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB                         53
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK                        0x0020000000000000
+
+#define TX_FES_STATUS_END_RESERVED_1A_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_END_RESERVED_1A_LSB                                           54
+#define TX_FES_STATUS_END_RESERVED_1A_MSB                                           58
+#define TX_FES_STATUS_END_RESERVED_1A_MASK                                          0x07c0000000000000
+
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET                           0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB                              59
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK                             0x0800000000000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                        60
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                       0x1000000000000000
+
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                   61
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                  0x2000000000000000
+
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB                      62
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB                                  63
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK                                 0x8000000000000000
+
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB                                   1
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB                                   1
+#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK                                  0x0000000000000002
+
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB                                    2
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB                                    3
+#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK                                   0x000000000000000c
+
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB                                     4
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB                                     5
+#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK                                    0x0000000000000030
+
+#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET                                      0x0000000000000008
+#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB                                         6
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB                                         10
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK                                        0x00000000000007c0
+
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK                             0x0000000000000800
+
+#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_SERVICE_CBW_LSB                                           12
+#define TX_FES_STATUS_END_SERVICE_CBW_MSB                                           14
+#define TX_FES_STATUS_END_SERVICE_CBW_MASK                                          0x0000000000007000
+
+#define TX_FES_STATUS_END_RESERVED_2C_OFFSET                                        0x0000000000000008
+#define TX_FES_STATUS_END_RESERVED_2C_LSB                                           21
+#define TX_FES_STATUS_END_RESERVED_2C_MSB                                           31
+#define TX_FES_STATUS_END_RESERVED_2C_MASK                                          0x00000000ffe00000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                   0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                      32
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                      47
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                     0x0000ffff00000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                     48
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                     63
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                    0xffff000000000000
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB                              0
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB                              7
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK                             0x00000000000000ff
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB                                 8
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB                                 15
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK                                0x000000000000ff00
+
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET                   0x0000000000000010
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB                      16
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB                      20
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK                     0x00000000001f0000
+
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK                                     0x0000000000200000
+
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK                             0x0000000000400000
+
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                      0x0000000000800000
+
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET                          0x0000000000000010
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK                            0x0000000001000000
+
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                      0x0000000000000010
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                        0x0000000002000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                  0x0000000000000010
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                     26
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                     30
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                    0x000000007c000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK                                       0x0000000080000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET                                     0x0000000000000010
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB                                        32
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB                                        47
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK                                       0x0000ffff00000000
+
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET                              0x0000000000000010
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB                                 48
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB                                 63
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK                                0xffff000000000000
+
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET                                0x0000000000000018
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB                                   0
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB                                   23
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK                                  0x0000000000ffffff
+
+#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET                                      0x0000000000000018
+#define TX_FES_STATUS_END_TXOP_DURATION_LSB                                         24
+#define TX_FES_STATUS_END_TXOP_DURATION_MSB                                         30
+#define TX_FES_STATUS_END_TXOP_DURATION_MASK                                        0x000000007f000000
+
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET                           0x0000000000000018
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK                             0x0000000080000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET                          0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB                             32
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB                             33
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK                            0x0000000300000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                      34
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                     0x0000000400000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB                                      35
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB                                      37
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK                                     0x0000003800000000
+
+#define TX_FES_STATUS_END_FEC_TYPE_OFFSET                                           0x0000000000000018
+#define TX_FES_STATUS_END_FEC_TYPE_LSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MSB                                              38
+#define TX_FES_STATUS_END_FEC_TYPE_MASK                                             0x0000004000000000
+
+#define TX_FES_STATUS_END_STBC_OFFSET                                               0x0000000000000018
+#define TX_FES_STATUS_END_STBC_LSB                                                  39
+#define TX_FES_STATUS_END_STBC_MSB                                                  39
+#define TX_FES_STATUS_END_STBC_MASK                                                 0x0000008000000000
+
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET                                   0x0000000000000018
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB                                      40
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB                                      55
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK                                     0x00ffff0000000000
+
+#define TX_FES_STATUS_END_RU_SIZE_OFFSET                                            0x0000000000000018
+#define TX_FES_STATUS_END_RU_SIZE_LSB                                               56
+#define TX_FES_STATUS_END_RU_SIZE_MSB                                               59
+#define TX_FES_STATUS_END_RU_SIZE_MASK                                              0x0f00000000000000
+
+#define TX_FES_STATUS_END_RESERVED_17A_OFFSET                                       0x0000000000000018
+#define TX_FES_STATUS_END_RESERVED_17A_LSB                                          60
+#define TX_FES_STATUS_END_RESERVED_17A_MSB                                          63
+#define TX_FES_STATUS_END_RESERVED_17A_MASK                                         0xf000000000000000
+
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB                                       0
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB                                       2
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK                                      0x0000000000000007
+
+#define TX_FES_STATUS_END_LTF_SIZE_OFFSET                                           0x0000000000000020
+#define TX_FES_STATUS_END_LTF_SIZE_LSB                                              3
+#define TX_FES_STATUS_END_LTF_SIZE_MSB                                              4
+#define TX_FES_STATUS_END_LTF_SIZE_MASK                                             0x0000000000000018
+
+#define TX_FES_STATUS_END_CP_SETTING_OFFSET                                         0x0000000000000020
+#define TX_FES_STATUS_END_CP_SETTING_LSB                                            5
+#define TX_FES_STATUS_END_CP_SETTING_MSB                                            6
+#define TX_FES_STATUS_END_CP_SETTING_MASK                                           0x0000000000000060
+
+#define TX_FES_STATUS_END_RESERVED_18A_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18A_LSB                                          7
+#define TX_FES_STATUS_END_RESERVED_18A_MSB                                          11
+#define TX_FES_STATUS_END_RESERVED_18A_MASK                                         0x0000000000000f80
+
+#define TX_FES_STATUS_END_DCM_OFFSET                                                0x0000000000000020
+#define TX_FES_STATUS_END_DCM_LSB                                                   12
+#define TX_FES_STATUS_END_DCM_MSB                                                   12
+#define TX_FES_STATUS_END_DCM_MASK                                                  0x0000000000001000
+
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET                                  0x0000000000000020
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK                                    0x0000000000002000
+
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET                                 0x0000000000000020
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK                                   0x0000000000004000
+
+#define TX_FES_STATUS_END_RESERVED_18B_OFFSET                                       0x0000000000000020
+#define TX_FES_STATUS_END_RESERVED_18B_LSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MASK                                         0x0000000000008000
+
+#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET                                      0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB                                         16
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB                                         23
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK                                        0x0000000000ff0000
+
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET                                    0x0000000000000020
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB                                       24
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB                                       31
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK                                      0x00000000ff000000
+
+#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET                                     0x0000000000000020
+#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB                                        56
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB                                        63
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK                                       0xff00000000000000
+
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET                                0x0000000000000028
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB                                   0
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB                                   15
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_END_RESERVED_21A_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21A_LSB                                          16
+#define TX_FES_STATUS_END_RESERVED_21A_MSB                                          19
+#define TX_FES_STATUS_END_RESERVED_21A_MASK                                         0x00000000000f0000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET                                 0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB                                    20
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB                                    27
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK                                   0x000000000ff00000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET                          0x0000000000000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK                            0x0000000010000000
+
+#define TX_FES_STATUS_END_INTERFERENCE_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_INTERFERENCE_LSB                                          29
+#define TX_FES_STATUS_END_INTERFERENCE_MSB                                          29
+#define TX_FES_STATUS_END_INTERFERENCE_MASK                                         0x0000000020000000
+
+#define TX_FES_STATUS_END_RESERVED_21B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_21B_LSB                                          30
+#define TX_FES_STATUS_END_RESERVED_21B_MSB                                          31
+#define TX_FES_STATUS_END_RESERVED_21B_MASK                                         0x00000000c0000000
+
+#define TX_FES_STATUS_END_RESERVED_22B_OFFSET                                       0x0000000000000028
+#define TX_FES_STATUS_END_RESERVED_22B_LSB                                          32
+#define TX_FES_STATUS_END_RESERVED_22B_MSB                                          35
+#define TX_FES_STATUS_END_RESERVED_22B_MASK                                         0x0000000f00000000
+
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET                              0x0000000000000028
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB                                 56
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB                                 63
+#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK                                0xff00000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_prot.h b/hw/wcn8750/v1/tx_fes_status_prot.h
new file mode 100644
index 000000000000..702cc1add940
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_prot.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_PROT_H_
+#define _TX_FES_STATUS_PROT_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2
+
+struct tx_fes_status_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t success                                                 :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      reserved_0                                              : 19,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  5;
+             uint32_t frame_type                                              :  2,
+                      frame_subtype                                           :  4,
+                      rx_pwr_mgmt                                             :  1,
+                      status                                                  :  1,
+                      duration_field                                          : 16,
+                      reserved_1a                                             :  2,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_2a                                             : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t rate_mcs                                                :  5,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      reserved_0                                              : 19,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      success                                                 :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      reserved_1a                                             :  2,
+                      duration_field                                          : 16,
+                      status                                                  :  1,
+                      rx_pwr_mgmt                                             :  1,
+                      frame_subtype                                           :  4,
+                      frame_type                                              :  2;
+             uint32_t reserved_2a                                             : 16;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_PROT_SUCCESS_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_SUCCESS_LSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MASK                                             0x0000000000000001
+
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK                            0x0000000000000002
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                      0x0000000000000004
+
+#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_0_LSB                                           3
+#define TX_FES_STATUS_PROT_RESERVED_0_MSB                                           21
+#define TX_FES_STATUS_PROT_RESERVED_0_MASK                                          0x00000000003ffff8
+
+#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_PKT_TYPE_LSB                                             22
+#define TX_FES_STATUS_PROT_PKT_TYPE_MSB                                             25
+#define TX_FES_STATUS_PROT_PKT_TYPE_MASK                                            0x0000000003c00000
+
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB                                  26
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK                                 0x0000000004000000
+
+#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET                                          0x0000000000000000
+#define TX_FES_STATUS_PROT_RATE_MCS_LSB                                             27
+#define TX_FES_STATUS_PROT_RATE_MCS_MSB                                             31
+#define TX_FES_STATUS_PROT_RATE_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET                                        0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB                                           32
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB                                           33
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK                                          0x0000000300000000
+
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB                                        34
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB                                        37
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK                                       0x0000003c00000000
+
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB                                          38
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK                                         0x0000004000000000
+
+#define TX_FES_STATUS_PROT_STATUS_OFFSET                                            0x0000000000000000
+#define TX_FES_STATUS_PROT_STATUS_LSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MSB                                               39
+#define TX_FES_STATUS_PROT_STATUS_MASK                                              0x0000008000000000
+
+#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET                                    0x0000000000000000
+#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB                                       40
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB                                       55
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK                                      0x00ffff0000000000
+
+#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_RESERVED_1A_LSB                                          56
+#define TX_FES_STATUS_PROT_RESERVED_1A_MSB                                          57
+#define TX_FES_STATUS_PROT_RESERVED_1A_MASK                                         0x0300000000000000
+
+#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET                                           0x0000000000000000
+#define TX_FES_STATUS_PROT_AGC_CBW_LSB                                              58
+#define TX_FES_STATUS_PROT_AGC_CBW_MSB                                              60
+#define TX_FES_STATUS_PROT_AGC_CBW_MASK                                             0x1c00000000000000
+
+#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET                                       0x0000000000000000
+#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB                                          61
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB                                          63
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK                                         0xe000000000000000
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB  0
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB  7
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET      0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB         8
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB         13
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK        0x0000000000003f00
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET         0x0000000000000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB            14
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB            15
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK           0x000000000000c000
+
+#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET                                       0x0000000000000008
+#define TX_FES_STATUS_PROT_RESERVED_2A_LSB                                          16
+#define TX_FES_STATUS_PROT_RESERVED_2A_MSB                                          31
+#define TX_FES_STATUS_PROT_RESERVED_2A_MASK                                         0x00000000ffff0000
+
+#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB                                        32
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB                                        63
+#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_start.h b/hw/wcn8750/v1/tx_fes_status_start.h
new file mode 100644
index 000000000000..bc8e06ec59fb
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_start.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_H_
+#define _TX_FES_STATUS_START_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START 2
+
+struct tx_fes_status_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1a                                             :  8,
+                      transmit_start_reason                                   :  3,
+                      disabled_user_bitmap_36_32                              :  5,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      schedule_try                                            :  4,
+                      medium_prot_type                                        :  3,
+                      reserved_1b                                             :  2;
+             uint32_t optimal_bw_try_count                                    :  4,
+                      number_of_users                                         :  7,
+                      coex_nack_count                                         :  5,
+                      cca_ed0                                                 : 16;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1b                                             :  2,
+                      medium_prot_type                                        :  3,
+                      schedule_try                                            :  4,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      disabled_user_bitmap_36_32                              :  5,
+                      transmit_start_reason                                   :  3,
+                      reserved_1a                                             :  8;
+             uint32_t cca_ed0                                                 : 16,
+                      coex_nack_count                                         :  5,
+                      number_of_users                                         :  7,
+                      optimal_bw_try_count                                    :  4;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_ID_LSB                                         0
+#define TX_FES_STATUS_START_SCHEDULE_ID_MSB                                         31
+#define TX_FES_STATUS_START_SCHEDULE_ID_MASK                                        0x00000000ffffffff
+
+#define TX_FES_STATUS_START_RESERVED_1A_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1A_LSB                                         32
+#define TX_FES_STATUS_START_RESERVED_1A_MSB                                         39
+#define TX_FES_STATUS_START_RESERVED_1A_MASK                                        0x000000ff00000000
+
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET                            0x0000000000000000
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB                               40
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB                               42
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK                              0x0000070000000000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB                          43
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB                          47
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK                         0x0000f80000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET                             0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB                                48
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB                                52
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK                               0x001f000000000000
+
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB                                    53
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB                                    54
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK                                   0x0060000000000000
+
+#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET                                     0x0000000000000000
+#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB                                        55
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB                                        58
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK                                       0x0780000000000000
+
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB                                    59
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB                                    61
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK                                   0x3800000000000000
+
+#define TX_FES_STATUS_START_RESERVED_1B_OFFSET                                      0x0000000000000000
+#define TX_FES_STATUS_START_RESERVED_1B_LSB                                         62
+#define TX_FES_STATUS_START_RESERVED_1B_MSB                                         63
+#define TX_FES_STATUS_START_RESERVED_1B_MASK                                        0xc000000000000000
+
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET                             0x0000000000000008
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB                                0
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB                                3
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK                               0x000000000000000f
+
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB                                     4
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB                                     10
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK                                    0x00000000000007f0
+
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET                                  0x0000000000000008
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB                                     11
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB                                     15
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK                                    0x000000000000f800
+
+#define TX_FES_STATUS_START_CCA_ED0_OFFSET                                          0x0000000000000008
+#define TX_FES_STATUS_START_CCA_ED0_LSB                                             16
+#define TX_FES_STATUS_START_CCA_ED0_MSB                                             31
+#define TX_FES_STATUS_START_CCA_ED0_MASK                                            0x00000000ffff0000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB                           32
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB                           63
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK                          0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_start_ppdu.h b/hw/wcn8750/v1/tx_fes_status_start_ppdu.h
new file mode 100644
index 000000000000..a87b3b0a0ccc
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_start_ppdu.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PPDU_H_
+#define _TX_FES_STATUS_START_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3
+
+struct tx_fes_status_start_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      ndp_frame                                               :  3,
+                      reserved_2b                                             :  1,
+                      coex_based_tx_bw                                        :  3,
+                      coex_based_ant_mask                                     :  8,
+                      reserved_2c                                             :  1;
+             uint32_t coex_based_tx_pwr_shared_ant                            :  8,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      concurrent_bt_tx                                        :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wan_rx                                       :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_result_alt_based                                   :  1,
+                      request_packet_bw                                       :  3,
+                      response_type                                           :  5;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t reserved_2c                                             :  1,
+                      coex_based_ant_mask                                     :  8,
+                      coex_based_tx_bw                                        :  3,
+                      reserved_2b                                             :  1,
+                      ndp_frame                                               :  3,
+                      subband_mask                                            : 16;
+             uint32_t response_type                                           :  5,
+                      request_packet_bw                                       :  3,
+                      coex_result_alt_based                                   :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      concurrent_wan_rx                                       :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_bt_tx                                        :  1,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      coex_based_tx_pwr_shared_ant                            :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB                                      16
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB                                      18
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK                                     0x0000000000070000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK                                   0x0000000000080000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB                               20
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB                               22
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK                              0x0000000000700000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET                         0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB                            23
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB                            30
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK                           0x000000007f800000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK                                   0x0000000080000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB                   32
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB                   39
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK                  0x000000ff00000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB                          40
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB                          47
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK                         0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET                            0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB                               48
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK                              0x0001000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB                             49
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK                            0x0002000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB                              50
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK                             0x0004000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB                              51
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK                             0x0008000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB                          52
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK                         0x0010000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB                        53
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK                       0x0020000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB                         54
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK                        0x0040000000000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB                          55
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK                         0x0080000000000000
+
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET                           0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB                              56
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB                              58
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK                             0x0700000000000000
+
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB                                  59
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK                                 0xf800000000000000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_start_prot.h b/hw/wcn8750/v1/tx_fes_status_start_prot.h
new file mode 100644
index 000000000000..aca9ac5eb28b
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_start_prot.h
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_START_PROT_H_
+#define _TX_FES_STATUS_START_PROT_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3
+
+struct tx_fes_status_start_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      reserved_2b                                             :  4,
+                      prot_coex_based_tx_bw                                   :  3,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_result_alt_based                              :  1;
+             uint32_t prot_coex_tx_pwr_shared_ant                             :  8,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_request_packet_bw                                  :  3,
+                      response_type                                           :  5,
+                      reserved_3a                                             :  1;
+             uint32_t concurrent_rx_activity_tracker1                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      reserved_4a                                             : 18;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t prot_coex_result_alt_based                              :  1,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_based_tx_bw                                   :  3,
+                      reserved_2b                                             :  4,
+                      subband_mask                                            : 16;
+             uint32_t reserved_3a                                             :  1,
+                      response_type                                           :  5,
+                      prot_request_packet_bw                                  :  3,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_coex_tx_pwr_shared_ant                             :  8;
+             uint32_t reserved_4a                                             : 18,
+                      coex_pwr_reduction_wan_ratid1                           :  1,
+                      concurrent_wan_rx_ratid1                                :  1,
+                      concurrent_wan_tx_ratid1                                :  1,
+                      concurrent_rx_activity_tracker6                         :  1,
+                      concurrent_tx_activity_tracker6                         :  1,
+                      concurrent_rx_activity_tracker5                         :  1,
+                      concurrent_tx_activity_tracker5                         :  1,
+                      concurrent_rx_activity_tracker4                         :  1,
+                      concurrent_tx_activity_tracker4                         :  1,
+                      concurrent_rx_activity_tracker3                         :  1,
+                      concurrent_tx_activity_tracker3                         :  1,
+                      concurrent_rx_activity_tracker2                         :  1,
+                      concurrent_tx_activity_tracker2                         :  1,
+                      concurrent_rx_activity_tracker1                         :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK                       0x00000000ffffffff
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET                     0x0000000000000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB                        32
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB                        63
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK                       0xffffffff00000000
+
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK                                  0x000000000000ffff
+
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB                                    16
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK                                   0x00000000000f0000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB                          20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB                          22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK                         0x0000000000700000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET                    0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB                       23
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB                       30
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK                      0x000000007f800000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK                    0x0000000080000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB                    32
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB                    39
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK                   0x000000ff00000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET                        0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB                           40
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB                           47
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK                          0x0000ff0000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET                       0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB                          48
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK                         0x0001000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET                     0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB                        49
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK                       0x0002000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB                         50
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK                        0x0004000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB                         51
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK                        0x0008000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET                  0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB                     52
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK                    0x0010000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET                0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB                   53
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK                  0x0020000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB                    54
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK                   0x0040000000000000
+
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET                      0x0000000000000008
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB                         55
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB                         57
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK                        0x0380000000000000
+
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET                               0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB                                  58
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB                                  62
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK                                 0x7c00000000000000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET                                 0x0000000000000008
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB                                    63
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK                                   0x8000000000000000
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB                0
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK               0x0000000000000001
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB                1
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK               0x0000000000000002
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB                2
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK               0x0000000000000004
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB                3
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK               0x0000000000000008
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB                4
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK               0x0000000000000010
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB                5
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK               0x0000000000000020
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB                6
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK               0x0000000000000040
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB                7
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK               0x0000000000000080
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB                8
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK               0x0000000000000100
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB                9
+#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK               0x0000000000000200
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET             0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB                10
+#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK               0x0000000000000400
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB                       11
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET                    0x0000000000000010
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB                       12
+#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK                      0x0000000000001000
+
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB                  13
+#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK                 0x0000000000002000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET                                 0x0000000000000010
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB                                    14
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB                                    31
+#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK                                   0x00000000ffffc000
+
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET                               0x0000000000000010
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB                                  32
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB                                  63
+#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK                                 0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_user_ppdu.h b/hw/wcn8750/v1/tx_fes_status_user_ppdu.h
new file mode 100644
index 000000000000..dad9a040ff46
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_user_ppdu.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_PPDU_H_
+#define _TX_FES_STATUS_USER_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3
+
+struct tx_fes_status_user_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      bw_drop_underflow_warning                               :  1,
+                      qc_eosp_setting                                         :  1,
+                      mpdu_tx_count                                           : 11,
+                      user_blocked                                            :  1,
+                      pre_trig_response_delim_count                           :  7;
+             uint32_t underflow_byte_count                                    : 16,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      coex_abort_mpdu_count                                   :  9,
+                      transmitted_tid                                         :  4,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      cv_corr_user_valid_in_phy                               :  1;
+             uint32_t duration                                                : 16,
+                      num_eof_delim_added                                     : 16;
+             uint32_t psdu_octet                                              : 24,
+                      qos_buf_state                                           :  8;
+             uint32_t num_null_delim_added                                    : 22,
+                      fc_more_data_setting                                    :  1,
+                      fc_pwr_mgt_setting                                      :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  5;
+             uint32_t ht_control                                              : 32;
+#else
+             uint32_t pre_trig_response_delim_count                           :  7,
+                      user_blocked                                            :  1,
+                      mpdu_tx_count                                           : 11,
+                      qc_eosp_setting                                         :  1,
+                      bw_drop_underflow_warning                               :  1,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t cv_corr_user_valid_in_phy                               :  1,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      transmitted_tid                                         :  4,
+                      coex_abort_mpdu_count                                   :  9,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      underflow_byte_count                                    : 16;
+             uint32_t num_eof_delim_added                                     : 16,
+                      duration                                                : 16;
+             uint32_t qos_buf_state                                           :  8,
+                      psdu_octet                                              : 24;
+             uint32_t mcs                                                     :  5,
+                      nss                                                     :  3,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  1,
+                      num_null_delim_added                                    : 22;
+             uint32_t ht_control                                              : 32;
+#endif
+};
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB                            8
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK                           0x00000000000001ff
+
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET                       0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB                          9
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB                          10
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK                         0x0000000000000600
+
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK                      0x0000000000000800
+
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK                                0x0000000000001000
+
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET                                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB                                   13
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB                                   23
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK                                  0x0000000000ffe000
+
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET                                 0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK                                   0x0000000001000000
+
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET                0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB                   25
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB                   31
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK                  0x00000000fe000000
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET                         0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB                            32
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB                            47
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK                           0x0000ffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB                     48
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK                    0x0001000000000000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET                        0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB                           49
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB                           57
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK                          0x03fe000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET                              0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB                                 58
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB                                 61
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK                                0x3c00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET                   0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB                      62
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK                     0x4000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET                    0x0000000000000000
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB                       63
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK                      0x8000000000000000
+
+#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET                                     0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_DURATION_LSB                                        0
+#define TX_FES_STATUS_USER_PPDU_DURATION_MSB                                        15
+#define TX_FES_STATUS_USER_PPDU_DURATION_MASK                                       0x000000000000ffff
+
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET                          0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB                             16
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB                             31
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK                            0x00000000ffff0000
+
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET                                   0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB                                      55
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK                                     0x00ffffff00000000
+
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET                                0x0000000000000008
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB                                   56
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB                                   63
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK                                  0xff00000000000000
+
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB                            21
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK                           0x00000000003fffff
+
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET                         0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB                            22
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK                           0x0000000000400000
+
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET                           0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB                              23
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK                             0x0000000000800000
+
+#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_NSS_LSB                                             24
+#define TX_FES_STATUS_USER_PPDU_NSS_MSB                                             26
+#define TX_FES_STATUS_USER_PPDU_NSS_MASK                                            0x0000000007000000
+
+#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET                                          0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_MCS_LSB                                             27
+#define TX_FES_STATUS_USER_PPDU_MCS_MSB                                             31
+#define TX_FES_STATUS_USER_PPDU_MCS_MASK                                            0x00000000f8000000
+
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET                                   0x0000000000000010
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB                                      32
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB                                      63
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK                                     0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_fes_status_user_response.h b/hw/wcn8750/v1/tx_fes_status_user_response.h
new file mode 100644
index 000000000000..dea7df35887f
--- /dev/null
+++ b/hw/wcn8750/v1/tx_fes_status_user_response.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
+#define _TX_FES_STATUS_USER_RESPONSE_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
+
+#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1
+
+struct tx_fes_status_user_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fes_transmit_result                                     :  4,
+                      reserved_0                                              : 23,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      mic_overwritten                                         :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t pre_padding_fcs_overwritten                             :  1,
+                      reserved_after_struct16                                 : 15;
+#else
+             uint32_t mic_overwritten                                         :  1,
+                      overwritten_blackout_window_bitmap                      :  4,
+                      reserved_0                                              : 23,
+                      fes_transmit_result                                     :  4;
+             uint32_t reserved_after_struct16                                 : 15,
+                      pre_padding_fcs_overwritten                             :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET                      0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB                         0
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB                         3
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK                        0x000000000000000f
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET                               0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB                                  4
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB                                  26
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK                                 0x0000000007fffff0
+
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET       0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB          27
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB          30
+#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK         0x0000000078000000
+
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET                          0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB                             31
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB                             31
+#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK                            0x0000000080000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB   46
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB   47
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK  0x0000c00000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET              0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB                 48
+#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK                0x0001000000000000
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET                  0x0000000000000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB                     49
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB                     63
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK                    0xfffe000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_flush_req.h b/hw/wcn8750/v1/tx_flush_req.h
new file mode 100644
index 000000000000..af502ec619eb
--- /dev/null
+++ b/hw/wcn8750/v1/tx_flush_req.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_FLUSH_REQ_H_
+#define _TX_FLUSH_REQ_H_
+
+#define NUM_OF_DWORDS_TX_FLUSH_REQ 2
+
+#define NUM_OF_QWORDS_TX_FLUSH_REQ 1
+
+struct tx_flush_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t flush_req_reason                                        :  8,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_user_number_or_link_id                        :  6,
+                      mlo_abort_reason                                        :  5,
+                      reserved_0a                                             :  5;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      mlo_abort_reason                                        :  5,
+                      flush_req_user_number_or_link_id                        :  6,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_reason                                        :  8;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB                                           0
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB                                           7
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK                                          0x00000000000000ff
+
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET                                      0x0000000000000000
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB                                         8
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB                                         15
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK                                        0x000000000000ff00
+
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET                        0x0000000000000000
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB                           16
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB                           21
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK                          0x00000000003f0000
+
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET                                        0x0000000000000000
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB                                           22
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB                                           26
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK                                          0x0000000007c00000
+
+#define TX_FLUSH_REQ_RESERVED_0A_OFFSET                                             0x0000000000000000
+#define TX_FLUSH_REQ_RESERVED_0A_LSB                                                27
+#define TX_FLUSH_REQ_RESERVED_0A_MSB                                                31
+#define TX_FLUSH_REQ_RESERVED_0A_MASK                                               0x00000000f8000000
+
+#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET                                           0x0000000000000000
+#define TX_FLUSH_REQ_TLV64_PADDING_LSB                                              32
+#define TX_FLUSH_REQ_TLV64_PADDING_MSB                                              63
+#define TX_FLUSH_REQ_TLV64_PADDING_MASK                                             0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_mpdu_start.h b/hw/wcn8750/v1/tx_mpdu_start.h
new file mode 100644
index 000000000000..1a0c370d2963
--- /dev/null
+++ b/hw/wcn8750/v1/tx_mpdu_start.h
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MPDU_START_H_
+#define _TX_MPDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MPDU_START 10
+
+#define NUM_OF_QWORDS_TX_MPDU_START 5
+
+struct tx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_length                                             : 14,
+                      frame_not_from_tqm                                      :  1,
+                      vht_control_present                                     :  1,
+                      mpdu_header_length                                      :  8,
+                      retry_count                                             :  7,
+                      wds                                                     :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      mpdu_sequence_number                                    : 12,
+                      raw_already_encrypted                                   :  1,
+                      frame_type                                              :  2,
+                      txdma_dropped_mpdu_warning                              :  1;
+             uint32_t iv_byte_0                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_3                                               :  8;
+             uint32_t iv_byte_4                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_7                                               :  8;
+             uint32_t iv_byte_8                                               :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_11                                              :  8;
+             uint32_t iv_byte_12                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_15                                              :  8;
+             uint32_t iv_byte_16                                              :  8,
+                      iv_byte_17                                              :  8,
+                      iv_len                                                  :  5,
+                      icv_len                                                 :  5,
+                      vht_control_offset                                      :  6;
+             uint32_t mpdu_type                                               :  1,
+                      transmit_bw_restriction                                 :  1,
+                      allowed_transmit_bw                                     :  4,
+                      tx_notify_frame                                         :  3,
+                      frame_subtype                                           :  4,
+                      reserved_8a                                             : 19;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t wds                                                     :  1,
+                      retry_count                                             :  7,
+                      mpdu_header_length                                      :  8,
+                      vht_control_present                                     :  1,
+                      frame_not_from_tqm                                      :  1,
+                      mpdu_length                                             : 14;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t txdma_dropped_mpdu_warning                              :  1,
+                      frame_type                                              :  2,
+                      raw_already_encrypted                                   :  1,
+                      mpdu_sequence_number                                    : 12,
+                      pn_47_32                                                : 16;
+             uint32_t iv_byte_3                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_0                                               :  8;
+             uint32_t iv_byte_7                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_4                                               :  8;
+             uint32_t iv_byte_11                                              :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_8                                               :  8;
+             uint32_t iv_byte_15                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_12                                              :  8;
+             uint32_t vht_control_offset                                      :  6,
+                      icv_len                                                 :  5,
+                      iv_len                                                  :  5,
+                      iv_byte_17                                              :  8,
+                      iv_byte_16                                              :  8;
+             uint32_t reserved_8a                                             : 19,
+                      frame_subtype                                           :  4,
+                      tx_notify_frame                                         :  3,
+                      allowed_transmit_bw                                     :  4,
+                      transmit_bw_restriction                                 :  1,
+                      mpdu_type                                               :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MPDU_START_MPDU_LENGTH_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_MPDU_LENGTH_LSB                                               0
+#define TX_MPDU_START_MPDU_LENGTH_MSB                                               13
+#define TX_MPDU_START_MPDU_LENGTH_MASK                                              0x0000000000003fff
+
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK                                       0x0000000000004000
+
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET                                    0x0000000000000000
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK                                      0x0000000000008000
+
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET                                     0x0000000000000000
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB                                        16
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB                                        23
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK                                       0x0000000000ff0000
+
+#define TX_MPDU_START_RETRY_COUNT_OFFSET                                            0x0000000000000000
+#define TX_MPDU_START_RETRY_COUNT_LSB                                               24
+#define TX_MPDU_START_RETRY_COUNT_MSB                                               30
+#define TX_MPDU_START_RETRY_COUNT_MASK                                              0x000000007f000000
+
+#define TX_MPDU_START_WDS_OFFSET                                                    0x0000000000000000
+#define TX_MPDU_START_WDS_LSB                                                       31
+#define TX_MPDU_START_WDS_MSB                                                       31
+#define TX_MPDU_START_WDS_MASK                                                      0x0000000080000000
+
+#define TX_MPDU_START_PN_31_0_OFFSET                                                0x0000000000000000
+#define TX_MPDU_START_PN_31_0_LSB                                                   32
+#define TX_MPDU_START_PN_31_0_MSB                                                   63
+#define TX_MPDU_START_PN_31_0_MASK                                                  0xffffffff00000000
+
+#define TX_MPDU_START_PN_47_32_OFFSET                                               0x0000000000000008
+#define TX_MPDU_START_PN_47_32_LSB                                                  0
+#define TX_MPDU_START_PN_47_32_MSB                                                  15
+#define TX_MPDU_START_PN_47_32_MASK                                                 0x000000000000ffff
+
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET                                   0x0000000000000008
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB                                      16
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB                                      27
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK                                     0x000000000fff0000
+
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET                                  0x0000000000000008
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK                                    0x0000000010000000
+
+#define TX_MPDU_START_FRAME_TYPE_OFFSET                                             0x0000000000000008
+#define TX_MPDU_START_FRAME_TYPE_LSB                                                29
+#define TX_MPDU_START_FRAME_TYPE_MSB                                                30
+#define TX_MPDU_START_FRAME_TYPE_MASK                                               0x0000000060000000
+
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET                             0x0000000000000008
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK                               0x0000000080000000
+
+#define TX_MPDU_START_IV_BYTE_0_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_0_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_0_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_0_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_1_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_1_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_1_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_1_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_2_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_2_LSB                                                 48
+#define TX_MPDU_START_IV_BYTE_2_MSB                                                 55
+#define TX_MPDU_START_IV_BYTE_2_MASK                                                0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_3_OFFSET                                              0x0000000000000008
+#define TX_MPDU_START_IV_BYTE_3_LSB                                                 56
+#define TX_MPDU_START_IV_BYTE_3_MSB                                                 63
+#define TX_MPDU_START_IV_BYTE_3_MASK                                                0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_4_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_4_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_4_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_4_MASK                                                0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_5_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_5_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_5_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_5_MASK                                                0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_6_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_6_LSB                                                 16
+#define TX_MPDU_START_IV_BYTE_6_MSB                                                 23
+#define TX_MPDU_START_IV_BYTE_6_MASK                                                0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_7_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_7_LSB                                                 24
+#define TX_MPDU_START_IV_BYTE_7_MSB                                                 31
+#define TX_MPDU_START_IV_BYTE_7_MASK                                                0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_8_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_8_LSB                                                 32
+#define TX_MPDU_START_IV_BYTE_8_MSB                                                 39
+#define TX_MPDU_START_IV_BYTE_8_MASK                                                0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_9_OFFSET                                              0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_9_LSB                                                 40
+#define TX_MPDU_START_IV_BYTE_9_MSB                                                 47
+#define TX_MPDU_START_IV_BYTE_9_MASK                                                0x0000ff0000000000
+
+#define TX_MPDU_START_IV_BYTE_10_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_10_LSB                                                48
+#define TX_MPDU_START_IV_BYTE_10_MSB                                                55
+#define TX_MPDU_START_IV_BYTE_10_MASK                                               0x00ff000000000000
+
+#define TX_MPDU_START_IV_BYTE_11_OFFSET                                             0x0000000000000010
+#define TX_MPDU_START_IV_BYTE_11_LSB                                                56
+#define TX_MPDU_START_IV_BYTE_11_MSB                                                63
+#define TX_MPDU_START_IV_BYTE_11_MASK                                               0xff00000000000000
+
+#define TX_MPDU_START_IV_BYTE_12_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_12_LSB                                                0
+#define TX_MPDU_START_IV_BYTE_12_MSB                                                7
+#define TX_MPDU_START_IV_BYTE_12_MASK                                               0x00000000000000ff
+
+#define TX_MPDU_START_IV_BYTE_13_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_13_LSB                                                8
+#define TX_MPDU_START_IV_BYTE_13_MSB                                                15
+#define TX_MPDU_START_IV_BYTE_13_MASK                                               0x000000000000ff00
+
+#define TX_MPDU_START_IV_BYTE_14_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_14_LSB                                                16
+#define TX_MPDU_START_IV_BYTE_14_MSB                                                23
+#define TX_MPDU_START_IV_BYTE_14_MASK                                               0x0000000000ff0000
+
+#define TX_MPDU_START_IV_BYTE_15_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_15_LSB                                                24
+#define TX_MPDU_START_IV_BYTE_15_MSB                                                31
+#define TX_MPDU_START_IV_BYTE_15_MASK                                               0x00000000ff000000
+
+#define TX_MPDU_START_IV_BYTE_16_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_16_LSB                                                32
+#define TX_MPDU_START_IV_BYTE_16_MSB                                                39
+#define TX_MPDU_START_IV_BYTE_16_MASK                                               0x000000ff00000000
+
+#define TX_MPDU_START_IV_BYTE_17_OFFSET                                             0x0000000000000018
+#define TX_MPDU_START_IV_BYTE_17_LSB                                                40
+#define TX_MPDU_START_IV_BYTE_17_MSB                                                47
+#define TX_MPDU_START_IV_BYTE_17_MASK                                               0x0000ff0000000000
+
+#define TX_MPDU_START_IV_LEN_OFFSET                                                 0x0000000000000018
+#define TX_MPDU_START_IV_LEN_LSB                                                    48
+#define TX_MPDU_START_IV_LEN_MSB                                                    52
+#define TX_MPDU_START_IV_LEN_MASK                                                   0x001f000000000000
+
+#define TX_MPDU_START_ICV_LEN_OFFSET                                                0x0000000000000018
+#define TX_MPDU_START_ICV_LEN_LSB                                                   53
+#define TX_MPDU_START_ICV_LEN_MSB                                                   57
+#define TX_MPDU_START_ICV_LEN_MASK                                                  0x03e0000000000000
+
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET                                     0x0000000000000018
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB                                        58
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB                                        63
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK                                       0xfc00000000000000
+
+#define TX_MPDU_START_MPDU_TYPE_OFFSET                                              0x0000000000000020
+#define TX_MPDU_START_MPDU_TYPE_LSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MASK                                                0x0000000000000001
+
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET                                0x0000000000000020
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK                                  0x0000000000000002
+
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET                                    0x0000000000000020
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB                                       2
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB                                       5
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK                                      0x000000000000003c
+
+#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET                                        0x0000000000000020
+#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB                                           6
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB                                           8
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK                                          0x00000000000001c0
+
+#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET                                          0x0000000000000020
+#define TX_MPDU_START_FRAME_SUBTYPE_LSB                                             9
+#define TX_MPDU_START_FRAME_SUBTYPE_MSB                                             12
+#define TX_MPDU_START_FRAME_SUBTYPE_MASK                                            0x0000000000001e00
+
+#define TX_MPDU_START_RESERVED_8A_OFFSET                                            0x0000000000000020
+#define TX_MPDU_START_RESERVED_8A_LSB                                               13
+#define TX_MPDU_START_RESERVED_8A_MSB                                               31
+#define TX_MPDU_START_RESERVED_8A_MASK                                              0x00000000ffffe000
+
+#define TX_MPDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000020
+#define TX_MPDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MPDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MPDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_msdu_extension.h b/hw/wcn8750/v1/tx_msdu_extension.h
new file mode 100644
index 000000000000..f8da5593497b
--- /dev/null
+++ b/hw/wcn8750/v1/tx_msdu_extension.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tso_enable                                              :  1,
+                      reserved_0a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      reserved_0b                                             :  7;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      udp_length                                              : 16;
+             uint32_t checksum_offset                                         : 14,
+                      partial_checksum_en                                     :  1,
+                      reserved_4a                                             :  1,
+                      payload_start_offset                                    : 14,
+                      reserved_4b                                             :  2;
+             uint32_t payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      wds                                                     :  1,
+                      reserved_5b                                             : 15;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_ptr_39_32                                          :  8,
+                      reserved_7a                                             :  8,
+                      buf0_len                                                : 16;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_ptr_39_32                                          :  8,
+                      reserved_9a                                             :  8,
+                      buf1_len                                                : 16;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_ptr_39_32                                          :  8,
+                      reserved_11a                                            :  8,
+                      buf2_len                                                : 16;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_ptr_39_32                                          :  8,
+                      reserved_13a                                            :  8,
+                      buf3_len                                                : 16;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_ptr_39_32                                          :  8,
+                      reserved_15a                                            :  8,
+                      buf4_len                                                : 16;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_ptr_39_32                                          :  8,
+                      reserved_17a                                            :  8,
+                      buf5_len                                                : 16;
+#else
+             uint32_t reserved_0b                                             :  7,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_0a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t udp_length                                              : 16,
+                      ip_identification                                       : 16;
+             uint32_t reserved_4b                                             :  2,
+                      payload_start_offset                                    : 14,
+                      reserved_4a                                             :  1,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 14;
+             uint32_t reserved_5b                                             : 15,
+                      wds                                                     :  1,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_len                                                : 16,
+                      reserved_7a                                             :  8,
+                      buf0_ptr_39_32                                          :  8;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_len                                                : 16,
+                      reserved_9a                                             :  8,
+                      buf1_ptr_39_32                                          :  8;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_len                                                : 16,
+                      reserved_11a                                            :  8,
+                      buf2_ptr_39_32                                          :  8;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_len                                                : 16,
+                      reserved_13a                                            :  8,
+                      buf3_ptr_39_32                                          :  8;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_len                                                : 16,
+                      reserved_15a                                            :  8,
+                      buf4_ptr_39_32                                          :  8;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_len                                                : 16,
+                      reserved_17a                                            :  8,
+                      buf5_ptr_39_32                                          :  8;
+#endif
+};
+
+#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
+#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
+
+#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
+#define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
+#define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
+#define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
+#define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
+
+#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
+#define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
+#define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
+
+#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
+#define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
+#define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
+
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
+
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
+
+#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
+#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
+
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
+
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
+
+#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
+#define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
+
+#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
+#define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
+
+#define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
+#define TX_MSDU_EXTENSION_WDS_LSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
+
+#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
+#define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET                                        0x0000001c
+#define TX_MSDU_EXTENSION_RESERVED_7A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_7A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_7A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
+#define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           8
+#define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
+#define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
+#define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
+#define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
+#define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
+#define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
+#define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
+#define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_msdu_start.h b/hw/wcn8750/v1/tx_msdu_start.h
new file mode 100644
index 000000000000..e62a76009f3a
--- /dev/null
+++ b/hw/wcn8750/v1/tx_msdu_start.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_MSDU_START_H_
+#define _TX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_START 8
+
+#define NUM_OF_QWORDS_TX_MSDU_START 4
+
+struct tx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_len                                                : 14,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      encap_type                                              :  2,
+                      epd_en                                                  :  1,
+                      da_sa_present                                           :  2,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      dummy_msdu_delimitation                                 :  1,
+                      reserved_0a                                             :  5;
+             uint32_t tso_enable                                              :  1,
+                      reserved_1a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      mesh_enable                                             :  1,
+                      reserved_1b                                             :  6;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      checksum_offset                                         : 13,
+                      partial_checksum_en                                     :  1,
+                      reserved_4                                              :  2;
+             uint32_t payload_start_offset                                    : 14,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5b                                             :  2;
+             uint32_t udp_length                                              : 16,
+                      reserved_6                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      dummy_msdu_delimitation                                 :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      da_sa_present                                           :  2,
+                      epd_en                                                  :  1,
+                      encap_type                                              :  2,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      msdu_len                                                : 14;
+             uint32_t reserved_1b                                             :  6,
+                      mesh_enable                                             :  1,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_1a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t reserved_4                                              :  2,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 13,
+                      ip_identification                                       : 16;
+             uint32_t reserved_5b                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      payload_start_offset                                    : 14;
+             uint32_t reserved_6                                              : 16,
+                      udp_length                                              : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_MSDU_START_MSDU_LEN_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_MSDU_LEN_LSB                                                  0
+#define TX_MSDU_START_MSDU_LEN_MSB                                                  13
+#define TX_MSDU_START_MSDU_LEN_MASK                                                 0x0000000000003fff
+
+#define TX_MSDU_START_FIRST_MSDU_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_FIRST_MSDU_LSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MASK                                               0x0000000000004000
+
+#define TX_MSDU_START_LAST_MSDU_OFFSET                                              0x0000000000000000
+#define TX_MSDU_START_LAST_MSDU_LSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MASK                                                0x0000000000008000
+
+#define TX_MSDU_START_ENCAP_TYPE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_ENCAP_TYPE_LSB                                                16
+#define TX_MSDU_START_ENCAP_TYPE_MSB                                                17
+#define TX_MSDU_START_ENCAP_TYPE_MASK                                               0x0000000000030000
+
+#define TX_MSDU_START_EPD_EN_OFFSET                                                 0x0000000000000000
+#define TX_MSDU_START_EPD_EN_LSB                                                    18
+#define TX_MSDU_START_EPD_EN_MSB                                                    18
+#define TX_MSDU_START_EPD_EN_MASK                                                   0x0000000000040000
+
+#define TX_MSDU_START_DA_SA_PRESENT_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_DA_SA_PRESENT_LSB                                             19
+#define TX_MSDU_START_DA_SA_PRESENT_MSB                                             20
+#define TX_MSDU_START_DA_SA_PRESENT_MASK                                            0x0000000000180000
+
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET                                       0x0000000000000000
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK                                         0x0000000000200000
+
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000000400000
+
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000000800000
+
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                0x0000000001000000
+
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x0000000000000000
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                0x0000000002000000
+
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET                                0x0000000000000000
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK                                  0x0000000004000000
+
+#define TX_MSDU_START_RESERVED_0A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_0A_LSB                                               27
+#define TX_MSDU_START_RESERVED_0A_MSB                                               31
+#define TX_MSDU_START_RESERVED_0A_MASK                                              0x00000000f8000000
+
+#define TX_MSDU_START_TSO_ENABLE_OFFSET                                             0x0000000000000000
+#define TX_MSDU_START_TSO_ENABLE_LSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MSB                                                32
+#define TX_MSDU_START_TSO_ENABLE_MASK                                               0x0000000100000000
+
+#define TX_MSDU_START_RESERVED_1A_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1A_LSB                                               33
+#define TX_MSDU_START_RESERVED_1A_MSB                                               38
+#define TX_MSDU_START_RESERVED_1A_MASK                                              0x0000007e00000000
+
+#define TX_MSDU_START_TCP_FLAG_OFFSET                                               0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_LSB                                                  39
+#define TX_MSDU_START_TCP_FLAG_MSB                                                  47
+#define TX_MSDU_START_TCP_FLAG_MASK                                                 0x0000ff8000000000
+
+#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET                                          0x0000000000000000
+#define TX_MSDU_START_TCP_FLAG_MASK_LSB                                             48
+#define TX_MSDU_START_TCP_FLAG_MASK_MSB                                             56
+#define TX_MSDU_START_TCP_FLAG_MASK_MASK                                            0x01ff000000000000
+
+#define TX_MSDU_START_MESH_ENABLE_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_MESH_ENABLE_LSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MSB                                               57
+#define TX_MSDU_START_MESH_ENABLE_MASK                                              0x0200000000000000
+
+#define TX_MSDU_START_RESERVED_1B_OFFSET                                            0x0000000000000000
+#define TX_MSDU_START_RESERVED_1B_LSB                                               58
+#define TX_MSDU_START_RESERVED_1B_MSB                                               63
+#define TX_MSDU_START_RESERVED_1B_MASK                                              0xfc00000000000000
+
+#define TX_MSDU_START_L2_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_L2_LENGTH_LSB                                                 0
+#define TX_MSDU_START_L2_LENGTH_MSB                                                 15
+#define TX_MSDU_START_L2_LENGTH_MASK                                                0x000000000000ffff
+
+#define TX_MSDU_START_IP_LENGTH_OFFSET                                              0x0000000000000008
+#define TX_MSDU_START_IP_LENGTH_LSB                                                 16
+#define TX_MSDU_START_IP_LENGTH_MSB                                                 31
+#define TX_MSDU_START_IP_LENGTH_MASK                                                0x00000000ffff0000
+
+#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET                                         0x0000000000000008
+#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB                                            32
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB                                            63
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK                                           0xffffffff00000000
+
+#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET                                      0x0000000000000010
+#define TX_MSDU_START_IP_IDENTIFICATION_LSB                                         0
+#define TX_MSDU_START_IP_IDENTIFICATION_MSB                                         15
+#define TX_MSDU_START_IP_IDENTIFICATION_MASK                                        0x000000000000ffff
+
+#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET                                        0x0000000000000010
+#define TX_MSDU_START_CHECKSUM_OFFSET_LSB                                           16
+#define TX_MSDU_START_CHECKSUM_OFFSET_MSB                                           28
+#define TX_MSDU_START_CHECKSUM_OFFSET_MASK                                          0x000000001fff0000
+
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET                                    0x0000000000000010
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK                                      0x0000000020000000
+
+#define TX_MSDU_START_RESERVED_4_OFFSET                                             0x0000000000000010
+#define TX_MSDU_START_RESERVED_4_LSB                                                30
+#define TX_MSDU_START_RESERVED_4_MSB                                                31
+#define TX_MSDU_START_RESERVED_4_MASK                                               0x00000000c0000000
+
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET                                   0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB                                      32
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB                                      45
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK                                     0x00003fff00000000
+
+#define TX_MSDU_START_RESERVED_5A_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5A_LSB                                               46
+#define TX_MSDU_START_RESERVED_5A_MSB                                               47
+#define TX_MSDU_START_RESERVED_5A_MASK                                              0x0000c00000000000
+
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET                                     0x0000000000000010
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB                                        48
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB                                        61
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK                                       0x3fff000000000000
+
+#define TX_MSDU_START_RESERVED_5B_OFFSET                                            0x0000000000000010
+#define TX_MSDU_START_RESERVED_5B_LSB                                               62
+#define TX_MSDU_START_RESERVED_5B_MSB                                               63
+#define TX_MSDU_START_RESERVED_5B_MASK                                              0xc000000000000000
+
+#define TX_MSDU_START_UDP_LENGTH_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_UDP_LENGTH_LSB                                                0
+#define TX_MSDU_START_UDP_LENGTH_MSB                                                15
+#define TX_MSDU_START_UDP_LENGTH_MASK                                               0x000000000000ffff
+
+#define TX_MSDU_START_RESERVED_6_OFFSET                                             0x0000000000000018
+#define TX_MSDU_START_RESERVED_6_LSB                                                16
+#define TX_MSDU_START_RESERVED_6_MSB                                                31
+#define TX_MSDU_START_RESERVED_6_MASK                                               0x00000000ffff0000
+
+#define TX_MSDU_START_TLV64_PADDING_OFFSET                                          0x0000000000000018
+#define TX_MSDU_START_TLV64_PADDING_LSB                                             32
+#define TX_MSDU_START_TLV64_PADDING_MSB                                             63
+#define TX_MSDU_START_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_peer_entry.h b/hw/wcn8750/v1/tx_peer_entry.h
new file mode 100644
index 000000000000..c26c7f6a3e05
--- /dev/null
+++ b/hw/wcn8750/v1/tx_peer_entry.h
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_PEER_ENTRY_H_
+#define _TX_PEER_ENTRY_H_
+
+#define NUM_OF_DWORDS_TX_PEER_ENTRY 22
+
+#define NUM_OF_QWORDS_TX_PEER_ENTRY 11
+
+struct tx_peer_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_a_47_32                                        : 16,
+                      mac_addr_b_15_0                                         : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t use_ad_b                                                :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      vlan_llc_mode                                           :  1,
+                      key_type                                                :  4,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      ignore_hard_filters                                     :  1,
+                      ignore_soft_filters                                     :  1,
+                      epd_output                                              :  1,
+                      wds                                                     :  1,
+                      insert_or_strip                                         :  1,
+                      sw_filter_id                                            : 16;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t sta_partial_aid                                         : 11,
+                      transmit_vif                                            :  4,
+                      block_this_user                                         :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      use_qos_alt_mute_mask                                   :  1,
+                      dl_ul_direction                                         :  1,
+                      use_ad_c                                                :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      multi_link_addr_ad3_valid                               :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      data_fromtods_00_ad3                                    :  2,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      reserved_12                                             :  1;
+             uint32_t insert_vlan_outer_tci                                   : 16,
+                      insert_vlan_inner_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t multi_link_addr_crypto_enable                           :  1,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      reserved_17a                                            :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t mac_addr_c_47_32                                        : 16,
+                      multi_link_addr_ad3_47_32                               : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_b_15_0                                         : 16,
+                      mac_addr_a_47_32                                        : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t sw_filter_id                                            : 16,
+                      insert_or_strip                                         :  1,
+                      wds                                                     :  1,
+                      epd_output                                              :  1,
+                      ignore_soft_filters                                     :  1,
+                      ignore_hard_filters                                     :  1,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      key_type                                                :  4,
+                      vlan_llc_mode                                           :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      use_ad_b                                                :  1;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t reserved_12                                             :  1,
+                      mgmt_fromtods_00_ad3                                    :  2,
+                      data_fromtods_00_ad3                                    :  2,
+                      multi_link_addr_ad1_trans_dis                           :  1,
+                      multi_link_addr_mgmt_crypto_en                          :  1,
+                      multi_link_addr_fromtods_00_crypto_en                   :  1,
+                      multi_link_addr_ad3_valid                               :  1,
+                      a_msdu_11s_fromtods_10_ad3                              :  2,
+                      use_ad_c                                                :  1,
+                      dl_ul_direction                                         :  1,
+                      use_qos_alt_mute_mask                                   :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      block_this_user                                         :  1,
+                      transmit_vif                                            :  4,
+                      sta_partial_aid                                         : 11;
+             uint32_t insert_vlan_inner_tci                                   : 16,
+                      insert_vlan_outer_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_17a                                            :  9,
+                      a_msdu_fromtods_11_ad4                                  :  2,
+                      a_msdu_fromtods_11_ad3                                  :  2,
+                      a_msdu_fromtods_10_ad3                                  :  2,
+                      multi_link_addr_crypto_enable                           :  1;
+             uint32_t mac_addr_c_31_0                                         : 32;
+             uint32_t multi_link_addr_ad3_47_32                               : 16,
+                      mac_addr_c_47_32                                        : 16;
+             uint32_t multi_link_addr_ad3_31_0                                : 32;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET                                       0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET                                        0x0000000000000000
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB                                           48
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB                                           63
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK                                          0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET                                       0x0000000000000008
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB                                          0
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB                                          31
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK                                         0x00000000ffffffff
+
+#define TX_PEER_ENTRY_USE_AD_B_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_USE_AD_B_LSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MSB                                                  32
+#define TX_PEER_ENTRY_USE_AD_B_MASK                                                 0x0000000100000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB                                   33
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK                                  0x0000000200000000
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET                                0x0000000000000008
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB                                   34
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK                                  0x0000000400000000
+
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET                                          0x0000000000000008
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB                                             35
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK                                            0x0000000800000000
+
+#define TX_PEER_ENTRY_KEY_TYPE_OFFSET                                               0x0000000000000008
+#define TX_PEER_ENTRY_KEY_TYPE_LSB                                                  36
+#define TX_PEER_ENTRY_KEY_TYPE_MSB                                                  39
+#define TX_PEER_ENTRY_KEY_TYPE_MASK                                                 0x000000f000000000
+
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET                                     0x0000000000000008
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB                                        40
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB                                        42
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK                                       0x0000070000000000
+
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB                                       43
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK                                      0x0000080000000000
+
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET                                    0x0000000000000008
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB                                       44
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK                                      0x0000100000000000
+
+#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET                                             0x0000000000000008
+#define TX_PEER_ENTRY_EPD_OUTPUT_LSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MSB                                                45
+#define TX_PEER_ENTRY_EPD_OUTPUT_MASK                                               0x0000200000000000
+
+#define TX_PEER_ENTRY_WDS_OFFSET                                                    0x0000000000000008
+#define TX_PEER_ENTRY_WDS_LSB                                                       46
+#define TX_PEER_ENTRY_WDS_MSB                                                       46
+#define TX_PEER_ENTRY_WDS_MASK                                                      0x0000400000000000
+
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET                                        0x0000000000000008
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB                                           47
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK                                          0x0000800000000000
+
+#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET                                           0x0000000000000008
+#define TX_PEER_ENTRY_SW_FILTER_ID_LSB                                              48
+#define TX_PEER_ENTRY_SW_FILTER_ID_MSB                                              63
+#define TX_PEER_ENTRY_SW_FILTER_ID_MASK                                             0xffff000000000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET                                      0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB                                         0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB                                         31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK                                        0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET                                     0x0000000000000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB                                        32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB                                        63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK                                       0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET                                     0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB                                        0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB                                        31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK                                       0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET                                    0x0000000000000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB                                       32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB                                       63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK                                      0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET                                   0x0000000000000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK                                     0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET                                   0x0000000000000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB                                      32
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB                                      63
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK                                     0xffffffff00000000
+
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB                                           0
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB                                           10
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK                                          0x00000000000007ff
+
+#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET                                           0x0000000000000030
+#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB                                              11
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB                                              14
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK                                             0x0000000000007800
+
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK                                          0x0000000000008000
+
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB                                           16
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB                                           17
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK                                          0x0000000000030000
+
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK                                    0x0000000000040000
+
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET                                        0x0000000000000030
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK                                          0x0000000000080000
+
+#define TX_PEER_ENTRY_USE_AD_C_OFFSET                                               0x0000000000000030
+#define TX_PEER_ENTRY_USE_AD_C_LSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MSB                                                  20
+#define TX_PEER_ENTRY_USE_AD_C_MASK                                                 0x0000000000100000
+
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET                             0x0000000000000030
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB                                21
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB                                22
+#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK                               0x0000000000600000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET                              0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB                                 23
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK                                0x0000000000800000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET                  0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB                     24
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK                    0x0000000001000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET                         0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB                            25
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK                           0x0000000002000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET                          0x0000000000000030
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB                             26
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK                            0x0000000004000000
+
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB                                      27
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB                                      28
+#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK                                     0x0000000018000000
+
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET                                   0x0000000000000030
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB                                      29
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB                                      30
+#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK                                     0x0000000060000000
+
+#define TX_PEER_ENTRY_RESERVED_12_OFFSET                                            0x0000000000000030
+#define TX_PEER_ENTRY_RESERVED_12_LSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MASK                                              0x0000000080000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB                                     32
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB                                     47
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK                                    0x0000ffff00000000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET                                  0x0000000000000030
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB                                     48
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB                                     63
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK                                    0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET                          0x0000000000000040
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB                             32
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK                            0x0000000100000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB                                    33
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB                                    34
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK                                   0x0000000600000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB                                    35
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB                                    36
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK                                   0x0000001800000000
+
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET                                 0x0000000000000040
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB                                    37
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB                                    38
+#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK                                   0x0000006000000000
+
+#define TX_PEER_ENTRY_RESERVED_17A_OFFSET                                           0x0000000000000040
+#define TX_PEER_ENTRY_RESERVED_17A_LSB                                              39
+#define TX_PEER_ENTRY_RESERVED_17A_MSB                                              47
+#define TX_PEER_ENTRY_RESERVED_17A_MASK                                             0x0000ff8000000000
+
+#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET                                             0x0000000000000040
+#define TX_PEER_ENTRY_SW_PEER_ID_LSB                                                48
+#define TX_PEER_ENTRY_SW_PEER_ID_MSB                                                63
+#define TX_PEER_ENTRY_SW_PEER_ID_MASK                                               0xffff000000000000
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET                                        0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK                                          0x00000000ffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET                                       0x0000000000000048
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB                                          32
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB                                          47
+#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK                                         0x0000ffff00000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET                              0x0000000000000048
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB                                 48
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB                                 63
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK                                0xffff000000000000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET                               0x0000000000000050
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB                                  0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB                                  31
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK                                 0x00000000ffffffff
+
+#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET                                          0x0000000000000050
+#define TX_PEER_ENTRY_TLV64_PADDING_LSB                                             32
+#define TX_PEER_ENTRY_TLV64_PADDING_MSB                                             63
+#define TX_PEER_ENTRY_TLV64_PADDING_MASK                                            0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_queue_extension.h b/hw/wcn8750/v1/tx_queue_extension.h
new file mode 100644
index 000000000000..e46bae7cff4c
--- /dev/null
+++ b/hw/wcn8750/v1/tx_queue_extension.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_QUEUE_EXTENSION_H_
+#define _TX_QUEUE_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18
+
+#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9
+
+struct tx_queue_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t frame_ctl                                               : 16,
+                      qos_ctl                                                 : 16;
+             uint32_t ampdu_flag                                              :  1,
+                      tx_notify_no_htc_override                               :  1,
+                      reserved_1a                                             :  7,
+                      checksum_tso_disable_for_frag                           :  1,
+                      key_id                                                  :  8,
+                      qos_buf_state_overwrite                                 :  1,
+                      buf_state_sta_id                                        :  1,
+                      buf_state_source                                        :  1,
+                      ht_control_overwrite_enable                             :  1,
+                      ht_control_overwrite_source                             :  4,
+                      reserved_1b                                             :  6;
+             uint32_t ul_headroom_insertion_enable                            :  1,
+                      ul_headroom_offset                                      :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      bqrp_offset                                             :  5,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqr_rsvd_9_8                                            :  2,
+                      base_pn_63_48                                           : 16;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_default_tb_ppdu                              : 32;
+             uint32_t ht_control_default_non_tb_ppdu                          : 32;
+             uint32_t ht_control_overwrite_tb_ppdu_enable                     :  1,
+                      ht_control_overwrite_non_tb_ppdu_enable                 :  1,
+                      reserved_7a                                             : 30;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t cas_control_info                                        :  8,
+                      cas_offset                                              :  5,
+                      cas_insertion_enable                                    :  1,
+                      reserved_10a                                            :  2,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      reserved_10b                                            :  5,
+                      mpdu_hdr_len_override_en                                :  1,
+                      bar_ssn_overwrite_enable                                :  1;
+             uint32_t bar_ssn_offset                                          : 12,
+                      mpdu_hdr_len_override_val                               :  9,
+                      reserved_11a                                            : 11;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t pre_padding_fcs_overwrite_offset                        : 16,
+                      icf_blackout_info_offset                                : 16;
+             uint32_t trigger_common_info_length                              :  6,
+                      cmf_overwrite_offset                                    : 14,
+                      reserved_15a                                            : 12;
+             uint32_t hdr_ctrl_prot_key_id_byte_offset                        : 14,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      ctrl_pkt_protect                                        :  1,
+                      mac_hdr_protect                                         :  1,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      reserved_16a                                            :  2;
+             uint32_t pad_byte_offset                                         : 16,
+                      pad_byte_offset_valid                                   :  1,
+                      txop_duration_overwrite_enable                          :  1,
+                      txop_duration_offset                                    : 14;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t qos_ctl                                                 : 16,
+                      frame_ctl                                               : 16;
+             uint32_t reserved_1b                                             :  6,
+                      ht_control_overwrite_source                             :  4,
+                      ht_control_overwrite_enable                             :  1,
+                      buf_state_source                                        :  1,
+                      buf_state_sta_id                                        :  1,
+                      qos_buf_state_overwrite                                 :  1,
+                      key_id                                                  :  8,
+                      checksum_tso_disable_for_frag                           :  1,
+                      reserved_1a                                             :  7,
+                      tx_notify_no_htc_override                               :  1,
+                      ampdu_flag                                              :  1;
+             uint32_t base_pn_63_48                                           : 16,
+                      bqr_rsvd_9_8                                            :  2,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqrp_offset                                             :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      ul_headroom_offset                                      :  5,
+                      ul_headroom_insertion_enable                            :  1;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_default_tb_ppdu                              : 32;
+             uint32_t ht_control_default_non_tb_ppdu                          : 32;
+             uint32_t reserved_7a                                             : 30,
+                      ht_control_overwrite_non_tb_ppdu_enable                 :  1,
+                      ht_control_overwrite_tb_ppdu_enable                     :  1;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t bar_ssn_overwrite_enable                                :  1,
+                      mpdu_hdr_len_override_en                                :  1,
+                      reserved_10b                                            :  5,
+                      pre_padding_fcs_overwrite_enable                        :  1,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      reserved_10a                                            :  2,
+                      cas_insertion_enable                                    :  1,
+                      cas_offset                                              :  5,
+                      cas_control_info                                        :  8;
+             uint32_t reserved_11a                                            : 11,
+                      mpdu_hdr_len_override_val                               :  9,
+                      bar_ssn_offset                                          : 12;
+             uint32_t fw2sw_info                                              : 32;
+             uint32_t icf_blackout_info_offset                                : 16,
+                      pre_padding_fcs_overwrite_offset                        : 16;
+             uint32_t reserved_15a                                            : 12,
+                      cmf_overwrite_offset                                    : 14,
+                      trigger_common_info_length                              :  6;
+             uint32_t reserved_16a                                            :  2,
+                      hdr_ctrl_prot_tx_peer_idx                               : 11,
+                      mac_hdr_protect                                         :  1,
+                      ctrl_pkt_protect                                        :  1,
+                      hdr_ctrl_prot_key_id_bit_offset                         :  3,
+                      hdr_ctrl_prot_key_id_byte_offset                        : 14;
+             uint32_t txop_duration_offset                                    : 14,
+                      txop_duration_overwrite_enable                          :  1,
+                      pad_byte_offset_valid                                   :  1,
+                      pad_byte_offset                                         : 16;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET                                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB                                            0
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB                                            15
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK                                           0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET                                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_CTL_LSB                                              16
+#define TX_QUEUE_EXTENSION_QOS_CTL_MSB                                              31
+#define TX_QUEUE_EXTENSION_QOS_CTL_MASK                                             0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET                                        0x0000000000000000
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB                                           32
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK                                          0x0000000100000000
+
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET                         0x0000000000000000
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB                            33
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK                           0x0000000200000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB                                          34
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB                                          40
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK                                         0x000001fc00000000
+
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET                     0x0000000000000000
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB                        41
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK                       0x0000020000000000
+
+#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET                                            0x0000000000000000
+#define TX_QUEUE_EXTENSION_KEY_ID_LSB                                               42
+#define TX_QUEUE_EXTENSION_KEY_ID_MSB                                               49
+#define TX_QUEUE_EXTENSION_KEY_ID_MASK                                              0x0003fc0000000000
+
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET                           0x0000000000000000
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB                              50
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK                             0x0004000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB                                     51
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK                                    0x0008000000000000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET                                  0x0000000000000000
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB                                     52
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK                                    0x0010000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB                          53
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK                         0x0020000000000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB                          54
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB                          57
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK                         0x03c0000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET                                       0x0000000000000000
+#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB                                          58
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB                                          63
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK                                         0xfc00000000000000
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK                        0x0000000000000001
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET                                0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB                                   1
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB                                   5
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK                                  0x000000000000003e
+
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET                             0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK                               0x0000000000000040
+
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET                                       0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB                                          7
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB                                          11
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK                                         0x0000000000000f80
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET                              0x0000000000000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB                                 12
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB                                 13
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK                                0x0000000000003000
+
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET                                      0x0000000000000008
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB                                         14
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB                                         15
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB                                        16
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB                                        31
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK                                       0x00000000ffff0000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET                                     0x0000000000000008
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB                                        32
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB                                        63
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK                                       0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET                                    0x0000000000000010
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB                                       0
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB                                       31
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK                                      0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET                        0x0000000000000010
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB                           32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB                           63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK                          0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET                    0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB                       0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB                       31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK                      0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET               0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB                  32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB                  32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK                 0x0000000100000000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET           0x0000000000000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB              33
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB              33
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK             0x0000000200000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET                                       0x0000000000000018
+#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB                                          34
+#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB                                          63
+#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK                                         0xfffffffc00000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET                                       0x0000000000000020
+#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB                                          0
+#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB                                          31
+#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK                                         0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET                         0x0000000000000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB                            32
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB                            63
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK                           0xffffffff00000000
+
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET                                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB                                     0
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB                                     7
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK                                    0x00000000000000ff
+
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET                                        0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB                                           8
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB                                           12
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK                                          0x0000000000001f00
+
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET                              0x0000000000000028
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK                                0x0000000000002000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB                                         14
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB                                         15
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK                                        0x000000000000c000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET               0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB                  16
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB                  19
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK                 0x00000000000f0000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET              0x0000000000000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB                 20
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB                 23
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK                0x0000000000f00000
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET                  0x0000000000000028
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB                     24
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK                    0x0000000001000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB                                         25
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB                                         29
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK                                        0x000000003e000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK                            0x0000000040000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET                          0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK                            0x0000000080000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET                                    0x0000000000000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB                                       32
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB                                       43
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK                                      0x00000fff00000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET                         0x0000000000000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB                            44
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB                            52
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK                           0x001ff00000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET                                      0x0000000000000028
+#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB                                         53
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK                                        0xffe0000000000000
+
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET                                        0x0000000000000030
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB                                           0
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB                                           31
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK                                          0x00000000ffffffff
+
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET                  0x0000000000000030
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB                     32
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB                     47
+#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK                    0x0000ffff00000000
+
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET                          0x0000000000000030
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB                             48
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB                             63
+#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK                            0xffff000000000000
+
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET                        0x0000000000000038
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB                           0
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB                           5
+#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK                          0x000000000000003f
+
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET                              0x0000000000000038
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB                                 6
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB                                 19
+#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK                                0x00000000000fffc0
+
+#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET                                      0x0000000000000038
+#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB                                         20
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB                                         31
+#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK                                        0x00000000fff00000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET                  0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB                     32
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB                     45
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK                    0x00003fff00000000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET                   0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB                      46
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB                      48
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK                     0x0001c00000000000
+
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET                                  0x0000000000000038
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB                                     49
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB                                     49
+#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK                                    0x0002000000000000
+
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET                                   0x0000000000000038
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB                                      50
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB                                      50
+#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK                                     0x0004000000000000
+
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET                         0x0000000000000038
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB                            51
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB                            61
+#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK                           0x3ff8000000000000
+
+#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET                                      0x0000000000000038
+#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB                                         62
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB                                         63
+#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK                                        0xc000000000000000
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET                                   0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB                                      0
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB                                      15
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK                                     0x000000000000ffff
+
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET                             0x0000000000000040
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB                                16
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB                                16
+#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK                               0x0000000000010000
+
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET                    0x0000000000000040
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB                       17
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB                       17
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK                      0x0000000000020000
+
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET                              0x0000000000000040
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB                                 18
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB                                 31
+#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK                                0x00000000fffc0000
+
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET                                     0x0000000000000040
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB                                        32
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB                                        63
+#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK                                       0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/tx_rate_stats_info.h b/hw/wcn8750/v1/tx_rate_stats_info.h
new file mode 100644
index 000000000000..ce84032dd353
--- /dev/null
+++ b/hw/wcn8750/v1/tx_rate_stats_info.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_rate_stats_info_valid                                :  1,
+                      transmit_bw                                             :  3,
+                      transmit_pkt_type                                       :  4,
+                      transmit_stbc                                           :  1,
+                      transmit_ldpc                                           :  1,
+                      transmit_sgi                                            :  2,
+                      transmit_mcs                                            :  5,
+                      unequal_modulation_info                                 :  3,
+                      ofdma_transmission                                      :  1,
+                      reserved_0a                                             :  4,
+                      tones_in_ru                                             :  4,
+                      transmit_nss                                            :  3;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#else
+             uint32_t transmit_nss                                            :  3,
+                      tones_in_ru                                             :  4,
+                      reserved_0a                                             :  4,
+                      ofdma_transmission                                      :  1,
+                      unequal_modulation_info                                 :  3,
+                      transmit_mcs                                            :  5,
+                      transmit_sgi                                            :  2,
+                      transmit_ldpc                                           :  1,
+                      transmit_stbc                                           :  1,
+                      transmit_pkt_type                                       :  4,
+                      transmit_bw                                             :  3,
+                      tx_rate_stats_info_valid                                :  1;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#endif
+};
+
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET                          0x00000000
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK                            0x00000001
+
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB                                          1
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB                                          3
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK                                         0x0000000e
+
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET                                 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB                                    4
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB                                    7
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK                                   0x000000f0
+
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK                                       0x00000100
+
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK                                       0x00000200
+
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB                                         10
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB                                         11
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK                                        0x00000c00
+
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB                                         12
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB                                         16
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK                                        0x0001f000
+
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET                           0x00000000
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB                              17
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB                              19
+#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK                             0x000e0000
+
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET                                0x00000000
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB                                   20
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK                                  0x00100000
+
+#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_RESERVED_0A_LSB                                          21
+#define TX_RATE_STATS_INFO_RESERVED_0A_MSB                                          24
+#define TX_RATE_STATS_INFO_RESERVED_0A_MASK                                         0x01e00000
+
+#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB                                          25
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB                                          28
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK                                         0x1e000000
+
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB                                         29
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB                                         31
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK                                        0xe0000000
+
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET                             0x00000004
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB                                0
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB                                31
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK                               0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h b/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
new file mode 100644
index 000000000000..220a82edf96d
--- /dev/null
+++ b/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4
+
+#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
+
+struct tx_raw_or_native_frame_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fc_to_ds_mask                                           :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_order_mask                                           :  1,
+                      duration_field_mask                                     :  1,
+                      sequence_control_mask                                   :  1,
+                      qc_tid_mask                                             :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_amsdu_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_15to8_mask                                           :  1,
+                      iv_mask                                                 :  1,
+                      fc_to_ds_setting                                        :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_more_frag_setting                                    :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  2,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_order_setting                                        :  1,
+                      qc_tid_setting                                          :  4;
+             uint32_t qc_eosp_setting                                         :  2,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_amsdu_setting                                        :  1,
+                      qc_15to8_setting                                        :  8,
+                      mlo_addr_override                                       :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      sequence_control_source                                 :  1,
+                      fragment_number                                         :  4,
+                      sequence_number                                         : 12;
+             uint32_t mlo_addr_override_for_ctrl                              :  1,
+                      reserved_2a                                             : 31;
+             uint32_t tlv64_padding                                           : 32;
+#else
+             uint32_t qc_tid_setting                                          :  4,
+                      fc_order_setting                                        :  1,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_more_data_setting                                    :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_more_frag_setting                                    :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_to_ds_setting                                        :  1,
+                      iv_mask                                                 :  1,
+                      qc_15to8_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_amsdu_mask                                           :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_tid_mask                                             :  1,
+                      sequence_control_mask                                   :  1,
+                      duration_field_mask                                     :  1,
+                      fc_order_mask                                           :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_to_ds_mask                                           :  1;
+             uint32_t sequence_number                                         : 12,
+                      fragment_number                                         :  4,
+                      sequence_control_source                                 :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      mlo_addr_override                                       :  1,
+                      qc_15to8_setting                                        :  8,
+                      qc_amsdu_setting                                        :  1,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_eosp_setting                                         :  2;
+             uint32_t reserved_2a                                             : 31,
+                      mlo_addr_override_for_ctrl                              :  1;
+             uint32_t tlv64_padding                                           : 32;
+#endif
+};
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK                             0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK                           0x0000000000000002
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK                         0x0000000000000004
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK                             0x0000000000000008
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK                           0x0000000000000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK                         0x0000000000000020
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK                        0x0000000000000040
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK                             0x0000000000000080
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET                     0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK                       0x0000000000000100
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK                     0x0000000000000200
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK                               0x0000000000000400
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET                            0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK                              0x0000000000000800
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK                        0x0000000000001000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK                             0x0000000000002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET                             0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK                               0x0000000000004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET                           0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK                             0x0000000000008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET                                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK                                   0x0000000000010000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK                          0x0000000000020000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK                        0x0000000000040000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK                      0x0000000000080000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB                           20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB                           21
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK                          0x0000000000300000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET                      0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK                        0x0000000000400000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET                    0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB                       23
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB                       24
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK                      0x0000000001800000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB                      25
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB                      26
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK                     0x0000000006000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK                          0x0000000008000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET                          0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB                             28
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB                             31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK                            0x00000000f0000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB                            32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB                            33
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK                           0x0000000300000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET                   0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB                      34
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB                      35
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK                     0x0000000c00000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB                           36
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK                          0x0000001000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET                        0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB                           37
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB                           44
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK                          0x00001fe000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET                       0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB                          45
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK                         0x0000200000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET               0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB                  46
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK                 0x0000400000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET                 0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB                    47
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK                   0x0000800000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB                            48
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB                            51
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK                           0x000f000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET                         0x0000000000000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB                            52
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB                            63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK                           0xfff0000000000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET              0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB                 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK                0x0000000000000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET                             0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB                                1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB                                31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK                               0x00000000fffffffe
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET                           0x0000000000000008
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB                              32
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB                              63
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK                             0xffffffff00000000
+
+#endif
diff --git a/hw/wcn8750/v1/txpcu_buffer_basics.h b/hw/wcn8750/v1/txpcu_buffer_basics.h
new file mode 100644
index 000000000000..4032a78ad617
--- /dev/null
+++ b/hw/wcn8750/v1/txpcu_buffer_basics.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t available_memory                                        :  8,
+                      partial_tx_data_tlv_count                               :  8,
+                      tx_data_tlv_count                                       : 16;
+#else
+             uint32_t tx_data_tlv_count                                       : 16,
+                      partial_tx_data_tlv_count                               :  8,
+                      available_memory                                        :  8;
+#endif
+};
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET                                 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB                                    0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB                                    7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK                                   0x000000ff
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET                        0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB                           8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB                           15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK                          0x0000ff00
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET                                0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB                                   16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB                                   31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK                                  0xffff0000
+
+#endif
diff --git a/hw/wcn8750/v1/txpcu_buffer_status.h b/hw/wcn8750/v1/txpcu_buffer_status.h
new file mode 100644
index 000000000000..847ca277267d
--- /dev/null
+++ b/hw/wcn8750/v1/txpcu_buffer_status.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_BUFFER_STATUS_H_
+#define _TXPCU_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
+
+struct txpcu_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t reserved                                                : 15,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved                                                : 15;
+#endif
+};
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x00000000000000ff
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x000000000000ff00
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0x00000000ffff0000
+
+#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            32
+#define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            46
+#define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff00000000
+
+#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x0000000000000000
+#define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            47
+#define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x0000800000000000
+
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x0000000000000000
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  48
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  63
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/txpcu_user_buffer_status.h b/hw/wcn8750/v1/txpcu_user_buffer_status.h
new file mode 100644
index 000000000000..f6ad0fd73721
--- /dev/null
+++ b/hw/wcn8750/v1/txpcu_user_buffer_status.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _TXPCU_USER_BUFFER_STATUS_H_
+#define _TXPCU_USER_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
+
+#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1
+
+struct txpcu_user_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t stored_word_count_user                                  : 14,
+                      reserved_1a                                             :  1,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved_1a                                             :  1,
+                      stored_word_count_user                                  : 14;
+#endif
+};
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB       0
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB       7
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK      0x00000000000000ff
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET   0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB      16
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB      31
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK     0x00000000ffff0000
+
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET                      0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB                         32
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB                         45
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK                        0x00003fff00000000
+
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET                                 0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB                                    46
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK                                   0x0000400000000000
+
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET                                    0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB                                       47
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK                                      0x0000800000000000
+
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                          0x0000000000000000
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                             48
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                             63
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                            0xffff000000000000
+
+#endif
diff --git a/hw/wcn8750/v1/u_sig_eht_su_mu_info.h b/hw/wcn8750/v1/u_sig_eht_su_mu_info.h
new file mode 100644
index 000000000000..1a08f3ab39b2
--- /dev/null
+++ b/hw/wcn8750/v1/u_sig_eht_su_mu_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  5,
+                      validate_0b                                             :  1,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1b                                             :  1,
+                      mcs_of_eht_sig                                          :  2,
+                      num_eht_sig_symbols                                     :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      reserved_1d                                             :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      validate_0b                                             :  1,
+                      disregard_0a                                            :  5,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      reserved_1d                                             :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      num_eht_sig_symbols                                     :  5,
+                      mcs_of_eht_sig                                          :  2,
+                      validate_1b                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB                                        0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK                                       0x00000007
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB                                        3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB                                        5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK                                       0x00000038
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET                                      0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK                                        0x00000040
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB                                       7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB                                       12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK                                      0x00001f80
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET                                   0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB                                      13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB                                      19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK                                     0x000fe000
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB                                       20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB                                       24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK                                      0x01f00000
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK                                       0x02000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB                                        26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB                                        31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK                                       0xfc000000
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                           0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                              0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                              1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                             0x00000003
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK                                       0x00000004
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET                   0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB                      3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB                      7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK                     0x000000f8
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK                                       0x00000100
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET                                  0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB                                     9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB                                     10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK                                    0x00000600
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB                                11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB                                15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK                               0x0000f800
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET                                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB                                                16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB                                                19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK                                               0x000f0000
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET                                            0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB                                               20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB                                               25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK                                              0x03f00000
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK                               0x04000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB                                        27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB                                        29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK                                       0x38000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET                                          0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK                                            0x40000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/u_sig_eht_tb_info.h b/hw/wcn8750/v1/u_sig_eht_tb_info.h
new file mode 100644
index 000000000000..8e417b38d233
--- /dev/null
+++ b/hw/wcn8750/v1/u_sig_eht_tb_info.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  6,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      spatial_reuse                                           :  8,
+                      disregard_1b                                            :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1c                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      disregard_0a                                            :  6,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1c                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      disregard_1b                                            :  5,
+                      spatial_reuse                                           :  8,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB                                           0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB                                           2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK                                          0x00000007
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB                                           3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB                                           5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK                                          0x00000038
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET                                         0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK                                           0x00000040
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB                                          7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB                                          12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK                                         0x00001f80
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET                                      0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB                                         13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB                                         19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK                                        0x000fe000
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB                                          20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB                                          25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK                                         0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB                                           31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK                                          0xfc000000
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                              0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                                 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                                 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                                0x00000003
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK                                          0x00000004
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET                                      0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB                                         3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB                                         10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK                                        0x000007f8
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET                                       0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB                                          11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB                                          15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK                                         0x0000f800
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET                                                0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB                                                   16
+#define U_SIG_EHT_TB_INFO_CRC_MSB                                                   19
+#define U_SIG_EHT_TB_INFO_CRC_MASK                                                  0x000f0000
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET                                               0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB                                                  20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB                                                  25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK                                                 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB                                           30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK                                          0x7c000000
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/unallocated_ru_160_info.h b/hw/wcn8750/v1/unallocated_ru_160_info.h
new file mode 100644
index 000000000000..ccd4a7bab9ad
--- /dev/null
+++ b/hw/wcn8750/v1/unallocated_ru_160_info.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t subband80_0_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_1_cc1                                         :  8;
+#else
+             uint32_t subband80_1_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_0_cc0                                         :  8;
+#endif
+};
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB                                 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB                                 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK                                0x000000ff
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB                                 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB                                 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK                                0x0000ff00
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB                                 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB                                 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK                                0x00ff0000
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB                                 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB                                 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK                                0xff000000
+
+#endif
diff --git a/hw/wcn8750/v1/uniform_descriptor_header.h b/hw/wcn8750/v1/uniform_descriptor_header.h
new file mode 100644
index 000000000000..7a2de6ccd8df
--- /dev/null
+++ b/hw/wcn8750/v1/uniform_descriptor_header.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t owner                                                   :  4,
+                      buffer_type                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      reserved_0a                                             :  4;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      buffer_type                                             :  4,
+                      owner                                                   :  4;
+#endif
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET                                      0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB                                         0
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB                                         3
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK                                        0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                                   4
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                                   7
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
+
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_a_info.h b/hw/wcn8750/v1/vht_sig_a_info.h
new file mode 100644
index 000000000000..acd20f43949e
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_a_info.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t bandwidth                                               :  2,
+                      vhta_reserved_0                                         :  1,
+                      stbc                                                    :  1,
+                      group_id                                                :  6,
+                      n_sts                                                   : 12,
+                      txop_ps_not_allowed                                     :  1,
+                      vhta_reserved_0b                                        :  1,
+                      reserved_0                                              :  8;
+             uint32_t gi_setting                                              :  2,
+                      su_mu_coding                                            :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      mcs                                                     :  4,
+                      beamformed                                              :  1,
+                      vhta_reserved_1                                         :  1,
+                      crc                                                     :  8,
+                      tail                                                    :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      vhta_reserved_0b                                        :  1,
+                      txop_ps_not_allowed                                     :  1,
+                      n_sts                                                   : 12,
+                      group_id                                                :  6,
+                      stbc                                                    :  1,
+                      vhta_reserved_0                                         :  1,
+                      bandwidth                                               :  2;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      tail                                                    :  6,
+                      crc                                                     :  8,
+                      vhta_reserved_1                                         :  1,
+                      beamformed                                              :  1,
+                      mcs                                                     :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      su_mu_coding                                            :  1,
+                      gi_setting                                              :  2;
+#endif
+};
+
+#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET                                             0x00000000
+#define VHT_SIG_A_INFO_BANDWIDTH_LSB                                                0
+#define VHT_SIG_A_INFO_BANDWIDTH_MSB                                                1
+#define VHT_SIG_A_INFO_BANDWIDTH_MASK                                               0x00000003
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK                                         0x00000004
+
+#define VHT_SIG_A_INFO_STBC_OFFSET                                                  0x00000000
+#define VHT_SIG_A_INFO_STBC_LSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MASK                                                    0x00000008
+
+#define VHT_SIG_A_INFO_GROUP_ID_OFFSET                                              0x00000000
+#define VHT_SIG_A_INFO_GROUP_ID_LSB                                                 4
+#define VHT_SIG_A_INFO_GROUP_ID_MSB                                                 9
+#define VHT_SIG_A_INFO_GROUP_ID_MASK                                                0x000003f0
+
+#define VHT_SIG_A_INFO_N_STS_OFFSET                                                 0x00000000
+#define VHT_SIG_A_INFO_N_STS_LSB                                                    10
+#define VHT_SIG_A_INFO_N_STS_MSB                                                    21
+#define VHT_SIG_A_INFO_N_STS_MASK                                                   0x003ffc00
+
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET                                   0x00000000
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK                                     0x00400000
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET                                      0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK                                        0x00800000
+
+#define VHT_SIG_A_INFO_RESERVED_0_OFFSET                                            0x00000000
+#define VHT_SIG_A_INFO_RESERVED_0_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_0_MSB                                               31
+#define VHT_SIG_A_INFO_RESERVED_0_MASK                                              0xff000000
+
+#define VHT_SIG_A_INFO_GI_SETTING_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_GI_SETTING_LSB                                               0
+#define VHT_SIG_A_INFO_GI_SETTING_MSB                                               1
+#define VHT_SIG_A_INFO_GI_SETTING_MASK                                              0x00000003
+
+#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET                                          0x00000004
+#define VHT_SIG_A_INFO_SU_MU_CODING_LSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MASK                                            0x00000004
+
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                     0x00000004
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK                                       0x00000008
+
+#define VHT_SIG_A_INFO_MCS_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_MCS_LSB                                                      4
+#define VHT_SIG_A_INFO_MCS_MSB                                                      7
+#define VHT_SIG_A_INFO_MCS_MASK                                                     0x000000f0
+
+#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_BEAMFORMED_LSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MASK                                              0x00000100
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK                                         0x00000200
+
+#define VHT_SIG_A_INFO_CRC_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_CRC_LSB                                                      10
+#define VHT_SIG_A_INFO_CRC_MSB                                                      17
+#define VHT_SIG_A_INFO_CRC_MASK                                                     0x0003fc00
+
+#define VHT_SIG_A_INFO_TAIL_OFFSET                                                  0x00000004
+#define VHT_SIG_A_INFO_TAIL_LSB                                                     18
+#define VHT_SIG_A_INFO_TAIL_MSB                                                     23
+#define VHT_SIG_A_INFO_TAIL_MASK                                                    0x00fc0000
+
+#define VHT_SIG_A_INFO_RESERVED_1_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_RESERVED_1_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_1_MSB                                               30
+#define VHT_SIG_A_INFO_RESERVED_1_MASK                                              0x7f000000
+
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                             0x00000004
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                               0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_mu160_info.h b/hw/wcn8750/v1/vht_sig_b_mu160_info.h
new file mode 100644
index 000000000000..13931c5c3556
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_mu160_info.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+             uint32_t length_copy_d                                           : 19,
+                      mcs_copy_d                                              :  4,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  3;
+             uint32_t length_copy_e                                           : 19,
+                      mcs_copy_e                                              :  4,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  3;
+             uint32_t length_copy_f                                           : 19,
+                      mcs_copy_f                                              :  4,
+                      tail_copy_f                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_g                                           : 19,
+                      mcs_copy_g                                              :  4,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t reserved_2                                              :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+             uint32_t reserved_4                                              :  3,
+                      tail_copy_d                                             :  6,
+                      mcs_copy_d                                              :  4,
+                      length_copy_d                                           : 19;
+             uint32_t reserved_5                                              :  3,
+                      tail_copy_e                                             :  6,
+                      mcs_copy_e                                              :  4,
+                      length_copy_e                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_f                                             :  6,
+                      mcs_copy_f                                              :  4,
+                      length_copy_f                                           : 19;
+             uint32_t reserved_7                                              :  3,
+                      tail_copy_g                                             :  6,
+                      mcs_copy_g                                              :  4,
+                      length_copy_g                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB                                             18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK                                            0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB                                                19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB                                                22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK                                               0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET                                      0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET                                  0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB                                     29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB                                     31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK                                    0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK                                        0xe0000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_mu20_info.h b/hw/wcn8750/v1/vht_sig_b_mu20_info.h
new file mode 100644
index 000000000000..c51ac839a757
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_mu20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 16,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      mu_user_number                                          :  3,
+                      reserved_0                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      mu_user_number                                          :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 16;
+#endif
+};
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB                                              15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK                                             0x0000ffff
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB                                                 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB                                                 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK                                                0x000f0000
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB                                      26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB                                      28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK                                     0x1c000000
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_mu40_info.h b/hw/wcn8750/v1/vht_sig_b_mu40_info.h
new file mode 100644
index 000000000000..0eb4c164cca1
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_mu40_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy                                             : 17,
+                      mcs_copy                                                :  4,
+                      tail_copy                                               :  6,
+                      reserved_1                                              :  5;
+#else
+             uint32_t mu_user_number                                          :  3,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 17;
+             uint32_t reserved_1                                              :  5,
+                      tail_copy                                               :  6,
+                      mcs_copy                                                :  4,
+                      length_copy                                             : 17;
+#endif
+};
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB                                                 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB                                                 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK                                                0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB                                          28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK                                         0x18000000
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB                                         16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK                                        0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET                                         0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB                                            17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB                                            20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK                                           0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK                                         0xf8000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_mu80_info.h b/hw/wcn8750/v1/vht_sig_b_mu80_info.h
new file mode 100644
index 000000000000..33d0f1bc08fc
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_mu80_info.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB                                                 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB                                                 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK                                                0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET                                       0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_su160_info.h b/hw/wcn8750/v1/vht_sig_b_su160_info.h
new file mode 100644
index 000000000000..7ba503724b56
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_su160_info.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+             uint32_t length_copy_d                                           : 21,
+                      vhtb_reserved_copy_d                                    :  2,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  2,
+                      rx_ndp_copy_d                                           :  1;
+             uint32_t length_copy_e                                           : 21,
+                      vhtb_reserved_copy_e                                    :  2,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  2,
+                      rx_ndp_copy_e                                           :  1;
+             uint32_t length_copy_f                                           : 21,
+                      vhtb_reserved_copy_f                                    :  2,
+                      tail_copy_f                                             :  6,
+                      reserved_6                                              :  2,
+                      rx_ndp_copy_f                                           :  1;
+             uint32_t length_copy_g                                           : 21,
+                      vhtb_reserved_copy_g                                    :  2,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  2,
+                      rx_ndp_copy_g                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+             uint32_t rx_ndp_copy_d                                           :  1,
+                      reserved_4                                              :  2,
+                      tail_copy_d                                             :  6,
+                      vhtb_reserved_copy_d                                    :  2,
+                      length_copy_d                                           : 21;
+             uint32_t rx_ndp_copy_e                                           :  1,
+                      reserved_5                                              :  2,
+                      tail_copy_e                                             :  6,
+                      vhtb_reserved_copy_e                                    :  2,
+                      length_copy_e                                           : 21;
+             uint32_t rx_ndp_copy_f                                           :  1,
+                      reserved_6                                              :  2,
+                      tail_copy_f                                             :  6,
+                      vhtb_reserved_copy_f                                    :  2,
+                      length_copy_f                                           : 21;
+             uint32_t rx_ndp_copy_g                                           :  1,
+                      reserved_7                                              :  2,
+                      tail_copy_g                                             :  6,
+                      vhtb_reserved_copy_g                                    :  2,
+                      length_copy_g                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB                                             20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK                                            0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET                                   0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB                                      21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB                                      22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK                                     0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK                                            0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET                            0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET                            0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET                            0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET                            0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET                            0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET                            0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET                                      0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET                            0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK                                     0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_su20_info.h b/hw/wcn8750/v1/vht_sig_b_su20_info.h
new file mode 100644
index 000000000000..2c7f11ba3c21
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_su20_info.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      vhtb_reserved                                           :  3,
+                      tail                                                    :  6,
+                      reserved                                                :  5,
+                      rx_ndp                                                  :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  5,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  3,
+                      length                                                  : 17;
+#endif
+};
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_su40_info.h b/hw/wcn8750/v1/vht_sig_b_su40_info.h
new file mode 100644
index 000000000000..467259003e8d
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_su40_info.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved                                                :  4,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy                                             : 19,
+                      vhtb_reserved_copy                                      :  2,
+                      tail_copy                                               :  6,
+                      reserved_copy                                           :  4,
+                      rx_ndp_copy                                             :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  4,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 19;
+             uint32_t rx_ndp_copy                                             :  1,
+                      reserved_copy                                           :  4,
+                      tail_copy                                               :  6,
+                      vhtb_reserved_copy                                      :  2,
+                      length_copy                                             : 19;
+#endif
+};
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB                                       19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB                                       20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK                                      0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB                                            27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK                                           0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB                                         18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK                                        0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET                               0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB                                  19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB                                  20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK                                 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB                                       27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB                                       30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK                                      0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK                                        0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/vht_sig_b_su80_info.h b/hw/wcn8750/v1/vht_sig_b_su80_info.h
new file mode 100644
index 000000000000..92ceeab9b476
--- /dev/null
+++ b/hw/wcn8750/v1/vht_sig_b_su80_info.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB                                              20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK                                             0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB                                       21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB                                       22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK                                      0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET                             0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET                             0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET                                       0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET                             0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK                                      0x80000000
+
+#endif
diff --git a/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h b/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
new file mode 100644
index 000000000000..e40a7e796a87
--- /dev/null
+++ b/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM2SW_COMPLETION_RING_RX_H_
+#define _WBM2SW_COMPLETION_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8
+
+struct wbm2sw_completion_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      wbm_internal_error                                      :  1;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t buffer_phys_addr_39_32                                  :  8,
+                      sw_buffer_cookie                                        : 20,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie                                        : 20,
+                      buffer_phys_addr_39_32                                  :  8;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET                                  0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB                                     3
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB                                     5
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK                                    0x00000038
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB                                   13
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB                                   14
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK                                  0x00006000
+
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK                                     0x00008000
+
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK                     0x00010000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET                          0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB                             17
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB                             18
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK                            0x00060000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET                           0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB                              19
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB                              23
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK                             0x00f80000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET                            0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB                               24
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB                               25
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK                              0x03000000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET                             0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB                                26
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB                                30
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK                               0x7c000000
+
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB          0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB          7
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK         0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET    0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK      0x00000100
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET   0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK     0x00000200
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK         0x00000400
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET        0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK          0x00000800
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK           0x00002000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB            15
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB            26
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK           0x07ff8000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET              0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                0xf0000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000010
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB      0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB      31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK  0x00000004
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB         3
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB         16
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK        0x0001fff8
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK          0x00020000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK        0x00040000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK        0x00080000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET       0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK         0x00100000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET   0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK     0x00800000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK              0x01000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK              0x02000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK          0x04000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB        27
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB        28
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK       0x18000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB        29
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB        30
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK       0x60000000
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET                      0x00000018
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB                        7
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK                       0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET                           0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB                              8
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB                              27
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK                             0x0fffff00
+
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/wbm_buffer_ring.h b/hw/wcn8750/v1/wbm_buffer_ring.h
new file mode 100644
index 000000000000..b1532e15595b
--- /dev/null
+++ b/hw/wcn8750/v1/wbm_buffer_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+#endif
+};
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                       0x00000000
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                          0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                         0xffffffff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                      0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                         0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                         7
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                        0x000000ff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                  0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                     8
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                     11
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                    0x00000f00
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                       0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                          12
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                         0xfffff000
+
+#endif
diff --git a/hw/wcn8750/v1/wbm_link_descriptor_ring.h b/hw/wcn8750/v1/wbm_link_descriptor_ring.h
new file mode 100644
index 000000000000..851807aa4c1c
--- /dev/null
+++ b/hw/wcn8750/v1/wbm_link_descriptor_ring.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          desc_addr_info;
+#else
+             struct   buffer_addr_info                                          desc_addr_info;
+#endif
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET             0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB                0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK               0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET            0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB               0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB               7
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK              0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET        0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB           8
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB           11
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK          0x00000f00
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET             0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB                12
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK               0xfffff000
+
+#endif
diff --git a/hw/wcn8750/v1/wbm_release_ring.h b/hw/wcn8750/v1/wbm_release_ring.h
new file mode 100644
index 000000000000..e86d52753912
--- /dev/null
+++ b/hw/wcn8750/v1/wbm_release_ring.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      reserved_2a                                             :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2b                                             : 22,
+                      wbm_internal_error                                      :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 28,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      reserved_2b                                             : 22,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_7a                                             : 28;
+#endif
+};
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET    0x00000000
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB       0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK      0xffffffff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET   0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB      0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB      7
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK     0x000000ff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB  8
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB  11
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET    0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB       12
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK      0xfffff000
+
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB                                  0
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB                                  2
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK                                 0x00000007
+
+#define WBM_RELEASE_RING_RESERVED_2A_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2A_LSB                                            3
+#define WBM_RELEASE_RING_RESERVED_2A_MSB                                            5
+#define WBM_RELEASE_RING_RESERVED_2A_MASK                                           0x00000038
+
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB                                    6
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB                                    8
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK                                   0x000001c0
+
+#define WBM_RELEASE_RING_RESERVED_2B_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2B_LSB                                            9
+#define WBM_RELEASE_RING_RESERVED_2B_MSB                                            30
+#define WBM_RELEASE_RING_RESERVED_2B_MASK                                           0x7ffffe00
+
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET                                  0x00000008
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK                                    0x80000000
+
+#define WBM_RELEASE_RING_RESERVED_3A_OFFSET                                         0x0000000c
+#define WBM_RELEASE_RING_RESERVED_3A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_3A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_3A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_4A_OFFSET                                         0x00000010
+#define WBM_RELEASE_RING_RESERVED_4A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_4A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_4A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_5A_OFFSET                                         0x00000014
+#define WBM_RELEASE_RING_RESERVED_5A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_5A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_5A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_6A_OFFSET                                         0x00000018
+#define WBM_RELEASE_RING_RESERVED_6A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_6A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_6A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_7A_OFFSET                                         0x0000001c
+#define WBM_RELEASE_RING_RESERVED_7A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_7A_MSB                                            27
+#define WBM_RELEASE_RING_RESERVED_7A_MASK                                           0x0fffffff
+
+#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET                                       0x0000001c
+#define WBM_RELEASE_RING_LOOPING_COUNT_LSB                                          28
+#define WBM_RELEASE_RING_LOOPING_COUNT_MSB                                          31
+#define WBM_RELEASE_RING_LOOPING_COUNT_MASK                                         0xf0000000
+
+#endif
diff --git a/hw/wcn8750/v1/wbm_release_ring_rx.h b/hw/wcn8750/v1/wbm_release_ring_rx.h
new file mode 100644
index 000000000000..a68bc8115a82
--- /dev/null
+++ b/hw/wcn8750/v1/wbm_release_ring_rx.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_RX_H_
+#define _WBM_RELEASE_RING_RX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4
+
+struct wbm_release_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 14,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t reserved_3a                                             : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      reserved_2a                                             : 14,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         19
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x000fffc0
+
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET                             0x00000008
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB                                20
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB                                31
+#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK                               0xfff00000
+
+#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET                                      0x0000000c
+#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB                                         0
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB                                         31
+#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK                                        0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/wbm_release_ring_tx.h b/hw/wcn8750/v1/wbm_release_ring_tx.h
new file mode 100644
index 000000000000..d1412153c6ae
--- /dev/null
+++ b/hw/wcn8750/v1/wbm_release_ring_tx.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef _WBM_RELEASE_RING_TX_H_
+#define _WBM_RELEASE_RING_TX_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4
+
+struct wbm_release_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             : 26;
+             uint32_t tqm_status_number                                       : 32;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t reserved_2a                                             : 26,
+                      buffer_or_desc_type                                     :  3,
+                      release_source_module                                   :  3;
+             uint32_t tqm_status_number                                       : 32;
+#endif
+};
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 3
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 5
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x00000038
+
+#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         6
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         31
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0xffffffc0
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   31
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0xffffffff
+
+#endif
diff --git a/hw/wcn8750/v1/wcss_seq_hwiobase.h b/hw/wcn8750/v1/wcss_seq_hwiobase.h
new file mode 100644
index 000000000000..4e455f399300
--- /dev/null
+++ b/hw/wcn8750/v1/wcss_seq_hwiobase.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOBASE_H
+#define WCSS_SEQ_HWIOBASE_H
+
+#define UMAC_NOC_BASE                                                 0x140000
+#define UMAC_NOC_BASE_SIZE                                          0x00004480
+#define UMAC_NOC_BASE_PHYS                                          0x00140000
+
+#define PHYA0_BASE                                                    0x300000
+#define PHYA0_BASE_SIZE                                             0x00300000
+#define PHYA0_BASE_PHYS                                             0x00300000
+
+#define PHYA1_BASE                                                    0x600000
+#define PHYA1_BASE_SIZE                                             0x00300000
+#define PHYA1_BASE_PHYS                                             0x00600000
+
+#define DMAC_BASE                                                     0x900000
+#define DMAC_BASE_SIZE                                              0x00080000
+#define DMAC_BASE_PHYS                                              0x00900000
+
+#define UMAC_BASE                                                     0xa00000
+#define UMAC_BASE_SIZE                                              0x0004d000
+#define UMAC_BASE_PHYS                                              0x00a00000
+
+#define PMAC0_BASE                                                    0xa80000
+#define PMAC0_BASE_SIZE                                             0x00040000
+#define PMAC0_BASE_PHYS                                             0x00a80000
+
+#define PMAC1_BASE                                                    0xac0000
+#define PMAC1_BASE_SIZE                                             0x00040000
+#define PMAC1_BASE_PHYS                                             0x00ac0000
+
+#define WFSS_AMCSS_BASE                                               0xb00000
+#define WFSS_AMCSS_BASE_SIZE                                        0x00040000
+#define WFSS_AMCSS_BASE_PHYS                                        0x00b00000
+
+#define CXC_BASE                                                      0xb40000
+#define CXC_BASE_SIZE                                               0x00010000
+#define CXC_BASE_PHYS                                               0x00b40000
+
+#define WFSS_PMM_BASE                                                 0xb50000
+#define WFSS_PMM_BASE_SIZE                                          0x00002401
+#define WFSS_PMM_BASE_PHYS                                          0x00b50000
+
+#define WFSS_CC_BASE                                                  0xb60000
+#define WFSS_CC_BASE_SIZE                                           0x00008000
+#define WFSS_CC_BASE_PHYS                                           0x00b60000
+
+#define WCMN_CORE_BASE                                                0xb68000
+#define WCMN_CORE_BASE_SIZE                                         0x000008a9
+#define WCMN_CORE_BASE_PHYS                                         0x00b68000
+
+#define WIFI_CFGBUS_APB_TSLV_BASE                                     0xb6b000
+#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS                              0x00b6b000
+
+#define WFSS_CFGBUS_BASE                                              0xb6c000
+#define WFSS_CFGBUS_BASE_SIZE                                       0x000000a0
+#define WFSS_CFGBUS_BASE_PHYS                                       0x00b6c000
+
+#define WIFI_CFGBUS_AHB_TSLV_BASE                                     0xb6d000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS                              0x00b6d000
+
+#define UMAC_ACMT_BASE                                                0xb6e000
+#define UMAC_ACMT_BASE_SIZE                                         0x00001000
+#define UMAC_ACMT_BASE_PHYS                                         0x00b6e000
+
+#define WCSS_CC_BASE                                                  0xb80000
+#define WCSS_CC_BASE_SIZE                                           0x00010000
+#define WCSS_CC_BASE_PHYS                                           0x00b80000
+
+#define PMM_TOP_BASE                                                  0xb90000
+#define PMM_TOP_BASE_SIZE                                           0x00010000
+#define PMM_TOP_BASE_PHYS                                           0x00b90000
+
+#define WCSS_TOP_CMN_BASE                                             0xba0000
+#define WCSS_TOP_CMN_BASE_SIZE                                      0x00004000
+#define WCSS_TOP_CMN_BASE_PHYS                                      0x00ba0000
+
+#define WCSS_CFGBUS_BASE                                              0xba4000
+#define WCSS_CFGBUS_BASE_SIZE                                       0x00008000
+#define WCSS_CFGBUS_BASE_PHYS                                       0x00ba4000
+
+#define MSIP_BASE                                                     0xbb0000
+#define MSIP_BASE_SIZE                                              0x00010000
+#define MSIP_BASE_PHYS                                              0x00bb0000
+
+#define RFA_BASE                                                      0xbc0000
+#define RFA_BASE_SIZE                                               0x00040000
+#define RFA_BASE_PHYS                                               0x00bc0000
+
+#define DBG_BASE                                                     0x1000000
+#define DBG_BASE_SIZE                                               0x00100000
+#define DBG_BASE_PHYS                                               0x01000000
+
+#define Q6SS_WLAN_BASE                                               0x1100000
+#define Q6SS_WLAN_BASE_SIZE                                         0x00100000
+#define Q6SS_WLAN_BASE_PHYS                                         0x01100000
+
+#endif
diff --git a/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h b/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
new file mode 100644
index 000000000000..60d2a0b5099f
--- /dev/null
+++ b/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
@@ -0,0 +1,13579 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOREG_UMAC_H
+#define WCSS_SEQ_HWIOREG_UMAC_H
+
+#include "seq_hwio.h"
+#include "wcss_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+#include "HALhwio.h"
+#else
+#include "msmhwio.h"
+#endif
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x)                                                     ((x) + 0x1c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_PHYS(x)                                                     ((x) + 0x1c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OFFS                                                        (0x1c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_BMSK                                    0xc0000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_SHFT                                            30
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK                                            0x38000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT                                                    27
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_BMSK                                               0x4000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_SHFT                                                      26
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_BMSK                                                 0x2000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_SHFT                                                        25
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_BMSK                                               0x1ffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_SHFT                                                       0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)                                        ((base) + 0X20 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n)                                        ((base) + 0X20 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n)                                             (0X20 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x)                                                     ((x) + 0x30)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_PHYS(x)                                                     ((x) + 0x30)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_OFFS                                                        (0x30)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ATTR                                                                     0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_BMSK                                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_SHFT                                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x)                                                      ((x) + 0x34)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_PHYS(x)                                                      ((x) + 0x34)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_OFFS                                                         (0x34)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_BMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_SHFT                                                            0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x)                                                     ((x) + 0x38)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_PHYS(x)                                                     ((x) + 0x38)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OFFS                                                        (0x38)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_BMSK                                    0xc0000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_SHFT                                            30
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK                                            0x38000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT                                                    27
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_BMSK                                               0x4000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_SHFT                                                      26
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_BMSK                                                 0x2000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_SHFT                                                        25
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_BMSK                                               0x1ffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_SHFT                                                       0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)                                        ((base) + 0X3C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n)                                        ((base) + 0X3C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n)                                             (0X3C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x)                                                     ((x) + 0x4c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_PHYS(x)                                                     ((x) + 0x4c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_OFFS                                                        (0x4c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ATTR                                                                     0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_BMSK                                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_SHFT                                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x)                                                      ((x) + 0x50)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_PHYS(x)                                                      ((x) + 0x50)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_OFFS                                                         (0x50)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_BMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_SHFT                                                            0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x)                                                     ((x) + 0x54)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_PHYS(x)                                                     ((x) + 0x54)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OFFS                                                        (0x54)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_BMSK                                    0xc0000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_SHFT                                            30
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_BMSK                                            0x38000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_SHFT                                                    27
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_BMSK                                               0x4000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_SHFT                                                      26
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_BMSK                                                 0x2000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_SHFT                                                        25
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_BMSK                                               0x1ffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_SHFT                                                       0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n)                                        ((base) + 0X58 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_PHYS(base,n)                                        ((base) + 0X58 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OFFS(n)                                             (0X58 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x)                                                     ((x) + 0x68)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_PHYS(x)                                                     ((x) + 0x68)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_OFFS                                                        (0x68)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ATTR                                                                     0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_BMSK                                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_SHFT                                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x)                                                      ((x) + 0x6c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_PHYS(x)                                                      ((x) + 0x6c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_OFFS                                                         (0x6c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_BMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_SHFT                                                            0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x)                                                     ((x) + 0x70)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_PHYS(x)                                                     ((x) + 0x70)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OFFS                                                        (0x70)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_BMSK                                    0xc0000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_SHFT                                            30
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_BMSK                                            0x38000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_SHFT                                                    27
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_BMSK                                               0x4000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_SHFT                                                      26
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_BMSK                                                 0x2000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_SHFT                                                        25
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_BMSK                                               0x1ffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_SHFT                                                       0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n)                                        ((base) + 0X74 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_PHYS(base,n)                                        ((base) + 0X74 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OFFS(n)                                             (0X74 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x)                                                     ((x) + 0x84)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_PHYS(x)                                                     ((x) + 0x84)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_OFFS                                                        (0x84)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_RMSK                                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ATTR                                                                     0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_BMSK                                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_SHFT                                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x)                                                      ((x) + 0x88)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_PHYS(x)                                                      ((x) + 0x88)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_OFFS                                                         (0x88)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_BMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_SHFT                                                            0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)                                        ((base) + 0X94 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n)                                        ((base) + 0X94 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n)                                             (0X94 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)                                        ((base) + 0XB0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n)                                        ((base) + 0XB0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n)                                             (0XB0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_RMSK                                                0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_MAXn                                                         1
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR                                                 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ATTR                                                             0x3
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT                                               0
+
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x)                                                     ((x) + 0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS                                                        (0xc8)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK                                                               0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK                                            0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT                                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x)                                        ((x) + 0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS                                           (0xcc)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK                                            0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR                                            0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK                                       0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR                                                        0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK                    0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK                       0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT                            1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK                            0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_BMSK                                       0x2000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_SHFT                                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK                                    0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT                                        12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK                                     0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT                                        11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK                                     0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT                                        10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK                                     0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT                                         9
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x)                                                ((x) + 0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS                                                   (0x100)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR                                                    0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR                                                                0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK                                 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT                                         24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK                                   0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT                                         16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK                                     0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK                                       0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT                                          0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_BMSK                         0x2
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_SHFT                           1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n)                                ((base) + 0X138 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_PHYS(base,n)                                ((base) + 0X138 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OFFS(n)                                     (0X138 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_RMSK                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_MAXn                                                 1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR                                         0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR_RMSK                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ATTR                                                     0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_BMSK                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_SHFT                                           0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n)                                ((base) + 0X14C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_PHYS(base,n)                                ((base) + 0X14C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OFFS(n)                                     (0X14C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_RMSK                                        0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_MAXn                                                 1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR                                         0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR_RMSK                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ATTR                                                     0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_BMSK                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_SHFT                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_BMSK                                       0x40000000
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_SHFT                                               30
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n)                          ((base) + 0X1B8 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_PHYS(base,n)                          ((base) + 0X1B8 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OFFS(n)                               (0X1B8 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_RMSK                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_MAXn                                           1
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR                                   0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR_RMSK                              0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ATTR                                               0x3
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_BMSK                        0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_SHFT                                 0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n)                                       ((base) + 0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n)                                            (0X2D0 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK                                                    0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn                                                       31
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR                                                0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK                                           0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR                                                            0x1
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK                                   0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT                                       0
+
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x)                                                    ((x) + 0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS                                                       (0x360)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK                                                              0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR                                                        0x00000000
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR                                                                    0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK                                                 0x2
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT                                                   1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK                                                  0x1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT                                                    0
+
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n)                                          ((base) + 0X364 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_PHYS(base,n)                                          ((base) + 0X364 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OFFS(n)                                               (0X364 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_RMSK                                                  0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_MAXn                                                           1
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR_RMSK                                              0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ATTR                                                               0x3
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_BMSK                                            0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_SHFT                                                     0
+
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n)                                           ((base) + 0X36C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_PHYS(base,n)                                           ((base) + 0X36C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OFFS(n)                                                (0X36C + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_MAXn                                                            1
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ATTR                                                                0x3
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),val)
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n))
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_BMSK                                             0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_SHFT                                                      0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x)                                                  ((x) + 0x374)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_PHYS(x)                                                  ((x) + 0x374)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_OFFS                                                     (0x374)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_RMSK                                                     0xffffff7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR                                                      0x7ffff07f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_BMSK                                   0x80000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_SHFT                                           31
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_BMSK                               0x7ffff000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_SHFT                                       12
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_BMSK                                        0x800
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_SHFT                                           11
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_BMSK                                         0x400
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_SHFT                                            10
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_BMSK                                         0x200
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_SHFT                                             9
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_BMSK                                          0x100
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_SHFT                                              8
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_BMSK                                             0x7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_SHFT                                                0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x)                                                  ((x) + 0x378)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_PHYS(x)                                                  ((x) + 0x378)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_OFFS                                                     (0x378)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR                                                      0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_BMSK                                  0xfff80000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_SHFT                                          19
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_BMSK                                     0x7ffc0
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_SHFT                                           6
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_BMSK                                        0x3f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_SHFT                                           0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x)                                                  ((x) + 0x37c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_PHYS(x)                                                  ((x) + 0x37c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_OFFS                                                     (0x37c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_RMSK                                                     0x7fffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR                                                      0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_BMSK                                   0x70000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_SHFT                                           28
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_BMSK                                       0x8000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_SHFT                                              27
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_BMSK                                  0x7e00000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_SHFT                                         21
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_BMSK                                        0x100000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_SHFT                                              20
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_BMSK                                    0xfc000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_SHFT                                         14
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_BMSK                                         0x2000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_SHFT                                             13
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_BMSK                                    0x1f80
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_SHFT                                         7
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_BMSK                                           0x40
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_SHFT                                              6
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_BMSK                                      0x3f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_SHFT                                         0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x)                                                  ((x) + 0x380)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_PHYS(x)                                                  ((x) + 0x380)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_OFFS                                                     (0x380)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_RMSK                                                      0x1ffff7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR                                                      0x00044f7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_BMSK                                        0x1fc0000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_SHFT                                               18
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_BMSK                                          0x3c000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_SHFT                                               14
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_BMSK                                      0x2000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_SHFT                                          13
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_BMSK                                           0x1000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_SHFT                                               12
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_BMSK                                      0xf00
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_BMSK                                          0x7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_SHFT                                             0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x)                                                  ((x) + 0x384)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_PHYS(x)                                                  ((x) + 0x384)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_OFFS                                                     (0x384)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR                                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_BMSK                             0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_SHFT                                      0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x)                                                  ((x) + 0x388)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_PHYS(x)                                                  ((x) + 0x388)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_OFFS                                                     (0x388)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_RMSK                                                     0x1fffff7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR                                                      0x00e04f7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_BMSK                                     0x18000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_SHFT                                             27
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_BMSK                                     0x4000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_SHFT                                            26
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_BMSK                                    0x2000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_SHFT                                           25
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_BMSK                                     0x1000000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_SHFT                                            24
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_BMSK                                              0x800000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_SHFT                                                    23
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_BMSK                                          0x400000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_SHFT                                                22
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_BMSK                                          0x200000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_SHFT                                                21
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_BMSK                               0x1f8000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_SHFT                                     15
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_BMSK                                       0x4000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_SHFT                                           14
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_BMSK                                        0x2000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_SHFT                                            13
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_BMSK                                       0x1000
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_SHFT                                           12
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_BMSK                                      0xf00
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_BMSK                                          0x7f
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_SHFT                                             0
+
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x)                                                  ((x) + 0x38c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_PHYS(x)                                                  ((x) + 0x38c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_OFFS                                                     (0x38c)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR                                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_BMSK                             0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_SHFT                                      0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x)                                                  ((x) + 0x390)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_PHYS(x)                                                  ((x) + 0x390)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_OFFS                                                     (0x390)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_RMSK                                                     0xffffff7f
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR                                                      0x7ffff07f
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_BMSK                                   0x80000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_SHFT                                           31
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_BMSK                               0x7ffff000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_SHFT                                       12
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_BMSK                                        0x800
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_SHFT                                           11
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_BMSK                                         0x400
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_SHFT                                            10
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_BMSK                                         0x200
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_SHFT                                             9
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_BMSK                                          0x100
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_SHFT                                              8
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_BMSK                                             0x7f
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_SHFT                                                0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x)                                                  ((x) + 0x394)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_PHYS(x)                                                  ((x) + 0x394)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_OFFS                                                     (0x394)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RMSK                                                     0xfffff7ff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR                                                      0x800007ff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_BMSK                                  0x80000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_SHFT                                          31
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_BMSK                                   0x40000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_SHFT                                           30
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_BMSK                                  0x3ffc0000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_SHFT                                          18
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_BMSK                                     0x3f000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_SHFT                                          12
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_BMSK                                     0x7f0
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_SHFT                                         4
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_BMSK                                   0xf
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_SHFT                                     0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x)                                                  ((x) + 0x398)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_PHYS(x)                                                  ((x) + 0x398)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_OFFS                                                     (0x398)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR                                                      0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_BMSK                         0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_SHFT                                  0
+
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x)                                                  ((x) + 0x39c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_PHYS(x)                                                  ((x) + 0x39c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_OFFS                                                     (0x39c)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR                                                      0x3fe04002
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR_RMSK                                                 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ATTR                                                                  0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_BMSK                                            0xe0000000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_SHFT                                                    29
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_BMSK                        0x1fe00000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_SHFT                                21
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_BMSK                                  0x100000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_SHFT                                        20
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_BMSK                             0x80000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_SHFT                                  19
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_BMSK                                        0x60000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_SHFT                                             17
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_BMSK                                          0x10000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_SHFT                                               16
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_BMSK                                      0x8000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_SHFT                                          15
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_BMSK                                                 0x4000
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_SHFT                                                     14
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_BMSK                                     0x3f00
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_BMSK                                       0xfc
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_SHFT                                          2
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_BMSK                                          0x2
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_SHFT                                            1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_BMSK                                           0x1
+#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_SHFT                                             0
+
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x)                                                ((x) + 0x3a0)
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_PHYS(x)                                                ((x) + 0x3a0)
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OFFS                                                   (0x3a0)
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RMSK                                                        0x3ff
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR                                                    0x0000014a
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ATTR                                                                0x3
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_BMSK                                         0x3e0
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_SHFT                                             5
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_BMSK                                          0x1f
+#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_SHFT                                             0
+
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x)                                              ((x) + 0x3a4)
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_PHYS(x)                                              ((x) + 0x3a4)
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OFFS                                                 (0x3a4)
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RMSK                                                        0xf
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR                                                  0x00000001
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR_RMSK                                             0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ATTR                                                              0x3
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_BMSK                                0xf
+#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_SHFT                                  0
+
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n)                                                      (0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn                                                                 63
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT                                                             0
+
+#define WBM_REG_REG_BASE                                                                                        (UMAC_BASE      + 0x00034000)
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x)                                                                        ((x) + 0x40)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)                                                                   ((x) + 0x130)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK                                                       0x7fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT                                                           2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK                                                    0x2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT                                                      1
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)                                                                      ((x) + 0x134)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK                                0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT                                        16
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK                                          0xffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT                                               0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)                                                   ((x) + 0x138)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)                                                   ((x) + 0x13c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK                                    0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT                                             8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK                                         0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT                                            0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)                                               ((x) + 0x140)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)                                               ((x) + 0x144)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)                                               ((x) + 0x148)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)                                               ((x) + 0x14c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)                                                          ((x) + 0x150)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)                                                            ((x) + 0x24c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                       0xffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                              8
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_BMSK                                                  0xf0000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_SHFT                                                          28
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x8000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                        27
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_BMSK                                                   0xf0000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_SHFT                                                           28
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_BMSK                                                   0xf0000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_SHFT                                                           28
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_BMSK                                               0xf0000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_SHFT                                                       28
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0x51c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xfffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)                                                             ((x) + 0x52c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                             0xf0000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                     28
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                            0x8000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                   27
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                       (0x5e8)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                   (0x5ec)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                       (0x5f0)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                   (0x5f4)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x)                                                                         ((x) + 0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS                                                                            (0x1f7c)
+#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK                                                                                  0x3f
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR                                                                             0x00000000
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK                                                                        0xffffffff
+#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR                                                                                         0x3
+#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK                                                         0x20
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT                                                            5
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK                                                         0x10
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT                                                            4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                    0x8
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                      3
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                    0x4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                      2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                             0x2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                               1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                         0x1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                           0
+
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x)                                                                  ((x) + 0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS                                                                     (0x1f80)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK                                                                     0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR                                                                      0x00000000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK                                                                 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR                                                                                  0x3
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK                                                          0xffe00000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT                                                                  21
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK                                                            0x1f0000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT                                                                  16
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK                                                                  0xf800
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT                                                                      11
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK                                                                   0x7c0
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT                                                                       6
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK                                                                    0x3e
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT                                                                       1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK                                                                       0x1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT                                                                         0
+
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                 (0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                      0x3ff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                  0x00000020
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                              0x1
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK                                                 0x200
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT                                                     9
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK                                                 0x100
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT                                                     8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                            0x80
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                               7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                            0x40
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                               6
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                     0x20
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                        5
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                  0x10
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                     4
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                     0x8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                       3
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                               0x7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                 0
+
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                   (0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK                                                                      0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn                                                                             255
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR                                                                       0x00000000
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                  0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                   0x1
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                          0
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)                                                                  ((x) + 0x3010)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)                                                               ((x) + 0x3040)
+#define REO_REG_REG_BASE                                                                                               (UMAC_BASE      + 0x00038000)
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                                                                             ((x) + 0x0)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT                                                        28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT                                                        24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT                                                        20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT                                                        16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT                                                        12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT                                                         8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT                                                         4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT                                                         0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)                                                                 ((x) + 0xc)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)                                                                 ((x) + 0x10)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS                                                          (0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR                                                           0x76043210
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK                            0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT                                    28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK                             0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT                                    24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK                              0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT                                    20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK                               0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT                                    16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK                                0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT                                    12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK                                 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT                                     8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS                                                          (0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x6666ba98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS                                                          (0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT                                    0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS                                                          (0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT                                    0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)                                                             ((x) + 0x38)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK                                       0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT                                               28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK                                        0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT                                               24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK                                         0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT                                               20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK                                          0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT                                               16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK                                           0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT                                               12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK                                            0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT                                                8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK                                             0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK                                              0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)                                                             ((x) + 0x3c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT                                              24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT                                              20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT                                              16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT                                              12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT                                               8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS                                                      (0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK                   0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT                           28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK                    0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT                           24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK                     0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT                           20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK                      0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT                           16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK                       0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT                           12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK                        0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT                            8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT                            0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS                                                      (0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR                                                       0x00000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK               0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT                       28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK                   0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT                          24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK                    0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT                          20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK                     0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT                          16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK                      0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT                          12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK                       0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT                           8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT                            0
+
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS                                                                         (0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK                                                                            0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR                                                                          0x00000000
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR                                                                                      0x3
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)            \
+                in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK                                                                   0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT                                                                         0
+
+#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)                                                                             ((x) + 0x6c)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)                                                                             ((x) + 0x70)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK                                                  0x100000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT                                                        20
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK                                                          0x80000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT                                                               19
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                                    0x40000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                         18
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                                 0x3e000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                      13
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                                    0x1f00
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                         8
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                             0xff
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                                0
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                                                                       ((x) + 0x344)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK                                                                  0xffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                                                                         8
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK                                                               0x400000
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     22
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x)                                                                       ((x) + 0x524)
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_PHYS(x)                                                                       ((x) + 0x524)
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OFFS                                                                          (0x524)
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RMSK                                                                          0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR                                                                           0x00000000
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ATTR                                                                                       0x3
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                                0
+
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x)                                                                       ((x) + 0x528)
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_PHYS(x)                                                                       ((x) + 0x528)
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OFFS                                                                          (0x528)
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RMSK                                                                            0xffffff
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR                                                                           0x00000000
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ATTR                                                                                       0x3
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_BMSK                                                                  0xffff00
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_SHFT                                                                         8
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                             0xff
+#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                                0
+
+#define HWIO_REO_R0_FW2REO_RING_ID_ADDR(x)                                                                             ((x) + 0x52c)
+#define HWIO_REO_R0_FW2REO_RING_ID_PHYS(x)                                                                             ((x) + 0x52c)
+#define HWIO_REO_R0_FW2REO_RING_ID_OFFS                                                                                (0x52c)
+#define HWIO_REO_R0_FW2REO_RING_ID_RMSK                                                                                      0xff
+#define HWIO_REO_R0_FW2REO_RING_ID_POR                                                                                 0x00000000
+#define HWIO_REO_R0_FW2REO_RING_ID_POR_RMSK                                                                            0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_ID_ATTR                                                                                             0x3
+#define HWIO_REO_R0_FW2REO_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_ID_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_BMSK                                                                           0xff
+#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_SHFT                                                                              0
+
+#define HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x)                                                                         ((x) + 0x530)
+#define HWIO_REO_R0_FW2REO_RING_STATUS_PHYS(x)                                                                         ((x) + 0x530)
+#define HWIO_REO_R0_FW2REO_RING_STATUS_OFFS                                                                            (0x530)
+#define HWIO_REO_R0_FW2REO_RING_STATUS_RMSK                                                                            0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_STATUS_POR                                                                             0x00000000
+#define HWIO_REO_R0_FW2REO_RING_STATUS_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_STATUS_ATTR                                                                                         0x1
+#define HWIO_REO_R0_FW2REO_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                            0xffff0000
+#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                                    16
+#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK                                                                0xffff
+#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT                                                                     0
+
+#define HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x)                                                                           ((x) + 0x534)
+#define HWIO_REO_R0_FW2REO_RING_MISC_PHYS(x)                                                                           ((x) + 0x534)
+#define HWIO_REO_R0_FW2REO_RING_MISC_OFFS                                                                              (0x534)
+#define HWIO_REO_R0_FW2REO_RING_MISC_RMSK                                                                                0x7fffff
+#define HWIO_REO_R0_FW2REO_RING_MISC_POR                                                                               0x00000080
+#define HWIO_REO_R0_FW2REO_RING_MISC_POR_RMSK                                                                          0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MISC_ATTR                                                                                           0x3
+#define HWIO_REO_R0_FW2REO_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_BMSK                                                               0x400000
+#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     22
+#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_BMSK                                                                  0x3fc000
+#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_SHFT                                                                        14
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_BMSK                                                                   0x3000
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_SHFT                                                                       12
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_BMSK                                                                    0xf00
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_SHFT                                                                        8
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_BMSK                                                                       0x80
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_SHFT                                                                          7
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_BMSK                                                                        0x40
+#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_SHFT                                                                           6
+#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                                  0x20
+#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                                     5
+#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                                   0x10
+#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                      4
+#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_BMSK                                                                        0x8
+#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_SHFT                                                                          3
+#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_BMSK                                                                        0x4
+#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_SHFT                                                                          2
+#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK                                                                     0x2
+#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                       1
+#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_BMSK                                                                     0x1
+#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_SHFT                                                                       0
+
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x)                                                                    ((x) + 0x540)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_PHYS(x)                                                                    ((x) + 0x540)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OFFS                                                                       (0x540)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR                                                                        0x00000000
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ATTR                                                                                    0x3
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                                  0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                                           0
+
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x)                                                                    ((x) + 0x544)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_PHYS(x)                                                                    ((x) + 0x544)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OFFS                                                                       (0x544)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_RMSK                                                                             0xff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR                                                                        0x00000000
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ATTR                                                                                    0x3
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                                        0xff
+#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                                           0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                                         ((x) + 0x554)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                                         ((x) + 0x554)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS                                                            (0x554)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR                                                             0x00000000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                                         0x3
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                                  0xffff0000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                                          16
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                                              0x8000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                                  15
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                                        0x7fff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                                             0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                                         ((x) + 0x558)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                                         ((x) + 0x558)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS                                                            (0x558)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK                                                                0xffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR                                                             0x00000000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                                         0x3
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                                  0xffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                                       0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)                                                            ((x) + 0x55c)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_PHYS(x)                                                            ((x) + 0x55c)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_OFFS                                                               (0x55c)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR                                                                0x00000000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ATTR                                                                            0x1
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                                 0xffff0000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                         16
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                                            0x8000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                                                15
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                      0x7fff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                           0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                                         ((x) + 0x560)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                                         ((x) + 0x560)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS                                                            (0x560)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                                 0x3ff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR                                                             0x00000000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                                         0x3
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                                              0x3ff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                                  0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                                        ((x) + 0x564)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                                        ((x) + 0x564)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS                                                           (0x564)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                                  0x7
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR                                                            0x00000003
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                                        0x3
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                                             0x7
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                                               0
+
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                                       ((x) + 0x568)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                                       ((x) + 0x568)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS                                                          (0x568)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK                                                            0xffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR                                                           0x00000000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                                       0x1
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                                             0xff0000
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                                   16
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                                            0xffff
+#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                                 0
+
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x)                                                                  ((x) + 0x56c)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_PHYS(x)                                                                  ((x) + 0x56c)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OFFS                                                                     (0x56c)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR                                                                      0x00000000
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ATTR                                                                                  0x3
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK                                                                0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                         0
+
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x)                                                                  ((x) + 0x570)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_PHYS(x)                                                                  ((x) + 0x570)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OFFS                                                                     (0x570)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_RMSK                                                                          0x1ff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR                                                                      0x00000000
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ATTR                                                                                  0x3
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                              0x100
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                                  8
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                      0xff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                         0
+
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x)                                                                      ((x) + 0x574)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_PHYS(x)                                                                      ((x) + 0x574)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OFFS                                                                         (0x574)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR                                                                          0x00000000
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ATTR                                                                                      0x3
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_BMSK                                                                   0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_SHFT                                                                            0
+
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)                                                                ((x) + 0x594)
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_PHYS(x)                                                                ((x) + 0x594)
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OFFS                                                                   (0x594)
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_RMSK                                                                       0xffff
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR                                                                    0x00000000
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ATTR                                                                                0x3
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                                    0xffff
+#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                         0
+
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x)                                                                         ((x) + 0x598)
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_PHYS(x)                                                                         ((x) + 0x598)
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_OFFS                                                                            (0x598)
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_RMSK                                                                            0xffff003f
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR                                                                             0x00000000
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_ATTR                                                                                         0x3
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                   0xffff0000
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                           16
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                          0x3f
+#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                             0
+
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x59c)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_PHYS(x)                                                                      ((x) + 0x59c)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OFFS                                                                         (0x59c)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR                                                                          0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ATTR                                                                                      0x3
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                               0
+
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0x5a0)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_PHYS(x)                                                                      ((x) + 0x5a0)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OFFS                                                                         (0x5a0)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RMSK                                                                           0xffffff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR                                                                          0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ATTR                                                                                      0x3
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_BMSK                                                                 0xffff00
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                            0xff
+#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                               0
+
+#define HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x)                                                                            ((x) + 0x5a4)
+#define HWIO_REO_R0_FW2REO1_RING_ID_PHYS(x)                                                                            ((x) + 0x5a4)
+#define HWIO_REO_R0_FW2REO1_RING_ID_OFFS                                                                               (0x5a4)
+#define HWIO_REO_R0_FW2REO1_RING_ID_RMSK                                                                                     0xff
+#define HWIO_REO_R0_FW2REO1_RING_ID_POR                                                                                0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_ID_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_ID_ATTR                                                                                            0x3
+#define HWIO_REO_R0_FW2REO1_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_ID_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_BMSK                                                                          0xff
+#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_SHFT                                                                             0
+
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x)                                                                        ((x) + 0x5a8)
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_PHYS(x)                                                                        ((x) + 0x5a8)
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_OFFS                                                                           (0x5a8)
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_RMSK                                                                           0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR                                                                            0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_ATTR                                                                                        0x1
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                           0xffff0000
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                                   16
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK                                                               0xffff
+#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT                                                                    0
+
+#define HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x)                                                                          ((x) + 0x5ac)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_PHYS(x)                                                                          ((x) + 0x5ac)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_OFFS                                                                             (0x5ac)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_RMSK                                                                               0x7fffff
+#define HWIO_REO_R0_FW2REO1_RING_MISC_POR                                                                              0x00000080
+#define HWIO_REO_R0_FW2REO1_RING_MISC_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MISC_ATTR                                                                                          0x3
+#define HWIO_REO_R0_FW2REO1_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x400000
+#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    22
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_BMSK                                                                 0x3fc000
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_SHFT                                                                       14
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK                                                                  0x3000
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT                                                                      12
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK                                                                   0xf00
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT                                                                       8
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK                                                                      0x80
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT                                                                         7
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_BMSK                                                                       0x40
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_SHFT                                                                          6
+#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                                 0x20
+#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                                    5
+#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                                  0x10
+#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                     4
+#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK                                                                       0x8
+#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT                                                                         3
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_BMSK                                                                       0x4
+#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_SHFT                                                                         2
+#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK                                                                    0x2
+#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                      1
+#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_BMSK                                                                    0x1
+#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_SHFT                                                                      0
+
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0x5b8)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_PHYS(x)                                                                   ((x) + 0x5b8)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OFFS                                                                      (0x5b8)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR                                                                       0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ATTR                                                                                   0x3
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0x5bc)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_PHYS(x)                                                                   ((x) + 0x5bc)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OFFS                                                                      (0x5bc)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_RMSK                                                                            0xff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR                                                                       0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ATTR                                                                                   0x3
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                                        ((x) + 0x5cc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                                        ((x) + 0x5cc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS                                                           (0x5cc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR                                                            0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                                        0x3
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                                 0xffff0000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                                         16
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                                             0x8000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                                 15
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                                       0x7fff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                                            0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                                        ((x) + 0x5d0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                                        ((x) + 0x5d0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS                                                           (0x5d0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK                                                               0xffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR                                                            0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                                        0x3
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                                 0xffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                                      0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)                                                           ((x) + 0x5d4)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x)                                                           ((x) + 0x5d4)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_OFFS                                                              (0x5d4)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_RMSK                                                              0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR                                                               0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ATTR                                                                           0x1
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                                0xffff0000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                        16
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                                           0x8000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                                               15
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                     0x7fff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                          0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                                        ((x) + 0x5d8)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                                        ((x) + 0x5d8)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS                                                           (0x5d8)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                                0x3ff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR                                                            0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                                        0x3
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                                             0x3ff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                                 0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                                       ((x) + 0x5dc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                                       ((x) + 0x5dc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS                                                          (0x5dc)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                                 0x7
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR                                                           0x00000003
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                                       0x3
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                                            0x7
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                                              0
+
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                                      ((x) + 0x5e0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                                      ((x) + 0x5e0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS                                                         (0x5e0)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK                                                           0xffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR                                                          0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                                      0x1
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                                            0xff0000
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                                  16
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                                           0xffff
+#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                                0
+
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x5e4)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_PHYS(x)                                                                 ((x) + 0x5e4)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OFFS                                                                    (0x5e4)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK                                                               0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x5e8)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_PHYS(x)                                                                 ((x) + 0x5e8)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OFFS                                                                    (0x5e8)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_RMSK                                                                         0x1ff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                             0x100
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                                 8
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                     0xff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x5ec)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_PHYS(x)                                                                     ((x) + 0x5ec)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OFFS                                                                        (0x5ec)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR                                                                         0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ATTR                                                                                     0x3
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_BMSK                                                                  0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_SHFT                                                                           0
+
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)                                                               ((x) + 0x60c)
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x)                                                               ((x) + 0x60c)
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OFFS                                                                  (0x60c)
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_RMSK                                                                      0xffff
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR                                                                   0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK                                                              0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ATTR                                                                               0x3
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                                   0xffff
+#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                        0
+
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x610)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_PHYS(x)                                                                        ((x) + 0x610)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OFFS                                                                           (0x610)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_RMSK                                                                           0xffff003f
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR                                                                            0x00000000
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ATTR                                                                                        0x3
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x7d0)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0x7d4)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                                                                            ((x) + 0x7d8)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                                                                          ((x) + 0x7e0)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0x7e4)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0x7e8)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)                                                            ((x) + 0x7f4)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x818)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x81c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x820)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x824)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x828)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x82c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)                                                                     ((x) + 0x830)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x844)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x848)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0xb90)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_PHYS(x)                                                                      ((x) + 0xb90)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OFFS                                                                         (0xb90)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR                                                                          0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ATTR                                                                                      0x3
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                               0
+
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0xb94)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_PHYS(x)                                                                      ((x) + 0xb94)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OFFS                                                                         (0xb94)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RMSK                                                                          0xfffffff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR                                                                          0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ATTR                                                                                      0x3
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                            0xff
+#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                               0
+
+#define HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x)                                                                            ((x) + 0xb98)
+#define HWIO_REO_R0_REO2SW9_RING_ID_PHYS(x)                                                                            ((x) + 0xb98)
+#define HWIO_REO_R0_REO2SW9_RING_ID_OFFS                                                                               (0xb98)
+#define HWIO_REO_R0_REO2SW9_RING_ID_RMSK                                                                                   0xffff
+#define HWIO_REO_R0_REO2SW9_RING_ID_POR                                                                                0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_ID_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_ID_ATTR                                                                                            0x3
+#define HWIO_REO_R0_REO2SW9_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_ID_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_BMSK                                                                           0xff00
+#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_SHFT                                                                                8
+#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_BMSK                                                                          0xff
+#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_SHFT                                                                             0
+
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x)                                                                        ((x) + 0xb9c)
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_PHYS(x)                                                                        ((x) + 0xb9c)
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_OFFS                                                                           (0xb9c)
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_RMSK                                                                           0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR                                                                            0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_ATTR                                                                                        0x1
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                           0xffff0000
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                                   16
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_BMSK                                                               0xffff
+#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_SHFT                                                                    0
+
+#define HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x)                                                                          ((x) + 0xba0)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_PHYS(x)                                                                          ((x) + 0xba0)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_OFFS                                                                             (0xba0)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_RMSK                                                                             0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MISC_POR                                                                              0x00000080
+#define HWIO_REO_R0_REO2SW9_RING_MISC_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MISC_ATTR                                                                                          0x3
+#define HWIO_REO_R0_REO2SW9_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                                      0x4000000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                                             26
+#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_BMSK                                                                     0x3c00000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_SHFT                                                                            22
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_BMSK                                                                 0x3fc000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_SHFT                                                                       14
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_BMSK                                                                  0x3000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_SHFT                                                                      12
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_BMSK                                                                   0xf00
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_SHFT                                                                       8
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_BMSK                                                                      0x80
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_SHFT                                                                         7
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_BMSK                                                                       0x40
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_SHFT                                                                          6
+#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                                 0x20
+#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                                    5
+#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                                  0x10
+#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                     4
+#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_BMSK                                                                       0x8
+#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_SHFT                                                                         3
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_BMSK                                                                       0x4
+#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_SHFT                                                                         2
+#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_BMSK                                                                    0x2
+#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                      1
+#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_BMSK                                                                    0x1
+#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_SHFT                                                                      0
+
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0xba4)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_PHYS(x)                                                                   ((x) + 0xba4)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OFFS                                                                      (0xba4)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR                                                                       0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ATTR                                                                                   0x3
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0xba8)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_PHYS(x)                                                                   ((x) + 0xba8)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OFFS                                                                      (0xba8)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_RMSK                                                                            0xff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR                                                                       0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ATTR                                                                                   0x3
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x)                                                            ((x) + 0xbb4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_PHYS(x)                                                            ((x) + 0xbb4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OFFS                                                               (0xbb4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR                                                                0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ATTR                                                                            0x3
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                                     0xffff0000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                                             16
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                                 0x8000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                                     15
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                                           0x7fff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                                0
+
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x)                                                           ((x) + 0xbb8)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_PHYS(x)                                                           ((x) + 0xbb8)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_OFFS                                                              (0xbb8)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_RMSK                                                              0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR                                                               0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ATTR                                                                           0x1
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                                0xffff0000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                        16
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                                        0x8000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                                            15
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                     0x7fff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                          0
+
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                                         ((x) + 0xbbc)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                                         ((x) + 0xbbc)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OFFS                                                            (0xbbc)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RMSK                                                                 0x3ff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR                                                             0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                                        0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ATTR                                                                         0x3
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                               0x3ff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                                   0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0xbd8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_PHYS(x)                                                                 ((x) + 0xbd8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OFFS                                                                    (0xbd8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_BMSK                                                               0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0xbdc)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_PHYS(x)                                                                 ((x) + 0xbdc)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OFFS                                                                    (0xbdc)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_RMSK                                                                         0x1ff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                             0x100
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                                 8
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                     0xff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0xbe0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_PHYS(x)                                                                     ((x) + 0xbe0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OFFS                                                                        (0xbe0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR                                                                         0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ATTR                                                                                     0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_BMSK                                                                  0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_SHFT                                                                           0
+
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0xbe4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_PHYS(x)                                                           ((x) + 0xbe4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OFFS                                                              (0xbe4)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_RMSK                                                              0xffcfffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR                                                               0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ATTR                                                                           0x3
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                                   0xff000000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                                           24
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                                    0x800000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                                          23
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                                  0x400000
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                                        22
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                                  0xfffff
+#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0xbe8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_PHYS(x)                                                                 ((x) + 0xbe8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OFFS                                                                    (0xbe8)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_BMSK                                                               0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0xbec)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_PHYS(x)                                                                 ((x) + 0xbec)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OFFS                                                                    (0xbec)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_RMSK                                                                         0x1ff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                                             0x100
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                                 8
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_BMSK                                                                     0xff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_SHFT                                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x)                                                                     ((x) + 0xbf0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_PHYS(x)                                                                     ((x) + 0xbf0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OFFS                                                                        (0xbf0)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR                                                                         0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ATTR                                                                                     0x3
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_BMSK                                                                  0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_SHFT                                                                           0
+
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x)                                                               ((x) + 0xc00)
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_PHYS(x)                                                               ((x) + 0xc00)
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OFFS                                                                  (0xc00)
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_RMSK                                                                      0xffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR                                                                   0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR_RMSK                                                              0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ATTR                                                                               0x3
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                                   0xffff
+#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                        0
+
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x)                                                                        ((x) + 0xc04)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_PHYS(x)                                                                        ((x) + 0xc04)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OFFS                                                                           (0xc04)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_RMSK                                                                           0xffff003f
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR                                                                            0x00000000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ATTR                                                                                        0x3
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
+
+#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0xc08)
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_BMSK                                                              0xf0000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_SHFT                                                                      28
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_BMSK                                                               0xf0000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_SHFT                                                                       28
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x8000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     27
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                          0xf0000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                                  28
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x8000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                                27
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x)                                                                 ((x) + 0x126c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_PHYS(x)                                                                 ((x) + 0x126c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OFFS                                                                    (0x126c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x)                                                                 ((x) + 0x1270)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_PHYS(x)                                                                 ((x) + 0x1270)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OFFS                                                                    (0x1270)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RMSK                                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_BMSK                                                            0xffff00
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_SHFT                                                                   8
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x)                                                                       ((x) + 0x1274)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_PHYS(x)                                                                       ((x) + 0x1274)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OFFS                                                                          (0x1274)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_RMSK                                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR                                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ATTR                                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_BMSK                                                                     0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_SHFT                                                                        0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x)                                                                   ((x) + 0x1278)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_PHYS(x)                                                                   ((x) + 0x1278)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_OFFS                                                                      (0x1278)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ATTR                                                                                   0x1
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                      0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                              16
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_BMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_SHFT                                                               0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x)                                                                     ((x) + 0x127c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_PHYS(x)                                                                     ((x) + 0x127c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OFFS                                                                        (0x127c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RMSK                                                                          0x7fffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR                                                                         0x00000080
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ATTR                                                                                     0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_BMSK                                                            0x3fc000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_SHFT                                                                  14
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_BMSK                                                             0x3000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_SHFT                                                                 12
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_BMSK                                                              0xf00
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_SHFT                                                                  8
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_BMSK                                                                 0x80
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_SHFT                                                                    7
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_BMSK                                                                  0x40
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_SHFT                                                                     6
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                            0x20
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                               5
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                             0x10
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                4
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_BMSK                                                                  0x8
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_SHFT                                                                    3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_BMSK                                                                  0x4
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_SHFT                                                                    2
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_BMSK                                                               0x2
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                 1
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_BMSK                                                               0x1
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_SHFT                                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x)                                                              ((x) + 0x1288)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_PHYS(x)                                                              ((x) + 0x1288)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OFFS                                                                 (0x1288)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                            0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x)                                                              ((x) + 0x128c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_PHYS(x)                                                              ((x) + 0x128c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OFFS                                                                 (0x128c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_RMSK                                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                                  0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                                   ((x) + 0x129c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                                   ((x) + 0x129c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OFFS                                                      (0x129c)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                            0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                                    16
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                                        0x8000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                            15
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                                  0x7fff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                                       0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                                   ((x) + 0x12a0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                                   ((x) + 0x12a0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OFFS                                                      (0x12a0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_RMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                            0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x)                                                      ((x) + 0x12a4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_PHYS(x)                                                      ((x) + 0x12a4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_OFFS                                                         (0x12a4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ATTR                                                                      0x1
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                           0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                   16
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                                      0x8000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                                          15
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                0x7fff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                                   ((x) + 0x12a8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                                   ((x) + 0x12a8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OFFS                                                      (0x12a8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                           0x3ff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                                        0x3ff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                            0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                                  ((x) + 0x12ac)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                                  ((x) + 0x12ac)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OFFS                                                     (0x12ac)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                            0x7
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR                                                      0x00000003
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                                  0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                                       0x7
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                                         0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                                 ((x) + 0x12b0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                                 ((x) + 0x12b0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_OFFS                                                    (0x12b0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_RMSK                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                                 0x1
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                                       0xff0000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                             16
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                                      0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                           0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x)                                                            ((x) + 0x12b4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_PHYS(x)                                                            ((x) + 0x12b4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OFFS                                                               (0x12b4)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x)                                                            ((x) + 0x12b8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_PHYS(x)                                                            ((x) + 0x12b8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OFFS                                                               (0x12b8)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x)                                                                ((x) + 0x12bc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_PHYS(x)                                                                ((x) + 0x12bc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OFFS                                                                   (0x12bc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x)                                                          ((x) + 0x12dc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_PHYS(x)                                                          ((x) + 0x12dc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OFFS                                                             (0x12dc)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_RMSK                                                                 0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR                                                              0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ATTR                                                                          0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x)                                                                   ((x) + 0x12e0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_PHYS(x)                                                                   ((x) + 0x12e0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OFFS                                                                      (0x12e0)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_RMSK                                                                      0xffff003f
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ATTR                                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                             0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                     16
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                    0x3f
+#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                       0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x)                                                                 ((x) + 0x12e4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_PHYS(x)                                                                 ((x) + 0x12e4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OFFS                                                                    (0x12e4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x)                                                                 ((x) + 0x12e8)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_PHYS(x)                                                                 ((x) + 0x12e8)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OFFS                                                                    (0x12e8)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RMSK                                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_BMSK                                                            0xffff00
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_SHFT                                                                   8
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x)                                                                       ((x) + 0x12ec)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_PHYS(x)                                                                       ((x) + 0x12ec)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OFFS                                                                          (0x12ec)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_RMSK                                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR                                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ATTR                                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_BMSK                                                                     0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_SHFT                                                                        0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x)                                                                   ((x) + 0x12f0)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_PHYS(x)                                                                   ((x) + 0x12f0)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_OFFS                                                                      (0x12f0)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ATTR                                                                                   0x1
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                      0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                              16
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_BMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_SHFT                                                               0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x)                                                                     ((x) + 0x12f4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_PHYS(x)                                                                     ((x) + 0x12f4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OFFS                                                                        (0x12f4)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RMSK                                                                          0x7fffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR                                                                         0x00000080
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ATTR                                                                                     0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_BMSK                                                            0x3fc000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_SHFT                                                                  14
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_BMSK                                                             0x3000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_SHFT                                                                 12
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_BMSK                                                              0xf00
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_SHFT                                                                  8
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_BMSK                                                                 0x80
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_SHFT                                                                    7
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_BMSK                                                                  0x40
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_SHFT                                                                     6
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                            0x20
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                               5
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                             0x10
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                4
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_BMSK                                                                  0x8
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_SHFT                                                                    3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_BMSK                                                                  0x4
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_SHFT                                                                    2
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_BMSK                                                               0x2
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                 1
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_BMSK                                                               0x1
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_SHFT                                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x)                                                              ((x) + 0x1300)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_PHYS(x)                                                              ((x) + 0x1300)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OFFS                                                                 (0x1300)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                            0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x)                                                              ((x) + 0x1304)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_PHYS(x)                                                              ((x) + 0x1304)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OFFS                                                                 (0x1304)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_RMSK                                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                                  0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                                   ((x) + 0x1314)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                                   ((x) + 0x1314)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OFFS                                                      (0x1314)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                            0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                                    16
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                                        0x8000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                            15
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                                  0x7fff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                                       0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                                   ((x) + 0x1318)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                                   ((x) + 0x1318)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OFFS                                                      (0x1318)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_RMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                            0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x)                                                      ((x) + 0x131c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_PHYS(x)                                                      ((x) + 0x131c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_OFFS                                                         (0x131c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ATTR                                                                      0x1
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                           0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                   16
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                                      0x8000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                                          15
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                0x7fff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                                   ((x) + 0x1320)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                                   ((x) + 0x1320)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OFFS                                                      (0x1320)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                           0x3ff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                                        0x3ff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                            0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                                  ((x) + 0x1324)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                                  ((x) + 0x1324)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OFFS                                                     (0x1324)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                            0x7
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR                                                      0x00000003
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                                  0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                                       0x7
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                                         0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                                 ((x) + 0x1328)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                                 ((x) + 0x1328)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_OFFS                                                    (0x1328)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_RMSK                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                                 0x1
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                                       0xff0000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                             16
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                                      0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                           0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x)                                                            ((x) + 0x132c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_PHYS(x)                                                            ((x) + 0x132c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OFFS                                                               (0x132c)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x)                                                            ((x) + 0x1330)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_PHYS(x)                                                            ((x) + 0x1330)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OFFS                                                               (0x1330)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x)                                                                ((x) + 0x1334)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_PHYS(x)                                                                ((x) + 0x1334)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OFFS                                                                   (0x1334)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x)                                                          ((x) + 0x1354)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_PHYS(x)                                                          ((x) + 0x1354)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OFFS                                                             (0x1354)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_RMSK                                                                 0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR                                                              0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ATTR                                                                          0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x)                                                                   ((x) + 0x1358)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_PHYS(x)                                                                   ((x) + 0x1358)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OFFS                                                                      (0x1358)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_RMSK                                                                      0xffff003f
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ATTR                                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                             0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                     16
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                    0x3f
+#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                       0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x)                                                                 ((x) + 0x135c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_PHYS(x)                                                                 ((x) + 0x135c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OFFS                                                                    (0x135c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x)                                                                 ((x) + 0x1360)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_PHYS(x)                                                                 ((x) + 0x1360)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OFFS                                                                    (0x1360)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RMSK                                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_BMSK                                                            0xffff00
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_SHFT                                                                   8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x)                                                                       ((x) + 0x1364)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_PHYS(x)                                                                       ((x) + 0x1364)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OFFS                                                                          (0x1364)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RMSK                                                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR                                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ATTR                                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_BMSK                                                                      0xff00
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_SHFT                                                                           8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_BMSK                                                                     0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_SHFT                                                                        0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x)                                                                   ((x) + 0x1368)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_PHYS(x)                                                                   ((x) + 0x1368)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_OFFS                                                                      (0x1368)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ATTR                                                                                   0x1
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                      0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                              16
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_BMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_SHFT                                                               0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x)                                                                     ((x) + 0x136c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_PHYS(x)                                                                     ((x) + 0x136c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OFFS                                                                        (0x136c)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR                                                                         0x00000080
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ATTR                                                                                     0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_BMSK                                                         0xf0000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_SHFT                                                                 28
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x8000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_SHFT                                                               27
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                                 0x4000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                                        26
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_BMSK                                                                0x3c00000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_SHFT                                                                       22
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_BMSK                                                            0x3fc000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_SHFT                                                                  14
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_BMSK                                                             0x3000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_SHFT                                                                 12
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_BMSK                                                              0xf00
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_SHFT                                                                  8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_BMSK                                                                 0x80
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_SHFT                                                                    7
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_BMSK                                                                  0x40
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_SHFT                                                                     6
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                            0x20
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                               5
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                             0x10
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                4
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_BMSK                                                                  0x8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_SHFT                                                                    3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_BMSK                                                                  0x4
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_SHFT                                                                    2
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_BMSK                                                               0x2
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                 1
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_BMSK                                                               0x1
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_SHFT                                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x)                                                              ((x) + 0x1370)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_PHYS(x)                                                              ((x) + 0x1370)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OFFS                                                                 (0x1370)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                            0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x)                                                              ((x) + 0x1374)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_PHYS(x)                                                              ((x) + 0x1374)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OFFS                                                                 (0x1374)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_RMSK                                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                                  0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x)                                                       ((x) + 0x1380)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_PHYS(x)                                                       ((x) + 0x1380)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OFFS                                                          (0x1380)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ATTR                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                                0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                                        16
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                            0x8000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                                15
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                                      0x7fff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                           0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x)                                                      ((x) + 0x1384)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_PHYS(x)                                                      ((x) + 0x1384)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_OFFS                                                         (0x1384)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ATTR                                                                      0x1
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                           0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                   16
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                                   0x8000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                                       15
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                0x7fff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                     0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                                    ((x) + 0x1388)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                                    ((x) + 0x1388)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OFFS                                                       (0x1388)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RMSK                                                            0x3ff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR                                                        0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ATTR                                                                    0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                          0x3ff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                              0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x)                                                            ((x) + 0x13a4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_PHYS(x)                                                            ((x) + 0x13a4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OFFS                                                               (0x13a4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x)                                                            ((x) + 0x13a8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_PHYS(x)                                                            ((x) + 0x13a8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OFFS                                                               (0x13a8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x)                                                                ((x) + 0x13ac)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_PHYS(x)                                                                ((x) + 0x13ac)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OFFS                                                                   (0x13ac)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                      ((x) + 0x13b0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_PHYS(x)                                                      ((x) + 0x13b0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OFFS                                                         (0x13b0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_RMSK                                                         0xffc0ffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ATTR                                                                      0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                              0xff000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                                      24
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                               0x800000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                                     23
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                             0x400000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                                   22
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x)                                                            ((x) + 0x13b4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_PHYS(x)                                                            ((x) + 0x13b4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OFFS                                                               (0x13b4)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x)                                                            ((x) + 0x13b8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_PHYS(x)                                                            ((x) + 0x13b8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OFFS                                                               (0x13b8)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x)                                                                ((x) + 0x13bc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_PHYS(x)                                                                ((x) + 0x13bc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OFFS                                                                   (0x13bc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x)                                                          ((x) + 0x13cc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_PHYS(x)                                                          ((x) + 0x13cc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OFFS                                                             (0x13cc)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_RMSK                                                                 0xffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR                                                              0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ATTR                                                                          0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x)                                                                   ((x) + 0x13d0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_PHYS(x)                                                                   ((x) + 0x13d0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OFFS                                                                      (0x13d0)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_RMSK                                                                      0xffff003f
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ATTR                                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                             0xffff0000
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                     16
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                    0x3f
+#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                       0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x)                                                                 ((x) + 0x13d4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_PHYS(x)                                                                 ((x) + 0x13d4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OFFS                                                                    (0x13d4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x)                                                                 ((x) + 0x13d8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_PHYS(x)                                                                 ((x) + 0x13d8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OFFS                                                                    (0x13d8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RMSK                                                                      0xffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR                                                                     0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ATTR                                                                                 0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_BMSK                                                            0xffff00
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_SHFT                                                                   8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                          0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x)                                                                       ((x) + 0x13dc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_PHYS(x)                                                                       ((x) + 0x13dc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OFFS                                                                          (0x13dc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RMSK                                                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR                                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ATTR                                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_BMSK                                                                      0xff00
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_SHFT                                                                           8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_BMSK                                                                     0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_SHFT                                                                        0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x)                                                                   ((x) + 0x13e0)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_PHYS(x)                                                                   ((x) + 0x13e0)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_OFFS                                                                      (0x13e0)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_RMSK                                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ATTR                                                                                   0x1
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                                      0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                              16
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_BMSK                                                          0xffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_SHFT                                                               0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x)                                                                     ((x) + 0x13e4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_PHYS(x)                                                                     ((x) + 0x13e4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OFFS                                                                        (0x13e4)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR                                                                         0x00000080
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ATTR                                                                                     0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_BMSK                                                         0xf0000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_SHFT                                                                 28
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x8000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_SHFT                                                               27
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                                 0x4000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                                        26
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_BMSK                                                                0x3c00000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_SHFT                                                                       22
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_BMSK                                                            0x3fc000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_SHFT                                                                  14
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_BMSK                                                             0x3000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_SHFT                                                                 12
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_BMSK                                                              0xf00
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_SHFT                                                                  8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_BMSK                                                                 0x80
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_SHFT                                                                    7
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_BMSK                                                                  0x40
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_SHFT                                                                     6
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                            0x20
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                               5
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                             0x10
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                                4
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_BMSK                                                                  0x8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_SHFT                                                                    3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_BMSK                                                                  0x4
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_SHFT                                                                    2
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_BMSK                                                               0x2
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_SHFT                                                                 1
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_BMSK                                                               0x1
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_SHFT                                                                 0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x)                                                              ((x) + 0x13e8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_PHYS(x)                                                              ((x) + 0x13e8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OFFS                                                                 (0x13e8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_RMSK                                                                 0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                            0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x)                                                              ((x) + 0x13ec)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_PHYS(x)                                                              ((x) + 0x13ec)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OFFS                                                                 (0x13ec)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_RMSK                                                                       0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR                                                                  0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR_RMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ATTR                                                                              0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                                  0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x)                                                       ((x) + 0x13f8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_PHYS(x)                                                       ((x) + 0x13f8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OFFS                                                          (0x13f8)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR                                                           0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ATTR                                                                       0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                                0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                                        16
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                            0x8000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                                15
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                                      0x7fff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                           0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x)                                                      ((x) + 0x13fc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_PHYS(x)                                                      ((x) + 0x13fc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_OFFS                                                         (0x13fc)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ATTR                                                                      0x1
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                           0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                                   16
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                                   0x8000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                                       15
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                                0x7fff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                                     0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                                    ((x) + 0x1400)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                                    ((x) + 0x1400)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OFFS                                                       (0x1400)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RMSK                                                            0x3ff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR                                                        0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ATTR                                                                    0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                          0x3ff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                              0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x)                                                            ((x) + 0x141c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_PHYS(x)                                                            ((x) + 0x141c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OFFS                                                               (0x141c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x)                                                            ((x) + 0x1420)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_PHYS(x)                                                            ((x) + 0x1420)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OFFS                                                               (0x1420)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x)                                                                ((x) + 0x1424)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_PHYS(x)                                                                ((x) + 0x1424)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OFFS                                                                   (0x1424)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                      ((x) + 0x1428)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_PHYS(x)                                                      ((x) + 0x1428)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OFFS                                                         (0x1428)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_RMSK                                                         0xffc0ffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR                                                          0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ATTR                                                                      0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                              0xff000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                                      24
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                               0x800000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                                     23
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                             0x400000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                                   22
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x)                                                            ((x) + 0x142c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_PHYS(x)                                                            ((x) + 0x142c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OFFS                                                               (0x142c)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_BMSK                                                          0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x)                                                            ((x) + 0x1430)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_PHYS(x)                                                            ((x) + 0x1430)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OFFS                                                               (0x1430)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_RMSK                                                                    0x1ff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR                                                                0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR_RMSK                                                           0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ATTR                                                                            0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                                        0x100
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                            8
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_BMSK                                                                0xff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_SHFT                                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x)                                                                ((x) + 0x1434)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_PHYS(x)                                                                ((x) + 0x1434)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OFFS                                                                   (0x1434)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR                                                                    0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR_RMSK                                                               0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ATTR                                                                                0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_BMSK                                                             0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_SHFT                                                                      0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x)                                                          ((x) + 0x1444)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_PHYS(x)                                                          ((x) + 0x1444)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OFFS                                                             (0x1444)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_RMSK                                                                 0xffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR                                                              0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR_RMSK                                                         0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ATTR                                                                          0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                              0xffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                                   0
+
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x)                                                                   ((x) + 0x1448)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_PHYS(x)                                                                   ((x) + 0x1448)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OFFS                                                                      (0x1448)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_RMSK                                                                      0xffff003f
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR                                                                       0x00000000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR_RMSK                                                                  0xffffffff
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ATTR                                                                                   0x3
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x), m)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),v)
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x))
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                             0xffff0000
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                     16
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                    0x3f
+#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                       0
+
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_BMSK                                          0x10000
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_SHFT                                               16
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_BMSK                                           0x8000
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_SHFT                                               15
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_BMSK                                                0x4000
+#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_SHFT                                                    14
+#define HWIO_REO_R0_MISC_CFG_ADDR(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_PHYS(x)                                                                                   ((x) + 0x1458)
+#define HWIO_REO_R0_MISC_CFG_OFFS                                                                                      (0x1458)
+#define HWIO_REO_R0_MISC_CFG_RMSK                                                                                             0x1
+#define HWIO_REO_R0_MISC_CFG_POR                                                                                       0x00000000
+#define HWIO_REO_R0_MISC_CFG_POR_RMSK                                                                                  0xffffffff
+#define HWIO_REO_R0_MISC_CFG_ATTR                                                                                                   0x3
+#define HWIO_REO_R0_MISC_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x))
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK                                                                        0x1
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT                                                                          0
+
+#define HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x)                                                                              ((x) + 0x145c)
+#define HWIO_REO_R0_MISC_CFG_BN_1_PHYS(x)                                                                              ((x) + 0x145c)
+#define HWIO_REO_R0_MISC_CFG_BN_1_OFFS                                                                                 (0x145c)
+#define HWIO_REO_R0_MISC_CFG_BN_1_RMSK                                                                                    0x3cfff
+#define HWIO_REO_R0_MISC_CFG_BN_1_POR                                                                                  0x00000801
+#define HWIO_REO_R0_MISC_CFG_BN_1_POR_RMSK                                                                             0xffffffff
+#define HWIO_REO_R0_MISC_CFG_BN_1_ATTR                                                                                              0x3
+#define HWIO_REO_R0_MISC_CFG_BN_1_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_BN_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_BN_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_BN_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_BN_1_IN(x))
+#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_BMSK                                                        0x3c000
+#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_SHFT                                                             14
+#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_BMSK                                                     0x800
+#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_SHFT                                                        11
+#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_BMSK                                             0x400
+#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_SHFT                                                10
+#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_BMSK                                                                           0x3c0
+#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_SHFT                                                                               6
+#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_BMSK                                                                      0x20
+#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_SHFT                                                                         5
+#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_BMSK                                                          0x10
+#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_SHFT                                                             4
+#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_BMSK                                                             0x8
+#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_SHFT                                                               3
+#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_BMSK                                               0x4
+#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_SHFT                                                 2
+#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_BMSK                                                            0x2
+#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_SHFT                                                              1
+#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_BMSK                                                                            0x1
+#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_SHFT                                                                              0
+
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x)                                                                        ((x) + 0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS                                                                           (0x1460)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK                                                                                0x7ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR                                                                            0x000003ff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK                                                                       0xffffffff
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR                                                                                        0x3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)            \
+                in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x))
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v)
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x))
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK                                                                         0x400
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT                                                                            10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK                                                                        0x200
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT                                                                            9
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK                                                                        0x100
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT                                                                            8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK                                                                         0x80
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT                                                                            7
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK                                                                         0x40
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT                                                                            6
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK                                                                         0x20
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT                                                                            5
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK                                                                         0x10
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT                                                                            4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK                                                                          0x8
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT                                                                            3
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK                                                                          0x4
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT                                                                            2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK                                                                          0x2
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT                                                                            1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK                                                                          0x1
+#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT                                                                            0
+
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x)                                                                         ((x) + 0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS                                                                            (0x1464)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK                                                                                 0x1ff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR                                                                             0x0000002d
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR                                                                                         0x3
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK                                                             0x1fe
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT                                                                 1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK                                                                           0x1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT                                                                             0
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                                                                       ((x) + 0x1468)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                                                                       ((x) + 0x146c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                                                                       ((x) + 0x1470)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                                                                       ((x) + 0x1474)
+#define HWIO_REO_R0_MISC_CTL_ADDR(x)                                                                                   ((x) + 0x14dc)
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK                                                                         0x1e00000
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT                                                                                21
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK                                                                     0x1e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT                                                                           17
+#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_BMSK                                                              0x30000000
+#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_SHFT                                                                      28
+#define HWIO_REO_R0_MISC_CTL_5_ADDR(x)                                                                                 ((x) + 0x14ec)
+#define HWIO_REO_R0_MISC_CTL_5_PHYS(x)                                                                                 ((x) + 0x14ec)
+#define HWIO_REO_R0_MISC_CTL_5_OFFS                                                                                    (0x14ec)
+#define HWIO_REO_R0_MISC_CTL_5_RMSK                                                                                          0x3f
+#define HWIO_REO_R0_MISC_CTL_5_POR                                                                                     0x00000000
+#define HWIO_REO_R0_MISC_CTL_5_POR_RMSK                                                                                0xffffffff
+#define HWIO_REO_R0_MISC_CTL_5_ATTR                                                                                                 0x3
+#define HWIO_REO_R0_MISC_CTL_5_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x))
+#define HWIO_REO_R0_MISC_CTL_5_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CTL_5_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CTL_5_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CTL_5_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_5_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_5_IN(x))
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_BMSK                                                                       0x20
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_SHFT                                                                          5
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_BMSK                                                                       0x10
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_SHFT                                                                          4
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_BMSK                                                                0xc
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_SHFT                                                                  2
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_BMSK                                                                0x3
+#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_SHFT                                                                  0
+
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x)                                                         ((x) + 0x16b4)
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x)                                                         ((x) + 0x16b4)
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OFFS                                                            (0x16b4)
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_RMSK                                                            0x1fff000f
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR                                                             0x00000000
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR_RMSK                                                        0xffffffff
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ATTR                                                                         0x3
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x)            \
+                in_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x))
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), m)
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),v)
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x))
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK                                          0x1fff0000
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT                                                  16
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK                                           0xf
+#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT                                             0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                          (0x16c0)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                      (0x16c4)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                          (0x16c8)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                      (0x16cc)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_CREDIT_ADDR(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_PHYS(x)                                                                                     ((x) + 0x16d0)
+#define HWIO_REO_R0_CREDIT_OFFS                                                                                        (0x16d0)
+#define HWIO_REO_R0_CREDIT_RMSK                                                                                        0xffffffff
+#define HWIO_REO_R0_CREDIT_POR                                                                                         0x00000000
+#define HWIO_REO_R0_CREDIT_POR_RMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_ATTR                                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_ADDR(x))
+#define HWIO_REO_R0_CREDIT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x))
+#define HWIO_REO_R0_CREDIT_VAL_BMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_VAL_SHFT                                                                                             0
+
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x)                                                                     ((x) + 0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS                                                                        (0x16d4)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK                                                                               0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR                                                                         0x00000002
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK                                                                        0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT                                                                          0
+
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x)                                                                      ((x) + 0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS                                                                         (0x16d8)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR                                                                          0x00000000
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR                                                                                      0x1
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x))
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT                                                                              0
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_BMSK                                                 0x2000000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_SHFT                                                        25
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_BMSK                                                     0x1000000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_SHFT                                                            24
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_BMSK                                                    0x800000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_SHFT                                                          23
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_BMSK                                                      0x400000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_SHFT                                                            22
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_BMSK                                                      0x200000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_SHFT                                                            21
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_BMSK                                                0x100000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_SHFT                                                      20
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_BMSK                                                 0x80000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_SHFT                                                      19
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_BMSK                                           0x40000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_SHFT                                                18
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_BMSK                                                0x20000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_SHFT                                                     17
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_BMSK                                              0x10000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_SHFT                                                   16
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK                                                 0x2000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT                                                     13
+#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x)                                                                                ((x) + 0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_OFFS                                                                                   (0x1704)
+#define HWIO_REO_R0_LPM_FW_CTRL_RMSK                                                                                          0x7
+#define HWIO_REO_R0_LPM_FW_CTRL_POR                                                                                    0x00000000
+#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK                                                                               0xffffffff
+#define HWIO_REO_R0_LPM_FW_CTRL_ATTR                                                                                                0x3
+#define HWIO_REO_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                           0x4
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                             2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                           0x2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                             1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                                0x1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                                  0
+
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x)                                                                      ((x) + 0x1708)
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_PHYS(x)                                                                      ((x) + 0x1708)
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OFFS                                                                         (0x1708)
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_RMSK                                                                             0xffff
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR                                                                          0x00000000
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ATTR                                                                                      0x3
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x))
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x))
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_BMSK                                                        0x8000
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_SHFT                                                            15
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_BMSK                                                           0x4000
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_SHFT                                                               14
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_BMSK                                                           0x2000
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_SHFT                                                               13
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_BMSK                                                           0x1000
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_SHFT                                                               12
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_BMSK                                                            0x800
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_SHFT                                                               11
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_BMSK                                                            0x400
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_SHFT                                                               10
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_BMSK                                                             0x200
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_SHFT                                                                 9
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_BMSK                                                             0x100
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_SHFT                                                                 8
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_BMSK                                                              0x80
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_SHFT                                                                 7
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_BMSK                                                              0x40
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_SHFT                                                                 6
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_BMSK                                                              0x20
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_SHFT                                                                 5
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_BMSK                                                              0x10
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_SHFT                                                                 4
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_BMSK                                                               0x8
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_SHFT                                                                 3
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_BMSK                                                               0x4
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_SHFT                                                                 2
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_BMSK                                                               0x2
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_SHFT                                                                 1
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_BMSK                                                               0x1
+#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_SHFT                                                                 0
+
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x)                                                                    ((x) + 0x170c)
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_PHYS(x)                                                                    ((x) + 0x170c)
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OFFS                                                                       (0x170c)
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_RMSK                                                                           0xffff
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR                                                                        0x00000000
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR_RMSK                                                                   0xffffffff
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ATTR                                                                                    0x3
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x))
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x))
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_BMSK                                                      0x8000
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_SHFT                                                          15
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_BMSK                                                         0x4000
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_SHFT                                                             14
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_BMSK                                                         0x2000
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_SHFT                                                             13
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_BMSK                                                         0x1000
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_SHFT                                                             12
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_BMSK                                                          0x800
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_SHFT                                                             11
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_BMSK                                                          0x400
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_SHFT                                                             10
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_BMSK                                                           0x200
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_SHFT                                                               9
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_BMSK                                                           0x100
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_SHFT                                                               8
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_BMSK                                                            0x80
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_SHFT                                                               7
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_BMSK                                                            0x40
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_SHFT                                                               6
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_BMSK                                                            0x20
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_SHFT                                                               5
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_BMSK                                                            0x10
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_SHFT                                                               4
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_BMSK                                                             0x8
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_SHFT                                                               3
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_BMSK                                                             0x4
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_SHFT                                                               2
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_BMSK                                                             0x2
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_SHFT                                                               1
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_BMSK                                                             0x1
+#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_SHFT                                                               0
+
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x)                                                             ((x) + 0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS                                                                (0x1710)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK                                             0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT                                                     28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK                                              0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT                                                     24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK                                               0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT                                                     20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK                                                0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT                                                     16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK                                                 0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT                                                     12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK                                                  0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT                                                      8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT                                                      0
+
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x)                                                             ((x) + 0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS                                                                (0x1714)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK                                                                0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR                                                                 0x00060000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK                                                            0xffffffff
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR                                                                             0x3
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x))
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK                                            0xf0000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT                                                    28
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK                                             0xf000000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT                                                    24
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK                                              0xf00000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT                                                    20
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK                                               0xf0000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT                                                    16
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK                                                0xf000
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT                                                    12
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK                                                 0xf00
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT                                                     8
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK                                                   0xf0
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT                                                      4
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK                                                    0xf
+#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT                                                      0
+
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x)                                                               ((x) + 0x2008)
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_PHYS(x)                                                               ((x) + 0x2008)
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_OFFS                                                                  (0x2008)
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_RMSK                                                                  0xffffffff
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR                                                                   0x00000000
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR_RMSK                                                              0xffffffff
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ATTR                                                                               0x1
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_IN(x)            \
+                in_dword(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x))
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_BMSK                                                        0xffffffff
+#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_SHFT                                                                 0
+
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x)                                                                          ((x) + 0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS                                                                             (0x20c4)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK                                                                                   0x3f
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR                                                                              0x00000000
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR                                                                                          0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x))
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK                                                         0x20
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT                                                            5
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK                                                                   0x10
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT                                                                      4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK                                                                0x8
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT                                                                  3
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK                                                            0x4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT                                                              2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK                                                                      0x2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT                                                                        1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK                                                                  0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT                                                                    0
+
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x)                                                      ((x) + 0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS                                                         (0x20c8)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK                                                         0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR                                                          0x00000000
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR                                                                      0x3
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)            \
+                in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK                                                   0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT                                                            0
+
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                                     ((x) + 0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                        (0x20d0)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                              0x7f
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR                                                                         0x00000000
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                                     0x1
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                                   0x40
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                      6
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                                   0x20
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                      5
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                         0x10
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                            4
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                            0x8
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                              3
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                      0x7
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                        0
+
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                                     ((base) + 0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                          (0X20D4 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK                                                                             0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn                                                                                    255
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR                                                                              0x00000000
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR                                                                                          0x1
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                        0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                                 0
+
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                                                                             ((x) + 0x3028)
+#define HWIO_REO_R2_FW2REO_RING_HP_ADDR(x)                                                                             ((x) + 0x3048)
+#define HWIO_REO_R2_FW2REO_RING_HP_PHYS(x)                                                                             ((x) + 0x3048)
+#define HWIO_REO_R2_FW2REO_RING_HP_OFFS                                                                                (0x3048)
+#define HWIO_REO_R2_FW2REO_RING_HP_RMSK                                                                                    0xffff
+#define HWIO_REO_R2_FW2REO_RING_HP_POR                                                                                 0x00000000
+#define HWIO_REO_R2_FW2REO_RING_HP_POR_RMSK                                                                            0xffffffff
+#define HWIO_REO_R2_FW2REO_RING_HP_ATTR                                                                                             0x3
+#define HWIO_REO_R2_FW2REO_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x))
+#define HWIO_REO_R2_FW2REO_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_FW2REO_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_FW2REO_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_HP_IN(x))
+#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_BMSK                                                                           0xffff
+#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_SHFT                                                                                0
+
+#define HWIO_REO_R2_FW2REO_RING_TP_ADDR(x)                                                                             ((x) + 0x304c)
+#define HWIO_REO_R2_FW2REO_RING_TP_PHYS(x)                                                                             ((x) + 0x304c)
+#define HWIO_REO_R2_FW2REO_RING_TP_OFFS                                                                                (0x304c)
+#define HWIO_REO_R2_FW2REO_RING_TP_RMSK                                                                                    0xffff
+#define HWIO_REO_R2_FW2REO_RING_TP_POR                                                                                 0x00000000
+#define HWIO_REO_R2_FW2REO_RING_TP_POR_RMSK                                                                            0xffffffff
+#define HWIO_REO_R2_FW2REO_RING_TP_ATTR                                                                                             0x3
+#define HWIO_REO_R2_FW2REO_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x))
+#define HWIO_REO_R2_FW2REO_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_FW2REO_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_FW2REO_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_TP_IN(x))
+#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_BMSK                                                                           0xffff
+#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_SHFT                                                                                0
+
+#define HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x)                                                                            ((x) + 0x3050)
+#define HWIO_REO_R2_FW2REO1_RING_HP_PHYS(x)                                                                            ((x) + 0x3050)
+#define HWIO_REO_R2_FW2REO1_RING_HP_OFFS                                                                               (0x3050)
+#define HWIO_REO_R2_FW2REO1_RING_HP_RMSK                                                                                   0xffff
+#define HWIO_REO_R2_FW2REO1_RING_HP_POR                                                                                0x00000000
+#define HWIO_REO_R2_FW2REO1_RING_HP_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R2_FW2REO1_RING_HP_ATTR                                                                                            0x3
+#define HWIO_REO_R2_FW2REO1_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x))
+#define HWIO_REO_R2_FW2REO1_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_FW2REO1_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_FW2REO1_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_HP_IN(x))
+#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_BMSK                                                                          0xffff
+#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_SHFT                                                                               0
+
+#define HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x)                                                                            ((x) + 0x3054)
+#define HWIO_REO_R2_FW2REO1_RING_TP_PHYS(x)                                                                            ((x) + 0x3054)
+#define HWIO_REO_R2_FW2REO1_RING_TP_OFFS                                                                               (0x3054)
+#define HWIO_REO_R2_FW2REO1_RING_TP_RMSK                                                                                   0xffff
+#define HWIO_REO_R2_FW2REO1_RING_TP_POR                                                                                0x00000000
+#define HWIO_REO_R2_FW2REO1_RING_TP_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R2_FW2REO1_RING_TP_ATTR                                                                                            0x3
+#define HWIO_REO_R2_FW2REO1_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x))
+#define HWIO_REO_R2_FW2REO1_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_FW2REO1_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_FW2REO1_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_TP_IN(x))
+#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_BMSK                                                                          0xffff
+#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_SHFT                                                                               0
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                                                                            ((x) + 0x3070)
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                                                                            ((x) + 0x3074)
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                                                                            ((x) + 0x3078)
+#define HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x)                                                                            ((x) + 0x30b0)
+#define HWIO_REO_R2_REO2SW9_RING_HP_PHYS(x)                                                                            ((x) + 0x30b0)
+#define HWIO_REO_R2_REO2SW9_RING_HP_OFFS                                                                               (0x30b0)
+#define HWIO_REO_R2_REO2SW9_RING_HP_RMSK                                                                                  0xfffff
+#define HWIO_REO_R2_REO2SW9_RING_HP_POR                                                                                0x00000000
+#define HWIO_REO_R2_REO2SW9_RING_HP_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R2_REO2SW9_RING_HP_ATTR                                                                                            0x3
+#define HWIO_REO_R2_REO2SW9_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x))
+#define HWIO_REO_R2_REO2SW9_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_REO2SW9_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_REO2SW9_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_HP_IN(x))
+#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_BMSK                                                                         0xfffff
+#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_SHFT                                                                               0
+
+#define HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x)                                                                            ((x) + 0x30b4)
+#define HWIO_REO_R2_REO2SW9_RING_TP_PHYS(x)                                                                            ((x) + 0x30b4)
+#define HWIO_REO_R2_REO2SW9_RING_TP_OFFS                                                                               (0x30b4)
+#define HWIO_REO_R2_REO2SW9_RING_TP_RMSK                                                                                  0xfffff
+#define HWIO_REO_R2_REO2SW9_RING_TP_POR                                                                                0x00000000
+#define HWIO_REO_R2_REO2SW9_RING_TP_POR_RMSK                                                                           0xffffffff
+#define HWIO_REO_R2_REO2SW9_RING_TP_ATTR                                                                                            0x3
+#define HWIO_REO_R2_REO2SW9_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x))
+#define HWIO_REO_R2_REO2SW9_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_REO2SW9_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_REO2SW9_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_TP_IN(x))
+#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_BMSK                                                                         0xfffff
+#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_SHFT                                                                               0
+#define TQM_REG_REG_BASE	(UMAC_BASE      + 0x0003c000)
+#define TQM_REG_REG_BASE_SIZE	0x4000
+
+#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)                                                                            ((x) + 0x30b8)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x)                                                                       ((x) + 0x3118)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_PHYS(x)                                                                       ((x) + 0x3118)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OFFS                                                                          (0x3118)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x)                                                                       ((x) + 0x311c)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_PHYS(x)                                                                       ((x) + 0x311c)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OFFS                                                                          (0x311c)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x)                                                                       ((x) + 0x3120)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_PHYS(x)                                                                       ((x) + 0x3120)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OFFS                                                                          (0x3120)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x)                                                                       ((x) + 0x3124)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_PHYS(x)                                                                       ((x) + 0x3124)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OFFS                                                                          (0x3124)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x)                                                                       ((x) + 0x3128)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_PHYS(x)                                                                       ((x) + 0x3128)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OFFS                                                                          (0x3128)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x)                                                                       ((x) + 0x312c)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_PHYS(x)                                                                       ((x) + 0x312c)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OFFS                                                                          (0x312c)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x)                                                                       ((x) + 0x3130)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_PHYS(x)                                                                       ((x) + 0x3130)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OFFS                                                                          (0x3130)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_SHFT                                                                          0
+
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x)                                                                       ((x) + 0x3134)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_PHYS(x)                                                                       ((x) + 0x3134)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OFFS                                                                          (0x3134)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_RMSK                                                                              0xffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR                                                                           0x00000000
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR_RMSK                                                                      0xffffffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ATTR                                                                                       0x3
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x)            \
+                in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x))
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x), m)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),v)
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x))
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_BMSK                                                                     0xffff
+#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_SHFT                                                                          0
+
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK                                                             0x80
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT                                                                7
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK                                                    0x40
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT                                                       6
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK                                                     0x20
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT                                                        5
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK                                                           0x10
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT                                                              4
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK                                                          0x8
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT                                                            3
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                    0xf0000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                            28
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_BMSK                                                     0xf0000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_SHFT                                                             28
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x8000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT                                                           27
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_BMSK                                                    0xf0000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_SHFT                                                            28
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0x64c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_PHYS(x)                                                         ((x) + 0x64c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OFFS                                                            (0x64c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR                                                             0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ATTR                                                                         0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                         0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                  0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x)                                                         ((x) + 0x650)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_PHYS(x)                                                         ((x) + 0x650)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OFFS                                                            (0x650)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RMSK                                                              0xffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR                                                             0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ATTR                                                                         0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                    0xffff00
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                               0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                  0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x)                                                               ((x) + 0x654)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_PHYS(x)                                                               ((x) + 0x654)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OFFS                                                                  (0x654)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RMSK                                                                      0xffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR                                                                   0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ATTR                                                                               0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_BMSK                                                              0xff00
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_SHFT                                                                   8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                             0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                                0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x)                                                           ((x) + 0x658)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_PHYS(x)                                                           ((x) + 0x658)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_OFFS                                                              (0x658)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR                                                               0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ATTR                                                                           0x1
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                              0xffff0000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                      16
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                  0xffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                       0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x)                                                             ((x) + 0x65c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_PHYS(x)                                                             ((x) + 0x65c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OFFS                                                                (0x65c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RMSK                                                                0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR                                                                 0x00000080
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ATTR                                                                             0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                 0xf0000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                         28
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                0x8000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                       27
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                         0x4000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                                26
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                        0x3c00000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                               22
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                    0x3fc000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                          14
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                     0x3000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                         12
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                      0xf00
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                         0x80
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                            7
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                          0x40
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                             6
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                    0x20
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                       5
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                     0x10
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                        4
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                          0x8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                            3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                          0x4
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                            2
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                       0x2
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                         1
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                      ((x) + 0x660)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                      ((x) + 0x660)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OFFS                                                         (0x660)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                    0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                      ((x) + 0x664)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                      ((x) + 0x664)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OFFS                                                         (0x664)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK                                                               0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                          0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                               ((x) + 0x670)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                               ((x) + 0x670)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                  (0x670)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                   0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                               0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                        0xffff0000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                                16
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                    0x8000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                        15
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                              0x7fff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                   0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                              ((x) + 0x674)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                              ((x) + 0x674)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                 (0x674)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                              0x1
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                   0xffff0000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                           16
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                           0x8000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                               15
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                        0x7fff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                             0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                            ((x) + 0x678)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                            ((x) + 0x678)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                               (0x678)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                    0x3ff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                                0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                           0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                            0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                  0x3ff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                      0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                    ((x) + 0x694)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                    ((x) + 0x694)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                       (0x694)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                    ((x) + 0x698)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                    ((x) + 0x698)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                       (0x698)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                            0x1ff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                0x100
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                    8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                        0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)                                                        ((x) + 0x69c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_PHYS(x)                                                        ((x) + 0x69c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OFFS                                                           (0x69c)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                              0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                              ((x) + 0x6a0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                              ((x) + 0x6a0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                 (0x6a0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                 0xffc0ffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                      0xff000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                              24
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                       0x800000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                             23
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                     0x400000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                           22
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                      0xffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                    ((x) + 0x6a4)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                    ((x) + 0x6a4)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                       (0x6a4)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                    ((x) + 0x6a8)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                    ((x) + 0x6a8)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                       (0x6a8)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                            0x1ff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                                0x100
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                    8
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                        0xff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x)                                                        ((x) + 0x6ac)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_PHYS(x)                                                        ((x) + 0x6ac)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OFFS                                                           (0x6ac)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                              0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                  ((x) + 0x6bc)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                  ((x) + 0x6bc)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                     (0x6bc)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                         0xffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                      0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                  0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                      0xffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                           0
+
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x)                                                           ((x) + 0x6c0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_PHYS(x)                                                           ((x) + 0x6c0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OFFS                                                              (0x6c0)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_RMSK                                                              0xffff003f
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR                                                               0x00000000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ATTR                                                                           0x3
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                     0xffff0000
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                             16
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                            0x3f
+#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                               0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x6c4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_PHYS(x)                                                      ((x) + 0x6c4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OFFS                                                         (0x6c4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                      0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                               0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0x6c8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_PHYS(x)                                                      ((x) + 0x6c8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OFFS                                                         (0x6c8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RMSK                                                           0xffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                 0xffff00
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x)                                                            ((x) + 0x6cc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_PHYS(x)                                                            ((x) + 0x6cc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OFFS                                                               (0x6cc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RMSK                                                                   0xffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR                                                                0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_BMSK                                                           0xff00
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_SHFT                                                                8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x)                                                        ((x) + 0x6d0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_PHYS(x)                                                        ((x) + 0x6d0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_OFFS                                                           (0x6d0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ATTR                                                                        0x1
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                           0xffff0000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                   16
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                               0xffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                    0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x)                                                          ((x) + 0x6d4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_PHYS(x)                                                          ((x) + 0x6d4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OFFS                                                             (0x6d4)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR                                                              0x00000080
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                              0xf0000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                      28
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                             0x8000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                    27
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                      0x4000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                             26
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                     0x3c00000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                            22
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                 0x3fc000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                       14
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                  0x3000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                      12
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                   0xf00
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                       8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                      0x80
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                         7
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                       0x40
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                          6
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                       0x4
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                         2
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                   ((x) + 0x6d8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                   ((x) + 0x6d8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OFFS                                                      (0x6d8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                 0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                   ((x) + 0x6dc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                   ((x) + 0x6dc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OFFS                                                      (0x6dc)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_RMSK                                                            0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                       0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                            ((x) + 0x6e8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                            ((x) + 0x6e8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                               (0x6e8)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                               0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                           0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                            0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                     0xffff0000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                             16
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                 0x8000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                     15
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                           0x7fff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                           ((x) + 0x6ec)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                           ((x) + 0x6ec)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                              (0x6ec)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                           0x1
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                0xffff0000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                        16
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                        0x8000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                            15
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                     0x7fff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                          0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                         ((x) + 0x6f0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                         ((x) + 0x6f0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                            (0x6f0)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                 0x3ff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                             0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                         0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                               0x3ff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                   0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0x70c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                 ((x) + 0x70c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                    (0x70c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0x710)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                 ((x) + 0x710)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                    (0x710)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                         0x1ff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0x714)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_PHYS(x)                                                     ((x) + 0x714)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OFFS                                                        (0x714)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                           ((x) + 0x718)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                           ((x) + 0x718)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                              (0x718)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                              0xffc0ffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                   0xff000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                           24
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                    0x800000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                          23
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                  0x400000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                        22
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                   0xffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                 ((x) + 0x71c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                 ((x) + 0x71c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                    (0x71c)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                 ((x) + 0x720)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                 ((x) + 0x720)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                    (0x720)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                         0x1ff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                             0x100
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                 8
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x)                                                     ((x) + 0x724)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_PHYS(x)                                                     ((x) + 0x724)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OFFS                                                        (0x724)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                           0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                               ((x) + 0x734)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                               ((x) + 0x734)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                  (0x734)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                      0xffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                   0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                               0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                   0xffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                        0
+
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x)                                                        ((x) + 0x738)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_PHYS(x)                                                        ((x) + 0x738)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OFFS                                                           (0x738)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_RMSK                                                           0xffff003f
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                  0xffff0000
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                          16
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                         0x3f
+#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS                                                           (0x73c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x740)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x740)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OFFS                                                           (0x740)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x744)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x744)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OFFS                                                                 (0x744)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x748)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x748)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_OFFS                                                             (0x748)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x74c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x74c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OFFS                                                               (0x74c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x750)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x750)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x750)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x754)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x754)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x754)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x760)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x760)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x760)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x764)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x764)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x764)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x768)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x768)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x768)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x784)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x784)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x784)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x788)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x788)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x788)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x78c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x78c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x78c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x790)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x790)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x790)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x794)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x794)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x794)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x798)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x798)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x798)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x79c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x79c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x79c)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0x7ac)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0x7ac)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0x7ac)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0x7b0)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0x7b0)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OFFS                                                             (0x7b0)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS                                                           (0x7b4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x7b8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x7b8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OFFS                                                           (0x7b8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x7bc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x7bc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OFFS                                                                 (0x7bc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x7c0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x7c0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_OFFS                                                             (0x7c0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x7c4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x7c4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OFFS                                                               (0x7c4)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x7c8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x7c8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x7c8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x7cc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x7cc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x7cc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x7d8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x7d8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x7d8)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x7dc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x7dc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x7dc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x7e0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x7e0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x7e0)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x7fc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x7fc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x7fc)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x800)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x800)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x800)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x804)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x804)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x804)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x808)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x808)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x808)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x80c)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x80c)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x80c)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x810)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x810)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x810)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x814)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x814)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x814)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0x824)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0x824)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0x824)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0x828)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0x828)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OFFS                                                             (0x828)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x82c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x82c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OFFS                                                           (0x82c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x830)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x830)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OFFS                                                           (0x830)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x834)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x834)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OFFS                                                                 (0x834)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x838)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x838)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_OFFS                                                             (0x838)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x83c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x83c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OFFS                                                               (0x83c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x840)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x840)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x840)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x844)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x844)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x844)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x850)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x850)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x850)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x854)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x854)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x854)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x858)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x858)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x858)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x874)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x874)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x874)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x878)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x878)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x878)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x87c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x87c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x87c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x880)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x880)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x880)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x884)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x884)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x884)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x888)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x888)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x888)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x88c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x88c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x88c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0x89c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0x89c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0x89c)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0x8a0)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0x8a0)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OFFS                                                             (0x8a0)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x8a4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x8a4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OFFS                                                           (0x8a4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x8a8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x8a8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OFFS                                                           (0x8a8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x8ac)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x8ac)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OFFS                                                                 (0x8ac)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x8b0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x8b0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_OFFS                                                             (0x8b0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x8b4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x8b4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OFFS                                                               (0x8b4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x8b8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x8b8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x8b8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x8bc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x8bc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x8bc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x8c8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x8c8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x8c8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x8cc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x8cc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x8cc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x8d0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x8d0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x8d0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x8ec)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x8ec)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x8ec)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x8f0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x8f0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x8f0)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x8f4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x8f4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x8f4)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x8f8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x8f8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x8f8)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x8fc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x8fc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x8fc)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x900)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x900)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x900)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x904)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x904)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x904)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0x914)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0x914)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0x914)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0x918)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0x918)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OFFS                                                             (0x918)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x91c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x91c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OFFS                                                           (0x91c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x920)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x920)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OFFS                                                           (0x920)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x924)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x924)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OFFS                                                                 (0x924)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x928)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x928)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_OFFS                                                             (0x928)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x92c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x92c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OFFS                                                               (0x92c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x930)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x930)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x930)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x934)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x934)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x934)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x940)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x940)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x940)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x944)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x944)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x944)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x948)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x948)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x948)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x964)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x964)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x964)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x968)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x968)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x968)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x96c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x96c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x96c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x970)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x970)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x970)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x974)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x974)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x974)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x978)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x978)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x978)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x97c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x97c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x97c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0x98c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0x98c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0x98c)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0x990)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0x990)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OFFS                                                             (0x990)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0x994)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0x994)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OFFS                                                           (0x994)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0x998)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0x998)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OFFS                                                           (0x998)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0x99c)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0x99c)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OFFS                                                                 (0x99c)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0x9a0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0x9a0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_OFFS                                                             (0x9a0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0x9a4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0x9a4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OFFS                                                               (0x9a4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0x9a8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0x9a8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0x9a8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0x9ac)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0x9ac)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0x9ac)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0x9b8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0x9b8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0x9b8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0x9bc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0x9bc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0x9bc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0x9c0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0x9c0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0x9c0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0x9dc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0x9dc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0x9dc)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0x9e0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0x9e0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0x9e0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0x9e4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0x9e4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OFFS                                                          (0x9e4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0x9e8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0x9e8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0x9e8)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0x9ec)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0x9ec)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0x9ec)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0x9f0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0x9f0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0x9f0)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0x9f4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0x9f4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OFFS                                                          (0x9f4)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0xa04)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0xa04)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0xa04)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0xa08)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0xa08)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OFFS                                                             (0xa08)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)                                                        ((x) + 0xa0c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_PHYS(x)                                                        ((x) + 0xa0c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OFFS                                                           (0xa0c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)                                                        ((x) + 0xa10)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_PHYS(x)                                                        ((x) + 0xa10)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OFFS                                                           (0xa10)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RMSK                                                             0xffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR                                                            0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ATTR                                                                        0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xffff00
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                          8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                              0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                 0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x)                                                              ((x) + 0xa14)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_PHYS(x)                                                              ((x) + 0xa14)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OFFS                                                                 (0xa14)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RMSK                                                                     0xffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR                                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ATTR                                                                              0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_BMSK                                                             0xff00
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_SHFT                                                                  8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                            0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                               0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x)                                                          ((x) + 0xa18)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_PHYS(x)                                                          ((x) + 0xa18)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_OFFS                                                             (0xa18)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ATTR                                                                          0x1
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                             0xffff0000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                     16
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                 0xffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                      0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x)                                                            ((x) + 0xa1c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_PHYS(x)                                                            ((x) + 0xa1c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OFFS                                                               (0xa1c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR                                                                0x00000080
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ATTR                                                                            0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK                                                0xf0000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT                                                        28
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK                                        0x4000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT                                               26
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK                                                       0x3c00000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT                                                              22
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                   0x3fc000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                         14
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                    0x3000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                        12
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                     0xf00
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                         8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                        0x80
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                           7
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                         0x40
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                            6
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                   0x20
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                      5
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                    0x10
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                       4
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                         0x8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                           3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                         0x4
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                           2
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                      0x2
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                        1
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                      0x1
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                        0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)                                                     ((x) + 0xa20)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x)                                                     ((x) + 0xa20)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS                                                        (0xa20)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK                                   0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)                                                     ((x) + 0xa24)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x)                                                     ((x) + 0xa24)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS                                                        (0xa24)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK                                                              0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR                                                         0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR                                                                     0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK                                         0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT                                            0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)                                              ((x) + 0xa30)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)                                              ((x) + 0xa30)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS                                                 (0xa30)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR                                                  0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR                                                              0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK                       0xffff0000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                               16
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                                   0x8000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                                       15
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                             0x7fff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)                                             ((x) + 0xa34)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)                                             ((x) + 0xa34)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS                                                (0xa34)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR                                                             0x1
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                  0xffff0000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                          16
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                          0x8000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                              15
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                       0x7fff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                            0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)                                           ((x) + 0xa38)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)                                           ((x) + 0xa38)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS                                              (0xa38)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK                                 0x3ff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT                                     0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                   ((x) + 0xa54)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                   ((x) + 0xa54)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                      (0xa54)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                   ((x) + 0xa58)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                   ((x) + 0xa58)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                      (0xa58)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)                                                       ((x) + 0xa5c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x)                                                       ((x) + 0xa5c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OFFS                                                          (0xa5c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)                                             ((x) + 0xa60)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x)                                             ((x) + 0xa60)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS                                                (0xa60)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK                                                0xffc0ffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR                                                 0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK                     0xff000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT                             24
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK                      0x800000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT                            23
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK                                    0x400000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT                                          22
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)                                                   ((x) + 0xa64)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x)                                                   ((x) + 0xa64)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS                                                      (0xa64)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK                                                 0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)                                                   ((x) + 0xa68)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x)                                                   ((x) + 0xa68)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS                                                      (0xa68)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK                                                           0x1ff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR                                                       0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR                                                                   0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK                                               0x100
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT                                                   8
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK                                                       0xff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT                                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)                                                       ((x) + 0xa6c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x)                                                       ((x) + 0xa6c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OFFS                                                          (0xa6c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR                                                           0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ATTR                                                                       0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                 ((x) + 0xa7c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                 ((x) + 0xa7c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                    (0xa7c)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                        0xffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                     0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                     0xffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                          0
+
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x)                                                          ((x) + 0xa80)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_PHYS(x)                                                          ((x) + 0xa80)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OFFS                                                             (0xa80)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_RMSK                                                             0xffff003f
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR                                                              0x00000000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ATTR                                                                          0x3
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                    0xffff0000
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                            16
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                           0x3f
+#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                              0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                    (0xdcc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                (0xdd0)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                    (0xdd4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                (0xdd8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0xddc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_PHYS(x)                                                         ((x) + 0xddc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OFFS                                                            (0xddc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR                                                             0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ATTR                                                                         0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                         0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                                  0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x)                                                         ((x) + 0xde0)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_PHYS(x)                                                         ((x) + 0xde0)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OFFS                                                            (0xde0)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RMSK                                                              0xffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR                                                             0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR_RMSK                                                        0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ATTR                                                                         0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                    0xffff00
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                               0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                  0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x)                                                               ((x) + 0xde4)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_PHYS(x)                                                               ((x) + 0xde4)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OFFS                                                                  (0xde4)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_RMSK                                                                        0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR                                                                   0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ATTR                                                                               0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK                                                             0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT                                                                0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x)                                                           ((x) + 0xde8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_PHYS(x)                                                           ((x) + 0xde8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_OFFS                                                              (0xde8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR                                                               0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ATTR                                                                           0x1
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                              0xffff0000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                      16
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK                                                  0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT                                                       0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x)                                                             ((x) + 0xdec)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_PHYS(x)                                                             ((x) + 0xdec)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OFFS                                                                (0xdec)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RMSK                                                                  0x7fffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR                                                                 0x00000080
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ATTR                                                                             0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x400000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                       22
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK                                                    0x3fc000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT                                                          14
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK                                                     0x3000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT                                                         12
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK                                                      0xf00
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT                                                          8
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK                                                         0x80
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT                                                            7
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK                                                          0x40
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT                                                             6
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                    0x20
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                       5
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                     0x10
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                        4
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK                                                          0x8
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                                                            3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK                                                          0x4
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT                                                            2
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK                                                       0x2
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT                                                         1
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)                                                      ((x) + 0xdf8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x)                                                      ((x) + 0xdf8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OFFS                                                         (0xdf8)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_RMSK                                                         0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                    0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                             0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)                                                      ((x) + 0xdfc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x)                                                      ((x) + 0xdfc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OFFS                                                         (0xdfc)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_RMSK                                                               0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR                                                          0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ATTR                                                                      0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                          0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                             0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                           ((x) + 0xe0c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                           ((x) + 0xe0c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS                                              (0xe0c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR                                               0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                           0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                    0xffff0000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                            16
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                                0x8000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                    15
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                          0x7fff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                               0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                           ((x) + 0xe10)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                           ((x) + 0xe10)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS                                              (0xe10)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK                                                  0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR                                               0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                           0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                    0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                         0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)                                              ((x) + 0xe14)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)                                              ((x) + 0xe14)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_OFFS                                                 (0xe14)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR                                                  0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ATTR                                                              0x1
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                   0xffff0000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                           16
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                              0x8000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                                  15
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                        0x7fff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                             0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                           ((x) + 0xe18)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                           ((x) + 0xe18)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS                                              (0xe18)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                   0x3ff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR                                               0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                           0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                                0x3ff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                    0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                          ((x) + 0xe1c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                          ((x) + 0xe1c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS                                             (0xe1c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                    0x7
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR                                              0x00000003
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                         0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                          0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                               0x7
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                                 0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                         ((x) + 0xe20)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                         ((x) + 0xe20)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS                                            (0xe20)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK                                              0xffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR                                             0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                        0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                         0x1
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                               0xff0000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                     16
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                              0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                   0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)                                                    ((x) + 0xe24)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)                                                    ((x) + 0xe24)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS                                                       (0xe24)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)                                                    ((x) + 0xe28)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)                                                    ((x) + 0xe28)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS                                                       (0xe28)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK                                                            0x1ff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR                                                        0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK                                                   0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR                                                                    0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                0x100
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                    8
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK                                                        0xff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                                                           0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x)                                                        ((x) + 0xe2c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_PHYS(x)                                                        ((x) + 0xe2c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OFFS                                                           (0xe2c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR                                                            0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ATTR                                                                        0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK                                                     0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT                                                              0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)                                                  ((x) + 0xe4c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)                                                  ((x) + 0xe4c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS                                                     (0xe4c)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK                                                         0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR                                                      0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR                                                                  0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                      0xffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                           0
+
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x)                                                           ((x) + 0xe50)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_PHYS(x)                                                           ((x) + 0xe50)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OFFS                                                              (0xe50)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_RMSK                                                              0xffff003f
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR                                                               0x00000000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ATTR                                                                           0x3
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x), m)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),v)
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x))
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                     0xffff0000
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                             16
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                            0x3f
+#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                               0
+
+#define HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x)                                                                       ((x) + 0xeac)
+#define HWIO_TQM_R0_EVENTMASK_IX_4_PHYS(x)                                                                       ((x) + 0xeac)
+#define HWIO_TQM_R0_EVENTMASK_IX_4_OFFS                                                                          (0xeac)
+#define HWIO_TQM_R0_EVENTMASK_IX_4_RMSK                                                                          0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_4_POR                                                                           0x00000000
+#define HWIO_TQM_R0_EVENTMASK_IX_4_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_4_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_EVENTMASK_IX_4_IN(x)            \
+                in_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x))
+#define HWIO_TQM_R0_EVENTMASK_IX_4_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x), m)
+#define HWIO_TQM_R0_EVENTMASK_IX_4_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),v)
+#define HWIO_TQM_R0_EVENTMASK_IX_4_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_4_IN(x))
+#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_BMSK                                                                     0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_SHFT                                                                              0
+
+#define HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x)                                                                       ((x) + 0xeb0)
+#define HWIO_TQM_R0_EVENTMASK_IX_5_PHYS(x)                                                                       ((x) + 0xeb0)
+#define HWIO_TQM_R0_EVENTMASK_IX_5_OFFS                                                                          (0xeb0)
+#define HWIO_TQM_R0_EVENTMASK_IX_5_RMSK                                                                          0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_5_POR                                                                           0x00000000
+#define HWIO_TQM_R0_EVENTMASK_IX_5_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_5_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_EVENTMASK_IX_5_IN(x)            \
+                in_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x))
+#define HWIO_TQM_R0_EVENTMASK_IX_5_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x), m)
+#define HWIO_TQM_R0_EVENTMASK_IX_5_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),v)
+#define HWIO_TQM_R0_EVENTMASK_IX_5_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_5_IN(x))
+#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_BMSK                                                                     0xffffffff
+#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_SHFT                                                                              0
+
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK                                                          0x80000000
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT                                                                  31
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_BMSK                                                  0x10000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_SHFT                                                       16
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK                                                            0x8000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT                                                                15
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK                                                        0x4000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT                                                            14
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK                                                                0x2000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT                                                                    13
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK                                                            0x1000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT                                                                12
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK                                               0x800
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT                                                  11
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK                                               0x400
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT                                                  10
+#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x)                                                                          ((x) + 0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS                                                                             (0xed8)
+#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK                                                                                    0xf
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR                                                                              0x00000000
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK                                                                         0xffffffff
+#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR                                                                                          0x3
+#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                     0x8
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                       3
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                     0x4
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                       2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                              0x2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                                1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                          0x1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                            0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x)                                                                       ((x) + 0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS                                                                          (0xee0)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK                                                                             0x1ffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR                                                                           0x00000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)            \
+                in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_BMSK                                              0x10000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_SHFT                                                   16
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_BMSK                                             0x8000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_SHFT                                                 15
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_BMSK                                                0x4000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_SHFT                                                    14
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_BMSK                                                  0x2000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_SHFT                                                      13
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_BMSK                                               0x1000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_SHFT                                                   12
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_BMSK                                              0x800
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_SHFT                                                 11
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_BMSK                                              0x400
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_SHFT                                                 10
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_BMSK                                              0x200
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_SHFT                                                  9
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_BMSK                                              0x100
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_SHFT                                                  8
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_BMSK                                               0x80
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_SHFT                                                  7
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_BMSK                                               0x40
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_SHFT                                                  6
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_BMSK                                               0x20
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_SHFT                                                  5
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_BMSK                                         0x10
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_SHFT                                            4
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_BMSK                                                   0x8
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_SHFT                                                     3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_BMSK                                                 0x4
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_SHFT                                                   2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK                                             0x2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT                                               1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK                                                     0x1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT                                                       0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK                                                     0x20000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT                                                             29
+#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_BMSK                                                 0xc00000
+#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_SHFT                                                       22
+#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_BMSK                                                                   0x40
+#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_SHFT                                                                      6
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x)                                                  ((x) + 0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS                                                     (0xf70)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR                                                      0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR                                                                  0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT                                                        0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x)                                           ((x) + 0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS                                              (0xf74)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x)                                           ((x) + 0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS                                              (0xf78)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x)                                                                        ((x) + 0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS                                                                           (0xf84)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK                                                                                0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR                                                                            0x00000710
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR                                                                                        0x3
+#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)            \
+                in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK                                                                          0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT                                                                              0
+
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x)                                                                ((x) + 0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS                                                                   (0x1204)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK                                                                        0x1ff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR                                                                    0x000001fe
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK                                          0x100
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT                                              8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK                                            0x80
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT                                               7
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK                                            0x40
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT                                               6
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK                                            0x20
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT                                               5
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK                                            0x10
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT                                               4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK                                             0x8
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT                                               3
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK                                             0x4
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT                                               2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK                                             0x2
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT                                               1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK                                              0x1
+#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT                                                0
+
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x)                                                                   ((x) + 0x120c)
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_PHYS(x)                                                                   ((x) + 0x120c)
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OFFS                                                                      (0x120c)
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_RMSK                                                                         0xfffff
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR                                                                       0x00000000
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ATTR                                                                                   0x3
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x)            \
+                in_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x))
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x), m)
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),v)
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),m,v,HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x))
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_BMSK                                             0xc0000
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_SHFT                                                  18
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_BMSK                                           0x30000
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_SHFT                                                16
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_BMSK                                            0xc000
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_SHFT                                                14
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_BMSK                                          0x3000
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_SHFT                                              12
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_BMSK                                             0xc00
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_SHFT                                                10
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_BMSK                                             0x300
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_SHFT                                                 8
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_BMSK                                              0xc0
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_SHFT                                                 6
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_BMSK                                              0x30
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_SHFT                                                 4
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_BMSK                                               0xc
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_SHFT                                                 2
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_BMSK                                                0x3
+#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_SHFT                                                  0
+
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1214)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1214)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_OFFS                                                                   (0x1214)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1218)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1218)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1218)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x121c)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x121c)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x121c)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1220)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1220)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1220)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1224)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1224)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_OFFS                                                                   (0x1224)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1228)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1228)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1228)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x122c)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x122c)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x122c)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1230)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1230)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1230)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1234)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1234)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_OFFS                                                                   (0x1234)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1238)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1238)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1238)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x123c)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x123c)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x123c)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1240)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1240)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1240)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1244)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1244)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_OFFS                                                                   (0x1244)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1248)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1248)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1248)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x124c)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x124c)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x124c)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1250)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1250)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1250)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1254)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1254)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_OFFS                                                                   (0x1254)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1258)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1258)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1258)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x125c)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x125c)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x125c)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1260)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1260)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1260)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1264)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1264)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_OFFS                                                                   (0x1264)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_RMSK                                                                       0x3fff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x3f80
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1268)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1268)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1268)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RMSK                                                                         0xff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0xfe
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x126c)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x126c)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x126c)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1270)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1270)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1270)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x1274)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x1274)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_OFFS                                                                   (0x1274)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_RMSK                                                                       0x1fff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x1f80
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x1278)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x1278)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x1278)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RMSK                                                                         0x7f
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0x7e
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x127c)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x127c)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x127c)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x1280)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x1280)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x1280)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x)                                                                 ((x) + 0x12d4)
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_PHYS(x)                                                                 ((x) + 0x12d4)
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_OFFS                                                                    (0x12d4)
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_RMSK                                                                        0x1fff
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR                                                                     0x00000000
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR_RMSK                                                                0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ATTR                                                                                 0x1
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                           0x1f80
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                                7
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                   0x7f
+#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                      0
+
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x)                                                                 ((x) + 0x12d8)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_PHYS(x)                                                                 ((x) + 0x12d8)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OFFS                                                                    (0x12d8)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RMSK                                                                          0x7f
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR                                                                     0x00000000
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR_RMSK                                                                0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ATTR                                                                                 0x3
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                   0x7e
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                      1
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                  0x1
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                    0
+
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x)                                                               ((x) + 0x12dc)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_PHYS(x)                                                               ((x) + 0x12dc)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_OFFS                                                                  (0x12dc)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR                                                                   0x00000000
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ATTR                                                                               0x1
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                          0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                   0
+
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x)                                                               ((x) + 0x12e0)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_PHYS(x)                                                               ((x) + 0x12e0)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_OFFS                                                                  (0x12e0)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR                                                                   0x00000000
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ATTR                                                                               0x1
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                          0xffffffff
+#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                   0
+
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x)                                                                ((x) + 0x12e4)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_PHYS(x)                                                                ((x) + 0x12e4)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_OFFS                                                                   (0x12e4)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_RMSK                                                                       0x1fff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR                                                                    0x00000000
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ATTR                                                                                0x1
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                          0x1f80
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                               7
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_BMSK                                                                  0x7f
+#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_SHFT                                                                     0
+
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x)                                                                ((x) + 0x12e8)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_PHYS(x)                                                                ((x) + 0x12e8)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OFFS                                                                   (0x12e8)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RMSK                                                                         0x7f
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR                                                                    0x00000000
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ATTR                                                                                0x3
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_BMSK                                                                  0x7e
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_SHFT                                                                     1
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_BMSK                                                                 0x1
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_SHFT                                                                   0
+
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x)                                                              ((x) + 0x12ec)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_PHYS(x)                                                              ((x) + 0x12ec)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_OFFS                                                                 (0x12ec)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR                                                                  0x00000000
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ATTR                                                                              0x1
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x)                                                              ((x) + 0x12f0)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_PHYS(x)                                                              ((x) + 0x12f0)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_OFFS                                                                 (0x12f0)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR                                                                  0x00000000
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ATTR                                                                              0x1
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK                                                         0xffffffff
+#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                  0
+
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x)                                                               ((x) + 0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS                                                                  (0x12f4)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK                                                                    0x3fefff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR                                                                   0x00080170
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR                                                                               0x3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)            \
+                in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v)
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x))
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK                                            0x200000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT                                                  21
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK                                         0x100000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT                                               20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK                                      0x80000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT                                           19
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK                                             0x40000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT                                                  18
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK                                                    0x20000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT                                                         17
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK                                                        0x10000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT                                                             16
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK                                          0x8000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT                                              15
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK                                                 0x4000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT                                                     14
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK                                                0x2000
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT                                                    13
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK                                                     0x800
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT                                                        11
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK                                                      0x400
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT                                                         10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK                                                0x200
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT                                                    9
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK                                             0x100
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT                                                 8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK                                               0x80
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT                                                  7
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK                                                       0x40
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT                                                          6
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK                                                  0x20
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT                                                     5
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK                                                 0x10
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT                                                    4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK                                               0x8
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT                                                 3
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK                                                 0x4
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT                                                   2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK                                               0x2
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT                                                 1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK                                             0x1
+#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT                                               0
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x)                                                                       ((x) + 0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS                                                                          (0x12f8)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK                                                                          0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR                                                                           0x00000000
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK                                                  0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT                                                           0
+
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x)                                                                       ((x) + 0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS                                                                          (0x12fc)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK                                                                             0x7ffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR                                                                           0x00011100
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)            \
+                in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v)
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x))
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                              0x40000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                   18
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                           0x3e000
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                13
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                              0x1f00
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                   8
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                       0xff
+#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                          0
+
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x)                                                             ((x) + 0x1300)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_PHYS(x)                                                             ((x) + 0x1300)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OFFS                                                                (0x1300)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RMSK                                                                      0x7f
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR                                                                 0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ATTR                                                                             0x3
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK                                                               0x7e
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT                                                                  1
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK                                                              0x1
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT                                                                0
+
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x)                                                             ((x) + 0x1304)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_PHYS(x)                                                             ((x) + 0x1304)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_OFFS                                                                (0x1304)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_RMSK                                                                    0x1fff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR                                                                 0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ATTR                                                                             0x1
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                       0x1f80
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                            7
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_BMSK                                                               0x7f
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_SHFT                                                                  0
+
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x)                                                           ((x) + 0x1308)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_PHYS(x)                                                           ((x) + 0x1308)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_OFFS                                                              (0x1308)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR                                                               0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ATTR                                                                           0x1
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK                                                      0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT                                                               0
+
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x)                                                           ((x) + 0x130c)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_PHYS(x)                                                           ((x) + 0x130c)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_OFFS                                                              (0x130c)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR                                                               0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ATTR                                                                           0x1
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK                                                      0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT                                                               0
+
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x)                                                             ((x) + 0x1310)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_PHYS(x)                                                             ((x) + 0x1310)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_OFFS                                                                (0x1310)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_RMSK                                                                      0x1f
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR                                                                 0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ATTR                                                                             0x1
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                         0x18
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                            3
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_BMSK                                                                0x7
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_SHFT                                                                  0
+
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x)                                                             ((x) + 0x1314)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_PHYS(x)                                                             ((x) + 0x1314)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OFFS                                                                (0x1314)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RMSK                                                                       0x7
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR                                                                 0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ATTR                                                                             0x3
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_BMSK                                                                0x6
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_SHFT                                                                  1
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_BMSK                                                              0x1
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_SHFT                                                                0
+
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x)                                                           ((x) + 0x1318)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_PHYS(x)                                                           ((x) + 0x1318)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_OFFS                                                              (0x1318)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR                                                               0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ATTR                                                                           0x1
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_BMSK                                                      0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_SHFT                                                               0
+
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x)                                                             ((x) + 0x131c)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_PHYS(x)                                                             ((x) + 0x131c)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_OFFS                                                                (0x131c)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_RMSK                                                                      0x1f
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR                                                                 0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ATTR                                                                             0x1
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                         0x18
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                            3
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_BMSK                                                                0x7
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_SHFT                                                                  0
+
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x)                                                             ((x) + 0x1320)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_PHYS(x)                                                             ((x) + 0x1320)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OFFS                                                                (0x1320)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RMSK                                                                       0x7
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR                                                                 0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ATTR                                                                             0x3
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_BMSK                                                                0x6
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_SHFT                                                                  1
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_BMSK                                                              0x1
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_SHFT                                                                0
+
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x)                                                           ((x) + 0x1324)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_PHYS(x)                                                           ((x) + 0x1324)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_OFFS                                                              (0x1324)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RMSK                                                              0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR                                                               0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR_RMSK                                                          0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ATTR                                                                           0x1
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_BMSK                                                      0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_SHFT                                                               0
+
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x)                                                      ((x) + 0x1328)
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_PHYS(x)                                                      ((x) + 0x1328)
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_OFFS                                                         (0x1328)
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_RMSK                                                          0xfffffff
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR                                                          0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ATTR                                                                      0x1
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK                                                    0xfffffff
+#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT                                                            0
+
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x)                                                        ((x) + 0x132c)
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_PHYS(x)                                                        ((x) + 0x132c)
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OFFS                                                           (0x132c)
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RMSK                                                               0x3fff
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR                                                            0x00000000
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR_RMSK                                                       0xffffffff
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ATTR                                                                        0x3
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x)            \
+                in_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x))
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x), m)
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),v)
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x))
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_BMSK                                              0x3000
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_SHFT                                                  12
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_BMSK                                                          0xfff
+#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_SHFT                                                              0
+
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x)                                                       ((x) + 0x1330)
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_PHYS(x)                                                       ((x) + 0x1330)
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_OFFS                                                          (0x1330)
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_RMSK                                                           0xfffffff
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR                                                           0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR_RMSK                                                      0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ATTR                                                                       0x1
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK                                                     0xfffffff
+#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT                                                             0
+
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x)                                                              ((x) + 0x1334)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_PHYS(x)                                                              ((x) + 0x1334)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_OFFS                                                                 (0x1334)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_RMSK                                                                      0x7ff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR                                                                  0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ATTR                                                                              0x1
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK                                                         0x7c0
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT                                                             6
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_BMSK                                                                0x3f
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_SHFT                                                                   0
+
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x)                                                              ((x) + 0x1338)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_PHYS(x)                                                              ((x) + 0x1338)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OFFS                                                                 (0x1338)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RMSK                                                                       0x3f
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR                                                                  0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ATTR                                                                              0x3
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x))
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK                                                                0x3e
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT                                                                   1
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK                                                               0x1
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT                                                                 0
+
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x)                                                            ((x) + 0x133c)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_PHYS(x)                                                            ((x) + 0x133c)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_OFFS                                                               (0x133c)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR                                                                0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ATTR                                                                            0x1
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK                                                       0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT                                                                0
+
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x)                                                            ((x) + 0x1340)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_PHYS(x)                                                            ((x) + 0x1340)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_OFFS                                                               (0x1340)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RMSK                                                               0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR                                                                0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ATTR                                                                            0x1
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK                                                       0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT                                                                0
+
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x)                                                             ((x) + 0x1344)
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_PHYS(x)                                                             ((x) + 0x1344)
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_OFFS                                                                (0x1344)
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RMSK                                                                  0x1fffff
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR                                                                 0x00000000
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR_RMSK                                                            0xffffffff
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ATTR                                                                             0x1
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_IN(x)            \
+                in_dword(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x))
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x), m)
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_BMSK                                                 0x1e0000
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_SHFT                                                       17
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_BMSK                                                      0x1fff0
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_SHFT                                                            4
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_BMSK                                                           0xf
+#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_SHFT                                                             0
+
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x)                                                                  ((x) + 0x1348)
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_PHYS(x)                                                                  ((x) + 0x1348)
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OFFS                                                                     (0x1348)
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_RMSK                                                                            0x7
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR                                                                      0x00000000
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ATTR                                                                                  0x3
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x))
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK                                                            0x4
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT                                                              2
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK                                                              0x2
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT                                                                1
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK                                                              0x1
+#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT                                                                0
+
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x)                                                                   ((x) + 0x134c)
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_PHYS(x)                                                                   ((x) + 0x134c)
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_OFFS                                                                      (0x134c)
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_RMSK                                                                         0x3ffff
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR                                                                       0x00001441
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ATTR                                                                                   0x1
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x))
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_BMSK                                                      0x20000
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_SHFT                                                           17
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK                                                           0x1f000
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT                                                                12
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK                                                        0x800
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT                                                           11
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK                                                0x400
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT                                                   10
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK                                                  0x3c0
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT                                                      6
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK                                               0x20
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT                                                  5
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK                                                              0x1f
+#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT                                                                 0
+
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x)                                                 ((x) + 0x1350)
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_PHYS(x)                                                 ((x) + 0x1350)
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_OFFS                                                    (0x1350)
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RMSK                                                    0xffffffff
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR                                                     0x00000000
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ATTR                                                                 0x1
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_IN(x)            \
+                in_dword(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x))
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x), m)
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK                                   0x80000000
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT                                           31
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK                                       0x40000000
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT                                               30
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK                                         0x30000000
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT                                                 28
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK                                    0xffffe00
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT                                            9
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK                                               0x180
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT                                                   7
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK                                         0x70
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT                                            4
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK                                     0xf
+#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT                                       0
+
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x)                                                                   ((x) + 0x1354)
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_PHYS(x)                                                                   ((x) + 0x1354)
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OFFS                                                                      (0x1354)
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RMSK                                                                         0x13fff
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR                                                                       0x00000020
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ATTR                                                                                   0x3
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x)            \
+                in_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x))
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x), m)
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),v)
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),m,v,HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x))
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK                                               0x10000
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT                                                    16
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK                                                    0x2000
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT                                                        13
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK                                                0x1000
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT                                                    12
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK                                                  0xfff
+#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT                                                      0
+
+#define HWIO_TQM_R0_SM_STATES_IX4_ADDR(x)                                                                        ((x) + 0x15f0)
+#define HWIO_TQM_R0_SM_STATES_IX4_PHYS(x)                                                                        ((x) + 0x15f0)
+#define HWIO_TQM_R0_SM_STATES_IX4_OFFS                                                                           (0x15f0)
+#define HWIO_TQM_R0_SM_STATES_IX4_RMSK                                                                           0xffffffff
+#define HWIO_TQM_R0_SM_STATES_IX4_POR                                                                            0x00000000
+#define HWIO_TQM_R0_SM_STATES_IX4_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_SM_STATES_IX4_ATTR                                                                                        0x1
+#define HWIO_TQM_R0_SM_STATES_IX4_IN(x)            \
+                in_dword(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x))
+#define HWIO_TQM_R0_SM_STATES_IX4_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x), m)
+#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK                                                 0xc0000000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT                                                         30
+#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK                                                 0x30000000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT                                                         28
+#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK                                                  0xc000000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT                                                         26
+#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK                                                  0x3000000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT                                                         24
+#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK                                                   0xc00000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT                                                         22
+#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK                                                   0x300000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT                                                         20
+#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK                                                    0xc0000
+#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT                                                         18
+#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK                                                  0x30000
+#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT                                                       16
+#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK                                                      0xc000
+#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT                                                          14
+#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK                                                           0x3000
+#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT                                                               12
+#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK                                                       0xf00
+#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT                                                           8
+#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK                                                              0xf8
+#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT                                                                 3
+#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK                                                                 0x7
+#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT                                                                   0
+
+#define HWIO_TQM_R0_SM_STATES_IX5_ADDR(x)                                                                        ((x) + 0x15f4)
+#define HWIO_TQM_R0_SM_STATES_IX5_PHYS(x)                                                                        ((x) + 0x15f4)
+#define HWIO_TQM_R0_SM_STATES_IX5_OFFS                                                                           (0x15f4)
+#define HWIO_TQM_R0_SM_STATES_IX5_RMSK                                                                                  0xf
+#define HWIO_TQM_R0_SM_STATES_IX5_POR                                                                            0x00000000
+#define HWIO_TQM_R0_SM_STATES_IX5_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_SM_STATES_IX5_ATTR                                                                                        0x1
+#define HWIO_TQM_R0_SM_STATES_IX5_IN(x)            \
+                in_dword(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x))
+#define HWIO_TQM_R0_SM_STATES_IX5_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x), m)
+#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK                                                    0xc
+#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT                                                      2
+#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK                                                    0x3
+#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT                                                      0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS                                                   (0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR                                                    0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK                                               0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR                                                                0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK                                              0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT                                                 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS                                                    (0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR                                                     0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR                                                                 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT                                                   0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS                                                (0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK                                                      0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR                                                 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR                                                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK                                           0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS                                                 (0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK                                                 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR                                                  0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR                                                              0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK                                       0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT                                                0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS                                              (0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK                                              0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR                                               0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR                                                           0x3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK                                    0xffff0000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT                                            16
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK                            0xfff0
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT                                 4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK                                  0x8
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT                                    3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK                                       0x4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT                                         2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT                               1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK                                         0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT                                           0
+
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS                                                                       (0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS                                                                      (0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK                                                                         0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR                                                                       0x00000000
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR                                                                                   0x3
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK                                                             0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                   0
+
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS                                                                       (0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS                                                                 (0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK                                                                        0xf
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR                                                                  0x00000000
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR                                                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x))
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK                                                0x8
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT                                                  3
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x4
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT                                                   2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT                                                   1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT                                                0
+
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS                                                                     (0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK                                                                     0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR                                                                      0x00000000
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR                                                                                  0x1
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK                                                               0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT                                                                        0
+
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS                                                                  (0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR                                                                   0x00000000
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR                                                                               0x1
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK                                                            0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT                                                                     0
+
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                  (0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                        0xff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                   0x00000000
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                               0x1
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                             0x80
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                             0x40
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                6
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                      0x20
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                         5
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                   0x10
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                      4
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                      0x8
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                        3
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                0x7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                  0
+
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x)                                                                   ((x) + 0x211c)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_PHYS(x)                                                                   ((x) + 0x211c)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_OFFS                                                                      (0x211c)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR                                                                       0x00000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ATTR                                                                                   0x1
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_IN(x)            \
+                in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x))
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x), m)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK                                            0xc0000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT                                                    30
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK                                            0x30000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT                                                    28
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK                                             0xc000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT                                                    26
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK                                             0x3000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT                                                    24
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK                                              0xc00000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT                                                    22
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK                                              0x300000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT                                                    20
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK                                               0xc0000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT                                                    18
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK                                             0x30000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT                                                  16
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK                                                 0xc000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT                                                     14
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK                                                      0x3000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT                                                          12
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK                                                  0xf00
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT                                                      8
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK                                                         0xf8
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT                                                            3
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK                                                            0x7
+#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT                                                              0
+
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x)                                                                   ((x) + 0x2120)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_PHYS(x)                                                                   ((x) + 0x2120)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_OFFS                                                                      (0x2120)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_RMSK                                                                             0xf
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR                                                                       0x00000000
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ATTR                                                                                   0x1
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_IN(x)            \
+                in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x))
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x), m)
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK                                               0xc
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT                                                 2
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK                                               0x3
+#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT                                                 0
+
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                               ((base) + 0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                    (0X2124 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn                                                                              127
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR                                                                        0x00000000
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                    0x1
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                           0
+
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x)                                                               ((x) + 0x3068)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_PHYS(x)                                                               ((x) + 0x3068)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OFFS                                                                  (0x3068)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_RMSK                                                                      0xffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR                                                                   0x00000000
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ATTR                                                                               0x3
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK                                                             0xffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                  0
+
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x)                                                               ((x) + 0x306c)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_PHYS(x)                                                               ((x) + 0x306c)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OFFS                                                                  (0x306c)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_RMSK                                                                      0xffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR                                                                   0x00000000
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ATTR                                                                               0x3
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK                                                             0xffff
+#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                  0
+
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x)                                                            ((x) + 0x3070)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_PHYS(x)                                                            ((x) + 0x3070)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OFFS                                                               (0x3070)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_RMSK                                                                   0xffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR                                                                0x00000000
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ATTR                                                                            0x3
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_BMSK                                                          0xffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_SHFT                                                               0
+
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x)                                                            ((x) + 0x3074)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_PHYS(x)                                                            ((x) + 0x3074)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OFFS                                                               (0x3074)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_RMSK                                                                   0xffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR                                                                0x00000000
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR_RMSK                                                           0xffffffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ATTR                                                                            0x3
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_BMSK                                                          0xffff
+#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_SHFT                                                               0
+
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS                                                                 (0x3078)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x307c)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x307c)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OFFS                                                                 (0x307c)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS                                                                 (0x3080)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x3084)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x3084)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OFFS                                                                 (0x3084)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3088)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3088)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OFFS                                                                 (0x3088)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x308c)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x308c)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OFFS                                                                 (0x308c)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3090)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3090)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OFFS                                                                 (0x3090)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x3094)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x3094)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OFFS                                                                 (0x3094)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x3098)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x3098)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OFFS                                                                 (0x3098)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x309c)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x309c)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OFFS                                                                 (0x309c)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x30a0)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x30a0)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OFFS                                                                 (0x30a0)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x30a4)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x30a4)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OFFS                                                                 (0x30a4)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x)                                                              ((x) + 0x30a8)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_PHYS(x)                                                              ((x) + 0x30a8)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OFFS                                                                 (0x30a8)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x)                                                              ((x) + 0x30ac)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_PHYS(x)                                                              ((x) + 0x30ac)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OFFS                                                                 (0x30ac)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_RMSK                                                                     0xffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR                                                                  0x00000000
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ATTR                                                                              0x3
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK                                                            0xffff
+#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                 0
+
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x)                                                               ((x) + 0x30e8)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_PHYS(x)                                                               ((x) + 0x30e8)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OFFS                                                                  (0x30e8)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_RMSK                                                                      0xffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR                                                                   0x00000000
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ATTR                                                                               0x3
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x)            \
+                in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x))
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x), m)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),v)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x))
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_BMSK                                                             0xffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_SHFT                                                                  0
+
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x)                                                               ((x) + 0x30ec)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_PHYS(x)                                                               ((x) + 0x30ec)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OFFS                                                                  (0x30ec)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_RMSK                                                                      0xffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR                                                                   0x00000000
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ATTR                                                                               0x3
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x)            \
+                in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x))
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x), m)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),v)
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x))
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_BMSK                                                             0xffff
+#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_P_TQM3_BMSK                                                                       0x40000
+#define HWIO_UMCMN_R0_ISR_P_TQM3_SHFT                                                                            18
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_BMSK                                                   0x4000000
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_SHFT                                                          26
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_BMSK                                                   0x2000000
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_SHFT                                                          25
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_BMSK                                                   0x1000000
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_SHFT                                                          24
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_BMSK                                                    0x800000
+#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_SHFT                                                          23
+#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_BMSK                                                         0x400000
+#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_SHFT                                                               22
+#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_BMSK                                                             0x80
+#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_SHFT                                                                7
+#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_BMSK                                                               0x1
+#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_SHFT                                                                 0
+
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_BMSK                                                     0x800000
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_SHFT                                                           23
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_BMSK                                                     0x400000
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_SHFT                                                           22
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_BMSK                                                     0x200000
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_SHFT                                                           21
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_BMSK                                                     0x100000
+#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_SHFT                                                           20
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK                                               0x400000
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT                                                     22
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK                                               0x200000
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT                                                     21
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK                                               0x100000
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT                                                     20
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK                                                0x80000
+#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT                                                     19
+#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK                                     0x40000
+#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT                                          18
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK                                            0x80000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT                                                    31
+#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK                                           0x40000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT                                                   30
+#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK                                               0x20000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT                                                       29
+#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK                                              0x10000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT                                                      28
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK                                               0x8000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT                                                      27
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK                                               0x4000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT                                                      26
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK                                               0x2000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT                                                      25
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK                                               0x1000000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT                                                      24
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK                                                0x800000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT                                                      23
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK                                                0x400000
+#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT                                                      22
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK                                               0x40000
+#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT                                                    18
+#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK                                                0x20000
+#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT                                                     17
+#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK                                           0x8000
+#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT                                               15
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_IMR_P_TQM3_BMSK                                                                       0x40000
+#define HWIO_UMCMN_R0_IMR_P_TQM3_SHFT                                                                            18
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x10000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                28
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                         0x8000000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                27
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_BMSK                                                   0x4000000
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_SHFT                                                          26
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_BMSK                                                   0x2000000
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_SHFT                                                          25
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_BMSK                                                   0x1000000
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_SHFT                                                          24
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_BMSK                                                    0x800000
+#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_SHFT                                                          23
+#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_BMSK                                                         0x400000
+#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_SHFT                                                               22
+#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_BMSK                                                             0x80
+#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_SHFT                                                                7
+#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_BMSK                                                               0x1
+#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_SHFT                                                                 0
+
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_BMSK                                                     0x800000
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_SHFT                                                           23
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_BMSK                                                     0x400000
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_SHFT                                                           22
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_BMSK                                                     0x200000
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_SHFT                                                           21
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_BMSK                                                     0x100000
+#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_SHFT                                                           20
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK                                               0x400000
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT                                                     22
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK                                               0x200000
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT                                                     21
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK                                               0x100000
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT                                                     20
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK                                                0x80000
+#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT                                                     19
+#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK                                     0x40000
+#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT                                          18
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK                                            0x80000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT                                                    31
+#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK                                           0x40000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT                                                   30
+#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK                                               0x20000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT                                                       29
+#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK                                              0x10000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT                                                      28
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK                                               0x8000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT                                                      27
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK                                               0x4000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT                                                      26
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK                                               0x2000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT                                                      25
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK                                               0x1000000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT                                                      24
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK                                                0x800000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT                                                      23
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK                                                0x400000
+#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT                                                      22
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK                                               0x40000
+#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT                                                    18
+#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK                                                0x20000
+#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT                                                     17
+#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK                                           0x8000
+#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT                                               15
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK                                             0x40
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT                                                6
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS                                                (0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK                                                       0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR                                                 0x0000000a
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK                                                 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT                                                   0
+
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS                                                                   (0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK                                                                         0x1f
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK                                                   0x10
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT                                                      4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK                                                    0x8
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT                                                      3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK                                                    0x4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT                                                      2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK                                                    0x2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT                                                      1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_LINK_ID_ADDR(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_PHYS(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_OFFS                                                                       (0x170)
+#define HWIO_UMCMN_R0_LINK_ID_RMSK                                                                           0xffff
+#define HWIO_UMCMN_R0_LINK_ID_POR                                                                        0x000052c8
+#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_LINK_ID_ATTR                                                                                    0x3
+#define HWIO_UMCMN_R0_LINK_ID_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x))
+#define HWIO_UMCMN_R0_LINK_ID_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m)
+#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v)
+#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x))
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK                                                               0x80
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT                                                                  7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK                                                               0x40
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT                                                                  6
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK                                                               0x38
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT                                                                  3
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK                                                                0x7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK                                                    0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT                                                        14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK                                                0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT                                                    13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK                                                    0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT                                                        12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK                                                     0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT                                                        11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK                                                     0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT                                                        10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK                                                     0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT                                                         9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK                                                     0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT                                                         8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK                                                       0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT                                                          7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK                                                       0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT                                                          6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK                                                       0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT                                                          5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK                                                       0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT                                                          4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK                                                         0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT                                                           3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK                                                        0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT                                                          2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK                                                         0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT                                                           1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK                                                        0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT                                                          0
+
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS                                                             (0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK                                                                    0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR                                                              0x00000000
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK                                                         0xffffffff
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR                                                                          0x3
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS                                                (0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK                                                   0x1ffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR                                                 0x00000000
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK                   0x1fe00
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT                         9
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK                    0x1fe
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT                        1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK                         0x1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT                           0
+
+#define HWIO_UMCMN_R0_ISR_S18_ADDR(x)                                                                    ((x) + 0x194)
+#define HWIO_UMCMN_R0_ISR_S18_PHYS(x)                                                                    ((x) + 0x194)
+#define HWIO_UMCMN_R0_ISR_S18_OFFS                                                                       (0x194)
+#define HWIO_UMCMN_R0_ISR_S18_RMSK                                                                       0x7fffffff
+#define HWIO_UMCMN_R0_ISR_S18_POR                                                                        0x00000000
+#define HWIO_UMCMN_R0_ISR_S18_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_ISR_S18_ATTR                                                                                    0x0
+#define HWIO_UMCMN_R0_ISR_S18_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x))
+#define HWIO_UMCMN_R0_ISR_S18_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_ISR_S18_ADDR(x), m)
+#define HWIO_UMCMN_R0_ISR_S18_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x),v)
+#define HWIO_UMCMN_R0_ISR_S18_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S18_IN(x))
+#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_BMSK                                                  0x40000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_SHFT                                                          30
+#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK                                        0x20000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT                                                29
+#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK                                         0x10000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT                                                 28
+#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x8000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT                                              27
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK                                   0x4000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT                                          26
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK                                      0x2000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             25
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK                                      0x1000000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             24
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x800000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             23
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x400000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             22
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x200000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             21
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x100000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             20
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK                                        0x80000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             19
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK                                               0x40000
+#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT                                                    18
+#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x20000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            17
+#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x10000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         16
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x8000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           15
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x4000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        14
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x2000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           13
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x1000
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        12
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x800
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           11
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x400
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        10
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x200
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            9
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x100
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         8
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK                                         0x80
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            7
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                      0x40
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         6
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK                                         0x20
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            5
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                      0x10
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         4
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK                                          0x8
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            3
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                       0x4
+#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         2
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x2
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT                                          1
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x1
+#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                       0
+
+#define HWIO_UMCMN_R0_IMR_S18_ADDR(x)                                                                    ((x) + 0x198)
+#define HWIO_UMCMN_R0_IMR_S18_PHYS(x)                                                                    ((x) + 0x198)
+#define HWIO_UMCMN_R0_IMR_S18_OFFS                                                                       (0x198)
+#define HWIO_UMCMN_R0_IMR_S18_RMSK                                                                       0x7fffffff
+#define HWIO_UMCMN_R0_IMR_S18_POR                                                                        0x00000000
+#define HWIO_UMCMN_R0_IMR_S18_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_IMR_S18_ATTR                                                                                    0x3
+#define HWIO_UMCMN_R0_IMR_S18_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x))
+#define HWIO_UMCMN_R0_IMR_S18_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_IMR_S18_ADDR(x), m)
+#define HWIO_UMCMN_R0_IMR_S18_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x),v)
+#define HWIO_UMCMN_R0_IMR_S18_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S18_IN(x))
+#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_BMSK                                                  0x40000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_SHFT                                                          30
+#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK                                        0x20000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT                                                29
+#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK                                         0x10000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT                                                 28
+#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x8000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT                                              27
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK                                   0x4000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT                                          26
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK                                      0x2000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             25
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK                                      0x1000000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             24
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x800000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             23
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x400000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             22
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x200000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             21
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK                                       0x100000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             20
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK                                        0x80000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT                                             19
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK                                               0x40000
+#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT                                                    18
+#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x20000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            17
+#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x10000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         16
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x8000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           15
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x4000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        14
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK                                       0x2000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           13
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                    0x1000
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        12
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x800
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT                                           11
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x400
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                        10
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x200
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            9
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x100
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         8
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK                                         0x80
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            7
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                      0x40
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         6
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK                                         0x20
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            5
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                      0x10
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         4
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK                                          0x8
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT                                            3
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                       0x4
+#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                         2
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK                                        0x2
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT                                          1
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK                                     0x1
+#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT                                       0
+
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                             0x1ff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK                                           0x100
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT                                               8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK                                            0x80
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT                                               7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK                                            0x40
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT                                               6
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK                                            0x20
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT                                               5
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n)                                                 (0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn                                                             7
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR                                                     0x00000000
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR                                                                 0x3
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)                \
+                in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT                                                         0
+
+#define MAC_TCL_REG_REG_BASE                                                                           (UMAC_BASE      + 0x00044000)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x)                                                          ((x) + 0x14)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_PHYS(x)                                                          ((x) + 0x14)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OFFS                                                             (0x14)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RMSK                                                                0x3ffe0
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR                                                              0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ATTR                                                                          0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_BMSK                                                    0x3ffc0
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_SHFT                                                          6
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_BMSK                                                          0x20
+#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_SHFT                                                             5
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x)                                                          ((x) + 0x18)
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_PHYS(x)                                                          ((x) + 0x18)
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OFFS                                                             (0x18)
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RMSK                                                                0x3ffe0
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR                                                              0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ATTR                                                                          0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_BMSK                                                    0x3ffc0
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_SHFT                                                          6
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_BMSK                                                          0x20
+#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_SHFT                                                             5
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                                                     ((x) + 0x20)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK                                  0x800000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT                                        23
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_BMSK                                     0x20000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_SHFT                                          17
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_BMSK                                     0x10000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_SHFT                                          16
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_BMSK                                            0x200
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_SHFT                                                9
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_BMSK                                            0x100
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_SHFT                                                8
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK                                      0x200000
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT                                            21
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x)                                          ((x) + 0x34)
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_PHYS(x)                                          ((x) + 0x34)
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OFFS                                             (0x34)
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RMSK                                             0xffffffff
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR                                              0x005a0060
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR_RMSK                                         0xffffffff
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ATTR                                                          0x3
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x)            \
+                in_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x))
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x), m)
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),v)
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x))
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_BMSK                                 0xffff0000
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_SHFT                                         16
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_BMSK                                        0xffff
+#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_SHFT                                             0
+
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x)                                          ((x) + 0x38)
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_PHYS(x)                                          ((x) + 0x38)
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OFFS                                             (0x38)
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_RMSK                                             0xffffffff
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR                                              0x004a004a
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR_RMSK                                         0xffffffff
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ATTR                                                          0x3
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x)            \
+                in_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x))
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x), m)
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),v)
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x))
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_BMSK                                    0xffff0000
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_SHFT                                            16
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_BMSK                                     0xffff
+#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_SHFT                                          0
+
+#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_BMSK                                                       0xc000
+#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_SHFT                                                           14
+#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_BMSK                                                       0x3000
+#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_SHFT                                                           12
+#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_BMSK                                                        0xc00
+#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_SHFT                                                           10
+#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_BMSK                                                0xc0
+#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_SHFT                                                   6
+#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_BMSK                                              0x30
+#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_SHFT                                                 4
+
+#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_BMSK                                                              0x80
+#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_SHFT                                                                 7
+#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_BMSK                                                              0x40
+#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_SHFT                                                                 6
+#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_BMSK                                                              0x20
+#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_SHFT                                                                 5
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x)                                                            ((x) + 0x64)
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_PHYS(x)                                                            ((x) + 0x64)
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OFFS                                                               (0x64)
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_RMSK                                                                   0x1fff
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR                                                                0x00000004
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ATTR                                                                            0x3
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_BMSK                                                     0x1fe0
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_SHFT                                                          5
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_BMSK                                                         0x1f
+#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_SHFT                                                            0
+
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x)                                                            ((x) + 0x68)
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_PHYS(x)                                                            ((x) + 0x68)
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OFFS                                                               (0x68)
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_RMSK                                                                   0x1fff
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR                                                                0x00000004
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ATTR                                                                            0x3
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_BMSK                                                     0x1fe0
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_SHFT                                                          5
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_BMSK                                                         0x1f
+#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_SHFT                                                            0
+
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x)                                                            ((x) + 0x6c)
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_PHYS(x)                                                            ((x) + 0x6c)
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OFFS                                                               (0x6c)
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_RMSK                                                                   0x1fff
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR                                                                0x00000004
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ATTR                                                                            0x3
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x)            \
+                in_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x))
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x), m)
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),v)
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x))
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK                                                     0x1fe0
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT                                                          5
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_BMSK                                                         0x1f
+#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_SHFT                                                            0
+
+#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_BMSK                                                     0xf0000000
+#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_SHFT                                                             28
+#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_BMSK                                                      0xf000000
+#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_SHFT                                                             24
+#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_BMSK                                                       0xf00000
+#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_SHFT                                                             20
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n)                                                      ((base) + 0X74 + (0x4*(n)))
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT                                                   17
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT                                                     14
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT                                                          12
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT                                                        8
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT                                                       7
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT                                                          3
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT                                                            1
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT                                                                   0
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n)                                                        ((base) + 0X174 + (0x4*(n)))
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK                                                                0xffffffff
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_BMSK                                         0x6000000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_SHFT                                                25
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_BMSK                                                       0x1000000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_SHFT                                                              24
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK                                              0x800000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT                                                    23
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x)                                                   ((x) + 0x818)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_PHYS(x)                                                   ((x) + 0x818)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OFFS                                                      (0x818)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_RMSK                                                            0xff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR                                                       0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR_RMSK                                                  0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ATTR                                                                   0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_BMSK                                                       0xf0
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_SHFT                                                          4
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_BMSK                                                        0xf
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_SHFT                                                          0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x)                                         ((x) + 0x81c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_PHYS(x)                                         ((x) + 0x81c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OFFS                                            (0x81c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_RMSK                                            0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR                                             0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR_RMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ATTR                                                         0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_BMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_SHFT                                                 0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x)                                        ((x) + 0x820)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_PHYS(x)                                        ((x) + 0x820)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OFFS                                           (0x820)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x)                                        ((x) + 0x824)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_PHYS(x)                                        ((x) + 0x824)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OFFS                                           (0x824)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x)                                       ((x) + 0x828)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_PHYS(x)                                       ((x) + 0x828)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OFFS                                          (0x828)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR                                           0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ATTR                                                       0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_SHFT                                               0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x)                                         ((x) + 0x82c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_PHYS(x)                                         ((x) + 0x82c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OFFS                                            (0x82c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_RMSK                                            0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR                                             0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR_RMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ATTR                                                         0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_BMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_SHFT                                                 0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x)                                        ((x) + 0x830)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_PHYS(x)                                        ((x) + 0x830)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OFFS                                           (0x830)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x)                                        ((x) + 0x834)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_PHYS(x)                                        ((x) + 0x834)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OFFS                                           (0x834)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x)                                       ((x) + 0x838)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_PHYS(x)                                       ((x) + 0x838)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OFFS                                          (0x838)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR                                           0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ATTR                                                       0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_SHFT                                               0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x)                                         ((x) + 0x83c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_PHYS(x)                                         ((x) + 0x83c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OFFS                                            (0x83c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_RMSK                                            0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR                                             0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR_RMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ATTR                                                         0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_BMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_SHFT                                                 0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x)                                        ((x) + 0x840)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_PHYS(x)                                        ((x) + 0x840)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OFFS                                           (0x840)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x)                                        ((x) + 0x844)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_PHYS(x)                                        ((x) + 0x844)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OFFS                                           (0x844)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x)                                       ((x) + 0x848)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_PHYS(x)                                       ((x) + 0x848)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OFFS                                          (0x848)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR                                           0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ATTR                                                       0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_SHFT                                               0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x)                                         ((x) + 0x84c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_PHYS(x)                                         ((x) + 0x84c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OFFS                                            (0x84c)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_RMSK                                            0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR                                             0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR_RMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ATTR                                                         0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_BMSK                                        0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_SHFT                                                 0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x)                                        ((x) + 0x850)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_PHYS(x)                                        ((x) + 0x850)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OFFS                                           (0x850)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x)                                        ((x) + 0x854)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_PHYS(x)                                        ((x) + 0x854)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OFFS                                           (0x854)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR                                            0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ATTR                                                        0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_BMSK                                       0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_SHFT                                                0
+
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x)                                       ((x) + 0x858)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_PHYS(x)                                       ((x) + 0x858)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OFFS                                          (0x858)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR                                           0x00000000
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ATTR                                                       0x3
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x)            \
+                in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x), m)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),v)
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x))
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_SHFT                                               0
+
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x)                                                      ((x) + 0x85c)
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_PHYS(x)                                                      ((x) + 0x85c)
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OFFS                                                         (0x85c)
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_RMSK                                                               0x3f
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR                                                          0x00000000
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ATTR                                                                      0x3
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x)            \
+                in_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x))
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x), m)
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),v)
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),m,v,HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x))
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_BMSK                                                     0x20
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_SHFT                                                        5
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_BMSK                                           0x10
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_SHFT                                              4
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_BMSK                                                 0x8
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_SHFT                                                   3
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_BMSK                                         0x4
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_SHFT                                           2
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_BMSK                                          0x2
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_SHFT                                            1
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_BMSK                                                0x1
+#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_SHFT                                                  0
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_BMSK                                                         0x1000
+#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_SHFT                                                             12
+#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_BMSK                                                          0x800
+#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_SHFT                                                             11
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_BMSK                                                 0x1000
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_SHFT                                                     12
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_BMSK                                               0x800
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_SHFT                                                  11
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_BMSK                                                      0x400
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_SHFT                                                         10
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_BMSK                                                     0x200
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_SHFT                                                         9
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK                                                        0x40
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT                                                           6
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK                                                    0x20
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT                                                       5
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_BMSK                                                      0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_SHFT                                                        1
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_BMSK                                                             0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_SHFT                                                               0
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x)                                                           ((x) + 0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS                                                              (0x868)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK                                                                     0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR                                                               0x00000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK                                                          0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR                                                                           0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)            \
+                in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK                                                        0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT                                                          1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK                                                        0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT                                                          0
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_BMSK                                                  0x80
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_SHFT                                                     7
+#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS                                                                   (0x8bc)
+#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK                                                                          0x7
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                           0x4
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                             2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                           0x2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                             1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x)                                                      ((x) + 0x8c0)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_PHYS(x)                                                      ((x) + 0x8c0)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OFFS                                                         (0x8c0)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x))
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x))
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_BMSK                                               0xffffffff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x)                                                      ((x) + 0x8c4)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_PHYS(x)                                                      ((x) + 0x8c4)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OFFS                                                         (0x8c4)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_RMSK                                                               0xff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x))
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x))
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x8c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0x8cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK                                                0xfffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                                                            ((x) + 0x8d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                                                          ((x) + 0x8d8)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                                                   ((x) + 0x8e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                                                   ((x) + 0x8e8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                        ((x) + 0x8f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                         16
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                       0x7fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                            0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                        ((x) + 0x8fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                 0xffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                      0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0x910)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0x914)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0x918)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0x940)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0xb20)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_PHYS(x)                                                      ((x) + 0xb20)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OFFS                                                         (0xb20)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0xb24)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_PHYS(x)                                                      ((x) + 0xb24)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OFFS                                                         (0xb24)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RMSK                                                          0xfffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_BMSK                                                0xfffff00
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x)                                                            ((x) + 0xb28)
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_PHYS(x)                                                            ((x) + 0xb28)
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_OFFS                                                               (0xb28)
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_RMSK                                                                     0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR                                                                0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_ATTR                                                                            0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x)                                                        ((x) + 0xb2c)
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_PHYS(x)                                                        ((x) + 0xb2c)
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_OFFS                                                           (0xb2c)
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR                                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR_RMSK                                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ATTR                                                                        0x1
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                           0xffff0000
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                   16
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_BMSK                                               0xffff
+#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_SHFT                                                    0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x)                                                          ((x) + 0xb30)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_PHYS(x)                                                          ((x) + 0xb30)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OFFS                                                             (0xb30)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RMSK                                                               0x7fffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR                                                              0x00000080
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ATTR                                                                          0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_BMSK                                                 0x3fc000
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_SHFT                                                       14
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_BMSK                                                  0x3000
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_SHFT                                                      12
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_BMSK                                                   0xf00
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_SHFT                                                       8
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_BMSK                                                      0x80
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_SHFT                                                         7
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_BMSK                                                       0x40
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_SHFT                                                          6
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_BMSK                                                       0x4
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_SHFT                                                         2
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x)                                                   ((x) + 0xb3c)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_PHYS(x)                                                   ((x) + 0xb3c)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OFFS                                                      (0xb3c)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_RMSK                                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR                                                       0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ATTR                                                                   0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                 0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                          0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x)                                                   ((x) + 0xb40)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_PHYS(x)                                                   ((x) + 0xb40)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OFFS                                                      (0xb40)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_RMSK                                                            0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR                                                       0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ATTR                                                                   0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                       0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                          0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                        ((x) + 0xb50)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                        ((x) + 0xb50)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OFFS                                           (0xb50)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                 0xffff0000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                         16
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                             0x8000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                 15
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                       0x7fff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                            0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                        ((x) + 0xb54)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                        ((x) + 0xb54)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OFFS                                           (0xb54)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_RMSK                                               0xffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                 0xffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                      0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x)                                           ((x) + 0xb58)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_PHYS(x)                                           ((x) + 0xb58)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_OFFS                                              (0xb58)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_RMSK                                              0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR                                               0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ATTR                                                           0x1
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                0xffff0000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                        16
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                           0x8000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                               15
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                     0x7fff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                          0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                        ((x) + 0xb5c)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                        ((x) + 0xb5c)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OFFS                                           (0xb5c)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                0x3ff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                             0x3ff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                 0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                       ((x) + 0xb60)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                       ((x) + 0xb60)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OFFS                                          (0xb60)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                 0x7
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR                                           0x00000003
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                       0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                            0x7
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                              0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                      ((x) + 0xb64)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                      ((x) + 0xb64)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_OFFS                                         (0xb64)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_RMSK                                          0xfffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                      0x1
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                           0xff00000
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                  20
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                          0xfffff
+#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0xb68)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_PHYS(x)                                                 ((x) + 0xb68)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OFFS                                                    (0xb68)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_RMSK                                                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR                                                     0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR_RMSK                                                0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ATTR                                                                 0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_BMSK                                               0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0xb6c)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_PHYS(x)                                                 ((x) + 0xb6c)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OFFS                                                    (0xb6c)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_RMSK                                                         0x1ff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR                                                     0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR_RMSK                                                0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ATTR                                                                 0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0xb70)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_PHYS(x)                                                     ((x) + 0xb70)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OFFS                                                        (0xb70)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_RMSK                                                        0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR                                                         0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR_RMSK                                                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ATTR                                                                     0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_BMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_SHFT                                                           0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x)                                               ((x) + 0xb90)
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_PHYS(x)                                               ((x) + 0xb90)
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OFFS                                                  (0xb90)
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_RMSK                                                      0xffff
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR                                                   0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR_RMSK                                              0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ATTR                                                               0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                   0xffff
+#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                        0
+
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x)                                                        ((x) + 0xb94)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_PHYS(x)                                                        ((x) + 0xb94)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OFFS                                                           (0xb94)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_RMSK                                                           0xffff003f
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR                                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR_RMSK                                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ATTR                                                                        0x3
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x))
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                  0xffff0000
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                          16
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                         0x3f
+#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                            0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x)                                                      ((x) + 0xb98)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_PHYS(x)                                                      ((x) + 0xb98)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OFFS                                                         (0xb98)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x)                                                      ((x) + 0xb9c)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_PHYS(x)                                                      ((x) + 0xb9c)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OFFS                                                         (0xb9c)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RMSK                                                          0xfffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR                                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR_RMSK                                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ATTR                                                                      0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_BMSK                                                0xfffff00
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_SHFT                                                        8
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                            0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                               0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x)                                                            ((x) + 0xba0)
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_PHYS(x)                                                            ((x) + 0xba0)
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_OFFS                                                               (0xba0)
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_RMSK                                                                     0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR                                                                0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_ATTR                                                                            0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x)                                                        ((x) + 0xba4)
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_PHYS(x)                                                        ((x) + 0xba4)
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_OFFS                                                           (0xba4)
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_RMSK                                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR                                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR_RMSK                                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ATTR                                                                        0x1
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_BMSK                                           0xffff0000
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_SHFT                                                   16
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_BMSK                                               0xffff
+#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_SHFT                                                    0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x)                                                          ((x) + 0xba8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_PHYS(x)                                                          ((x) + 0xba8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OFFS                                                             (0xba8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RMSK                                                               0x7fffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR                                                              0x00000080
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ATTR                                                                          0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_BMSK                                                 0x3fc000
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_SHFT                                                       14
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_BMSK                                                  0x3000
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_SHFT                                                      12
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_BMSK                                                   0xf00
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_SHFT                                                       8
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_BMSK                                                      0x80
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_SHFT                                                         7
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_BMSK                                                       0x40
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_SHFT                                                          6
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                 0x20
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                    5
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                  0x10
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                     4
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_BMSK                                                       0x8
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_SHFT                                                         3
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_BMSK                                                       0x4
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_SHFT                                                         2
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_BMSK                                                    0x2
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_SHFT                                                      1
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_BMSK                                                    0x1
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_SHFT                                                      0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x)                                                   ((x) + 0xbb4)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_PHYS(x)                                                   ((x) + 0xbb4)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OFFS                                                      (0xbb4)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_RMSK                                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR                                                       0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ATTR                                                                   0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK                                 0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT                                          0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x)                                                   ((x) + 0xbb8)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_PHYS(x)                                                   ((x) + 0xbb8)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OFFS                                                      (0xbb8)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_RMSK                                                            0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR                                                       0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR_RMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ATTR                                                                   0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK                                       0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT                                          0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                        ((x) + 0xbc8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)                                        ((x) + 0xbc8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OFFS                                           (0xbc8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                 0xffff0000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                         16
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK                             0x8000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT                                 15
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                       0x7fff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                            0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                        ((x) + 0xbcc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)                                        ((x) + 0xbcc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OFFS                                           (0xbcc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_RMSK                                               0xffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                 0xffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                      0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x)                                           ((x) + 0xbd0)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_PHYS(x)                                           ((x) + 0xbd0)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_OFFS                                              (0xbd0)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_RMSK                                              0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR                                               0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ATTR                                                           0x1
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK                0xffff0000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                        16
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK                           0x8000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT                               15
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK                     0x7fff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                          0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)                                        ((x) + 0xbd4)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)                                        ((x) + 0xbd4)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OFFS                                           (0xbd4)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RMSK                                                0x3ff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ATTR                                                        0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK                             0x3ff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT                                 0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)                                       ((x) + 0xbd8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)                                       ((x) + 0xbd8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OFFS                                          (0xbd8)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_RMSK                                                 0x7
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR                                           0x00000003
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ATTR                                                       0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK                                            0x7
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT                                              0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)                                      ((x) + 0xbdc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)                                      ((x) + 0xbdc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_OFFS                                         (0xbdc)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_RMSK                                          0xfffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR                                          0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK                                     0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ATTR                                                      0x1
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK                           0xff00000
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT                                  20
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK                          0xfffff
+#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT                                0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x)                                                 ((x) + 0xbe0)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_PHYS(x)                                                 ((x) + 0xbe0)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OFFS                                                    (0xbe0)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_RMSK                                                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR                                                     0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR_RMSK                                                0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ATTR                                                                 0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_BMSK                                               0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x)                                                 ((x) + 0xbe4)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_PHYS(x)                                                 ((x) + 0xbe4)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OFFS                                                    (0xbe4)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_RMSK                                                         0x1ff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR                                                     0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR_RMSK                                                0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ATTR                                                                 0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                             0x100
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                 8
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_BMSK                                                     0xff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_SHFT                                                        0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x)                                                     ((x) + 0xbe8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_PHYS(x)                                                     ((x) + 0xbe8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OFFS                                                        (0xbe8)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_RMSK                                                        0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR                                                         0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR_RMSK                                                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ATTR                                                                     0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_BMSK                                                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_SHFT                                                           0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x)                                               ((x) + 0xc08)
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_PHYS(x)                                               ((x) + 0xc08)
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OFFS                                                  (0xc08)
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_RMSK                                                      0xffff
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR                                                   0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR_RMSK                                              0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ATTR                                                               0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK                                   0xffff
+#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT                                        0
+
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x)                                                        ((x) + 0xc0c)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_PHYS(x)                                                        ((x) + 0xc0c)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OFFS                                                           (0xc0c)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_RMSK                                                           0xffff003f
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR                                                            0x00000000
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR_RMSK                                                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ATTR                                                                        0x3
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x)            \
+                in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x), m)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),v)
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x))
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                  0xffff0000
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                          16
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                         0x3f
+#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                            0
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x400000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                    22
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_BMSK                                              0xf0000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_SHFT                                                      28
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                             0x8000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                    27
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_BMSK                                               0xf0000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_SHFT                                                       28
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                              (0xd78)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                          (0xd7c)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                           ((x) + 0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                              (0xd80)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                               0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                          0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                           0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                   0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                         13
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                     0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                         12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                   0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                      10
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                   0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                       6
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                    0x30
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                       4
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                     0xf
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                       0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                       ((x) + 0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                          (0xd84)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                            0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                           0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                      0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                       0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                       12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                        0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                            0
+
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                              0x7f
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                   0x40
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                      6
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                   0x20
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                      5
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_BMSK                                                     0x1c0000
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_SHFT                                                           18
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_BMSK                                                      0x38000
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_SHFT                                                           15
+#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK                                                    0x1c00
+#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT                                                        10
+
+#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_BMSK                                                     0x4000000
+#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_SHFT                                                            26
+#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK                                            0x2000000
+#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT                                                   25
+#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK                                                    0x1000000
+#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT                                                           24
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                                  0x10000
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                       16
+#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_BMSK                                                          0x1000
+#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_SHFT                                                              12
+#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_BMSK                                                           0x800
+#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_SHFT                                                              11
+#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_BMSK                                                                0x4
+#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_SHFT                                                                  2
+#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_BMSK                                                               0x2
+#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_SHFT                                                                 1
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_BMSK                                                0x1c0000
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_SHFT                                                      18
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_BMSK                                                 0x38000
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_SHFT                                                      15
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK                                               0x1c00
+#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT                                                   10
+
+#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_BMSK                                                0x4000000
+#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_SHFT                                                       26
+#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK                                       0x2000000
+#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT                                              25
+#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK                                               0x1000000
+#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT                                                      24
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                             0x10000
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                  16
+#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_BMSK                                                     0x1000
+#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_SHFT                                                         12
+#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_BMSK                                                      0x800
+#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_SHFT                                                         11
+#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_BMSK                                                           0x4
+#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_SHFT                                                             2
+#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_BMSK                                                          0x2
+#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_SHFT                                                            1
+#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_BMSK                                                0x40
+#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_SHFT                                                   6
+#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_BMSK                                                0x20
+#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_SHFT                                                   5
+#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x)                                                               ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS                                                                  (0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK                                                                       0x1ff
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR                                                                   0x00000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK                                                              0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR                                                                               0x3
+#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                                  0x100
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                                      8
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK                                                           0xc0
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT                                                              6
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK                                                        0x3f
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT                                                           0
+
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                     ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                          (0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK                                                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn                                                                    511
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR                                                              0x00000000
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR                                                                          0x1
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                        0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                 0
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                                                            ((x) + 0x2000)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                                                            ((x) + 0x2004)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                                                            ((x) + 0x2008)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x)                                                            ((x) + 0x2028)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_PHYS(x)                                                            ((x) + 0x2028)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_OFFS                                                               (0x2028)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_RMSK                                                                  0xfffff
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR                                                                0x00000000
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_ATTR                                                                            0x3
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x)            \
+                in_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x))
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x), m)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),v)
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x))
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_BMSK                                                         0xfffff
+#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_SHFT                                                               0
+
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x)                                                            ((x) + 0x202c)
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_PHYS(x)                                                            ((x) + 0x202c)
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_OFFS                                                               (0x202c)
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_RMSK                                                                  0xfffff
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR                                                                0x00000000
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_ATTR                                                                            0x3
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x)            \
+                in_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x))
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x), m)
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),v)
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x))
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_BMSK                                                         0xfffff
+#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_SHFT                                                               0
+
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x)                                                            ((x) + 0x2030)
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_PHYS(x)                                                            ((x) + 0x2030)
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_OFFS                                                               (0x2030)
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_RMSK                                                                  0xfffff
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR                                                                0x00000000
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_ATTR                                                                            0x3
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x)            \
+                in_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x))
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x), m)
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUT(x, v)            \
+                out_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),v)
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x))
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_BMSK                                                         0xfffff
+#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_SHFT                                                               0
+
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x)                                                            ((x) + 0x2034)
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_PHYS(x)                                                            ((x) + 0x2034)
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_OFFS                                                               (0x2034)
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_RMSK                                                                  0xfffff
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR                                                                0x00000000
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR_RMSK                                                           0xffffffff
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_ATTR                                                                            0x3
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x)            \
+                in_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x))
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x), m)
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUT(x, v)            \
+                out_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),v)
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x))
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_BMSK                                                         0xfffff
+#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_SHFT                                                               0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_BMSK                                           0x10000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_SHFT                                                16
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_BMSK                                            0x8000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_SHFT                                                15
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_BMSK                                            0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_SHFT                                                14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_BMSK                                            0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_SHFT                                                13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_BMSK                                            0x1000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_SHFT                                                12
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_BMSK                                             0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_SHFT                                                11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_BMSK                                             0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_SHFT                                                10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_BMSK                                              0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_SHFT                                                  9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_BMSK                                              0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_SHFT                                                  8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_BMSK                                               0x80
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_SHFT                                                  7
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_BMSK                                               0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_SHFT                                                  6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_BMSK                                               0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_SHFT                                                  5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_BMSK                                               0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_SHFT                                                  4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_BMSK                                                0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_SHFT                                                  3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_BMSK                                                0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_SHFT                                                  2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_BMSK                                                0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_SHFT                                                  1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_BMSK                                                0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_SHFT                                                  0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_BMSK                                       0x10000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_SHFT                                            16
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_BMSK                                        0x8000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_SHFT                                            15
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_BMSK                                        0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_SHFT                                            14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_BMSK                                        0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_SHFT                                            13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_BMSK                                        0x1000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_SHFT                                            12
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_BMSK                                         0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_SHFT                                            11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_BMSK                                         0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_SHFT                                            10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_BMSK                                          0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_SHFT                                              9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_BMSK                                          0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_SHFT                                              8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_BMSK                                           0x80
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_SHFT                                              7
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_BMSK                                           0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_SHFT                                              6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_BMSK                                           0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_SHFT                                              5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK                                           0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT                                              4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK                                            0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT                                              3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK                                            0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT                                              2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK                                            0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT                                              1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK                                            0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT                                              0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK                                           0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT                                               14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK                                           0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT                                               13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK                                            0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT                                               11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK                                            0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT                                               10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK                                             0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT                                                 9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK                                             0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT                                                 8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK                                              0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT                                                 6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK                                              0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT                                                 5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK                                              0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT                                                 4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_BMSK                                               0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_SHFT                                                 3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK                                               0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT                                                 2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK                                               0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT                                                 1
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_BMSK                                           0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_SHFT                                               14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_BMSK                                           0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_SHFT                                               13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_BMSK                                            0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_SHFT                                               11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_BMSK                                            0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_SHFT                                               10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_BMSK                                             0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_SHFT                                                 9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_BMSK                                             0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_SHFT                                                 8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_BMSK                                              0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_SHFT                                                 6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_BMSK                                              0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_SHFT                                                 5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_BMSK                                              0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_SHFT                                                 4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_BMSK                                               0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_SHFT                                                 3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_BMSK                                               0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_SHFT                                                 2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_BMSK                                               0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_SHFT                                                 1
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK                                        0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT                                            14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK                                        0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT                                            13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK                                         0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT                                            11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK                                         0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT                                            10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK                                          0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT                                              9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK                                          0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT                                              8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK                                           0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT                                              6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK                                           0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT                                              5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK                                           0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT                                              4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_BMSK                                            0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_SHFT                                              3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK                                            0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT                                              2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK                                            0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT                                              1
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_BMSK                                              0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_SHFT                                                  14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_BMSK                                              0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_SHFT                                                  13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_BMSK                                               0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_SHFT                                                  11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_BMSK                                               0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_SHFT                                                  10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_BMSK                                                0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_SHFT                                                    9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_BMSK                                                0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_SHFT                                                    8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_BMSK                                                 0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_SHFT                                                    6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_BMSK                                                 0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_SHFT                                                    5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_BMSK                                                 0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_SHFT                                                    4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_BMSK                                                  0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_SHFT                                                    3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_BMSK                                                  0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_SHFT                                                    2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_BMSK                                                  0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_SHFT                                                    1
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_BMSK                                               0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_SHFT                                                  4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_BMSK                                                0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_SHFT                                                  3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_BMSK                                                0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_SHFT                                                  2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_BMSK                                                0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_SHFT                                                  1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_BMSK                                                0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_SHFT                                                  0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK                                           0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT                                              4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK                                            0x8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT                                              3
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK                                            0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT                                              2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK                                            0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT                                              1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK                                            0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT                                              0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_BMSK                                         0x800000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_SHFT                                               23
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_BMSK                                         0x400000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_SHFT                                               22
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_BMSK                                         0x200000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_SHFT                                               21
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_BMSK                                         0x100000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_SHFT                                               20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_BMSK                                          0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_SHFT                                               19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_BMSK                                          0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_SHFT                                               18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_BMSK                                          0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_SHFT                                               17
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_BMSK                                          0x10000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_SHFT                                               16
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_BMSK                                           0x8000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_SHFT                                               15
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK                                           0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT                                               14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK                                           0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT                                               13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_BMSK                                           0x1000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_SHFT                                               12
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK                                            0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT                                               11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK                                            0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT                                               10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK                                             0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT                                                 9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK                                             0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT                                                 8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_BMSK                                              0x80
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_SHFT                                                 7
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK                                              0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT                                                 6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK                                              0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT                                                 5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK                                              0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT                                                 4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK                                               0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT                                                 2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK                                               0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT                                                 1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_BMSK                                               0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_SHFT                                                 0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_BMSK                                         0x800000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_SHFT                                               23
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_BMSK                                         0x400000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_SHFT                                               22
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_BMSK                                         0x200000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_SHFT                                               21
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_BMSK                                         0x100000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_SHFT                                               20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_BMSK                                          0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_SHFT                                               19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_BMSK                                          0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_SHFT                                               18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_BMSK                                          0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_SHFT                                               17
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_BMSK                                          0x10000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_SHFT                                               16
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_BMSK                                           0x8000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_SHFT                                               15
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_BMSK                                           0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_SHFT                                               14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_BMSK                                           0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_SHFT                                               13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_BMSK                                           0x1000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_SHFT                                               12
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_BMSK                                            0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_SHFT                                               11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_BMSK                                            0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_SHFT                                               10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_BMSK                                             0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_SHFT                                                 9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_BMSK                                             0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_SHFT                                                 8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_BMSK                                              0x80
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_SHFT                                                 7
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_BMSK                                              0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_SHFT                                                 6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_BMSK                                              0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_SHFT                                                 5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_BMSK                                              0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_SHFT                                                 4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_BMSK                                               0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_SHFT                                                 2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_BMSK                                               0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_SHFT                                                 1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_BMSK                                               0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_SHFT                                                 0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_BMSK                                      0x800000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_SHFT                                            23
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_BMSK                                      0x400000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_SHFT                                            22
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_BMSK                                      0x200000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_SHFT                                            21
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_BMSK                                      0x100000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_SHFT                                            20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_BMSK                                       0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_SHFT                                            19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_BMSK                                       0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_SHFT                                            18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_BMSK                                       0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_SHFT                                            17
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_BMSK                                       0x10000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_SHFT                                            16
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_BMSK                                        0x8000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_SHFT                                            15
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK                                        0x4000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT                                            14
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK                                        0x2000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT                                            13
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_BMSK                                        0x1000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_SHFT                                            12
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK                                         0x800
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT                                            11
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK                                         0x400
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT                                            10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK                                          0x200
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT                                              9
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK                                          0x100
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT                                              8
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_BMSK                                           0x80
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_SHFT                                              7
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK                                           0x40
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT                                              6
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK                                           0x20
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT                                              5
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK                                           0x10
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT                                              4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK                                            0x4
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT                                              2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK                                            0x2
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT                                              1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_BMSK                                            0x1
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_SHFT                                              0
+
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_BMSK                                             0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_SHFT                                                  19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_BMSK                                             0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_SHFT                                                  18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_BMSK                                             0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_SHFT                                                  17
+
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                               0x1000000
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                      24
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x)                                                                    ((x) + 0x4400)
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_PHYS(x)                                                                    ((x) + 0x4400)
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_OFFS                                                                       (0x4400)
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_RMSK                                                                         0xffffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR                                                                        0x0020e93b
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ATTR                                                                                    0x1
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_BMSK                                                              0xff0000
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_SHFT                                                                    16
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_BMSK                                                                0xffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_SHFT                                                                     0
+
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x)                                                                   ((x) + 0x4404)
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_PHYS(x)                                                                   ((x) + 0x4404)
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_OFFS                                                                      (0x4404)
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_RMSK                                                                      0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR                                                                       0xb51bbb75
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR_RMSK                                                                  0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ATTR                                                                                   0x1
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_BMSK                                                               0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_SHFT                                                                        0
+
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x)                                                                    ((x) + 0x4408)
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_PHYS(x)                                                                    ((x) + 0x4408)
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_OFFS                                                                       (0x4408)
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_RMSK                                                                              0x1
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR                                                                        0x00000000
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ATTR                                                                                    0x1
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_BMSK                                                                         0x1
+#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_SHFT                                                                           0
+
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x)                                                                    ((x) + 0x4410)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_PHYS(x)                                                                    ((x) + 0x4410)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_OFFS                                                                       (0x4410)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_RMSK                                                                       0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR                                                                        0xdeadbeef
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ATTR                                                                                    0x1
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_BMSK                                                              0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_SHFT                                                                       0
+
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x)                                                                   ((x) + 0x4414)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_PHYS(x)                                                                   ((x) + 0x4414)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_OFFS                                                                      (0x4414)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_RMSK                                                                      0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR                                                                       0xdeadbeef
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR_RMSK                                                                  0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ATTR                                                                                   0x1
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_BMSK                                                             0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_SHFT                                                                      0
+
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x)                                                             ((x) + 0x4418)
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_PHYS(x)                                                             ((x) + 0x4418)
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_OFFS                                                                (0x4418)
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_RMSK                                                                    0xffff
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR                                                                 0x000000dd
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR_RMSK                                                            0xffffffff
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ATTR                                                                             0x1
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_IN(x)            \
+                in_dword(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x))
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x), m)
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_BMSK                                                        0xffff
+#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_SHFT                                                             0
+
+#endif
diff --git a/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h b/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
new file mode 100644
index 000000000000..072ec2ed4af7
--- /dev/null
+++ b/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H
+#define WCSS_SEQ_HWIOREG_WIFI_TOP_H
+
+#include "wcss_seq_hwiobase.h"
+
+#define WFSS_PMM_REG_BASE                                                                                            (WFSS_PMM_BASE      + 0x00000000)
+
+#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x)                                                            ((x) + 0x164)
+
+#endif
diff --git a/hw/wcn8750/v1/wcss_version.h b/hw/wcn8750/v1/wcss_version.h
new file mode 100644
index 000000000000..cbfded86e5a4
--- /dev/null
+++ b/hw/wcn8750/v1/wcss_version.h
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: ISC
+ */
+
+#define WCSS_VERSION	3150

From a93a0ebc2fcba3b6c6c95b448afb6d7558632575 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 26 Mar 2026 18:02:43 -0700
Subject: [PATCH 198/290] fw-api: CL 32045293 - update fw common interface
 files

Change-Id: I99b4d4de1f311438743136de4dabd118c4c7bc18
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  10 +++--
 fw/wmi_unified.h  | 104 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a5a94c79fea3..a5e7b230197e 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1612,6 +1612,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_iface_ipi_stats,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -3160,7 +3161,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR)
 /* NOTE:
  * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID
  * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and
@@ -6307,7 +6309,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params,  WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params,  WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID);
 
 /* WMI command for unified disconnect cmd */
@@ -6400,7 +6403,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID);
     /*---*/ \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, key_install_fixed_param, WMITLV_SIZE_FIX)\
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
 
 /* WMI command for unified SMD Config cmd */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f312fd43ee06..8dc8885037b2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -23576,6 +23576,10 @@ typedef struct {
  *         to be used.
  *     wmi_peer_assoc_smd_params peer_assoc_smd_params;
  *     wmi_uhr_rate_set peer_uhr_rates; <-- UHR capabilities of the peer
+ *     wmi_peer_uhr_npca_op_params npca_op_params[0,1]
+ *         Only present if NPCA enable is set in peer_uhr_ops &
+ *         NPCA support is set in peer_uhr_cap_mac of fixed_param.
+ *         Otherwise, array length should be 0.
  */
 } wmi_peer_assoc_complete_cmd_fixed_param;
 
@@ -23637,6 +23641,105 @@ typedef struct {
      */
 } wmi_peer_uhr_mode_update_cmd_fixed_param;
 
+
+/* npca_op_param macros */
+#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_GET(_var) \
+    WMI_GET_BITS(_var, 0, 4)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_SET(_var, _val) \
+    WMI_SET_BITS(_var, 0, 4, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_GET(_var) \
+    WMI_GET_BITS(_var, 4, 4)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_SET(_var, _val) \
+    WMI_SET_BITS(_var, 4, 4, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 8, 6)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 8, 6, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 14, 6)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 14, 6, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_GET(_var) \
+    WMI_GET_BITS(_var, 20, 2)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_SET(_var, _val) \
+    WMI_SET_BITS(_var, 20, 2, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_GET(_var) \
+    WMI_GET_BITS(_var, 22, 1)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_SET(_var, _val) \
+    WMI_SET_BITS(_var, 22, 1, _val)
+
+#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET(_var) \
+    WMI_GET_BITS(_var, 23, 1)
+#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_SET(_var, _val) \
+    WMI_SET_BITS(_var, 23, 1, _val)
+
+/* npca_op_param1 macros */
+#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_GET(_var) \
+    WMI_GET_BITS(_var, 0, 16)
+#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_SET(_var, _val) \
+    WMI_SET_BITS(_var, 0, 16, _val)
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params */
+    /*
+     * All below fields are advertised by UHR AP in UHR NPCA Op Param Field
+     * in UHR Operation IE
+     *
+     * Bit 0-3  : NPCA Primary Channel.
+     *            Indicates the channel number of a channel within BSS
+     *            bandwidth that both STA and AP switch to for NPCA operation.
+     *
+     * Bit 4-7  : NPCA Minimum Duration Threshold (NMDT).
+     *            FW to convert this value into microsecs using
+     *            512 + (NMDT * 128) usec.
+     *
+     * Bit 8-13 : NPCA Switch Delay, in units of 4 us.
+     *            The time needed by an NPCA AP to switch from the BSS
+     *            primary channel to the NPCA primary channel.
+     *
+     * Bit 14-19: NPCA Switch Back Delay, in units of 4 us.
+     *            The time needed by an NPCA AP to switch from the NPCA
+     *            primary channel to the BSS primary channel.
+     *
+     * Bit 20-21: Initial NPCA QSRC.
+     *            Indicates the value that is used to initialize the EDCAF
+     *            QSRC[AC] variables when an NPCA STA in the BSS switches
+     *            to NPCA operation.
+     *
+     * Bit 22   : MOPLEN NPCA.
+     *            Indicates which conditions can be used to initiate an
+     *            NPCA operation.
+     *            Value 1 means both PHYLEN and MOPLEN operations are
+     *            permitted in BSS.
+     *            Value 0 means only PHYLEN operation is allowed in the BSS.
+     *
+     * Bit 23   : NPCA Disabled Subchannel Bitmap Present
+     *
+     * Bit 24-31: Reserved
+     */
+    /* Use WMI_PEER_UHR_NPCA_OP_PARAM_ GET/SET macros for each field */
+    A_UINT32 npca_op_param;
+
+    /*
+     * Bit 0-15 : NPCA Disabled Subchannel Bitmap. Valid only when
+     *            WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET is
+     *            TRUE.
+     *            The bitmap indexes 20 MHz subchannels in ascending frequency
+     *            order, with the LSB representing the lowest frequency.
+     *            A bit set to 1 indicates the subchannel is punctured,
+     *            while 0 indicates it is not.
+     *
+     * Bit 16-31: Reserved
+     */
+    /* Use WMI_PEER_UHR_NPCA_OP_PARAM1_ GET/SET macros for each field */
+    A_UINT32 npca_op_param1;
+} wmi_peer_uhr_npca_op_params;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */
     A_UINT32 vdev_id;
@@ -55492,6 +55595,7 @@ typedef struct {
      *     wmi_vdev_install_key_cmd_fixed_param key_install_fixed_param;
      *     A_UINT8 key_data[];
      *     wmi_uhr_rate_set peer_uhr_rates[];
+     *     wmi_peer_uhr_npca_op_params npca_op_params[0,1]
      */
 } wmi_smd_roam_peer_unified_setup_cmd_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c35dbd4adf4e..abf09c736e9e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1736
+#define __WMI_REVISION_ 1737
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 3de1614ba1bc416d4e02bcabec3f6363b49ebf80 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 27 Mar 2026 18:01:49 -0700
Subject: [PATCH 199/290] fw-api: CL 32054464 - update fw common interface
 files

Change-Id: Ib1fe85715e7f7523177d6bf97b4246b7a6d6e524
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 10 ++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8dc8885037b2..a6a7e21d2b9d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -14778,6 +14778,16 @@ typedef struct {
      * Proxy mode AFC-Response payload clear count
      */
     A_UINT32 payload_clear_count;
+
+    /*
+     * Received payload count from HOST
+     */
+    A_UINT32 payload_received_count;
+
+    /*
+     * payload parsing failure count due to platform memory alloc failure
+     */
+    A_UINT32 payload_parser_mem_alloc_failure_count;
 } wmi_ctrl_path_afc_stats_struct;
 
 /* AT - Airtime */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index abf09c736e9e..1e5714a66b54 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1737
+#define __WMI_REVISION_ 1738
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 88ca7fa2f7978337883b7db3573f0d11f5b6ce3c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 27 Mar 2026 18:04:30 -0700
Subject: [PATCH 200/290] fw-api: CL 32059381 - update fw common interface
 files

Change-Id: I833da7ea4451b2d8df243e7856f5dd9d69aa0f60
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 185 ++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 174 insertions(+), 11 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 55af6f6757ce..7c3539b7d630 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -12746,8 +12746,66 @@ typedef struct {
                  is_e_ani_enabled:          1, /* bit 6 */
                  is_spur_mit_enabled:       1, /* bit 7 */
                  is_multigain_rssi_enabled: 1, /* bit 8 */
+                 is_olpc_clpc:              1, /* bit 9 */
+                 is_abi_en_dis:             1, /* bit 10 */
+                 is_str_sig_rec:            1, /* bit 11 */
+                 is_verbose_enabled:        1, /* bit 12 */
+                 is_dyn_ant_sel_supported:  1, /* bit 13 */
+                 is_dfs_punc_enabled:       1, /* bit 14 */
+                 is_ctl_blob_downloaded:    1, /* bit 15 */
+                 dpd_pow_bo_status:         1, /* bit 16 */
+                 is_eeprom_compressed:      1, /* bit 17 */
+                 is_ctl_table_loaded:       1, /* bit 18 */
+                 reserved: 13; /* bits 31:19 */
+        };
+    };
 
-                 reserved: 23; /* bits 31:9 */
+    union {
+        A_UINT32 rxsop_config;
+        struct {
+            A_UINT32
+                is_rxsop_enabled:    1, /* bit 0 */
+                rxsop_config_value:  8, /* bit 8:1 */
+                rxsop_reserved: 23; /* bits 31:9 */
+        };
+    };
+
+    A_INT32 reg_tx_pow_limit; /* dBm units */
+    A_INT32 user_pow_limit; /* dBm units */
+    A_UINT32 abi_max_rg_gain; /* dB units */
+    A_UINT32 abi_max_lg_gain; /* dB units */
+    A_UINT32 abi_max_vlg_gain; /* dB units */
+    /* abi_hold_mode:
+     * Controls how long gain table decisions are held:
+     *     0: Cleared each packet
+     *     1: Held for timer value
+     *     2: Gain table choices are under CSR control
+     */
+    A_UINT32 abi_hold_mode;
+    A_UINT32 abi_hold_count;
+    A_INT32 rssi_temp_offset; /* dB units */
+    A_INT32 rssi_xlna_bypass_offset; /* dB units */
+    A_INT32 rssi_cbw_offset; /* dB units */
+    A_INT32 rssi_chan_freq_offset; /* dB units */
+    A_UINT32 regdb_version;
+    A_UINT32 otp_version;
+    A_UINT32 cfr_clip_factor[4];
+    union {
+        A_UINT32 hc__premcs__pkt_type__word32;
+        struct {
+            A_UINT32
+                hc_premcs:   16, /* bits 15:0 */
+                hc_pkt_type: 16; /* bits 31:16 */
+        };
+    };
+    union {
+        A_UINT32 hc_nss_thr__is_rx_gain_forced__rx_gain_forced_val__word32;
+        struct {
+            A_UINT32
+                hc_nss_thr: 8,         /* bits 7:0 */
+                is_rx_gain_forced: 8,  /* bits 15:8 */
+                rx_gain_forced_val: 8, /* bits 23:16 */
+                reserved2: 8; /* bits 31:24 */
         };
     };
 } htt_stats_optional_configs_tlv;
@@ -12797,6 +12855,92 @@ typedef struct {
 #define HTT_STATS_OPT_CONF_SET_MULTIGAIN_RSSI(word, value) \
     ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8))
 
+#define HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) \
+    (((word) & 0x200) >> 9)
+#define HTT_STATS_OPT_CONF_SET_OLPC_CLPC(word, value) \
+    ((word) = ((word) & ~0x200) | (((value) & 0x1) << 9))
+
+#define HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) \
+    (((word) & 0x400) >> 10)
+#define HTT_STATS_OPT_CONF_SET_ABI_EN_DIS(word, value) \
+    ((word) = ((word) & ~0x400) | (((value) & 0x1) << 10))
+
+#define HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) \
+    (((word) & 0x800) >> 11)
+#define HTT_STATS_OPT_CONF_SET_STR_SIG_REC(word, value) \
+    ((word) = ((word) & ~0x800) | (((value) & 0x1) << 11))
+
+#define HTT_STATS_OPT_CONF_GET_VERBOSE(word) \
+    (((word) & 0x1000) >> 12)
+#define HTT_STATS_OPT_CONF_SET_VERBOSE(word, value) \
+    ((word) = ((word) & ~0x1000) | (((value) & 0x1) << 12))
+
+#define HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) \
+    (((word) & 0x2000) >> 13)
+#define HTT_STATS_OPT_CONF_SET_DYN_ANT_SEL(word, value) \
+    ((word) = ((word) & ~0x2000) | (((value) & 0x1) << 13))
+
+#define HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) \
+    (((word) & 0x4000) >> 14)
+#define HTT_STATS_OPT_CONF_SET_DFS_PUNC(word, value) \
+    ((word) = ((word) & ~0x4000) | (((value) & 0x1) << 14))
+
+#define HTT_STATS_OPT_CONF_GET_CTL_BLOB_DOWNLODED(word) \
+    (((word) & 0x8000) >> 15)
+#define HTT_STATS_OPT_CONF_SET_CTL_BLOB_DOWNLODED(word, value) \
+    ((word) = ((word) & ~0x8000) | (((value) & 0x1) << 15))
+
+#define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \
+    (((word) & 0x10000) >> 16)
+#define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \
+    ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16))
+
+#define HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) \
+    (((word) & 0x20000) >> 17)
+#define HTT_STATS_OPT_CONF_SET_EEPROM_COMPRESSED(word, value) \
+    ((word) = ((word) & ~0x20000) | (((value) & 0x1) << 17))
+
+#define HTT_STATS_OPT_CONF_GET_CTL_TABLE_LOADED(word) \
+    (((word) & 0x40000) >> 18)
+#define HTT_STATS_OPT_CONF_SET_CTL_TABLE_LOADED(word, value) \
+    ((word) = ((word) & ~0x40000) | (((value) & 0x1) << 18))
+
+
+#define HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) \
+    (((word) & 0x1) >> 0)
+#define HTT_STATS_OPT_CONF_SET_RXSOP_ENABLED(word, value) \
+    ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0))
+
+#define HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) \
+    (((word) & 0x1FE) >> 1)
+#define HTT_STATS_OPT_CONF_SET_RXSOP_CONFIG_VALUE(word, value) \
+    ((word) = ((word) & ~0x1FE) | (((value) & 0xFF) << 1))
+
+#define HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) \
+    ((word) & 0xFFFF)
+#define HTT_STATS_OPT_CONF_SET_HC_PREMCS(word, value) \
+    ((word) = ((value) & 0xFFFF))
+
+#define HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) \
+    (((word) & 0xFFFF0000) >> 16)
+#define HTT_STATS_OPT_CONF_SET_HC_PKT_TYPE(word, value) \
+    ((word) = ((word) & ~0xFFFF0000) | (((value) & 0xFFFF) << 16))
+
+#define HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) \
+    (((word) & 0x000000FF) >> 0)
+#define HTT_STATS_OPT_CONF_SET_HC_NSS_THR(word, value) \
+    ((word) = ((word) & ~0x000000FF) | (((value) & 0xFF) << 0))
+
+#define HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) \
+    (((word) & 0x0000FF00) >> 8)
+#define HTT_STATS_OPT_CONF_SET_IS_RX_GAIN_FORCED(word, value) \
+    ((word) = ((word) & ~0x0000FF00) | (((value) & 0xFF) << 8))
+
+#define HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) \
+    (((word) & 0x00FF0000) >> 16)
+#define HTT_STATS_OPT_CONF_SET_RX_GAIN_FORCED_VAL(word, value) \
+    ((word) = ((word) & ~0x00FF0000) | (((value) & 0xFF) << 16))
+
 
 /* FTM STATS */
 /* ================= dword_txparams ================= */
@@ -16176,12 +16320,19 @@ typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     union {
         struct {
-            A_UINT32 afc_local_rsvd : 8,
+            A_UINT32 afc_local_rsvd : 8, /* bits 7:0 */
                      /* enum WMI_AFC_FEATURE_6G_DEPLOYMENT_TYPE */
-                     deployment_type: 8,
+                     deployment_type: 8, /* bits 15:8 */
                      /* Bit 0 : LPI, Bit 1 : SP, Bit 2 : VLP, others: rsvd */
-                     power_mode_mask: 8,
-                     reserved       : 8;
+                     power_mode_mask: 8, /* bits 23:16 */
+                     /* Tx is suspended or not */
+                     is_tx_allowed_by_afc: 1, /* bit 24 */
+                     /* is_tx_allowed_by_hw_min_power_check:
+                      * channel is blocked or not due to the HW Minimum power
+                      * compliance check
+                      */
+                     is_tx_allowed_by_hw_min_power_check: 1, /* bit 25 */
+                     reserved: 6;
         };
         A_UINT32 afc_ini_params; /* AFC_INI_CONFIG */
     };
@@ -16209,19 +16360,30 @@ typedef struct {
 } htt_stats_reg_6g_tlv;
 
 #define HTT_STATS_REG_6G_GET_AFC_LOCAL_RSVD(word) \
-    HTT_STATS_GET_FIELD(0xFF, 0, (word))
+    HTT_STATS_GET_FIELD(0x000000FF, 0, (word))
 #define HTT_STATS_REG_6G_SET_AFC_LOCAL_RSVD(word,value) \
-    HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
+    HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) \
-    HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+    HTT_STATS_GET_FIELD(0x0000FF00, 8, (word))
 #define HTT_STATS_REG_6G_SET_DEPLOYMENT_TYPE(word,value) \
-    HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
+    HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) \
-    HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+    HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
 #define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \
-    HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_IS_TX_ALLOWED_BY_AFC(word) \
+    HTT_STATS_GET_FIELD(0x01000000, 24, (word))
+#define HTT_STATS_REG_6G_SET_IS_TX_ALLOWED_BY_AFC(word,value) \
+    HTT_STATS_SET_FIELD(0x01000000, 24, (word), (value))
+
+#define HTT_STATS_REG_6G_GET_IS_TX_ALLOWED_BY_HW_MIN_POWER_CHECK(word) \
+    HTT_STATS_GET_FIELD(0x02000000, 25, (word))
+#define HTT_STATS_REG_6G_SET_IS_TX_ALLOWED_BY_HW_MIN_POWER_CHECK(word,value) \
+    HTT_STATS_SET_FIELD(0x02000000, 25, (word), (value))
+
 
 #define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
@@ -16254,6 +16416,7 @@ typedef struct {
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 #define HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS 16
 
+
 typedef struct {
     union {
         struct {

From d408589140c91200e571f622395661f9fd735b9a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 1 Apr 2026 06:01:52 -0700
Subject: [PATCH 201/290] fw-api: CL 32083726 - update fw common interface
 files

Change-Id: I62fdbda20d7e4408e007e49941fed9f9df10a246
CRs-Fixed: 3830439
---
 fw/htt_ppdu_stats.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 2a10a2e45591..7f0fb14620de 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -501,6 +501,11 @@ enum HTT_PPDU_STATS_SEQ_TYPE {
     HTT_SEQTYPE_BE_UL_MU_OFDMA_TRIG = 13,
     HTT_SEQTYPE_BE_UL_MU_MIMO_TRIG  = 14,
     HTT_SEQTYPE_BE_UL_BSR_TRIG      = 15,
+    HTT_SEQTYPE_BN_MU_MIMO          = 16,
+    HTT_SEQTYPE_BN_MU_OFDMA         = 17,
+    HTT_SEQTYPE_BN_UL_MU_OFDMA_TRIG = 18,
+    HTT_SEQTYPE_BN_UL_MU_MIMO_TRIG  = 19,
+    HTT_SEQTYPE_BN_UL_BSR_TRIG      = 20,
 };
 typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE;
 

From 7783390a1d3d521850267129f6b677479d22d2b7 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 1 Apr 2026 18:01:49 -0700
Subject: [PATCH 202/290] fw-api: CL 32088692 - update fw common interface
 files

Change-Id: I6e6cee21002d87a05e561c51c1bc645a850dc622
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 15 ++++++++++++++-
 fw/wmi_version.h |  2 +-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a6a7e21d2b9d..ecf8eaa6fde2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -6112,6 +6112,7 @@ typedef enum {
     WMI_VENDOR1_REQ1_VERSION_4_20   = 7,
     WMI_VENDOR1_REQ1_VERSION_4_40   = 8,
     WMI_VENDOR1_REQ1_VERSION_4_50   = 9,
+    WMI_VENDOR1_REQ1_VERSION_4_60   = 10,
 } WMI_VENDOR1_REQ1_VERSION;
 
 typedef enum {
@@ -6120,6 +6121,7 @@ typedef enum {
     WMI_VENDOR1_REQ2_VERSION_3_20   = 2,
     WMI_VENDOR1_REQ2_VERSION_3_50   = 3,
     WMI_VENDOR1_REQ2_VERSION_3_61   = 4,
+    WMI_VENDOR1_REQ2_VERSION_3_70   = 5,
 } WMI_VENDOR1_REQ2_VERSION;
 
 typedef enum {
@@ -24297,7 +24299,7 @@ typedef struct {
     /** unique id identifying the VDEV, generated by the caller */
     A_UINT32 vdev_id;
     /** roam scan RSSI threshold */
-    A_UINT32 roam_scan_rssi_thresh;
+    A_UINT32 roam_scan_rssi_thresh; /* 2 GHz threshold */
     /** When using Hw generated beacon RSSI interrupts */
     A_UINT32 roam_rssi_thresh_diff;
     /** 5G scan max count */
@@ -24312,6 +24314,15 @@ typedef struct {
     A_INT32 rssi_thresh_offset_5g;
     /** flags for WMI_ROAM_SCAN_RSSI_THRESHOLD Command */
     A_UINT32 flags; /* see WMI_ROAM_SCAN_RSSI_THRESHOLD_FLAG defs */
+    /*
+     * If roam_scan_rssi_thresh_5ghz and roam_scan_rssi_thresh_6ghz are 0
+     * (due to the host not explicitly filling in values for these fields),
+     * the FW shall apply the roam_scan_rssi_thresh specification to the
+     * 5 GHz and 6 GHz bands, along with the 2.4 GHz band that the
+     * roam_scan_rssi_thresh specification is predominantly intended for.
+     */
+    A_UINT32 roam_scan_rssi_thresh_5ghz; /* 5 GHz threshold */
+    A_UINT32 roam_scan_rssi_thresh_6ghz; /* 6 GHz threshold */
     /* The TLVs will follow.
      * wmi_roam_scan_extended_threshold_param extended_param;
      * wmi_roam_earlystop_rssi_thres_param earlystop_param;
@@ -24495,6 +24506,8 @@ typedef struct {
 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NONE 0x1
 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_STATIC 0x2
 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_DYNAMIC 0x3
+/* Restrict RCL to Neighbor Report and BTM request channels only */
+#define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NEIGHBOR_REPORT 0x4
 
 #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_STATIC 0x1 /* Flush static roam scan channel list in FW */
 #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_DYNAMIC 0x2 /* Flush dynamic roam scan channel list in FW */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1e5714a66b54..4aff2c387c45 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1738
+#define __WMI_REVISION_ 1739
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 0e7b90003ba979f9d9175d8b67983d46484590ac Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 2 Apr 2026 18:01:55 -0700
Subject: [PATCH 203/290] fw-api: CL 32091641 - update fw common interface
 files

Change-Id: If3a1e56dd5d55ea984ceab8f746fe1ec54f7cdac
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 48 ++++++++----------------------------------------
 1 file changed, 8 insertions(+), 40 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 7c3539b7d630..6324a7b5c015 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -12752,11 +12752,9 @@ typedef struct {
                  is_verbose_enabled:        1, /* bit 12 */
                  is_dyn_ant_sel_supported:  1, /* bit 13 */
                  is_dfs_punc_enabled:       1, /* bit 14 */
-                 is_ctl_blob_downloaded:    1, /* bit 15 */
-                 dpd_pow_bo_status:         1, /* bit 16 */
-                 is_eeprom_compressed:      1, /* bit 17 */
-                 is_ctl_table_loaded:       1, /* bit 18 */
-                 reserved: 13; /* bits 31:19 */
+                 dpd_pow_bo_status:         1, /* bit 15 */
+                 is_eeprom_compressed:      1, /* bit 16 */
+                 reserved: 15; /* bits 31:17 */
         };
     };
 
@@ -12770,8 +12768,6 @@ typedef struct {
         };
     };
 
-    A_INT32 reg_tx_pow_limit; /* dBm units */
-    A_INT32 user_pow_limit; /* dBm units */
     A_UINT32 abi_max_rg_gain; /* dB units */
     A_UINT32 abi_max_lg_gain; /* dB units */
     A_UINT32 abi_max_vlg_gain; /* dB units */
@@ -12787,7 +12783,6 @@ typedef struct {
     A_INT32 rssi_xlna_bypass_offset; /* dB units */
     A_INT32 rssi_cbw_offset; /* dB units */
     A_INT32 rssi_chan_freq_offset; /* dB units */
-    A_UINT32 regdb_version;
     A_UINT32 otp_version;
     A_UINT32 cfr_clip_factor[4];
     union {
@@ -12885,25 +12880,15 @@ typedef struct {
 #define HTT_STATS_OPT_CONF_SET_DFS_PUNC(word, value) \
     ((word) = ((word) & ~0x4000) | (((value) & 0x1) << 14))
 
-#define HTT_STATS_OPT_CONF_GET_CTL_BLOB_DOWNLODED(word) \
+#define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \
     (((word) & 0x8000) >> 15)
-#define HTT_STATS_OPT_CONF_SET_CTL_BLOB_DOWNLODED(word, value) \
+#define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \
     ((word) = ((word) & ~0x8000) | (((value) & 0x1) << 15))
 
-#define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \
-    (((word) & 0x10000) >> 16)
-#define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \
-    ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16))
-
 #define HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) \
-    (((word) & 0x20000) >> 17)
+    (((word) & 0x10000) >> 16)
 #define HTT_STATS_OPT_CONF_SET_EEPROM_COMPRESSED(word, value) \
-    ((word) = ((word) & ~0x20000) | (((value) & 0x1) << 17))
-
-#define HTT_STATS_OPT_CONF_GET_CTL_TABLE_LOADED(word) \
-    (((word) & 0x40000) >> 18)
-#define HTT_STATS_OPT_CONF_SET_CTL_TABLE_LOADED(word, value) \
-    ((word) = ((word) & ~0x40000) | (((value) & 0x1) << 18))
+    ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16))
 
 
 #define HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) \
@@ -16325,14 +16310,7 @@ typedef struct {
                      deployment_type: 8, /* bits 15:8 */
                      /* Bit 0 : LPI, Bit 1 : SP, Bit 2 : VLP, others: rsvd */
                      power_mode_mask: 8, /* bits 23:16 */
-                     /* Tx is suspended or not */
-                     is_tx_allowed_by_afc: 1, /* bit 24 */
-                     /* is_tx_allowed_by_hw_min_power_check:
-                      * channel is blocked or not due to the HW Minimum power
-                      * compliance check
-                      */
-                     is_tx_allowed_by_hw_min_power_check: 1, /* bit 25 */
-                     reserved: 6;
+                     reserved: 8;
         };
         A_UINT32 afc_ini_params; /* AFC_INI_CONFIG */
     };
@@ -16374,16 +16352,6 @@ typedef struct {
 #define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \
     HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
 
-#define HTT_STATS_REG_6G_GET_IS_TX_ALLOWED_BY_AFC(word) \
-    HTT_STATS_GET_FIELD(0x01000000, 24, (word))
-#define HTT_STATS_REG_6G_SET_IS_TX_ALLOWED_BY_AFC(word,value) \
-    HTT_STATS_SET_FIELD(0x01000000, 24, (word), (value))
-
-#define HTT_STATS_REG_6G_GET_IS_TX_ALLOWED_BY_HW_MIN_POWER_CHECK(word) \
-    HTT_STATS_GET_FIELD(0x02000000, 25, (word))
-#define HTT_STATS_REG_6G_SET_IS_TX_ALLOWED_BY_HW_MIN_POWER_CHECK(word,value) \
-    HTT_STATS_SET_FIELD(0x02000000, 25, (word), (value))
-
 
 #define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))

From 5c7d89991628f92dc46bc14130d0eefee0af20e3 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 3 Apr 2026 18:01:58 -0700
Subject: [PATCH 204/290] fw-api: CL 32115955 - update fw common interface
 files

Change-Id: I49e43f4c68bb378eb26cf16f8b463c3be625feba
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 15 +++++++--------
 fw/wmi_version.h |  2 +-
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ecf8eaa6fde2..f2d05d577272 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -18061,7 +18061,13 @@ typedef struct {
     A_UINT32 vdev_stats_id;
     /** cfp_enable: indicate whether control frame protection is enabled */
     A_UINT32 cfp_enable;
-
+    /*
+     * VDEV ID that will be assigned for both legacy and MLD VAPs.
+     * This will be configured to rx_meta_data in the AST entry.
+     * This information will then be used by host to achieve intra-bss
+     * forwarding for the Rx packets.
+     */
+    A_UINT32 global_vdev_id;
 
 /* This TLV is followed by another TLV of array of structures
  *   wmi_vdev_txrx_streams cfg_txrx_streams[];
@@ -19197,13 +19203,6 @@ typedef struct {
     A_UINT32 vdev_op_ul_nss; /* vdev operating uplink nss. 1 ~ n: 1ss ~ nss */
     A_UINT32 vdev_op_dl_nss; /* vdev operating downlink nss. 1 ~ n: 1ss ~ nss */
     A_UINT32 uhr_ops; /* refer to WMI_UHR_OPS_XXX macros */
-    /*
-     * VDEV ID that will be assigned for both legacy and MLD VAPs.
-     * This will be configured to rx_meta_data in the AST entry.
-     * This information will then be used by host to achieve intra-bss
-     * forwarding for the Rx packets.
-     */
-    A_UINT32 global_vdev_id;
 
 /* The TLVs follows this structure:
  *     wmi_channel chan; <-- WMI channel
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4aff2c387c45..0943d428fd59 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1739
+#define __WMI_REVISION_ 1740
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 78e07c9a0196ccbf5d3dfbf008414455834e4d03 Mon Sep 17 00:00:00 2001
From: Abinandhu M <abinmano@qti.qualcomm.com>
Date: Tue, 10 Mar 2026 17:11:27 +0530
Subject: [PATCH 205/290] qcacld-3.0: Use orig_key_mgmt vdev param for AKM
 negotiation

Currently, the driver overwrites the supplicant
configured connect request AKMs with that of the
candidate's AKM. Due to this, the STA attempts
connection via an AKM which is not present in the
original connect request.

To fix this, use the intersection of original AKM
list and the candidate supported AKMs to derive the
connection AKM.

Change-Id: I700630fda91b4b3ff73e50a38e3c0386ede85e42
CRs-Fixed: 4490428
---
 core/sme/src/csr/csr_util.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/core/sme/src/csr/csr_util.c b/core/sme/src/csr/csr_util.c
index ecd857bcd604..a0ffa150b281 100644
--- a/core/sme/src/csr/csr_util.c
+++ b/core/sme/src/csr/csr_util.c
@@ -2454,7 +2454,7 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev,
 	int32_t ap_akm = 0;
 	uint8_t i;
 
-	neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_KEY_MGMT);
+	neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_ORIG_KEY_MGMT);
 	if (neg_akm < 0) {
 		sme_err("Invalid AKM suite");
 		return;
@@ -2470,6 +2470,7 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev,
 		sme_err("Invalid AKM suite");
 		return;
 	}
+	sme_debug("Intersected AKM with AP's AKM 0x%x", neg_akm);
 
 	/*
 	 * As there can be multiple AKM present select the most secured AKM

From a9ceabde2e748e0445013914fd646df357da9288 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 9 Apr 2026 18:01:44 -0700
Subject: [PATCH 206/290] fw-api: CL 32168619 - update fw common interface
 files

Change-Id: I369a2ab8f0c8dd4ed5fe2b558164a1f38796d561
CRs-Fixed: 3830439
---
 fw/htt.h         | 3 +++
 fw/wmi_unified.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index b6411c191bd6..76e269688cca 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -22333,6 +22333,9 @@ extern void (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_SET) (A_UINT32 *var, A_UINT3
 extern A_UINT32 (*HTT_RX_PEER_META_DATA_DECAP_TYPE_GET) (A_UINT32 var);
 extern void (*HTT_RX_PEER_META_DATA_DECAP_TYPE_SET) (A_UINT32 *var, A_UINT32 val);
 
+extern A_UINT32 (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_GET) (A_UINT32 var);
+extern void (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_SET) (A_UINT32 *var, A_UINT32 val);
+
 
 /*
  * In some systems, the host SW wants to specify priorities between
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f2d05d577272..23e620ab7f2f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -46786,7 +46786,7 @@ typedef enum {
     WMI_6GHZ_REG_PWRMODE_C2C = 4, /*C2C client mode for AP and client products*/
     WMI_6GHZ_REG_PWRMODE_GVP = 5, /* GVP mode for AP and client products */
 
-    WMI_6GHZ_REG_PWRMODE_MAX = 5
+    WMI_6GHZ_REG_PWRMODE_MAX = 6
 } WMI_6GHZ_REG_PWRMODE_TYPE;
 
 typedef struct {

From 3424c5548d3039bff03c4384c8af7d500c0e1e33 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 12 Apr 2026 18:04:09 -0700
Subject: [PATCH 207/290] fw-api: CL 32226903 - update fw common interface
 files

Change-Id: I09dfa14fca2a59b3b6ede26ae2f77c3442d8b58c
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 10 ++++++++++
 fw/wmi_unified.h  | 21 +++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index a5e7b230197e..9aa58fc5af13 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1613,6 +1613,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_iface_ipi_stats,
     WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params,
+    WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2580,6 +2581,7 @@ typedef enum {
     OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \
     OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \
     OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \
+    OP(WMI_NDP_CHANNEL_INFO_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -7388,6 +7390,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, wmi_nan_peer_params_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CNF_EVENTID);
 
+/* NDP Channel Info Event */
+#define WMITLV_TABLE_WMI_NDP_CHANNEL_INFO_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param, wmi_ndp_channel_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, channel_list, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_channel_info, channel_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CHANNEL_INFO_EVENTID);
+
 /* Coex report antenna isolation event */
 #define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 23e620ab7f2f..dc3f726a5881 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2665,6 +2665,8 @@ typedef enum {
     WMI_NAN_PEER_SCHEDULE_CNF_EVENTID,
     /* Confirmation event that FW has received WMI_NAN_PEER_PARAMS_CMDID */
     WMI_NAN_PEER_PARAMS_CNF_EVENTID,
+    /* Indicate negotiated committed NDP channels information. */
+    WMI_NDP_CHANNEL_INFO_EVENTID,
 
     /* Coex Event */
     WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
@@ -31865,6 +31867,25 @@ typedef struct {
     A_UINT32 status;
 } wmi_nan_peer_params_cnf_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param */
+
+    A_UINT32 vdev_id; /* Virtual device ID used for NDP operations (NDI VDEV) */
+    /** peer NDI MAC address */
+    wmi_mac_addr peer_ndi_macaddr;
+    /** Number of channels on this peer */
+    A_UINT32 num_ndp_channels;
+    /**
+     * TLV (tag length value) parameters follow the ndp_confirm
+     * structure. The TLV's are:
+     * wmi_channel ndp_channel_list[];
+     * A_UINT32 nss_list[]; // Nss indexing should match with channel indexing,
+     *                      // since Nss is associated with the channel.
+     * wmi_ndp_channel_info channel_info[]; // Indexing should match with
+     *                                      // channel indexing.
+     */
+} wmi_ndp_channel_info_event_fixed_param;
+
 typedef enum {
     WMI_NDP_BAND_CAP_2GHZ = 0x01,
     WMI_NDP_BAND_CAP_5GHZ = 0x02,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0943d428fd59..93cc9d29d865 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1740
+#define __WMI_REVISION_ 1741
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 7450395d4ef112c1edf72a016d359063ac730514 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 12 Apr 2026 18:06:05 -0700
Subject: [PATCH 208/290] fw-api: CL 32227070 - update fw common interface
 files

Change-Id: I3e30a77a4b510a3a2465269c2f6b51efc2678376
CRs-Fixed: 3830439
---
 fw/htt.h | 58 +++++++++++++++++++++++++++++++++++++++-----------------
 1 file changed, 41 insertions(+), 17 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 76e269688cca..f11c398ac942 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -283,9 +283,10 @@
  * 3.153 Add passthru_pkt flag in rx_peer_metadata structs.
  * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def.
  * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t.
+ * 3.156 Add qdata_consent_pkt flag in rx_peer_metadata_v1a and v2.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 155
+#define HTT_CURRENT_VERSION_MINOR 156
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -22007,14 +22008,14 @@ PREPACK struct htt_rx_peer_metadata_v1 {
  */
 PREPACK struct htt_rx_peer_metadata_v1a {
     A_UINT32
-        peer_id:         13,
-        ml_peer_valid:   1,
-        vdev_id:         8,
-        logical_link_id: 4,
-        chip_id:         3,
-        qdata_refill:    1,
-        passthru_pkt:    1,
-        reserved2:       1;
+        peer_id:           13,
+        ml_peer_valid:     1,
+        vdev_id:           8,
+        logical_link_id:   4,
+        chip_id:           3,
+        qdata_refill:      1,
+        passthru_pkt:      1,
+        qdata_consent_pkt: 1;
 } POSTPACK;
 
 #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S    0
@@ -22094,6 +22095,17 @@ PREPACK struct htt_rx_peer_metadata_v1a {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S)); \
     } while (0)
 
+#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S    31
+#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M    0x80000000
+#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S)
+
+#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT, _val);  \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S)); \
+    } while (0)
+
 
 /**
  * @brief target -> RX PEER METADATA V1B format
@@ -22201,14 +22213,15 @@ PREPACK struct htt_rx_peer_metadata_v1b {
  */
 PREPACK struct htt_rx_peer_metadata_v2 {
     A_UINT32
-        peer_id:          5,
-        ml_peer_valid:    1,
-        vdev_id:          3,
-        logical_link_id:  3,
-        qdata_refill:     1,
-        peer_session_id:  8,
-        passthru_pkt:     1,
-        reserved:        10;
+        peer_id:           5,
+        ml_peer_valid:     1,
+        vdev_id:           3,
+        logical_link_id:   3,
+        qdata_refill:      1,
+        peer_session_id:   8,
+        passthru_pkt:      1,
+        qdata_consent_pkt: 1,
+        reserved:          9;
 } POSTPACK;
 
 #define HTT_RX_PEER_META_DATA_V2_PEER_ID_S 0
@@ -22294,6 +22307,17 @@ PREPACK struct htt_rx_peer_metadata_v2 {
         ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S)); \
     } while (0)
 
+#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S 22
+#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M 0x00400000
+#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_GET(_var) \
+    (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S)
+
+#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT, _val);  \
+        ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S)); \
+    } while (0)
+
 
 /* generic variables for masks and shifts for various fields */
 extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S;

From 36cbdb342f578b66bbabc78396ab47dfce88a2ec Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 12 Apr 2026 18:07:59 -0700
Subject: [PATCH 209/290] fw-api: CL 32227291 - update fw common interface
 files

Change-Id: I7bde622379ad6ad74a3292d3f119729974123f9d
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 6324a7b5c015..c7222d1262af 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1621,6 +1621,11 @@ typedef struct {
     A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS];
 
     A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS];
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_mu_ppdu_dist_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v;
@@ -3905,6 +3910,11 @@ typedef struct {
     A_UINT32 standalone_be_ulmumimo_trigger_tried[HTT_NUM_AC_WMM];
     /** 11BE EHT MU Standalone UL MU-MIMO Basic Trigger completed with error(s) */
     A_UINT32 standalone_be_ulmumimo_trigger_err[HTT_NUM_AC_WMM];
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_selfgen_be_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_selfgen_be_stats_tlv htt_tx_selfgen_be_stats_tlv;
@@ -4713,6 +4723,11 @@ typedef struct {
     A_UINT32 be_mu_rts_trigger_blocked;
     /** 11BE EHT MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */
     A_UINT32 be_bsr_trigger_blocked;
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_selfgen_be_err_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_selfgen_be_err_stats_tlv htt_tx_selfgen_be_err_stats_tlv;
@@ -4873,6 +4888,11 @@ typedef struct {
     A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS];
     /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */
     A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS];
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_selfgen_be_sched_status_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv
@@ -4981,6 +5001,11 @@ typedef struct {
     A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS];
     /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */
     A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_pdev_mu_mimo_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_mu_mimo_stats_tlv htt_tx_pdev_mu_mimo_sch_stats_tlv;
@@ -5040,6 +5065,11 @@ typedef struct {
     A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS];
     /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/
     A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_pdev_dl_mu_mimo_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_dl_mu_mimo_stats_tlv
@@ -7218,6 +7248,11 @@ typedef struct {
     A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS];
     /** 11BE DL MU MIMO LDPC count */
     A_UINT32 be_mu_mimo_tx_ldpc;
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_pdev_be_rate_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_be_rate_stats_tlv htt_tx_pdev_rate_stats_be_tlv;

From f36a7e42251a7025df7a2eac0957a4a90da29146 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 12 Apr 2026 18:09:54 -0700
Subject: [PATCH 210/290] fw-api: CL 32227711 - update fw common interface
 files

Change-Id: I4b83b4551ba36864fc332800d03c915925868391
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index dcd795d1710f..e2392e383174 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -778,6 +778,8 @@ typedef  enum  {
     WMI_SERVICE_IDLE_POWER_INDICATE_SUPPORT = 498,
     /* Indicates FW support to add Radar type and domain in WMI radar event */
     WMI_SERVICE_RADAR_FLAGS_TYPE_SUPPORT = 499,
+    /* Indicates FW support to perform Master migration when master peer gets deleted */
+    WMI_SERVICE_ML_PEER_MASTER_MIGRATION_SUPPORT = 500,
 
 
     WMI_MAX_EXT2_SERVICE

From 9b3e32a13b4e7e873c0dd3879437b06d41f640ee Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Mon, 13 Apr 2026 06:01:51 -0700
Subject: [PATCH 211/290] fw-api: CL 32229597 - update fw common interface
 files

Change-Id: I2305f70b9ad7a02647d5eaea393ee991c325f803
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 16 ++++++++--
 fw/wmi_unified.h  | 76 +++++++++++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 3 files changed, 87 insertions(+), 7 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 9aa58fc5af13..01d9a549787d 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1614,6 +1614,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_iface_ipi_stats,
     WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params,
     WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2218,6 +2220,7 @@ typedef enum {
     OP(WMI_TWT_ADD_CH_USAGE_CMDID) \
     OP(WMI_COEX_GET_POLICY_STATS_CMDID) \
     OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \
+    OP(WMI_PEER_UHR_OMP_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2995,8 +2998,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \
-   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params,  WMITLV_SIZE_VAR) \
-   WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_uhr_config, uhr_config,  WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_uhr_config, uhr_config,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR)
 /* NOTE:
  * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as
  * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility.
@@ -3186,6 +3190,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID);
  */
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
 
+#define WMITLV_TABLE_WMI_PEER_UHR_OMP_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, wmi_peer_uhr_omp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_npca_params, peer_omp_npca_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_OMP_CMDID);
+
 /* Peer Set Rate Report Condition Cmd */
 #define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -5282,7 +5291,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_tx_stream_list, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_rx_stream_list, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID);
 
 #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index dc3f726a5881..411889d45b35 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -919,7 +919,11 @@ typedef enum {
     /* WMI_PEER_ASSOC_V2_CMDID: extended alternative for WMI_PEER_ASSOC_CMDID */
     WMI_PEER_ASSOC_V2_CMDID,
 
-    /* beacon/management specific commands */
+    /* WMI_PEER_UHR_OMP_CMDID for UHR OMP frame*/
+    WMI_PEER_UHR_OMP_CMDID,
+
+
+    /*--- beacon/management specific commands ---*/
 
     /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */
     WMI_BCN_TX_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MGMT),
@@ -19223,6 +19227,8 @@ typedef struct {
  *         optional TLV used for SMD
  *     wmi_vdev_start_uhr_config uhr_config_info
  *         optional TLV used if VAP is 11BN
+ *     wmi_uhr_ap_npca_params npca_params
+ *         optional TLV used to update NPCA information
  */
 } wmi_vdev_start_request_cmd_fixed_param;
 
@@ -23753,6 +23759,67 @@ typedef struct {
     A_UINT32 npca_op_param1;
 } wmi_peer_uhr_npca_op_params;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param */
+    A_UINT32 sw_peer_id;
+    A_UINT32 pdev_id;
+
+    /*
+     * Variable-length TLV arrays follow this fixed param:
+     *   wmi_peer_uhr_omp_npca_params peer_omp_npca_params[];
+     *   Place Holder for other TLVs
+     */
+} wmi_peer_uhr_omp_cmd_fixed_param;
+
+typedef struct{
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params */
+    /*
+     * Bit0:3:  NPCA hw_link_id
+     *          WMI_OMP_NPCA_HW_LINK_ID_GET /  _SET
+     * Bit4:    Enable/Disable  NPCA params
+     *          WMI_OMP_NPCA_ENABLE_GET / _SET
+     * Bit5:    Update NPCA params
+     *          WMI_OMP_NPCA_UPDATE_GET / _SET
+     * Bit6:31: Reserved
+    */
+    A_UINT32 omp_npca_caps;
+    /*
+     * Bit0:5:   NPCA Switch Delay
+     *           The time needed by an NPCA STA to switch from the
+     *           BSS primary channel to the NPCA primary channel,
+     *           in units of 4 us.
+     *           WMI_OMP_NPCA_SWITCH_DELAY_GET / _SET
+     *
+     * Bit6:11: NPCA Switch Back Delay
+     *           The time needed by an NPCA STA to switch from the
+     *           NPCA primary channel to the BSS primary channel,
+     *           in units of 4
+     *           WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET / _SET
+     *
+     * Bit12:31: Reserved
+     */
+    A_UINT32 omp_npca_param;
+} wmi_peer_uhr_omp_npca_params;
+
+#define WMI_OMP_NPCA_HW_LINK_ID_GET(_var)       WMI_GET_BITS(_var, 0, 4)
+#define WMI_OMP_NPCA_HW_LINK_ID_SET(_var, _val) WMI_SET_BITS(_var, 0, 4, _val)
+
+#define WMI_OMP_NPCA_ENABLE_GET(_var)           WMI_GET_BITS(_var, 4, 1)
+#define WMI_OMP_NPCA_ENABLE_SET(_var, _val)     WMI_SET_BITS(_var, 4, 1, _val)
+
+#define WMI_OMP_NPCA_UPDATE_GET(_var)           WMI_GET_BITS(_var, 5, 1)
+#define WMI_OMP_NPCA_UPDATE_SET(_var, _val)     WMI_SET_BITS(_var, 5, 1, _val)
+
+#define WMI_OMP_NPCA_SWITCH_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 0, 6)
+#define WMI_OMP_NPCA_SWITCH_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 0, 6, _val)
+
+#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 6, 6)
+#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 6, 6, _val)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */
     A_UINT32 vdev_id;
@@ -42432,6 +42499,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID);
         WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID);
         WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID);
+        WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -43609,6 +43677,8 @@ typedef struct {
      *     optional TLV for dbw_chan
      * wmi_dbw_chan_info dbw_chan_info
      *     optional TLV used for dbw_chan_info
+     * wmi_uhr_ap_npca_params npca_params
+     *      optional TLV used to update NPCA information
      */
 } wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param;
 
@@ -55102,13 +55172,13 @@ typedef struct {
      *           The time needed by an NPCA STA to switch from the
      *           BSS primary channel to the NPCA primary channel,
      *           in units of 4 us.
-     *           WMI_NPCA_AP_CAP_SWT_DELAY_GET / _SET
+     *           WMI_NPCA_AP_CAP_SWITCH_DELAY_GET / _SET
      *
      * Bit18:23: NPCA Switch Back Delay
      *           The time needed by an NPCA STA to switch from the
      *           NPCA primary channel to the BSS primary channel,
      *           in units of 4 us.
-     *           WMI_NPCA_AP_CAP_SWTB_DELAY_GET / _SET
+     *           WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET / _SET
      *
      * Bit24:25: The Initial NPCA QSRC field indicates the value
      *           that is used to initialize the EDCAF QSRC[AC] variables
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 93cc9d29d865..1dbf822b9389 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1741
+#define __WMI_REVISION_ 1742
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 7e715c579f188ed71491b7e0c5b4f996a0bdf37e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 14 Apr 2026 18:01:47 -0700
Subject: [PATCH 212/290] fw-api: CL 32239632 - update fw common interface
 files

Change-Id: I049351832e203775820a3984312386d8f20a3fae
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 12 ++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 411889d45b35..024476b04c8d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -26722,6 +26722,18 @@ typedef enum {
 
     /* WoW error if close to TBTT */
     WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12,
+
+    /* WoW error if platform not ready */
+    WMI_WOW_NON_ACK_REASON_PLATFORM = 13,
+
+    /* WoW error if resume n processs */
+    WMI_WOW_NON_ACK_RESUME_IN_PROCESS = 14,
+
+    /* WoW error UT command */
+    WMI_WOW_NON_ACK_REASON_UNIT_TEST_CMD = 15,
+
+    /* WoW error if MCC lite mode active */
+    WMI_WOW_NON_ACK_REASON_MCC_LITE = 16,
 } WMI_WOW_NACK_STATUS;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1dbf822b9389..af5abece2106 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1742
+#define __WMI_REVISION_ 1743
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e981e5130671c67cc7382b43e21f18a02caab350 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 16 Apr 2026 18:01:38 -0700
Subject: [PATCH 213/290] fw-api: CL 32267210 - update fw common interface
 files

Change-Id: I08c3cb53cf08ea7860bfbafb32e28ea037234a01
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h | 10 +++++++++-
 fw/wmi_unified.h  | 29 +++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index e2392e383174..6fc95d2b5a83 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -780,6 +780,7 @@ typedef  enum  {
     WMI_SERVICE_RADAR_FLAGS_TYPE_SUPPORT = 499,
     /* Indicates FW support to perform Master migration when master peer gets deleted */
     WMI_SERVICE_ML_PEER_MASTER_MIGRATION_SUPPORT = 500,
+    WMI_SERVICE_NAN_AP_ASSISTED_DFS_OPERATION_SUPPORT = 501, /* Indicates FW supports NAN DFS operation */
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 01d9a549787d..3a87f1569949 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1616,6 +1616,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params,
+    WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2585,6 +2586,7 @@ typedef enum {
     OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \
     OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \
     OP(WMI_NDP_CHANNEL_INFO_EVENTID) \
+    OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -4434,7 +4436,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_CMDID);
 #define WMITLV_TABLE_WMI_NAN_CONFIG_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, wmi_nan_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_availability_attributes_data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CONFIG_CMDID);
 
 /* NAN Disable Command */
@@ -8834,6 +8837,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID);
 
+/* NAN DFS Channel Availability Indication Event */
+#define WMITLV_TABLE_WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, wmi_nan_dfs_channel_availability_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 024476b04c8d..4fd435bdbe62 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2671,6 +2671,8 @@ typedef enum {
     WMI_NAN_PEER_PARAMS_CNF_EVENTID,
     /* Indicate negotiated committed NDP channels information. */
     WMI_NDP_CHANNEL_INFO_EVENTID,
+    /* Event to indicate availability of STA AP connection on DFS channel */
+    WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID,
 
     /* Coex Event */
     WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
@@ -31652,10 +31654,21 @@ typedef struct {
      * specific parameter defined in WMI_NAN_CONFIG_CHANGE_PARAM.
      */
     A_UINT32 nan_conf_change_bitmap;
+    /* nan_availability_attributes_len:
+     * number of valid bytes (i.e. excluding final alignment-padding)
+     * in the TLV nan_availability_attributes_data[]
+     */
+    A_UINT32 nan_availability_attributes_len;
 /*
  * TLVs following this structure:
  *     wmi_nan_ctrl_config_param nan_ctrl_config[];
  *     wmi_nan_disc_band_config_param nan_disc_band_config[];
+ *     A_UINT8 nan_availability_attributes_data[]:
+ *         NAN availability attributes sent down (along with header)
+ *         are sent in stream of bytes (ieee80211 protocol order).
+ *         The host must manually byteswap these bytes within each 4-byte word
+ *         if the host's endianness doesn't match the target's, to ensure the
+ *         expected byte order is maintained.
  */
 } wmi_nan_config_cmd_fixed_param;
 
@@ -31766,6 +31779,12 @@ typedef struct {
  */
 } wmi_nan_peer_params_cmd_fixed_param;
 
+typedef enum {
+    WMI_NAN_STATUS_NO_NAN_AVAIL_DFS_CHANNEL_DETECTED  = 0x1,
+    WMI_NAN_STATUS_NO_DFS_BEACONS_RECEIVED            = 0x2,
+    WMI_NAN_STATUS_STA_DISCONNECTED_FROM_DFS          = 0x3,
+} WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE;
+
 #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag)      WMI_GET_BITS(flag, 0, 1)
 #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val)
 #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag)      WMI_GET_BITS(flag, 1, 1)
@@ -31946,6 +31965,16 @@ typedef struct {
     A_UINT32 status;
 } wmi_nan_peer_params_cnf_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals
+                          *  WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param */
+    A_UINT32 vdev_id;
+    /** status:
+     * Status code; see WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE
+     */
+    A_UINT32 status;
+} wmi_nan_dfs_channel_availability_ind_event_fixed_param;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index af5abece2106..f8ef4b026c67 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1743
+#define __WMI_REVISION_ 1744
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 2afc1681dd72e3ac8ce2e7d4c37c2cb9b54ba936 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 17 Apr 2026 18:01:47 -0700
Subject: [PATCH 214/290] fw-api: CL 32280311 - update fw common interface
 files

Change-Id: Id7cccce49f7a94f9073183cb79c6be31a023c342
CRs-Fixed: 3830439
---
 fw/htt.h       | 258 ++++++++++++++++++++++++++++++++++++++++++++++---
 fw/htt_stats.h |  51 ++++++++--
 2 files changed, 290 insertions(+), 19 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index f11c398ac942..c83725d2a56a 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -284,9 +284,10 @@
  * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def.
  * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t.
  * 3.156 Add qdata_consent_pkt flag in rx_peer_metadata_v1a and v2.
+ * 3.157 Add TCL_METADATA_V3 defs.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 156
+#define HTT_CURRENT_VERSION_MINOR 157
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -583,6 +584,7 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t {
  * should be used:
  *     V1 -> use htt_tx_tcl_metadata struct
  *     V2 -> use htt_tx_tcl_metadata_v2 struct
+ *     V3 -> use htt_tx_tcl_metadata_v3 struct
  * Old FW will only support V1.
  * New FW will support V2. New FW will still support V1, at least during
  * a transition period.
@@ -608,11 +610,17 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t {
  * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and
  * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index
  * in TCLV2 command and do the dynamic AST allocations.
+ *
+ * Apr 2026: Added HTT_OPTION_TLV_TCL_METADATA_V3.
+ * This version supports the updated tcl_data_cmd introduced in Boron.
+ * All fields are identical to V2; however, the field ordering has been
+ * modified to accommodate MAC requirements.
  */
 enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES {
     HTT_OPTION_TLV_TCL_METADATA_V1 = 1,
     HTT_OPTION_TLV_TCL_METADATA_V2 = 2,
-    /* values 3-20 reserved */
+    HTT_OPTION_TLV_TCL_METADATA_V3 = 3,
+    /* values 4-20 reserved */
     HTT_OPTION_TLV_TCL_METADATA_V21 = 21,
 };
 
@@ -865,13 +873,16 @@ typedef enum {
     HTT_STATS_PDEV_RTT_DELAY_TAG                    = 205, /* htt_stats_pdev_rtt_delay_tlv */
     HTT_STATS_PDEV_AOA_TAG                          = 206, /* htt_stats_pdev_aoa_tlv */
     HTT_STATS_PDEV_FTM_TPCCAL_TAG                   = 207, /* htt_stats_pdev_ftm_tpccal_tlv */
-    HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG          = 208, /* htt_stats_pdev_ulmumimo_grp_stats_tlv */
-    HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG     = 209, /* htt_stats_pdev_ulmumimo_denylist_stats_tlv */
-    HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG     = 210, /* htt_stats_pdev_ulmumimo_seq_term_stats_tlv */
-    HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ulmumimo_hist_ineligibility_tlv */
+    HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG          = 208, /* htt_stats_pdev_ul_mumimo_grp_stats_tlv */
+    HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG     = 209, /* htt_stats_pdev_ul_mumimo_denylist_stats_tlv */
+    HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG     = 210, /* htt_stats_pdev_ul__mumimo_seq_term_stats_tlv */
+    HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv */
     HTT_STATS_PHY_PAPRD_PB_TAG                      = 212, /* htt_stats_phy_paprd_pb_tlv */
     HTT_STATS_HDS_PROF_STATS_TAG                    = 213, /* htt_stat_hds_prof_stats_tlv */
-    HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TLV_TAG = 214, /* htt_stats_tx_pdev_mdsb_num_users_histogram_tlv */
+    HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG = 214, /* htt_stats_tx_pdev_mdsb_num_users_histogram_tlv */
+        /* preserve old name as an alias for the corrected name */
+        HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TLV_TAG =
+            HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG,
     HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_TAG = 215, /* htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv */
     HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_TAG        = 216, /* htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv */
     HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_TAG        = 217, /* htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv */
@@ -880,8 +891,8 @@ typedef enum {
     HTT_STATS_TX_SELFGEN_BN_ERR_TAG                 = 220, /* htt_stats_tx_selfgen_bn_err_tlv, TOPIC=advanced */
     HTT_STATS_TX_SELFGEN_BN_TAG                     = 221, /* htt_stats_tx_selfgen_bn_tlv, TOPIC=advanced */
     HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG        = 222, /* htt_stats_tx_selfgen_bn_sched_status_tlv, TOPIC=advanced */
-    HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG      = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv, TOPIC=advanced */
-    HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG      = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv, TOPIC=advanced */
+    HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG      = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv, TOPIC=advanced */
+    HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG      = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv, TOPIC=advanced */
     HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TAG          = 225, /* htt_stats_rx_peer_tid_reo_queue_ba_tlv */
     HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG                = 226, /* htt_stats_txbf_ofdma_bn_ndpa_tlv */
     HTT_STATS_TXBF_OFDMA_BN_NDP_TAG                 = 227, /* htt_stats_txbf_ofdma_bn_ndp_tlv */
@@ -915,14 +926,14 @@ typedef enum {
     HTT_STATS_REGDB_CTRY_TAG                        = 247, /* htt_stats_regdb_ctry_tlv */
     HTT_STATS_REGDB_REGDOMAIN_TAG                   = 248, /* htt_stats_regdb_regdomain_tlv */
     HTT_STATS_REG_6G_TAG                            = 249, /* htt_stats_reg_6g_tlv*/
-    HTT_STATS_REG_6G_CH_PWR_INFO_TAG                = 250, /* htt_stats_reg_6g_ch_power_info_tlv*/
+    HTT_STATS_REG_6G_CH_PWR_INFO_TAG                = 250, /* htt_stats_reg_6g_ch_power_info_tlv */
     HTT_STATS_REG_6G_OOBE_TAG                       = 251, /* htt_stats_reg_6g_oobe_tlv*/
     HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_TAG       = 252, /* htt_stats_tx_selfgen_resp_frame_stats_tlv */
     HTT_STATS_DPD_HALPHY_TAG                        = 253, /* htt_stats_dpd_halphy_tlv */
     HTT_STATS_DPD_HW_CAL_PARAMS_TAG                 = 254, /* htt_stats_dpd_hw_cal_params_tlv */
     HTT_STATS_DPD_HW_CAL_RESULTS_TAG                = 255, /* htt_stats_dpd_hw_cal_results_tlv */
     HTT_STATS_TX_PDEV_TXOP_DUR_TAG                  = 256, /* htt_stats_tx_pdev_txop_dur_tlv */
-    HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG            = 257, /* htt_stats_sched_txq_combined_seq_state_tlv */
+    HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG            = 257, /* htt_stats_txq_combined_seq_state_tlv */
     HTT_STATS_CTL_TAG                               = 258, /* htt_stats_ctl_tlv */
     HTT_STATS_ENHANCED_CTL_TAG                      = 259, /* htt_stats_enhanced_ctl_tlv */
 
@@ -2947,6 +2958,231 @@ PREPACK struct htt_tx_tcl_metadata_v2 {
  *                 End V2 Version of TCL Data Command
  *-----------------------------------------------------------------*/
 
+
+/*------------------------------------------------------------------
+ *                 V3 Version of TCL Data Command
+ * V3 Version to support peer_id, vdev_id, svc_class_id and
+ * MLO global_seq all flavours of TCL Data Cmd. same fields as V2,
+ * but the ordering of the fields changes.
+ *-----------------------------------------------------------------*/
+
+typedef struct {
+    A_UINT32
+        valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
+        vdev_id:       8,
+        pdev_id:       2,
+        host_inspected:1,
+        rsvd:          2,
+        /* type: vdev_id based or peer_id or svc_id or global seq based */
+        type:          2,
+        /* padding: these 16 bits cannot be used by FW for the tcl command */
+        padding:      16;
+} htt_tx_tcl_vdev_metadata_v3;
+
+typedef struct {
+    A_UINT32
+        valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
+        peer_id:       13,
+        /* type: vdev_id based or peer_id or svc_id or global seq based */
+        type:          2,
+        /* padding: these 16 bits cannot be used by FW for the tcl command */
+        padding:       16;
+} htt_tx_tcl_peer_metadata_v3;
+
+typedef struct {
+    A_UINT32
+        valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
+        svc_class_id:  8,
+        /* ast_index:
+         * Indicates to firmware the AST index to be used for AST Override
+         */
+        ast_index:     3,
+        rsvd:          2,
+        /* type: vdev_id based or peer_id or svc_id or global seq based */
+        type:          2,
+        /* padding: these 16 bits cannot be used by FW for the tcl command */
+        padding:      16;
+} htt_tx_tcl_svc_class_id_metadata_v3;
+
+typedef struct {
+    A_UINT32
+        global_seq_no: 12,
+        host_inspected: 1,
+        htt_ext_present:1,
+        /* type: vdev_id based or peer_id or svc_id or global seq based */
+        type:           2,
+        /* padding: these 16 bits cannot be used by FW for the tcl command */
+        padding:       16;
+} htt_tx_tcl_global_seq_metadata_v3;
+
+PREPACK struct htt_tx_tcl_metadata_v3 {
+    union {
+        htt_tx_tcl_vdev_metadata_v3 vdev_meta_v3;
+        htt_tx_tcl_peer_metadata_v3 peer_meta_v3;
+        htt_tx_tcl_svc_class_id_metadata_v3 svc_class_id_meta_v3;
+        htt_tx_tcl_global_seq_metadata_v3 global_seq_meta_v3;
+    };
+} POSTPACK;
+
+/* =====================================================================
+ * Common fields
+ * ===================================================================== */
+
+/* type field */
+#define HTT_TX_TCL_METADATA_TYPE_V3_M                  0x0000C000
+#define HTT_TX_TCL_METADATA_TYPE_V3_S                  14
+
+/* valid htt ext (used by VDEV / PEER / SVC metadata) */
+#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M      0x00000001
+#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S      0
+
+
+/* =====================================================================
+ * VDEV V3 metadata
+ * ===================================================================== */
+
+#define HTT_TX_TCL_METADATA_V3_VDEV_ID_M               0x000001FE
+#define HTT_TX_TCL_METADATA_V3_VDEV_ID_S               1
+
+#define HTT_TX_TCL_METADATA_V3_PDEV_ID_M               0x00000600
+#define HTT_TX_TCL_METADATA_V3_PDEV_ID_S               9
+
+#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M        0x00000800
+#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S        11
+
+
+/* =====================================================================
+ * PEER V3 metadata
+ * ===================================================================== */
+
+#define HTT_TX_TCL_METADATA_V3_PEER_ID_M               0x00003FFE
+#define HTT_TX_TCL_METADATA_V3_PEER_ID_S               1
+
+
+/* =====================================================================
+ * SVC CLASS ID metadata
+ * ===================================================================== */
+
+#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M             0x000001FE
+#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S             1
+
+#define HTT_TX_TCL_METADATA_AST_INDEX_M                   0x00000E00
+#define HTT_TX_TCL_METADATA_AST_INDEX_S                   9
+
+
+/* =====================================================================
+ * Global Sequence Number metadata
+ * ===================================================================== */
+
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M              0x00000FFF
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S              0
+
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M  0x00001000
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S  12
+
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M 0x00002000
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S 13
+
+/*----- Get and Set V3 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */
+#define HTT_TX_TCL_METADATA_TYPE_V3_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_TYPE_V3_M) >> \
+    HTT_TX_TCL_METADATA_TYPE_V3_S)
+#define HTT_TX_TCL_METADATA_TYPE_V3_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V3, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V3_S)); \
+     } while (0)
+
+#define HTT_TX_TCL_METADATA_V3_VALID_HTT_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M) >> \
+    HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S)
+#define HTT_TX_TCL_METADATA_V3_VALID_HTT_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S)); \
+     } while (0)
+
+/*----- Get and Set V3 type field in Vdev meta fields ----*/
+#define HTT_TX_TCL_METADATA_V3_VDEV_ID_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_VDEV_ID_M) >> \
+    HTT_TX_TCL_METADATA_V3_VDEV_ID_S)
+#define HTT_TX_TCL_METADATA_V3_VDEV_ID_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VDEV_ID, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VDEV_ID_S)); \
+     } while (0)
+
+#define HTT_TX_TCL_METADATA_V3_PDEV_ID_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_PDEV_ID_M) >> \
+    HTT_TX_TCL_METADATA_V3_PDEV_ID_S)
+#define HTT_TX_TCL_METADATA_V3_PDEV_ID_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PDEV_ID, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PDEV_ID_S)); \
+     } while (0)
+
+#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M) >> \
+    HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S)
+#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_HOST_INSPECTED, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S)); \
+     } while (0)
+
+/*----- Get and Set V3 type field in Peer meta fields ----*/
+#define HTT_TX_TCL_METADATA_V3_PEER_ID_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_PEER_ID_M) >> \
+    HTT_TX_TCL_METADATA_V3_PEER_ID_S)
+#define HTT_TX_TCL_METADATA_V3_PEER_ID_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PEER_ID, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PEER_ID_S)); \
+     } while (0)
+
+/*----- Get and Set V3 type field in Service Class fields ----*/
+#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M) >> \
+    HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S)
+#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S)); \
+     } while (0)
+
+/*----- Get and Set V3 type field in Global sequence fields ----*/
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M) >> \
+    HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S)
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S)); \
+     } while (0)
+
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M) >> \
+    HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S)
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S)); \
+     } while (0)
+
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_GET(_var) \
+    (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M) >> \
+    HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S)
+#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT, _val); \
+         ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S)); \
+     } while (0)
+
+/*------------------------------------------------------------------
+ *                 End V3 Version of TCL Data Command
+ *-----------------------------------------------------------------*/
+
+
 typedef enum {
    HTT_TX_FW2WBM_TX_STATUS_OK,
    HTT_TX_FW2WBM_TX_STATUS_DROP,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index c7222d1262af..5bd300678e6f 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -5097,7 +5097,10 @@ typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** Represents the count for 11BN DL MU OFDMA sequences */
     A_UINT32 bn_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS];
-} htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv;
+} htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv
+    htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv;
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -5162,7 +5165,10 @@ typedef struct {
     /**
      * TODO_BORON_OFDMA : Add array for BN_BRP number of users
      */
-} htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv;
+} htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv
+    htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv;
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -5353,6 +5359,17 @@ typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 htt_stats_type;
 } htt_stats_error_tlv_v;
+/* Multiple TLV tag values
+ * (HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG,
+ * HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG)
+ * correspond to this htt_stats_error_tlv_v struct.
+ * Provide aliases that have the expected names
+ * that are consistent with the TLV tag enum names.
+ */
+typedef htt_stats_error_tlv_v
+    htt_stats_unsupported_error_stats_tlv;
+typedef htt_stats_error_tlv_v
+    htt_stats_unavailable_error_stats_tlv;
 
 typedef enum {
     HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true                                       */
@@ -5502,7 +5519,10 @@ typedef struct {
      * Indexed by htt_sched_txq_combined_seq_status_tlv_enum.
      */
     HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, combined_seq_state);
-} htt_stats_sched_txq_combined_seq_state_tlv;
+} htt_stats_txq_combined_seq_state_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_txq_combined_seq_state_tlv
+     htt_stats_sched_txq_combined_seq_state_tlv;
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -10994,7 +11014,10 @@ typedef struct {
     A_UINT32 mu_grp_candidate_skip_1ss
         [HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]
         [HTT_STATS_CANDIDATE_SKIP_REASON_MAX];
-} htt_stats_pdev_ulmumimo_grp_stats_tlv;
+} htt_stats_pdev_ul_mumimo_grp_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_pdev_ul_mumimo_grp_stats_tlv
+    htt_stats_pdev_ulmumimo_grp_stats_tlv;
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -11005,7 +11028,10 @@ typedef struct {
     A_UINT32 trig_bitmap_fail_cnt;
     /* Num of times peer denylisted due to trigger consecutive failure */
     A_UINT32 trig_consecutive_fail_cnt;
-} htt_stats_pdev_ulmumimo_denylist_stats_tlv;
+} htt_stats_pdev_ul_mumimo_denylist_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_pdev_ul_mumimo_denylist_stats_tlv
+    htt_stats_pdev_ulmumimo_denylist_stats_tlv;
 
 #define HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM 10
 typedef struct {
@@ -11042,7 +11068,10 @@ typedef struct {
      * for low traffic classification
      */
     A_UINT32 num_terminate_seq_low_traffic;
-} htt_stats_pdev_ulmumimo_seq_term_stats_tlv;
+} htt_stats_pdev_ul_mumimo_seq_term_stats_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_pdev_ul_mumimo_seq_term_stats_tlv
+    htt_stats_pdev_ulmumimo_seq_term_stats_tlv;
 
 #define HTT_STATS_MAX_ULMUMIMO_TRIGGERS 6
 #define HTT_STATS_TXOP_HISTOGRAM_BINS 24
@@ -11070,7 +11099,10 @@ typedef struct {
      * Checks for 8 eligible instances of ULMUMIMO in the past 32 instances.
      */
     A_UINT32 history_ineligibility;
-} htt_stats_pdev_ulmumimo_hist_ineligibility_tlv;
+} htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
+    htt_stats_pdev_ulmumimo_hist_ineligibility_tlv;
 
 
 /* RTT VREG MASK */
@@ -16473,7 +16505,10 @@ typedef struct {
         psd_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS];
     htt_stats_reg_freq_power_pair_t
         eirp_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS];
-} htt_stats_reg_6g_ch_power_info_tlv;
+} htt_stats_reg_6g_ch_pwr_info_tlv;
+/* preserve old name alias for new name consistent with the tag name */
+typedef htt_stats_reg_6g_ch_pwr_info_tlv
+    htt_stats_reg_6g_ch_power_info_tlv;
 
 #define HTT_STATS_REG_6G_GET_POWER_TYPE(word) \
     HTT_STATS_GET_FIELD(0xFF, 0, (word))

From a2d30225d0d8a07a05417a7d2bc2c97564467e99 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 17 Apr 2026 18:03:56 -0700
Subject: [PATCH 215/290] fw-api: CL 32280322 - update fw common interface
 files

Change-Id: I125186f3e769b153988e593d3938a8516ea65b90
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 85 ++++++++++++++++++++++++++++--------------------
 fw/wmi_version.h |  2 +-
 2 files changed, 51 insertions(+), 36 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4fd435bdbe62..e75558a9426a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -38537,9 +38537,13 @@ typedef enum {
 } WMI_PDEV_POWER_DATAPATH_STATS_OPERATION;
 
 typedef enum {
-   WMI_PDEV_POWER_STATS_TYPE = 0x00000001,
-   WMI_PDEV_DATAPATH_STATS_TYPE = 0x00000002,
-   WMI_PDEV_POWER_DATAPATH_STATS_ALL = 0x00000003,
+   WMI_PDEV_POWER_STATS_TYPE =             0x00000001,
+   WMI_PDEV_DATAPATH_STATS_TYPE =          0x00000002,
+   WMI_PDEV_POWER_DATAPATH_STATS_ALL =     0x00000003,
+   WMI_PDEV_SOC_POWER_STATS_TYPE =         0x00000004,
+   WMI_PDEV_SOC_POWER_DATAPATH_STATS_ALL = 0x00000005,
+
+
    WMI_PDEV_STATS_TYPE_MAX,
 } WMI_PDEV_POWER_DATAPATH_STATS_TYPE;
 
@@ -38790,47 +38794,58 @@ typedef struct {
 
 /* Power stats in event payload*/
 typedef struct {
-   /** Power Statistics */
-   A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_stats_info */
+    /** Power Statistics */
+    A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_stats_info */
 
-   /** Common element - core_index (PDEV ID) */
-   A_UINT32 core_index;
+    /** Common element - core_index (PDEV ID) */
+    A_UINT32 core_index;
 
-   A_UINT32 radio_on_time;    /* Time radio was on (ms) */
-   A_UINT32 radio_off_time;   /* Time radio was off (ms) */
-   A_UINT32 wlan_pwr_on_time; /* WLAN power on time (ms) */
-   /* tx_time:
-    * ms duration the radio is in a continuous transmit state
-    * encompassing all packet types (management, data, action frames)
-    */
-   A_UINT32 tx_time;
-   /* rx_time:
-    * ms duration the radio is in a continuous receiving data state
-    * Including all Rx packets instead of only collecting for my BSS data
-    */
-   A_UINT32 rx_time;
+    A_UINT32 radio_on_time;    /* Time radio was on (ms) */
+    A_UINT32 radio_off_time;   /* Time radio was off (ms) */
+    A_UINT32 wlan_pwr_on_time; /* WLAN power on time (ms) */
+    /* tx_time:
+     * ms duration the radio is in a continuous transmit state
+     * encompassing all packet types (management, data, action frames)
+     */
+    A_UINT32 tx_time;
+    /* rx_time:
+     * ms duration the radio is in a continuous receiving data state
+     * Including all Rx packets instead of only collecting for my BSS data
+     */
+    A_UINT32 rx_time;
 
-   /* Number of sleep levels being sent to the host */
-   A_UINT32 sleep_levels_num;
-   A_UINT32 sleep_time_per_levels[WMI_MAX_SLEEP_LEVELS]; /* ms */
+    /* Number of sleep levels being sent to the host */
+    A_UINT32 sleep_levels_num;
+    A_UINT32 sleep_time_per_levels[WMI_MAX_SLEEP_LEVELS]; /* ms */
 } wmi_pdev_power_stats_info;
 
 typedef struct {
-   A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param */
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param */
 
-   /** Status of the operation */
-   A_UINT32 status; /* 0 = success, non-zero = error */
+    /** Status of the operation */
+    A_UINT32 status; /* 0 = success, non-zero = error */
 
-   /** Stats type bitmap indicating which stats are included */
-   A_UINT32 stats_type_bitmap;
+    /** Stats type bitmap indicating which stats are included */
+    A_UINT32 stats_type_bitmap;
 
-   /*
-    * Following this structure are the TLVs:
-    *     wmi_pdev_power_stats_info[num_cores];
-    *     wmi_pdev_tx_rate_info[num_tx_rate_info]
-    * where num_cores and num_tx_rate_info are determined from the TLV array
-    * (i.e. array size / array element size)
-    */
+    A_UINT32 wlan_soc_pwr_on_time; /* WLAN power on time (ms) */
+
+    /* wlan_soc_sleep_levels_num:
+     * Number of sleep levels supported.
+     * Could be less than WMI_MAX_SLEEP_LEVELS based on the chip.
+     */
+     A_UINT32 wlan_soc_sleep_levels_num;
+
+    /** soc sleep level. Same WMI_MAX_SLEEP_LEVELS is used for sizing */
+    A_UINT32 wlan_soc_sleep_time_per_level[WMI_MAX_SLEEP_LEVELS]; /* ms */
+
+    /*
+     * Following this structure are the TLVs:
+     *     wmi_pdev_power_stats_info[num_cores];
+     *     wmi_pdev_tx_rate_info[num_tx_rate_info]
+     * where num_cores and num_tx_rate_info are determined from the TLV array
+     * (i.e. array size / array element size)
+     */
 } wmi_pdev_power_datapath_stats_event_fixed_param;
 
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f8ef4b026c67..8641a3f2f8f0 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1744
+#define __WMI_REVISION_ 1745
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 1c6d12855dcffdfc8c22861a26ec4b4d3b6a12c1 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 18 Apr 2026 18:01:49 -0700
Subject: [PATCH 216/290] fw-api: CL 32290054 - update fw common interface
 files

Change-Id: I83ff29000fadbd95de529b1d203579b7fd05a844
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   5 ++
 fw/wmi_tlv_defs.h |  17 +++++++
 fw/wmi_unified.h  | 115 ++++++++++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |   2 +-
 4 files changed, 135 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 6fc95d2b5a83..9d606f3a3792 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -781,6 +781,11 @@ typedef  enum  {
     /* Indicates FW support to perform Master migration when master peer gets deleted */
     WMI_SERVICE_ML_PEER_MASTER_MIGRATION_SUPPORT = 500,
     WMI_SERVICE_NAN_AP_ASSISTED_DFS_OPERATION_SUPPORT = 501, /* Indicates FW supports NAN DFS operation */
+    /*
+     * Indicates FW supports TDLS Stats command/event,
+     * used for sending TDLS connect info and TDLS data stats
+     */
+    WMI_SERVICE_TDLS_STATS_SUPPORT = 502,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 3a87f1569949..690b606aface 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1617,6 +1617,10 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params,
     WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats,
+    WMITLV_TAG_STRUC_wmi_tdls_data_stats,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2222,6 +2226,7 @@ typedef enum {
     OP(WMI_COEX_GET_POLICY_STATS_CMDID) \
     OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \
     OP(WMI_PEER_UHR_OMP_CMDID) \
+    OP(WMI_REQUEST_TDLS_STATS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2587,6 +2592,7 @@ typedef enum {
     OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \
     OP(WMI_NDP_CHANNEL_INFO_EVENTID) \
     OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \
+    OP(WMI_TDLS_STATS_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -5242,6 +5248,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID);
 
+/* Request TDLS Stats cmd enabling the monitoring of TDLS stats */
+#define WMITLV_TABLE_WMI_REQUEST_TDLS_STATS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param, wmi_request_tdls_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_TDLS_STATS_CMDID);
+
 /* Host sets the current country code */
 #define WMITLV_TABLE_WMI_SET_CURRENT_COUNTRY_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_current_country_cmd_fixed_param, wmi_set_current_country_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -8149,6 +8160,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HALPHY_CTRL_PATH_STATS_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_chan_stats, radio_chan_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_CHAN_STATS_EVENTID);
 
+#define WMITLV_TABLE_WMI_TDLS_STATS_EVENTID(id, op, buf, len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param, wmi_tdls_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_connect_info_stats, tdls_connect_info_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_data_stats, tdls_data_stats, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_STATS_EVENTID);
+
 #define WMITLV_TABLE_WMI_PKGID_EVENTID(id, op, buf, len) \
     WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pkgid_event_fixed_param, wmi_pkgid_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PKGID_EVENTID);
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e75558a9426a..57f59038b254 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1269,6 +1269,8 @@ typedef enum {
     /** request for HALPHY stats through ctrl path */
     WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID,
 
+    /** request for TDLS connect info and TDLS data stats */
+    WMI_REQUEST_TDLS_STATS_CMDID,
 
     /** ARP OFFLOAD REQUEST*/
     WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL),
@@ -2439,6 +2441,9 @@ typedef enum {
     /** FW IPA link stats Event */
     WMI_IPA_LINK_STATS_EVENTID,
 
+    /* TDLS Stats event having TDLS connect info and data stats */
+    WMI_TDLS_STATS_EVENTID,
+
 
     /* NLO specific events */
     /** NLO match event after the first match */
@@ -16135,6 +16140,102 @@ typedef struct {
      */
 } wmi_radio_chan_stats_event_fixed_param;
 
+typedef enum {
+    WMI_TDLS_CHANNEL_SWITCH_FRAME_TX_RX = 0x0,
+    WMI_TDLS_BT_COEX_INDICATION         = 0x1,
+} wmi_tdls_connect_info_stats_reason_code;
+
+typedef enum {
+    WMI_TDLS_FRAME_SUBTYPE_REQUEST  = 0x0,
+    WMI_TDLS_FRAME_SUBTYPE_RESPONSE = 0x1,
+} wmi_tdls_connect_info_stats_subtype;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     *  WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats */
+    A_UINT32 tlv_header;
+    /* type:
+     * Type of frame sent to the Peer, will be having value 4,
+     * i.e TDLS State change
+     */
+    A_UINT32 type;
+    /* subtype:
+     * SubType of frame sent to the Peer, eg. req/resp,
+     * Takes values from enum wmi_tdls_connect_info_stats_subtype.
+     */
+    A_UINT32 subtype;
+    /* reason_code:
+     * Reason code for the reason of sending this TLV, eg. for TDLS
+     * channel switch req/resp or for BT running indication
+     * Takes values from enum wmi_tdls_connect_info_stats_reason_code.
+     */
+    A_UINT32 reason_code;
+    /* tx_rx:
+     * Indicates whether we are sender or receiver of this frame,
+     * 1 value means Tx, 0 value means Rx.
+     */
+    A_UINT32 tx_rx;
+    /* Current operating channel frequency */
+    A_UINT32 op_freq_mhz;
+    /* Peer MAC address for which this stats is being logged */
+    wmi_mac_addr peer_mac_addr;
+    /* The timestamp at which the WMI event is reported. */
+    A_UINT32 timestamp;
+    /* Last known RSSI */
+    A_INT32 rssi; /* dBm units */
+    /* Peer Dialog token */
+    A_UINT32 peer_dialog_token;
+} wmi_tdls_connect_info_stats;
+
+/* max MCS counters supported for enhance stats */
+#define WMI_ENHANCE_STATS_MAX_MCS_COUNTERS 16
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     *  WMITLV_TAG_STRUC_wmi_tdls_data_stats */
+    A_UINT32 tlv_header;
+    /* Current operating channel frequency */
+    A_UINT32 op_freq_mhz;
+    /* Peer MAC address for which this stats is being logged */
+    wmi_mac_addr peer_mac_addr;
+    /* The timestamp at which the WMI event is reported. */
+    A_UINT32 timestamp;
+    /* Last known RSSI */
+    A_INT32  rssi; /* dBm units */
+    /* Last Tx Data rate */
+    A_UINT32 data_rate;
+    /* tx_ppdus_cumulative:
+     * Total PPDUs Tx-ed combining all the MCS rates over the last 15 secs
+     */
+    A_UINT32 tx_ppdus_cumulative;
+    /* tx_mcs_data_ppdu:
+     * PPDUs Txed over each MCS rate for all the supported MCS
+     * over the last 15 secs
+     */
+    A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS];
+    /* Total PPDU Tx failures seen over the last 15 secs */
+    A_UINT32 tx_ppdu_failures;
+    /* Total PPDUs Rx-ed combining all the MCS rates over the last 15 secs */
+    A_UINT32 rx_ppdus_cumulative;
+    /* rx_mcs_data_ppdu:
+     * PPDUs Rxed over each MCS rate for all the supported MCS
+     * over the last 15 secs
+     */
+    A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS];
+    /* Total Rx PPDU failures seen over the last 15 secs */
+    A_UINT32 rx_ppdu_failures;
+} wmi_tdls_data_stats;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     *  WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** VDEV identifier */
+    A_UINT32 vdev_id;
+    /* Total TDLS Peers this VDEV is connected to */
+    A_UINT32 peer_cnt;
+} wmi_tdls_stats_event_fixed_param;
+
 /**
  *  PDEV statistics
  *
@@ -39838,6 +39939,16 @@ typedef struct {
     A_UINT32 reset_after_request;
 } wmi_request_radio_chan_stats_cmd_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** VDEV identifier */
+    A_UINT32 vdev_id;
+    /* flag to enable or disable this feature of getting TDLS stats */
+    A_UINT32 enable;
+} wmi_request_tdls_stats_cmd_fixed_param;
+
 typedef struct {
     /** TLV tag and len; tag equals
      * WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param */
@@ -42556,6 +42667,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID);
         WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID);
         WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID);
+        WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -49354,9 +49466,6 @@ typedef struct {
 /* max beacon bmiss bitmask array size, in 32-bit words */
 #define WMI_MAX_BCN_BMISS_HISTORY_LENGTH 8
 
-/* max MCS counters supported for enhance stats */
-#define WMI_ENHANCE_STATS_MAX_MCS_COUNTERS 16
-
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_beacon_stats */
     A_UINT32 vdev_id; /* ID of the vdev these beacon stats are from */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8641a3f2f8f0..7bbcf4d9d426 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1745
+#define __WMI_REVISION_ 1746
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c8bb175e77fd9f85bdc0a31d88958a9c6252b4df Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 18 Apr 2026 18:03:52 -0700
Subject: [PATCH 217/290] fw-api: CL 32292001 - update fw common interface
 files

Change-Id: I74c9702b6b2dc9b0035965d401b0d4fcf0aa080b
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 1 +
 fw/wmi_unified.h  | 9 +++++++++
 fw/wmi_version.h  | 2 +-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 9d606f3a3792..c695991c37f3 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -786,6 +786,7 @@ typedef  enum  {
      * used for sending TDLS connect info and TDLS data stats
      */
     WMI_SERVICE_TDLS_STATS_SUPPORT = 502,
+    WMI_SERVICE_L3_HEADER_PADDING_ENABLE = 503,
 
 
     WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 57f59038b254..7c012d81d489 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10643,6 +10643,8 @@ typedef enum {
 
     /* Set TAS mode after boot up */
     WMI_PDEV_PARAM_SET_TAS_MODE,
+
+    WMI_PDEV_PARAM_L3_HEADER_PADDING_ENABLE,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -16164,6 +16166,13 @@ typedef struct {
      * Takes values from enum wmi_tdls_connect_info_stats_subtype.
      */
     A_UINT32 subtype;
+    /* status:
+     * Completion status of this frame, required only for Tx frames
+     * to know if frame is sent out successfully
+     *     0 - status is success
+     *     1 - status is failure
+     */
+    A_UINT32 status;
     /* reason_code:
      * Reason code for the reason of sending this TLV, eg. for TDLS
      * channel switch req/resp or for BT running indication
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7bbcf4d9d426..d002839c85a7 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1746
+#define __WMI_REVISION_ 1747
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 4c05beb0cbb10913921f95324beef1ee836d20c7 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 19 Apr 2026 18:01:55 -0700
Subject: [PATCH 218/290] fw-api: CL 32293073 - update fw common interface
 files

Change-Id: I6c686eac7382057e00cbee2cb75f51238e67f292
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 7c012d81d489..20878d98403d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10645,6 +10645,9 @@ typedef enum {
     WMI_PDEV_PARAM_SET_TAS_MODE,
 
     WMI_PDEV_PARAM_L3_HEADER_PADDING_ENABLE,
+
+    /* To enable/ disable beacon LIO update based on screen on/off */
+    WMI_PDEV_PARAM_BEACON_LIO_UPDATE_ON_SCREEN_ON_OFF,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d002839c85a7..7b5ae00f738b 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1747
+#define __WMI_REVISION_ 1748
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 25745e135b776f39a51b16d2673026eff785584a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 19 Apr 2026 18:03:51 -0700
Subject: [PATCH 219/290] fw-api: CL 32294648 - update fw common interface
 files

Change-Id: I845d113813f1792479479ad4aa4ece738afa6317
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 16 ++++++++++++++++
 fw/wmi_unified.h  | 26 ++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 690b606aface..0c168ba4914c 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1621,6 +1621,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats,
     WMITLV_TAG_STRUC_wmi_tdls_data_stats,
+    WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2227,6 +2229,7 @@ typedef enum {
     OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \
     OP(WMI_PEER_UHR_OMP_CMDID) \
     OP(WMI_REQUEST_TDLS_STATS_CMDID) \
+    OP(WMI_GET_CHIPSET_LOGGING_STATS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2593,6 +2596,7 @@ typedef enum {
     OP(WMI_NDP_CHANNEL_INFO_EVENTID) \
     OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \
     OP(WMI_TDLS_STATS_EVENTID) \
+    OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -3423,6 +3427,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID);
 
 WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLM_STATS_CMDID);
 
+/* Get chipset debug log stats Cmd */
+#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param, wmi_get_chipset_logging_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_CMDID);
+
 /* Network list offload config Cmd */
 #define WMITLV_TABLE_WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -8859,6 +8869,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, wmi_nan_dfs_channel_availability_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID);
 
+/* Chipset debug log stats event */
+#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param, wmi_get_chipset_logging_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 20878d98403d..68e2b7d1e162 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -374,6 +374,7 @@ typedef enum {
     WMI_GRP_MANUAL_UL_TRIG, /* 0x4d Manual UL OFDMA Trigger */
     WMI_GRP_ENERGY_MGMT,    /* 0x4e energy management */
     WMI_GRP_SMD,            /* 0x4f SMD Roaming */
+    WMI_GRP_CHIPSET_LOG     /* 0x50 Chipset Debug Logging */
 } WMI_GRP_ID;
 
 #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -1860,6 +1861,9 @@ typedef enum {
      * (Combine PeerCreate,Assoc, Key Install)
      */
     WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID,
+
+    /** WMI command for host to request chipset debug log stats from FW */
+    WMI_GET_CHIPSET_LOGGING_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CHIPSET_LOG),
 } WMI_CMD_ID;
 
 typedef enum {
@@ -2856,6 +2860,9 @@ typedef enum {
     WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID,
 
     WMI_ENERGY_MGMT_OEM_DATA_EVENTID =WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT),
+
+    /** WMI event to send chipset debug log stats to host */
+    WMI_GET_CHIPSET_LOGGING_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHIPSET_LOG),
 } WMI_EVT_ID;
 
 /* defines for OEM message sub-types */
@@ -42680,6 +42687,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID);
         WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID);
         WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID);
+        WMI_RETURN_STRING(WMI_GET_CHIPSET_LOGGING_STATS_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -55946,6 +55954,24 @@ typedef struct {
     A_UINT32 rx_chains;
 } wmi_vdev_current_operating_param_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param */
+    /** unique id identifying the request */
+    A_UINT32 request_id;
+} wmi_get_chipset_logging_stats_cmd_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param */
+    /** unique id identifying the request */
+    A_UINT32 request_id;
+    /** length in bytes of the chipset log stats data */
+    A_UINT32 data_len;
+    /**
+     * Following this structure is the TLV:
+     * A_UINT8 data[]; <-- chipset log stats data, length given by data_len
+     */
+} wmi_get_chipset_logging_stats_event_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7b5ae00f738b..b11c619ceda6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1748
+#define __WMI_REVISION_ 1749
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 36119b3358156928282ca8a775d1b915eae82faa Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Mon, 20 Apr 2026 18:01:53 -0700
Subject: [PATCH 220/290] fw-api: CL 32296279 - update fw common interface
 files

Change-Id: I5d231a041d538decf82764104b99b29233217a58
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 68e2b7d1e162..6a75f2c6d033 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10655,6 +10655,12 @@ typedef enum {
 
     /* To enable/ disable beacon LIO update based on screen on/off */
     WMI_PDEV_PARAM_BEACON_LIO_UPDATE_ON_SCREEN_ON_OFF,
+
+    /**
+     * Configure the CSA wait timeout (in ms) before blocking TX
+     * after radar detection
+     */
+    WMI_PDEV_PARAM_DFS_NOL_CSA_WAIT_TIMEOUT,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b11c619ceda6..9917bd5d5000 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1749
+#define __WMI_REVISION_ 1750
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 71d5d69082e1a5f2e6b6d42c0993f7961f5c9b15 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 21 Apr 2026 06:01:46 -0700
Subject: [PATCH 221/290] fw-api: CL 32306378 - update fw common interface
 files

Change-Id: I37d2c1dbc11ece51f2ee34ba5161966bedc45126
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 1 +
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6a75f2c6d033..db40ee11da07 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -35068,6 +35068,7 @@ typedef struct {
     /* picks protocol type from WMI_USD_SERVICE_PROTOCOL_TYPE */
     A_UINT32 protocol_type;
     wmi_mac_addr device_mac_addr;
+    wmi_mac_addr multicast_addr;
 } wmi_usd_service_cmd_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9917bd5d5000..be7a18a0f0b8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1750
+#define __WMI_REVISION_ 1751
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 38f771a775abdb163c06b791a29d1c7cb640dcaf Mon Sep 17 00:00:00 2001
From: Vedant Yevale <vyevale@qti.qualcomm.com>
Date: Fri, 22 Aug 2025 14:32:54 +0530
Subject: [PATCH 222/290] disp: msm: dsi: Nullify display modes after kfree

The 'display->modes' pointer must be set to NULL immediately
after calling kfree on it to prevent potential double-free
vulnerabilities or use-after-free issues.

This change ensures robust memory management by clearing the
pointer to previously freed memory, aligning with best practices
for kernel memory deallocation.

Change-Id: I4fd939bc6ee5f3d9c506f0c311a9400f366e7fd2
Signed-off-by: Vedant Yevale <vyevale@qti.qualcomm.com>
(cherry picked from commit 1d3c5a477ea8f6aca1158209e1b87209c21c61f5)
---
 msm/dsi/dsi_display.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c
index 38c478f94641..3de65e4d9170 100644
--- a/msm/dsi/dsi_display.c
+++ b/msm/dsi/dsi_display.c
@@ -7168,8 +7168,10 @@ exit:
 	rc = 0;
 
 error:
-	if (rc)
+	if (rc) {
 		kfree(display->modes);
+		display->modes = NULL;
+	}
 
 	mutex_unlock(&display->display_lock);
 	return rc;

From f1b2a6fc4bf691c35aa5e442572399fc6d80466b Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 22 Apr 2026 18:01:34 -0700
Subject: [PATCH 223/290] fw-api: CL 32320410 - update fw common interface
 files

Change-Id: Ib23b588140dbd0ed3b67dce70ef172f96c8a42ca
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 5 -----
 fw/wmi_version.h | 2 +-
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index db40ee11da07..0becb5697451 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -14812,11 +14812,6 @@ typedef struct {
      */
     A_UINT32 payload_clear_count;
 
-    /*
-     * Received payload count from HOST
-     */
-    A_UINT32 payload_received_count;
-
     /*
      * payload parsing failure count due to platform memory alloc failure
      */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index be7a18a0f0b8..b3a843ab5e9d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1751
+#define __WMI_REVISION_ 1752
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From a7ba7bc1bfe52d6dadb009daecc258a39bb86a54 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 22 Apr 2026 18:03:31 -0700
Subject: [PATCH 224/290] fw-api: CL 32322205 - update fw common interface
 files

Change-Id: I99b9ebd39ab152ca39aba681b9afbc07b8daf2f6
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 7 +++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 0becb5697451..ec6551ba3e77 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -31696,6 +31696,13 @@ typedef struct {
         A_UINT32 nan_ctrl_flags; /* 32-bit control flags word */
     };
     A_UINT32 supp_disc_bands; /* Possible values are enum WMI_NAN_DISC_BANDS */
+    /* warmup_timer_value:
+     * NANWarmUp timer value in seconds, to be used when starting
+     * a NAN cluster as part of NAN enablement.
+     * If warmup_timer_value == 0, target needs to use default 120 sec,
+     * as mentioned in spec.
+     */
+    A_UINT32 warmup_timer_value;
 /*
 * TLVs following this structure:
 *     wmi_nan_disc_band_config_param nan_disc_band_config[];
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b3a843ab5e9d..bc854d101c4a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1752
+#define __WMI_REVISION_ 1753
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 0117d737f3053be0cefe5be0aa62644b70ecd627 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 22 Apr 2026 18:08:33 -0700
Subject: [PATCH 225/290] fw-api: CL 32323534 - update fw common interface
 files

Change-Id: Id86af687cec500279d4b1d37b42cbb3bf3736fd9
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 5bd300678e6f..d94e7c8392ab 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -5283,6 +5283,11 @@ typedef struct {
     A_UINT32 user_index;
     /** HTT_STATS_TX_SCHED_MODE_xxx */
     A_UINT32 tx_sched_mode;
+    /**
+     * Wi-Fi version identifier to differentiate stats while printing
+     * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value).
+     */
+    A_UINT32 wifi_version;
 } htt_stats_tx_pdev_mpdu_stats_tlv;
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv;

From f6e3b8233d546bbd5cfc468d3e07ae81e9c1b9df Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 24 Apr 2026 18:04:13 -0700
Subject: [PATCH 226/290] fw-api: CL 32335202 - update fw common interface
 files

Change-Id: I2fe1a9b9f4b343760b51134c6fa3afdc05e3fa74
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 11 +++++++++++
 fw/wmi_unified.h  | 47 +++++++++++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 3 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index c695991c37f3..ba2551604936 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -788,6 +788,17 @@ typedef  enum  {
     WMI_SERVICE_TDLS_STATS_SUPPORT = 502,
     WMI_SERVICE_L3_HEADER_PADDING_ENABLE = 503,
 
+    /*
+     * Indicates FW supports only known action ids and discards
+     * saving any unknown action ids
+     */
+    WMI_SERVICE_SUPPORT_KNOWN_ACTION_IDS = 504,
+    /*
+     * Indicates FW supports cloud based control for whitelist or blacklist
+     * AP configuration
+     */
+    WMI_SERVICE_SUPPORT_WHITELIST_BLACKLIST_AP_CONFIG = 505,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ec6551ba3e77..09474ac7779f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -28383,6 +28383,9 @@ typedef struct {
 #define WMI_MAX_VENDOR_OUI_ACTION_SUPPORTED_PER_ACTION 10
 #define WMI_MAX_VENDOR_OUI_DATA_LENGTH                 20
 
+#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_ALLOW_DISALLOW_NSS 30
+#define WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH                     64
+
 typedef enum
 {
     WMI_VENDOR_OUI_ACTION_CONNECTION_1X1 = 0, /* Connect in 1X1 only */
@@ -28474,7 +28477,25 @@ typedef enum
 
 
     /* Add any action before this line */
-    WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
+    WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID,
+
+
+    /*
+     * 0-127 is reserved for action IDs for which the data is static.
+     * Size of the data is fixed and is not configurable.
+     */
+
+    /* Dynamic length OUIs starts below */
+
+    /* connection in 4 x 4 */
+    WMI_VENDOR_OUI_ACTION_ALLOW_NSS_GREATER_THAN_2 = 128,
+
+    /* connection in 2 x 2 */
+    WMI_VENDOR_OUI_ACTION_DISALLOW_NSS_GREATER_THAN_2 = 129,
+
+
+    /* Add any new dynamic length action ID before this line */
+    WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID
 } wmi_vendor_oui_action_id;
 
 typedef struct {
@@ -28484,6 +28505,25 @@ typedef struct {
     A_UINT32 total_num_vendor_oui; /* total number of OUI present in ini for all actions.
                                    ** For first command, this value will be used for allocating memory in FW accordingly */
     A_UINT32 num_vendor_oui_ext; /* the number of wmi_vendor_oui_ext for action_id */
+    /* total_num_vendor_oui_ext:
+     * Max possible OUIs which HOST can support for all the extended
+     * ACTION IDs: WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_*.
+     * The max ext action id should be less than
+     * WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID and greater than
+     * WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
+     */
+    A_UINT32 total_num_vendor_oui_ext;
+    /* num_vendor_oui_ext2:
+     * The number of wmi_vendor_oui_ext_2 for action_id
+     * (The number of OUIs that HOST could accomodate in current WMI cmd)
+     */
+    A_UINT32 num_vendor_oui_ext2;
+    /*
+     * More data indicates that for this action_id, there are more data
+     * pending to be sent via the next WMI command.
+     */
+    A_UINT32 more_data;
+
     /* followed by TLVs, an array of structure of type wmi_vendor_oui_ext
     ** wmi_vendor_oui_ext vendor_oui_ext[num_vendor_oui_ext];
     */
@@ -28548,7 +28588,10 @@ typedef struct _wmi_vendor_oui_ext {
 
     /* oui_data_length:
      * Length of oui_data to compare in beacon which follows OUI header.
-     * Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes.
+     * Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes,
+     * for action ids < 127.
+     * Max length is capped to WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH bytes,
+     * for action ids > 127.
      */
     A_UINT32 oui_data_length;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index bc854d101c4a..cae5a8cfdb1c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1753
+#define __WMI_REVISION_ 1754
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From cb9a0a40dbc2f8088d23ca2f1d3dcc71175d23db Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 25 Apr 2026 18:01:42 -0700
Subject: [PATCH 227/290] fw-api: CL 32356331 - update fw common interface
 files

Change-Id: I2cd3b4f5339e5278d7291da5615352e1c6a9831a
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index ba2551604936..3b296eb6e8e0 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -798,7 +798,11 @@ typedef  enum  {
      * AP configuration
      */
     WMI_SERVICE_SUPPORT_WHITELIST_BLACKLIST_AP_CONFIG = 505,
-
+    /*
+     * Indicate FW support for PASSTHRU VDEV AMPDU Aggregation
+     * and Rate Adaptation
+     */
+    WMI_SERVICE_PASSTHRU_VDEV_AMPDU_RA_SUPPORT = 506,
 
     WMI_MAX_EXT2_SERVICE
 

From ea3b788227661afd32d9100f5cc0d37114030379 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Mon, 27 Apr 2026 18:01:41 -0700
Subject: [PATCH 228/290] fw-api: CL 32362944 - update fw common interface
 files

Change-Id: I1d0e39d8acc96a951c9c3820e4462be465296709
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 3b296eb6e8e0..543b95adb8b9 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -803,6 +803,9 @@ typedef  enum  {
      * and Rate Adaptation
      */
     WMI_SERVICE_PASSTHRU_VDEV_AMPDU_RA_SUPPORT = 506,
+    /* FW supports CalDB transmission over WMI */
+    WMI_SERVICE_CALDB_OVER_WMI = 507,
+
 
     WMI_MAX_EXT2_SERVICE
 

From eb0e117a36ae7272042deefdd6b82afbdd03996a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 29 Apr 2026 18:01:54 -0700
Subject: [PATCH 229/290] fw-api: CL 32387418 - update fw common interface
 files

Change-Id: I5584f2694327b570594a95f74eb54082dd7eada1
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 13 +++++++
 fw/wmi_unified.h  | 94 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 108 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 0c168ba4914c..f3495352f26c 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1623,6 +1623,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_tdls_data_stats,
     WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_anomaly_report_hdr,
+    WMITLV_TAG_STRUC_wmi_anomaly_entry_t,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2597,6 +2599,7 @@ typedef enum {
     OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \
     OP(WMI_TDLS_STATS_EVENTID) \
     OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \
+    OP(WMI_ANOMALY_REPORT_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -8774,6 +8777,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_ac_info, vdev_ac_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID);
 
+/* WMI Anomaly Report Event */
+#define WMITLV_TABLE_WMI_ANOMALY_REPORT_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, \
+        WMITLV_TAG_STRUC_wmi_anomaly_report_hdr, \
+        wmi_anomaly_report_hdr, hdr, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, \
+        WMITLV_TAG_ARRAY_STRUC, \
+        wmi_anomaly_entry_t, entries, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ANOMALY_REPORT_EVENTID);
+
 #define WMITLV_TABLE_WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, wmi_pdev_set_tx_chainmask_comp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID);
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 09474ac7779f..72e0c9c04ce5 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2448,6 +2448,9 @@ typedef enum {
     /* TDLS Stats event having TDLS connect info and data stats */
     WMI_TDLS_STATS_EVENTID,
 
+    /** WMI Anomaly Report Event — single event ID for all FW anomaly types */
+    WMI_ANOMALY_REPORT_EVENTID,
+
 
     /* NLO specific events */
     /** NLO match event after the first match */
@@ -56024,6 +56027,97 @@ typedef struct {
      */
 } wmi_get_chipset_logging_stats_event_fixed_param;
 
+/* -----------------------------------------------------------------------
+ * TLV #1 — Message-level header
+ * ----------------------------------------------------------------------- */
+typedef struct {
+    A_UINT32 tlv_header;     /* WMITLV_TAG_STRUC_wmi_anomaly_report_hdr */
+    A_UINT32 pdev_id;        /* PDEV ID (common for all entries in batch) */
+} wmi_anomaly_report_hdr;
+
+/* -----------------------------------------------------------------------
+ * Per-Anomaly Context Sub-Structures (all fields A_UINT32 per WMI convention)
+ * ----------------------------------------------------------------------- */
+
+/*
+ * Context for WMI_ANOMALY_ID_VDEV_DELETE_REQUESTED_BEFORE_STOP
+ * (ID 0000–0999)
+ */
+typedef struct {
+    A_UINT32 vdev_state; /* Internal VDEV state at time of fault */
+    A_UINT32 vdev_type;  /* VDEV type (AP/STA/IBSS/etc.) */
+} wmi_anomaly_vdev_ctx_t;
+
+/*
+ * Context for WMI_ANOMALY_ID_DELETE_VDEV_BEFORE_DELETING_ALL_PEERS
+ * (ID 1000–1999)
+ */
+typedef struct {
+    A_UINT32 peer_count; /* Number of peers still associated */
+    /* MAC address of first offending peer (lower 32 bits) */
+    A_UINT32 peer_mac_addr_lo;
+    /* MAC address of first offending peer (upper 16 bits) */
+    A_UINT32 peer_mac_addr_hi;
+    A_UINT32 peer_state; /* Internal peer state at time of fault */
+} wmi_anomaly_peer_ctx_t;
+
+/*
+ * Context for WMI_ANOMALY_ID_BEACON_TEMPLATE_SANITY_FAILED
+ * (ID 2000–2999)
+ */
+typedef struct {
+    A_UINT32 bcn_buf_len;     /* Beacon buffer length that was received */
+    A_UINT32 max_allowed_len; /* Maximum allowed beacon buffer length */
+    A_UINT32 ie_offset;       /* IE offset at which sanity failed */
+    A_UINT32 fail_reason;     /* Internal reason code for the failure */
+} wmi_anomaly_beacon_ctx_t;
+
+/*
+ * Context for halPhy bucket groups
+ * (ID 5000–9999)
+ */
+typedef struct {
+    A_UINT32 phy_err_code; /* Hardware PHY error code at fault time */
+    A_UINT32 chain_mask;   /* Active RX/TX chain mask at fault time */
+    A_UINT32 cal_step;     /* Calibration step index; 0 if not applicable */
+    A_UINT32 hw_status;    /* Raw hardware status register snapshot */
+} wmi_anomaly_halphy_ctx_t;
+
+/*
+ * Context for uCode bucket groups
+ * (ID 10000–14999)
+ */
+typedef struct {
+    A_UINT32 ucode_pc;       /* uCode program counter at fault time */
+    A_UINT32 sched_state;    /* Scheduler state machine value at fault time */
+    A_UINT32 txrx_status;    /* TX/RX pipeline status register snapshot */
+    A_UINT32 watchdog_count; /* Watchdog expiry count since last reset */
+} wmi_anomaly_ucode_ctx_t;
+
+/* -----------------------------------------------------------------------
+ * TLV #2 — Per-Anomaly Entry (ARRAY_STRUC element)
+ * anomaly_id is the discriminant — tells host which union member is valid.
+ * ----------------------------------------------------------------------- */
+typedef struct {
+    A_UINT32 tlv_header;     /* WMITLV_TAG_STRUC_wmi_anomaly_entry_t */
+    A_UINT32 anomaly_id;     /* [31:1]=WMI_ANOMALY_ID  [0]=type(0=A/1=E) */
+    A_UINT32 vdev_id;        /* Virtual Device ID (0xFFFFFFFF if N/A) */
+    A_UINT32 priority;       /* WMI_ANOMALY_PRIORITY */
+    A_UINT32 related_cmd_id; /* WMI_CMD_ID (0 if N/A) */
+    A_UINT32 reserved[2];    /* for future use when needed */
+    union {
+        wmi_anomaly_vdev_ctx_t   vdev;    /* ID 0000–0999 */
+        wmi_anomaly_peer_ctx_t   peer;    /* ID 1000–1999 */
+        wmi_anomaly_beacon_ctx_t beacon;  /* ID 2000–2999 */
+        wmi_anomaly_halphy_ctx_t halphy;  /* ID 5000–9999 */
+        wmi_anomaly_ucode_ctx_t  ucode;   /* ID 10000–14999 */
+    } ctx;
+    /* NOTE:
+     * No new fields can be added here - this restriction allows new fields
+     * to be added to the end of the wmi_anomaly_xxx_ctx_t structs instead.
+     */
+} wmi_anomaly_entry_t;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index cae5a8cfdb1c..2edafa8e2805 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1754
+#define __WMI_REVISION_ 1755
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 486d7b2d1ef29c77bcc25153a1801ca746524e55 Mon Sep 17 00:00:00 2001
From: Mandar Mahesh Kamble <maheshka@qti.qualcomm.com>
Date: Wed, 11 Dec 2024 15:03:38 +0530
Subject: [PATCH 230/290] tty: msm: Update timer handling for interrupt-safe
 context

Modified timer handling to address recent updates in
del_timer_sync() behavior. The function is not permitted to be invoked
from interrupt context unless the timer is marked with TIMER_IRQSAFE.
To ensure compliance and avoid potential race conditions, the affected
timer is now explicitly marked with TIMER_IRQSAFE.

Change-Id: I5724f4172e6576ba2f0cce5e383d76dbdb0ce637
Signed-off-by: Mandar Mahesh Kamble <maheshka@qti.qualcomm.com>
---
 drivers/tty/serial/msm_serial_hs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index cfee5b5799b6..47c50bb1eef3 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -2684,7 +2684,7 @@ static int msm_hs_startup(struct uart_port *uport)
 	tx->dma_in_flight = false;
 	MSM_HS_DBG("%s():desc usage flag 0x%lx\n", __func__, rx->queued_flag);
 	timer_setup(&(tx->tx_timeout_timer),
-			tx_timeout_handler, 0);
+			tx_timeout_handler, TIMER_IRQSAFE);
 
 	/* Enable reading the current CTS, no harm even if CTS is ignored */
 	msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;

From 8314ce5fdc69ea03cd3504019ef15791f4b80db2 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 30 Apr 2026 06:58:55 -0700
Subject: [PATCH 231/290] fw-api: CL 32397726 - update fw common interface
 files

Change-Id: I37120efd1592e9011a0fd6ad3be59557db6ce600
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 543b95adb8b9..ebcf53298474 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -788,11 +788,9 @@ typedef  enum  {
     WMI_SERVICE_TDLS_STATS_SUPPORT = 502,
     WMI_SERVICE_L3_HEADER_PADDING_ENABLE = 503,
 
-    /*
-     * Indicates FW supports only known action ids and discards
-     * saving any unknown action ids
-     */
-    WMI_SERVICE_SUPPORT_KNOWN_ACTION_IDS = 504,
+    /* Indicates FW supports Extended OUI Action IDs */
+    WMI_SERVICE_SUPPORTED_EXT_OUI_ACTION_IDS = 504,
+
     /*
      * Indicates FW supports cloud based control for whitelist or blacklist
      * AP configuration

From 1a9ce1b3308f45dd0167d1e93e7b8f162e02e8d5 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 30 Apr 2026 07:00:56 -0700
Subject: [PATCH 232/290] fw-api: CL 32397731 - update fw common interface
 files

Change-Id: I2e0c04b7be6c047e88400de5ef185900a703532e
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 15 ++++++++++++---
 fw/wmi_version.h |  2 +-
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 72e0c9c04ce5..b15c15df8ff1 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5256,10 +5256,13 @@ typedef struct {
      *  Bit 29 - enable ipi_stats feature:
      *      0 -> disable the feature
      *      1 -> enable the feature
-     *     Refer to below WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET/SET
-     *     macros.
+     *     Refer to below WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET/SET macros.
+     * Bit 30 - enable pcie_oob_wakeup feature:
+     *      0 -> disable the feature
+     *      1 -> enable the feature
+     *     Refer to below WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET/SET macros.
      *
-     *  Bits 31:30 - Reserved
+     *  Bit 31 - Reserved
      */
     A_UINT32 flags2;
     /** @brief host_service_flags - can be used by Host to indicate
@@ -5908,6 +5911,12 @@ typedef struct {
 #define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_SET(flags2, value) \
     WMI_SET_BITS(flags2, 29, 1, value)
 
+#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET(flags2) \
+    WMI_GET_BITS(flags2, 30, 1)
+#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_SET(flags2, value) \
+    WMI_SET_BITS(flags2, 30, 1, value)
+
+
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
     WMI_GET_BITS(host_service_flags, 0, 1)
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_SET(host_service_flags, val) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 2edafa8e2805..40257ddf3472 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1755
+#define __WMI_REVISION_ 1756
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 2b1f7f09c8e7b390cf6269122f7428946ecdcdf9 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 30 Apr 2026 07:02:49 -0700
Subject: [PATCH 233/290] fw-api: CL 32402810 - update fw common interface
 files

Change-Id: I8b13011f540ab3832ca932067e8c2b52d02bca02
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index d94e7c8392ab..f2d50d3ebede 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -3980,6 +3980,9 @@ typedef struct {
     A_UINT32 sta_dps_bn_bsr_trigger_err[HTT_NUM_AC_WMM];
     /** 11bn UHR MU RTS trigger to DPS client completed with errors(s) */
     A_UINT32 sta_dps_bn_mu_rts_trigger_err[HTT_NUM_AC_WMM];
+
+    /** 11BN UHR UL OFDMA RU allocation mode - trigger error count */
+    A_UINT32 bn_basic_trig_ru_alloc_mode_err[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES];
 } htt_stats_tx_selfgen_bn_tlv;
 
 typedef struct { /* DEPRECATED */

From 67e61c3081543bf46794f4c3f6afe5dd740bd2ed Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 30 Apr 2026 07:04:43 -0700
Subject: [PATCH 234/290] fw-api: CL 32402817 - update fw common interface
 files

Change-Id: I090be2dadd25095e61b5a3fdfcacec68674461b8
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |   4 +-
 fw/wmi_unified.h  | 111 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 115 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index f3495352f26c..dffa14356f79 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1625,6 +1625,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_anomaly_report_hdr,
     WMITLV_TAG_STRUC_wmi_anomaly_entry_t,
+    WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -3207,7 +3208,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID);
 
 #define WMITLV_TABLE_WMI_PEER_UHR_OMP_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, wmi_peer_uhr_omp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_npca_params, peer_omp_npca_params, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_npca_params, peer_omp_npca_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_sta_dps_params, peer_omp_dps_params, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_OMP_CMDID);
 
 /* Peer Set Rate Report Condition Cmd */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b15c15df8ff1..09bc704c8ccf 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -23955,6 +23955,117 @@ typedef struct{
 #define WMI_OMP_NPCA_SWITCH_BACK_DELAY_SET(_var, _val) \
     WMI_SET_BITS(_var, 6, 6, _val)
 
+
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params */
+
+    /*
+     * Bit0:3:  STA DPS hw_link_id
+     *          WMI_OMP_STA_DPS_HW_LINK_ID_GET / _SET
+     * Bit4:    Enable/Disable STA DPS params
+     *          WMI_OMP_STA_DPS_ENABLE_GET / _SET
+     * Bit5:    Update STA DPS params
+     *          WMI_OMP_STA_DPS_UPDATE_GET / _SET
+     * Bit6:31: Reserved
+     */
+    A_UINT32 omp_sta_dps_caps;
+
+    /*
+     * Bit0:5:   STA DPS Padding Delay
+     *           WMI_OMP_STA_DPS_PADDING_DELAY_GET / _SET
+     *
+     * Bit6:7:   Reserved
+     *
+     * Bit8:13:  STA DPS Transition Delay
+     *           WMI_OMP_STA_DPS_TRANSITION_DELAY_GET / _SET
+     *
+     * Bit14:15: Reserved
+     *
+     * Bit16:    ICF Required
+     *           WMI_OMP_STA_DPS_ICF_REQUIRED_GET / _SET
+     *
+     * Bit17:    Parameterized Mode
+     *           WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET / _SET
+     *
+     * Bit18:20: LC Mode Bandwidth
+     *           WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET / _SET
+     *           0  :  20  MHz
+     *           1  :  40  MHz
+     *           2  :  80  MHz
+     *           3  : 160  MHz
+     *           4  : 320  MHz
+     *           5-7: Reserved
+     *
+     * Bit21:24: LC Mode NSS
+     *           WMI_OMP_STA_DPS_LC_MODE_NSS_GET / _SET
+     *
+     * Bit25:28: LC Mode MCS
+     *           WMI_OMP_STA_DPS_LC_MODE_MCS_GET / _SET
+     *
+     * Bit29:    Mobile AP STA DPS Static HCM
+     *           WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET / _SET
+     *
+     * Bit30:31: Reserved
+     */
+    A_UINT32 omp_sta_dps_param;
+} wmi_peer_uhr_omp_sta_dps_params;
+
+#define WMI_OMP_STA_DPS_HW_LINK_ID_GET(_var) \
+    WMI_GET_BITS(_var, 0, 4)
+#define WMI_OMP_STA_DPS_HW_LINK_ID_SET(_var, _val) \
+    WMI_SET_BITS(_var, 0, 4, _val)
+
+#define WMI_OMP_STA_DPS_ENABLE_GET(_var) \
+    WMI_GET_BITS(_var, 4, 1)
+#define WMI_OMP_STA_DPS_ENABLE_SET(_var, _val) \
+    WMI_SET_BITS(_var, 4, 1, _val)
+
+#define WMI_OMP_STA_DPS_UPDATE_GET(_var) \
+    WMI_GET_BITS(_var, 5, 1)
+#define WMI_OMP_STA_DPS_UPDATE_SET(_var, _val) \
+    WMI_SET_BITS(_var, 5, 1, _val)
+
+#define WMI_OMP_STA_DPS_PADDING_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 0, 6)
+#define WMI_OMP_STA_DPS_PADDING_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 0, 6, _val)
+
+#define WMI_OMP_STA_DPS_TRANSITION_DELAY_GET(_var) \
+    WMI_GET_BITS(_var, 8, 6)
+#define WMI_OMP_STA_DPS_TRANSITION_DELAY_SET(_var, _val) \
+    WMI_SET_BITS(_var, 8, 6, _val)
+
+#define WMI_OMP_STA_DPS_ICF_REQUIRED_GET(_var) \
+    WMI_GET_BITS(_var, 16, 1)
+#define WMI_OMP_STA_DPS_ICF_REQUIRED_SET(_var, _val) \
+    WMI_SET_BITS(_var, 16, 1, _val)
+
+#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET(_var) \
+    WMI_GET_BITS(_var, 17, 1)
+#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_SET(_var, _val) \
+    WMI_SET_BITS(_var, 17, 1, _val)
+
+#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET(_var) \
+    WMI_GET_BITS(_var, 18, 3)
+#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_SET(_var, _val) \
+    WMI_SET_BITS(_var, 18, 3, _val)
+
+#define WMI_OMP_STA_DPS_LC_MODE_NSS_GET(_var) \
+    WMI_GET_BITS(_var, 21, 4)
+#define WMI_OMP_STA_DPS_LC_MODE_NSS_SET(_var, _val) \
+    WMI_SET_BITS(_var, 21, 4, _val)
+
+#define WMI_OMP_STA_DPS_LC_MODE_MCS_GET(_var) \
+    WMI_GET_BITS(_var, 25, 4)
+#define WMI_OMP_STA_DPS_LC_MODE_MCS_SET(_var, _val) \
+    WMI_SET_BITS(_var, 25, 4, _val)
+
+#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET(_var) \
+    WMI_GET_BITS(_var, 29, 1)
+#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_SET(_var, _val) \
+    WMI_SET_BITS(_var, 29, 1, _val)
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */
     A_UINT32 vdev_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 40257ddf3472..22e2b0191a00 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1756
+#define __WMI_REVISION_ 1757
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From f15e9c849c3b3394e2cc9f5263d94b405761753e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 3 May 2026 18:01:48 -0700
Subject: [PATCH 235/290] fw-api: CL 32412612 - update fw common interface
 files

 SCL original promoter: ddahlby (SCL=32409974)
WINE promoted user: yeshanit
WINE request id: 5876892

Jobs fixed ...

ChangeRequest4520747 on 2026/04/30 by prismsvc *closed*

Job created automatically by Orbit/PRISM to track changes for Change Request 4520747. Please visit https://orbit/CR/4520747 for details for the Change Request.

Affected files ...

... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/doc/wmi_doc.html#1092 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/doc/wmi_py/wmi_msg_lib.py#23 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_services.h#431 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_tlv_defs.h#660 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_tlv_defs_expanded.h#632 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_unified.h#1715 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_version.h#1710 edit

Change-Id: Iae047a9d29e856494e4c8d70289bbeb7584b6fe0
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   3 +-
 fw/wmi_tlv_defs.h |  29 ++-
 fw/wmi_unified.h  | 520 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 4 files changed, 551 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index ebcf53298474..d49fb574c7ec 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -803,7 +803,8 @@ typedef  enum  {
     WMI_SERVICE_PASSTHRU_VDEV_AMPDU_RA_SUPPORT = 506,
     /* FW supports CalDB transmission over WMI */
     WMI_SERVICE_CALDB_OVER_WMI = 507,
-
+    /* Indicates FW Supports RTT Proximity Detection (USD ranging) */
+    WMI_SERVICE_RTT_PD = 508,
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index dffa14356f79..34542191b8c1 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1626,6 +1626,12 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_anomaly_report_hdr,
     WMITLV_TAG_STRUC_wmi_anomaly_entry_t,
     WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2233,6 +2239,8 @@ typedef enum {
     OP(WMI_PEER_UHR_OMP_CMDID) \
     OP(WMI_REQUEST_TDLS_STATS_CMDID) \
     OP(WMI_GET_CHIPSET_LOGGING_STATS_CMDID) \
+    OP(WMI_RTT_PEER_MEAS_REQ_CMDID) \
+    OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2601,6 +2609,7 @@ typedef enum {
     OP(WMI_TDLS_STATS_EVENTID) \
     OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \
     OP(WMI_ANOMALY_REPORT_EVENTID) \
+    OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6481,6 +6490,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, wmi_pdev_set_cumac_chip_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_CMDID);
 
+/* RTT Peer measurement start request */
+#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REQ_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param, wmi_rtt_peer_meas_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_req_peer_info, peer_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REQ_CMDID);
+
+/* RTT Peer measurement cancel request */
+#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_CANCEL_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_CANCEL_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -6546,7 +6566,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_shared_mem_model_tbtt_count_down_config, shared_mem_model_tbtt_count_down_config, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_shared_mem_model_tbtt_count_down_config, shared_mem_model_tbtt_count_down_config, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_capabilities, rtt_peer_meas_caps, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
 
 #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
@@ -8890,6 +8911,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID);
 
+/* RTT Peer measurement report event */
+#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REPORT_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param, wmi_rtt_peer_meas_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_report_peer_meas_result_info, peer_meas_result_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REPORT_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 09bc704c8ccf..21241b42d99a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1212,6 +1212,10 @@ typedef enum {
     WMI_RTT_PASN_AUTH_STATUS_CMD,
     /** RTT 11az PASN deauthentication cmd */
     WMI_RTT_PASN_DEAUTH_CMD,
+    /** request to start peer measurement */
+    WMI_RTT_PEER_MEAS_REQ_CMDID,
+    /** request to cancel an ongoing peer measurement */
+    WMI_RTT_PEER_MEAS_CANCEL_CMDID,
 
     /** spectral scan command */
     /** configure spectral scan */
@@ -2379,6 +2383,8 @@ typedef enum {
     WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID,
     /** RTT 11az PASN peer delete event */
     WMI_RTT_PASN_PEER_DELETE_EVENTID,
+    /** RTT peer (Proximity Detection) measurement report */
+    WMI_RTT_PEER_MEAS_REPORT_EVENTID,
 
     /*STATS specific events*/
     /** txrx stats event requested by host */
@@ -4283,6 +4289,7 @@ typedef struct {
      *     WMI_MAC_PHY_CAPABILITIES_EXT2 mac_phy_caps2[];
      *     wmi_shared_mem_model_tbtt_count_down_config
      *         wmi_shared_mem_model_tbtt_count_down_config[];
+     *     wmi_rtt_peer_meas_capabilities rtt_peer_meas_caps[];
      */
 } wmi_service_ready_ext2_event_fixed_param;
 
@@ -56239,6 +56246,519 @@ typedef struct {
 } wmi_anomaly_entry_t;
 
 
+/* RTT Peer Measurement (Proximity Detection/Ranging) capabilities */
+
+/*
+ * macros to set/get bitfields within
+ * wmi_rtt_peer_meas_capabilities
+ */
+
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_GET(flags)  WMI_GET_BITS(flags, 0, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_GET(flags)  WMI_GET_BITS(flags, 1, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 2, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_GET(flags)  WMI_GET_BITS(flags, 3, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_GET(flags) WMI_GET_BITS(flags, 4, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value)
+
+#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_GET(flags) WMI_GET_BITS(flags, 0, 16)
+#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 0, 16, value)
+#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_GET(flags) WMI_GET_BITS(flags, 16, 16)
+#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 16, 16, value)
+
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 0, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 1, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 2, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 3, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 4, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 5, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 6, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 7, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 8, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 9, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_GET(flags)  WMI_GET_BITS(flags, 10, 1)
+#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 10, 1, value)
+
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_GET(caps)  WMI_GET_BITS(caps, 0, 8)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_SET(caps, value) WMI_SET_BITS(caps, 0, 8, value)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_GET(caps)  WMI_GET_BITS(caps, 8, 8)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_SET(caps, value) WMI_SET_BITS(caps, 8, 8, value)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_GET(caps)  WMI_GET_BITS(caps, 16, 8)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_GET(caps) WMI_GET_BITS(caps, 24, 8)
+#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_GET(params)  WMI_GET_BITS(params, 0, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 0, 3, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_GET(params)  WMI_GET_BITS(params, 3, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 3, 3, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_GET(params) WMI_GET_BITS(params, 6, 2)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 6, 2, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_GET(params)  WMI_GET_BITS(params, 8, 2)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 8, 2, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_GET(params)  WMI_GET_BITS(params, 10, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 10, 3, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_GET(params)  WMI_GET_BITS(params, 13, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 13, 3, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_GET(params)  WMI_GET_BITS(params, 16, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 16, 3, value)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_GET(params)  WMI_GET_BITS(params, 19, 3)
+#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 19, 3, value)
+
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities */
+    A_UINT32 tlv_header;
+    /**
+     * Support flag
+     * Bit 0     : report AP tsf
+     * Bit 1     : randomize mac address
+     * Bit 2     : Proximity Detection (PD) support i.e. USD ranging
+     * Bit 3     : PD concurrent ISTA and RSTA support
+     * Bit 4     : PD randomize mac address connected state
+     * Bits 31-5 : Reserved
+     */
+    A_UINT32 support_flag;
+    A_UINT32 max_peers;
+    /**
+     * pd max peers
+     * Bits 15-0  : pd_max_peers ISTA role
+     * Bits 31-16 : pd_max_peers RSTA role
+     */
+    A_UINT32 pd_max_peers;
+    /**
+     * FTM support flag
+     * Bit 0      : ftm supported
+     * Bit 1      : asap mode is supported
+     * Bit 2      : non-asap mode is supported
+     * Bit 3      : request lci
+     * Bit 4      : request civicloc
+     * Bit 5      : trigger based supported (TB ranging)
+     * Bit 6      : non-trigger based supported (NTB ranging)
+     * Bit 7      : 6 Ghz supported
+     * Bit 8      : Support Rsta role
+     * Bit 9      : Support edca responder
+     * Bit 10     : Support range report
+     * Bits 31-11 : Reserved
+     */
+    A_UINT32 ftm_support_flag;
+    /** Bitmap of BW supported per wmi_channel_width enum */
+    A_UINT32 supported_bw_bitmap;
+    /** Bitmap of Preambles supported per WMI_RATE_PREAMBLE */
+    A_UINT32 supported_preamble_bitmap;
+    /**
+     * capabilities
+     * Bits 7-0   : Max burst exponents
+     * Bits 15-8  : Max FTM per burst
+     * Bits 23-16 : Max Tx antennas
+     * Bits 31-24 : Max Rx antennas
+     */
+    A_UINT32 capabilities;
+    /**
+     * ranging 11az parameters
+     * Bits 2-0   : Max Tx LTF repetition
+     * Bits 5-3   : Max Rx LTF repetition
+     * Bits 7-6   : Max Rx LTF total
+     * Bits 9-8   : Max Tx LTF total
+     * Bits 12-10 : Max Rx STS LE 80
+     * Bits 15-13 : Max Rx STS GT 80
+     * Bits 18-16 : Max Tx STS LE 80
+     * Bits 21-19 : Max Tx STS GT 80
+     * Bits 31-22 : Reserved
+     */
+    A_UINT32 ranging_11az_parameters;
+    /* Min allowed ranging interval supported by target in EDCA-based ranging, in ms */
+    A_UINT32 min_interval_edca_ms;
+    /* Min allowed ranging interval supported by target in NTB (Non-Trigger Based) ranging, in ms */
+    A_UINT32 min_interval_ntb_ms;
+} wmi_rtt_peer_meas_capabilities;
+
+/*
+ * macros to set/get bitfields within
+ * wmi_rtt_peer_meas_req_peer_info
+ */
+
+#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_GET(flags)  WMI_GET_BITS(flags, 0, 1)
+#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_GET(flags)  WMI_GET_BITS(flags, 1, 1)
+#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value)
+
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_GET(flags)  WMI_GET_BITS(flags, 0, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_GET(flags)  WMI_GET_BITS(flags, 1, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_SET(flags, value)  WMI_SET_BITS(flags, 1, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_GET(flags)  WMI_GET_BITS(flags, 2, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_GET(flags)  WMI_GET_BITS(flags, 3, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_GET(flags) WMI_GET_BITS(flags, 4, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_GET(flags)  WMI_GET_BITS(flags, 5, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_GET(flags)  WMI_GET_BITS(flags, 6, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_GET(flags)  WMI_GET_BITS(flags, 7, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_GET(flags)  WMI_GET_BITS(flags, 8, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_GET(flags) WMI_GET_BITS(flags, 9, 1)
+#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value)
+
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_GET(info)  WMI_GET_BITS(info, 0, 8)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_SET(info, value) WMI_SET_BITS(info, 0, 8, value)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_GET(info)  WMI_GET_BITS(info, 8, 8)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_SET(info, value) WMI_SET_BITS(info, 8, 8, value)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_GET(info)  WMI_GET_BITS(info, 16, 8)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_SET(info, value) WMI_SET_BITS(info, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_GET(info)  WMI_GET_BITS(info, 24, 8)
+#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_SET(info, value) WMI_SET_BITS(info, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_GET(elem)  WMI_GET_BITS(elem, 0, 16)
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_SET(elem, value) WMI_SET_BITS(elem, 0, 16, value)
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_GET(elem)  WMI_GET_BITS(elem, 16, 8)
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_SET(elem, value) WMI_SET_BITS(elem, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_GET(elem)  WMI_GET_BITS(elem, 24, 8)
+#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_SET(elem, value) WMI_SET_BITS(elem, 24, 8, value)
+
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info */
+    A_UINT32 tlv_header;
+    /** Destination mac address for measurement */
+    wmi_mac_addr dest_mac;
+    /** Channel for ranging */
+    wmi_channel channel;
+    /**
+     * request_flag
+     * Bit 0     : Report AP TSF
+     * Bit 1     : PD request - indicates a peer-to-peer Proximity Detection request
+     * Bits 31-2 : Reserved
+     */
+    A_UINT32 request_flag;
+    A_UINT32 preamble; /** see WMI_RATE_PREAMBLE for possible values */
+    /**
+     * Control flag
+     * Bit 0      : FTM requested
+     * Bit 1      : Asap mode
+     * Bit 2      : LCI Req = True/False
+     * Bit 3      : Location Civic Req = True/False
+     * Bit 4      : Trigger based (TB ranging)
+     * Bit 5      : Non-trigger based (NTB ranging)
+     * Bit 6      : I2R LMR Feedback
+     * Bit 7      : RSTA (Operate as the RSTA in the measurement)
+     * Bit 8      : Range Report
+     * Bit 9      : Suppress PD result
+     * Bits 31-10 : Reserved
+     */
+    A_UINT32 control_flag;
+    A_UINT32 burst_period;
+    /**
+     * Burst Information
+     * Bits 7-0   : num_burst_exponent
+     * Bits 15-8  : burst_duration
+     * Bits 23-16 : ftms_per_burst
+     * Bits 31-24 : ftmr_retries
+     */
+    A_UINT32 burst_info;
+    A_UINT32 min_time_between_measurements; /** In units of 100 us */
+    A_UINT32 max_time_between_measurements; /** In units of 10 ms. */
+    /**
+     * Availability window sub elements
+     * Bits 15-0  : nominal_time (in unit of 1 ms)
+     * Bits 23-16 : meas_per_aw
+     * Bits 31-24 : aw_duration (in unit of 1 ms)
+     */
+    A_UINT32 availibility_sub_elem;
+} wmi_rtt_peer_meas_req_peer_info;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique request ID */
+    A_UINT32 req_id;
+    A_UINT32 vdev_id;
+    /** Timeout (in ms) for the whole operation, if zero it means there's no timeout */
+    A_UINT32 timeout;
+    /** Randomized mac address if randomization is enabled */
+    wmi_mac_addr random_mac_addr;
+    /**
+     * This fixed param TLV will be followed by the below TLVs
+     *   - wmi_rtt_peer_meas_req_peer_info rtt_peer_info[]
+     */
+} wmi_rtt_peer_meas_req_cmd_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** Cancel all the requests associated with this req_id */
+    A_UINT32 req_id;
+} wmi_rtt_peer_meas_cancel_meas_cmd_fix_param;
+
+typedef enum {
+    WMI_RTT_PEER_MEAS_STATUS_SUCCESS, /* measurement completed successfully */
+    WMI_RTT_PEER_MEAS_STATUS_REFUSED, /* measurement was locally refused */
+    WMI_RTT_PEER_MEAS_STATUS_TIMEOUT, /* measurement timed out */
+    WMI_RTT_PEER_MEAS_STATUS_FAILURE, /* measurement failed */
+} WMI_RTT_PEER_MEAS_STATUS;
+
+typedef enum {
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_UNSPECIFIED, /* unspecified failure, not used */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_NO_RESPONSE, /* no response from the FTM responder */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_REJECTED, /* FTM responder rejected measurement */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_WRONG_CHANNEL, /* peer is on a different channel */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_NOT_CAPABLE, /* peer can't actually do FTM */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_INVALID_TIMESTAMP, /* invalid T1/T4 timestamps received */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_BUSY, /* peer reports busy, may retry later */
+    WMI_RTT_PEER_MEAS_FTM_FAILURE_BAD_CHANGED_PARAMS, /* peer changed params no longer supported */
+} WMI_RTT_PEER_MEAS_FAILURE;
+
+typedef enum {
+    WMI_PEER_MEAS_TYPE_INVALID,
+    WMI_PEER_MEAS_TYPE_FTM, /* Fine Timing Measurement (IEEE 802.11mc / 802.11az) */
+    WMI_PEER_MEAS_TYPES,
+    WMI_PEER_MEAS_MAX = WMI_PEER_MEAS_TYPES - 1,
+} WMI_RTT_PEER_MEAS_TYPES;
+
+typedef enum {
+    WMI_RTT_GI_UNKNOWN     = 0,  /* default / not available */
+    WMI_RTT_GI_08_US       = 1,  /* 0.8 µs GI */
+    WMI_RTT_GI_16_US       = 2,  /* 1.6 µs GI (11az ranging common) */
+    WMI_RTT_GI_32_US       = 3,  /* 3.2 µs GI */
+    WMI_RTT_GI_ZERO_POWER  = 4,  /* "zero power GI" (secure LTF behavior) */
+} WMI_RTT_GI_TYPE;
+
+/*
+ * macros to set/get bitfields within
+ * wmi_rtt_peer_meas_report_peer_meas_result_info
+ */
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_GET(flags)  WMI_GET_BITS(flags, 0, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_GET(flags)  WMI_GET_BITS(flags, 1, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_GET(flags)  WMI_GET_BITS(flags, 2, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_GET(flags)  WMI_GET_BITS(flags, 3, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_GET(flags)  WMI_GET_BITS(flags, 4, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_GET(flags)  WMI_GET_BITS(flags, 5, 1)
+#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_SET(flags, value)  WMI_SET_BITS(flags, 5, 1, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_GET(info)  WMI_GET_BITS(info, 0, 16)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_SET(info, value) WMI_SET_BITS(info, 0, 16, value)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_GET(info)  WMI_GET_BITS(info, 16, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_SET(info, value) WMI_SET_BITS(info, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_GET(info)  WMI_GET_BITS(info, 24, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_SET(info, value) WMI_SET_BITS(info, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_GET(params)  WMI_GET_BITS(params, 0, 16)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_SET(params, value) WMI_SET_BITS(params, 0, 16, value)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_GET(params)  WMI_GET_BITS(params, 16, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_SET(params, value) WMI_SET_BITS(params, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_GET(params)  WMI_GET_BITS(params, 24, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_SET(params, value) WMI_SET_BITS(params, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_GET(params)  WMI_GET_BITS(params, 0, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_SET(params, value) WMI_SET_BITS(params, 0, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_GET(params)  WMI_GET_BITS(params, 8, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_SET(params, value) WMI_SET_BITS(params, 8, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_GET(params)  WMI_GET_BITS(params, 16, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_SET(params, value) WMI_SET_BITS(params, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_GET(params)  WMI_GET_BITS(params, 24, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_SET(params, value) WMI_SET_BITS(params, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_GET(params)  WMI_GET_BITS(params, 0, 16)
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_SET(params, value) WMI_SET_BITS(params, 0, 16, value)
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_GET(params)  WMI_GET_BITS(params, 16, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_SET(params, value) WMI_SET_BITS(params, 16, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_GET(params)  WMI_GET_BITS(params, 24, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_SET(params, value) WMI_SET_BITS(params, 24, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_GET(code)  WMI_GET_BITS(code, 0, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_SET(code, value) WMI_SET_BITS(code, 0, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_GET(code)  WMI_GET_BITS(code, 8, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_SET(code, value) WMI_SET_BITS(code, 8, 8, value)
+
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_GET(info)   WMI_GET_BITS(info, 0, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_SET(info, value) WMI_SET_BITS(info, 0, 8, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_GET(info)  WMI_GET_BITS(info, 8, 4)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_SET(info, value) WMI_SET_BITS(info, 8, 4, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_GET(info)  WMI_GET_BITS(info, 12, 4)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_SET(info, value) WMI_SET_BITS(info, 12, 4, value)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_GET(info)  WMI_GET_BITS(info, 16, 8)
+#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_SET(info, value) WMI_SET_BITS(info, 16, 8, value)
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info */
+    A_UINT32 tlv_header;
+    /** Destination mac address for measurement */
+    wmi_mac_addr dest_mac;
+    /** Measurement status and reason */
+    A_UINT32 status; /** refer WMI_RTT_PEER_MEAS_STATUS */
+    A_UINT32 ftm_failure_reason; /** refer WMI_RTT_PEER_MEAS_STATUS */
+    /**
+     * Result flag
+     * Bit 0      : final           : 1 => this is last response for this peer/session
+     * Bit 1      : tb_ranging      : 1 => if this is TB ranging
+     * Bit 2      : ntb_ranging     : 1 => if this is NTB ranging
+     * Bit 3      : ap_tsf_valid    : 1 => ap_tsf field is valid
+     * Bit 4      : is_delayed_lmr  : 1 => reported LMR belongs to previous burst
+     * Bit 5      : meas_type       : WMI_PEER_MEAS_TYPES (e.g. FTM)
+     * Bits 31-6  : Reserved
+     */
+    A_UINT32 result_flag;
+    /** FTM Burst Counts */
+    A_UINT32 num_ftmr_attempts;   /** Number of FTM request frames transmitted */
+    A_UINT32 num_ftmr_successes;  /** Number of FTM request frames ACKed */
+     /**
+      * Burst Info
+      * Bits 15-0  : burst_index [0..num_bursts-1]
+      * Bits 23-16 : num_bursts_exp (Negotiated num bursts exponent)
+      * Bits 31-24 : busy_retry_time (In seconds, if peer was busy)
+      */
+    A_UINT32 burst_info;
+    /**
+     * Negotiated/Actual Burst Parameters
+     * Bits 15-0  : burst_period (In units of 100ms)
+     * Bits 23-16 : burst_duration (Actual burst duration negotiated)
+     * Bits 31-24 : ftms_per_burst (Actual FTMs per burst negotiated)
+     */
+    A_UINT32 burst_params;
+
+    /** AP TSF at measurement time (valid if ap_tsf_valid=1) */
+    struct {
+        A_UINT32 ap_tsf_l32;
+        A_UINT32 ap_tsf_h32;
+    } ap_tsf;
+
+    /** optional legacy 32-bit TSF when measurement started */
+    A_UINT32 meas_start_tsf;
+
+    /** RSSI Information */
+    struct {
+        A_INT32  rssi_avg_dbm;
+        A_INT32  rssi_spread_db;
+    } rssi;
+
+    /** RTT statistics (units: picoseconds) */
+    struct {
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } rtt_avg_ps;
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } rtt_variance_ps;
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } rtt_spread_ps;
+    } rtt;
+
+    /** Distance statistics (units: millimeters) */
+    struct {
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } dist_avg_mm;
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } dist_variance_mm;
+        union {
+            A_INT64 value; /* for use by target only */
+            struct {
+                A_UINT32 value_l32;
+                A_UINT32 value_h32;
+            } part;
+        } dist_spread_mm;
+    } dist;
+
+    /**
+     * Negotiated/Actual 11az params
+     * Bits 7-0   : max_i2r_repetition
+     * Bits 15-8  : max_r2i_repetition
+     * Bits 23-16 : max_i2r_sts
+     * Bits 31-24 : max_r2i_sts
+     */
+    A_UINT32 ftm_11az_params;
+    A_UINT32 min_time_between_measurements; /** In units of 100 us */
+    A_UINT32 max_time_between_measurements; /** In units of 10 ms */
+
+    /**
+     * Negotiated/Actual avail windows params
+     * Bits 15-0  : nominal_time_ms (In units of 1 ms)
+     * Bits 23-16 : measurements_per_aw
+     * Bits 31-24 : aw_duration (In units of 1 ms)
+     */
+    A_UINT32 avail_window_params;
+
+    /**
+     * Negotiated/Actual FTM IE channel code
+     * Bits 7-0   : chan_bw (refer wmi_channel_width)
+     * Bits 15-8  : preamble (refer WMI_RATE_PREAMBLE)
+     * Bits 31-16 : reserved
+     */
+    A_UINT32 ftm_ie_channel_code;
+
+    /**
+     * Tx/Rx Rate Info
+     *  Bits 7-0   : rateMcsIdx  - OFDM/CCK rate code would be as per IEEE standard in the units of 0.5mbps
+     *                         -   HT/VHT/HE it would be mcs index
+     *  Bits 11-8  : Nss (1*1, 2*2, 3*3, 4*4)
+     *  Bits 15-12 : Rx packet BW (0-20 Mhz, 1 - 40 Mhz, 2 - 80 Mhz, 3 - 160 Mhz, 4 - 320 Mhz)
+     *  Bits 23-16 : gi (refer WMI_RTT_GI_TYPE)
+     *  Bits 31-24 : Reserved
+     */
+    A_UINT32 tx_rate_info_1;
+    A_UINT32 rx_rate_info_1;
+
+    /** bits 31:0: TX/RX Bit rate in 100kbps */
+    A_UINT32 tx_rate_info_2;
+    A_UINT32 rx_rate_info_2;
+} wmi_rtt_peer_meas_report_peer_meas_result_info;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 req_id; /** Unique Identifier */
+    A_UINT32 vdev_id;
+    /**
+     * This fixed param TLV will be followed by the below TLVs
+     *   - wmi_rtt_peer_meas_report_peer_meas_result_info peer_meas_info[]
+     */
+} wmi_rtt_peer_meas_report_event_fixed_param;
+
+
 
 /* ADD NEW DEFS HERE */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 22e2b0191a00..e79eda5c0679 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1757
+#define __WMI_REVISION_ 1758
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e32be1e992edb63d54db67116860c911746e5918 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 3 May 2026 18:04:54 -0700
Subject: [PATCH 236/290] fw-api: CL 32415720 - update fw common interface
 files

Change-Id: Ifb141a461641a7abd7f712b95817ca526501d2c5
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  3 +++
 fw/wmi_tlv_defs.h | 14 ++++++++++++++
 fw/wmi_unified.h  | 48 ++++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 65 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index d49fb574c7ec..0cb39023a90f 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -805,6 +805,9 @@ typedef  enum  {
     WMI_SERVICE_CALDB_OVER_WMI = 507,
     /* Indicates FW Supports RTT Proximity Detection (USD ranging) */
     WMI_SERVICE_RTT_PD = 508,
+    /* Indicates FW support for Channel Hopping Status Report*/
+    WMI_SERVICE_VDEV_CHAN_HOP_STATUS_REPORT = 509,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 34542191b8c1..6ec01ddba08e 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1632,6 +1632,9 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param,
     WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info,
+    WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status,
+    WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2241,6 +2244,7 @@ typedef enum {
     OP(WMI_GET_CHIPSET_LOGGING_STATS_CMDID) \
     OP(WMI_RTT_PEER_MEAS_REQ_CMDID) \
     OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \
+    OP(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2610,6 +2614,7 @@ typedef enum {
     OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \
     OP(WMI_ANOMALY_REPORT_EVENTID) \
     OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \
+    OP(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6501,6 +6506,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REQ_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_CANCEL_CMDID);
 
+#define WMITLV_TABLE_WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -8917,6 +8926,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_report_peer_meas_result_info, peer_meas_result_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REPORT_EVENTID);
 
+#define WMITLV_TABLE_WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param, wmi_vdev_chan_hop_status_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_chan_hop_slot_status, slot_status, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 21241b42d99a..8c8525c6931a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -783,6 +783,8 @@ typedef enum {
     /** WMI cmd for Channel Hopping Schedule */
     WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID,
 
+    /** WMI cmd to request channel hopping per-slot status report */
+    WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID,
 
     /* peer specific commands */
 
@@ -2185,6 +2187,8 @@ typedef enum {
     WMI_VDEV_UNIFIED_DISCONNECT_EVENTID,
     /** WMI event for sending vdev operating params */
     WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID,
+    /** channel hopping per-slot status report event */
+    WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID,
 
     /* peer specific events */
     /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */
@@ -42870,6 +42874,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID);
         WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID);
         WMI_RETURN_STRING(WMI_GET_CHIPSET_LOGGING_STATS_CMDID);
+        WMI_RETURN_STRING(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -55923,6 +55928,46 @@ typedef struct {
     A_UINT32 role; /* holds wmi_channel_hopping_role enum value */
 } wmi_channel_hopping_channel_params;
 
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+} wmi_vdev_get_chan_hop_status_report_cmd_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status */
+    A_UINT32 tlv_header;
+    A_UINT32 role; /* holds wmi_channel_hopping_role enum value */
+    A_UINT32 chan_mhz;
+    /*
+     * TSF of the most recent actual frequency transition leading into
+     * slot. Carried forward for consecutive same-frequency slots.
+     */
+    A_UINT32 channel_switch_tsf;
+    A_UINT32 channel_start_tsf; /* TSF when this slot's active period began. */
+    A_UINT32 channel_end_tsf; /* TSF when this slot's active period ended. */
+    /**
+     * tx_traffic_index = (tx_duration_us / channel_spent_us) * 100
+     * Range: 0 - 100
+     */
+    A_UINT32 tx_traffic_index;
+    /**
+     * rx_traffic_index = (rx_duration_us / channel_spent_us) * 100
+     * Range: 0 - 100
+     */
+    A_UINT32 rx_traffic_index;
+} wmi_vdev_chan_hop_slot_status;
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    /** TSF timestamp of the current channel hopping request */
+    A_UINT32 hopping_request_tsf;
+    /* Index of the current channel in the channel hopping list */
+    A_UINT32 current_channel_index;
+} wmi_vdev_chan_hop_status_report_event_fixed_param;
+
 typedef enum {
     WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1,
     WMI_SMD_ROAM_CONFIG_ROLE_TARGET_AP,
@@ -56464,11 +56509,12 @@ typedef struct {
      * Bits 31-10 : Reserved
      */
     A_UINT32 control_flag;
-    A_UINT32 burst_period;
+    A_UINT32 burst_period; /* units = 100 ms */
     /**
      * Burst Information
      * Bits 7-0   : num_burst_exponent
      * Bits 15-8  : burst_duration
+     *              units = IEEE 802.11 FTM burst dur encoding (250 us * 2^n)
      * Bits 23-16 : ftms_per_burst
      * Bits 31-24 : ftmr_retries
      */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index e79eda5c0679..027a0f730c73 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1758
+#define __WMI_REVISION_ 1759
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c797dc8f311898db4f4efee76c209195913f3457 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 5 May 2026 18:01:58 -0700
Subject: [PATCH 237/290] fw-api: CL 32437017 - update fw common interface
 files

Change-Id: I9f77b2a1e4b7b43eea1393505bc757ee3154a622
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 3 ++-
 fw/wmi_unified.h  | 8 +++++++-
 fw/wmi_version.h  | 2 +-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 0cb39023a90f..319a2112b9b8 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -807,7 +807,8 @@ typedef  enum  {
     WMI_SERVICE_RTT_PD = 508,
     /* Indicates FW support for Channel Hopping Status Report*/
     WMI_SERVICE_VDEV_CHAN_HOP_STATUS_REPORT = 509,
-
+    /* Indicates FW support for Predictive roaming */
+    WMI_SERVICE_ROAMING_PREDICTIVE = 510,
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8c8525c6931a..2a97e07c0ca4 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -26134,8 +26134,14 @@ typedef struct {
 enum wlan_roam_invoke_reason {
     ROAM_INVOKE_REASON_UNDEFINED = 0,
     /* FW will use default parameters to do roam scan, ignore other parameters like WLM, etc. */
-    ROAM_INVOKE_REASON_NUD_FAILURE, /* Neighbor Unreachable Detection */
+
+    /* Neighbor Unreachable Detection */
+    ROAM_INVOKE_REASON_NUD_FAILURE,
+
     ROAM_INVOKE_REASON_USER_SPACE,
+
+    /* Trigger for Out-Of-Quality (OOQ) roaming */
+    ROAM_INVOKE_REASON_PREDICTIVE,
 };
 
 /** WMI_ROAM_INVOKE_CMD: command to invoke roaming forcefully
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 027a0f730c73..a03873338aec 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1759
+#define __WMI_REVISION_ 1760
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 5409c7189d42d167384814b39093890a5345d74f Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 7 May 2026 18:01:49 -0700
Subject: [PATCH 238/290] fw-api: CL 32464183 - update fw common interface
 files

Change-Id: Ie47269874d0fa4fe586be912cf11497d51474abc
CRs-Fixed: 3830439
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index c83725d2a56a..0716a4625152 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -936,6 +936,7 @@ typedef enum {
     HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG            = 257, /* htt_stats_txq_combined_seq_state_tlv */
     HTT_STATS_CTL_TAG                               = 258, /* htt_stats_ctl_tlv */
     HTT_STATS_ENHANCED_CTL_TAG                      = 259, /* htt_stats_enhanced_ctl_tlv */
+    HTT_STATS_NPCA_TAG                              = 260, /* htt_stats_npca_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index f2d50d3ebede..68c6c694a69b 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -948,6 +948,8 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_EXT_STATS_DPD = 85,
 
+    HTT_DBG_EXT_STATS_NPCA = 86,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -16972,5 +16974,25 @@ typedef struct {
     A_INT32  nmse_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE];
 } htt_stats_dpd_hw_cal_results_tlv;
 
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 mu_rts_tx_success;
+    A_UINT32 mu_rts_tx_fail;
+    A_UINT32 mu_rts_rx_success;
+    A_UINT32 bsrp_ntb_tx_success;
+    A_UINT32 bsrp_ntb_tx_fail;
+    A_UINT32 bsrp_ntb_rx_success;
+    A_UINT32 bsrp_tx_success;
+    A_UINT32 bsrp_tx_fail;
+    A_UINT32 bsrp_rx_success;
+    A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    A_UINT32 npca_su_tx_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+    A_UINT32 npca_rx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    A_UINT32 npca_su_rx_punctured_mode[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    A_UINT32 schd_cmd_result_npca[HTT_STATS_MAX_SCH_CMD_RESULT];
+    htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS];
+    htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
+} htt_stats_npca_tlv;
+
 
 #endif /* __HTT_STATS_H__ */

From 5f612b84b420b95beed9191517d72dde8be15d0c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 7 May 2026 18:03:43 -0700
Subject: [PATCH 239/290] fw-api: CL 32465518 - update fw common interface
 files

Change-Id: I2e542350a04e2f74d4c28270eaa0676868aed3ee
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   6 +++
 fw/wmi_tlv_defs.h |  22 ++++++++++
 fw/wmi_unified.h  | 103 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 4 files changed, 131 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 319a2112b9b8..34edff232b59 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -810,6 +810,12 @@ typedef  enum  {
     /* Indicates FW support for Predictive roaming */
     WMI_SERVICE_ROAMING_PREDICTIVE = 510,
 
+    /* Services related to MAPC / C-TDMA (802.11bn) */
+    WMI_SERVICE_CO_AP_CTDMA_SUPPORT = 511,
+    WMI_SERVICE_UHR_CO_AP_CTDMA_TB_PPDU_SUPPORT = 512,
+    WMI_SERVICE_UHR_CO_AP_CTDMA_TXOP_RETURN_SUPPORT = 513,
+
+
     WMI_MAX_EXT2_SERVICE
 
 } WMI_SERVICE;
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 6ec01ddba08e..6c1e2779b5ab 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1635,6 +1635,12 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status,
     WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_mapc_cmn_params,
+    WMITLV_TAG_STRUC_wmi_mapc_cotdma_params,
+    WMITLV_TAG_STRUC_wmi_mapc_cosr_params,
+    WMITLV_TAG_STRUC_wmi_mapc_cobf_params,
+    WMITLV_TAG_STRUC_wmi_mapc_cortwt_params,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2245,6 +2251,7 @@ typedef enum {
     OP(WMI_RTT_PEER_MEAS_REQ_CMDID) \
     OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \
     OP(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID) \
+    OP(WMI_PEER_SET_MAPC_PARAMS_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -6468,6 +6475,21 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID);
 
+/* WMI commad to config MAPC params used for co-ordinated AP features in 11bn */
+#define WMITLV_TABLE_WMI_PEER_SET_MAPC_PARAMS_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param, wmi_peer_set_mapc_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    /*--- Common MAPC params ---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cmn_params, mapc_cmn_params, WMITLV_SIZE_VAR) \
+    /*--- Co-TDMA scheme params ---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cotdma_params, cotdma_params, WMITLV_SIZE_VAR) \
+    /*--- Co-SR scheme params (future) ---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cosr_params, cosr_params, WMITLV_SIZE_VAR) \
+    /*--- Co-BF scheme params (future) ---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cobf_params, cobf_params, WMITLV_SIZE_VAR) \
+    /*--- Co-rTWT scheme params (future) ---*/ \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cortwt_params, cortwt_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_MAPC_PARAMS_CMDID);
+
 /* WMI Command for Energy management OEM cmd data */
 #define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, wmi_energy_mgmt_oem_data_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2a97e07c0ca4..a37efe035e27 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -374,7 +374,8 @@ typedef enum {
     WMI_GRP_MANUAL_UL_TRIG, /* 0x4d Manual UL OFDMA Trigger */
     WMI_GRP_ENERGY_MGMT,    /* 0x4e energy management */
     WMI_GRP_SMD,            /* 0x4f SMD Roaming */
-    WMI_GRP_CHIPSET_LOG     /* 0x50 Chipset Debug Logging */
+    WMI_GRP_CHIPSET_LOG,    /* 0x50 Chipset Debug Logging */
+    WMI_GRP_MAPC,           /* 0x51 MAPC for co-ordinated features */
 } WMI_GRP_ID;
 
 #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -1870,6 +1871,9 @@ typedef enum {
 
     /** WMI command for host to request chipset debug log stats from FW */
     WMI_GET_CHIPSET_LOGGING_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CHIPSET_LOG),
+
+    /** WMI cmds for MAPC (Multi-AP Coordination) */
+    WMI_PEER_SET_MAPC_PARAMS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MAPC),
 } WMI_CMD_ID;
 
 typedef enum {
@@ -22409,6 +22413,7 @@ enum wmi_peer_type {
     WMI_PEER_TYPE_TRANS_BSS = 5,  /* For creating BSS peer when connecting with non-transmit AP */
     WMI_PEER_TYPE_PASN = 6,       /* Peer is used for Pre-Association Security Negotiation */
     WMI_PEER_TYPE_BRIDGE = 7,     /* For creating Dummy Peer in case of 4 Link MLO */
+    WMI_PEER_TYPE_MAPC = 8,       /* Peer is a MAPC Co-ordinated AP */
     WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */
                                   /* Reserved from 128 - 255 for target internal use.*/
     WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */
@@ -56143,6 +56148,102 @@ typedef struct {
     A_UINT32 status; /** wmi_smd_peer_setup_status_type */
 } wmi_smd_roam_peer_unified_setup_complete_event_fixed_param;
 
+/* ================================================================ */
+/* WMI_PEER_SET_MAPC_PARAMS_CMDID structures                        */
+/* ================================================================ */
+
+/* Scheme enable bitmap — indicates which scheme TLVs are present */
+#define WMI_MAPC_SCHEME_COBF    (1 << 0)  /* Co-BF   */
+#define WMI_MAPC_SCHEME_COSR    (1 << 1)  /* Co-SR   */
+#define WMI_MAPC_SCHEME_COTDMA  (1 << 2)  /* Co-TDMA */
+#define WMI_MAPC_SCHEME_CORTWT  (1 << 3)  /* Co-rTWT */
+#define WMI_MAPC_SCHEME_COCR    (1 << 4)  /* Co-CR   */
+
+/*
+ * wmi_peer_set_mapc_params_cmd_fixed_param:
+ * Identity + routing hint for WMI_PEER_SET_MAPC_PARAMS_CMDID.
+ * mapc_scheme_enable_bitmap indicates which scheme TLVs follow.
+ * Sent after WMI_PEER_CREATE_CMDID (peer_type=WMI_PEER_TYPE_MAPC)
+ * and after each MAPC Negotiation Agreement Establishment/Update.
+ */
+typedef struct {
+    A_UINT32     tlv_header; /* WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param */
+    A_UINT32     vdev_id;
+    wmi_mac_addr peer_macaddr;
+    A_UINT32     mapc_scheme_enable_bitmap; /* WMI_MAPC_SCHEME_* bitmask */
+} wmi_peer_set_mapc_params_cmd_fixed_param;
+
+/*
+ * wmi_mapc_cmn_params:
+ * Common MAPC params shared across all schemes.
+ */
+typedef struct {
+    A_UINT32     tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cmn_params */
+
+    /* peer's advertised MAPC capability bitmap */
+    A_UINT32     mapc_capability_bitmap;
+
+    /* APID assigned by local AP to remote C-AP */
+    A_UINT32     apid_to_neighbor_peer;
+
+    /* APID assigned by remote C-AP to local AP */
+    A_UINT32     apid_from_neighbor_peer;
+
+    /* Vendor Q2Q APID assigned to remote peer */
+    A_UINT32     q2q_apid_to_neighbor_peer;
+
+    /* Vendor Q2Q APID assigned by remote peer */
+    A_UINT32     q2q_apid_from_neighbor_peer;
+} wmi_mapc_cmn_params;
+
+/*
+ * wmi_mapc_cotdma_params: mapc_ctdma_profile + mapc_txop_sharing_policy
+ * Co-TDMA per-peer policy parameters.
+ */
+typedef struct {
+    A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cotdma_params */
+
+    /* Channel info — mapc_ctdma_profile */
+    A_UINT32 channel_width; /* operating channel width (MHz) */
+    A_UINT32 ccfs;          /* center channel frequency segment index */
+    A_UINT32 bss_color;     /* 802.11ax/be BSS color */
+
+    /* 1 = peer supports RX-driven TXOP return */
+    A_UINT32 rx_txop_return_support;
+
+    A_UINT32 disable_subchannel_bitmap; /* subchannels to disable */
+
+    /* TXOP sharing policy — mapc_txop_sharing_policy */
+    A_UINT32 primary_ac;  /* primary AC: VO=0 VI=1 BE=2 BK=3 */
+    A_UINT32 nbr_ap_prio; /* Cotroller set nbr shared ap prio */
+    A_UINT32 latency_sensitive_threshold_us;
+    A_UINT32 service_start_time; /* TSF-relative service window start (us) */
+    A_UINT32 service_interval;   /* periodicity (us); 0 = always available */
+    A_UINT32 service_end_time;   /* TSF-relative service window end (us) */
+    A_UINT32 critical_traffic_dur_thresh_us;
+    A_UINT32 max_shared_txop_dur_us; /* per-AC max shared TXOP */
+    A_UINT32 min_shared_txop_dur_us; /* per-AC min TXOP to trigger C-TDMA */
+} wmi_mapc_cotdma_params;
+
+/*
+ * Stub structures for future MAPC coordination schemes.
+ * Included now to reserve TLV slots in WMI_PEER_SET_MAPC_PARAMS_CMDID so that
+ * the TLV layout remains stable when these schemes are implemented.  Host must
+ * send 0 array entries for each stub; FW ignores them until the feature lands.
+ */
+
+/* Co-SR (Coordinated Spatial Reuse, 802.11bn): allows coordinated BSS-color /
+ * OBSS_PD threshold negotiation between C-APs to improve spatial reuse. */
+typedef struct { A_UINT32 tlv_header; } wmi_mapc_cosr_params;
+
+/* Co-BF (Coordinated Beamforming, 802.11bn): enables joint beamforming vector
+ * coordination between C-APs to suppress inter-BSS interference. */
+typedef struct { A_UINT32 tlv_header; } wmi_mapc_cobf_params;
+
+/* Co-rTWT (Coordinated restricted-TWT, 802.11bn): allows C-APs to align their
+ * restricted-TWT service periods to avoid overlapping transmissions. */
+typedef struct { A_UINT32 tlv_header; } wmi_mapc_cortwt_params;
+
 
 typedef enum {
     WMI_PDEV_SET_CUMAC_CHIP_ID_SUCCESS = 0,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a03873338aec..8eed6aba6b00 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1760
+#define __WMI_REVISION_ 1761
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e7116cb9e98bf2de8fa7d246d43dbb64cc0c1252 Mon Sep 17 00:00:00 2001
From: Pragaspathi Thilagaraj <tpragasp@qti.qualcomm.com>
Date: Tue, 7 Apr 2026 01:23:20 +0530
Subject: [PATCH 240/290] qcacld-3.0: Add A_INT64 typedef

Add A_INT64 as a signed 64-bit integer type in uapi/linux/a_types.h.
This complements the existing A_UINT64 definition and provides a
consistent signed 64-bit typedef for consumers of this UAPI header.

CRs-Fixed: 4492650
Change-Id: Ie7f5fb55ba291273ecf35920a217fc65dfa3f661
---
 uapi/linux/a_types.h | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/uapi/linux/a_types.h b/uapi/linux/a_types.h
index 190d40df6afd..5537fae67697 100644
--- a/uapi/linux/a_types.h
+++ b/uapi/linux/a_types.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -29,15 +30,21 @@
 #define _A_TYPES_H_
 #include <athdefs.h>
 
-typedef unsigned int A_UINT32;
 typedef unsigned long long A_UINT64;
+typedef          long long A_INT64;
+
+typedef unsigned int A_UINT32;
+typedef          int A_INT32;
+
 typedef unsigned short A_UINT16;
+typedef          short A_INT16;
+
 typedef unsigned char A_UINT8;
-typedef int A_INT32;
-typedef short A_INT16;
-typedef char A_INT8;
+typedef          char A_INT8;
+
 typedef unsigned char A_UCHAR;
-typedef char A_CHAR;
+typedef          char A_CHAR;
+
 typedef _Bool A_BOOL;
 
 #endif /* _ATHTYPES_H_ */

From be91f2f082256d1dec3a71ca455c6cca9247bd95 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 8 May 2026 18:02:01 -0700
Subject: [PATCH 241/290] fw-api: CL 32477405 - update fw common interface
 files

Change-Id: Ic79bd8e20c37ba78e27f066ca24c4c3b05f952e4
CRs-Fixed: 3830439
---
 fw/htt.h | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 0716a4625152..0a50c23b9cf1 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -6235,7 +6235,11 @@ enum htt_srng_ring_id {
  *                    newer packet_type_enable_data_flags_* are valid or not
  *                    If not set, will use pkt_type_enable_flags for both status
  *                    and full pkt buffer configuration.
- *          b'30:31 - rsvd1:  reserved for future use
+ *          b'30    - is_monitor_mode: specify whether monitor mode is enabled.
+ *                    Helpful to configure monitor-mode related filters.
+ *                    These filters cause throughput dip if enabled in
+ *                    non-monitor mode.
+ *          b'31    - rsvd1:  reserved for future use
  * dword1 - b'0:15  - ring_buffer_size: size of bufferes referenced by rx ring,
  *                    in byte units.
  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
@@ -6452,7 +6456,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
              drop_thresh_valid: 1,
              rx_mon_global_en:  1,
              packet_type_enable_data: 1,
-             rsvd1:             2;
+             is_monitor_mode:   1,
+             rsvd1:             1;
     A_UINT32 ring_buffer_size: 16,
              config_length_mgmt:3,
              config_length_ctrl:3,
@@ -6655,6 +6660,18 @@ enum htt_reg_write_selection {
                 ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \
             } while (0)
 
+#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M    0x40000000
+#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S           30
+#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_GET(_var) \
+            (((_var) & HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M) >> \
+                    HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S)
+#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE, _val); \
+                ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S)); \
+            } while (0)
+
+
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M           0x0000ffff
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S           0
 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \

From e280ec35850b1acee9632b7b9ead5a8cf2a93643 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 8 May 2026 18:04:07 -0700
Subject: [PATCH 242/290] fw-api: CL 32479166 - update fw common interface
 files

Change-Id: I3ce8a6e26a34300bc1fabeeec03fa8fdfc86a630
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 41 +++++++++++++++++++++++++++++++++++++----
 fw/wmi_version.h |  2 +-
 2 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a37efe035e27..e6138c762ed6 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44618,11 +44618,32 @@ typedef struct {
 #define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \
     WMI_SET_BITS(flag, 7, 1, val)
 
+/* bits 8-15: unused / reserved */
+
+/*
+ * Bit 16: indicates whether pdev_id is valid or vdev_id is valid.
+ * 0: pdev_id is valid (MAC-level TWT enable/disable)
+ * 1: vdev_id is valid (STA vdev-level TWT enable/disable)
+ */
+#define TWT_EN_DIS_FLAGS_GET_VDEV_ID(flag)      WMI_GET_BITS(flag, 16, 1)
+#define TWT_EN_DIS_FLAGS_SET_VDEV_ID(flag, val) WMI_SET_BITS(flag, 16, 1, val)
+
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param  */
-    /** pdev_id for identifying the MAC.  See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0
+    /**
+     * pdev_id or vdev_id depending on bit 16 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 0:
+     *   pdev_id identifies the MAC.
+     *   See macros starting with WMI_PDEV_ID_ for values.
+     *   In non-DBDC case host should set it to 0.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 1:
+     *   vdev_id is for STA vdev-level TWT enable.
+     *   TWT enable applies only to that specific STA vdev.
      */
-    A_UINT32 pdev_id;
+    union {
+        A_UINT32 pdev_id;
+        A_UINT32 vdev_id;
+    };
     A_UINT32 sta_cong_timer_ms;     /* STA TWT congestion timer TO value in terms of ms */
     A_UINT32 mbss_support;          /* Reserved */
     A_UINT32 default_slot_size;              /* This is the default value for the TWT slot setup by AP (units = microseconds) */
@@ -44672,8 +44693,20 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_cmd_fixed_param  */
-    /** pdev_id for identifying the MAC.  See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */
-    A_UINT32 pdev_id;       /* host should never set it to WMI_PDEV_ID_SOC  */
+    /**
+     * pdev_id or vdev_id depending on bit 16 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 0:
+     *   pdev_id identifies the MAC.
+     *   See macros starting with WMI_PDEV_ID_ for values.
+     *   In non-DBDC case host should set it to 0.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 1:
+     *   vdev_id is for STA vdev-level TWT disable.
+     *   TWT disable applies only to that specific STA vdev.
+     */
+    union {
+        A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC  */
+        A_UINT32 vdev_id;
+    };
     A_UINT32 flags;         /* enable/disable flags, refer to MACROs TWT_EN_DIS_FLAGS_* (TWT_EN_DIS_FLAGS_GET_BTWT etc.) */
     A_UINT32 reason_code;   /* refer to WMI_DISABLE_TWT_REASON_T */
 } wmi_twt_disable_cmd_fixed_param;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8eed6aba6b00..ae86a7759307 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1761
+#define __WMI_REVISION_ 1762
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 66cea4aabb2c6b96a39a5f5cd0c107117f1c19b8 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 9 May 2026 18:04:34 -0700
Subject: [PATCH 243/290] fw-api: CL 32489576 - update fw common interface
 files

Change-Id: I49041d8fb1fe6844158bed3685cfcdd8ac3b4716
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 19 ++++++++++---------
 fw/wmi_version.h |  2 +-
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e6138c762ed6..343c91f7e02d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -53555,6 +53555,7 @@ typedef struct {
 #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_2G_RATE_NUM_EXT   8
 
 #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_6G_RATE_NUM    24
+#define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_RATE_NUM_EXT   4
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_custom_tx_power_per_mcs_cmd_fixed_param */
@@ -53580,22 +53581,22 @@ typedef struct {
      */
     A_UINT32 bitmap_of_2GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM];
 
-    /* 5GHz band has 4 chains and each chain has 24 rates.
+    /* 5GHz band has 4 chains and each chain has 24 rates and 4 extended rates.
      * bitmap_of_5GHz_band[0] -> chain 0 bitmap:
-     * |bit  0|bit  1|......|bit  23|
-     * |rate 0|rate 1|......|rate 23|
+     * |bit  0|bit  1|......|bit  23| bit   24 |......| bit   27 |
+     * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3|
      *
      * bitmap_of_5GHz_band[1] -> chain 1 bitmap:
-     * |bit  0|bit  1|......|bit  23|
-     * |rate 0|rate 1|......|rate 23|
+     * |bit  0|bit  1|......|bit  23| bit   24 |......| bit   27 |
+     * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3|
      *
      * bitmap_of_5GHz_band[2] -> chain 2 bitmap:
-     * |bit  0|bit  1|......|bit  23|
-     * |rate 0|rate 1|......|rate 23|
+     * |bit  0|bit  1|......|bit  23| bit   24 |......| bit   27 |
+     * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3|
      *
      * bitmap_of_5GHz_band[3] -> chain 3 bitmap:
-     * |bit  0|bit  1|......|bit  23|
-     * |rate 0|rate 1|......|rate 23|
+     * |bit  0|bit  1|......|bit  23| bit   24 |......| bit   27 |
+     * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3|
      */
     A_UINT32 bitmap_of_5GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM];
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ae86a7759307..d240459659aa 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1762
+#define __WMI_REVISION_ 1763
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 221de7eef147a76fc4764f863e2caddb79046de6 Mon Sep 17 00:00:00 2001
From: Deeksha Gupta <deegupta@qti.qualcomm.com>
Date: Thu, 25 Jan 2024 16:08:03 +0530
Subject: [PATCH 244/290] =?UTF-8?q?qcacld-3.0:=20Set=20=E2=80=9CWIPHY=5FFL?=
 =?UTF-8?q?AG=5FDFS=5FOFFLOAD=E2=80=9D=20always=20in=20wiphy=20flag?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Ensure the "WIPHY_FLAG_DFS_OFFLOAD" flag is always set in
wiphy flag, regardless of DFS master capability ini.
This changes eliminates the need for supplicant to check
DFS flags for the SAP channel, as the DFS logic is
consistently offloaded to the driver.

CRs-Fixed: 3716167
Change-Id: I571f1cf15d268b85ad4de4d2f2a93d39f59b1231
---
 core/hdd/src/wlan_hdd_cfg80211.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/core/hdd/src/wlan_hdd_cfg80211.c b/core/hdd/src/wlan_hdd_cfg80211.c
index 9edadf77f669..3c0adf628743 100644
--- a/core/hdd/src/wlan_hdd_cfg80211.c
+++ b/core/hdd/src/wlan_hdd_cfg80211.c
@@ -1718,7 +1718,7 @@ static const struct nl80211_vendor_cmd_info wlan_hdd_cfg80211_vendor_events[] =
 };
 
 /**
- * __is_driver_dfs_capable() - get driver DFS capability
+ * __is_driver_dfs_capable() - get driver DFS offload capability
  * @wiphy:   pointer to wireless wiphy structure.
  * @wdev:    pointer to wireless_dev structure.
  * @data:    Pointer to the data to be passed via vendor interface
@@ -17739,7 +17739,7 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx)
 {
 	int value;
 	bool fils_enabled, mac_spoofing_enabled;
-	bool dfs_master_capable = true, is_oce_sta_enabled = false;
+	bool is_oce_sta_enabled = false;
 	QDF_STATUS status;
 	struct wiphy *wiphy = hdd_ctx->wiphy;
 	uint8_t allow_mcc_go_diff_bi = 0, enable_mcc = 0;
@@ -17764,11 +17764,7 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx)
 	if (fils_enabled)
 		wlan_hdd_cfg80211_set_wiphy_fils_feature(wiphy);
 
-	status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc,
-						     &dfs_master_capable);
-	if (QDF_IS_STATUS_SUCCESS(status) && dfs_master_capable)
-		wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy);
-
+	wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy);
 
 	status = ucfg_mlme_get_bigtk_support(hdd_ctx->psoc,
 					     &is_bigtk_supported);

From 1b0f7e3489a3e79fee044d1795d1fdea2fc3f71b Mon Sep 17 00:00:00 2001
From: Abinandhu M <abinmano@qti.qualcomm.com>
Date: Sun, 10 May 2026 22:52:01 +0530
Subject: [PATCH 245/290] qcacld-3.0:  Disable SAP bringup in DFS when
 DFSmastercap is disabled

Issue Scenario:
1) INI gEnableDFSMasterCap is set to 0
2) User tries to force start SAP on 160 MHz.
3) SAP starts on 160 MHz which contains DFS channels.

This is a violation since the DUT does not support DFS
master capability.

To fix this, stop the SAP bringup if atleast one of the
bonded channels is DFS.

CRs-Fixed: 4516874
Change-Id: Iaeb77d52059505bafb8a0d38386cb1790432b498
---
 .../policy_mgr/inc/wlan_policy_mgr_api.h      | 18 +++++++++
 .../src/wlan_policy_mgr_get_set_utils.c       | 39 +++++++++++++++++++
 core/hdd/src/wlan_hdd_hostapd.c               | 19 +++++++++
 3 files changed, 76 insertions(+)

diff --git a/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h
index d902f7ee4327..141ce08f47a2 100644
--- a/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h
+++ b/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h
@@ -210,6 +210,24 @@ QDF_STATUS
 policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc,
 				       uint8_t *sta_sap_scc_on_dfs_chnl);
 
+/**
+ * policy_mgr_is_bonded_chan_dfs() - check whether the given bonded
+ * channel configuration falls under DFS
+ * @psoc: pointer to psoc
+ * @ch_width: channel width of the operating channel
+ * @mhz_freq_seg1: center frequency of segment 1; used for 80+80 MHz
+ * @chan_freq: primary/operating channel frequency in MHz
+ *
+ * This API checks whether the given channel or bonded channel span
+ * includes DFS, based on the channel width and frequency segments.
+ *
+ * Return: true if the given bonded channel is DFS, else false.
+ */
+bool
+policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc,
+			      enum phy_ch_width ch_width,
+			      qdf_freq_t mhz_freq_seg1,
+			      uint32_t chan_freq);
 /**
  * policy_mgr_get_dfs_master_dynamic_enabled() - support dfs master or not
  * on AP interafce when STA+SAP(GO) concurrency
diff --git a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c
index 5661c5a03491..0bffbe5e612e 100644
--- a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c
+++ b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c
@@ -181,6 +181,45 @@ policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc,
 	return QDF_STATUS_SUCCESS;
 }
 
+bool
+policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc,
+			      enum phy_ch_width ch_width,
+			      qdf_freq_t mhz_freq_seg1,
+			      uint32_t chan_freq)
+{
+	bool is_ch_dfs = false;
+	struct policy_mgr_psoc_priv_obj *pm_ctx;
+
+	pm_ctx = policy_mgr_get_context(psoc);
+	if (!pm_ctx) {
+		policy_mgr_err("pm_ctx is NULL");
+		return false;
+	}
+
+	if (ch_width == CH_WIDTH_160MHZ) {
+		if (wlan_reg_get_5g_bonded_channel_state_for_freq(pm_ctx->pdev,
+								  chan_freq,
+								  ch_width)
+				== CHANNEL_STATE_DFS)
+			is_ch_dfs = true;
+	} else if (ch_width == CH_WIDTH_80P80MHZ) {
+		if (wlan_reg_get_channel_state_for_freq(
+					pm_ctx->pdev,
+					chan_freq) ==
+				CHANNEL_STATE_DFS ||
+			wlan_reg_get_channel_state_for_freq(
+					pm_ctx->pdev,
+					mhz_freq_seg1) ==
+				CHANNEL_STATE_DFS)
+			is_ch_dfs = true;
+	} else {
+		if (wlan_reg_is_dfs_for_freq(pm_ctx->pdev, chan_freq))
+			is_ch_dfs = true;
+	}
+
+	return is_ch_dfs;
+}
+
 static bool
 policy_mgr_update_dfs_master_dynamic_enabled(
 	struct wlan_objmgr_psoc *psoc, uint8_t vdev_id)
diff --git a/core/hdd/src/wlan_hdd_hostapd.c b/core/hdd/src/wlan_hdd_hostapd.c
index 80659541d94a..76a1a5228125 100644
--- a/core/hdd/src/wlan_hdd_hostapd.c
+++ b/core/hdd/src/wlan_hdd_hostapd.c
@@ -5244,6 +5244,7 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter,
 	bool deliver_start_evt = true;
 	struct s_ext_cap *p_ext_cap;
 	enum reg_phymode reg_phy_mode, updated_phy_mode;
+	bool dfs_master_capable;
 
 	hdd_enter();
 
@@ -5787,6 +5788,24 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter,
 			config->ch_width_orig = CH_WIDTH_20MHZ;
 	}
 
+	status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc,
+						     &dfs_master_capable);
+	if (QDF_IS_STATUS_ERROR(status)) {
+		hdd_err("Failed to get dfs master capable");
+		ret = -EINVAL;
+		goto error;
+	}
+
+	if (!dfs_master_capable &&
+	    policy_mgr_is_bonded_chan_dfs(hdd_ctx->psoc,
+					  config->ch_width_orig,
+					  config->ch_params.mhz_freq_seg1,
+					  config->chan_freq)) {
+		hdd_err("Failed to bringup SAP; Atleast one bonded channel is DFS");
+		ret = -EINVAL;
+		goto error;
+	}
+
 	if (wlan_hdd_setup_driver_overrides(adapter)) {
 		ret = -EINVAL;
 		goto error;

From a05138617ca027054782c52d1383ea9be46e4a37 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 13 May 2026 12:02:32 -0700
Subject: [PATCH 246/290] fw-api: CL 32516836 - update fw common interface
 files

Change-Id: Ie1c92d1f9f52920395b0e00acfaca4d8b8ab5cfe
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 6 ++++++
 fw/wmi_unified.h  | 3 +++
 fw/wmi_version.h  | 2 +-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 34edff232b59..2ff0b90c30e8 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -815,6 +815,12 @@ typedef  enum  {
     WMI_SERVICE_UHR_CO_AP_CTDMA_TB_PPDU_SUPPORT = 512,
     WMI_SERVICE_UHR_CO_AP_CTDMA_TXOP_RETURN_SUPPORT = 513,
 
+    /*
+     * Indicates FW supports cloud based control for Uplink Tx Beamformer
+     * AP configuration
+     */
+    WMI_SERVICE_SUPPORT_UL_TX_BEAMFORMER_AP_CONFIG = 514,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 343c91f7e02d..15bab1960b09 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -28529,6 +28529,7 @@ typedef struct {
 #define WMI_MAX_VENDOR_OUI_DATA_LENGTH                 20
 
 #define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_ALLOW_DISALLOW_NSS 30
+#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_UL_TX_BEAMFORMER 30
 #define WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH                     64
 
 typedef enum
@@ -28638,6 +28639,8 @@ typedef enum
     /* connection in 2 x 2 */
     WMI_VENDOR_OUI_ACTION_DISALLOW_NSS_GREATER_THAN_2 = 129,
 
+    WMI_VENDOR_OUI_ACTION_ENABLE_UL_TX_BEAMFORMER = 130,
+
 
     /* Add any new dynamic length action ID before this line */
     WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d240459659aa..c6313e5a0c2e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1763
+#define __WMI_REVISION_ 1764
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 44c9746282ac97289d90a660b1cfb639ccf95a4d Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 15 May 2026 18:02:00 -0700
Subject: [PATCH 247/290] fw-api: CL 32544807 - update fw common interface
 files

Change-Id: Id45d1786ca4116b28a367b3705928a9e434e99a8
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 4 ++++
 fw/wmi_version.h | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 15bab1960b09..f19420b4e557 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19422,6 +19422,10 @@ enum WMI_VDEV_UP_FLAGS {
      * Valid only for VBSS subtype vaps.
      */
     WMI_VDEV_UP_FLAG_VBSS_PASSIVE  = 0x00000004,
+    /** REDUCE_OFF_DIAGONAL_NULL_THR
+     * The flag will be set to reduce off diagonal nulling threshold.
+     */
+    WMI_VDEV_UP_FLAG_REDUCE_OFF_DIAGONAL_NULL_THR = 0x00000008,
 };
 
 typedef struct{
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c6313e5a0c2e..9c9e6a072807 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1764
+#define __WMI_REVISION_ 1765
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From bb466adee1ff83586e1c61092a07f0898c43d433 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 16 May 2026 18:01:51 -0700
Subject: [PATCH 248/290] fw-api: CL 32554999 - update fw common interface
 files

Change-Id: Id7721d7fa0705aab328628fd6737921380fe3882
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  3 ++-
 fw/wmi_unified.h  | 59 +++++++++++++++++++++++++++++++++++++++++++----
 fw/wmi_version.h  |  2 +-
 3 files changed, 58 insertions(+), 6 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 6c1e2779b5ab..54aeed3061d5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -4980,7 +4980,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_VDEV_WORK_MEMORY_CMDID);
 /* Enable/Disable Smart Antenna */
 #define WMITLV_TABLE_WMI_PDEV_SMART_ANT_ENABLE_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, wmi_pdev_smart_ant_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pdev_smart_ant_param, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_ENABLE_CMDID);
 
 /* Set Smart Antenna RX antenna */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f19420b4e557..378fb0f4524f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10688,6 +10688,17 @@ typedef enum {
      * after radar detection
      */
     WMI_PDEV_PARAM_DFS_NOL_CSA_WAIT_TIMEOUT,
+
+    /**
+     * Smart antenna MPDU MCS params config.
+     * bit   | purpose
+     * ------|---------
+     * 0:9   | Max MPDU count for training
+     * 10    | MCS margin enable (0: disable, 1: enable)
+     * 11:13 | MCS margin value
+     * 14:31 | Reserved
+     */
+    WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -37329,11 +37340,29 @@ typedef struct {
     A_UINT32 rx_antenna;          /* rx antenna */
     A_UINT32 tx_default_antenna;  /* tx default antenna */
    /*
-    * Following this structure is the TLV:
-    * wmi_pdev_smart_ant_gpio_handle
+    * Following this structure are the TLVs:
+    *   - wmi_pdev_smart_ant_gpio_handle
+    *
+    *   - A_UINT32 pdev_smart_ant_param[]
+    *     bit 0   : enable separate antenna for RTS (1:enable, 0:disable)
+    *               Refer to WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET/SET
+    *     bit 1-31: reserved
     */
 } wmi_pdev_smart_ant_enable_cmd_fixed_param;
 
+/*
+ * Bit field definitions for pdev_smart_ant_param A_UINT32
+ * within WMI_PDEV_SMART_ANT_ENABLE_CMDID
+ */
+#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS   0
+#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS  1
+
+#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET(enable_field) \
+    WMI_GET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS)
+
+#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_SET(enable_field, value) \
+    WMI_SET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS, value)
+
 /** GPIO pins/function values to control antennas */
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle */
@@ -37402,15 +37431,35 @@ typedef struct {
 #define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \
     WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value)
 
+#define WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS     25
+#define WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS    1
+
+#define WMI_GET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold) \
+    WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS)
+
+#define WMI_SET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold, value) \
+    WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS, value)
+
+#define WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS     26
+#define WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS    1
+
+#define WMI_GET_SA_TRAIN_USING_QOS_NULL(per_threshold) \
+    WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS)
+
+#define WMI_SET_SA_TRAIN_USING_QOS_NULL(per_threshold, value) \
+    WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS, value)
+
+
 #define WMI_RATE_SERIES_320_BIT_POS     0
 #define WMI_RATE_SERIES_320_NUM_BITS    16
 
 #define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \
     WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS)
 
-#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \
+#define WMI_SET_RATE_SERIES_320(train_rate_series_ext, value) \
     WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value)
 
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */
     /* rate array */
@@ -37453,7 +37502,9 @@ typedef struct {
      *    0  | PER Threshold is valid
      *  1:8  | Per Threshold
      *  9:24 | min_tx_pkts Minimum number of pkts need to be checked
-     * 25:31 | Reserved
+     *    25 | enable_training_for_latency_traffic
+     *    26 | train_using_qos_null
+     * 27:31 | Reserved
      */
     A_UINT32 per_threshold;
 /*
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9c9e6a072807..c6acc0a3926d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1765
+#define __WMI_REVISION_ 1766
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ade1ddf800d0d99c36d860867b2da714d903cb47 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 17 May 2026 18:04:15 -0700
Subject: [PATCH 249/290] fw-api: CL 32559532 - update fw common interface
 files

Change-Id: Iae691011c4602fe236e0fc4296621e267a91f3b4
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 7 +++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 378fb0f4524f..ea778567c827 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -56785,6 +56785,13 @@ typedef enum {
     WMI_RTT_GI_ZERO_POWER  = 4,  /* "zero power GI" (secure LTF behavior) */
 } WMI_RTT_GI_TYPE;
 
+typedef enum {
+    WMI_PEER_AUTHORIZE_CLEAR = 0,
+    WMI_PEER_AUTHORIZE_SECURED_MODE = 1,
+    WMI_PEER_AUTHORIZE_OPEN_MODE = 2,
+    WMI_PEER_AUTHORIZE_SW_ENCRYPTION_MODE = 3,
+} WMI_PEER_AUTHORIZE_TYPE;
+
 /*
  * macros to set/get bitfields within
  * wmi_rtt_peer_meas_report_peer_meas_result_info
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index c6acc0a3926d..d4a06a98720d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1766
+#define __WMI_REVISION_ 1767
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 7f34bf2dc154a7c100e1e6fe7a52e6afeb099d2e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 17 May 2026 18:06:15 -0700
Subject: [PATCH 250/290] fw-api: CL 32559793 - update fw common interface
 files

Change-Id: I2a12086d2ee447478ed5b051a22d9c36c97e545b
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 8 ++++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ea778567c827..94ee224803ac 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10699,6 +10699,14 @@ typedef enum {
      * 14:31 | Reserved
      */
     WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS,
+
+    /** On-demand AWGN interference status request.
+     * FW reads awgn_prev_int_seg and sends WMI_DCS_INTERFERENCE_EVENTID
+     * with interference_type=ATH_CAP_DCS_AGWNIM only if interference is
+     * currently detected (bitmap != 0). A bitmap of 0 means no interference.
+     * param_value is reserved (set to 1 to trigger the request).
+     */
+    WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d4a06a98720d..ba153a8ef1e9 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1767
+#define __WMI_REVISION_ 1768
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From fb917f8bc73d0aed71016c62a19bb1f08c432852 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 17 May 2026 18:08:18 -0700
Subject: [PATCH 251/290] fw-api: CL 32560454 - update fw common interface
 files

Change-Id: I1481d231bd2e470b22042631db664126f5596a7e
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  3 +++
 fw/wmi_unified.h  | 63 ++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 52 insertions(+), 14 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 2ff0b90c30e8..f6b3b8e2c00d 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -821,6 +821,9 @@ typedef  enum  {
      */
     WMI_SERVICE_SUPPORT_UL_TX_BEAMFORMER_AP_CONFIG = 514,
 
+    /* Indicates FW supports enable/disable TWT per vdev */
+    WMI_SERVICE_STA_TWT_EN_DIS_VDEV_SUPPORT = 515,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 94ee224803ac..069863abddbc 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44684,25 +44684,25 @@ typedef struct {
 #define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \
     WMI_SET_BITS(flag, 7, 1, val)
 
-/* bits 8-15: unused / reserved */
-
 /*
- * Bit 16: indicates whether pdev_id is valid or vdev_id is valid.
+ * Bit 8: indicates whether pdev_id is valid or vdev_id is valid.
  * 0: pdev_id is valid (MAC-level TWT enable/disable)
  * 1: vdev_id is valid (STA vdev-level TWT enable/disable)
  */
-#define TWT_EN_DIS_FLAGS_GET_VDEV_ID(flag)      WMI_GET_BITS(flag, 16, 1)
-#define TWT_EN_DIS_FLAGS_SET_VDEV_ID(flag, val) WMI_SET_BITS(flag, 16, 1, val)
+#define TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flag)      WMI_GET_BITS(flag, 8, 1)
+#define TWT_EN_DIS_FLAGS_SET_VDEV_SUPPORT(flag, val) WMI_SET_BITS(flag, 8, 1, val)
+
+/* bits 9-31: unused / reserved */
 
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param  */
     /**
-     * pdev_id or vdev_id depending on bit 16 of flags.
-     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 0:
+     * pdev_id or vdev_id depending on bit 8 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0:
      *   pdev_id identifies the MAC.
      *   See macros starting with WMI_PDEV_ID_ for values.
      *   In non-DBDC case host should set it to 0.
-     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 1:
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1:
      *   vdev_id is for STA vdev-level TWT enable.
      *   TWT enable applies only to that specific STA vdev.
      */
@@ -44752,20 +44752,37 @@ typedef enum _WMI_ENABLE_TWT_STATUS_T {
 
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_complete_event_fixed_param */
-    /** pdev_id for identifying the MAC.  See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */
-    A_UINT32 pdev_id;
+    /**
+     * pdev_id or vdev_id depending on bit 8 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0:
+     *   pdev_id identifies the MAC.
+     *   See macros starting with WMI_PDEV_ID_ for values.
+     *   In non-DBDC case host should set it to 0.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1:
+     *   vdev_id is for STA vdev-level TWT enable.
+     *   TWT enable applies only to that specific STA vdev.
+     */
+    union {
+        A_UINT32 pdev_id;
+        A_UINT32 vdev_id;
+    };
     A_UINT32 status;        /* WMI_ENABLE_TWT_STATUS_T */
+    /* flags:
+     * mirrors TWT_EN_DIS_FLAGS_* from the enable command;
+     * bit 8 indicates pdev vs vdev
+     */
+    A_UINT32 flags;
 } wmi_twt_enable_complete_event_fixed_param;
 
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_cmd_fixed_param  */
     /**
-     * pdev_id or vdev_id depending on bit 16 of flags.
-     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 0:
+     * pdev_id or vdev_id depending on bit 8 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0:
      *   pdev_id identifies the MAC.
      *   See macros starting with WMI_PDEV_ID_ for values.
      *   In non-DBDC case host should set it to 0.
-     * When TWT_EN_DIS_FLAGS_GET_VDEV_ID(flags) == 1:
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1:
      *   vdev_id is for STA vdev-level TWT disable.
      *   TWT disable applies only to that specific STA vdev.
      */
@@ -44779,8 +44796,26 @@ typedef struct {
 
 typedef struct {
     A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_complete_event_fixed_param */
-    A_UINT32 pdev_id;
+    /**
+     * pdev_id or vdev_id depending on bit 8 of flags.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0:
+     *   pdev_id identifies the MAC.
+     *   See macros starting with WMI_PDEV_ID_ for values.
+     *   In non-DBDC case host should set it to 0.
+     * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1:
+     *   vdev_id is for STA vdev-level TWT disable.
+     *   TWT disable applies only to that specific STA vdev.
+     */
+    union {
+        A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC  */
+        A_UINT32 vdev_id;
+    };
     A_UINT32 status; /* refer to WMI_DISABLE_TWT_STATUS_T enum */
+    /* flags:
+     * mirrors TWT_EN_DIS_FLAGS_* from the enable command;
+     * bit 8 indicates pdev vs vdev
+     */
+    A_UINT32 flags;
 } wmi_twt_disable_complete_event_fixed_param;
 
 typedef struct {

From 3759ce5221446164d7bef684402d16116215e927 Mon Sep 17 00:00:00 2001
From: Surya Prakash Sivaraj <suryapra@qti.qualcomm.com>
Date: Fri, 22 May 2026 11:01:54 +0530
Subject: [PATCH 252/290] qcacld-3.0: Add print log for new roam scan type

Firmware sends the roam scan info tlv to driver during roaming.
Currently, in this tlv, firmware fills scan type as (0-3) and
driver log this as "PARTIAL", "FULL", "NO SCAN" and "Higher Band"
But with new requirement, idle roaming shall only roam to higher band
(2.4 GHz < 5 GHz < 6 GHz) than current band.
1. If current band is 2.4 GHz, it cannot roam to 2.4 GHz.
It can roam to 5 GHz and 6 GHz.
2. If current band is 5 GHz, it cannot roam to 2.4 GHz and 5 GHz.
It can roam to 6 GHz.
So, to add this requirement, firmware introduces new scan type 4 for
which driver need to log.

Change-Id: I80d1c47a434da5009aed4cab08c6eae91bda5b0e
CRs-Fixed: 3379468
---
 .../mlme/dispatcher/inc/wlan_mlme_api.h       | 23 +++++++++++++++++--
 .../mlme/dispatcher/src/wlan_mlme_api.c       | 12 ++++++----
 core/hdd/src/wlan_hdd_stats.c                 |  6 +++--
 core/wma/src/wma_scan_roam.c                  |  2 +-
 4 files changed, 33 insertions(+), 10 deletions(-)

diff --git a/components/mlme/dispatcher/inc/wlan_mlme_api.h b/components/mlme/dispatcher/inc/wlan_mlme_api.h
index 401bd9c549e5..3b757579f129 100644
--- a/components/mlme/dispatcher/inc/wlan_mlme_api.h
+++ b/components/mlme/dispatcher/inc/wlan_mlme_api.h
@@ -2444,11 +2444,30 @@ wlan_mlme_get_ignore_fw_reg_offload_ind(struct wlan_objmgr_psoc *psoc,
 char *mlme_get_roam_trigger_str(uint32_t roam_scan_trigger);
 
 /**
- * mlme_get_roam_scan_type_str() - Get the string for roam sacn type
+ * enum roam_stats_scan_type  - Roam scan type defines
+ * @ROAM_STATS_SCAN_TYPE_PARTIAL: Partial scan
+ * @ROAM_STATS_SCAN_TYPE_FULL: Full scan
+ * @ROAM_STATS_SCAN_TYPE_NO_SCAN: No roam scan was triggered. This is generally
+ * used in BTM events to indicate BTM frame exchange logs.
+ * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ: Higher band roam scan from 2 GHz
+ * to 5 GHz or 6 GHz
+ * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ: Higher band roam scan from 5 GHz to
+ * 6 GHz
+ */
+enum roam_stats_scan_type {
+	ROAM_STATS_SCAN_TYPE_PARTIAL = 0,
+	ROAM_STATS_SCAN_TYPE_FULL = 1,
+	ROAM_STATS_SCAN_TYPE_NO_SCAN = 2,
+	ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ = 3,
+	ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ = 4,
+};
+
+/**
+ * mlme_get_roam_scan_type_str() - Get the string for roam scan type
  * @roam_scan_type: roam scan type coming from fw via
  * wmi_roam_scan_info tlv
  *
- *  Return: Meaningful string for roam sacn type
+ *  Return: Meaningful string for roam scan type
  */
 char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type);
 
diff --git a/components/mlme/dispatcher/src/wlan_mlme_api.c b/components/mlme/dispatcher/src/wlan_mlme_api.c
index dd930d969742..633b36067c91 100644
--- a/components/mlme/dispatcher/src/wlan_mlme_api.c
+++ b/components/mlme/dispatcher/src/wlan_mlme_api.c
@@ -3793,14 +3793,16 @@ char *mlme_get_roam_status_str(uint32_t roam_status)
 char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type)
 {
 	switch (roam_scan_type) {
-	case 0:
+	case ROAM_STATS_SCAN_TYPE_PARTIAL:
 		return "PARTIAL";
-	case 1:
+	case ROAM_STATS_SCAN_TYPE_FULL:
 		return "FULL";
-	case 2:
+	case ROAM_STATS_SCAN_TYPE_NO_SCAN:
 		return "NO SCAN";
-	case 3:
-		return "Higher Band";
+	case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ:
+		return "Higher Band: 5 GHz + 6 GHz";
+	case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ:
+		return "Higher Band : 6 GHz";
 	default:
 		return "UNKNOWN";
 	}
diff --git a/core/hdd/src/wlan_hdd_stats.c b/core/hdd/src/wlan_hdd_stats.c
index 8f7deb17dcda..47c143862f89 100644
--- a/core/hdd/src/wlan_hdd_stats.c
+++ b/core/hdd/src/wlan_hdd_stats.c
@@ -3914,7 +3914,8 @@ hdd_get_roam_rt_stats_event_len(struct mlme_roam_debug_info *roam_stats)
 		len += nla_total_size(sizeof(uint8_t));
 
 	if (roam_stats->scan.present) {
-		if (roam_stats->scan.num_chan && !roam_stats->scan.type)
+		if (roam_stats->scan.num_chan &&
+		    roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL)
 			for (i = 0; i < roam_stats->scan.num_chan;)
 				i++;
 
@@ -3987,7 +3988,8 @@ roam_rt_stats_fill_scan_freq(struct sk_buff *vendor_event,
 		kfree_skb(vendor_event);
 		return;
 	}
-	if (roam_stats->scan.num_chan && !roam_stats->scan.type) {
+	if (roam_stats->scan.num_chan &&
+	    roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL) {
 		for (i = 0; i < roam_stats->scan.num_chan; i++) {
 			if (nla_put_u32(vendor_event, i,
 					roam_stats->scan.chan_freq[i])) {
diff --git a/core/wma/src/wma_scan_roam.c b/core/wma/src/wma_scan_roam.c
index 276f64af9cf8..915e196f4d81 100644
--- a/core/wma/src/wma_scan_roam.c
+++ b/core/wma/src/wma_scan_roam.c
@@ -2070,7 +2070,7 @@ wma_rso_print_scan_info(struct wmi_roam_scan_data *scan, uint8_t vdev_id,
 
 	tmp = buf;
 	/* For partial scans, print the channel info */
-	if (!scan->type) {
+	if (scan->type == ROAM_STATS_SCAN_TYPE_PARTIAL) {
 		buf_cons = qdf_snprint(tmp, buf_left, "{");
 		buf_left -= buf_cons;
 		tmp += buf_cons;

From 8614fa0454ca3a9a4783721b86dc0c1f19046015 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 22 May 2026 18:02:25 -0700
Subject: [PATCH 253/290] fw-api: CL 32578922 - update fw common interface
 files

 SCL original promoter: ddahlby (SCL=32573576)
WINE promoted user: yeshanit
WINE request id: 5903286

Jobs fixed ...

ChangeRequest4539549 on 2026/05/18 by prismsvc *closed*

Job created automatically by Orbit/PRISM to track changes for Change Request 4539549. Please visit https://orbit/CR/4539549 for details for the Change Request.

Affected files ...

... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_services.h#437 edit
... //components/rel/wlanfw_cmn.cnss/1.0.0/fw_interface/include/wmi_version.h#1721 edit

Change-Id: I0d5a4c167bdab1b650073a0c60bb6c7964aa677e
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 8 ++++++++
 fw/wmi_version.h  | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index f6b3b8e2c00d..ddbfd3f67fce 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -824,6 +824,14 @@ typedef  enum  {
     /* Indicates FW supports enable/disable TWT per vdev */
     WMI_SERVICE_STA_TWT_EN_DIS_VDEV_SUPPORT = 515,
 
+    /*
+     * Indicates FW supports AWGN interference status request via
+     * WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST, allowing host to query
+     * the current AWGN CCA segment bitmap (awgn_prev_int_seg) which
+     * is sent back immediately via WMI_DCS_INTERFERENCE_EVENTID.
+     */
+    WMI_SERVICE_AWGN_INT_STATUS_REQUEST_SUPPORT = 516,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ba153a8ef1e9..9fe5aa0931f8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1768
+#define __WMI_REVISION_ 1769
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 074f7db0f398677aa84362ade95a2215d484929e Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 22 May 2026 18:04:25 -0700
Subject: [PATCH 254/290] fw-api: CL 32623458 - update fw common interface
 files

Change-Id: I813789353f01b866f6c6aa133c18520a1b92e6d3
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index ddbfd3f67fce..830df224684c 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -832,6 +832,8 @@ typedef  enum  {
      */
     WMI_SERVICE_AWGN_INT_STATUS_REQUEST_SUPPORT = 516,
 
+    WMI_SERVICE_WMI_ANOMALY_REPORTING = 517,
+
 
     WMI_MAX_EXT2_SERVICE
 

From db9a57ba1be07e9da38c303f258b82fcdf57d16a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 22 May 2026 18:08:56 -0700
Subject: [PATCH 255/290] fw-api: CL 32623461 - update fw common interface
 files

Change-Id: I97631e151f90475b4744303fcd5a0d5fd94e270e
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 278 ++++++++++++++++++++++++++++-------------------
 fw/wmi_version.h |   2 +-
 2 files changed, 165 insertions(+), 115 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 069863abddbc..1d3b698c5492 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -3257,8 +3257,15 @@ typedef struct _wmi_ppe_threshold {
 #define WMI_MAX_EHTCAP_MAC_SIZE  2
 #define WMI_MAX_EHTCAP_PHY_SIZE  3
 
+/* WMI_MAX_UHRCAP_MAC_SIZE:
+ * Kept as 4 for backwards compatibility, elements [2] and [3] are reserved.
+ */
 #define WMI_MAX_UHRCAP_MAC_SIZE  4
 #define WMI_MAX_UHRCAP_PHY_SIZE  8 /* as per spec recommendation */
+/* WMI_MAX_UHRCAP_DBE_SIZE:
+ * B0-B7 header + up to 24+24 bits EHT-MCS maps
+ */
+#define WMI_MAX_UHRCAP_DBE_SIZE  2
 
 /*
  * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid)
@@ -4268,6 +4275,14 @@ typedef struct {
      */
     A_UINT32 uhr_cap_mac_info[WMI_MAX_UHRCAP_MAC_SIZE];
 
+    /*
+     * UHR DBE Capability Parameters:
+     * total WMI_MAX_UHRCAP_DBE_SIZE * A_UINT32 bits
+     * Present only when DBE Support bit (B10) in uhr_cap_mac_info is set.
+     * Carries DBE Maximum Supported Bandwidth and optional EHT-MCS Maps.
+     */
+    A_UINT32 uhr_cap_dbe_info[WMI_MAX_UHRCAP_DBE_SIZE];
+
     /* Followed by next TLVs:
      *     WMI_DMA_RING_CAPABILITIES          dma_ring_caps[];
      *     wmi_spectral_bin_scaling_params    wmi_bin_scaling_params[];
@@ -23746,6 +23761,13 @@ typedef struct {
      */
     wmi_ppe_threshold peer_uhr_ppet;
 
+    /** peer_uhr_cap_dbe:
+     * UHR DBE Capability Parameters from BSS beacon UHR cap IE,
+     * total WMI_MAX_UHRCAP_DBE_SIZE*A_UINT32 bits.
+     * Valid only when DBE Support bit (B10) in peer_uhr_cap_mac is set.
+     */
+    A_UINT32 peer_uhr_cap_dbe[WMI_MAX_UHRCAP_DBE_SIZE];
+
 /* Following this struct are the TLV's:
  *     A_UINT8 peer_legacy_rates[];
  *     A_UINT8 peer_ht_rates[];
@@ -40999,6 +41021,13 @@ typedef struct {
                 reserved2: 24;
         };
     };
+
+    /*
+     * UHR DBE Capability Parameters of 802.11bn
+     * (conditional on DBE Support bit)
+     */
+    A_UINT32 uhr_cap_dbe_info_2G[WMI_MAX_UHRCAP_DBE_SIZE];
+    A_UINT32 uhr_cap_dbe_info_5G[WMI_MAX_UHRCAP_DBE_SIZE];
 } WMI_MAC_PHY_CAPABILITIES_EXT2;
 
 #define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \
@@ -41025,40 +41054,40 @@ typedef struct {
 #define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 1, 1, value)
 
-/* Bit 2: Max Nss Rx for sounding NDP (≤ 160 MHz) */
+/* Bit 2: Max Nss Rx for sounding NDP (= 160 MHz) */
 #define WMI_UHRCAP_PHY_MAX_NSS_RX_160_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 2, 1)
 #define WMI_UHRCAP_PHY_MAX_NSS_RX_160_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 2, 1, value)
 
-/* Bit 3: Max Nss,total Rx for DL MU-MIMO (≤ 160 MHz) */
+/* Bit 3: Max Nss,total Rx for DL MU-MIMO (= 160 MHz) */
 #define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 3, 1)
 #define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 3, 1, value)
 
-/* Bit 4: Max Nss Rx for sounding NDP (≤ 320 MHz) */
+/* Bit 4: Max Nss Rx for sounding NDP (= 320 MHz) */
 #define WMI_UHRCAP_PHY_MAX_NSS_RX_320_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 4, 1)
 #define WMI_UHRCAP_PHY_MAX_NSS_RX_320_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 4, 1, value)
 
-/* Bit 5: Max Nss,total Rx for DL MU-MIMO (≤ 320 MHz) */
+/* Bit 5: Max Nss,total Rx for DL MU-MIMO (= 320 MHz) */
 #define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 5, 1)
 #define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 5, 1, value)
 
-/* Bit 6: ELR Rx Support */
-#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \
+/* Bit 6: ELR Tx Support */
+#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 6, 1)
-#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 6, 1, value)
 
-/* Bit 7: ELR Tx Support */
-#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \
+/* Bit 7: ELR Rx Support */
+#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 7, 1)
-#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value)
 
 /* Bit 8: Partial BW DL MU-MIMO support */
@@ -41073,128 +41102,126 @@ typedef struct {
 #define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 9, 1, value)
 
-/* Bit 10: COBF support */
-#define WMI_UHRCAP_PHY_COBF_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 10: MCS 15 support */
+#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 10, 1)
-#define WMI_UHRCAP_PHY_COBF_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 10, 1, value)
 
-/* Bit 11: COBF Joint Sounding Support */
-#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 11: 2XLDPC Tx Support */
+#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 11, 1)
-#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 11, 1, value)
 
-/* Bit 12: COSR Mode 1 Support */
-#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 12: 2XLDPC Rx Support */
+#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 12, 1)
-#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 12, 1, value)
 
-/* Bit 13: COSR Mode 2 Support */
-#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_GET(uhr_cap_phy) \
-    WMI_GET_BITS(uhr_cap_phy[0], 13, 1)
-#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_SET(uhr_cap_phy, value) \
-    WMI_SET_BITS(uhr_cap_phy[0], 13, 1, value)
-
-/* Bits 14-15: UEQM Tx Max NSS Tx Support */
+/* Bits 13-14: UEQM Tx Support and Max NSS Tx */
 #define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_GET(uhr_cap_phy) \
-    WMI_GET_BITS(uhr_cap_phy[0], 14, 2)
+    WMI_GET_BITS(uhr_cap_phy[0], 13, 2)
 #define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_SET(uhr_cap_phy, value) \
-    WMI_SET_BITS(uhr_cap_phy[0], 14, 2, value)
+    WMI_SET_BITS(uhr_cap_phy[0], 13, 2, value)
 
-/* Bits 16-17:UEQM Rx Max NSS Rx Support */
+/* Bits 15-16: UEQM Rx Support and Max NSS Rx */
 #define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_GET(uhr_cap_phy) \
-    WMI_GET_BITS(uhr_cap_phy[0], 16, 2)
+    WMI_GET_BITS(uhr_cap_phy[0], 15, 2)
 #define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_SET(uhr_cap_phy, value) \
-    WMI_SET_BITS(uhr_cap_phy[0], 16, 2, value)
+    WMI_SET_BITS(uhr_cap_phy[0], 15, 2, value)
 
-/* Bit 18: UEQM LT 242ToneRU support */
-#define WMI_UHRCAP_PHY_UEQM_LT_242TONERU_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 17: Reserved */
+
+/* Bit 18: Co-BF joint sounding support */
+#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 18, 1)
-#define WMI_UHRCAP_PHY_UEQM_LT_242TONERU_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 18, 1, value)
 
-/* Bit 19: DRU DBW 20 PWB 20 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_20_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 19: IM pilots tx support */
+#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 19, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_20_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 19, 1, value)
 
-/* Bit 20: DRU DBW 40 PWB 40 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_40_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 20: IM pilots rx support */
+#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 20, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_40_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 20, 1, value)
 
-/* Bit 21: DRU DBW 80 PWB 80 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_80_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 21: COSR mode 1 support */
+#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 21, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_80_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 21, 1, value)
 
-/* Bit 22: DRU DBW 20 PWB 80 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 22: COSR mode 2 support */
+#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 22, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_20_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 22, 1, value)
 
-/* Bit 23: DRU DBW 40 PWB 80 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 23: DRU DBW 20 in PBW 20 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 23, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_40_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 23, 1, value)
 
-/* Bit 24: DRU DBW 60 PWB 80 support */
-#define WMI_UHRCAP_PHY_DRU_DBW_60_PWB_80_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 24: DRU DBW 40 in PBW 40 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 24, 1)
-#define WMI_UHRCAP_PHY_DRU_DBW_60_PWB_80_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 24, 1, value)
 
-/* Bit 25: DRU RRU HYBRID support */
-#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 25: DRU DBW 80 in PBW 80 support */
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 25, 1)
-#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 25, 1, value)
 
-/* Bit 26: 2XLDPC Tx Support */
-#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 26: DRU DBW 80 in PBW 160 MHz support */
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 26, 1)
-#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 26, 1, value)
 
-/* Bit 27: 2XLDPC Rx Support */
-#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 27: DRU DBW 80 in PBW 320 MHz support */
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 27, 1)
-#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 27, 1, value)
 
-/* Bit 28: IM Pilots Tx Support */
-#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 28: DRU DBW 20 in PBW >= 80 MHz support */
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 28, 1)
-#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 28, 1, value)
 
-/* Bit 29: IM Pilots Rx Support */
-#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 29: DRU DBW 40 in PBW >= 80 MHz support */
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 29, 1)
-#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 29, 1, value)
 
-/* Bit 30: MCS 15 Support */
-#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 30: DRU DBW 60 in PBW >= 80 MHz support */
+#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 30, 1)
-#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 30, 1, value)
 
-/* Bit 31: Intermediate MCS Support */
-#define WMI_UHRCAP_PHY_INTERMEDIATE_MCS_SUPPORT_GET(uhr_cap_phy) \
+/* Bit 31: DRU+RRU hybrid mode support */
+#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_GET(uhr_cap_phy) \
     WMI_GET_BITS(uhr_cap_phy[0], 31, 1)
-#define WMI_UHRCAP_PHY_INTERMEDIATE_MCS_SUPPORT_SET(uhr_cap_phy, value) \
+#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_SET(uhr_cap_phy, value) \
     WMI_SET_BITS(uhr_cap_phy[0], 31, 1, value)
 
+/* Bits 32-39: Reserved */
+
 /*
- * ToDo: Bits 32-63
+ * ToDo: Bits 40-63
  */
 
 /*
@@ -41243,11 +41270,7 @@ typedef struct {
 #define WMI_UHRCAP_MAC_DPS_AP_HCM_SET(uhr_cap_mac, value) \
     WMI_SET_BITS(uhr_cap_mac[0], 2, 1, value)
 
-/* Bit 3: Multi Link Power Management support */
-#define WMI_UHRCAP_MAC_MULTI_LINK_PM_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[0], 3, 1)
-#define WMI_UHRCAP_MAC_MULTI_LINK_PM_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[0], 3, 1, value)
+/* Bit 3: Reserved */
 
 /* Bit 4: NPCA support */
 #define WMI_UHRCAP_MAC_NPCA_GET(uhr_cap_mac) \
@@ -41412,46 +41435,73 @@ typedef struct {
 #define WMI_UHRCAP_MAC_BTM_ASSURANCE_SET(uhr_cap_mac, value) \
     WMI_SET_BITS(uhr_cap_mac[1], 4, 1, value)
 
-/* Bits 36-63 --- Reserved */
+/* Bit 36: Co-BF Support */
+#define WMI_UHRCAP_MAC_COBF_SUPPORT_GET(uhr_cap_mac) \
+    WMI_GET_BITS(uhr_cap_mac[1], 5, 1)
+#define WMI_UHRCAP_MAC_COBF_SUPPORT_SET(uhr_cap_mac, value) \
+    WMI_SET_BITS(uhr_cap_mac[1], 5, 1, value)
 
-/* To be decided spec not provided clear bits */
+/* Bits 37-63 --- Reserved */
 
-
-/* Bit 64-66: DBE Capabilities Params */
-#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[2], 0, 3)
-#define WMI_UHRCAP_MAC_DBE_MAX_SUP_BW_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[2], 0, 3, value)
-
-
-/* Bit 67: EHT-MCS Map (BW=160 MHz) Present */
-#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[2], 3, 1)
-#define WMI_UHRCAP_MAC_EHT_MCS_160_PRESENT_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[2], 3, 1, value)
-
-/* Bit 68: EHT-MCS Map (BW=320 MHz) Present */
-#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[2], 4, 1)
-#define WMI_UHRCAP_MAC_EHT_MCS_320_PRESENT_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[2], 4, 1, value)
-
-/* Bit 69-71: Reserved */
-
-/* Bit 72 to 95: EHT-MCS Map (BW=160 MHz) */
-#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[2], 8, 24)
-#define WMI_UHRCAP_MAC_EHT_MCS_MAP_160_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[2], 8, 24, value)
-
-/* Bit 96 to 121: EHT-MCS Map (BW=320 MHz) */
-#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_GET(uhr_cap_mac) \
-    WMI_GET_BITS(uhr_cap_mac[3], 0, 24)
-#define WMI_UHRCAP_MAC_EHT_MCS_MAP_320_SET(uhr_cap_mac, value) \
-    WMI_SET_BITS(uhr_cap_mac[3], 0, 24, value)
+/*
+ * NOTE: uhr_cap_mac[2] and uhr_cap_mac[3] (bits 64-127) are reserved.
+ * WMI_MAX_UHRCAP_MAC_SIZE is kept at 4 for backward compatibility.
+ * DBE Capability Parameters are carried in the separate uhr_cap_dbe[]
+ * array using WMI_UHRCAP_DBE_* macros below.
+ */
 
 /****** End of 11BN UHR MAC Capabilities Information field ******/ /* } */
 
+/****** 11BN UHR DBE Capability Parameters field ******/ /* { */
+
+/* Bits B0-B2: DBE Maximum Supported Bandwidth
+ *
+ * DBE Maximum Supported Bandwidth Lookup Table
+ *
+ * +------------------+-----------------------------+
+ * | Sub-field Value  | DBE Bandwidth               |
+ * +------------------+-----------------------------+
+ * |        0         | Reserved                    |
+ * |        1         | 40 MHz DBE bandwidth        |
+ * |        2         | 80 MHz DBE bandwidth        |
+ * |        3         | 160 MHz DBE bandwidth       |
+ * |        4         | 320 MHz DBE bandwidth       |
+ * |      5 to 7      | Reserved                    |
+ * +------------------+-----------------------------+
+ */
+#define WMI_UHRCAP_DBE_MAX_SUP_BW_GET(uhr_cap_dbe) \
+    WMI_GET_BITS(uhr_cap_dbe[0], 0, 3)
+#define WMI_UHRCAP_DBE_MAX_SUP_BW_SET(uhr_cap_dbe, value) \
+    WMI_SET_BITS(uhr_cap_dbe[0], 0, 3, value)
+
+/* Bit B3: EHT-MCS Map (BW=160 MHz) Present */
+#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_GET(uhr_cap_dbe) \
+    WMI_GET_BITS(uhr_cap_dbe[0], 3, 1)
+#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_SET(uhr_cap_dbe, value) \
+    WMI_SET_BITS(uhr_cap_dbe[0], 3, 1, value)
+
+/* Bit B4: EHT-MCS Map (BW=320 MHz) Present */
+#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_GET(uhr_cap_dbe) \
+    WMI_GET_BITS(uhr_cap_dbe[0], 4, 1)
+#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_SET(uhr_cap_dbe, value) \
+    WMI_SET_BITS(uhr_cap_dbe[0], 4, 1, value)
+
+/* Bits B5-B7: Reserved */
+
+/* Bits B8-B31: EHT-MCS Map (BW=160 MHz) — present only if B3 is set (0 or 24 bits) */
+#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_GET(uhr_cap_dbe) \
+    WMI_GET_BITS(uhr_cap_dbe[0], 8, 24)
+#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_SET(uhr_cap_dbe, value) \
+    WMI_SET_BITS(uhr_cap_dbe[0], 8, 24, value)
+
+/* Bits B32-B55: EHT-MCS Map (BW=320 MHz) — present only if B4 is set (0 or 24 bits) */
+#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_GET(uhr_cap_dbe) \
+    WMI_GET_BITS(uhr_cap_dbe[1], 0, 24)
+#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_SET(uhr_cap_dbe, value) \
+    WMI_SET_BITS(uhr_cap_dbe[1], 0, 24, value)
+
+/****** End of 11BN UHR DBE Capability Parameters field ******/ /* } */
+
 #define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \
     WMI_GET_BITS(npca_capability, 0, 1)
 #define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9fe5aa0931f8..51d83b4f419c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1769
+#define __WMI_REVISION_ 1770
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c7c691adf7642f0895855cc380ebfd419a37aebb Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 22 May 2026 18:10:52 -0700
Subject: [PATCH 256/290] fw-api: CL 32626000 - update fw common interface
 files

Change-Id: I875fd08ee345df13f3109281b0a00c43c0fd3bb5
CRs-Fixed: 3830439
---
 fw/htt.h       |  2 ++
 fw/htt_stats.h | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index 0a50c23b9cf1..18d7614c2450 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -937,6 +937,8 @@ typedef enum {
     HTT_STATS_CTL_TAG                               = 258, /* htt_stats_ctl_tlv */
     HTT_STATS_ENHANCED_CTL_TAG                      = 259, /* htt_stats_enhanced_ctl_tlv */
     HTT_STATS_NPCA_TAG                              = 260, /* htt_stats_npca_tlv */
+    HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TAG      = 261, /* htt_stats_sched_txq_tx_mode_simplified_tlv */
+    HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TAG          = 262, /* htt_stats_sched_txq_tx_mode_winner_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 68c6c694a69b..36e7615294db 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -5381,6 +5381,24 @@ typedef htt_stats_error_tlv_v
 typedef htt_stats_error_tlv_v
     htt_stats_unavailable_error_stats_tlv;
 
+/* NOTE: Variable length TLV, use length spec to infer array size */
+#define HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TLV_SZ(_num_elems) \
+    (sizeof(A_UINT32) * (_num_elems))
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /** Scheduler command posted per tx_mode (length = num tx modes+1) */
+    HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_simplified);
+} htt_stats_sched_txq_tx_mode_simplified_tlv;
+
+/* NOTE: Variable length TLV, use length spec to infer array size */
+#define HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TLV_SZ(_num_elems) \
+    (sizeof(A_UINT32) * (_num_elems))
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /** Scheduler command posted per tx_mode (length = num tx modes+1) */
+    HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_winner);
+} htt_stats_sched_txq_tx_mode_winner_tlv;
+
 typedef enum {
     HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true                                       */
     HTT_SCHED_TID_SKIP_NOTIFY_MPDU,             /* Skip the tid's 2nd sched_cmd when 1st cmd is ongoing                                          */

From 58fbfa4df8801654710ae79daa547352ef703fd1 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 23 May 2026 18:01:52 -0700
Subject: [PATCH 257/290] fw-api: CL 32636152 - update fw common interface
 files

Change-Id: I765f7cf88c5361bb627b080c79fd740a888c10d1
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 7 +++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 1d3b698c5492..afbe126ea6b1 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10722,6 +10722,13 @@ typedef enum {
      * param_value is reserved (set to 1 to trigger the request).
      */
     WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST,
+
+    /**
+     * Disable L3 validity check in offload manager.
+     * 0 - L3_valid check enabled (default)
+     * 1 - L3_valid check disabled (frames not dropped on L3_valid=false)
+     */
+    WMI_PDEV_PARAM_ENABLE_OFFLD_L3_VALID_CHECK,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 51d83b4f419c..14bd31b096bd 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1770
+#define __WMI_REVISION_ 1771
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From a5743ff473524adf98a42db6a9e5e64ac845187a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 24 May 2026 18:01:50 -0700
Subject: [PATCH 258/290] fw-api: CL 32640276 - update fw common interface
 files

Change-Id: Ibf222d4c6c6fc5b39550a96b4ed9343687211e9d
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h |  14 +-
 fw/wmi_unified.h  | 392 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 405 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 54aeed3061d5..f027d8ebccae 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1641,6 +1641,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_mapc_cosr_params,
     WMITLV_TAG_STRUC_wmi_mapc_cobf_params,
     WMITLV_TAG_STRUC_wmi_mapc_cortwt_params,
+    WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param,
+    WMITLV_TAG_STRUC_wmi_lpi_ap_info_t,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2622,6 +2624,7 @@ typedef enum {
     OP(WMI_ANOMALY_REPORT_EVENTID) \
     OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \
     OP(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID) \
+    OP(WMI_LPI_SCAN_RESULT_EVENTID_V2) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -4428,15 +4431,22 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PREAUTH_START_EVENTID);
 WMITLV_CREATE_PARAM_STRUC(WMI_LPI_RESULT_EVENTID);
 
 /* LPI Status Event */
-#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len)                                                         \
+#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, wmi_lpi_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_LPI_STATUS_EVENTID);
 
 /* LPI Handoff Event */
-#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len)                                                         \
+#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, wmi_lpi_handoff_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_LPI_HANDOFF_EVENTID);
 
+/* LPI Scan Result Indication Event */
+#define WMITLV_TABLE_WMI_LPI_SCAN_RESULT_EVENTID_V2(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param, wmi_lpi_scan_result_ind_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, freq_list, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_lpi_ap_info_t, ap_array, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_LPI_SCAN_RESULT_EVENTID_V2);
+
 /* Thermal Manager Params*/
 #define WMITLV_TABLE_WMI_THERMAL_MGMT_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, wmi_thermal_mgmt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index afbe126ea6b1..925d5b6761b8 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2712,6 +2712,11 @@ typedef enum {
     WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI),
     WMI_LPI_STATUS_EVENTID,
     WMI_LPI_HANDOFF_EVENTID,
+    /*
+     * New EVTID added for FW->LOWI intra-LPASS direct scan result delivery -
+     * replaces QMI path when LOWI-on-FW capability is enabled.
+     */
+    WMI_LPI_SCAN_RESULT_EVENTID_V2,
 
     /* ExtScan events */
     WMI_EXTSCAN_START_STOP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_EXTSCAN),
@@ -30563,6 +30568,11 @@ typedef struct {
     A_UINT32 ie_len;
     /** Scan control flags extended (see WMI_SCAN_FLAG_EXT_xxx) */
     A_UINT32 scan_ctrl_flags_ext;
+    /**
+     * dwell time in msec on active 5 GHz channels.
+     *  If 0, dwell_time_active is used for 5 GHz channels as well.
+     */
+    A_UINT32 dwell_time_active_5ghz;
 
 /**
  * TLV (tag length value) parameters follow the scan_cmd
@@ -30574,6 +30584,388 @@ typedef struct {
  */
 } wmi_lpi_start_scan_cmd_fixed_param;
 
+
+/* WMI_LPI_SCAN_RESULT_EVENTID_V2
+ * TLV (tag length value) parameters follow the fixed_param structure:
+ *   wmi_lpi_scan_result_ind_fixed_param fixed_param;
+ *   uint32_t scanned_freq_list[];
+ *   wmi_lpi_ap_info_t ap_array[];
+ */
+
+/**
+ * Maximum number of AP entries accumulated in LOWI per scan
+ * (across all batched events).
+ * FW sends ~7 APs per WMI_LPI_RESULT_EVENTID event
+ * (limited by LPI_RESULT_EVENT_SIZE=1200 bytes);
+ * LOWI accumulates batches until scan_is_completed is set.
+ */
+#define WMI_LPI_MAX_AP_NUM   35
+/** Number of radio chains reported per AP in rssi_chain[] */
+#define WMI_LPI_MAX_RADIO_CHAIN  5
+/** Number of A_UINT32 words used to pack the 12-byte MSAP field */
+#define WMI_LPI_MAX_MSAP_LEN_W   3
+
+/**
+ * wmi_lpi_ap_info_t - Per-AP scan record; element type for TLV #3
+ * (WMITLV_TAG_ARRAY_STRUC).
+ * Since this is a TLV struct (starts with tlv_header), new fields can be
+ * appended at the end in future versions without breaking older receivers.
+ *
+ * ap_info field layout:
+ *   bits [3:0]   = ap_flags: cur_connected[0], wifi_802_11_mc[1],
+ *                            msap_supported[2], is_active[3]
+ *   bits [16:4]  = valid_mask (13 bits);
+ *                  indicates which optional fields are present
+ *   bits [23:17] = reserved (must be set to 0 by sender; ignored by receiver)
+ *   bits [31:24] = phy_mode (8 bits); contains a WLAN_PHY_MODE value
+ *                  (refer enum WLAN_PHY_MODE defined in wlan_defs.h)
+ *
+ * scan_info field layout:
+ *   bits [7:0]   = scan_module_id;
+ *                  identifies which scan module produced this record:
+ *                  0 = WLS_SCAN_MODID_ANY (any/default)
+ *                  1 = WLS_SCAN_MODID_MGMT_RX_HDR_EXTSCAN (extscan module)
+ *                  2 = WLS_SCAN_MODID_MGMT_RX_HDR_ENLO (ENLO module)
+ *   bits [15:8]  = scan_id
+ *   bits [23:16] = flags
+ *   bits [31:24] = scan_cache
+ *
+ * ESS_and_SEC_info field layout:
+ *   bits [15:0]  = ess
+ *   bits [23:16] = sec_mode;
+ *                  bitmask of security modes (WLS_AP_SECUTIRY_MODE_* values):
+ *                  0x00=UNKNOWN
+ *                  0x01=OPEN
+ *                  0x02=WEP
+ *                  0x04=PSK(WPA/WPA2)
+ *                  0x08=EAP(Enterprise)
+ *                  0x10=WPA3_SAE
+ *                  0x20=WPA3_SuiteB
+ *                  0x40=WPA3_OWE
+ *   bits [31:24] = reserved
+ *
+ * MCS_and_NSS_info field layout:
+ *   bits [7:0]   = tx_nss
+ *   bits [15:8]  = tx_mcs
+ *   bits [23:16] = rx_nss
+ *   bits [31:24] = rx_mcs
+ */
+
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_ap_info_t */
+    A_UINT32 tlv_header;
+    /** 6-byte BSSID; uses existing wmi_mac_addr type */
+    wmi_mac_addr bssid;
+    /** ssid:
+     * length + up to 32 bytes packed as 8 x A_UINT32;
+     * uses existing wmi_ssid type
+     */
+    wmi_ssid ssid;
+    /** Primary channel frequency in MHz */
+    A_UINT32 frequency;
+    /** RSSI in dBm */
+    A_INT32 rssi;
+    /** Packed:
+     * ap_flags[3:0]    |
+     * valid_mask[16:4] |
+     * phy_mode[31:24] (WLAN_PHY_MODE value);
+     *  use WMI_LPI_AP_INFO_* macros
+     */
+    A_UINT32 ap_info;
+    /** Actual dwell time on this channel in milliseconds */
+    A_UINT32 dwell_time_ms;
+    /** TSF offset: local TSF minus AP TSF */
+    A_UINT32 tsf_offset;
+    /** Packed:
+     * scan_module_id[7:0] |
+     * scan_id[15:8]       |
+     * flags[23:16]        |
+     * scan_cache[31:24]; use WMI_LPI_SCAN_INFO_* macros
+     */
+    A_UINT32 scan_info;
+    /** Packed:
+     * ess[15:0] |
+     * sec_mode[23:16]; use WMI_LPI_ESS_SEC_* macros
+     */
+    A_UINT32 ESS_and_SEC_info;
+    /** Packed:
+     * tx_nss[7:0]   |
+     * tx_mcs[15:8]  |
+     * rx_nss[23:16] |
+     * rx_mcs[31:24]; use WMI_LPI_MCS_NSS_* macros
+     */
+    A_UINT32 MCS_and_NSS_info;
+    /** Bitmask of active radio chains used to discover this AP */
+    A_UINT32 radio_chain_mask;
+    /** RSSI per radio chain in dBm; 0 if chain not active */
+    A_INT32 rssi_chain[WMI_LPI_MAX_RADIO_CHAIN];
+    /** TX power in dBm; valid when WMI_LPI_VALID_TX_POWER set in valid_mask */
+    A_UINT32 tx_power;
+    /** TX rate in Mbps; valid when WMI_LPI_VALID_TX_RATE set in valid_mask */
+    A_UINT32 tx_rate;
+    /**
+     * TSF timestamp bits [31:0];
+     * valid when WMI_LPI_VALID_TSF set in valid_mask
+     */
+    A_UINT32 tsf_lo;
+    /**
+     * TSF timestamp bits [63:32];
+     * valid when WMI_LPI_VALID_TSF set in valid_mask
+     */
+    A_UINT32 tsf_hi;
+    /** Age of measurement in milliseconds; valid when WMI_LPI_VALID_AGE set in valid_mask */
+    A_UINT32 age;
+    /**
+     * MSAP data: 12 bytes packed as 3 x A_UINT32;
+     * valid when WMI_LPI_VALID_MSAP set in valid_mask
+     */
+    A_UINT32 msap[WMI_LPI_MAX_MSAP_LEN_W];
+    /**
+     * Band center frequency 1 in MHz;
+     * valid when WMI_LPI_VALID_CNT_FREQ1 set in valid_mask
+     */
+    A_UINT32 band_center_freq_1;
+    /**
+     * Band center frequency 2 in MHz;
+     * valid when WMI_LPI_VALID_CNT_FREQ2 set in valid_mask
+     */
+    A_UINT32 band_center_freq_2;
+    /** Venue info per IEEE 802.11u Table 9-62:
+     *  bits[7:0]  = venue_type (e.g. 0=unspecified, 1=assembly, 2=business,
+     *               3=educational, 4=factory, 5=institutional, 6=mercantile,
+     *               7=residential, 8=storage, 9=utility, 10=vehicular,
+     *               11=outdoor)
+     *  bits[15:8] = venue_info
+     *               (venue group/subtype per IEEE 802.11u Table 9-62)
+     *  valid when WMI_LPI_VALID_VENUE set in valid_mask */
+    A_UINT32 venue_type_and_info;
+} wmi_lpi_ap_info_t;
+
+
+/**
+ * wmi_lpi_scan_result_ind_fixed_param -
+ * Fixed params for TLV #1 of WMI_LPI_SCAN_RESULT_EVENTID_V2.
+ * Tag: WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param.
+ * TLV #2 (freq_list) and TLV #3 (ap_array) follow this struct
+ * in the event buffer.
+ * Scan completion is signalled by WMI_LPI_STATUS_EVENTID (unchanged);
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param */
+    A_UINT32 tlv_header;
+    /**
+     * Request ID echoed from the triggering scan request.
+     * For snoop scans, WLS substitutes the snoop subscriber's req_id.
+     */
+    A_UINT32 req_id;
+    /**
+     * Country code from scanned_freq_list: 4 ASCII bytes packed little-endian
+     */
+    A_UINT32 country_code;
+    /** Scan type performed: 0=passive, 1=active, 2=active+passive DFS */
+    A_UINT32 scan_type_performed;
+    /**
+     * Radio chain preference used for this scan:
+     *  0=default, 1=low-latency, 2=low-power, 3=hi-accuracy
+     */
+    A_UINT32 radio_chain_pref;
+/**
+ * TLV (tag length value) parameters follow the fixed_param structure:
+ *   A_UINT32 freq_list[];  // scanned frequencies in MHz; one per word
+ *   wmi_lpi_ap_info_t ap_array[];   // per-AP scan records;
+ *                                   // max WMI_LPI_MAX_AP_NUM entries
+ */
+} wmi_lpi_scan_result_ind_fixed_param;
+
+/* ---- ap_info field bit positions ---- */
+#define WMI_LPI_AP_INFO_CUR_CONNECTED_S    0
+#define WMI_LPI_AP_INFO_WIFI_MC_S          1
+#define WMI_LPI_AP_INFO_MSAP_SUPPORTED_S   2
+#define WMI_LPI_AP_INFO_IS_ACTIVE_S        3
+/* 13-bit valid_mask starts at bit 4 */
+#define WMI_LPI_AP_INFO_VALID_MASK_S       4
+/* 7-bit reserved field at bits [23:17] */
+#define WMI_LPI_AP_INFO_RESERVED_S         17
+/* 8-bit phy_mode at bits [31:24] */
+#define WMI_LPI_AP_INFO_PHY_MODE_S         24
+
+/* ap_info: cur_connected (bit 0) */
+#define WMI_LPI_AP_INFO_SET_CUR_CONNECTED(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0x1) << WMI_LPI_AP_INFO_CUR_CONNECTED_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_CUR_CONNECTED(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_CUR_CONNECTED_S) & 0x1)
+
+/* ap_info: wifi_802_11_mc (bit 1) */
+#define WMI_LPI_AP_INFO_SET_WIFI_MC(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0x1) << WMI_LPI_AP_INFO_WIFI_MC_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_WIFI_MC(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_WIFI_MC_S) & 0x1)
+
+/* ap_info: msap_supported (bit 2) */
+#define WMI_LPI_AP_INFO_SET_MSAP_SUPPORTED(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0x1) << WMI_LPI_AP_INFO_MSAP_SUPPORTED_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_MSAP_SUPPORTED(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_MSAP_SUPPORTED_S) & 0x1)
+
+/* ap_info: is_active (bit 3) */
+#define WMI_LPI_AP_INFO_SET_IS_ACTIVE(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0x1) << WMI_LPI_AP_INFO_IS_ACTIVE_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_IS_ACTIVE(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_IS_ACTIVE_S) & 0x1)
+
+/* ap_info: valid_mask (bits [16:4], 13 bits) */
+#define WMI_LPI_AP_INFO_SET_VALID_MASK(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0x1FFF) << WMI_LPI_AP_INFO_VALID_MASK_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_VALID_MASK(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & 0x1FFF)
+
+/*
+ * ap_info: reserved (bits [23:17], 7 bits)
+ * Sender must write 0.  Receiver must ignore.
+ * Reserved for future per-AP flag extensions.
+ */
+
+/* ap_info: phy_mode (bits [31:24], 8 bits) */
+#define WMI_LPI_AP_INFO_SET_PHY_MODE(pap, val) do { \
+    (pap)->ap_info |=  (((val) & 0xFF) << WMI_LPI_AP_INFO_PHY_MODE_S); \
+    } while (0)
+#define WMI_LPI_AP_INFO_GET_PHY_MODE(pap) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_PHY_MODE_S) & 0xFF)
+
+/* Helper: test a valid_mask bit directly in ap_info (valid_mask is at +4) */
+#define WMI_LPI_AP_INFO_VALID(pap, mask) \
+    (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & (mask))
+
+/* valid_mask bit values (13-bit field in ap_info[16:4]) */
+#define WMI_LPI_VALID_TX_POWER    0x0001 /* tx_power field present */
+#define WMI_LPI_VALID_TX_RATE     0x0002 /* tx_rate field present */
+#define WMI_LPI_VALID_TSF         0x0004 /* tsf_lo/tsf_hi fields present */
+#define WMI_LPI_VALID_AGE         0x0008 /* age field present */
+#define WMI_LPI_VALID_WIFI_MC     0x0010 /* wifi_802_11_mc value in ap_info[1]*/
+#define WMI_LPI_VALID_MSAP        0x0020 /* msap[] field present */
+#define WMI_LPI_VALID_CNT_FREQ1   0x0040 /* band_center_freq_1 present */
+#define WMI_LPI_VALID_CNT_FREQ2   0x0080 /* band_center_freq_2 present */
+#define WMI_LPI_VALID_VENUE       0x0100 /* venue_type_and_info present */
+#define WMI_LPI_VALID_HT_SCO_BIT0 0x0200 /* HT SCO bit 0 */
+#define WMI_LPI_VALID_HT_SCO_BIT1 0x0400 /* HT SCO bit 1 */
+#define WMI_LPI_VALID_LOC_CIVIC   0x0800 /* Location Civic supported */
+#define WMI_LPI_VALID_LCI         0x1000 /* LCI supported */
+
+/* ---- scan_info field bit positions ---- */
+#define WMI_LPI_SCAN_INFO_MODULE_ID_S 0  /* scan_module_id bits [7:0] */
+#define WMI_LPI_SCAN_INFO_SCAN_ID_S   8  /* scan_id        bits [15:8] */
+#define WMI_LPI_SCAN_INFO_FLAGS_S     16 /* flags          bits [23:16] */
+#define WMI_LPI_SCAN_INFO_CACHE_S     24 /* scan_cache     bits [31:24] */
+
+/* scan_info: scan_module_id (bits [7:0]) */
+#define WMI_LPI_SCAN_INFO_SET_MODULE_ID(pap, val) do { \
+    (pap)->scan_info |=  (((val) & 0xFF) << WMI_LPI_SCAN_INFO_MODULE_ID_S); \
+    } while (0)
+#define WMI_LPI_SCAN_INFO_GET_MODULE_ID(pap) \
+    (((pap)->scan_info >> WMI_LPI_SCAN_INFO_MODULE_ID_S) & 0xFF)
+
+/* scan_info: scan_id (bits [15:8]) */
+#define WMI_LPI_SCAN_INFO_SET_SCAN_ID(pap, val) do { \
+    (pap)->scan_info |=  (((val) & 0xFF) << WMI_LPI_SCAN_INFO_SCAN_ID_S); \
+    } while (0)
+#define WMI_LPI_SCAN_INFO_GET_SCAN_ID(pap) \
+    (((pap)->scan_info >> WMI_LPI_SCAN_INFO_SCAN_ID_S) & 0xFF)
+
+/* scan_info: flags (bits [23:16]) */
+#define WMI_LPI_SCAN_INFO_SET_FLAGS(pap, val) do { \
+    (pap)->scan_info |=  (((val) & 0xFF) << WMI_LPI_SCAN_INFO_FLAGS_S); \
+    } while (0)
+#define WMI_LPI_SCAN_INFO_GET_FLAGS(pap) \
+    (((pap)->scan_info >> WMI_LPI_SCAN_INFO_FLAGS_S) & 0xFF)
+
+/* scan_info: scan_cache (bits [31:24]) */
+#define WMI_LPI_SCAN_INFO_SET_CACHE(pap, val) do { \
+    (pap)->scan_info |=  (((val) & 0xFF) << WMI_LPI_SCAN_INFO_CACHE_S); \
+    } while (0)
+#define WMI_LPI_SCAN_INFO_GET_CACHE(pap) \
+    (((pap)->scan_info >> WMI_LPI_SCAN_INFO_CACHE_S) & 0xFF)
+
+/* ---- ESS_and_SEC_info field bit positions ---- */
+#define WMI_LPI_ESS_SEC_ESS_S      0  /* ess      bits [15:0]  */
+#define WMI_LPI_ESS_SEC_SEC_MODE_S 16 /* sec_mode bits [23:16] */
+
+/* ESS_and_SEC_info: ess (bits [15:0]) */
+#define WMI_LPI_ESS_SEC_SET_ESS(pap, val) do { \
+    (pap)->ESS_and_SEC_info |=  (((val) & 0xFFFF) << WMI_LPI_ESS_SEC_ESS_S); \
+    } while (0)
+#define WMI_LPI_ESS_SEC_GET_ESS(pap) \
+    (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_ESS_S) & 0xFFFF)
+
+/* ESS_and_SEC_info: sec_mode (bits [23:16]) */
+#define WMI_LPI_ESS_SEC_SET_SEC_MODE(pap, val) do { \
+    (pap)->ESS_and_SEC_info |=  (((val) & 0xFF) << WMI_LPI_ESS_SEC_SEC_MODE_S); \
+    } while (0)
+#define WMI_LPI_ESS_SEC_GET_SEC_MODE(pap) \
+    (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_SEC_MODE_S) & 0xFF)
+
+/* ---- MCS_and_NSS_info field bit positions ---- */
+#define WMI_LPI_MCS_NSS_TX_NSS_S 0  /* tx_nss bits [7:0] */
+#define WMI_LPI_MCS_NSS_TX_MCS_S 8  /* tx_mcs bits [15:8] */
+#define WMI_LPI_MCS_NSS_RX_NSS_S 16 /* rx_nss bits [23:16] */
+#define WMI_LPI_MCS_NSS_RX_MCS_S 24 /* rx_mcs bits [31:24] */
+
+/* MCS_and_NSS_info: tx_nss (bits [7:0]) */
+#define WMI_LPI_MCS_NSS_SET_TX_NSS(pap, val) do { \
+    (pap)->MCS_and_NSS_info |=  (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_NSS_S); \
+    } while (0)
+#define WMI_LPI_MCS_NSS_GET_TX_NSS(pap) \
+    (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_NSS_S) & 0xFF)
+
+/* MCS_and_NSS_info: tx_mcs (bits [15:8]) */
+#define WMI_LPI_MCS_NSS_SET_TX_MCS(pap, val) do { \
+    (pap)->MCS_and_NSS_info |=  (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_MCS_S); \
+    } while (0)
+#define WMI_LPI_MCS_NSS_GET_TX_MCS(pap) \
+    (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_MCS_S) & 0xFF)
+
+/* MCS_and_NSS_info: rx_nss (bits [23:16]) */
+#define WMI_LPI_MCS_NSS_SET_RX_NSS(pap, val) do { \
+    (pap)->MCS_and_NSS_info |=  (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_NSS_S); \
+    } while (0)
+#define WMI_LPI_MCS_NSS_GET_RX_NSS(pap) \
+    (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_NSS_S) & 0xFF)
+
+/* MCS_and_NSS_info: rx_mcs (bits [31:24]) */
+#define WMI_LPI_MCS_NSS_SET_RX_MCS(pap, val) do { \
+    (pap)->MCS_and_NSS_info |=  (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_MCS_S); \
+    } while (0)
+#define WMI_LPI_MCS_NSS_GET_RX_MCS(pap) \
+    (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_MCS_S) & 0xFF)
+
+
+/* ---- venue_type_and_info field bit positions ---- */
+#define WMI_LPI_VENUE_TYPE_S 0 /* venue_type bits [7:0] */
+#define WMI_LPI_VENUE_INFO_S 8 /* venue_info bits [15:8] */
+
+/* venue_type_and_info: venue_type (bits [7:0]) */
+#define WMI_LPI_VENUE_SET_TYPE(pap, val) do { \
+    (pap)->venue_type_and_info |=  (((val) & 0xFF) << WMI_LPI_VENUE_TYPE_S); \
+    } while (0)
+#define WMI_LPI_VENUE_GET_TYPE(pap) \
+    (((pap)->venue_type_and_info >> WMI_LPI_VENUE_TYPE_S) & 0xFF)
+
+/* venue_type_and_info: venue_info (bits [15:8]) */
+#define WMI_LPI_VENUE_SET_INFO(pap, val) do { \
+    (pap)->venue_type_and_info |=  (((val) & 0xFF) << WMI_LPI_VENUE_INFO_S); \
+    } while (0)
+#define WMI_LPI_VENUE_GET_INFO(pap) \
+    (((pap)->venue_type_and_info >> WMI_LPI_VENUE_INFO_S) & 0xFF)
+
+/* =========================================================================
+ * End of WMI_LPI_SCAN_RESULT_EVENTID_V2 definitions
+ * ====================================================================== */
+
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */
     /** Scan requestor ID */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 14bd31b096bd..d1cf1d6225f9 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1771
+#define __WMI_REVISION_ 1772
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 81b46e263fcd84ec744aba41057a677b8d1d5b49 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 27 May 2026 06:01:59 -0700
Subject: [PATCH 259/290] fw-api: CL 32668717 - update fw common interface
 files

Change-Id: I7232f5b85b3e918dc877e4a96d56d28fa692642c
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 142 +++++++++++++
 fw/wmi_unified.h  | 524 +++++++++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |   2 +-
 3 files changed, 663 insertions(+), 5 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index f027d8ebccae..d9ad9c4d8b16 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1643,6 +1643,11 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_mapc_cortwt_params,
     WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param,
     WMITLV_TAG_STRUC_wmi_lpi_ap_info_t,
+    WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2254,6 +2259,8 @@ typedef enum {
     OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \
     OP(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID) \
     OP(WMI_PEER_SET_MAPC_PARAMS_CMDID) \
+    OP(WMI_NAN_DISC_SERVICE_REQ_CMDID) \
+    OP(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2625,6 +2632,9 @@ typedef enum {
     OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \
     OP(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID) \
     OP(WMI_LPI_SCAN_RESULT_EVENTID_V2) \
+    OP(WMI_NAN_DISC_SERVICE_RSP_EVENTID) \
+    OP(WMI_NAN_DISC_MATCH_EVENTID) \
+    OP(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -4517,6 +4527,92 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_caps_ie_data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CMDID);
 
+/**
+ * NAN Discovery Service Request Command
+ * (NL80211_CMD_ADD_NAN_FUNCTION equivalent)
+ *
+ * Carries all parameters needed to register a NAN Publish, Subscribe, or
+ * Follow-up function with the firmware in offload mode.
+ *
+ * TLV layout (in order):
+ *
+ * [0] wmi_nan_disc_service_req_cmd_fixed_param  fixed_param
+ *     All fixed scalar fields: vdev_id, service_req_type, instance_id, ttl,
+ *     publish_type, followup_instance_id, followup_requestor_id,
+ *     followup_dest, sdea_ctrl, pairing_bootstrap_methods, srf_bf_idx,
+ *     srf_include, service_req_flags, and all _len / _num count fields.
+ *
+ * [1] A_UINT8  service_id[]
+ *     6-byte NAN Service ID (SHA-256 of service name, first 6 bytes),
+ *     zero-padded to 8 bytes for 4-byte WMI alignment.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_ID / cfg80211_nan_func.service_id
+ *
+ * [2] A_UINT8  serv_spec_info[]
+ *     Service Specific Info — opaque application payload, max 255 bytes.
+ *     Valid byte count given by fixed_param.serv_spec_info_len.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_INFO /
+ *     cfg80211_nan_func.serv_spec_info
+ *
+ * [3] A_UINT8  srf_bf[]
+ *     SRF (Service Range Filter) Bloom filter data.
+ *     Valid byte count given by fixed_param.srf_bf_len.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_SRF_BF / cfg80211_nan_func.srf_bf
+ *
+ * [4] wmi_mac_addr  srf_macs[]
+ *     SRF MAC address filter list (WMITLV_TAG_ARRAY_FIXED_STRUC).
+ *     Entry count given by fixed_param.num_srf_macs.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_SRF_MAC_ADDRS /
+ *     cfg80211_nan_func.srf_macs
+ *
+ * [5] A_UINT8  rx_match_filter[]
+ *     RX match filter byte stream (ieee80211 protocol order).
+ *     Valid byte count given by fixed_param.rx_match_filter_len.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_RX_MATCH_FILTER /
+ *     cfg80211_nan_func.rx_filters
+ *
+ * [6] A_UINT8  tx_match_filter[]
+ *     TX match filter byte stream (ieee80211 protocol order).
+ *     Valid byte count given by fixed_param.tx_match_filter_len.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_TX_MATCH_FILTER /
+ *     cfg80211_nan_func.tx_filters
+ *
+ * [7] A_UINT32  cipher_suites[]
+ *     Array of supported NAN cipher suite IDs (CSIDs).
+ *     Entry count given by fixed_param.num_cipher_suites.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_CIPHER_SUITES /
+ *     cfg80211_nan_func.cipher_suites
+ *
+ * [8] A_UINT8  nd_pmk[]
+ *     NAN Data Path PMK, exactly 32 bytes when present.
+ *     Present and valid only when
+ *     WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID(
+ *         fixed_param.service_req_flags) == 1;
+ *     zero-length TLV otherwise.
+ *     Maps to: NL80211_ATTR_NAN_FUNC_ND_PMK / cfg80211_nan_func.nd_pmk
+ */
+#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param, wmi_nan_disc_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      service_id,      WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      serv_spec_info,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      srf_bf,          WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, srf_macs,        WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      rx_match_filter, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      tx_match_filter, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32,      A_UINT32,     cipher_suites,   WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      nd_pmk,          WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,        A_UINT8,      extra_nan_attrs, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_CMDID);
+
+/** NAN Discovery Delete Function Cmd
+ *
+ * TLV (tag length value) parameters follow the
+ * wmi_nan_disc_cancel_service_req_cmd_fixed_param structure. The TLV's are:
+ * wmi_nan_disc_cancel_service_req_cmd_fixed_param fixed_param;
+ */
+#define WMITLV_TABLE_WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param, wmi_nan_disc_cancel_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID);
+
 /* NAN Data Get Capabilities Cmd */
 #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX)
@@ -7462,6 +7558,52 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_JOINED_CLUSTER_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, wmi_nan_enable_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_RSP_EVENTID);
 
+/** NAN Discovery Service Response Event
+ *
+ * TLV (tag length value) parameters follow the
+ * wmi_nan_disc_service_rsp_event_fixed_param structure. The TLV's are:
+ * wmi_nan_disc_service_rsp_event_fixed_param fixed_param;
+ */
+#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_RSP_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param, wmi_nan_disc_service_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_RSP_EVENTID);
+
+/** NAN Discovery Match Event (NL80211_CMD_NAN_MATCH equivalent)
+ *
+ * Unified event covering subscriber match, publisher replied, and follow-up
+ * received scenarios, discriminated by the type field in fixed_param.
+ *
+ * TLV (tag length value) parameters follow the
+ * wmi_nan_disc_match_event_fixed_param structure. The TLV's are:
+ * wmi_mac_addr  peer_addr[];
+ * A_UINT8  service_id[];
+ * A_UINT8  serv_spec_info[];
+ * A_UINT32 cipher_suites[];
+ * A_UINT8  scid[];
+ * A_UINT8  extra_info[];
+ * A_UINT8  ies[];
+ */
+#define WMITLV_TABLE_WMI_NAN_DISC_MATCH_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param, wmi_nan_disc_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_addr, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,   A_UINT8,  service_id,     WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,   A_UINT8,  serv_spec_info, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cipher_suites,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,   A_UINT8,  scid,           WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,   A_UINT8,  extra_info,     WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE,   A_UINT8,  ies,            WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_MATCH_EVENTID);
+
+/** NAN Discovery Service Request Terminated Event
+ *
+ * TLV (tag length value) parameters follow the
+ * wmi_nan_disc_service_req_terminated_event_fixed_param structure. The TLV's are:
+ * wmi_nan_disc_service_req_terminated_event_fixed_param fixed_param;
+ */
+#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param, wmi_nan_disc_service_req_terminated_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID);
+
 /* NAN Next DW Info Event */
 #define WMITLV_TABLE_WMI_NAN_NEXT_DW_INFO_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, wmi_nan_next_dw_info_fixed_param, fixed_param, WMITLV_SIZE_FIX)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 925d5b6761b8..e53617e96af6 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1579,7 +1579,26 @@ typedef enum {
      * negotiation etc.).
      */
     WMI_NAN_PEER_PARAMS_CMDID,
-
+    /**
+     * Command to request for NAN service discovery operations i.e.
+     * Publish, Subscribe, Followup to be handled by FW.
+     * This command carries the full NAN function parameters equivalent
+     * to NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func, including
+     * service ID, SRF filters, match filters, SDEA control, security
+     * (cipher suites, ND-PMK), and NAN3 pairing configuration.
+     */
+    WMI_NAN_DISC_SERVICE_REQ_CMDID,
+    /**
+     * Command to cancel an active NAN discovery service request
+     * (Publish or Subscribe).
+     * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION in the cfg80211
+     * offload interface.
+     * Host identifies the service request by instance_id (offload path)
+     * or cookie (standard path); FW frees the service request and sends
+     * WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID if the service request
+     * was active.
+     */
+    WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID,
 
     /** Modem power state command */
     WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX),
@@ -2699,6 +2718,29 @@ typedef enum {
     WMI_NDP_CHANNEL_INFO_EVENTID,
     /* Event to indicate availability of STA AP connection on DFS channel */
     WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID,
+    /**
+     * Event response to NAN discovery service request command
+     * (WMI_NAN_DISC_SERVICE_REQ_CMDID);
+     * carries the instance_id assigned by FW and a status code indicating
+     * whether the Publish / Subscribe service request was accepted
+     */
+    WMI_NAN_DISC_SERVICE_RSP_EVENTID,
+    /**
+     * NAN discovery match event; covers two match scenarios:
+     * subscriber found publisher (type=PUBLISH), publisher received subscribe
+     * (type=SUBSCRIBE).
+     * Equivalent of NL80211_CMD_NAN_MATCH in the cfg80211
+     * offload interface.
+     */
+    WMI_NAN_DISC_MATCH_EVENTID,
+    /**
+     * NAN discovery service request terminated event; sent when a Publish or
+     * Subscribe service request is cancelled by the host, expires (TTL), or is
+     * terminated by FW due to an error.
+     * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated)
+     * in the cfg80211 offload interface.
+     */
+    WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID,
 
     /* Coex Event */
     WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
@@ -5624,7 +5666,9 @@ typedef struct {
         struct {
             A_UINT32
                 dw_notif_lead_time: 8,
-                reserved2: 24;
+                /* enable supplicant based NAN offload mode */
+                enable_nan_ofld_mode: 1,
+                reserved2: 23;
         };
     };
 } wmi_resource_config;
@@ -5635,9 +5679,34 @@ typedef struct {
     WMI_SET_BITS(word32, 0, 1, value)
 
 #define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_GET(word32) \
-        WMI_GET_BITS(word32, 0, 8)
+    WMI_GET_BITS(word32, 0, 8)
 #define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_SET(word32, value) \
-        WMI_SET_BITS(word32, 0, 8, value)
+    WMI_SET_BITS(word32, 0, 8, value)
+
+#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_GET(word32) \
+    WMI_GET_BITS(word32, 8, 1)
+#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_SET(word32, value) \
+    WMI_SET_BITS(word32, 8, 1, value)
+
+/*
+ * WMI_NAN_DISC_COOKIE_GET / WMI_NAN_DISC_COOKIE_SET
+ *
+ * Accessor macros for the 64-bit cookie value split across
+ * cookie_low32 and cookie_high32 fields in WMI NAN disc structs.
+ *
+ * Usage (read):
+ *   A_UINT64 c = WMI_NAN_DISC_COOKIE_GET(p->cookie_low32, p->cookie_high32);
+ *
+ * Usage (write):
+ *   WMI_NAN_DISC_COOKIE_SET(p->cookie_low32, p->cookie_high32, my_cookie);
+ */
+#define WMI_NAN_DISC_COOKIE_GET(low32, high32) \
+    (((A_UINT64)(high32) << 32) | (A_UINT64)(low32))
+#define WMI_NAN_DISC_COOKIE_SET(low32, high32, cookie64) \
+    do { \
+        (low32)  = (A_UINT32)((cookie64) & 0xFFFFFFFFUL); \
+        (high32) = (A_UINT32)(((cookie64) >> 32) & 0xFFFFFFFFUL); \
+    } while (0)
 
 #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
     (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1))))
@@ -32542,6 +32611,244 @@ typedef struct {
  */
 } wmi_nan_peer_params_cmd_fixed_param;
 
+/*
+ * NAN service request type values for
+ * wmi_nan_disc_service_req_cmd_fixed_param.service_req_type.
+ * Maps to NL80211_NAN_FUNC_PUBLISH / SUBSCRIBE / FOLLOW_UP.
+ */
+typedef enum {
+    WMI_NAN_DISC_SERVICE_REQ_PUBLISH    = 1,
+    WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE  = 2,
+    WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP  = 3,
+} WMI_NAN_DISC_SERVICE_REQ_TYPE;
+
+/*
+ * Publish type values for
+ * wmi_nan_disc_service_req_cmd_fixed_param.publish_type.
+ * Valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH.
+ * Maps to NL80211_NAN_FUNC_PUBLISH_TYPE.
+ */
+typedef enum {
+    WMI_NAN_DISC_PUBLISH_UNSOLICITED           = 0,
+    WMI_NAN_DISC_PUBLISH_SOLICITED             = 1,
+    WMI_NAN_DISC_PUBLISH_UNSOLICITED_SOLICITED = 2,
+} WMI_NAN_DISC_PUBLISH_TYPE;
+
+/*
+ * NAN discovery service request termination reason values for
+ * wmi_nan_disc_service_req_terminated_event_fixed_param.reason.
+ * Maps to nl80211_nan_func_term_reason.
+ */
+typedef enum {
+    /**
+     * Service request was cancelled by an explicit host request
+     * (WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID).
+     * Maps to NL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0
+     */
+    WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST = 0,
+    /**
+     * Service request lifetime (TTL) elapsed;
+     * FW auto-expired the service request.
+     * Maps to NL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1
+     */
+    WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED = 1,
+    /**
+     * FW encountered an internal error and could not maintain
+     * the service request.
+     * Also covers NAN_TERMINATED_REASON_COUNT_REACHED from the HAL path.
+     * Maps to NL80211_NAN_FUNC_TERM_REASON_ERROR = 2
+     */
+    WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR = 2,
+} WMI_NAN_DISC_SERVICE_REQ_TERM_REASON;
+
+/*
+ * SDEA (Service Descriptor Extension Attribute) control field bit accessors.
+ * Maps to NL80211_ATTR_NAN_FUNC_SDEA_CTRL / cfg80211_nan_func.sdea_ctrl.
+ *   Bit 2 : Data Path Required
+ *   Bit 6 : Security Required
+ */
+#define WMI_NAN_DISC_SDEA_CTRL_GET_DATA_PATH_REQ(sdea) \
+    WMI_GET_BITS(sdea, 2, 1)
+#define WMI_NAN_DISC_SDEA_CTRL_SET_DATA_PATH_REQ(sdea, v) \
+    WMI_SET_BITS(sdea, 2, 1, v)
+#define WMI_NAN_DISC_SDEA_CTRL_GET_SECURITY_REQ(sdea) \
+    WMI_GET_BITS(sdea, 6, 1)
+#define WMI_NAN_DISC_SDEA_CTRL_SET_SECURITY_REQ(sdea, v) \
+    WMI_SET_BITS(sdea, 6, 1, v)
+
+/*
+ * service_req_flags field bit accessors for
+ * wmi_nan_disc_service_req_cmd_fixed_param.service_req_flags.
+ * Packs all boolean cfg80211_nan_func fields into one A_UINT32.
+ *
+ *   Bit 0 : close_range      — match only with close-range peers
+ *                              (NL80211_ATTR_NAN_FUNC_CLOSE_RANGE)
+ *   Bit 1 : publish_bcast    — send in broadcast discovery beacons;
+ *                              valid only for Publish
+ *                              (NL80211_ATTR_NAN_FUNC_PUBLISH_BCAST)
+ *   Bit 2 : subscribe_active — send active subscribe queries;
+ *                              valid only for Subscribe
+ *                              (NL80211_ATTR_NAN_FUNC_SUBSCRIBE_ACTIVE)
+ *   Bit 3 : gtk_required     — group temporal key required for
+ *                              multicast data
+ *                              (NL80211_ATTR_NAN_FUNC_GTK_REQUIRED)
+ *   Bit 4 : pairing_setup    — enable initial NAN3 pairing setup
+ *                              (NL80211_ATTR_NAN_FUNC_PAIRING_SETUP)
+ *   Bit 5 : pairing_cache    — enable persistent NAN3 pairing cache
+ *                              (NL80211_ATTR_NAN_FUNC_PAIRING_CACHE)
+ *   Bit 6 : pairing_verify   — enable NAN3 pairing re-verification
+ *                              (NL80211_ATTR_NAN_FUNC_PAIRING_VERIFY)
+ *   Bit 7 : nd_pmk_valid     — nd_pmk TLV is populated and valid
+ *                              (NL80211_ATTR_NAN_FUNC_ND_PMK)
+ *   Bits 8-31 : reserved, must be set to 0
+ */
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_CLOSE_RANGE(f) \
+    WMI_GET_BITS(f, 0, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_CLOSE_RANGE(f, v) \
+    WMI_SET_BITS(f, 0, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PUBLISH_BCAST(f) \
+    WMI_GET_BITS(f, 1, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PUBLISH_BCAST(f, v) \
+    WMI_SET_BITS(f, 1, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_SUBSCRIBE_ACTIVE(f) \
+    WMI_GET_BITS(f, 2, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_SUBSCRIBE_ACTIVE(f, v) \
+    WMI_SET_BITS(f, 2, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_GTK_REQUIRED(f) \
+    WMI_GET_BITS(f, 3, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_GTK_REQUIRED(f, v) \
+    WMI_SET_BITS(f, 3, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_SETUP(f) \
+    WMI_GET_BITS(f, 4, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_SETUP(f, v) \
+    WMI_SET_BITS(f, 4, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_CACHE(f) \
+    WMI_GET_BITS(f, 5, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_CACHE(f, v) \
+    WMI_SET_BITS(f, 5, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_VERIFY(f) \
+    WMI_GET_BITS(f, 6, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_VERIFY(f, v) \
+    WMI_SET_BITS(f, 6, 1, v)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID(f) \
+    WMI_GET_BITS(f, 7, 1)
+#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_ND_PMK_VALID(f, v) \
+    WMI_SET_BITS(f, 7, 1, v)
+
+/**
+ * WMI command to add a NAN discovery function
+ * (Publish / Subscribe / Follow-up).
+ * WMI equivalent of NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func.
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique id identifying the NMI VDEV */
+    A_UINT32 vdev_id;
+    /**
+     * NAN service request type:
+     * 1=Publish, 2=Subscribe, 3=Follow-up;
+     * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE
+     */
+    A_UINT32 service_req_type;
+    /**
+     * Unique cookie assigned by cfg80211 for this function.
+     *  Split into two A_UINT32 words for endian portability.
+     *  Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64.
+     */
+    A_UINT32 cookie_low32;  /* lower 32 bits of 64-bit cookie value */
+    A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */
+    /**
+     * Function lifetime in Discovery Windows;
+     * 0 = active until explicitly deleted
+     */
+    A_UINT32 ttl;
+    /**
+     * Publish transmission mode;
+     * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH;
+     * refer to WMI_NAN_DISC_PUBLISH_TYPE
+     */
+    A_UINT32 publish_type;
+    /**
+     * Local function instance ID to which this follow-up is associated;
+     * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP
+     */
+    A_UINT32 followup_instance_id;
+    /**
+     * Requestor instance ID from the prior match event;
+     * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP
+     */
+    A_UINT32 followup_requestor_id;
+    /**
+     * NMI MAC address of the peer to send the follow-up to;
+     * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP
+     */
+    wmi_mac_addr followup_dest;
+    /**
+     * SDEA control field bitmap; use WMI_NAN_DISC_SDEA_CTRL_GET/SET macros;
+     * bit2=Data Path Required, bit6=Security Required
+     */
+    A_UINT32 sdea_ctrl;
+    /**
+     * Bitmap of supported NAN3 pairing bootstrap methods;
+     * bit0=Opportunistic, bit1=PIN
+     */
+    A_UINT32 pairing_bootstrap_methods;
+    /**
+     * Bloom filter index for the SRF;
+     * valid only when TLV srf_bf[] is non-empty
+     */
+    A_UINT32 srf_bf_idx;
+    /**
+     * SRF filter mode:
+     * 0=exclude listed entries, 1=include only listed entries
+     */
+    A_UINT32 srf_include;
+    /**
+     * Packed boolean flags; use WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET/SET macros;
+     *  bit0=close_range, bit1=publish_bcast, bit2=subscribe_active,
+     *  bit3=gtk_required, bit4=pairing_setup, bit5=pairing_cache,
+     *  bit6=pairing_verify, bit7=nd_pmk_valid, bits8-31=reserved
+     */
+    A_UINT32 service_req_flags;
+    /** Actual number of bytes in TLV serv_spec_info[]; max 255 */
+    A_UINT32 serv_spec_info_len;
+    /** Actual number of bytes in TLV srf_bf[] */
+    A_UINT32 srf_bf_len;
+    /** Actual number of bytes in TLV rx_match_filter[] */
+    A_UINT32 rx_match_filter_len;
+    /** Actual number of bytes in TLV tx_match_filter[] */
+    A_UINT32 tx_match_filter_len;
+    /** extra_nan_attrs_len:
+     * number of valid bytes (i.e. excluding final alignment-padding)
+     * in the TLV extra_nan_attrs[]
+     */
+    A_UINT32 extra_nan_attrs_len;
+    /**
+     * TLV (tag length value) parameters follow this structure:
+     * A_UINT8  service_id[];        6-byte NAN Service ID,
+     *                               zero-padded to 8 bytes
+     * A_UINT8  serv_spec_info[];    Service Specific Info, max 255 bytes
+     * A_UINT8  srf_bf[];            SRF Bloom filter data
+     * wmi_mac_addr srf_macs[];      SRF MAC address filter list
+     * A_UINT8  rx_match_filter[];   RX match filter byte stream
+     * A_UINT8  tx_match_filter[];   TX match filter byte stream
+     * A_UINT32 cipher_suites[];     NAN cipher suite ID array
+     * A_UINT8  nd_pmk[];            NAN Data Path PMK, 32 bytes;
+     *                               present only when bit7 of
+     *                               service_req_flags is set
+     * A_UINT8  extra_nan_attrs[];   extra NAN attrs like Device Cap,
+     *                               Shared Key Desc, CSIA cap etc.
+     *                               are sent in stream of bytes
+     *                               (ieee80211 protocol order).
+     *                               The host must manually byteswap
+     *                               these bytes within each 4-byte word
+     *                               if the host's endianness doesn’t
+     *                               match the target’s, to ensure the
+     *                               expected byte order is maintained.
+     */
+} wmi_nan_disc_service_req_cmd_fixed_param;
+
 typedef enum {
     WMI_NAN_STATUS_NO_NAN_AVAIL_DFS_CHANNEL_DETECTED  = 0x1,
     WMI_NAN_STATUS_NO_DFS_BEACONS_RECEIVED            = 0x2,
@@ -32676,6 +32983,213 @@ typedef struct {
     A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel */
 } wmi_nan_enable_rsp_event_fixed_param;
 
+/**
+ * WMI event response to WMI_NAN_DISC_SERVICE_REQ_CMDID.
+ * Sent by FW for each Publish / Subscribe / Follow-up function registration.
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique id identifying the NMI VDEV */
+    A_UINT32 vdev_id;
+    /**
+     * Opaque cookie assigned by the driver; monotonically increasing per rdev.
+     *  Host must store this and include it in every subsequent match event
+     *  correlation. Equivalent of NL80211_ATTR_COOKIE in the CFG response.
+     *  Split into two A_UINT32 words for endian portability.
+     *  Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64.
+     */
+    A_UINT32 cookie_low32;  /* lower 32 bits of 64-bit cookie value */
+    A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */
+    /**
+     * FW/device-assigned service instance ID (1-255).
+     *  Used in SDF frames and match events.
+     *  Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the CFG response.
+     */
+    A_UINT32 instance_id;
+    /**
+     * NAN service request type of the registered service request;
+     * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE:
+     *  1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH
+     *  2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE
+     *  3 = WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP
+     */
+    A_UINT32 service_req_type;
+    /** Status code returned by FW: 0 = success, non-zero = failure */
+    A_UINT32 status;
+} wmi_nan_disc_service_rsp_event_fixed_param;
+
+/**
+ * WMI command to cancel an active NAN discovery service request.
+ * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION / cfg80211 offload interface.
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique id identifying the NMI VDEV */
+    A_UINT32 vdev_id;
+    /**
+     * NAN service request type being cancelled;
+     * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE:
+     *  1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH
+     *  2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE
+     */
+    A_UINT32 service_req_type;
+    /**
+     * Instance ID of the service request to cancel (offload path); range 1-255.
+     * FW resolves instance_id to the internal service request object.
+     * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in
+     * NL80211_CMD_DEL_NAN_FUNCTION
+     */
+    A_UINT32 instance_id;
+   /**
+     * Opaque cookie of the service request to cancel (standard path).
+     * Used when instance_id is not available;
+     * FW resolves cookie to service request.
+     * Equivalent of NL80211_ATTR_COOKIE in NL80211_CMD_DEL_NAN_FUNCTION.
+     * Set to 0 when instance_id is used instead.
+     * Split into two A_UINT32 words for endian portability.
+     * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64.
+     */
+    A_UINT32 cookie_low32;  /* lower 32 bits of 64-bit cookie value */
+    A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */
+} wmi_nan_disc_cancel_service_req_cmd_fixed_param;
+
+/**
+ * WMI event indicating a NAN discovery service request has been terminated.
+ * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated).
+ * Sent by FW when a Publish or Subscribe service request is cancelled by the
+ * host, expires due to TTL, or is terminated by FW due to an error.
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique id identifying the NMI VDEV */
+    A_UINT32 vdev_id;
+    /**
+     * Opaque cookie of the terminated service request; assigned by FW in
+     * WMI_NAN_DISC_SERVICE_RSP_EVENTID.
+     * Equivalent of NL80211_ATTR_COOKIE in the terminated event.
+     * Split into two A_UINT32 words for endian portability.
+     * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64.
+     */
+    A_UINT32 cookie_low32;  /* lower 32 bits of 64-bit cookie value */
+    A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */
+    /**
+     * Instance ID of the terminated service request (1-255).
+     *  Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the terminated event
+     */
+    A_UINT32 instance_id;
+    /**
+     * NAN service request type that was terminated;
+     * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE:
+     *  1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH
+     *  2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE
+     */
+    A_UINT32 service_req_type;
+    /**
+     * Termination reason; refer to WMI_NAN_DISC_SERVICE_REQ_TERM_REASON enum:
+     * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST (0) —
+     *     cancelled by host
+     * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED  (1) —
+     *     TTL elapsed
+     * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR        (2) —
+     *     FW internal error
+     */
+    A_UINT32 reason;
+} wmi_nan_disc_service_req_terminated_event_fixed_param;
+
+/**
+* WMI NAN discovery match event (NL80211_CMD_NAN_MATCH equivalent).
+ * Covers two match scenarios, discriminated by the type field:
+ * type = WMI_NAN_DISC_SERVICE_REQ_PUBLISH   —
+ *     subscriber found a matching publisher
+ * type = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE —
+ *     publisher received a subscribe frame
+ */
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param */
+    A_UINT32 tlv_header;
+    /** Unique id identifying the NMI VDEV */
+    A_UINT32 vdev_id;
+    /**
+     * Cookie assigned by the driver in the
+     * WMI_NAN_DISC_SERVICE_RSP_EVENTID response;
+     * host uses this to correlate the match to the originating function.
+     * Split into two A_UINT32 words for endian portability.
+     * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64.
+     */
+    A_UINT32 cookie_low32;  /* lower 32 bits of 64-bit cookie value */
+    A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */
+    /** Local function instance ID that triggered the match */
+    A_UINT32 inst_id;
+    /** Peer's function instance ID */
+    A_UINT32 peer_inst_id;
+    /**
+     * NAN service request type discriminating the match scenario;
+     * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE:
+     *  1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH   (subscriber matched a publisher)
+     *  2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE (publisher received a subscribe)
+     */
+    A_UINT32 type;
+    /**
+     * SDEA control field from peer; use WMI_NAN_DISC_SDEA_CTRL_GET macros;
+     *  bit2=Data Path Required, bit6=Security Required
+     */
+    A_UINT32 sdea_ctrl;
+    /** Peer's pairing bootstrap methods bitmap */
+    A_UINT32 bootstrap_methods;
+    /** 1 = peer requires NDP (derived from SDEA bit 2); 0 = no NDP required */
+    A_UINT32 data_path;
+    /**
+     * 1 = GTK protection required (derived from SDEA bit 10);
+     * 0 = not required
+     */
+    A_UINT32 gtk_required;
+    /** 1 = peer supports pairing setup; 0 = not supported */
+    A_UINT32 pairing_setup;
+    /** 1 = peer supports pairing cache; 0 = not supported */
+    A_UINT32 pairing_cache;
+    /** 1 = peer supports pairing verify; 0 = not supported */
+    A_UINT32 pairing_verify;
+    /**
+     * Received signal strength indicator (RSSI) in dBm;
+     * valid only when rssi_valid == 1
+     */
+    A_INT32  rssi;
+    /** 1 = rssi field is valid; 0 = rssi not populated */
+    A_UINT32 rssi_valid;
+    /** Actual number of bytes in TLV peer_addr[] (always 6) */
+    A_UINT32 peer_addr_len;
+    /** Actual number of bytes in TLV service_id[] (always 6) */
+    A_UINT32 service_id_len;
+    /** Actual number of bytes in TLV serv_spec_info[] */
+    A_UINT32 serv_spec_info_len;
+    /** Actual number of bytes in TLV scid[] */
+    A_UINT32 scid_len;
+    /**
+     * Actual number of bytes in TLV extra_info[];
+     * relevant when peer includes Extended SSI attribute
+     */
+    A_UINT32 extra_info_len;
+    /**
+     * Actual number of bytes in TLV ies[];
+     * raw IE blob parsed by supplicant: NPBA→bootstrap handler,
+     * Shared Key Descriptor→NIK exchange
+     */
+    A_UINT32 ies_len;
+    /**
+     * TLV (tag length value) parameters follow this structure:
+     * wmi_mac_addr  peer_addr[];  peer NMI address, 6 bytes (padded to 8)
+     * A_UINT8  service_id[];      local service ID, 6 bytes
+     * A_UINT8  serv_spec_info[];  service specific info from peer
+     * A_UINT32 cipher_suites[];   peer's NAN cipher suite ID array
+     * A_UINT8  scid[];            secure context ID; present when security_required == 1
+     * A_UINT8  extra_info[];      extended SSI; present when extra_info_len > 0
+     * A_UINT8  ies[];             raw IEs blob; present when ies_len > 0
+     */
+} wmi_nan_disc_match_event_fixed_param;
+
 typedef struct {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param */
     A_UINT32 tlv_header;
@@ -43401,6 +43915,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID);
         WMI_RETURN_STRING(WMI_GET_CHIPSET_LOGGING_STATS_CMDID);
         WMI_RETURN_STRING(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_DISC_SERVICE_REQ_CMDID);
+        WMI_RETURN_STRING(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d1cf1d6225f9..f1277d305b45 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1772
+#define __WMI_REVISION_ 1773
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From c8014b61bb9d26760685559a019e7ed2bc8a5198 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 28 May 2026 18:01:51 -0700
Subject: [PATCH 260/290] fw-api: CL 32688516 - update fw common interface
 files

Change-Id: I99daa05867576fda27e773d45d68fc09fd7604a4
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 18 ++++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e53617e96af6..cdc70a2fdc0e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10909,6 +10909,22 @@ typedef enum {
 #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_GET(value) WMI_GET_BITS(value, 16, 16)
 #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_SET(_value, value) WMI_SET_BITS(_value, 16, 16, value)
 
+/* WMI GET/SET macros for WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS */
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_GET(param) \
+    WMI_GET_BITS(param, 0, 10)
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_SET(_param, value) \
+    WMI_SET_BITS(_param, 0, 10, value)
+
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_GET(param) \
+    WMI_GET_BITS(param, 10, 1)
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_SET(_param, value) \
+    WMI_SET_BITS(_param, 10, 1, value)
+
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_GET(param) \
+    WMI_GET_BITS(param, 11, 3)
+#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_SET(_param, value) \
+    WMI_SET_BITS(_param, 11, 3, value)
+
 #define WMI_MBSSID_CTRL_FRAME_BASIC_TRIGGER ((A_UINT32) 1 << 0)
 #define WMI_MBSSID_CTRL_FRAME_BSR_TRIGGER ((A_UINT32) 1 << 1)
 #define WMI_MBSSID_CTRL_FRAME_MU_RTS_TRIGGER ((A_UINT32) 1 << 2)
@@ -23279,6 +23295,8 @@ typedef struct {
 #define WMI_PEER_EXT_IS_MESH_NODE       0x00000020 /* Indicates if the peer connecting is a mesh node */
 #define WMI_PEER_EXT_PROTECTED_TWT      0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */
 #define WMI_PEER_EXT_UHR                0x00000080 /* UHR enabled */
+#define WMI_PEER_EXT_2XLDPC             0x00000100 /* Peer supports 2x LDPC (3888-bit codeword) */
+
 #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000
 #define WMI_PEER_EXT_SMD_ASSOC          0x80000000
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f1277d305b45..4311246b96b0 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1773
+#define __WMI_REVISION_ 1774
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From d1cea237706a3414737773f4cdc341d5bf637bfd Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 29 May 2026 18:01:52 -0700
Subject: [PATCH 261/290] fw-api: CL 32692322 - update fw common interface
 files

Change-Id: I542168043420c52b4fe96b6f36cf5105843878ba
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 735 ++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 696 insertions(+), 39 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 36e7615294db..fec2c7616a30 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1199,7 +1199,9 @@ typedef struct {
 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \
     (((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \
      HTT_TX_PDEV_STATS_CMN_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_PDEV_CMN_MAC_ID_GET(_var) \
+    HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var)
 #define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \
@@ -1814,6 +1816,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_hw_pdev_errs_tlv htt_hw_stats_pdev_errs_tlv;
 
+#define HTT_STATS_HW_PDEV_ERRS_MAC_ID_GET(word) \
+    ((word >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -1843,6 +1848,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_whal_tx_tlv htt_hw_stats_whal_tx_tlv;
 
+#define HTT_STATS_WHAL_TX_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -1917,6 +1925,9 @@ typedef struct _htt_pdev_err_stats {
 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \
     (((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \
      HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PEER_MSDU_FLOWQ_TX_FLOW_NUMBER_GET(_var) \
+    HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var)
 
 #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \
     do { \
@@ -1927,6 +1938,9 @@ typedef struct _htt_pdev_err_stats {
 #define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \
     (((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \
      HTT_MSDU_FLOW_STATS_TID_NUM_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PEER_MSDU_FLOWQ_TID_NUM_GET(_var) \
+    HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var)
 
 #define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \
     do { \
@@ -1937,6 +1951,9 @@ typedef struct _htt_pdev_err_stats {
 #define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \
     (((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \
      HTT_MSDU_FLOW_STATS_DROP_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PEER_MSDU_FLOWQ_DROP_RULE_GET(_var) \
+    HTT_MSDU_FLOW_STATS_DROP_GET(_var)
 
 #define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \
     do { \
@@ -1992,7 +2009,9 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv;
 #define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \
     (((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \
      HTT_TX_TID_STATS_SW_PEER_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TID_DETAILS_SW_PEER_ID_GET(_var) \
+    HTT_TX_TID_STATS_SW_PEER_ID_GET(_var)
 #define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \
@@ -2002,7 +2021,9 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv;
 #define HTT_TX_TID_STATS_TID_NUM_GET(_var) \
     (((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \
      HTT_TX_TID_STATS_TID_NUM_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TID_DETAILS_TID_NUM_GET(_var) \
+    HTT_TX_TID_STATS_TID_NUM_GET(_var)
 #define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \
@@ -2018,7 +2039,9 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv;
 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \
     (((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \
      HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TID_DETAILS_NUM_SCHED_PENDING_GET(_var) \
+    HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var)
 #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \
@@ -2028,7 +2051,9 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv;
 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \
     (((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \
      HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TID_DETAILS_NUM_PPDU_IN_HWQ_GET(_var) \
+    HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var)
 #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \
@@ -2166,6 +2191,15 @@ typedef struct _htt_tx_tid_stats_v1_tlv {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv;
 
+#define HTT_STATS_TX_TID_DETAILS_V1_SW_PEER_ID_GET(word) \
+    (((word) >> 0) & 0xffff)
+#define HTT_STATS_TX_TID_DETAILS_V1_TID_NUM_GET(word) \
+    (((word) >> 16) & 0xffff)
+#define HTT_STATS_TX_TID_DETAILS_V1_NUM_SCHED_PENDING_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_TX_TID_DETAILS_V1_NUM_PPDU_IN_HWQ_GET(word) \
+    (((word) >> 8) & 0xff)
+
 #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff
 #define HTT_RX_TID_STATS_SW_PEER_ID_S 0
 #define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000
@@ -2174,7 +2208,9 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv;
 #define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \
     (((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \
      HTT_RX_TID_STATS_SW_PEER_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_TID_DETAILS_SW_PEER_ID_GET(_var) \
+    HTT_RX_TID_STATS_SW_PEER_ID_GET(_var)
 #define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \
@@ -2184,7 +2220,9 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv;
 #define HTT_RX_TID_STATS_TID_NUM_GET(_var) \
     (((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \
      HTT_RX_TID_STATS_TID_NUM_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_TID_DETAILS_TID_NUM_GET(_var) \
+    HTT_RX_TID_STATS_TID_NUM_GET(_var)
 #define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \
@@ -2445,7 +2483,9 @@ typedef struct {
 #define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) \
     (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M) >> \
      HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MPDU_CNT_GET(_var) \
+    HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var)
 #define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT, _val); \
@@ -2455,7 +2495,9 @@ typedef struct {
 #define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) \
     (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M) >> \
      HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MSDU_CNT_GET(_var) \
+    HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var)
 #define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT, _val); \
@@ -2642,8 +2684,14 @@ typedef htt_stats_peer_details_tlv htt_peer_details_tlv;
     HTT_PEER_DETAILS_GET(word, PEER_PS_EXIT)
 #define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) \
     HTT_PEER_DETAILS_GET(word, PEER_PSPOLL_TRIGGER)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_RECEIVED_GET(word) \
+    HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word)
 #define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) \
     HTT_PEER_DETAILS_GET(word, PEER_UAPSD_TRIGGER)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_RECEIVED_GET(word) \
+    HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word)
 #define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_0_GET(word) \
     HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_0)
 #define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_1_GET(word) \
@@ -2657,17 +2705,17 @@ typedef struct {
     A_UINT32     ast_index;
     htt_mac_addr mac_addr;
     A_UINT32
-        pdev_id        : 2,
-        vdev_id        : 8,
-        next_hop       : 1,
-        mcast          : 1,
-        monitor_direct : 1,
-        mesh_sta       : 1,
-        mec            : 1,
-        intra_bss      : 1,
-        chip_id        : 2,
-        ml_peer_id     : 13,
-        on_chip        : 1;
+        pdev_id        : 2,  /* bits 1:0 */
+        vdev_id        : 8,  /* bits 9:2 */
+        next_hop       : 1,  /* bit 10 */
+        mcast          : 1,  /* bit 11 */
+        monitor_direct : 1,  /* bit 12 */
+        mesh_sta       : 1,  /* bit 13 */
+        mec            : 1,  /* bit 14 */
+        intra_bss      : 1,  /* bit 15 */
+        chip_id        : 2,  /* bit 17:16 */
+        ml_peer_id     : 13, /* bit 30:18 */
+        on_chip        : 1;  /* bit 31 */
     A_UINT32
         tx_monitor_override_sta : 1,
         rx_monitor_override_sta : 1,
@@ -2676,6 +2724,34 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_ast_entry_tlv htt_ast_entry_tlv;
 
+#define HTT_STATS_AST_ENTRY_PDEV_ID_GET(word32) \
+    ((word32 >> 0) & 0x3)
+#define HTT_STATS_AST_ENTRY_VDEV_ID_GET(word32) \
+    ((word32 >> 2) & 0xff)
+#define HTT_STATS_AST_ENTRY_NEXT_HOP_GET(word32) \
+    ((word32 >> 10) & 0x1)
+#define HTT_STATS_AST_ENTRY_MCAST_GET(word32) \
+    ((word32 >> 11) & 0x1)
+#define HTT_STATS_AST_ENTRY_MONITOR_DIRECT_GET(word32) \
+    ((word32 >> 12) & 0x1)
+#define HTT_STATS_AST_ENTRY_MESH_STA_GET(word32) \
+    ((word32 >> 13) & 0x1)
+#define HTT_STATS_AST_ENTRY_MEC_GET(word32) \
+    ((word32 >> 14) & 0x1)
+#define HTT_STATS_AST_ENTRY_INTRA_BSS_GET(word32) \
+    ((word32 >> 15) & 0x1)
+#define HTT_STATS_AST_ENTRY_CHIP_ID_GET(word32) \
+    ((word32 >> 16) & 0x3)
+#define HTT_STATS_AST_ENTRY_ML_PEER_ID_GET(word32) \
+    ((word32 >> 18) & 0x1fff)
+#define HTT_STATS_AST_ENTRY_ON_CHIP_GET(word32) \
+    ((word32 >> 31) & 0x1)
+
+#define HTT_STATS_AST_ENTRY_TX_MONITOR_OVERRIDE_STA_GET(word32) \
+    ((word32 >> 0) & 0x1)
+#define HTT_STATS_AST_ENTRY_RX_MONITOR_OVERRIDE_STA_GET(word32) \
+    ((word32 >> 1) & 0x1)
+
 typedef enum {
     HTT_STATS_DIRECTION_TX,
     HTT_STATS_DIRECTION_RX,
@@ -3708,6 +3784,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv;
 
+#define HTT_STATS_TX_SELFGEN_CMN_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** 11AC VHT SU NDPA frame sent over the air */
@@ -5885,7 +5964,9 @@ typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v;
 #define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \
      HTT_TX_TQM_CMN_STATS_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TQM_CMN_MAC_ID_GET(_var) \
+    HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var)
 #define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \
@@ -5996,7 +6077,9 @@ typedef struct {
 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \
     (((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \
      HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \
+    HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var)
 #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \
@@ -6006,7 +6089,9 @@ typedef struct {
 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \
     (((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \
      HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \
+    HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var)
 #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \
@@ -6287,6 +6372,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv;
 
+#define HTT_STATS_TX_DE_CMN_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0)  & 0xffff)
 #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff)
 
@@ -6535,6 +6623,9 @@ typedef htt_stats_ring_if_tlv htt_ring_if_stats_tlv;
 #define HTT_RING_IF_CMN_MAC_ID_GET(_var) \
     (((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \
      HTT_RING_IF_CMN_MAC_ID_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RING_IF_CMN_MAC_ID_GET(_var) \
+    HTT_RING_IF_CMN_MAC_ID_GET(_var)
 
 #define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \
     do { \
@@ -6621,7 +6712,9 @@ typedef htt_stats_sfm_client_tlv htt_sfm_client_tlv;
 #define HTT_SFM_CMN_MAC_ID_GET(_var) \
     (((_var) & HTT_SFM_CMN_MAC_ID_M) >> \
      HTT_SFM_CMN_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SFM_CMN_MAC_ID_GET(_var) \
+    HTT_SFM_CMN_MAC_ID_GET(_var)
 #define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \
@@ -6700,7 +6793,9 @@ typedef struct {
 #define HTT_SRING_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_SRING_STATS_MAC_ID_M) >> \
      HTT_SRING_STATS_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_MAC_ID_GET(_var)  \
+    HTT_SRING_STATS_MAC_ID_GET(_var)
 #define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \
@@ -6710,7 +6805,9 @@ typedef struct {
 #define HTT_SRING_STATS_RING_ID_GET(_var) \
     (((_var) & HTT_SRING_STATS_RING_ID_M) >> \
      HTT_SRING_STATS_RING_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_RING_ID_GET(_var) \
+    HTT_SRING_STATS_RING_ID_GET(_var)
 #define HTT_SRING_STATS_RING_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \
@@ -6720,7 +6817,9 @@ typedef struct {
 #define HTT_SRING_STATS_ARENA_GET(_var) \
     (((_var) & HTT_SRING_STATS_ARENA_M) >> \
      HTT_SRING_STATS_ARENA_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_ARENA_GET(_var) \
+    HTT_SRING_STATS_ARENA_GET(_var)
 #define HTT_SRING_STATS_ARENA_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \
@@ -6730,7 +6829,9 @@ typedef struct {
 #define HTT_SRING_STATS_EP_TYPE_GET(_var) \
     (((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \
      HTT_SRING_STATS_EP_TYPE_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_EP_GET(_var) \
+    HTT_SRING_STATS_EP_TYPE_GET(_var)
 #define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \
@@ -6747,7 +6848,9 @@ typedef struct {
 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \
     (((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \
      HTT_SRING_STATS_NUM_AVAIL_WORDS_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \
+    HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var)
 #define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \
@@ -6757,7 +6860,9 @@ typedef struct {
 #define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \
     (((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \
      HTT_SRING_STATS_NUM_VALID_WORDS_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_NUM_VALID_WORDS_GET(_var) \
+    HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var)
 #define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \
@@ -6774,7 +6879,9 @@ typedef struct {
 #define HTT_SRING_STATS_HEAD_PTR_GET(_var) \
     (((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \
      HTT_SRING_STATS_HEAD_PTR_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_HEAD_PTR_GET(_var) \
+    HTT_SRING_STATS_HEAD_PTR_GET(_var)
 #define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \
@@ -6784,7 +6891,9 @@ typedef struct {
 #define HTT_SRING_STATS_TAIL_PTR_GET(_var) \
     (((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \
      HTT_SRING_STATS_TAIL_PTR_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_TAIL_PTR_GET(_var) \
+    HTT_SRING_STATS_TAIL_PTR_GET(_var)
 #define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \
@@ -6801,7 +6910,9 @@ typedef struct {
 #define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \
     (((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \
      HTT_SRING_STATS_CONSUMER_EMPTY_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_CONSUMER_EMPTY_GET(_var) \
+    HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var)
 #define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \
@@ -6811,7 +6922,9 @@ typedef struct {
 #define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \
     (((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \
      HTT_SRING_STATS_PRODUCER_FULL_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_PRODUCER_FULL_GET(_var) \
+    HTT_SRING_STATS_PRODUCER_FULL_GET(_var)
 #define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \
@@ -6828,7 +6941,9 @@ typedef struct {
 #define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \
     (((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \
      HTT_SRING_STATS_PREFETCH_COUNT_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_PREFETCH_COUNT_GET(_var) \
+    HTT_SRING_STATS_PREFETCH_COUNT_GET(_var)
 #define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \
@@ -6838,7 +6953,9 @@ typedef struct {
 #define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \
     (((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \
      HTT_SRING_STATS_INTERNAL_TP_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_SRING_STATS_INTERNAL_TAIL_PTR_GET(_var) \
+    HTT_SRING_STATS_INTERNAL_TP_GET(_var)
 #define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \
@@ -7269,6 +7386,11 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv;
 
+#define HTT_STATS_TX_PDEV_RATE_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(word) \
+    (((word) >> 8) & 0xf)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 vdev_id; /* which vdev produced these per-Nss tx stats */
@@ -7406,6 +7528,9 @@ typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv
 typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv
     htt_tx_pdev_rate_stats_be_ofdma_tlv;
 
+#define HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** tx_ppdu_dur_hist:
@@ -7452,6 +7577,9 @@ typedef struct {
 #define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M) >> \
      HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_PDEV_BN_RATE_MAC_ID_GET(_var) \
+    HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var)
 #define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_MAC_ID, _val); \
@@ -7463,6 +7591,9 @@ typedef struct {
 #define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) \
     (((_var) & HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M) >> \
      HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_PDEV_BN_RATE_WIFI_VERSION_GET(_var) \
+    HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var)
 #define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION, _val); \
@@ -7497,7 +7628,6 @@ typedef struct {
     A_UINT32 tx_11bn_su_elr;
 } htt_stats_tx_pdev_bn_rate_tlv;
 
-
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
  * TLV_TAGS:
  *      - HTT_STATS_TX_PDEV_RATE_STATS_TAG
@@ -7779,6 +7909,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_rate_stats_tlv htt_rx_pdev_rate_stats_tlv;
 
+#define HTT_STATS_RX_PDEV_RATE_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /** Tx PPDU duration histogram **/
@@ -7828,6 +7961,9 @@ typedef struct {
 #define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \
     (((_var) & HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M) >> \
      HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_PDEV_RATE_EXT_STATS_WIFI_VERSION_GET(_var) \
+    HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var)
 
 #define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
     do { \
@@ -8003,6 +8139,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv;
 
+#define HTT_STATS_RX_PDEV_UL_TRIG_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
  * TLV_TAGS:
  *      - HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG
@@ -8146,6 +8285,9 @@ typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv
 typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv
     htt_rx_pdev_be_ul_trigger_stats_tlv;
 
+#define HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
  * TLV_TAGS:
  *      - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG
@@ -8331,6 +8473,9 @@ typedef struct {
 typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv
     htt_rx_pdev_ul_mumimo_trig_stats_tlv;
 
+#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -8393,6 +8538,9 @@ typedef struct {
 typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv
     htt_rx_pdev_ul_mumimo_trig_be_stats_tlv;
 
+#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -8451,6 +8599,8 @@ typedef struct {
     A_UINT32 bn_ul_mumimo_basic_trigger_rx_qos_null_only;
 } htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv;
 
+#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
 
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS
  * TLV_TAGS:
@@ -8646,7 +8796,9 @@ typedef struct {
 #define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \
      HTT_RX_PDEV_FW_STATS_MAC_ID_S)
-
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \
+    HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var)
 #define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \
@@ -8860,6 +9012,9 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv;
 
+#define HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
+
 #define HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
 
 /* NOTE: Variable length TLV, use length spec to infer array size */
@@ -9952,6 +10107,9 @@ typedef enum {
 #define HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) \
     (((_var) & HTT_PER_RATE_STATS_WIFI_VERSION_M) >> \
      HTT_PER_RATE_STATS_WIFI_VERSION_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PER_RATE_STATS_WIFI_VERSION_GET(_var) \
+    HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var)
 
 #define HTT_PER_RATE_STATS_WIFI_VERSION_SET(_var, _val) \
     do { \
@@ -11213,6 +11371,9 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
 #define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHANNEL_M) >> \
      HTT_STATS_TPCCAL_POSTPROC_CHANNEL_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHANNEL_GET(_var) \
+    HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var)
 
 #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_M 0x00ff0000
 #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_S 16
@@ -11220,6 +11381,9 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
 #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHAIN_M) >> \
      HTT_STATS_TPCCAL_POSTPROC_CHAIN_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHAIN_GET(_var) \
+    HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var)
 
 #define HTT_STATS_TPCCAL_POSTPROC_BAND_M 0xff000000
 #define HTT_STATS_TPCCAL_POSTPROC_BAND_S 24
@@ -11227,6 +11391,9 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
 #define HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_POSTPROC_BAND_M) >> \
      HTT_STATS_TPCCAL_POSTPROC_BAND_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_BAND_GET(_var) \
+    HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var)
 
 #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M 0x000000ff
 #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S 0
@@ -11234,6 +11401,9 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
 #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M) >> \
      HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_NUMGAIN_GET(_var) \
+    HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var)
 
 #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M 0x0000ff00
 #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S 8
@@ -11241,6 +11411,9 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
 #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M) >> \
      HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CALDBSTATUS_GET(_var) \
+    HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var)
 
 /* STATS_TYPE : HTT_DBG_EXT_PDEV_STATS_FTM_TPCCAL
  * TLV_TAGS:
@@ -11400,6 +11573,12 @@ typedef struct {
 #define HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_PDADC_LAST_IDX_M) >> \
      HTT_STATS_TPCCAL_PDADC_LAST_IDX_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_LAST_IDX_GET(_var) \
+    HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_PDADC_LAST_IDX_GET(_var) \
+    HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var)
 
 #define HTT_STATS_TPCCAL_PDADC_NUMGAIN_M 0x000000ff
 #define HTT_STATS_TPCCAL_PDADC_NUMGAIN_S 0
@@ -11924,6 +12103,9 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv;
 #define HTT_STATS_ANI_MODE_GET(_var) \
     (((_var) & HTT_STATS_ANI_MODE_M) >> \
      HTT_STATS_ANI_MODE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_STATS_ANI_MODE_GET(_var) \
+    HTT_STATS_ANI_MODE_GET(_var)
 
 #define HTT_STATS_ANI_MODE_SET(_var, _val) \
     do { \
@@ -11937,6 +12119,9 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv;
 #define HTT_STATS_CURR_EANI_MODE_GET(_var) \
     (((_var) & HTT_STATS_CURR_EANI_MODE_M) >> \
      HTT_STATS_CURR_EANI_MODE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_STATS_CUREANIMODE_GET(_var) \
+    HTT_STATS_CURR_EANI_MODE_GET(_var) 
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -12048,76 +12233,107 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \
      HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_CALDATA_COMPRESSED_GET(_var) \
+    HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var)
 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \
      HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_CALDATASOURCE_GET(_var) \
+    HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var)
 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008
 #define HTT_STATS_PHY_RESET_XTALCAL_S 3
 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \
      HTT_STATS_PHY_RESET_XTALCAL_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_XTALCAL_GET(_var) \
+    HTT_STATS_PHY_RESET_XTALCAL_GET(_var)
 #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTALCAL_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GFPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GFPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \
@@ -12128,76 +12344,107 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GFPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var)
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \
      HTT_STATS_PHY_RESET_RXGAINCAL2G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL2G_GET(_var) \
+    HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var)
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL2G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \
      HTT_STATS_PHY_RESET_RXGAINCAL5G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL5G_GET(_var) \
+    HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var)
 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL5G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \
      HTT_STATS_PHY_RESET_RXGAINCAL6G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL6G_GET(_var) \
+    HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var)
 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL6G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000
 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13
 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \
      HTT_STATS_PHY_RESET_AOACAL2G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_AOACAL2G_GET(_var) \
+    HTT_STATS_PHY_RESET_AOACAL2G_GET(_var)
 #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL2G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000
 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14
 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \
      HTT_STATS_PHY_RESET_AOACAL5G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_AOACAL5G_GET(_var) \
+    HTT_STATS_PHY_RESET_AOACAL5G_GET(_var)
 #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL5G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000
 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15
 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \
      HTT_STATS_PHY_RESET_AOACAL6G_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_AOACAL6G_GET(_var) \
+    HTT_STATS_PHY_RESET_AOACAL6G_GET(_var)
 #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL6G_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \
      HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_XTAL_FROM_OTP_GET(_var) \
+    HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var)
 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \
@@ -12209,26 +12456,37 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \
      HTT_STATS_PHY_RESET_GLUT_LINEARITY_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_GLUT_LINEARITY_GET(_var) \
+    HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var)
 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_GLUT_LINEARITY_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \
      HTT_STATS_PHY_RESET_PLUT_LINEARITY_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_PLUT_LINEARITY_GET(_var) \
+    HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var)
 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_PLUT_LINEARITY_S)); \
     } while (0)
+
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \
      HTT_STATS_PHY_RESET_WLANDRIVERMODE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_WLANDRIVERMODE_GET(_var) \
+    HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var)
 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \
@@ -12748,6 +13006,11 @@ typedef struct {
     A_UINT32 power_boost_gain[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS];
 } htt_stats_phy_paprd_pb_tlv;
 
+#define HTT_STATS_PHY_PAPRD_PB_IS_DPD_VALID_GET(word) \
+    (((word) >> 0) & 0x1)
+
+#define HTT_STATS_PHY_PAPRD_PB_IS_PB_VALID_GET(word) \
+    (((word) >> 1) & 0x1)
 
 #define HTT_STATS_HDS_PROF_STATS_CIRCULAR_BUF_LEN 10
 
@@ -12902,122 +13165,194 @@ typedef struct {
 
 #define HTT_STATS_OPT_CONF_GET_DYN_CCA(word) \
     (((word) & 0x1) >> 0)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_CCA_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_DYN_CCA(word)
 #define HTT_STATS_OPT_CONF_SET_DYN_CCA(word, value) \
     ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0))
 
 #define HTT_STATS_OPT_CONF_GET_LPI(word) \
     (((word) & 0x2) >> 1)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_LPI_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_LPI(word)
 #define HTT_STATS_OPT_CONF_SET_LPI(word, value) \
     ((word) = ((word) & ~0x2) | (((value) & 0x1) << 1))
 
 #define HTT_STATS_OPT_CONF_GET_GTX(word) \
     (((word) & 0x4) >> 2)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_GTX_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_GTX(word)
 #define HTT_STATS_OPT_CONF_SET_GTX(word, value) \
     ((word) = ((word) & ~0x4) | (((value) & 0x1) << 2))
 
 #define HTT_STATS_OPT_CONF_GET_ANI(word) \
     (((word) & 0x8) >> 3)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANI_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_ANI(word)
 #define HTT_STATS_OPT_CONF_SET_ANI(word, value) \
     ((word) = ((word) & ~0x8) | (((value) & 0x1) << 3))
 
 #define HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) \
     (((word) & 0x10) >> 4)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_STATIC_ANI_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_STATIC_ANI(word)
 #define HTT_STATS_OPT_CONF_SET_STATIC_ANI(word, value) \
     ((word) = ((word) & ~0x10) | (((value) & 0x1) << 4))
 
 #define HTT_STATS_OPT_CONF_GET_ANN_PBT(word) \
     (((word) & 0x20) >> 5)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANN_PBT_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_ANN_PBT(word)
 #define HTT_STATS_OPT_CONF_SET_ANN_PBT(word, value) \
     ((word) = ((word) & ~0x20) | (((value) & 0x1) << 5))
 
 #define HTT_STATS_OPT_CONF_GET_EANI(word) \
     (((word) & 0x40) >> 6)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_E_ANI_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_EANI(word)
 #define HTT_STATS_OPT_CONF_SET_EANI(word, value) \
     ((word) = ((word) & ~0x40) | (((value) & 0x1) << 6))
 
 #define HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) \
     (((word) & 0x80) >> 7)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_SPUR_MIT_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_SPUR_MIT(word)
 #define HTT_STATS_OPT_CONF_SET_SPUR_MIT(word, value) \
     ((word) = ((word) & ~0x80) | (((value) & 0x1) << 7))
 
 #define HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) \
     (((word) & 0x100) >> 8)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_MULTIGAIN_RSSI_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word)
 #define HTT_STATS_OPT_CONF_SET_MULTIGAIN_RSSI(word, value) \
     ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8))
 
 #define HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) \
     (((word) & 0x200) >> 9)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_OLPC_CLPC_GET(word) \
+    HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word)
 #define HTT_STATS_OPT_CONF_SET_OLPC_CLPC(word, value) \
     ((word) = ((word) & ~0x200) | (((value) & 0x1) << 9))
 
 #define HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) \
     (((word) & 0x400) >> 10)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_ABI_EN_DIS_GET(word) \
+    HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word)
 #define HTT_STATS_OPT_CONF_SET_ABI_EN_DIS(word, value) \
     ((word) = ((word) & ~0x400) | (((value) & 0x1) << 10))
 
 #define HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) \
     (((word) & 0x800) >> 11)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_STR_SIG_REC_GET(word) \
+    HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word)
 #define HTT_STATS_OPT_CONF_SET_STR_SIG_REC(word, value) \
     ((word) = ((word) & ~0x800) | (((value) & 0x1) << 11))
 
 #define HTT_STATS_OPT_CONF_GET_VERBOSE(word) \
     (((word) & 0x1000) >> 12)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_VERBOSE_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_VERBOSE(word)
 #define HTT_STATS_OPT_CONF_SET_VERBOSE(word, value) \
     ((word) = ((word) & ~0x1000) | (((value) & 0x1) << 12))
 
 #define HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) \
     (((word) & 0x2000) >> 13)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_ANT_SEL_SUPPORTED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word)
 #define HTT_STATS_OPT_CONF_SET_DYN_ANT_SEL(word, value) \
     ((word) = ((word) & ~0x2000) | (((value) & 0x1) << 13))
 
 #define HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) \
     (((word) & 0x4000) >> 14)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_DFS_PUNC_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_DFS_PUNC(word)
 #define HTT_STATS_OPT_CONF_SET_DFS_PUNC(word, value) \
     ((word) = ((word) & ~0x4000) | (((value) & 0x1) << 14))
 
 #define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \
     (((word) & 0x8000) >> 15)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_DPD_POW_BO_STATUS_GET(word) \
+    HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word)
 #define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \
     ((word) = ((word) & ~0x8000) | (((value) & 0x1) << 15))
 
 #define HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) \
     (((word) & 0x10000) >> 16)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_EEPROM_COMPRESSED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word)
 #define HTT_STATS_OPT_CONF_SET_EEPROM_COMPRESSED(word, value) \
     ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16))
 
 
 #define HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) \
     (((word) & 0x1) >> 0)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_RXSOP_ENABLED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word)
 #define HTT_STATS_OPT_CONF_SET_RXSOP_ENABLED(word, value) \
     ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0))
 
 #define HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) \
     (((word) & 0x1FE) >> 1)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_RXSOP_CONFIG_VALUE_GET(word) \
+    HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word)
 #define HTT_STATS_OPT_CONF_SET_RXSOP_CONFIG_VALUE(word, value) \
     ((word) = ((word) & ~0x1FE) | (((value) & 0xFF) << 1))
 
 #define HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) \
     ((word) & 0xFFFF)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_HC_PREMCS_GET(word) \
+    HTT_STATS_OPT_CONF_GET_HC_PREMCS(word)
 #define HTT_STATS_OPT_CONF_SET_HC_PREMCS(word, value) \
     ((word) = ((value) & 0xFFFF))
 
 #define HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) \
     (((word) & 0xFFFF0000) >> 16)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_HC_PKT_TYPE_GET(word) \
+    HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word)
 #define HTT_STATS_OPT_CONF_SET_HC_PKT_TYPE(word, value) \
     ((word) = ((word) & ~0xFFFF0000) | (((value) & 0xFFFF) << 16))
 
 #define HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) \
     (((word) & 0x000000FF) >> 0)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_HC_NSS_THR_GET(word) \
+    HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word)
 #define HTT_STATS_OPT_CONF_SET_HC_NSS_THR(word, value) \
     ((word) = ((word) & ~0x000000FF) | (((value) & 0xFF) << 0))
 
 #define HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) \
     (((word) & 0x0000FF00) >> 8)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_IS_RX_GAIN_FORCED_GET(word) \
+    HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word)
 #define HTT_STATS_OPT_CONF_SET_IS_RX_GAIN_FORCED(word, value) \
     ((word) = ((word) & ~0x0000FF00) | (((value) & 0xFF) << 8))
 
 #define HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) \
     (((word) & 0x00FF0000) >> 16)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_OPTIONAL_CONFIGS_RX_GAIN_FORCED_VAL_GET(word) \
+    HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word)
 #define HTT_STATS_OPT_CONF_SET_RX_GAIN_FORCED_VAL(word, value) \
     ((word) = ((word) & ~0x00FF0000) | (((value) & 0xFF) << 16))
 
@@ -13321,6 +13656,48 @@ typedef struct {
     A_UINT32 bdReadRsp;
 } htt_stats_ftm_tlv;
 
+#define HTT_STATS_FTM_TX_PARAMS_XTALCAL_GAIN_IDX_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_INFINITE_BURSTING_MODE_GET(word) \
+    (((word) >> 8) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_FTM_MODE_GET(word) \
+    (((word) >> 16) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_SIFS_US_GET(word) \
+    (((word) >> 24) & 0xff)
+
+#define HTT_STATS_FTM_TX_PARAMS_AGG_STATUS_GET(word) \
+    (((word) >> 0) & 0x1)
+#define HTT_STATS_FTM_TX_PARAMS_DPDFLAG_GET(word) \
+    (((word) >> 1) & 0x1)
+#define HTT_STATS_FTM_TX_PARAMS_PPDU_DUR_BUF_LAST_IDX_GET(word) \
+    (((word) >> 2) & 0xff)
+
+#define HTT_STATS_FTM_TX_PARAMS_TARGET_TX_DUTY_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_PPDUTYPE_GET(word) \
+    (((word) >> 8) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLAN_GET(word) \
+    (((word) >> 16) & 0xff)
+#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLANEHT_GET(word) \
+    (((word) >> 24) & 0xff)
+
+#define HTT_STATS_FTM_TIMINGSTATS_TLVTIMESTAMPCNTFILLED_GET(word) \
+    (((word) >> 0) & 0xff)
+
+#define HTT_STATS_FTM_TIMINGSTATS_TLVCMD_ENTRY_GET(word) \
+    (((word) >> 0) & 0xffff)
+#define HTT_STATS_FTM_TIMINGSTATS_TLVCALTYPE_GET(word) \
+    (((word) >> 16) & 0xff)
+
+#define HTT_STATS_FTM_TLVPARAMS_FLAGTLVCMDPARSING_GET(word) \
+    (((word) >> 0) & 0x1)
+#define HTT_STATS_FTM_TLVPARAMS_NUMTLVCMDDROPPED_GET(word) \
+    (((word) >> 1) & 0xff)
+
+#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCALMAXNUMCHAN_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCAL_REFISS_GET(word) \
+    (((word) >> 0) & 0xff)
 
 typedef struct {
     union {
@@ -13792,6 +14169,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID, _val); \
@@ -13802,6 +14186,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID, _val); \
@@ -13812,6 +14203,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID, _val); \
@@ -13822,6 +14220,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID, _val); \
@@ -13832,6 +14237,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID, _val); \
@@ -13842,6 +14254,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID, _val); \
@@ -13852,6 +14271,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID, _val); \
@@ -13862,6 +14288,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID, _val); \
@@ -13872,6 +14305,13 @@ typedef struct {
 #define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) \
     (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M) >> \
      HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK0_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK1_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var)
+#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK2_ID_GET(_var) \
+    HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var)
 #define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID, _val); \
@@ -14130,6 +14570,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv;
 #define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var) \
     (((_var) & HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M) >> \
      HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ML_LINK_INFO_DETAILS_BRIDGE_PEER_GET(_var) \
+    HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var)
 #define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_BRIDGE_PEER, _val); \
@@ -14169,6 +14612,9 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv;
 #define HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var) \
     (((_var) & HTT_STATS_ML_LINK_INFO_PS_STATE_M) >> \
      HTT_STATS_ML_LINK_INFO_PS_STATE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ML_LINK_INFO_DETAILS_PS_GET(_var) \
+    HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var)
 #define HTT_STATS_ML_LINK_INFO_PS_STATE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_PS_STATE, _val); \
@@ -14818,6 +15264,8 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_pdev_mbssid_ctrl_frame_stats_tlv
     htt_pdev_mbssid_ctrl_frame_stats_tlv;
+#define HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_MAC_ID_GET(word) \
+    (((word) >> 0) & 0xff)
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -14890,6 +15338,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
 #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \
      HTT_BW_MGR_STATS_MAC_ID_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_MAC_ID_GET(_var) \
+    HTT_BW_MGR_STATS_MAC_ID_GET(_var)
 
 #define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \
     do { \
@@ -14903,6 +15354,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_PRI20_IDX_S)
 #define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \
      HTT_BW_MGR_STATS_PRI20_IDX_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_IDX_GET(_var) \
+    HTT_BW_MGR_STATS_PRI20_IDX_GET(_var)
 
 #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \
     do { \
@@ -14918,6 +15372,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_PRI20_FREQ_S)
 #define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_GET(_var) \
     HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_FREQ_MHZ_GET(_var) \
+    HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var)
 
 #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \
     do { \
@@ -14933,6 +15390,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_CENTER_FREQ1_S)
 #define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_GET(_var) \
     HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ1_GET(_var) \
+    HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var)
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \
     do { \
@@ -14948,6 +15408,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_CENTER_FREQ2_S)
 #define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_GET(_var) \
     HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ2_GET(_var) \
+    HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var)
 
 #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \
     do { \
@@ -14963,6 +15426,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)
 #define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_GET(_var) \
     HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_PHY_MODE_GET(_var) \
+    HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var)
 
 #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \
     do { \
@@ -14978,6 +15444,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
      HTT_BW_MGR_STATS_STATIC_PATTERN_S)
 #define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \
      HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \
+    HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var)
 
 #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \
     do { \
@@ -14991,6 +15460,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
 #define HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) \
     (((_var) & HTT_BW_MGR_STATS_WIFI_VERSION_M) >> \
      HTT_BW_MGR_STATS_WIFI_VERSION_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_BW_MGR_STATS_WIFI_VERSION_GET(_var) \
+    HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var)
 
 #define HTT_BW_MGR_STATS_WIFI_VERSION_SET(_var, _val) \
     do { \
@@ -14998,6 +15470,24 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv;
         ((_var) |= ((_val) << HTT_BW_MGR_STATS_WIFI_VERSION_S)); \
     } while (0)
 
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var)  \
+    (((_var) >> 8) & 0xff)
+
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_FREQ_MHZ_GET(_var)  \
+    (((_var) >> 16) & 0xffff)
+
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ1_GET(_var) \
+    (((_var) >> 0) & 0xffff)
+
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ2_GET(_var) \
+    (((_var) >> 16) & 0xffff)
+
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PHY_MODE_GET(_var) \
+    (((_var) >> 0) & 0xff)
+
+#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \
+    (((_var) >> 8) & 0xffff)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -15223,6 +15713,61 @@ typedef struct {
 /* preserve old name alias for new name consistent with the tag name */
 typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv;
 
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) \
+    (((word) >> 0) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_HWMLOS_GET(word) \
+    (((word) >> 1) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_GLOBAL_WSI_GET(word) \
+    (((word) >> 2) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_DMAC_GET(word) \
+    (((word) >> 3) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TCL_GET(word) \
+    (((word) >> 4) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TQM_GET(word) \
+    (((word) >> 5) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_WBM_GET(word) \
+    (((word) >> 6) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_REO_GET(word) \
+    (((word) >> 7) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_HOST_GET(word) \
+    (((word) >> 8) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PREREQUISITES_GET(word) \
+    (((word) >> 9) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PRE_RING_RESET_GET(word) \
+    (((word) >> 10) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_APPLY_SOFT_RESET_GET(word) \
+    (((word) >> 11) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_POST_RING_RESET_GET(word) \
+    (((word) >> 12) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_FW_TQM_CMDQS_GET(word) \
+    (((word) >> 13) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_GET(word) \
+    (((word) >> 14) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_UMAC_INTERRUPTS_GET(word) \
+    (((word) >> 15) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_WBM_GET(word) \
+    (((word) >> 16) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_REO_GET(word) \
+    (((word) >> 17) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_GET(word) \
+    (((word) >> 18) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_DMAC_GET(word) \
+    (((word) >> 19) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_SYNC_CMD_GET(word) \
+    (((word) >> 20) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_GLOBAL_WSI_GET(word) \
+    (((word) >> 21) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_HWMLOS_GET(word) \
+    (((word) >> 22) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) \
+    (((word) >> 23) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TCL_GET(word) \
+    (((word) >> 24) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_ENQ_GET(word) \
+    (((word) >> 25) & 0x1)
+#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) \
+    (((word) >> 26) & 0x1)
+
 /* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */
 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1
 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0
@@ -15839,6 +16384,9 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv;
 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \
     (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \
      HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CODEL_MSDUQ_TX_FLOW_NUM_GET(_var) \
+    HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var)
 #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \
@@ -15851,6 +16399,9 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv;
 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \
     (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \
      HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CODEL_MSDUQ_SVC_CLASS_ID_GET(_var) \
+    HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var)
 #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \
@@ -15863,6 +16414,9 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv;
 #define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \
     (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \
      HTT_CODEL_MSDUQ_STATS_DROPS_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CODEL_MSDUQ_CODEL_DROPS_GET(_var) \
+    HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var)
 #define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \
@@ -15875,6 +16429,9 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv;
 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \
     (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \
      HTT_CODEL_MSDUQ_STATS_NO_DROPS_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CODEL_MSDUQ_CODEL_NO_DROPS_GET(_var) \
+    HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var)
 #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \
@@ -16220,16 +16777,25 @@ typedef struct {
 
 #define HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) \
     HTT_STATS_GET_FIELD(0xFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_CTRY_MAJOR_VERSION_GET(word) \
+    HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word)
 #define HTT_STATS_REGDB_CTRY_SET_MAJOR_VERSION(word,value) \
     HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
 
 #define HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) \
     HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_CTRY_MINOR_VERSION_GET(word) \
+    HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word)
 #define HTT_STATS_REGDB_CTRY_SET_MINOR_VERSION(word,value) \
     HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
 
 #define HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) \
     HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_CTRY_CUSTOM_VERSION_GET(word) \
+    HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word)
 #define HTT_STATS_REGDB_CTRY_SET_CUSTOM_VERSION(word,value) \
     HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
 
@@ -16367,32 +16933,50 @@ typedef struct {
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) \
     HTT_STATS_GET_FIELD(0xFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_CTL_REGION_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_CTL_REGION(word,value) \
     HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) \
     HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_CCA_REGION_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_CCA_REGION(word,value) \
     HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) \
     HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_DFS_REGION_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_DFS_REGION(word,value) \
     HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) \
     HTT_STATS_GET_FIELD(0xFF000000, 24, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_DOMAIN_CTL_INDEX_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_DOMAIN_CTL_INDEX(word,value) \
     HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
 
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_NUM_RULES_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_NUM_RULES(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
 
 #define HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REGDB_REGDOMAIN_RULE_SIZE_GET(word) \
+    HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word)
 #define HTT_STATS_REGDB_REGDOMAIN_SET_RULE_SIZE(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 
@@ -16439,44 +17023,68 @@ typedef struct {
 
 #define HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) \
     HTT_STATS_GET_FIELD(0x0000FF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_DEPLOYMENT_TYPE_GET(word) \
+    HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word)
 #define HTT_STATS_REG_6G_SET_DEPLOYMENT_TYPE(word,value) \
     HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) \
     HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_POWER_MODE_MASK_GET(word) \
+    HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word)
 #define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \
     HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
 
-
 #define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_SET_TPC_COUNT_GET(word) \
+    HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word)
 #define HTT_STATS_REG_6G_SET_SET_TPC_COUNT(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_SET_TPC_PASS_COUNT_GET(word) \
+    HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word)
 #define HTT_STATS_REG_6G_SET_SET_TPC_PASS_COUNT(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) \
     HTT_STATS_GET_FIELD(0xF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CURRENT_POWER_MODE_GET(word) \
+    HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word)
 #define HTT_STATS_REG_6G_SET_CURRENT_POWER_MODE(word,value) \
     HTT_STATS_SET_FIELD(0xF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) \
     HTT_STATS_GET_FIELD(0xF0, 4, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_LAST_BEST_POWER_MODE_GET(word) \
+    HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word)
 #define HTT_STATS_REG_6G_SET_LAST_BEST_POWER_MODE(word,value) \
     HTT_STATS_SET_FIELD(0xF0, 4, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) \
     HTT_STATS_GET_FIELD(0x100, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_IS_CURRENT_MODE_BEST_POWER_MODE_GET(word) \
+    HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word)
 #define HTT_STATS_REG_6G_SET_IS_CURRENT_POWER_MODE_BEST(word,value) \
     HTT_STATS_SET_FIELD(0x100, 8, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_BEST_POWER_MODE_COUNT_GET(word) \
+    HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word)
 #define HTT_STATS_REG_6G_SET_BEST_POWER_MODE_COUNT(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
 #define HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS 16
 
 
@@ -16540,36 +17148,57 @@ typedef htt_stats_reg_6g_ch_pwr_info_tlv
 
 #define HTT_STATS_REG_6G_GET_POWER_TYPE(word) \
     HTT_STATS_GET_FIELD(0xFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_POWER_TYPE_6GHZ_GET(word) \
+    HTT_STATS_REG_6G_GET_POWER_TYPE(word)
 #define HTT_STATS_REG_6G_SET_POWER_TYPE(word,value) \
     HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_EIRP_POWER(word) \
     HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_GET(word) \
+    HTT_STATS_REG_6G_GET_EIRP_POWER(word)
 #define HTT_STATS_REG_6G_SET_EIRP_POWER(word,value) \
     HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_IS_PSD(word) \
     HTT_STATS_GET_FIELD(0x10000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_IS_PSD_POWER_GET(word) \
+    HTT_STATS_REG_6G_GET_IS_PSD(word)
 #define HTT_STATS_REG_6G_SET_IS_PSD(word,value) \
     HTT_STATS_SET_FIELD(0x10000, 16, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) \
     HTT_STATS_GET_FIELD(0x20000, 17, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_BOTH_PSD_EIRP_SUPPORT_GET(word) \
+    HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word)
 #define HTT_STATS_REG_6G_SET_BOTH_PSD_EIRP_SUPPORT(word,value) \
     HTT_STATS_SET_FIELD(0x20000, 17, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) \
     HTT_STATS_GET_FIELD(0xFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_POWER_LEVELS_GET(word) \
+    HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word)
 #define HTT_STATS_REG_6G_SET_NUM_POWER_LEVELS(word,value) \
     HTT_STATS_SET_FIELD(0xFF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) \
     HTT_STATS_GET_FIELD(0xFF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_PSD_LEVELS_GET(word) \
+    HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word)
 #define HTT_STATS_REG_6G_SET_NUM_PSD_LEVELS(word,value) \
     HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) \
     HTT_STATS_GET_FIELD(0xFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_EIRP_LEVELS_GET(word) \
+    HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word)
 #define HTT_STATS_REG_6G_SET_NUM_EIRP_LEVELS(word,value) \
     HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value))
 
@@ -16588,11 +17217,17 @@ typedef struct {
 
 #define HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OFFSET_GET(word) \
+    HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word)
 #define HTT_STATS_REG_6G_SET_OOBE_LIMIT_OFFSET(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
 
 #define HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_PSD_GET(word) \
+    HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word)
 #define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 
@@ -16615,11 +17250,17 @@ typedef struct {
 
 #define HTT_STATS_CTL_GET_REG_RULE_INDEX(word) \
     HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CTL_REGRULEINDEX_GET(word) \
+    HTT_STATS_CTL_GET_REG_RULE_INDEX(word)
 #define HTT_STATS_CTL_SET_REG_RULE_INDEX(word,value) \
     HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
 
 #define HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) \
     HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_CTL_POWERRULEINDEX_GET(word) \
+    HTT_STATS_CTL_GET_POWER_RULE_INDEX(word)
 #define HTT_STATS_CTL_SET_POWER_RULE_INDEX(word,value) \
     HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
 
@@ -16642,21 +17283,33 @@ typedef struct {
 
 #define HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) \
     HTT_STATS_GET_FIELD(0x00000001, 0, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ENHANCED_CTL_ENHANCEDCTLENABLE_GET(word) \
+    HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word)
 #define HTT_STATS_ENHANCED_CTL_SET_ENHANCED_CTL_ENABLE(word,value) \
     HTT_STATS_SET_FIELD(0x00000001, 0, (word), (value))
 
 #define HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) \
     HTT_STATS_GET_FIELD(0x0000FF00, 8, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ENHANCED_CTL_DOMAINCTLINDEX_GET(word) \
+    HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word)
 #define HTT_STATS_ENHANCED_CTL_SET_DOMAIN_CTL_INDEX(word,value) \
     HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value))
 
 #define HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) \
     HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ENHANCED_CTL_ARRAY_GAIN_CAP_CTLREGION_GET(word) \
+    HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word)
 #define HTT_STATS_ENHANCED_CTL_SET_ARRAY_GAIN_CAP_CTL_REGION(word,value) \
     HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
 
 #define HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) \
     HTT_STATS_GET_FIELD(0xFF000000, 24, (word))
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_ENHANCED_CTL_EXCEPTIONCTLREGION_GET(word) \
+    HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word)
 #define HTT_STATS_ENHANCED_CTL_SET_EXCEPTION_CTL_REGION(word,value) \
     HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
 
@@ -16899,6 +17552,8 @@ typedef struct {
     (((_var).channel_context.channel_info & \
       HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M) >> \
      HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S)
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_MHZ_GET(word) \
+    (((word) >> 0) & 0xffff)
 #define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ, _val); \
@@ -16910,6 +17565,8 @@ typedef struct {
     (((_var).channel_context.channel_info & \
       HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M) >> \
      HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S)
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_FLAGS_GET(word) \
+    (((word) >> 16) & 0xffff)
 #define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS, _val); \

From 2f8509c7f4a77c575dc665ecfa02c0cb4dc3fed8 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 29 May 2026 18:03:47 -0700
Subject: [PATCH 262/290] fw-api: CL 32697669 - update fw common interface
 files

Change-Id: I54453dbf6a4638ae7aeece661b9b27e40533c390
CRs-Fixed: 3830439
---
 fw/htt.h | 196 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 194 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 18d7614c2450..2f41c5add0d0 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -285,9 +285,10 @@
  * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t.
  * 3.156 Add qdata_consent_pkt flag in rx_peer_metadata_v1a and v2.
  * 3.157 Add TCL_METADATA_V3 defs.
+ * 3.158 Add more fields in htt_tx_monitor_cfg_t.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 157
+#define HTT_CURRENT_VERSION_MINOR 158
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -8110,7 +8111,10 @@ PREPACK struct htt_tx_monitor_cfg_t {
              pkt_swap:                               1,
              tx_mon_global_en:                       1,
              mac_addr_filter_en:                     1,
-             rsvd1:                                  4;
+             addr_filter_peer_bitmap_ppdu_drop:      1,
+             type_based_mpdu_stat_filter_en:         1,
+             special_pkt_filtering_en:               1,
+             pkt_buf_cnt_en:                         1;
     A_UINT32 ring_buffer_size:                      16,
              config_length_mgmt:                     3,
              config_length_ctrl:                     3,
@@ -8154,6 +8158,23 @@ PREPACK struct htt_tx_monitor_cfg_t {
              response_end_status_word_mask:         16;
     A_UINT32 fes_status_prot_word_mask:             11,
              rsvd6:                                 21;
+    A_UINT32 phy_tx_pkt_end:                         8,
+             mac_tx_user_desc_common:                8,
+             mac_tx_mu_uplink_user_setup:            8,
+             pdg_response:                           8;
+    A_UINT32 received_response_info:                 8,
+             rx_response_required_info:              8,
+             ranging_user_details:                   8,
+             mactx_pre_phy_desc:                     8;
+    A_UINT32 ofdma_trigger_details:                  16,
+             tqm_update_tx_mpdu_count_status:        16;
+    A_UINT32 phytx_location:                         16,
+             rsvd7:                                  16;
+    A_UINT32 received_response_info_part2;
+    A_UINT32 type_en_mgmt;
+    A_UINT32 type_en_ctrl;
+    A_UINT32 type_en_data;
+    A_UINT32 tlv_filter_mask_in4;
 } POSTPACK;
 
 #define HTT_TX_MONITOR_CFG_SZ    (sizeof(struct htt_tx_monitor_cfg_t))
@@ -8224,6 +8245,51 @@ PREPACK struct htt_tx_monitor_cfg_t {
                 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)); \
             } while (0)
 
+#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M 0x10000000
+#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S 28
+#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_GET(_var) \
+    (((_var) & HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M) >> \
+        HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S)
+#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP, _val); \
+        ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S)); \
+    } while (0)
+
+#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M 0x20000000
+#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S 29
+#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_GET(_var) \
+    (((_var) & HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M) >> \
+        HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S)
+#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN, _val); \
+        ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S)); \
+    } while (0)
+
+#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M 0x40000000
+#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S 30
+#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_GET(_var) \
+    (((_var) & HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M) >> \
+        HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S)
+#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN, _val); \
+        ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S)); \
+    } while (0)
+
+#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M 0x80000000
+#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S 31
+#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_GET(_var) \
+    (((_var) & HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M) >> \
+        HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S)
+#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN, _val); \
+        ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S)); \
+    } while (0)
+
+
 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M           0x0000ffff
 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S           0
 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \
@@ -8610,6 +8676,132 @@ PREPACK struct htt_tx_monitor_cfg_t {
                 ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \
             } while (0)
 
+
+#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M 0x000000ff
+#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S 0
+#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M) >> \
+                    HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S)
+#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHY_TX_PKT_END, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M 0x0000ff00
+#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S 8
+#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M) >> \
+                    HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S)
+#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M 0x00ff0000
+#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S 16
+#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M) >> \
+                    HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S)
+#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_M 0xff000000
+#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_S 24
+#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_PDG_RESPONSE_M) >> \
+                    HTT_TX_MONITOR_CFG_PDG_RESPONSE_S)
+#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDG_RESPONSE, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDG_RESPONSE_S)); \
+            } while (0)
+
+
+#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M 0x000000ff
+#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S 0
+#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M) >> \
+                    HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S)
+#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M 0x0000ff00
+#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S 8
+#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M) >> \
+                    HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S)
+#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M 0x00ff0000
+#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S 16
+#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M) >> \
+                    HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S)
+#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M 0xff000000
+#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S 24
+#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M) >> \
+                    HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S)
+#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S)); \
+            } while (0)
+
+
+#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M 0x0000ffff
+#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S 0
+#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M) >> \
+                    HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S)
+#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S)); \
+            } while (0)
+
+#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M 0xffff0000
+#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S 16
+#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M) >> \
+                    HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S)
+#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S)); \
+            } while (0)
+
+
+#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M 0x0000ffff
+#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S 0
+#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_GET(_var) \
+            (((_var) & HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M) >> \
+                    HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S)
+#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_SET(_var, _val) \
+            do { \
+                HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHYTX_LOCATION, _val); \
+                ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S)); \
+            } while (0)
+
+
 /*
  * pkt_type_enable_flags
  */

From 40b76f40b3e45bc1b5c33b791d52a2775a1f811d Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 29 May 2026 18:05:45 -0700
Subject: [PATCH 263/290] fw-api: CL 32697676 - update fw common interface
 files

Change-Id: Ieb8df0407342ff4a8a8c3eec180765795e75a2a1
CRs-Fixed: 3830439
---
 fw/wmi_services.h |   7 ++++
 fw/wmi_tlv_defs.h |  40 ++++++++++++++++++
 fw/wmi_unified.h  | 104 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 4 files changed, 152 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 830df224684c..43b84dad12bb 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -834,6 +834,13 @@ typedef  enum  {
 
     WMI_SERVICE_WMI_ANOMALY_REPORTING = 517,
 
+    /*
+     * Indicates that FW supports C-TAS power indication reporting and
+     * power limit enquiring through cmds WMI_SET_MODIFY_TX_PLIM_CMDID,
+     * WMI_GET_AVG_TX_POWER_CMDID and WMI_GET_TX_POWER_CALLING_CMDID.
+     */
+    WMI_SERVICE_CTAS_PLIM_INDICATION_SUPPORT = 518,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index d9ad9c4d8b16..aeff9c6e8d85 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1648,6 +1648,14 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain,
+    WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2261,6 +2269,9 @@ typedef enum {
     OP(WMI_PEER_SET_MAPC_PARAMS_CMDID) \
     OP(WMI_NAN_DISC_SERVICE_REQ_CMDID) \
     OP(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID) \
+    OP(WMI_SET_MODIFY_TX_PLIM_CMDID) \
+    OP(WMI_GET_AVG_TX_POWER_CMDID) \
+    OP(WMI_GET_TX_POWER_CALLING_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2635,6 +2646,9 @@ typedef enum {
     OP(WMI_NAN_DISC_SERVICE_RSP_EVENTID) \
     OP(WMI_NAN_DISC_MATCH_EVENTID) \
     OP(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID) \
+    OP(WMI_MODIFY_TX_PLIM_EVENTID) \
+    OP(WMI_AVG_TX_POWER_EVENTID) \
+    OP(WMI_PLIMIT_TABLE_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6358,6 +6372,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param, wmi_get_scan_cache_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_CACHE_RESULT_CMDID);
 
+#define WMITLV_TABLE_WMI_SET_MODIFY_TX_PLIM_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param, wmi_set_modify_tx_plim_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_SET_MODIFY_TX_PLIM_CMDID);
+
+#define WMITLV_TABLE_WMI_GET_AVG_TX_POWER_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param, wmi_get_avg_tx_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_AVG_TX_POWER_CMDID);
+
+#define WMITLV_TABLE_WMI_GET_TX_POWER_CALLING_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param, wmi_get_tx_power_calling_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_TX_POWER_CALLING_CMDID);
+
 #define WMITLV_TABLE_WMI_SAWF_EZMESH_HOP_COUNT_CMDID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param, wmi_sawf_ezmesh_hop_count_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_EZMESH_HOP_COUNT_CMDID);
@@ -8978,6 +9004,20 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_cache_info, scan_cache_info, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID);
 
+#define WMITLV_TABLE_WMI_MODIFY_TX_PLIM_EVENTID(id, op , buf, len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param, wmi_modify_tx_plim_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MODIFY_TX_PLIM_EVENTID);
+
+#define WMITLV_TABLE_WMI_AVG_TX_POWER_EVENTID(id, op , buf, len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param, wmi_avg_tx_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_avg_tx_power_region_per_antenna_chain, avg_tx_power_region_per_antenna_chain, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_AVG_TX_POWER_EVENTID);
+
+#define WMITLV_TABLE_WMI_PLIMIT_TABLE_EVENTID(id, op , buf, len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param, wmi_plimit_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_power_per_antenna_chain, tx_power_per_antenna_chain, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PLIMIT_TABLE_EVENTID);
+
 /* pdev per-vdev queue depth report event */
 #define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID(id,op,buf,len) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index cdc70a2fdc0e..ee6297d8a0fc 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1441,6 +1441,12 @@ typedef enum {
     /** WMI command to get scan cached result */
     WMI_GET_SCAN_CACHE_RESULT_CMDID,
 
+    WMI_SET_MODIFY_TX_PLIM_CMDID,
+
+    WMI_GET_AVG_TX_POWER_CMDID,
+
+    WMI_GET_TX_POWER_CALLING_CMDID,
+
 
     /*  Offload 11k related requests */
     WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD),
@@ -2646,6 +2652,12 @@ typedef enum {
     /** WMI event for FW diagnostic data sent to host */
     WMI_OPT_DP_DIAG_EVENTID,
 
+    WMI_MODIFY_TX_PLIM_EVENTID,
+
+    WMI_AVG_TX_POWER_EVENTID,
+
+    WMI_PLIMIT_TABLE_EVENTID,
+
 
     /* GPIO Event */
     WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
@@ -43935,6 +43947,9 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID);
         WMI_RETURN_STRING(WMI_NAN_DISC_SERVICE_REQ_CMDID);
         WMI_RETURN_STRING(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID);
+        WMI_RETURN_STRING(WMI_SET_MODIFY_TX_PLIM_CMDID);
+        WMI_RETURN_STRING(WMI_GET_AVG_TX_POWER_CMDID);
+        WMI_RETURN_STRING(WMI_GET_TX_POWER_CALLING_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -56053,6 +56068,35 @@ typedef struct {
     A_UINT32 tlv_header;
 } wmi_get_scan_cache_result_cmd_fixed_param;
 
+typedef enum {
+    WMI_PLIM_DIRECTION_NONE = 0,
+    WMI_PLIM_DIRECTION_INCREASE,
+    WMI_PLIM_DIRECTION_DECREASE
+} wmi_plim_direction_type;
+
+typedef struct {
+    /* WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* Requested level for future enhancement, default value shall be 1 */
+    A_UINT32 multiplier;
+    /* takes values from enum wmi_plim_direction_type */
+    A_UINT32 direction;
+} wmi_set_modify_tx_plim_cmd_fixed_param;
+
+typedef struct {
+    /* WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* Current active DSI (device state index) */
+    A_UINT32 dsi_id;
+} wmi_get_avg_tx_power_cmd_fixed_param;
+
+typedef struct {
+    /* WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* DSI index for which power limit info is to be fetched */
+    A_UINT32 dsi_id;
+} wmi_get_tx_power_calling_cmd_fixed_param;
+
 /* Element ID 61 (HT Operation) is present (see HT 7.3.2) */
 #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_GET(flags)  WMI_GET_BITS(flags, 0, 1)
 #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value)
@@ -56114,6 +56158,66 @@ typedef struct {
      */
 } wmi_scan_cache_result_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param */
+
+    A_UINT32 status; /* 0 = success, 1 = failure */
+} wmi_modify_tx_plim_event_fixed_param;
+
+typedef enum {
+    /* Invalid Chain combination */
+    WMI_POWER_REGION_INVALID    = 0,
+
+    /* Avg. tx power <= PowerLimit-backoff */
+    WMI_POWER_REGION_LOW        = 1,
+
+    /* PowerLimit-backoff < Avg. tx power <= PowerLimit */
+    WMI_POWER_REGION_MEDIUM     = 2,
+
+    /* PowerLimit < Avg. tx power <= PowerLimit+Boost */
+    WMI_POWER_REGION_HIGH       = 3,
+
+    /* Avg. tx power > PowerLimit+Boost */
+    WMI_POWER_REGION_EXTRA_HIGH = 4,
+
+} wmi_phyrf_tas_chain_power_region_type;
+
+typedef struct {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain */
+    /* Valid chain number for which chain_power_region is filled */
+    A_UINT32 chain_no;
+    A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */
+    /* takes values from enum wmi_phyrf_tas_chain_power_region_type */
+    A_UINT32 chain_power_region;
+} wmi_avg_tx_power_region_per_antenna_chain;
+
+typedef struct {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param */
+    A_UINT32  status; /* 0 = success, 1 = failure */
+    /* Exposure window over which TX power is averaged */
+    A_UINT32 time_window_in_sec;
+    /* The below TLVs follow this TLV
+     * struct wmi_avg_tx_power_region_per_antenna_chain[];
+     */
+} wmi_avg_tx_power_event_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain */
+    A_UINT32 chain_no; /* Valid chain number for which power is filled */
+    A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */
+    A_INT32 power; /* Power limit in units of 0.25 dBm */
+} wmi_tx_power_per_antenna_chain;
+
+typedef struct  {
+    A_UINT32 tlv_header;  /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param */
+    A_UINT32 status; /* 0 = success, 1 = failure */
+    A_UINT32 dsi_id; /* DSI index for which below entries are filled */
+    /* The below TLVs follow this TLV
+     * struct wmi_tx_power_per_antenna_chain[];
+     */
+} wmi_plimit_table_event_fixed_param;
+
+
 #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_GET(word32)        WMI_GET_BITS(word32, 0, 4)
 #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_SET(word32, value) WMI_SET_BITS(word32, 0, 4, value)
 #define WMI_POWER_BOOST_CAPABILITIES_POWER_BOOST_ENABLE_GET(word32)        WMI_GET_BITS(word32, 4, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4311246b96b0..31ed2096ba6b 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1774
+#define __WMI_REVISION_ 1775
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From ebb74a35fed38dd43ab19be78ef8e7e232d5d292 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 2 Jun 2026 18:01:47 -0700
Subject: [PATCH 264/290] fw-api: CL 32731178 - update fw common interface
 files

Change-Id: I6856eb39a14f535aa55394fa3876127f4d535e1d
CRs-Fixed: 3830439
---
 fw/wmi_services.h |  6 ++++++
 fw/wmi_unified.h  | 10 +++++++++-
 fw/wmi_version.h  |  2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 43b84dad12bb..c970c20720d1 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -841,6 +841,12 @@ typedef  enum  {
      */
     WMI_SERVICE_CTAS_PLIM_INDICATION_SUPPORT = 518,
 
+    /*
+     * Indicates FW supports NAN in offload mode
+     * (supplicant-based NAN offload mode architecture).
+     */
+    WMI_SERVICE_NAN_OFFLOAD_MODE_SUPPORT = 519,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ee6297d8a0fc..a2048cf1b8f7 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5680,7 +5680,9 @@ typedef struct {
                 dw_notif_lead_time: 8,
                 /* enable supplicant based NAN offload mode */
                 enable_nan_ofld_mode: 1,
-                reserved2: 23;
+                /* disable/enable temporal IOT mode */
+                enable_temporal_iot_mode: 1,
+                reserved2: 22;
         };
     };
 } wmi_resource_config;
@@ -5700,6 +5702,12 @@ typedef struct {
 #define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_SET(word32, value) \
     WMI_SET_BITS(word32, 8, 1, value)
 
+#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_GET(word32) \
+    WMI_GET_BITS(word32, 9, 1)
+#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_SET(word32, value) \
+    WMI_SET_BITS(word32, 9, 1, value)
+
+
 /*
  * WMI_NAN_DISC_COOKIE_GET / WMI_NAN_DISC_COOKIE_SET
  *
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 31ed2096ba6b..837867d7c82f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1775
+#define __WMI_REVISION_ 1776
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From dc14726a1218044dcac809d2177a03cbc74ad17c Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 2 Jun 2026 18:03:47 -0700
Subject: [PATCH 265/290] fw-api: CL 32742658 - update fw common interface
 files

Change-Id: I349dc7cd9e7d0b0a829199ae12661e7118279edf
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 118 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fec2c7616a30..447d1e0972fc 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -11566,6 +11566,23 @@ typedef struct {
     } tpcTargets;
 } htt_stats_pdev_ftm_tpccal_tlv;
 
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_TPCCAL_PDADC_NUMGAIN_GET(word) \
+    (((word) >> 0) & 0xff)
+
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_BAND_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHANNEL_GET(word) \
+    (((word) >> 8) & 0xffff)
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHAIN_GET(word) \
+    (((word) >> 24) & 0xff)
+
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_GAINIDX_GET(word) \
+    (((word) >> 0) & 0xff)
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_PDADC_GET(word) \
+    (((word) >> 8) & 0xff)
+
+#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_MEASPWR_GET(word) \
+    (((word) >> 0) & 0xffff)
 
 #define HTT_STATS_TPCCAL_PDADC_LAST_IDX_M 0x000000ff
 #define HTT_STATS_TPCCAL_PDADC_LAST_IDX_S 0
@@ -11600,6 +11617,9 @@ typedef struct {
 #define HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_PDADC_CHANNEL_M) >> \
      HTT_STATS_TPCCAL_PDADC_CHANNEL_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHANNEL_GET(_var) \
+    HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var)
 
 #define HTT_STATS_TPCCAL_PDADC_CHAIN_M 0xff000000
 #define HTT_STATS_TPCCAL_PDADC_CHAIN_S 24
@@ -11607,6 +11627,9 @@ typedef struct {
 #define HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_PDADC_CHAIN_M) >> \
      HTT_STATS_TPCCAL_PDADC_CHAIN_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHAIN_GET(_var) \
+    HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var)
 
 #define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M 0x000000ff
 #define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S 0
@@ -11614,6 +11637,9 @@ typedef struct {
 #define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M) >> \
      HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_GAININDEX_GET(_var) \
+    HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var)
 
 #define HTT_STATS_TPCCAL_RES_PDADC_VAL_M 0x0000ff00
 #define HTT_STATS_TPCCAL_RES_PDADC_VAL_S 8
@@ -11621,6 +11647,9 @@ typedef struct {
 #define HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_RES_PDADC_VAL_M) >> \
      HTT_STATS_TPCCAL_RES_PDADC_VAL_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_PDADC_GET(_var) \
+    HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var)
 
 #define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M 0x0000ffff
 #define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S 0
@@ -11628,6 +11657,10 @@ typedef struct {
 #define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) \
     (((_var) & HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M) >> \
      HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_MEASPWR_GET(_var) \
+    HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var)
+
 
 #define HTT_STATS_TPC_CAL_PDADC_BUF_LEN 3
 
@@ -13049,31 +13082,49 @@ typedef struct {
 
 #define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word) \
     ((word) & 0x0000ffff)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BANDWIDTH_MHZ_GET(word) \
+    HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word)
 #define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_SET(word, value) \
     ((word) |= ((value) & 0x0000ffff))
 
 #define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word) \
     (((word) & 0xffff0000) >> 16)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BAND_CENTER_FREQ1_GET(word) \
+    HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word)
 #define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_SET(word, value) \
     ((word) |= (((value) << 16) & 0xffff0000))
 
 #define HTT_STATS_HDS_PROF_PHY_MODE_GET(word) \
     (((word) & 0x000000ff) >> 0)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_PHYMODE_GET(word) \
+    HTT_STATS_HDS_PROF_PHY_MODE_GET(word)
 #define HTT_STATS_HDS_PROF_PHY_MODE_SET(word, value) \
     ((word) |= (((value) << 0) & 0x000000ff))
 
 #define HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word) \
     (((word) & 0x0000ff00) >> 8)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_TXCHAINMASK_GET(word) \
+    HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word)
 #define HTT_STATS_HDS_PROF_TX_CHAINMASK_SET(word, value) \
     ((word) |= (((value) << 8) & 0x0000ff00))
 
 #define HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word) \
     (((word) & 0x00ff0000) >> 16)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_RXCHAINMASK_GET(word) \
+    HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word)
 #define HTT_STATS_HDS_PROF_RX_CHAINMASK_SET(word, value) \
     ((word) |= (((value) << 16) & 0x00ff0000))
 
 #define HTT_STATS_HDS_PROF_SW_PROFILE_GET(word) \
     (((word) & 0xff000000) >> 24)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_SWPROFILE_GET(word) \
+    HTT_STATS_HDS_PROF_SW_PROFILE_GET(word)
 #define HTT_STATS_HDS_PROF_SW_PROFILE_SET(word, value) \
     ((word) |= (((value) << 24) & 0xff000000))
 
@@ -13683,6 +13734,10 @@ typedef struct {
 
 #define HTT_STATS_FTM_TIMINGSTATS_TLVTIMESTAMPCNTFILLED_GET(word) \
     (((word) >> 0) & 0xff)
+#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCMD_ENTRY_GET(word) \
+    (((word) >> 0) & 0xffff)
+#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCALTYPE_GET(word) \
+    (((word) >> 16) & 0xff)
 
 #define HTT_STATS_FTM_TIMINGSTATS_TLVCMD_ENTRY_GET(word) \
     (((word) >> 0) & 0xffff)
@@ -16709,31 +16764,49 @@ typedef struct {
 
 #define HTT_STATS_RESET_HISTORY_MHZ_GET(word) \
     ((word) & 0x0000ffff)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_MHZ_GET(word) \
+    HTT_STATS_RESET_HISTORY_MHZ_GET(word)
 #define HTT_STATS_RESET_HISTORY_MHZ_SET(word, value) \
     ((word) |= ((value) & 0x0000ffff))
 
 #define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \
     (((word) & 0xffff0000) >> 16)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \
+    HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word)
 #define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_SET(word, value) \
     ((word) |= (((value) << 16) & 0xffff0000))
 
 #define HTT_STATS_RESET_HISTORY_FLAGS_GET(word) \
     ((word) & 0x0000ffff)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_FLAGS_GET(word) \
+    HTT_STATS_RESET_HISTORY_FLAGS_GET(word)
 #define HTT_STATS_RESET_HISTORY_FLAGS_SET(word, value) \
     ((word) |= ((value) & 0x0000ffff))
 
 #define HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) \
     (((word) & 0x00ff0000) >> 16)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_PHY_ID_GET(word) \
+    HTT_STATS_RESET_HISTORY_PHY_ID_GET(word)
 #define HTT_STATS_RESET_HISTORY_PHY_ID_SET(word, value) \
     ((word) |= (((value) << 16) & 0x00ff0000))
 
 #define HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) \
     (((word) & 0xff000000) >> 24)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_SWPROFILE_GET(word) \
+    HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word)
 #define HTT_STATS_RESET_HISTORY_SWPROFILE_SET(word, value) \
     ((word) |= (((value) << 24) & 0xff000000))
 
 #define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) \
     (((word) & 0x00000001) >> 0)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_IS_HOME_CHAN_GET(word) \
+    HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word)
 #define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_SET(word, value) \
     ((word) |= (((value) << 0) & 0x00000001))
 
@@ -17104,14 +17177,29 @@ typedef struct {
 
 #define HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_FREQ_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word)
+#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_FREQ_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word)
+#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_FREQ_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word)
 #define HTT_STATS_REG_FREQ_POWER_PAIR_SET_FREQ_VALUE(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
 
 #define HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_POWER_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word)
+#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_POWER_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word)
+#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_POWER_GET(word) \
+    HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word)
 #define HTT_STATS_REG_FREQ_POWER_PAIR_SET_POWER_VALUE(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
 
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 index;
@@ -17417,6 +17505,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M) >> \
      HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_PKT_TYPE_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_PKT_TYPE, _val); \
@@ -17426,6 +17517,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_NSS_M) >> \
      HTT_STATS_WHAL_SELFGEN_NSS_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_NSS_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_NSS_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_NSS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_NSS, _val); \
@@ -17435,6 +17529,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_RATE_MCS_M) >> \
      HTT_STATS_WHAL_SELFGEN_RATE_MCS_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_RATE_MCS_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_RATE_MCS_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_RATE_MCS, _val); \
@@ -17444,6 +17541,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M) >> \
      HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_BANDWIDTH_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_BANDWIDTH, _val); \
@@ -17453,6 +17553,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M) >> \
      HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_CHAIN_MASK_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHAIN_MASK, _val); \
@@ -17462,6 +17565,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M) >> \
      HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_CHAIN_MASK_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK, _val); \
@@ -17481,6 +17587,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_M) >> \
      HTT_STATS_WHAL_SELFGEN_TX_PWR_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_TX_PWR_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR, _val); \
@@ -17490,6 +17599,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M) >> \
      HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_1_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR_1, _val); \
@@ -17499,6 +17611,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M) >> \
      HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR, _val); \
@@ -17508,6 +17623,9 @@ typedef struct {
 #define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) \
     (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M) >> \
      HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_1_GET(_var) \
+    HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var)
 #define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_SET(_var, _val) \
     do { \
         HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1, _val); \

From 7e1dddd481814e55a1148f79c445a3d21ec3a477 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Thu, 4 Jun 2026 18:04:23 -0700
Subject: [PATCH 266/290] fw-api: CL 32762973 - update fw common interface
 files

Change-Id: I4cceffdf4fadab9da40ff71a971cd133d96274b8
CRs-Fixed: 3830439
---
 fw/htt.h       |   3 +
 fw/htt_stats.h | 412 +++++++++++++++++++++++++++++++++++++++++++------
 2 files changed, 368 insertions(+), 47 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 2f41c5add0d0..a94a3138830f 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -940,6 +940,9 @@ typedef enum {
     HTT_STATS_NPCA_TAG                              = 260, /* htt_stats_npca_tlv */
     HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TAG      = 261, /* htt_stats_sched_txq_tx_mode_simplified_tlv */
     HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TAG          = 262, /* htt_stats_sched_txq_tx_mode_winner_tlv */
+    HTT_STATS_DFS_RADAR_HISTORY_TAG                 = 263, /* htt_stats_dfs_radar_history_tlv */
+    HTT_STATS_DFS_INI_TAG                           = 264, /* htt_stats_dfs_ini_tlv */
+    HTT_STATS_DFS_IPC_RING_TAG                      = 265, /* htt_stats_dfs_ipc_ring_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 447d1e0972fc..3b84a87e4c5e 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -927,6 +927,12 @@ enum htt_dbg_ext_stats_type {
      *     RESP Tags:
      *       - htt_stats_ctl_tlv
      *       - htt_stats_enhanced_ctl_tlv
+     * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_DFS):
+     *     no params
+     *     RESP Tags:
+     *       - htt_stats_dfs_radar_history_tlv
+     *       - htt_stats_dfs_ini_tlv
+     *       - htt_stats_dfs_ipc_ring_tlv
      */
     HTT_DBG_EXT_STATS_REGULATORY = 83,
 
@@ -6376,7 +6382,34 @@ typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv;
     (((word) >> 0) & 0xff)
 
 #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0)  & 0xffff)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_RX_RING_STATS_SW2RXDMA_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_RXDMA2REO_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REO2SW1_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REO2SW4_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_MAX_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword)
+
 #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff)
+/* provide alias macros that use preferred naming convention */
+#define HTT_STATS_RX_RING_STATS_SW2RXDMA_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_RXDMA2REO_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REO2SW1_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REO2SW4_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
+#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_CURR_NUM_ENTRIES_GET(dword) \
+    HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword)
 
 /* Rx debug info for status rings */
 typedef struct {
@@ -6386,12 +6419,54 @@ typedef struct {
      *                  (size of the ring in terms of entries)
      * BIT [16 : 31] :- current number of entries occupied in respective ring
      */
-    A_UINT32 entry_status_sw2rxdma;
-    A_UINT32 entry_status_rxdma2reo;
-    A_UINT32 entry_status_reo2sw1;
-    A_UINT32 entry_status_reo2sw4;
-    A_UINT32 entry_status_refillringipa;
-    A_UINT32 entry_status_refillringhost;
+    union {
+        A_UINT32 entry_status_sw2rxdma;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } sw2rxdma;
+    };
+    union {
+        A_UINT32 entry_status_rxdma2reo;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } rxdma2reo;
+    };
+    union {
+        A_UINT32 entry_status_reo2sw1;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } reo2sw1;
+    };
+    union {
+        A_UINT32 entry_status_reo2sw4;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } reo2sw4;
+    };
+    union {
+        A_UINT32 entry_status_refillringipa;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } refillringipa;
+    };
+    union {
+        A_UINT32 entry_status_refillringhost;
+        struct {
+            A_UINT32
+                max_num_entries:  16,
+                curr_num_entries: 16;
+        } refillringhost;
+    };
     /** datarate - Moving Average of Number of Entries */
     A_UINT32 datarate_refillringipa;
     A_UINT32 datarate_refillringhost;
@@ -12154,7 +12229,7 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv;
      HTT_STATS_CURR_EANI_MODE_S)
 /* provide alias macro that uses preferred naming convention */
 #define HTT_STATS_PHY_STATS_CUREANIMODE_GET(_var) \
-    HTT_STATS_CURR_EANI_MODE_GET(_var) 
+    HTT_STATS_CURR_EANI_MODE_GET(_var)
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -12303,22 +12378,8 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTALCAL_S)); \
     } while (0)
 
-#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010
-#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4
-#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \
-    (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \
-     HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)
-/* provide alias macro that uses preferred naming convention */
-#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GOPC_GET(_var) \
-    HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var)
-#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \
-    do { \
-        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \
-        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \
-    } while (0)
-
-#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020
-#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5
+#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000010
+#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 4
 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)
@@ -12331,22 +12392,22 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)); \
     } while (0)
 
-#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040
-#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6
-#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \
-    (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \
-     HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)
+#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000020
+#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 5
+#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \
+    (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \
+     HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)
 /* provide alias macro that uses preferred naming convention */
-#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GOPC_GET(_var) \
-    HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var)
-#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var)
+#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \
     do { \
-        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \
-        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \
     } while (0)
 
-#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080
-#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7
+#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000040
+#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 6
 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)
@@ -12359,21 +12420,22 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)); \
     } while (0)
 
-#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100
-#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8
-#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \
-    (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \
-     HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)
+#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000080
+#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 7
+#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \
+    (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \
+     HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)
 /* provide alias macro that uses preferred naming convention */
-#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GOPC_GET(_var) \
-    HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var)
-#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var)
+#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \
     do { \
-        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \
-        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)); \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \
     } while (0)
-#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200
-#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9
+
+#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000100
+#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 8
 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \
     (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \
      HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)
@@ -12386,6 +12448,20 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv;
         ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)); \
     } while (0)
 
+#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000200
+#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 9
+#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \
+    (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \
+     HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GOPC_GET(_var) \
+    HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var)
+#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)); \
+    } while (0)
+
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10
 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \
@@ -16817,6 +16893,7 @@ typedef enum {
     HTT_STATS_REGULATORY_SUBTYPE_REGDB = 0,
     HTT_STATS_REGULATORY_SUBTYPE_6GHZ  = 1,
     HTT_STATS_REGULATORY_SUBTYPE_CTL   = 2,
+    HTT_STATS_REGULATORY_SUBTYPE_DFS   = 3,
     HTT_STATS_REGULATORY_SUBTYPE_MAX
 } htt_stats_regulatory_subtype_t;
 
@@ -17402,6 +17479,247 @@ typedef struct {
     HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value))
 
 
+#define HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES  5
+
+/**
+ * @brief TLV structure for wifistats 83 (radar history)
+ * This structure holds the last 5 radar history detected.
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    struct {
+        union {
+            A_UINT32 freq_det_info;
+            struct {
+                A_UINT32 chan_freq:16, /* MHz units */
+                detector_id:8,
+                is_chirp:1,    /* Chirp radar pulse detected */
+                rsvd1:7;
+            };
+        };
+        union {
+            A_UINT32 rssi_pulse_info;
+            struct {
+                A_UINT32 rf_pulseid:16,
+                radar_rssi_dbm:8,
+                rsvd2:8;
+            };
+        };
+        union {
+            A_UINT32 domain_type_info;
+            struct {
+                A_UINT32 domain:8,
+                type:8,
+                rf_radar_type:8,
+                rsvd3:8;
+            };
+        };
+        union {
+            A_UINT32 sidx_freq_info;
+            struct {
+                A_UINT32 sidx:16,
+                freq_offset:16;
+            };
+        };
+        union {
+            A_UINT32 dur_info;
+            struct {
+                A_UINT32 rf_mindur:16,   /* us */
+                rf_maxdur:16;   /* us */
+            };
+        };
+        union {
+            A_UINT32 threshold_info;
+            struct {
+                A_UINT32 rf_threshold:16, /* units = dBm */
+                rsvd4:16;
+            };
+        };
+        union {
+            A_UINT32 pri_info;
+            struct {
+                A_UINT32 rf_minpri:16,   /* us */
+                rf_maxpri:16;   /* us */
+            };
+        };
+    } radar_entry_stats[HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES];
+    A_UINT32 idx;      /* next write position */
+    A_UINT32 count;    /* valid entries in buffer */
+} htt_stats_dfs_radar_history_tlv;
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * freq_det_info (word 0)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_GET(word) \
+    HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_GET(word) \
+    HTT_STATS_GET_FIELD(0x01000000, 24, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x01000000, 24, (word), (value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * rssi_pulse_info (word 1)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_GET(word) \
+    ((A_INT8)HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (A_UINT8)(value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * domain_type_info (word 2)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_GET(word) \
+    HTT_STATS_GET_FIELD(0x000000FF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FF00, 8, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_GET(word) \
+    HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * sidx_freq_info (word 3)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_GET(word) \
+    ((A_INT16)HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (A_UINT16)(value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_GET(word) \
+    ((A_INT16)HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_SET(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (A_UINT16)(value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * dur_info (word 4)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_GET(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_SET(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * threshold_info (word 5)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+/*
+ * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats
+ * pri_info (word 6)
+ */
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_GET(word) \
+    HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_SET(word, value) \
+    HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value))
+
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_GET(word) \
+    HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
+#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_SET(word, value) \
+    HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
+
+/*
+ * Sign-extend helper for signed bitfields in DFS radar entries.
+ * Used for radar_rssi_dbm (8-bit), sidx (16-bit), freq_offset (16-bit).
+ */
+#define HTT_STATS_SIGN_EXT(val, nbits) \
+    (((val) & (1u << ((nbits)-1))) ? \
+     ((val) | (~0u << (nbits))) : (val))
+
+/*
+ * Indices into htt_stats_dfs_ini_tlv.reg_val[]
+ * (same order as wfax_dfs_common[])
+ */
+enum htt_stats_dfs_ini_reg_idx {
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_L    = 0, /* offset 0xBC0 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_U  = 1, /* offset 0xBB4 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_L  = 2, /* offset 0xBF8 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_U    = 3, /* offset 0xBC4 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_U  = 4, /* offset 0xBFC */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_0_L = 5, /* offset 0xBD8 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL1_U   = 6, /* offset 0xBD4 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_L = 7, /* offset 0xBE0 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_L  = 8, /* offset 0xBB0 */
+    HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_U = 9, /* offset 0xBE4 */
+
+    HTT_STATS_DFS_INI_NUM_REGS = 10
+};
+
+
+/*
+ * htt_stats_dfs_ini_tlv - DFS common register
+ *
+ * Captures current live values of the 10 wfax_dfs_common HW registers.
+ * reg_val[i]:  current value read from hardware
+ *
+ * Use enum htt_stats_dfs_ini_reg_idx for reg_val[] index interpretation.
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 reg_val[HTT_STATS_DFS_INI_NUM_REGS];
+} htt_stats_dfs_ini_tlv;
+
+
+/* ======================= End DFS Channel Register Snapshot TLV ========== } */
+
+/* ======================= DFS IPC Ring Stats TLV ========================= {
+ * Head/tail index state for the 3 DFS IPC rings read at stats query time.
+ * Use enum htt_stats_dfs_ipc_ring_idx for ipc_ring_stats[] index
+ * interpretation.
+ */
+
+/* Indices into htt_stats_dfs_ipc_ring_tlv.ipc_ring_stats[] */
+enum htt_stats_dfs_ipc_ring_idx {
+    HTT_STATS_DFS_IPC_RING_DFS0 = 0, /* IPC_DFS0_RINGID (2) */
+    HTT_STATS_DFS_IPC_RING_DFS1 = 1, /* IPC_DFS1_RINGID (3) */
+    HTT_STATS_DFS_IPC_RING_DFS2 = 2, /* IPC_DFS2_RINGID (4) */
+
+    HTT_STATS_DFS_IPC_RING_COUNT = 3 /* DFS0, DFS1, DFS2 */
+};
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    struct {
+        A_UINT32 head_idx;
+        A_UINT32 shadow_head_idx;
+        A_UINT32 tail_idx;
+        A_UINT32 shadow_tail_idx;
+    } ipc_ring_stats[HTT_STATS_DFS_IPC_RING_COUNT];
+} htt_stats_dfs_ipc_ring_tlv;
+
+
 /*======================= End Regulatory stats ==================== } */
 
 /*

From c2adf7dc3fbf9c4d71742f0b49ad577cccb08b03 Mon Sep 17 00:00:00 2001
From: Santosh Sakore <ssakore@qti.qualcomm.com>
Date: Mon, 18 May 2026 16:15:14 +0530
Subject: [PATCH 267/290] msm:adsprpc: Fix UAF of ctx->perf in async invoke
 perf counter

In async invoke path, fastrpc_update_invoke_count is called at
invoke_end with perf_counter pointing into ctx->perf.
After fastrpc_invoke_send returns, the async response thread may
call context_free(ctx), freeing ctx->perf before invoke_end.
This causes a use-after-free write that corrupts the SLUB
freelist and may trigger a kernel panic on next allocation.
Fix by storing submission timestamp in ctx->invoke_start_time
before send, removing unsafe call from invoke_end, and moving
fastrpc_update_invoke_count to fastrpc_wait_on_async_queue.
There, ctx is guaranteed valid before context_free. This also
aligns async perf->invoke with sync, measuring full end-to-end
latency instead of submission-only latency.

Acked-by: Sharad Kumar <sharku@qti.qualcomm.com>
Change-Id: I91f2a2479b508fde2fe7c26783ee56dc9391eb17
Signed-off-by: Santosh Sakore <ssakore@qti.qualcomm.com>
---
 drivers/char/adsprpc.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index 39bdf863b597..ee38e227a93a 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
 /* Uncomment this block to log an error on every VERIFY failure */
@@ -444,6 +444,7 @@ struct smq_invoke_ctx {
 	uint32_t sc_interrupted;
 	struct fastrpc_file *fl_interrupted;
 	uint32_t handle_interrupted;
+	struct timespec64 invoke_start_time;  /* submission timestamp for async perf */
 };
 
 struct fastrpc_ctx_lst {
@@ -3362,6 +3363,15 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode,
 	inv_args(ctx);
 	PERF_END);
 
+	/*
+	 * Store submission timestamp in ctx before sending to DSP.
+	 * For async invokes, perf->invoke will be updated in the collector
+	 * thread (fastrpc_wait_on_async_queue) where ctx is still valid,
+	 * measuring full end-to-end latency consistent with the sync path.
+	 */
+	if (fl->profile && isasyncinvoke)
+		ctx->invoke_start_time = invoket;
+
 	PERF(fl->profile, GET_COUNTER(perf_counter, PERF_LINK),
 	VERIFY(err, 0 == (err = fastrpc_invoke_send(ctx,
 		kernel, invoke->handle)));
@@ -3423,9 +3433,6 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode,
 		err = -ECONNRESET;
 
 invoke_end:
-	if (fl->profile && !interrupted && isasyncinvoke)
-		fastrpc_update_invoke_count(invoke->handle, perf_counter,
-						&invoket);
 	return err;
 }
 
@@ -3495,6 +3502,15 @@ bail:
 		async_res->result = ierr;
 	if (ctx) {
 		if (fl->profile && ctx->perf && ctx->handle > FASTRPC_STATIC_HANDLE_MAX) {
+			/*
+			 * Update invoke/count perf counters here where ctx->perf is
+			 * guaranteed valid. This measures full end-to-end async latency
+			 * (submit → DSP → collect), consistent with the sync path.
+			 * invoke_start_time was stored in ctx before fastrpc_invoke_send
+			 * in fastrpc_internal_invoke.
+			 */
+			fastrpc_update_invoke_count(ctx->handle, perf_counter,
+				&ctx->invoke_start_time);
 			trace_fastrpc_perf_counters(ctx->handle, ctx->sc,
 			ctx->perf->count, ctx->perf->flush, ctx->perf->map,
 			ctx->perf->copy, ctx->perf->link, ctx->perf->getargs,

From 1d7a79622ddbbe4895d7566418a62362adce0fa0 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 6 Jun 2026 18:04:12 -0700
Subject: [PATCH 268/290] fw-api: CL 32796472 - update fw common interface
 files

Change-Id: I3a4c105c93c0840e1b06abcdf9bc23f121ba4450
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 14 +++++++++++++-
 fw/wmi_version.h |  2 +-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index a2048cf1b8f7..6c014a0cef49 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5523,8 +5523,15 @@ typedef struct {
      *      Refer to the below definitions of
      *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET and _SET
      *      macros.
+     *  Bit 26
+     *      This bit will be set by host to inform FW that the rx management
+     *      path directly to the host is enabled, so the FW need not forward
+     *      rx mgmt frames to the host.
+     *      Refer to the below definitions of
+     *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET and
+     *      _SET macros.
      *
-     *  Bits 31:26 - Reserved
+     *  Bits 31:27 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -6193,6 +6200,11 @@ typedef struct {
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_SET(host_service_flags, value) \
     WMI_SET_BITS(host_service_flags, 25, 1, value)
 
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET(host_service_flags) \
+    WMI_GET_BITS(host_service_flags, 26, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_SET(host_service_flags, value) \
+    WMI_SET_BITS(host_service_flags, 26, 1, value)
+
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 837867d7c82f..0b7e383b709e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1776
+#define __WMI_REVISION_ 1777
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 328cfa7dae2b75d2c5cb2a481c3cf1c247f1b722 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sat, 6 Jun 2026 18:06:21 -0700
Subject: [PATCH 269/290] fw-api: CL 32796759 - update fw common interface
 files

Change-Id: Ie60e82c71b2447b006a7d031661248e75490730a
CRs-Fixed: 3830439
---
 fw/htc_services.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/fw/htc_services.h b/fw/htc_services.h
index 73eb52c32911..3e4fca244b1e 100644
--- a/fw/htc_services.h
+++ b/fw/htc_services.h
@@ -64,7 +64,9 @@ typedef enum {
 /* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */
 #define WMI_CONTROL_SVC_WMAC3  MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9)
 #define WMI_CONTROL_SVC_WMAC4  MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10)
-#define WMI_MAX_SERVICES  11
+/* SMD high prio service - common for all macs */
+#define WMI_CONTROL_SMD_SVC  MAKE_SERVICE_ID(WMI_SERVICE_GROUP,11)
+#define WMI_MAX_SERVICES  12
 
 #define NMI_CONTROL_SVC   MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
 #define NMI_DATA_SVC      MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
@@ -98,6 +100,13 @@ typedef enum {
  */
 #define HTT_DATA4_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,3)
 
+/* H2T - Telemetry channel */
+#define HTT_TELEMETRY_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,4)
+/* T2H - Telemetry channel 1 */
+#define HTT_TELEMETRY1_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,5)
+/* T2H - Telemetry channel 2 */
+#define HTT_TELEMETRY2_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,6)
+
 /* raw stream service (i.e. flash, tcmd, calibration apps) */
 #define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
 

From 87b3e2425eafb3fe69efb4049387d172cfde0fcc Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 7 Jun 2026 18:01:41 -0700
Subject: [PATCH 270/290] fw-api: CL 32798720 - update fw common interface
 files

Change-Id: If7511eee9deb2e3b966ebb156163e2b565f1a395
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 30 +++++++++++++++++++++++++++++-
 fw/wmi_version.h |  2 +-
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 6c014a0cef49..b36235063ebc 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -28017,6 +28017,22 @@ typedef struct {
     A_UINT32  req_type;
 } wmi_aggr_state_trig_event_fixed_param;
 
+/*
+ * WMI_KEY_FIPS_STATUS
+ *
+ * Reported to the host in WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID via
+ * bits[4:5] of key_flags. Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET macros.
+ */
+typedef enum {
+    WMI_KEY_FIPS_NOT_APPROVED = 1,
+    WMI_KEY_FIPS_APPROVED     = 2,
+} WMI_KEY_FIPS_STATUS;
+
+#define WMI_KEY_FLAGS_FIPS_COMPLIANT_GET(key_flags) \
+    WMI_GET_BITS(key_flags, 4, 2)
+#define WMI_KEY_FLAGS_FIPS_COMPLIANT_SET(key_flags, val) \
+    WMI_SET_BITS(key_flags, 4, 2, val)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
@@ -28025,7 +28041,19 @@ typedef struct {
     wmi_mac_addr peer_macaddr;
     /** key index */
     A_UINT32 key_ix;
-    /** key flags */
+    /** key flags — bit definitions (see KEY_USAGE enum in wmi.h):
+     *  bit[0]:    key usage type
+     *             0 = PAIRWISE_USAGE — unicast/pairwise key
+     *             1 = GROUP_USAGE    — broadcast/multicast group key
+     *  bit[1]:    TX_USAGE (0x02) — default Tx key (static WEP only)
+     *  bit[2]:    PMK_USAGE (0x04) — PMK cache entry
+     *  bit[3]:    LTF_USAGE (0x08) — LTF key seed
+     *  bits[4:5]: FIPS compliance status (WMI_KEY_FIPS_STATUS enum)
+     *             1 = WMI_KEY_FIPS_NOT_APPROVED (WEP, TKIP, WAPI)
+     *             2 = WMI_KEY_FIPS_APPROVED     (AES-CCM/GCM/CMAC/GMAC)
+     *             Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET to access.
+     *  bits[6:31]: reserved
+     */
     A_UINT32 key_flags;
     /** Event status */
     A_UINT32 status;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0b7e383b709e..61e845021657 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1777
+#define __WMI_REVISION_ 1778
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From b20925de80a7b5fdd1b248b5c90902227fcbffd2 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Tue, 9 Jun 2026 18:01:48 -0700
Subject: [PATCH 271/290] fw-api: CL 32817922 - update fw common interface
 files

Change-Id: I6125a2de82bfa841ad03ba8cc8cd92e08430332b
CRs-Fixed: 3830439
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b36235063ebc..9a99113fd5aa 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -57288,6 +57288,8 @@ typedef struct {
                      offset: 16;
         };
     };
+    A_UINT32 tx_buffer_size; /* tx block ack window size */
+    A_UINT32 rx_buffer_size; /* rx block ack window size */
 } wmi_smd_roam_peer_tid_info;
 
 #define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROLE(cmd_flags)                      WMI_GET_BITS(mlo_flags, 0, 4)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 61e845021657..a252ae15c4ef 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1778
+#define __WMI_REVISION_ 1779
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 9c3c5d8625f5ab259ebbdcea04745af610e1e59d Mon Sep 17 00:00:00 2001
From: Aasir Rasheed <arasheed@qti.qualcomm.com>
Date: Wed, 10 Jun 2026 12:27:59 +0530
Subject: [PATCH 272/290] qcacld-3.0: Update phymode along with ch_width update
 to FW
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

AP sends "Operating Mode Notification" IE contains max supported
channel width indication (ap operating channel bandwidth) via
beacon/probe response/association/re-association response frame.
After sending OMN IE to DUT, AP expects DUT should do Tx/Rx of
data packet on ap operating channel bandwidth.

Due a recent change in FW (via CR/3701633), FW combined BW and
PHYMODE update requests into single message to avoid race condition
and assert in FW. It means whenever host updates ch_width to FW,
should also update corresponding phymode immediately via same
command WMI_PEER_SET_PARAM_CMDID with param id WMI_HOST_PEER_PHYMODE.

Currently on detecting OMN IE in any of above frame,
host sends WMI_PEER_SET_PARAM_CMDID command only once with
param id WMI_HOST_PEER_CHWIDTH to update ch_width only with
expectation “FW should use same ch_width for further Tx/Rx
of data packet”. But FW ignoring only ch_width updates (without
followed by phymode update), this results DUT fails to do Tx/Rx
of data packet on ch_width present in OMN IE.

Fix is to make sure on detection of OMN IE (contains valid ch_width)
in above frame(s), host should send WMI_PEER_SET_PARAM_CMDID command
two times to FW to update ch_width and corresponding phymode.

Change-Id: Ic23205bb6c164b1bcb9c183d0f7818b082b84583
CRs-Fixed: 3734683
---
 core/wma/src/wma_mgmt.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/core/wma/src/wma_mgmt.c b/core/wma/src/wma_mgmt.c
index e6136508c682..44e28b904b3a 100644
--- a/core/wma/src/wma_mgmt.c
+++ b/core/wma/src/wma_mgmt.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022, 2026 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -2732,6 +2732,10 @@ void wma_process_update_opmode(tp_wma_handle wma_handle,
 	wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac,
 			   WMI_PEER_CHWIDTH, update_vht_opmode->opMode,
 			   update_vht_opmode->smesessionId);
+
+	wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac,
+			   WMI_HOST_PEER_PHYMODE,
+			   fw_phymode, update_vht_opmode->smesessionId);
 }
 
 /**

From 2c47becdaf072266915bd9438620c060a6dc841d Mon Sep 17 00:00:00 2001
From: Abhishek Singh <absingh@qti.qualcomm.com>
Date: Wed, 11 Sep 2024 14:33:24 +0530
Subject: [PATCH 273/290] qcacld-3.0: Avoid phymode and puncture mismatch

Host semd wmi as following order after CSA received/vdev restart and
before vdev up, old puncture bitmap mismatched with new phy mode lead to
F/W assert.

1.	WMI PEER PHY MODE
2.	WMI PEER BW

To fix it, swap order as following
1.	WMI PEER BW
2.	WMI PEER PHY MODE

Change-Id: I1ae3e5093cb45520be0f50ffb31fa7386201340b
CRs-Fixed: 3650797
---
 core/wma/src/wma_dev_if.c | 6 +++---
 core/wma/src/wma_mgmt.c   | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/core/wma/src/wma_dev_if.c b/core/wma/src/wma_dev_if.c
index 15f3c657a065..4d045b27df28 100644
--- a/core/wma/src/wma_dev_if.c
+++ b/core/wma/src/wma_dev_if.c
@@ -943,14 +943,14 @@ static void wma_peer_send_phymode(struct wlan_objmgr_vdev *vdev,
 	fw_phymode = wma_host_to_fw_phymode(new_phymode);
 	vdev_id = wlan_vdev_get_id(vdev);
 
-	wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE,
-			   fw_phymode, vdev_id);
-
 	max_ch_width_supported =
 		wmi_get_ch_width_from_phy_mode(wma->wmi_handle, fw_phymode);
 	wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_CHWIDTH,
 			   max_ch_width_supported, vdev_id);
 
+	wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE,
+			   fw_phymode, vdev_id);
+
 	wma_debug("FW phymode %d old phymode %d new phymode %d bw %d macaddr "QDF_MAC_ADDR_FMT,
 		  fw_phymode, old_peer_phymode, new_phymode,
 		  max_ch_width_supported, QDF_MAC_ADDR_REF(peer_mac_addr));
diff --git a/core/wma/src/wma_mgmt.c b/core/wma/src/wma_mgmt.c
index 44e28b904b3a..1eac8fcc7907 100644
--- a/core/wma/src/wma_mgmt.c
+++ b/core/wma/src/wma_mgmt.c
@@ -2734,7 +2734,7 @@ void wma_process_update_opmode(tp_wma_handle wma_handle,
 			   update_vht_opmode->smesessionId);
 
 	wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac,
-			   WMI_HOST_PEER_PHYMODE,
+			   WMI_PEER_PHYMODE,
 			   fw_phymode, update_vht_opmode->smesessionId);
 }
 

From 13d4d7dd0ead133ad6f8818a399f746e4438b286 Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Wed, 10 Jun 2026 18:04:25 -0700
Subject: [PATCH 274/290] fw-api: CL 32835676 - update fw common interface
 files

Change-Id: Icd75f09dd3d08b8379bd78b9f39fbc04348870d8
CRs-Fixed: 3830439
---
 fw/wmi_tlv_defs.h | 22 ++++++++++++++
 fw/wmi_unified.h  | 76 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 99 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index aeff9c6e8d85..05e4a9aaa6c5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1656,6 +1656,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain,
     WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain,
+    WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2272,6 +2274,7 @@ typedef enum {
     OP(WMI_SET_MODIFY_TX_PLIM_CMDID) \
     OP(WMI_GET_AVG_TX_POWER_CMDID) \
     OP(WMI_GET_TX_POWER_CALLING_CMDID) \
+    OP(WMI_ATHDIAG_READ_WRITE_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -2649,6 +2652,7 @@ typedef enum {
     OP(WMI_MODIFY_TX_PLIM_EVENTID) \
     OP(WMI_AVG_TX_POWER_EVENTID) \
     OP(WMI_PLIMIT_TABLE_EVENTID) \
+    OP(WMI_ATHDIAG_READ_WRITE_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -6665,6 +6669,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_CANCEL_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID);
 
+/* Athdiag read/write command: fixed_param + optional write data TLV */
+#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_CMDID(id, op, buf, len) \
+    WMITLV_ELEM(id, op, buf, len, \
+        WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param, \
+        wmi_athdiag_read_write_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id, op, buf, len, \
+        WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
@@ -9146,6 +9159,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REPORT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_chan_hop_slot_status, slot_status, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID);
 
+/* Athdiag read/write event: fixed_param + optional read data TLV */
+#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_EVENTID(id, op, buf, len) \
+    WMITLV_ELEM(id, op, buf, len, \
+        WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param, \
+        wmi_athdiag_read_write_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id, op, buf, len, \
+        WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 9a99113fd5aa..f42670d89a8d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1447,6 +1447,9 @@ typedef enum {
 
     WMI_GET_TX_POWER_CALLING_CMDID,
 
+    /** WMI command for athdiag memory/register read or write */
+    WMI_ATHDIAG_READ_WRITE_CMDID,
+
 
     /*  Offload 11k related requests */
     WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD),
@@ -2658,6 +2661,9 @@ typedef enum {
 
     WMI_PLIMIT_TABLE_EVENTID,
 
+    /** WMI event to deliver athdiag read data or write completion status */
+    WMI_ATHDIAG_READ_WRITE_EVENTID,
+
 
     /* GPIO Event */
     WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
@@ -43998,6 +44004,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_SET_MODIFY_TX_PLIM_CMDID);
         WMI_RETURN_STRING(WMI_GET_AVG_TX_POWER_CMDID);
         WMI_RETURN_STRING(WMI_GET_TX_POWER_CALLING_CMDID);
+        WMI_RETURN_STRING(WMI_ATHDIAG_READ_WRITE_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -58190,6 +58197,75 @@ typedef struct {
      */
 } wmi_rtt_peer_meas_report_event_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param */
+    A_UINT32 tlv_header;
+    /* register offset to read or write using ath diag */
+    A_UINT32 offset;
+    /**
+     * Number of bytes to read from or write to 'offset'.
+     *
+     * For a read:  FW returns exactly 'data_length' bytes in the event.
+     * For a write: Host sends exactly 'data_length' bytes in the data TLV.
+     */
+    A_UINT32 data_length;
+    /**
+     * mem_type:
+     * Indicates the type of memory being accessed.
+     */
+    A_UINT32 mem_type;
+    /**
+     * is_write:
+     * Distinguishes between a read and a write operation.
+     *
+     *   0 = READ   FW reads 'data_length' bytes from 'offset'.
+     *               No data TLV is appended to this command.
+     *
+     *   1 = WRITE  FW writes 'data_length' bytes to 'offset'.
+     *               A WMITLV_TAG_ARRAY_BYTE TLV with the write payload
+     *               is appended to this command.
+     */
+    A_UINT32 is_write;
+} wmi_athdiag_read_write_cmd_fixed_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param */
+    A_UINT32 tlv_header;
+    /**
+     * Number of bytes to read from or write to 'offset'.
+     *
+     * For a read:  FW returns exactly 'data_length' bytes in the event.
+     * For a write: Host sends exactly 'data_length' bytes in the data TLV.
+     */
+    A_UINT32 data_length;
+    /**
+     * status:
+     * Result of the read or write operation performed by FW.
+     *
+     *   0        = Success  operation completed without error.
+     *   non-zero = Failure  FW-defined error codes.
+     */
+    A_UINT32 status;
+    /**
+     * is_write:
+     * Echoed back from the corresponding WMI_ATHDIAG_READ_WRITE_CMDID.
+     *
+     *   0 = READ  response  data TLV with 'data_length' bytes follows
+     *                        (only when status == 0)
+     *   1 = WRITE response  no data TLV appended; check 'status' only
+     */
+    A_UINT32 is_write;
+    /*
+     * This fixed_param TLV is followed by the following TLVs:
+     *   - A_UINT8 data[] (WMITLV_TAG_ARRAY_BYTE)
+     *     For READ  response (is_write == 0): read data, data_length bytes.
+     *                                         Present only when status == 0.
+     *     For WRITE response (is_write == 1): not present.
+     */
+} wmi_athdiag_read_write_event_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a252ae15c4ef..7cabd871a946 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1779
+#define __WMI_REVISION_ 1780
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From e222d053fdd823c7fd9e685c392da01ad8d8f4ed Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 12 Jun 2026 18:01:46 -0700
Subject: [PATCH 275/290] fw-api: CL 32860532 - update fw common interface
 files

Change-Id: I700caff11fd0f0d5a9db59e38f9c7bd03db8682a
CRs-Fixed: 3830439
---
 fw/htt.h       |   2 +
 fw/htt_stats.h | 987 ++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 987 insertions(+), 2 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index a94a3138830f..7234768e9b81 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -943,6 +943,8 @@ typedef enum {
     HTT_STATS_DFS_RADAR_HISTORY_TAG                 = 263, /* htt_stats_dfs_radar_history_tlv */
     HTT_STATS_DFS_INI_TAG                           = 264, /* htt_stats_dfs_ini_tlv */
     HTT_STATS_DFS_IPC_RING_TAG                      = 265, /* htt_stats_dfs_ipc_ring_tlv */
+    HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_TAG            = 266, /* htt_stats_phy_dpd_debug_chain_v1_tlv */
+    HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TAG            = 267, /* htt_stats_phy_tpc_debug_chain_v1_tlv */
 
     HTT_STATS_MAX_TAG,
 } htt_stats_tlv_tag_t;
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 3b84a87e4c5e..2ed4422436b2 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -956,6 +956,19 @@ enum htt_dbg_ext_stats_type {
 
     HTT_DBG_EXT_STATS_NPCA = 86,
 
+    /** HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG
+     * PARAMS:
+     *   - config_param0: subtype: htt_stats_phy_dpd_tpc_debug_subtype_t
+     *                    0 = DPD debug, 1 = TPC debug
+     *   - config_param1: chain bitmask (0 = default to chain 0 only)
+     * RESP MSG:
+     *   if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD):
+     *     - htt_stats_phy_dpd_debug_chain_v1_tlv (one per requested chain)
+     *   if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC):
+     *     - htt_stats_phy_tpc_debug_chain_v1_tlv (one per requested chain)
+     */
+    HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG = 87,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -17383,7 +17396,7 @@ typedef struct {
 #define HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) \
     HTT_STATS_GET_FIELD(0xFFFF, 0, (word))
 /* provide alias macro that uses preferred naming convention */
-#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OFFSET_GET(word) \
+#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_OFFSET_GET(word) \
     HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word)
 #define HTT_STATS_REG_6G_SET_OOBE_LIMIT_OFFSET(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value))
@@ -17391,7 +17404,7 @@ typedef struct {
 #define HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) \
     HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))
 /* provide alias macro that uses preferred naming convention */
-#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_PSD_GET(word) \
+#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_PSD_GET(word) \
     HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word)
 #define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \
     HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value))
@@ -18106,4 +18119,974 @@ typedef struct {
 } htt_stats_npca_tlv;
 
 
+/*===================== Start PHY DPD/TPC Debug stats ==================== { */
+
+typedef enum {
+    HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD = 0,
+    HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC = 1,
+    HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_MAX
+} htt_stats_phy_dpd_tpc_debug_subtype_t;
+
+/*
+ * htt_stats_phy_dpd_debug_params_v1
+ * Per-table DPD debug parameters. All fields packed into A_UINT32 words.
+ *
+ * Word 0: dpd_out_nmse_x10        (signed 32-bit, 1/10 dB units)
+ * Word 1: pa_max_avg_tx           (unsigned 32-bit, dBm units)
+ * Word 2: dpd_training_cnt        (unsigned 32-bit)
+ * Word 3: dpd_scaling             (unsigned 32-bit)
+ * Word 4: BIT[15:0]  dpd_training_power_db8 (signed 16-bit, 1/8 dB units)
+ *         BIT[31:16] dpd_out_sq             (unsigned 16-bit)
+ * Word 5: BIT[ 7:0]  dpd_state
+ *         BIT[15:8]  dpd_in_glut
+ *         BIT[23:16] dpd_in_tx_gain
+ *         BIT[31:24] dpd_out_train_dac_gain (signed 8-bit)
+ * Word 6: BIT[ 7:0]  dpd_in_gc (signed 8-bit)
+ *         BIT[15:8]  dpd_out_sq_idx
+ *         BIT[23:16] dpd_out_train_rx_gain_idx
+ *         BIT[31:24] dpd_in_kernel_sel
+ */
+typedef struct {
+    A_INT32  dpd_out_nmse_x10;
+    A_UINT32 pa_max_avg_tx;
+    A_UINT32 dpd_training_cnt;
+    A_UINT32 dpd_scaling;
+    union {
+        A_UINT32 dpd_training_power_db8__dpd_out_sq;
+        struct {
+            A_UINT32
+                dpd_training_power_db8: 16,
+                dpd_out_sq:             16;
+        };
+    };
+    union {
+        A_UINT32 dpd_state__dpd_in_glut__dpd_in_tx_gain__dpd_out_train_dac_gain;
+        struct {
+            A_UINT32
+                dpd_state:              8,
+                dpd_in_glut:            8,
+                dpd_in_tx_gain:         8,
+                dpd_out_train_dac_gain: 8;
+        };
+    };
+    union {
+        A_UINT32 dpd_in_gc__dpd_out_sq_idx__dpd_out_train_rx_gain_idx__dpd_in_kernel_sel;
+        struct {
+            A_UINT32
+                dpd_in_gc:                 8,
+                dpd_out_sq_idx:            8,
+                dpd_out_train_rx_gain_idx: 8,
+                dpd_in_kernel_sel:         8;
+        };
+    };
+} htt_stats_phy_dpd_debug_params_v1;
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M  0x0000ffff
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S  0
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M              0xffff0000
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S              16
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M               0x000000ff
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S               0
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M             0x0000ff00
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S             8
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M          0x00ff0000
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S          16
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M  0xff000000
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S  24
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M               0x000000ff
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S               0
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M          0x0000ff00
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S          8
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M  0x00ff0000
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S  16
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M       0xff000000
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S       24
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_TRAINING_POWER_DB8_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_STATE_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GLUT_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_TX_GAIN_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_DAC_GAIN_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GC_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_IDX_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S)
+/* provide alias macro that uses preferred naming convention */
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_KERNEL_SEL_GET(_var) \
+    HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var)
+#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S)); \
+    } while (0)
+
+/*
+ * htt_stats_phy_dpd_debug_chain_v1_tlv
+ * One TLV per chain. chain_idx identifies which chain this TLV carries.
+ *
+ * Word 0 (after tlv_hdr):
+ * BIT[ 7: 0] - chain_idx
+ * BIT[15: 8] - version
+ * BIT[31:16] - chainmask
+ * Word 1:
+ * BIT[ 7: 0] - num_gain_idx
+ * BIT[31: 8] - reserved
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    union {
+        A_UINT32 chain_idx__version__chainmask;
+        struct {
+            A_UINT32
+                chain_idx:  8,
+                version:    8,
+                chainmask: 16;
+        };
+    };
+    union {
+        A_UINT32 num_gain_idx__reserved;
+        struct {
+            A_UINT32
+                num_gain_idx:  8,
+                reserved:     24;
+        };
+    };
+    htt_stats_phy_dpd_debug_params_v1 dpd_debug_params[HTT_STATS_NUM_DPD_CAL_TABLE];
+} htt_stats_phy_dpd_debug_chain_v1_tlv;
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S 0
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M   0x0000ff00
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S   8
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S 16
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M 0x000000ff
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S 0
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S)
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S)
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S)
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M) >> \
+     HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S)
+#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S)); \
+    } while (0)
+
+/*
+ * htt_stats_phy_tpc_debug_chain_v1_tlv
+ * One TLV per chain. All sub-byte/sub-word fields packed into A_UINT32 words.
+ *
+ * Word 0 (after tlv_hdr):
+ * BIT[ 7: 0] - chain_idx
+ * BIT[15: 8] - version
+ * BIT[31:16] - chainmask
+ *
+ * Words 1-11: TPC per-chain debug params (all A_UINT32)
+ */
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    /*
+     * Word 0: BIT[ 7: 0]=chain_idx
+     *         BIT[15: 8]=version
+     *         BIT[31:16]=chainmask
+     */
+    union {
+        A_UINT32 chain_idx__version__chainmask;
+        struct {
+            A_UINT32
+                chain_idx:  8,
+                version:    8,
+                chainmask: 16;
+        };
+    };
+    /*
+     * Word 1: BIT[7:0]=lat_glut_idx,
+     *         BIT[15:8]=lat_tx_gain_idx,
+     *         BIT[23:16]=lat_dac_gain(s8),
+     *         BIT[31:24]=lat_target_power(s8)
+     */
+    union {
+        A_UINT32 lat_glut_idx__lat_tx_gain_idx__lat_dac_gain__lat_target_power;
+        struct {
+            A_UINT32
+                lat_glut_idx:     8,
+                lat_tx_gain_idx:  8,
+                lat_dac_gain:     8,
+                lat_target_power: 8;
+        };
+    };
+    /*
+     * Word 2: BIT[15:0]=lat_acc_clpc_error(s16),
+     *         BIT[31:16]=lat_clpc_err(s16)
+     */
+    union {
+        A_UINT32 lat_acc_clpc_error__lat_clpc_err;
+        struct {
+            A_UINT32
+                lat_acc_clpc_error: 16,
+                lat_clpc_err:       16;
+        };
+    };
+    /*
+     * Word 3: BIT[15:0]=lat_meas_pwr(s16),
+     *         BIT[23:16]=lat_wsi_temp_valid,
+     *         BIT[31:24]=lat_wsi_full_pkt_pwr_valid
+     */
+    union {
+        A_UINT32 lat_meas_pwr__lat_wsi_temp_valid__lat_wsi_full_pkt_pwr_valid;
+        struct {
+            A_UINT32
+                lat_meas_pwr:               16,
+                lat_wsi_temp_valid:          8,
+                lat_wsi_full_pkt_pwr_valid:  8;
+        };
+    };
+    /*
+     * Word 4: BIT[7:0]=lat_wsi_pream_pwr_valid,
+     *         BIT[23:8]=lat_wsi_temp(s16),
+     *         BIT[31:24]=lat_wsi_full_pkt_pwr
+     */
+    union {
+        A_UINT32 lat_wsi_pream_pwr_valid__lat_wsi_temp__lat_wsi_full_pkt_pwr;
+        struct {
+            A_UINT32
+                lat_wsi_pream_pwr_valid:  8,
+                lat_wsi_temp:            16,
+                lat_wsi_full_pkt_pwr:     8;
+        };
+    };
+    /*
+     * Word 5: BIT[7:0]=lat_wsi_pream_pwr,
+     *         BIT[15:8]=lat_wsi_tx_gain_idx,
+     *         BIT[23:16]=lat_wsi_tpc_pdet_gain_idx,
+     *         BIT[31:24]=lat_wsi_tpc_attn
+     */
+    union {
+        A_UINT32 lat_wsi_pream_pwr__lat_wsi_tx_gain_idx__lat_wsi_tpc_pdet_gain_idx__lat_wsi_tpc_attn;
+        struct {
+            A_UINT32
+                lat_wsi_pream_pwr:         8,
+                lat_wsi_tx_gain_idx:       8,
+                lat_wsi_tpc_pdet_gain_idx: 8,
+                lat_wsi_tpc_attn:          8;
+        };
+    };
+    /*
+     * Word 6: BIT[7:0]=glut_dac_gain_cal(s8),
+     *         BIT[15:8]=glut_max_dac_gain_cal(s8),
+     *         BIT[23:16]=dpd_dac_gain_cal(s8),
+     *         BIT[31:24]=dpd_tx_gain_idx_cal
+     */
+    union {
+        A_UINT32 glut_dac_gain_cal__glut_max_dac_gain_cal__dpd_dac_gain_cal__dpd_tx_gain_idx_cal;
+        struct {
+            A_UINT32
+                glut_dac_gain_cal:     8,
+                glut_max_dac_gain_cal: 8,
+                dpd_dac_gain_cal:      8,
+                dpd_tx_gain_idx_cal:   8;
+        };
+    };
+    /*
+     * Word 7: BIT[7:0]=target_pwr_clpc_thr_corr(s8),
+     *         BIT[15:8]=olpc_mode,
+     *         BIT[23:16]=wsi_timeout,
+     *         BIT[31:24]=target_pwr_clpc_thr_update(s8)
+     */
+    union {
+        A_UINT32 target_pwr_clpc_thr_corr__olpc_mode__wsi_timeout__target_pwr_clpc_thr_update;
+        struct {
+            A_UINT32
+                target_pwr_clpc_thr_corr:   8,
+                olpc_mode:                  8,
+                wsi_timeout:                8,
+                target_pwr_clpc_thr_update: 8;
+        };
+    };
+    /*
+     * Word 8: BIT[7:0]=ro_temp_valid,
+     *         BIT[15:8]=ro_full_pkt_pwr_valid,
+     *         BIT[23:16]=ro_pream_pwr_valid,
+     *         BIT[31:24]=reserved
+     */
+    union {
+        A_UINT32 ro_temp_valid__ro_full_pkt_pwr_valid__ro_pream_pwr_valid;
+        struct {
+            A_UINT32
+                ro_temp_valid:         8,
+                ro_full_pkt_pwr_valid: 8,
+                ro_pream_pwr_valid:    8,
+                reserved:              8;
+        };
+    };
+    /*
+     * Word 9: BIT[15:0]=ro_temp(s16),
+     *         BIT[23:16]=ro_full_pkt_pwr,
+     *         BIT[31:24]=ro_pream_pwr
+     */
+    union {
+        A_UINT32 ro_temp__ro_full_pkt_pwr__ro_pream_pwr;
+        struct {
+            A_UINT32
+                ro_temp:         16,
+                ro_full_pkt_pwr:  8,
+                ro_pream_pwr:     8;
+        };
+    };
+    /*
+     * Word 10: BIT[7:0]=ro_tpc_fe_sel,
+     *          BIT[15:8]=ro_full_pkt_avg_out,
+     *          BIT[23:16]=ro_lat_dc,
+     *          BIT[31:24]=ro_pdacc_avg_out
+     */
+    union {
+        A_UINT32 ro_tpc_fe_sel__ro_full_pkt_avg_out__ro_lat_dc__ro_pdacc_avg_out;
+        struct {
+            A_UINT32
+                ro_tpc_fe_sel:       8,
+                ro_full_pkt_avg_out: 8,
+                ro_lat_dc:           8,
+                ro_pdacc_avg_out:    8;
+        };
+    };
+    /*
+     * Word 11: BIT[15:0]=temp_per_chain,
+     *          BIT[23:16]=cal_cmd,
+     *          BIT[31:24]=cal_time
+     */
+    union {
+        A_UINT32 temp_per_chain__cal_cmd__cal_time;
+        struct {
+            A_UINT32
+                temp_per_chain: 16,
+                cal_cmd:         8,
+                cal_time:        8;
+        };
+    };
+    /*
+     * Word 12: BIT[7:0]=cal_result,
+     *          BIT[31:8]=reserved
+     */
+    union {
+        A_UINT32 cal_result__reserved;
+        struct {
+            A_UINT32
+                cal_result: 8,
+                reserved2: 24;
+        };
+    };
+} htt_stats_phy_tpc_debug_chain_v1_tlv;
+
+/* TPC chain header GET/SET macros */
+/* word 0 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S 0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M   0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S   8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S 16
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S)); \
+    } while (0)
+
+/* word 1 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M     0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S     0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M  0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S  8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M     0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S     16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M 0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S 24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S)); \
+    } while (0)
+
+/* word 2 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M 0x0000ffff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S 0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M       0xffff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S       16
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S)); \
+    } while (0)
+
+/* word 3 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M               0x0000ffff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S               0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M         0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S         16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M 0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S 24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S)); \
+    } while (0)
+
+/* word 4 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M 0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S 0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M            0x00ffff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S            8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M    0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S    24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S)); \
+    } while (0)
+
+/* word 5 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M         0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S         0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M       0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S       8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M 0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S 16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M          0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S          24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S)); \
+    } while (0)
+
+/* word 6 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M     0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S     0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M 0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S 8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M      0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S      16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M   0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S   24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S)); \
+    } while (0)
+
+/* word 7 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M   0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S   0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M                  0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S                  8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M                0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S                16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M 0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S 24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S)); \
+    } while (0)
+
+/* word 8 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M         0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S         0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M 0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S 8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M    0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S    16
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S)); \
+    } while (0)
+
+/* word 9 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M         0x0000ffff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S         0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M 0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S 16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M    0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S    24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S)); \
+    } while (0)
+
+/* word 10 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M       0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S       0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M 0x0000ff00
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S 8
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M           0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S           16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M    0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S    24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S)); \
+    } while (0)
+
+/* word 11 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M 0x0000ffff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S 0
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M        0x00ff0000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S        16
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M       0xff000000
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S       24
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S)); \
+    } while (0)
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S)); \
+    } while (0)
+
+/* word 12 */
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M 0x000000ff
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S 0
+
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_GET(_var) \
+    (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M) >> \
+     HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S)
+#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT, _val); \
+        ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S)); \
+    } while (0)
+
+/*===================== End PHY DPD/TPC Debug stats ==================== } */
+
+
 #endif /* __HTT_STATS_H__ */

From 197c246de9465b1e496a8f2a3d2824951290c48a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Fri, 12 Jun 2026 18:03:55 -0700
Subject: [PATCH 276/290] fw-api: CL 32860533 - update fw common interface
 files

Change-Id: I9d4f03a2786dee6590f64ef7dfc0c63e8d20c54d
CRs-Fixed: 3830439
---
 fw/wmi_services.h | 11 +++++++++++
 fw/wmi_unified.h  | 21 ++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index c970c20720d1..18acd1f63fd7 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -847,6 +847,17 @@ typedef  enum  {
      */
     WMI_SERVICE_NAN_OFFLOAD_MODE_SUPPORT = 519,
 
+    /* WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT:
+     * FW supports handling WMI_PDEV_SET_CUMAC_CHIP_CMDID.
+     * When this service bit is set in wmi_service_ready, the host can
+     * set WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT in
+     * wmi_resource_config.host_service_flags to indicate it will send
+     * WMI_PDEV_SET_CUMAC_CHIP_CMDID to trigger wal_mlo_cumac_init().
+     * If the host does not set this flag, FW will call wal_mlo_cumac_init()
+     * from wal_mlo_soc_init() with the default chip id.
+     */
+    WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT = 520,
+
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f42670d89a8d..9c221dab3851 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5536,8 +5536,14 @@ typedef struct {
      *      Refer to the below definitions of
      *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET and
      *      _SET macros.
+     *  Bit 27
+     *     This bit will be set by host to inform FW that the CUMAC_CMD_ID
+     *     will come post WMI_INIT_CMDID and the MLO_SRNG setup has to be
+     *     done as part of this cmd.
+     *     Refer to the below definitions of
+     *     WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET and SET_macros.
      *
-     *  Bits 31:27 - Reserved
+     *  Bits 31:28 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -6211,6 +6217,19 @@ typedef struct {
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_SET(host_service_flags, value) \
     WMI_SET_BITS(host_service_flags, 26, 1, value)
 
+/*
+ * Bit 27: Host supports WMI_PDEV_SET_CUMAC_CHIP_CMDID.
+ * When set, FW will call the MLO CUMAC init function from the
+ * WMI_PDEV_SET_CUMAC_CHIP_CMDID handler instead of the MLO SoC init function.
+ * Requires WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT to be set in
+ * wmi_service_ready before the host sets this bit.
+ */
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET(host_service_flags) \
+    WMI_GET_BITS(host_service_flags, 27, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_SET(host_service_flags, val) \
+    WMI_SET_BITS(host_service_flags, 27, 1, val)
+
+
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7cabd871a946..4efa48281edb 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1780
+#define __WMI_REVISION_ 1781
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work

From 32961570519d6f7d57542b37b6fd9ca50aad785a Mon Sep 17 00:00:00 2001
From: spuligil <spuligil@qti.qualcomm.com>
Date: Sun, 14 Jun 2026 18:01:38 -0700
Subject: [PATCH 277/290] fw-api: CL 32870364 - update fw common interface
 files

Change-Id: If4bbedb9340dd059741eea4f1e910cd2324999aa
CRs-Fixed: 3830439
---
 fw/htt_stats.h | 59 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 56 insertions(+), 3 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 2ed4422436b2..28d4c2f06ad1 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -16740,12 +16740,65 @@ static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id)
 
 /*===================== Start GTX stats ====================*/
 #define HTT_NUM_MCS_PER_NSS 16
+
+#define HTT_NUM_EXTRA_MCS_PER_NSS 4 /* Stores iMCS index 1.1, 3.1, 4.1, 7.1 */
+
+#define HTT_STATS_GTX_WIFI_VERSION_M 0x0000000f
+#define HTT_STATS_GTX_WIFI_VERSION_S 0
+
+#define HTT_STATS_GTX_WIFI_VERSION_GET(_var) \
+    (((_var) & HTT_STATS_GTX_WIFI_VERSION_M) >> \
+     HTT_STATS_GTX_WIFI_VERSION_S)
+#define HTT_STATS_GTX_WIFI_VERSION_SET(_var, _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_STATS_GTX_WIFI_VERSION, _val); \
+        ((_var) |= ((_val) << HTT_STATS_GTX_WIFI_VERSION_S)); \
+    } while (0)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32 gtx_enabled; /* shows whether Green Tx feature is enabled */
-    A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's minimum TPC in 0.25dBm units */
-    A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's maximum TPC in 0.25dBm units */
-    A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's difference between maximum and minimum TPC in 0.25dB unit*/
+
+    /* shows current MCS's minimum TPC in 0.25dBm units */
+    A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS];
+
+    /* shows current MCS's maximum TPC in 0.25dBm units */
+    A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS];
+
+    /*
+     * shows current MCS's difference between maximum and minimum TPC
+     * in 0.25dB units
+     */
+    A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS];
+    /**
+     * BIT [ 3 :  0]   :- wifi_version
+     * BIT [31 :  4]   :- reserved
+     */
+    union {
+        struct {
+            A_UINT32
+                     /* wifi_version:
+                      * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value.
+                      * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET
+                      * / _SET macros for accessing this bitfield.
+                      */
+                     wifi_version:  4,
+                     reserved:     28;
+        };
+        A_UINT32 wifi_version__word;
+    };
+
+    /* shows current MCS's minimum TPC in 0.25dBm units for iMCS cases */
+    A_INT32 mcs_tpc_min_ext[HTT_NUM_EXTRA_MCS_PER_NSS];
+
+    /* shows current MCS's maximum TPC in 0.25dBm units for iMCS cases */
+    A_INT32 mcs_tpc_max_ext[HTT_NUM_EXTRA_MCS_PER_NSS];
+
+    /*
+     * shows current MCS's difference between maximum and minimum TPC
+     * in 0.25dB units for iMCS cases
+     */
+    A_UINT32 mcs_tpc_diff_ext[HTT_NUM_EXTRA_MCS_PER_NSS];
 } htt_stats_gtx_tlv;
 /*===================== End GTX stats ====================*/
 

From 542be35e0e4883f60bd4839364eb6c142e96858b Mon Sep 17 00:00:00 2001
From: Parag Singhal <parsin@qti.qualcomm.com>
Date: Wed, 17 Jun 2026 10:57:44 +0530
Subject: [PATCH 278/290] msm: camera: common: Fix OOB access in bandwidth path
 handling

Invalid input from user can lead to an index going below the valid
range after offset calculation. Existing validation only checked
the upper bound, allowing negative values to pass and cause
out-of-bounds memory access.
Add complete bounds validation to ensure safe access.

CRs-Fixed: 4544133
Change-Id: Ib37b25ab84e9004eaeb216302857d65df18a2516
Signed-off-by: Parag Singhal <parsin@qti.qualcomm.com>
(cherry picked from commit d6cee3f552be8126f0c8b29ea833228bf3357fa8)
---
 drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
index 31cad8f760a8..d4137ef50e5f 100644
--- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
+++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
 #include <linux/uaccess.h>
@@ -783,7 +783,7 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data)
 			.path_data_type -
 			CAM_AXI_PATH_DATA_OPE_START_OFFSET;
 
-		if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
+		if (path_index < 0 || path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
 			CAM_WARN(CAM_OPE,
 				"Invalid path %d, start offset=%d, max=%d",
 				ctx_data->clk_info.axi_path[i]
@@ -1466,7 +1466,7 @@ static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr,
 		ctx_data->clk_info.axi_path[i].path_data_type -
 		CAM_AXI_PATH_DATA_OPE_START_OFFSET;
 
-		if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
+		if (path_index < 0 || path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
 			CAM_WARN(CAM_OPE,
 				"Invalid path %d, start offset=%d, max=%d",
 				ctx_data->clk_info.axi_path[i].path_data_type,
@@ -1503,7 +1503,7 @@ static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr,
 		ctx_data->clk_info.axi_path[i].path_data_type -
 			CAM_AXI_PATH_DATA_OPE_START_OFFSET;
 
-		if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
+		if (path_index < 0 || path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
 			CAM_WARN(CAM_OPE,
 				"Invalid path %d, start offset=%d, max=%d",
 				ctx_data->clk_info.axi_path[i].path_data_type,
@@ -2899,7 +2899,7 @@ static int cam_ope_mgr_remove_bw(struct cam_ope_hw_mgr *hw_mgr, int ctx_id)
 		ctx_data->clk_info.axi_path[i].path_data_type -
 		CAM_AXI_PATH_DATA_OPE_START_OFFSET;
 
-		if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
+		if (path_index < 0 || path_index >= CAM_OPE_MAX_PER_PATH_VOTES) {
 			CAM_WARN(CAM_OPE,
 				"Invalid path %d, start offset=%d, max=%d",
 				ctx_data->clk_info.axi_path[i].path_data_type,

From a1535b0667cd2868b6e25fbaa2ff1621c6aa3d65 Mon Sep 17 00:00:00 2001
From: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
Date: Wed, 29 Jul 2026 02:39:16 +0600
Subject: [PATCH 279/290] tcp: fix an incorrect __user annotation on
 tcp_proc_delayed_ack_control

No user pointers for sysctls anymore.

Fixes: c3f877ec98a12 ("BACKPORT: sysctl: pass kernel pointers to ->proc_handler")
Change-Id: Ie7d47a3bb5ed4238cea83a493937f38a3fee2571
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 include/net/tcp.h    | 2 +-
 net/ipv4/tcp_timer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/net/tcp.h b/include/net/tcp.h
index bbad196da16c..c8bd83fcabab 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -359,7 +359,7 @@ extern int tcp_use_userconfig_sysctl_handler(struct ctl_table *table,
 				int write, void __user *buffer, size_t *length,
 				loff_t *ppos);
 extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write,
-				void __user *buffer, size_t *length,
+				void *buffer, size_t *length,
 				loff_t *ppos);
 
 void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks);
diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c
index 3b7f98ef34a4..9787b935d6cd 100644
--- a/net/ipv4/tcp_timer.c
+++ b/net/ipv4/tcp_timer.c
@@ -47,7 +47,7 @@ static void set_tcp_default(void)
 
 /*sysctl handler for tcp_ack realted master control */
 int tcp_proc_delayed_ack_control(struct ctl_table *table, int write,
-				 void __user *buffer, size_t *length,
+				 void *buffer, size_t *length,
 				 loff_t *ppos)
 {
 	int ret = proc_dointvec_minmax(table, write, buffer, length, ppos);

From 69c739446987a997585b1c24c9d2cc46945313c8 Mon Sep 17 00:00:00 2001
From: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
Date: Wed, 29 Jul 2026 02:41:58 +0600
Subject: [PATCH 280/290] tcp: fix an incorrect __user annotation on
 tcp_use_userconfig_sysctl_handler

No user pointers for sysctls anymore.

Fixes: c3f877ec98a12 ("BACKPORT: sysctl: pass kernel pointers to ->proc_handler")
Change-Id: Ia9c27a7308aad6fb9b6476f1000d2588d0367014
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 include/net/tcp.h    | 2 +-
 net/ipv4/tcp_timer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/net/tcp.h b/include/net/tcp.h
index c8bd83fcabab..7a50f6984b80 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -356,7 +356,7 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos,
 
 /* sysctl master controller */
 extern int tcp_use_userconfig_sysctl_handler(struct ctl_table *table,
-				int write, void __user *buffer, size_t *length,
+				int write, void *buffer, size_t *length,
 				loff_t *ppos);
 extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write,
 				void *buffer, size_t *length,
diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c
index 9787b935d6cd..2e1e1908097e 100644
--- a/net/ipv4/tcp_timer.c
+++ b/net/ipv4/tcp_timer.c
@@ -61,7 +61,7 @@ int tcp_proc_delayed_ack_control(struct ctl_table *table, int write,
 
 /*sysctl handler for tcp_ack realted master control */
 int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, int write,
-				      void __user *buffer, size_t *length,
+				      void *buffer, size_t *length,
 				      loff_t *ppos)
 {
 	int ret = proc_dointvec_minmax(table, write, buffer, length, ppos);

From 6efbfed6418ef34334185c3ec45c7a8a838b8849 Mon Sep 17 00:00:00 2001
From: Keenan Dong <keenanat2000@gmail.com>
Date: Wed, 8 Apr 2026 16:46:00 +0800
Subject: [PATCH 281/290] BACKPORT: rtmutex: Use waiter::task instead of
 current in remove_waiter()

remove_waiter() is used by the slowlock paths, but it is also used for
proxy-lock rollback in rt_mutex_start_proxy_lock() when invoked from
futex_requeue().

In the latter case waiter::task is not current, but remove_waiter()
operates on current for the dequeue operation. That results in several
problems:

  1) the rbtree dequeue happens without waiter::task::pi_lock being held

  2) the waiter task's pi_blocked_on state is not cleared, which leaves a
     dangling pointer primed for UAF around.

  3) rt_mutex_adjust_prio_chain() operates on the wrong top priority waiter
     task

Use waiter::task instead of current in all related operations in
remove_waiter() to cure those problems.

[ tglx: Fixup rt_mutex_adjust_prio_chain(), add a comment and amend the
  	changelog ]

Fixes: 8161239a8bcc ("rtmutex: Simplify PI algorithm and make highest prio task get lock")
Change-Id: I3ff8da2830773e04f55828b11c9d461ab6ee57c5
Reported-by: Yuan Tan <yuantan098@gmail.com>
Reported-by: Yifan Wu <yifanwucs@gmail.com>
Reported-by: Juefei Pu <tomapufckgml@gmail.com>
Reported-by: Xin Liu <bird@lzu.edu.cn>
Signed-off-by: Keenan Dong <keenanat2000@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Cc: stable@vger.kernel.org
[Tashar02: Open-code scoped_guard() on msm-5.4]
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 kernel/locking/rtmutex.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index 7c727c4944e6..96c67ba69130 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -1063,20 +1063,23 @@ static void mark_wakeup_next_waiter(struct wake_q_head *wake_q,
  *
  * Must be called with lock->wait_lock held and interrupts disabled. I must
  * have just failed to try_to_take_rt_mutex().
+ *
+ * When invoked from rt_mutex_start_proxy_lock() waiter::task != current !
  */
 static void remove_waiter(struct rt_mutex *lock,
 			  struct rt_mutex_waiter *waiter)
 {
 	bool is_top_waiter = (waiter == rt_mutex_top_waiter(lock));
 	struct task_struct *owner = rt_mutex_owner(lock);
+	struct task_struct *waiter_task = waiter->task;
 	struct rt_mutex *next_lock;
 
 	lockdep_assert_held(&lock->wait_lock);
 
-	raw_spin_lock(&current->pi_lock);
+	raw_spin_lock(&waiter_task->pi_lock);
 	rt_mutex_dequeue(lock, waiter);
-	current->pi_blocked_on = NULL;
-	raw_spin_unlock(&current->pi_lock);
+	waiter_task->pi_blocked_on = NULL;
+	raw_spin_unlock(&waiter_task->pi_lock);
 
 	/*
 	 * Only update priority if the waiter was the highest priority
@@ -1112,7 +1115,7 @@ static void remove_waiter(struct rt_mutex *lock,
 	raw_spin_unlock_irq(&lock->wait_lock);
 
 	rt_mutex_adjust_prio_chain(owner, RT_MUTEX_MIN_CHAINWALK, lock,
-				   next_lock, NULL, current);
+				   next_lock, NULL, waiter_task);
 
 	raw_spin_lock_irq(&lock->wait_lock);
 }

From 2ec0afec5c816812750765423f18688c615ab352 Mon Sep 17 00:00:00 2001
From: Davidlohr Bueso <dave@stgolabs.net>
Date: Thu, 7 May 2026 04:29:13 -0700
Subject: [PATCH 282/290] BACKPORT: locking/rtmutex: Skip remove_waiter() when
 waiter is not enqueued

syzbot triggered the following splat in remove_waiter() via
FUTEX_CMP_REQUEUE_PI:

  KASAN: null-ptr-deref in range [0x0000000000000a88-0x0000000000000a8f]
   class_raw_spinlock_constructor
   remove_waiter+0x159/0x1200 kernel/locking/rtmutex.c:1561
   rt_mutex_start_proxy_lock+0x103/0x120
   futex_requeue+0x10e4/0x20d0
   __x64_sys_futex+0x34f/0x4d0

task_blocks_on_rt_mutex() does not arm the waiter upon deadlock detection,
leaving waiter->task nil, where 3bfdc63936dd ("rtmutex: Use waiter::task instead
of current in remove_waiter()") made this fatal.

Furthermore, rt_mutex_start_proxy_lock() should not be calling into remove_waiter()
upon a successfully grabbing the rtmutex. 1a1fb985f2e2 ("futex: Handle early deadlock
return correctly"), moved the remove_waiter() out of __rt_mutex_start_proxy_lock()
(where 'ret' was only ever 0 or < 0) into the wrapper. Tighten this check to
account for try_to_take_rt_mutex().

Fixes: 3bfdc63936dd ("rtmutex: Use waiter::task instead of current in remove_waiter()")
Change-Id: Ib19a2f223ba67d20496c0ae95096747f5350c520
Reported-by: syzbot+78147abe6c524f183ee9@syzkaller.appspotmail.com
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Cc: stable@vger.kernel.org
Closes: https://lore.kernel.org/all/69f114ac.050a0220.ac8b.0003.GAE@google.com/
Link: https://patch.msgid.link/20260507112913.1019537-1-dave@stgolabs.net
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 kernel/locking/rtmutex.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index 96c67ba69130..7a68ab2c5851 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -1076,6 +1076,9 @@ static void remove_waiter(struct rt_mutex *lock,
 
 	lockdep_assert_held(&lock->wait_lock);
 
+	if (!waiter_task) /* never enqueued */
+		return;
+
 	raw_spin_lock(&waiter_task->pi_lock);
 	rt_mutex_dequeue(lock, waiter);
 	waiter_task->pi_blocked_on = NULL;
@@ -1805,7 +1808,7 @@ int rt_mutex_start_proxy_lock(struct rt_mutex *lock,
 
 	raw_spin_lock_irq(&lock->wait_lock);
 	ret = __rt_mutex_start_proxy_lock(lock, waiter, task);
-	if (unlikely(ret))
+	if (unlikely(ret < 0))
 		remove_waiter(lock, waiter);
 	raw_spin_unlock_irq(&lock->wait_lock);
 

From 16656dc06db97192ddea4400dc10f5e055cd3c0c Mon Sep 17 00:00:00 2001
From: William Bowling <vakzz@zellic.io>
Date: Wed, 13 May 2026 04:16:35 +0000
Subject: [PATCH 283/290] net: skbuff: preserve shared-frag marker during
 coalescing

skb_try_coalesce() can attach paged frags from @from to @to.  If @from
has SKBFL_SHARED_FRAG set, the resulting @to skb can contain the same
externally-owned or page-cache-backed frags, but the shared-frag marker
is currently lost.

That breaks the invariant relied on by later in-place writers.  In
particular, ESP input checks skb_has_shared_frag() before deciding
whether an uncloned nonlinear skb can skip skb_cow_data().  If TCP
receive coalescing has moved shared frags into an unmarked skb, ESP can
see skb_has_shared_frag() as false and decrypt in place over page-cache
backed frags.

Propagate SKBFL_SHARED_FRAG when skb_try_coalesce() transfers paged
frags.  The tailroom copy path does not need the marker because it copies
bytes into @to's linear data rather than transferring frag descriptors.

Fixes: cef401de7be8 ("net: fix possible wrong checksum generation")
Fixes: f4c50a4034e6 ("xfrm: esp: avoid in-place decrypt on shared skb frags")
Signed-off-by: William Bowling <vakzz@zellic.io>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Tested-by: Jiayuan Chen <jiayuan.chen@linux.dev>
Link: https://patch.msgid.link/20260513041635.1289541-1-vakzz@zellic.io
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit f84eca5817390257cef78013d0112481c503b4a3)

Orabug: 39368828

Clean cherry-pick build needs a build fixup, on uek6/u3, shared-frag
state is carried in tx_flags(SKBTX_SHARED_FRAG), so propagate it when
frag ownership moves, and it doesn't have skb_shared_info.flags
SKBFL_SHARED_FRAG so accordingly adapted the patch. This is due to
missing 06b4feb37e64 (net: group skb_shinfo zerocopy related bits
together.) commit in UEK6U3.

Change-Id: I71564bc3a42d7523011705022a49393b63070fd5
Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Reviewed-by: Joseph Salisbury <joseph.salisbury@oracle.com>
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/core/skbuff.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index a7e5b5843539..b240d85ea1f1 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -5295,6 +5295,8 @@ bool skb_try_coalesce(struct sk_buff *to, struct sk_buff *from,
 	       from_shinfo->frags,
 	       from_shinfo->nr_frags * sizeof(skb_frag_t));
 	to_shinfo->nr_frags += from_shinfo->nr_frags;
+	if (from_shinfo->nr_frags)
+		to_shinfo->tx_flags |= from_shinfo->tx_flags & SKBTX_SHARED_FRAG;
 
 	if (!skb_cloned(from))
 		from_shinfo->nr_frags = 0;

From 06dad31134ce2a747433c09f4842574ceba54835 Mon Sep 17 00:00:00 2001
From: Hyunwoo Kim <imv4bel@gmail.com>
Date: Sat, 16 May 2026 07:28:53 +0900
Subject: [PATCH 284/290] net: skbuff: propagate shared-frag marker through
 frag-transfer helpers

Two frag-transfer helpers (__pskb_copy_fclone() and skb_shift()) fail
to propagate the SKBFL_SHARED_FRAG bit in skb_shinfo()->flags when
moving frags from source to destination.  __pskb_copy_fclone() defers
the rest of the shinfo metadata to skb_copy_header() after copying
frag descriptors, but that helper only carries over gso_{size,segs,
type} and never touches skb_shinfo()->flags; skb_shift() moves frag
descriptors directly and leaves flags untouched.  As a result, the
destination skb keeps a reference to the same externally-owned or
page-cache-backed pages while reporting skb_has_shared_frag() as
false.

The mismatch is harmful in any in-place writer that uses
skb_has_shared_frag() to decide whether shared pages must be detoured
through skb_cow_data().  ESP input is one such writer (esp4.c,
esp6.c), and a single nft 'dup to <local>' rule -- or any other
nf_dup_ipv4() / xt_TEE caller -- is enough to land a pskb_copy()'d
skb in esp_input() with the marker stripped, letting an unprivileged
user write into the page cache of a root-owned read-only file via
authencesn-ESN stray writes.

Set SKBFL_SHARED_FRAG on the destination whenever frag descriptors
were actually moved from the source.  skb_copy() and skb_copy_expand()
share skb_copy_header() too but linearize all paged data into freshly
allocated head storage and emerge with nr_frags == 0, so
skb_has_shared_frag() returns false on its own; they need no change.

The same omission exists in skb_gro_receive() and skb_gro_receive_list().
The former moves the incoming skb's frag descriptors into the
accumulator's last sub-skb via two paths (a direct frag-move loop and
the head_frag + memcpy path); the latter chains the incoming skb whole
onto p's frag_list.  Downstream skb_segment() reads only
skb_shinfo(p)->flags, and skb_segment_list() reuses each sub-skb's
shinfo as the nskb -- both p and lp must carry the marker.

The same omission also exists in tcp_clone_payload(), which builds an
MTU probe skb by moving frag descriptors from skbs on sk_write_queue
into a freshly allocated nskb.  The helper falls into the same family
and warrants the same fix for consistency; no TCP TX-side in-place
writer is currently known to reach a user page through this gap, but
a future consumer depending on the marker would regress silently.

The same omission exists in skb_segment(): the per-iteration flag
merge takes only head_skb's flag, and the inner switch that rebinds
frag_skb to list_skb on head_skb-frags exhaustion does not fold the
new frag_skb's flag into nskb.  Fold frag_skb's flag at both sites
so segments drawing frags from frag_list members carry the marker.

Fixes: cef401de7be8 ("net: fix possible wrong checksum generation")
Fixes: f4c50a4034e6 ("xfrm: esp: avoid in-place decrypt on shared skb frags")
Suggested-by: Sabrina Dubroca <sd@queasysnail.net>
Suggested-by: Sultan Alsawaf <sultan@kerneltoast.com>
Suggested-by: Ben Hutchings <ben@decadent.org.uk>
Suggested-by: Lin Ma <malin89@huawei.com>
Suggested-by: Jingguo Tan <tanjingguo@huawei.com>
Suggested-by: Aaron Esau <aaron1esau@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
Tested-by: Rajat Gupta <rajat.gupta@oss.qualcomm.com>
Link: https://patch.msgid.link/ageeJfJHwgzmKXbh@v4bel
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
(cherry picked from commit 48f6a5356a33dd78e7144ae1faef95ffc990aae0)

Orabug: 39368828
CVE: CVE-2026-46300

Conflicts:
-	net/core/gro.c - Not present in UEK6U3
-	net/core/skbuff.c UEK6U3 doesn't have commit: 06b4feb3
	("net: group skb_shinfo zerocopy related bits together.") so
	used skb_shinfo(nskb)->tx_flags
-	net/ipv4/tcp_output.c - net/ipv4/tcp_output.c - UEK6U3 doesn't
	have commit: 73601329 ("tcp: let tcp_mtu_probe() build
	headless packets") so we need not take the hunk corresponding
	to tcp_clone_payload()

Change-Id: I19fe41c96158d2614b04d4593083826135418615
Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Reviewed-by: Joseph Salisbury <joseph.salisbury@oracle.com>
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/core/skbuff.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index b240d85ea1f1..a54b7a4ad046 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -1605,6 +1605,7 @@ struct sk_buff *__pskb_copy_fclone(struct sk_buff *skb, int headroom,
 			skb_frag_ref(skb, i);
 		}
 		skb_shinfo(n)->nr_frags = i;
+		skb_shinfo(n)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG;
 	}
 
 	if (skb_has_frag_list(skb)) {
@@ -3489,6 +3490,8 @@ onlymerged:
 	tgt->ip_summed = CHECKSUM_PARTIAL;
 	skb->ip_summed = CHECKSUM_PARTIAL;
 
+	skb_shinfo(tgt)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG;
+
 	/* Yak, is it really working this way? Some helper please? */
 	skb->len -= shiftlen;
 	skb->data_len -= shiftlen;
@@ -3832,6 +3835,8 @@ int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
 	p->truesize += skb->truesize;
 	p->len += skb->len;
 
+	skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG;
+
 	NAPI_GRO_CB(skb)->same_flow = 1;
 
 	return 0;
@@ -4061,7 +4066,8 @@ normal:
 		skb_copy_from_linear_data_offset(head_skb, offset,
 						 skb_put(nskb, hsize), hsize);
 
-		skb_shinfo(nskb)->tx_flags |= skb_shinfo(head_skb)->tx_flags &
+		skb_shinfo(nskb)->tx_flags |= (skb_shinfo(head_skb)->tx_flags |
+					       skb_shinfo(frag_skb)->tx_flags) &
 					      SKBTX_SHARED_FRAG;
 
 		if (skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC))
@@ -4078,6 +4084,9 @@ normal:
 				nfrags = skb_shinfo(list_skb)->nr_frags;
 				frag = skb_shinfo(list_skb)->frags;
 				frag_skb = list_skb;
+
+				skb_shinfo(nskb)->tx_flags |= skb_shinfo(frag_skb)->tx_flags & SKBTX_SHARED_FRAG;
+
 				if (!skb_headlen(list_skb)) {
 					BUG_ON(!nfrags);
 				} else {
@@ -4294,10 +4303,12 @@ done:
 	p->data_len += len;
 	p->truesize += delta_truesize;
 	p->len += len;
+	skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG;
 	if (lp != p) {
 		lp->data_len += len;
 		lp->truesize += delta_truesize;
 		lp->len += len;
+		skb_shinfo(lp)->tx_flags |= skbinfo->tx_flags & SKBTX_SHARED_FRAG;
 	}
 	NAPI_GRO_CB(skb)->same_flow = 1;
 	return 0;

From aaee6ec86fdd8d2578edfea52c6f85a0ec5d5332 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 26 Mar 2026 15:51:38 +0000
Subject: [PATCH 285/290] ip6_tunnel: clear skb2->cb[] in ip4ip6_err()

[ Upstream commit 2edfa31769a4add828a7e604b21cb82aaaa05925 ]

Oskar Kjos reported the following problem.

ip4ip6_err() calls icmp_send() on a cloned skb whose cb[] was written
by the IPv6 receive path as struct inet6_skb_parm. icmp_send() passes
IPCB(skb2) to __ip_options_echo(), which interprets that cb[] region
as struct inet_skb_parm (IPv4). The layouts differ: inet6_skb_parm.nhoff
at offset 14 overlaps inet_skb_parm.opt.rr, producing a non-zero rr
value. __ip_options_echo() then reads optlen from attacker-controlled
packet data at sptr[rr+1] and copies that many bytes into dopt->__data,
a fixed 40-byte stack buffer (IP_OPTIONS_DATA_FIXED_SIZE).

To fix this we clear skb2->cb[], as suggested by Oskar Kjos.

Also add minimal IPv4 header validation (version == 4, ihl >= 5).

Fixes: c4d3efafcc93 ("[IPV6] IP6TUNNEL: Add support to IPv4 over IPv6 tunnel.")
Reported-by: Oskar Kjos <oskar.kjos@hotmail.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://patch.msgid.link/20260326155138.2429480-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit ea9f65b27c8404e164848ebff1443310fd187629)

Orabug: 39300926
CVE: CVE-2026-43037

Change-Id: I03aec3d53f61119bc726073dd91c17cc5a31dfd3
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/ipv6/ip6_tunnel.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c
index c79e6c032b30..604a6c018b2b 100644
--- a/net/ipv6/ip6_tunnel.c
+++ b/net/ipv6/ip6_tunnel.c
@@ -601,11 +601,16 @@ ip4ip6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
 	if (!skb2)
 		return 0;
 
+	/* Remove debris left by IPv6 stack. */
+	memset(IPCB(skb2), 0, sizeof(*IPCB(skb2)));
+
 	skb_dst_drop(skb2);
 
 	skb_pull(skb2, offset);
 	skb_reset_network_header(skb2);
 	eiph = ip_hdr(skb2);
+	if (eiph->version != 4 || eiph->ihl < 5)
+		goto out;
 
 	/* Try to guess incoming interface */
 	rt = ip_route_output_ports(dev_net(skb->dev), &fl4, NULL, eiph->saddr,

From 214ddb05df3990c38e380df1cff33248306ab447 Mon Sep 17 00:00:00 2001
From: Yochai Eisenrich <echelonh@gmail.com>
Date: Thu, 19 Mar 2026 22:06:10 +0200
Subject: [PATCH 286/290] net: fix fanout UAF in packet_release() via NETDEV_UP
 race

[ Upstream commit 42156f93d123436f2a27c468f18c966b7e5db796 ]

`packet_release()` has a race window where `NETDEV_UP` can re-register a
socket into a fanout group's `arr[]` array. The re-registration is not
cleaned up by `fanout_release()`, leaving a dangling pointer in the fanout
array.
`packet_release()` does NOT zero `po->num` in its `bind_lock` section.
After releasing `bind_lock`, `po->num` is still non-zero and `po->ifindex`
still matches the bound device. A concurrent `packet_notifier(NETDEV_UP)`
that already found the socket in `sklist` can re-register the hook.
For fanout sockets, this re-registration calls `__fanout_link(sk, po)`
which adds the socket back into `f->arr[]` and increments `f->num_members`,
but does NOT increment `f->sk_ref`.

The fix sets `po->num` to zero in `packet_release` while `bind_lock` is
held to prevent NETDEV_UP from linking, preventing the race window.

This bug was found following an additional audit with Claude Code based
on CVE-2025-38617.

Fixes: ce06b03e60fc ("packet: Add helpers to register/unregister ->prot_hook")
Link: https://blog.calif.io/p/a-race-within-a-race-exploiting-cve
Signed-off-by: Yochai Eisenrich <echelonh@gmail.com>
Reviewed-by: Willem de Bruijn <willemb@google.com>
Link: https://patch.msgid.link/20260319200610.25101-1-echelonh@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit ee642b1962caa9aa231c01abbd58bc453ae6b66e)

Orabug: 39250953
CVE: CVE-2026-31504

Change-Id: I002fefc6bd0bbe09ed5e2ad13009c783609ec04a
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/packet/af_packet.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index f7e02f9f9ed1..9c6cc1cf547c 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -3117,6 +3117,7 @@ static int packet_release(struct socket *sock)
 
 	spin_lock(&po->bind_lock);
 	unregister_prot_hook(sk, false);
+	WRITE_ONCE(po->num, 0);
 	packet_cached_dev_reset(po);
 
 	if (po->prot_hook.dev) {

From 90694eff39ecf2c294d880cbaa0267d91a9e7108 Mon Sep 17 00:00:00 2001
From: Minh Nguyen <minhnguyen.080505@gmail.com>
Date: Fri, 5 Jun 2026 14:31:31 -0400
Subject: [PATCH 287/290] net: skbuff: fix missing zerocopy reference in
 pskb_carve helpers

[ Upstream commit 98d0912e9f841e5529a5b89a972805f34cb1c69d ]

pskb_carve_inside_header() and pskb_carve_inside_nonlinear() both copy
the old skb_shared_info header into a new buffer via memcpy(), which
includes the destructor_arg pointer (uarg) for MSG_ZEROCOPY skbs.
Neither function calls net_zcopy_get() for the new shinfo, creating an
unaccounted holder: every skb_shared_info with destructor_arg set will
call skb_zcopy_clear() once when freed, but the corresponding
net_zcopy_get() was never called for the new copy. Repeated calls
drive uarg->refcnt to zero prematurely, freeing ubuf_info_msgzc while
TX skbs still hold live destructor_arg pointers.

KASAN reports use-after-free on a freed ubuf_info_msgzc:

  BUG: KASAN: slab-use-after-free in skb_release_data+0x77b/0x810
  Read of size 8 at addr ffff88801574d3e8 by task poc/220

  Call Trace:
   skb_release_data+0x77b/0x810
   kfree_skb_list_reason+0x13e/0x610
   skb_release_data+0x4cd/0x810
   sk_skb_reason_drop+0xf3/0x340
   skb_queue_purge_reason+0x282/0x440
   rds_tcp_inc_free+0x1e/0x30
   rds_recvmsg+0x354/0x1780
   __sys_recvmsg+0xdf/0x180

  Allocated by task 219:
   msg_zerocopy_realloc+0x157/0x7b0
   tcp_sendmsg_locked+0x2892/0x3ba0

  Freed by task 219:
   ip_recv_error+0x74a/0xb10
   tcp_recvmsg+0x475/0x530

The skb consuming the late access still referenced the same uarg via
shinfo->destructor_arg copied by pskb_carve_inside_nonlinear() without
a refcount bump. This has been verified to be reliably exploitable: a
working proof-of-concept achieves full root privilege escalation from
an unprivileged local user on a default kernel configuration.

The fix follows the pattern of pskb_expand_head() which has the same
memcpy/cloned structure. For pskb_carve_inside_header(), net_zcopy_get()
is placed after skb_orphan_frags() succeeds, so the orphan error path
needs no cleanup. For pskb_carve_inside_nonlinear(), net_zcopy_get() is
placed after all failure points and just before skb_release_data(), so
no error path needs cleanup at all -- matching pskb_expand_head() more
closely and avoiding the need for a balancing net_zcopy_put().

Fixes: 6fa01ccd8830 ("skbuff: Add pskb_extract() helper function")
Cc: stable@vger.kernel.org
Assisted-by: Claude:claude-sonnet-4-6
Signed-off-by: Minh Nguyen <minhnguyen.080505@gmail.com>
Reviewed-by: Willem de Bruijn <willemb@google.com>
Link: https://patch.msgid.link/20260526041240.329462-1-minhnguyen.080505@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 8dbed691e43a50903658130bde0fcb5abc425b37)

Orabug: 39619389
CVE: CVE-2026-52943

Change-Id: I594313483c8e53caaf6012c5c16a645b3f223b58
Signed-off-by: Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com>
Reviewed-by: Samasth Norway Ananda <samasth.norway.ananda@oracle.com>
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/core/skbuff.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index a54b7a4ad046..15e7a2a27989 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -6036,6 +6036,8 @@ static int pskb_carve_inside_header(struct sk_buff *skb, const u32 off,
 			kfree(data);
 			return -ENOMEM;
 		}
+		if (skb_zcopy(skb))
+			refcount_inc(&skb_uarg(skb)->refcnt);
 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
 			skb_frag_ref(skb, i);
 		if (skb_has_frag_list(skb))
@@ -6189,6 +6191,8 @@ static int pskb_carve_inside_nonlinear(struct sk_buff *skb, const u32 off,
 		kfree(data);
 		return -ENOMEM;
 	}
+	if (skb_zcopy(skb))
+		refcount_inc(&skb_uarg(skb)->refcnt);
 	skb_release_data(skb);
 
 	skb->head = data;

From 7b94a33952153f2586c79c875feecfe214abd259 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Thu, 26 Mar 2026 20:26:08 +0000
Subject: [PATCH 288/290] ipv6: icmp: clear skb2->cb[] in
 ip6_err_gen_icmpv6_unreach()

[ Upstream commit 86ab3e55673a7a49a841838776f1ab18d23a67b5 ]

Sashiko AI-review observed:

  In ip6_err_gen_icmpv6_unreach(), the skb is an outer IPv4 ICMP error packet
  where its cb contains an IPv4 inet_skb_parm. When skb is cloned into skb2
  and passed to icmp6_send(), it uses IP6CB(skb2).

  IP6CB interprets the IPv4 inet_skb_parm as an inet6_skb_parm. The cipso
  offset in inet_skb_parm.opt directly overlaps with dsthao in inet6_skb_parm
  at offset 18.

  If an attacker sends a forged ICMPv4 error with a CIPSO IP option, dsthao
  would be a non-zero offset. Inside icmp6_send(), mip6_addr_swap() is called
  and uses ipv6_find_tlv(skb, opt->dsthao, IPV6_TLV_HAO).

  This would scan the inner, attacker-controlled IPv6 packet starting at that
  offset, potentially returning a fake TLV without checking if the remaining
  packet length can hold the full 18-byte struct ipv6_destopt_hao.

  Could mip6_addr_swap() then perform a 16-byte swap that extends past the end
  of the packet data into skb_shared_info?

  Should the cb array also be cleared in ip6_err_gen_icmpv6_unreach() and
  ip6ip6_err() to prevent this?

This patch implements the first suggestion.

I am not sure if ip6ip6_err() needs to be changed.
A separate patch would be better anyway.

Fixes: ca15a078bd90 ("sit: generate icmpv6 error when receiving icmpv4 error")
Reported-by: Ido Schimmel <idosch@nvidia.com>
Closes: https://sashiko.dev/#/patchset/20260326155138.2429480-1-edumazet%40google.com
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Oskar Kjos <oskar.kjos@hotmail.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://patch.msgid.link/20260326202608.2976021-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit c438ba010171b70bad22fc18b1d5bdc3627476e8)

Orabug: 39300930
CVE: CVE-2026-43038

Change-Id: I07e2f318a3c835d56aae6b5e68d8e8e3c7e4c493
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 net/ipv6/icmp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c
index 169467b5c98a..012cadd47f43 100644
--- a/net/ipv6/icmp.c
+++ b/net/ipv6/icmp.c
@@ -639,6 +639,9 @@ int ip6_err_gen_icmpv6_unreach(struct sk_buff *skb, int nhs, int type,
 	if (!skb2)
 		return 1;
 
+	/* Remove debris left by IPv4 stack. */
+	memset(IP6CB(skb2), 0, sizeof(*IP6CB(skb2)));
+
 	skb_dst_drop(skb2);
 	skb_pull(skb2, nhs);
 	skb_reset_network_header(skb2);

From e70533ab68da697f3ed0bafd25c2d57b5b837331 Mon Sep 17 00:00:00 2001
From: Salvo Giangreco <giangrecosalvo9@gmail.com>
Date: Sat, 8 Aug 2026 16:40:24 +0200
Subject: [PATCH 289/290] techpack: datarmnet-ext: shs: fix CFI failure on
 module init with newer Clang versions

<4>[    1.660990] [6:           init:    1]  ------------[ cut here ]------------
<4>[    1.661004] [6:           init:    1]  CFI failure (target: DATARMNET163e93649e+0x0/0xfb8 [rmnet_shs]):
<4>[    1.661018] [6:           init:    1]  WARNING: CPU: 6 PID: 1 at kernel/cfi.c:30 __ubsan_handle_cfi_check_fail+0x4c/0x54
<4>[    1.661020] [6:           init:    1]  Modules linked in: rmnet_shs(+) rmnet_offload rmnet_core rmnet_ctl camera hdmi_dlkm stub_dlkm swr_dmic_dlkm rx_macro_dlkm tx_macro_dlkm va_macro_dlkm wcd938x_slave_dlkm adsp_loader_dlkm native_dlkm platform_dlkm machine_dlkm tas256x_dlkm wcd938x_dlkm mbhc_dlkm wcd9xxx_dlkm wcd_core_dlkm bolero_cdc_dlkm swr_ctrl_dlkm swr_dlkm pinctrl_lpi_dlkm q6_dlkm apr_dlkm q6_notifier_dlkm q6_pdr_dlkm snd_event_dlkm pinctrl_wcd_dlkm sec_audio_sysfs slimbus_ngd stm_ts sec_cmd sec_tsp_dumpkey sec_common_fn sec_secure_touch sec_tclm_v2 sec_tsp_log kperfmon wlan(C) hid_aksys bt_fm_slim slimbus btpower tda18250 m88rs6000t qm1d1b0004 qm1d1c0042 mxl301rf r820t it913x fc0013 fc0012 fc0011 si2157 tua9001 fc2580 e4000 tda18212 tda18218 max2165 mc44s803 mxl5007t mxl5005s mt2131 qt1010 mt2266 mt2063 mt2060 msi001 xc4000 xc5000 tda9887 tea5761 tea5767 mt20xx tuner_simple tuner_types tuner_xc2028 aqc111 cdc_ncm cdc_eem rtl8150 nfc_sec rdbg llcc_perfmon ssg_iosched blk_sec_stats
<4>[    1.661052] [6:           init:    1]  CPU: 6 PID: 1 Comm: init Tainted: G S      WC        5.4.302-qgki-52214-g542c168ade6d-dirty #1
<4>[    1.661055] [6:           init:    1]  Hardware name: Samsung A52SXQ PROJECT (board-id,02) (DT)
<4>[    1.661058] [6:           init:    1]  pstate: 60400005 (nZCv daif +PAN -UAO)
<4>[    1.661061] [6:           init:    1]  pc : __ubsan_handle_cfi_check_fail+0x4c/0x54
<4>[    1.661063] [6:           init:    1]  lr : __ubsan_handle_cfi_check_fail+0x4c/0x54
<4>[    1.661065] [6:           init:    1]  sp : ffffffc010063a40
<4>[    1.661067] [6:           init:    1]  x29: ffffffc010063a40 x28: 0000000000000379
<4>[    1.661070] [6:           init:    1]  x27: 00000000000037e7 x26: ffffff8045f72f40
<4>[    1.661073] [6:           init:    1]  x25: 0000000000000000 x24: ffffffc00b66e000
<4>[    1.661075] [6:           init:    1]  x23: ffffff8045f72f40 x22: 0000000000000001
<4>[    1.661077] [6:           init:    1]  x21: 02b3a43e29242445 x20: ffffffc012b4a000
<4>[    1.661079] [6:           init:    1]  x19: ffffffc00b691048 x18: ffffffc010059048
<4>[    1.661081] [6:           init:    1]  x17: ffffffc012eb9000 x16: 0000000000000010
<4>[    1.661084] [6:           init:    1]  x15: ffffffc01188446c x14: 3a295d7368735f74
<4>[    1.661086] [6:           init:    1]  x13: 0000000000000330 x12: 0000000000000018
<4>[    1.661088] [6:           init:    1]  x11: 000000000000000a x10: 00000000ffffffff
<4>[    1.661091] [6:           init:    1]  x9 : 102999c091cf4200 x8 : 102999c091cf4200
<4>[    1.661093] [6:           init:    1]  x7 : 6c69616620494643 x6 : ffffffc012eb8aab
<4>[    1.661095] [6:           init:    1]  x5 : 0000000000000001 x4 : 0000000000000000
<4>[    1.661097] [6:           init:    1]  x3 : 0000000000002020 x2 : 0000000000000001
<4>[    1.661099] [6:           init:    1]  x1 : 0000000000000000 x0 : 0000000000000040
<4>[    1.661102] [6:           init:    1]  Call trace:
<4>[    1.661105] [6:           init:    1]   __ubsan_handle_cfi_check_fail+0x4c/0x54
<4>[    1.661113] [6:           init:    1]   __cfi_check_fail+0x3c/0x8c [rmnet_shs]
<4>[    1.661120] [6:           init:    1]   __cfi_check+0x3a8/0x3b0 [rmnet_shs]
<4>[    1.661123] [6:           init:    1]   __cfi_slowpath_diag+0x10c/0x164
<4>[    1.661127] [6:           init:    1]   do_one_initcall+0x2c0/0x478
<4>[    1.661130] [6:           init:    1]   do_init_module+0x4c/0x204
<4>[    1.661133] [6:           init:    1]   load_module+0x16f8/0x18d4
<4>[    1.661136] [6:           init:    1]   __arm64_sys_finit_module+0xb4/0xf0
<4>[    1.661139] [6:           init:    1]   el0_svc_common+0xc0/0x1b0
<4>[    1.661142] [6:           init:    1]   el0_svc_handler+0x24/0x84
<4>[    1.661145] [6:           init:    1]   el0_svc+0x8/0x140
<4>[    1.661147] [6:           init:    1]  ---[ end trace 91166a70db25a0a4 ]---

Change-Id: Ie89f1489dfb834836df13a30a0a03cb7eb0bf500
---
 techpack/datarmnet-ext/shs/rmnet_shs_config.c | 4 ++--
 techpack/datarmnet-ext/shs/rmnet_shs_config.h | 3 +--
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.c b/techpack/datarmnet-ext/shs/rmnet_shs_config.c
index 56115cc8d2a9..a7988474c084 100644
--- a/techpack/datarmnet-ext/shs/rmnet_shs_config.c
+++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.c
@@ -61,14 +61,14 @@ DATARMNET5fc54f7a13 __read_mostly={.notifier_call=DATARMNETe9173bbe0e,.priority=
 "\x49\x32\x36\x33\x33\x36\x37\x39\x61\x65\x36\x34\x37\x61\x30\x36\x36\x62\x32\x38\x36\x32\x66\x39\x31\x33\x30\x31\x31\x64\x33\x33\x65\x33\x38\x32\x36\x63\x61\x32\x35"
 ,
 "\x49\x36\x36\x39\x35\x65\x39\x38\x30\x63\x35\x65\x37\x62\x62\x32\x39\x33\x36\x35\x63\x34\x37\x65\x31\x35\x33\x36\x64\x63\x31\x34\x65\x66\x61\x31\x63\x30\x30\x34\x33"
-};static int DATARMNET2cb9ae589c;int __init DATARMNET163e93649e(void){pr_info(
+};static int DATARMNET2cb9ae589c;static int __init DATARMNET163e93649e(void){pr_info(
 "\x25\x73\x28\x29\x3a\x20\x53\x74\x61\x72\x74\x69\x6e\x67\x20\x72\x6d\x6e\x65\x74\x20\x53\x48\x53\x20\x6d\x6f\x64\x75\x6c\x65\x20\x25\x73\x20" "\n"
 ,__func__,DATARMNETbc8418e817[(0xd2d+202-0xdf7)]);trace_rmnet_shs_high(
 DATARMNET1790979ccf,DATARMNET72cb00fdc0,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c),
 (0x16e8+787-0xc0c),(0x16e8+787-0xc0c),NULL,NULL);if(DATARMNET0dbc627e8f()){
 rm_err("\x25\x73",
 "\x53\x48\x53\x5f\x47\x4e\x4c\x3a\x20\x46\x61\x69\x6c\x65\x64\x20\x74\x6f\x20\x69\x6e\x69\x74\x20\x67\x65\x6e\x65\x72\x69\x63\x20\x6e\x65\x74\x6c\x69\x6e\x6b"
-);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}void __exit 
+);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}static void __exit 
 DATARMNETf3298dab6f(void){trace_rmnet_shs_high(DATARMNET1790979ccf,
 DATARMNET89958f9b63,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c),(0x16e8+787-0xc0c),
 (0x16e8+787-0xc0c),NULL,NULL);unregister_netdevice_notifier(&DATARMNET5fc54f7a13
diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.h b/techpack/datarmnet-ext/shs/rmnet_shs_config.h
index ac99913202f5..52a342bd3157 100644
--- a/techpack/datarmnet-ext/shs/rmnet_shs_config.h
+++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.h
@@ -20,7 +20,6 @@
 #define DATARMNET8120d41372	(0xd1f+216-0xdf5)
 #define DATARMNET47c2367f93	(0xd18+223-0xdf4)
 extern struct DATARMNETa6b20d7e8b DATARMNETecc0627c70;extern int 
-rmnet_is_real_dev_registered(const struct net_device*real_dev);int __init 
-DATARMNET163e93649e(void);void __exit DATARMNETf3298dab6f(void);
+rmnet_is_real_dev_registered(const struct net_device*real_dev);
 #endif 
 

From 629d9d7ba8bb08a7419cb3f98256f6cf0a599760 Mon Sep 17 00:00:00 2001
From: Nolen Johnson <johnsonnolen@gmail.com>
Date: Mon, 10 Aug 2026 20:21:11 -0400
Subject: [PATCH 290/290] drivers: staging: fw-api: Correct mis-merge

* Matches correct merge of LA.UM.9.14.1.r1-21700-QCM6490.QISI15.0.

Change-Id: I36ed254e33a2030fa120b0900422ff0ddc8e9f7e
---
 {hw => drivers/staging/fw-api/hw}/fig/v1/HALcomdef.h              | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/HALhwio.h                | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/ack_report.h             | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/boron_top_reg.h          | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/buffer_addr_info.h       | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/ce_src_desc.h            | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/ce_stat_desc.h           | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/coex_rx_status.h         | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/coex_tx_req.h            | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/coex_tx_status.h         | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/com_dtypes.h             | 0
 .../staging/fw-api/hw}/fig/v1/eht_sig_usr_mu_mimo_info.h          | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/eht_sig_usr_ofdma_info.h | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/eht_sig_usr_su_info.h    | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/expected_response.h      | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_mu_dl_info.h    | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_mu_ul_info.h    | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_su_info.h       | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b1_mu_info.h      | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b2_mu_info.h      | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b2_ofdma_info.h   | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/ht_sig_info.h            | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/l_sig_a_info.h           | 0
 {hw => drivers/staging/fw-api/hw}/fig/v1/l_sig_b_info.h           | 0
 .../staging/fw-api/hw}/fig/v1/macrx_abort_request_info.h          | 0
 .../staging/fw-api/hw}/fig/v1/mactx_eht_sig_usr_mu_mimo.h         | 0
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 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_ack_report.h | 0
 .../staging/fw-api/hw}/wcn8750/v1/rx_ppdu_end_user_stats.h        | 0
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 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_start.h      | 0
 .../staging/fw-api/hw}/wcn8750/v1/rx_ppdu_start_user_info.h       | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_preamble.h        | 0
 .../staging/fw-api/hw}/wcn8750/v1/rx_response_required_info.h     | 0
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 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_start_param.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_timing_info.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_trig_info.h       | 0
 .../staging/fw-api/hw}/wcn8750/v1/rxpcu_early_rx_indication.h     | 0
 .../staging/fw-api/hw}/wcn8750/v1/rxpcu_ppdu_end_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/rxpcu_ppdu_end_layout_info.h    | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rxpt_classify_info.h | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/seq_hwio.h           | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tcl_assist_cmd.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tcl_status_ring.h    | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tlv_hdr.h            | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tlv_tag_def.h        | 0
 .../staging/fw-api/hw}/wcn8750/v1/tqm2sw_completion_ring.h        | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_cbf_info.h        | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_setup.h       | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_1k_ba.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_ack_or_ba.h       | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_end.h  | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_prot.h | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start_ppdu.h      | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start_prot.h      | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_user_ppdu.h       | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_fes_status_user_response.h   | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_flush_req.h       | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_mpdu_start.h      | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_msdu_extension.h  | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_msdu_start.h      | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_peer_entry.h      | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_queue_extension.h | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_rate_stats_info.h | 0
 .../staging/fw-api/hw}/wcn8750/v1/tx_raw_or_native_frame_setup.h  | 0
 .../staging/fw-api/hw}/wcn8750/v1/txpcu_buffer_basics.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/txpcu_buffer_status.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/txpcu_user_buffer_status.h      | 0
 .../staging/fw-api/hw}/wcn8750/v1/u_sig_eht_su_mu_info.h          | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/u_sig_eht_tb_info.h  | 0
 .../staging/fw-api/hw}/wcn8750/v1/unallocated_ru_160_info.h       | 0
 .../staging/fw-api/hw}/wcn8750/v1/uniform_descriptor_header.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_a_info.h     | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu160_info.h          | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu20_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu40_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu80_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su160_info.h          | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su20_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su40_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su80_info.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/wbm2sw_completion_ring_rx.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_buffer_ring.h    | 0
 .../staging/fw-api/hw}/wcn8750/v1/wbm_link_descriptor_ring.h      | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_release_ring.h   | 0
 .../staging/fw-api/hw}/wcn8750/v1/wbm_release_ring_rx.h           | 0
 .../staging/fw-api/hw}/wcn8750/v1/wbm_release_ring_tx.h           | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwiobase.h  | 0
 .../staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwioreg_umac.h         | 0
 .../staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h     | 0
 {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_version.h       | 0
 564 files changed, 0 insertions(+), 0 deletions(-)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/HALcomdef.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/HALhwio.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/ack_report.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/boron_top_reg.h (100%)
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 rename {hw => drivers/staging/fw-api/hw}/fig/v1/ce_src_desc.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/ce_stat_desc.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/coex_rx_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/coex_tx_req.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/coex_tx_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/com_dtypes.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/eht_sig_usr_mu_mimo_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/eht_sig_usr_ofdma_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/eht_sig_usr_su_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/expected_response.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_mu_dl_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_mu_ul_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_a_su_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b1_mu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b2_mu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/he_sig_b2_ofdma_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/ht_sig_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/l_sig_a_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/l_sig_b_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/macrx_abort_request_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/mactx_eht_sig_usr_mu_mimo.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/mactx_eht_sig_usr_ofdma.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/mactx_eht_sig_usr_su.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/fig/v1/mactx_he_sig_a_mu_dl.h (100%)
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 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/eht_sig_usr_ofdma_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/eht_sig_usr_su_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/expected_response.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_a_mu_dl_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_a_mu_ul_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_a_su_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_b1_mu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_b2_mu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/he_sig_b2_ofdma_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/ht_sig_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/l_sig_a_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/l_sig_b_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/macrx_abort_request_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_eht_sig_usr_ofdma.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_eht_sig_usr_su.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_a_mu_dl.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_a_mu_ul.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_a_su.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_b1_mu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_b2_mu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_he_sig_b2_ofdma.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_ht_sig.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_l_sig_a.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_l_sig_b.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_phy_desc.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_u_sig_eht_su_mu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_u_sig_eht_tb.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_user_desc_common.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_user_desc_per_user.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_a.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_mu160.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_mu20.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_mu40.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_mu80.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_su160.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_su20.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_su40.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mactx_vht_sig_b_su80.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mlo_sta_id_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mon_buffer_addr.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mon_destination_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mon_drop.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/mon_ingress_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/msmhwiobase.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/msmhwioreg.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/no_ack_report.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/ofdma_trigger_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/pcu_ppdu_setup_init.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/pdg_response.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/pdg_response_rate_setting.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/pdg_tx_req.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_abort_request_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_common_user_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_a_mu_dl.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_a_mu_ul.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_a_su.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_b1_mu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_b2_mu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_he_sig_b2_ofdma.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_ht_sig.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_l_sig_a.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_l_sig_b.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_location.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_other_receive_info_ru_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_pkt_end.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_pkt_end_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_rssi_legacy.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_user_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phyrx_vht_sig_a.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phytx_abort_request_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phytx_pkt_end.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/phytx_ppdu_header_info_request.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/receive_pkt_start_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/receive_rssi_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/receive_user_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_15_8.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_23_16.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_31_24.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_36_32.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_7_0.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_response_user_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_trigger_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/received_trigger_info_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/reo_destination_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/reo_destination_ring_with_pn.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/reo_entrance_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/response_end_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/response_start_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/ru_allocation_160_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_attention.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_flow_search_entry.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_frame_1k_bitmap_ack.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_frame_bitmap_ack.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_frame_bitmap_req.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_location_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_desc_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_end.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_ext_desc_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_link_ptr.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_mpdu_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_desc_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_details.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_end.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_ext_desc_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_link.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_msdu_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_ack_report.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_end_user_stats.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_end_user_stats_ext.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_no_ack_report.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_ppdu_start_user_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_preamble.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_response_required_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_rxpcu_classification_overview.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_start_param.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_timing_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rx_trig_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rxpcu_early_rx_indication.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rxpcu_ppdu_end_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rxpcu_ppdu_end_layout_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/rxpt_classify_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/seq_hwio.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tcl_assist_cmd.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tcl_status_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tlv_hdr.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tlv_tag_def.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tqm2sw_completion_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_cbf_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_setup.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_1k_ba.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_ack_or_ba.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_end.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_prot.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start_ppdu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_start_prot.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_user_ppdu.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_fes_status_user_response.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_flush_req.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_mpdu_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_msdu_extension.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_msdu_start.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_peer_entry.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_queue_extension.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_rate_stats_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/tx_raw_or_native_frame_setup.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/txpcu_buffer_basics.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/txpcu_buffer_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/txpcu_user_buffer_status.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/u_sig_eht_su_mu_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/u_sig_eht_tb_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/unallocated_ru_160_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/uniform_descriptor_header.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_a_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu160_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu20_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu40_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_mu80_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su160_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su20_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su40_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/vht_sig_b_su80_info.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm2sw_completion_ring_rx.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_buffer_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_link_descriptor_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_release_ring.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_release_ring_rx.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wbm_release_ring_tx.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwiobase.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwioreg_umac.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h (100%)
 rename {hw => drivers/staging/fw-api/hw}/wcn8750/v1/wcss_version.h (100%)

diff --git a/hw/fig/v1/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h
similarity index 100%
rename from hw/fig/v1/HALcomdef.h
rename to drivers/staging/fw-api/hw/fig/v1/HALcomdef.h
diff --git a/hw/fig/v1/HALhwio.h b/drivers/staging/fw-api/hw/fig/v1/HALhwio.h
similarity index 100%
rename from hw/fig/v1/HALhwio.h
rename to drivers/staging/fw-api/hw/fig/v1/HALhwio.h
diff --git a/hw/fig/v1/ack_report.h b/drivers/staging/fw-api/hw/fig/v1/ack_report.h
similarity index 100%
rename from hw/fig/v1/ack_report.h
rename to drivers/staging/fw-api/hw/fig/v1/ack_report.h
diff --git a/hw/fig/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h
similarity index 100%
rename from hw/fig/v1/boron_top_reg.h
rename to drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h
diff --git a/hw/fig/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h
similarity index 100%
rename from hw/fig/v1/buffer_addr_info.h
rename to drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h
diff --git a/hw/fig/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h
similarity index 100%
rename from hw/fig/v1/ce_src_desc.h
rename to drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h
diff --git a/hw/fig/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h
similarity index 100%
rename from hw/fig/v1/ce_stat_desc.h
rename to drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h
diff --git a/hw/fig/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h
similarity index 100%
rename from hw/fig/v1/coex_rx_status.h
rename to drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h
diff --git a/hw/fig/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h
similarity index 100%
rename from hw/fig/v1/coex_tx_req.h
rename to drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h
diff --git a/hw/fig/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h
similarity index 100%
rename from hw/fig/v1/coex_tx_status.h
rename to drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h
diff --git a/hw/fig/v1/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h
similarity index 100%
rename from hw/fig/v1/com_dtypes.h
rename to drivers/staging/fw-api/hw/fig/v1/com_dtypes.h
diff --git a/hw/fig/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h
similarity index 100%
rename from hw/fig/v1/eht_sig_usr_mu_mimo_info.h
rename to drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h
diff --git a/hw/fig/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h
similarity index 100%
rename from hw/fig/v1/eht_sig_usr_ofdma_info.h
rename to drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h
diff --git a/hw/fig/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h
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rename from hw/fig/v1/eht_sig_usr_su_info.h
rename to drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h
diff --git a/hw/fig/v1/expected_response.h b/drivers/staging/fw-api/hw/fig/v1/expected_response.h
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rename from hw/fig/v1/expected_response.h
rename to drivers/staging/fw-api/hw/fig/v1/expected_response.h
diff --git a/hw/fig/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h
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rename from hw/fig/v1/he_sig_a_mu_dl_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h
diff --git a/hw/fig/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h
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rename from hw/fig/v1/he_sig_a_mu_ul_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h
diff --git a/hw/fig/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h
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rename from hw/fig/v1/he_sig_a_su_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h
diff --git a/hw/fig/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h
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rename from hw/fig/v1/he_sig_b1_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h
diff --git a/hw/fig/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h
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rename from hw/fig/v1/he_sig_b2_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h
diff --git a/hw/fig/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h
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rename from hw/fig/v1/he_sig_b2_ofdma_info.h
rename to drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h
diff --git a/hw/fig/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h
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rename from hw/fig/v1/ht_sig_info.h
rename to drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h
diff --git a/hw/fig/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h
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rename from hw/fig/v1/l_sig_a_info.h
rename to drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h
diff --git a/hw/fig/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h
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rename from hw/fig/v1/l_sig_b_info.h
rename to drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h
diff --git a/hw/fig/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h
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rename from hw/fig/v1/macrx_abort_request_info.h
rename to drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h
diff --git a/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
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rename from hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h
diff --git a/hw/fig/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h
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rename from hw/fig/v1/mactx_eht_sig_usr_ofdma.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h
diff --git a/hw/fig/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h
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rename from hw/fig/v1/mactx_eht_sig_usr_su.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h
diff --git a/hw/fig/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h
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rename from hw/fig/v1/mactx_he_sig_a_mu_dl.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h
diff --git a/hw/fig/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h
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rename from hw/fig/v1/mactx_he_sig_a_mu_ul.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h
diff --git a/hw/fig/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h
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rename from hw/fig/v1/mactx_he_sig_a_su.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h
diff --git a/hw/fig/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h
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rename from hw/fig/v1/mactx_he_sig_b1_mu.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h
diff --git a/hw/fig/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h
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rename from hw/fig/v1/mactx_he_sig_b2_mu.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h
diff --git a/hw/fig/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h
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rename from hw/fig/v1/mactx_he_sig_b2_ofdma.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h
diff --git a/hw/fig/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h
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rename from hw/fig/v1/mactx_ht_sig.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h
diff --git a/hw/fig/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h
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rename from hw/fig/v1/mactx_l_sig_a.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h
diff --git a/hw/fig/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h
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rename from hw/fig/v1/mactx_l_sig_b.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h
diff --git a/hw/fig/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h
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rename from hw/fig/v1/mactx_phy_desc.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h
diff --git a/hw/fig/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h
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rename from hw/fig/v1/mactx_u_sig_eht_su_mu.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h
diff --git a/hw/fig/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h
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rename from hw/fig/v1/mactx_u_sig_eht_tb.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h
diff --git a/hw/fig/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h
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rename from hw/fig/v1/mactx_user_desc_common.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h
diff --git a/hw/fig/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h
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rename from hw/fig/v1/mactx_user_desc_per_user.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h
diff --git a/hw/fig/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h
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rename from hw/fig/v1/mactx_vht_sig_a.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h
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rename from hw/fig/v1/mactx_vht_sig_b_mu160.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h
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rename from hw/fig/v1/mactx_vht_sig_b_mu20.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h
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rename from hw/fig/v1/mactx_vht_sig_b_mu40.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h
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rename from hw/fig/v1/mactx_vht_sig_b_mu80.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h
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rename from hw/fig/v1/mactx_vht_sig_b_su160.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h
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rename from hw/fig/v1/mactx_vht_sig_b_su20.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h
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rename from hw/fig/v1/mactx_vht_sig_b_su40.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h
diff --git a/hw/fig/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h
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rename from hw/fig/v1/mactx_vht_sig_b_su80.h
rename to drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h
diff --git a/hw/fig/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h
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rename from hw/fig/v1/mlo_sta_id_details.h
rename to drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h
diff --git a/hw/fig/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h
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rename from hw/fig/v1/mon_buffer_addr.h
rename to drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h
diff --git a/hw/fig/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h
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rename from hw/fig/v1/mon_destination_ring.h
rename to drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h
diff --git a/hw/fig/v1/mon_drop.h b/drivers/staging/fw-api/hw/fig/v1/mon_drop.h
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rename from hw/fig/v1/mon_drop.h
rename to drivers/staging/fw-api/hw/fig/v1/mon_drop.h
diff --git a/hw/fig/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h
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rename from hw/fig/v1/mon_ingress_ring.h
rename to drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h
diff --git a/hw/fig/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h
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diff --git a/hw/fig/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h
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diff --git a/hw/fig/v1/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h
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diff --git a/hw/fig/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h
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diff --git a/hw/fig/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h
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rename from hw/fig/v1/pcu_ppdu_setup_init.h
rename to drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h
diff --git a/hw/fig/v1/pdg_response.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response.h
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diff --git a/hw/fig/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h
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rename from hw/fig/v1/pdg_response_rate_setting.h
rename to drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h
diff --git a/hw/fig/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h
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rename to drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h
diff --git a/hw/fig/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h
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rename from hw/fig/v1/phyrx_abort_request_info.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h
diff --git a/hw/fig/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h
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rename from hw/fig/v1/phyrx_common_user_info.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h
diff --git a/hw/fig/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h
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rename from hw/fig/v1/phyrx_he_sig_a_mu_dl.h
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diff --git a/hw/fig/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h
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rename from hw/fig/v1/phyrx_he_sig_a_mu_ul.h
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diff --git a/hw/fig/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h
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rename from hw/fig/v1/phyrx_he_sig_a_su.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h
diff --git a/hw/fig/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h
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rename from hw/fig/v1/phyrx_he_sig_b1_mu.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h
diff --git a/hw/fig/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h
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rename from hw/fig/v1/phyrx_he_sig_b2_mu.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h
diff --git a/hw/fig/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h
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rename from hw/fig/v1/phyrx_he_sig_b2_ofdma.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h
diff --git a/hw/fig/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h
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rename from hw/fig/v1/phyrx_ht_sig.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h
diff --git a/hw/fig/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h
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rename from hw/fig/v1/phyrx_l_sig_a.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h
diff --git a/hw/fig/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h
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rename from hw/fig/v1/phyrx_l_sig_b.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h
diff --git a/hw/fig/v1/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h
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rename from hw/fig/v1/phyrx_location.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_location.h
diff --git a/hw/fig/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h
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rename from hw/fig/v1/phyrx_other_receive_info_ru_details.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h
diff --git a/hw/fig/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h
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rename from hw/fig/v1/phyrx_pkt_end.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h
diff --git a/hw/fig/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h
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rename from hw/fig/v1/phyrx_pkt_end_info.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h
diff --git a/hw/fig/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h
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rename from hw/fig/v1/phyrx_rssi_legacy.h
rename to drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h
diff --git a/hw/fig/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h
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diff --git a/hw/fig/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h
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rename from hw/fig/v1/tx_fes_status_user_response.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h
diff --git a/hw/fig/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h
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rename from hw/fig/v1/tx_flush_req.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h
diff --git a/hw/fig/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h
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rename from hw/fig/v1/tx_mpdu_start.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h
diff --git a/hw/fig/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h
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rename from hw/fig/v1/tx_msdu_extension.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h
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rename from hw/fig/v1/tx_msdu_start.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h
diff --git a/hw/fig/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h
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rename from hw/fig/v1/tx_peer_entry.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h
diff --git a/hw/fig/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h
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rename from hw/fig/v1/tx_queue_extension.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h
diff --git a/hw/fig/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h
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rename from hw/fig/v1/tx_rate_stats_info.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h
diff --git a/hw/fig/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h
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rename from hw/fig/v1/tx_raw_or_native_frame_setup.h
rename to drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h
diff --git a/hw/fig/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h
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rename from hw/fig/v1/txpcu_buffer_basics.h
rename to drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h
diff --git a/hw/fig/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h
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rename from hw/fig/v1/txpcu_buffer_status.h
rename to drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h
diff --git a/hw/fig/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h
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rename from hw/fig/v1/txpcu_user_buffer_status.h
rename to drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h
diff --git a/hw/fig/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h
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rename from hw/fig/v1/u_sig_eht_su_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h
diff --git a/hw/fig/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h
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rename from hw/fig/v1/u_sig_eht_tb_info.h
rename to drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h
diff --git a/hw/fig/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h
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rename from hw/fig/v1/unallocated_ru_160_info.h
rename to drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h
diff --git a/hw/fig/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h
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rename from hw/fig/v1/uniform_descriptor_header.h
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diff --git a/hw/fig/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h
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rename from hw/fig/v1/vht_sig_a_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h
diff --git a/hw/fig/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h
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rename from hw/fig/v1/vht_sig_b_mu160_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h
diff --git a/hw/fig/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h
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rename from hw/fig/v1/vht_sig_b_mu20_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h
diff --git a/hw/fig/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h
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rename from hw/fig/v1/vht_sig_b_mu40_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h
diff --git a/hw/fig/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h
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rename from hw/fig/v1/vht_sig_b_mu80_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h
diff --git a/hw/fig/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h
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rename from hw/fig/v1/vht_sig_b_su160_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h
diff --git a/hw/fig/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h
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rename from hw/fig/v1/vht_sig_b_su20_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h
diff --git a/hw/fig/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h
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rename from hw/fig/v1/vht_sig_b_su40_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h
diff --git a/hw/fig/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h
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rename from hw/fig/v1/vht_sig_b_su80_info.h
rename to drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h
diff --git a/hw/fig/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h
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rename from hw/fig/v1/wbm2sw_completion_ring_rx.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h
diff --git a/hw/fig/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h
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rename from hw/fig/v1/wbm_buffer_ring.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h
diff --git a/hw/fig/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h
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rename from hw/fig/v1/wbm_link_descriptor_ring.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h
diff --git a/hw/fig/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h
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rename from hw/fig/v1/wbm_release_ring.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h
diff --git a/hw/fig/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h
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rename from hw/fig/v1/wbm_release_ring_rx.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h
diff --git a/hw/fig/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h
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rename from hw/fig/v1/wbm_release_ring_tx.h
rename to drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h
diff --git a/hw/fig/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h
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rename from hw/fig/v1/wcss_seq_hwiobase.h
rename to drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h
diff --git a/hw/fig/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h
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rename from hw/fig/v1/wcss_seq_hwioreg_umac.h
rename to drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h
diff --git a/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
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rename from hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
rename to drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h
diff --git a/hw/fig/v1/wcss_version.h b/drivers/staging/fw-api/hw/fig/v1/wcss_version.h
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rename from hw/fig/v1/wcss_version.h
rename to drivers/staging/fw-api/hw/fig/v1/wcss_version.h
diff --git a/hw/fig/v2/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h
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rename from hw/fig/v2/HALcomdef.h
rename to drivers/staging/fw-api/hw/fig/v2/HALcomdef.h
diff --git a/hw/fig/v2/HALhwio.h b/drivers/staging/fw-api/hw/fig/v2/HALhwio.h
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rename from hw/fig/v2/HALhwio.h
rename to drivers/staging/fw-api/hw/fig/v2/HALhwio.h
diff --git a/hw/fig/v2/ack_report.h b/drivers/staging/fw-api/hw/fig/v2/ack_report.h
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rename from hw/fig/v2/ack_report.h
rename to drivers/staging/fw-api/hw/fig/v2/ack_report.h
diff --git a/hw/fig/v2/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h
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rename from hw/fig/v2/boron_top_reg.h
rename to drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h
diff --git a/hw/fig/v2/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h
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rename from hw/fig/v2/buffer_addr_info.h
rename to drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h
diff --git a/hw/fig/v2/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h
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rename from hw/fig/v2/ce_src_desc.h
rename to drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h
diff --git a/hw/fig/v2/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h
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rename from hw/fig/v2/ce_stat_desc.h
rename to drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h
diff --git a/hw/fig/v2/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h
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rename from hw/fig/v2/coex_rx_status.h
rename to drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h
diff --git a/hw/fig/v2/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h
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rename from hw/fig/v2/coex_tx_req.h
rename to drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h
diff --git a/hw/fig/v2/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h
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rename from hw/fig/v2/coex_tx_status.h
rename to drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h
diff --git a/hw/fig/v2/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h
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rename from hw/fig/v2/com_dtypes.h
rename to drivers/staging/fw-api/hw/fig/v2/com_dtypes.h
diff --git a/hw/fig/v2/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h
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rename from hw/fig/v2/eht_sig_usr_mu_mimo_info.h
rename to drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h
diff --git a/hw/fig/v2/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h
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rename from hw/fig/v2/eht_sig_usr_ofdma_info.h
rename to drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h
diff --git a/hw/fig/v2/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h
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rename from hw/fig/v2/eht_sig_usr_su_info.h
rename to drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h
diff --git a/hw/fig/v2/expected_response.h b/drivers/staging/fw-api/hw/fig/v2/expected_response.h
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rename from hw/fig/v2/expected_response.h
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diff --git a/hw/fig/v2/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h
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rename from hw/fig/v2/he_sig_a_mu_dl_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h
diff --git a/hw/fig/v2/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h
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rename from hw/fig/v2/he_sig_a_mu_ul_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h
diff --git a/hw/fig/v2/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h
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rename from hw/fig/v2/he_sig_a_su_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h
diff --git a/hw/fig/v2/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h
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rename from hw/fig/v2/he_sig_b1_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h
diff --git a/hw/fig/v2/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h
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rename from hw/fig/v2/he_sig_b2_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h
diff --git a/hw/fig/v2/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h
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rename from hw/fig/v2/he_sig_b2_ofdma_info.h
rename to drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h
diff --git a/hw/fig/v2/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h
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rename from hw/fig/v2/ht_sig_info.h
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diff --git a/hw/fig/v2/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h
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rename from hw/fig/v2/l_sig_a_info.h
rename to drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h
diff --git a/hw/fig/v2/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h
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rename from hw/fig/v2/l_sig_b_info.h
rename to drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h
diff --git a/hw/fig/v2/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h
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rename from hw/fig/v2/macrx_abort_request_info.h
rename to drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h
diff --git a/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
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rename from hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h
diff --git a/hw/fig/v2/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h
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rename from hw/fig/v2/mactx_eht_sig_usr_ofdma.h
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diff --git a/hw/fig/v2/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h
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rename from hw/fig/v2/mactx_eht_sig_usr_su.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h
diff --git a/hw/fig/v2/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h
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rename from hw/fig/v2/mactx_he_sig_a_mu_dl.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h
diff --git a/hw/fig/v2/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h
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rename from hw/fig/v2/mactx_he_sig_a_mu_ul.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h
diff --git a/hw/fig/v2/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h
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rename from hw/fig/v2/mactx_he_sig_a_su.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h
diff --git a/hw/fig/v2/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h
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rename from hw/fig/v2/mactx_he_sig_b1_mu.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h
diff --git a/hw/fig/v2/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h
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rename from hw/fig/v2/mactx_he_sig_b2_mu.h
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diff --git a/hw/fig/v2/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h
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rename from hw/fig/v2/mactx_he_sig_b2_ofdma.h
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diff --git a/hw/fig/v2/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h
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rename to drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h
diff --git a/hw/fig/v2/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h
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rename from hw/fig/v2/mactx_l_sig_a.h
rename to drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h
diff --git a/hw/fig/v2/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h
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rename to drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h
diff --git a/hw/fig/v2/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h
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diff --git a/hw/fig/v2/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h
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diff --git a/hw/fig/v2/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h
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diff --git a/hw/fig/v2/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h
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rename to drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h
diff --git a/hw/fig/v2/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h
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diff --git a/hw/fig/v2/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h
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rename to drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h
diff --git a/hw/fig/v2/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h
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rename from hw/fig/v2/mactx_vht_sig_b_mu80.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h
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rename from hw/fig/v2/mactx_vht_sig_b_su160.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h
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rename from hw/fig/v2/mactx_vht_sig_b_su40.h
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diff --git a/hw/fig/v2/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h
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rename from hw/fig/v2/mactx_vht_sig_b_su80.h
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diff --git a/hw/fig/v2/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h
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rename to drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h
diff --git a/hw/fig/v2/mon_drop.h b/drivers/staging/fw-api/hw/fig/v2/mon_drop.h
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diff --git a/hw/fig/v2/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h
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diff --git a/hw/fig/v2/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h
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diff --git a/hw/fig/v2/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h
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diff --git a/hw/fig/v2/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h
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diff --git a/hw/fig/v2/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h
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diff --git a/hw/fig/v2/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h
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rename to drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h
diff --git a/hw/fig/v2/pdg_response.h b/drivers/staging/fw-api/hw/fig/v2/pdg_response.h
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rename to drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h
diff --git a/hw/fig/v2/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h
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diff --git a/hw/fig/v2/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h
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rename to drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h
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rename to drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h
diff --git a/hw/fig/v2/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h
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diff --git a/hw/fig/v2/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h
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diff --git a/hw/fig/v2/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h
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rename to drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h
diff --git a/hw/fig/v2/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h
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rename from hw/fig/v2/phyrx_he_sig_b1_mu.h
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diff --git a/hw/fig/v2/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h
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rename from hw/fig/v2/phyrx_he_sig_b2_mu.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h
diff --git a/hw/fig/v2/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h
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rename from hw/fig/v2/phyrx_he_sig_b2_ofdma.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h
diff --git a/hw/fig/v2/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h
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rename from hw/fig/v2/phyrx_ht_sig.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h
diff --git a/hw/fig/v2/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h
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rename from hw/fig/v2/phyrx_l_sig_a.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h
diff --git a/hw/fig/v2/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h
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rename from hw/fig/v2/phyrx_l_sig_b.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h
diff --git a/hw/fig/v2/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h
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rename from hw/fig/v2/phyrx_location.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_location.h
diff --git a/hw/fig/v2/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h
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rename from hw/fig/v2/phyrx_other_receive_info_ru_details.h
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diff --git a/hw/fig/v2/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h
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diff --git a/hw/fig/v2/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h
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rename from hw/fig/v2/phyrx_rssi_legacy.h
rename to drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h
diff --git a/hw/fig/v2/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h
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rename to drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h
diff --git a/hw/fig/v2/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h
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rename to drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h
diff --git a/hw/fig/v2/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h
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diff --git a/hw/fig/v2/phytx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h
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diff --git a/hw/fig/v2/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h
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diff --git a/hw/fig/v2/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h
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rename to drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h
diff --git a/hw/fig/v2/receive_rssi_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h
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diff --git a/hw/fig/v2/receive_user_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h
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diff --git a/hw/fig/v2/received_response_user_15_8.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h
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rename to drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h
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rename to drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h
diff --git a/hw/fig/v2/received_response_user_31_24.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h
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rename to drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h
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diff --git a/hw/fig/v2/received_response_user_info.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h
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diff --git a/hw/fig/v2/received_trigger_info.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h
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diff --git a/hw/fig/v2/received_trigger_info_details.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h
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rename from hw/fig/v2/received_trigger_info_details.h
rename to drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h
diff --git a/hw/fig/v2/reo_destination_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h
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diff --git a/hw/fig/v2/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h
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rename to drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h
diff --git a/hw/fig/v2/reo_entrance_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h
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diff --git a/hw/fig/v2/response_end_status.h b/drivers/staging/fw-api/hw/fig/v2/response_end_status.h
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diff --git a/hw/fig/v2/response_start_status.h b/drivers/staging/fw-api/hw/fig/v2/response_start_status.h
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diff --git a/hw/fig/v2/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h
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diff --git a/hw/fig/v2/rx_attention.h b/drivers/staging/fw-api/hw/fig/v2/rx_attention.h
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rename to drivers/staging/fw-api/hw/fig/v2/rx_attention.h
diff --git a/hw/fig/v2/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h
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diff --git a/hw/fig/v2/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h
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rename from hw/fig/v2/rx_frame_bitmap_ack.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h
diff --git a/hw/fig/v2/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h
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rename from hw/fig/v2/rx_frame_bitmap_req.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h
diff --git a/hw/fig/v2/rx_location_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h
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rename from hw/fig/v2/rx_location_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_location_info.h
diff --git a/hw/fig/v2/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h
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rename from hw/fig/v2/rx_mpdu_desc_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h
diff --git a/hw/fig/v2/rx_mpdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h
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rename from hw/fig/v2/rx_mpdu_details.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h
diff --git a/hw/fig/v2/rx_mpdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h
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rename from hw/fig/v2/rx_mpdu_end.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h
diff --git a/hw/fig/v2/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h
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rename from hw/fig/v2/rx_mpdu_ext_desc_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h
diff --git a/hw/fig/v2/rx_mpdu_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h
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rename from hw/fig/v2/rx_mpdu_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h
diff --git a/hw/fig/v2/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h
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rename from hw/fig/v2/rx_mpdu_link_ptr.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h
diff --git a/hw/fig/v2/rx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h
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rename from hw/fig/v2/rx_mpdu_start.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h
diff --git a/hw/fig/v2/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h
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rename from hw/fig/v2/rx_msdu_desc_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h
diff --git a/hw/fig/v2/rx_msdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h
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rename from hw/fig/v2/rx_msdu_details.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h
diff --git a/hw/fig/v2/rx_msdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h
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rename from hw/fig/v2/rx_msdu_end.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h
diff --git a/hw/fig/v2/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h
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rename from hw/fig/v2/rx_msdu_ext_desc_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h
diff --git a/hw/fig/v2/rx_msdu_link.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h
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rename from hw/fig/v2/rx_msdu_link.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h
diff --git a/hw/fig/v2/rx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h
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rename from hw/fig/v2/rx_msdu_start.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h
diff --git a/hw/fig/v2/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h
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rename from hw/fig/v2/rx_ppdu_ack_report.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h
diff --git a/hw/fig/v2/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h
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rename from hw/fig/v2/rx_ppdu_end_user_stats.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h
diff --git a/hw/fig/v2/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h
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rename from hw/fig/v2/rx_ppdu_end_user_stats_ext.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h
diff --git a/hw/fig/v2/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h
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rename from hw/fig/v2/rx_ppdu_no_ack_report.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h
diff --git a/hw/fig/v2/rx_ppdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h
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rename from hw/fig/v2/rx_ppdu_start.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h
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rename from hw/fig/v2/rx_ppdu_start_user_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h
diff --git a/hw/fig/v2/rx_preamble.h b/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h
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rename from hw/fig/v2/rx_preamble.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_preamble.h
diff --git a/hw/fig/v2/rx_response_required_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h
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rename from hw/fig/v2/rx_response_required_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h
diff --git a/hw/fig/v2/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h
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rename from hw/fig/v2/rx_rxpcu_classification_overview.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h
diff --git a/hw/fig/v2/rx_start_param.h b/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h
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rename from hw/fig/v2/rx_start_param.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_start_param.h
diff --git a/hw/fig/v2/rx_timing_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h
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rename from hw/fig/v2/rx_timing_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h
diff --git a/hw/fig/v2/rx_trig_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h
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rename from hw/fig/v2/rx_trig_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h
diff --git a/hw/fig/v2/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h
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rename from hw/fig/v2/rxpcu_early_rx_indication.h
rename to drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h
diff --git a/hw/fig/v2/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h
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rename from hw/fig/v2/rxpcu_ppdu_end_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h
diff --git a/hw/fig/v2/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h
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rename from hw/fig/v2/rxpcu_ppdu_end_layout_info.h
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diff --git a/hw/fig/v2/rxpt_classify_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h
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rename from hw/fig/v2/rxpt_classify_info.h
rename to drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h
diff --git a/hw/fig/v2/seq_hwio.h b/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h
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rename from hw/fig/v2/seq_hwio.h
rename to drivers/staging/fw-api/hw/fig/v2/seq_hwio.h
diff --git a/hw/fig/v2/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h
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rename from hw/fig/v2/tcl_assist_cmd.h
rename to drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h
diff --git a/hw/fig/v2/tcl_status_ring.h b/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h
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rename from hw/fig/v2/tcl_status_ring.h
rename to drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h
diff --git a/hw/fig/v2/tlv_hdr.h b/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h
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rename from hw/fig/v2/tlv_hdr.h
rename to drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h
diff --git a/hw/fig/v2/tlv_tag_def.h b/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h
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rename from hw/fig/v2/tlv_tag_def.h
rename to drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h
diff --git a/hw/fig/v2/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h
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rename from hw/fig/v2/tqm2sw_completion_ring.h
rename to drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h
diff --git a/hw/fig/v2/tx_cbf_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h
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rename from hw/fig/v2/tx_cbf_info.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h
diff --git a/hw/fig/v2/tx_fes_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h
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rename from hw/fig/v2/tx_fes_setup.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h
diff --git a/hw/fig/v2/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h
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rename from hw/fig/v2/tx_fes_status_1k_ba.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h
diff --git a/hw/fig/v2/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h
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rename from hw/fig/v2/tx_fes_status_ack_or_ba.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h
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rename from hw/fig/v2/tx_fes_status_end.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h
diff --git a/hw/fig/v2/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h
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rename from hw/fig/v2/tx_fes_status_prot.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h
diff --git a/hw/fig/v2/tx_fes_status_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h
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rename from hw/fig/v2/tx_fes_status_start.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h
diff --git a/hw/fig/v2/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h
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rename from hw/fig/v2/tx_fes_status_start_ppdu.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h
diff --git a/hw/fig/v2/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h
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rename from hw/fig/v2/tx_fes_status_start_prot.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h
diff --git a/hw/fig/v2/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h
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rename from hw/fig/v2/tx_fes_status_user_ppdu.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h
diff --git a/hw/fig/v2/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h
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rename from hw/fig/v2/tx_fes_status_user_response.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h
diff --git a/hw/fig/v2/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h
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rename from hw/fig/v2/tx_flush_req.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h
diff --git a/hw/fig/v2/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h
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rename from hw/fig/v2/tx_mpdu_start.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h
diff --git a/hw/fig/v2/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h
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rename from hw/fig/v2/tx_msdu_extension.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h
diff --git a/hw/fig/v2/tx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h
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rename from hw/fig/v2/tx_msdu_start.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h
diff --git a/hw/fig/v2/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h
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rename from hw/fig/v2/tx_peer_entry.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h
diff --git a/hw/fig/v2/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h
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rename from hw/fig/v2/tx_queue_extension.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h
diff --git a/hw/fig/v2/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h
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rename from hw/fig/v2/tx_rate_stats_info.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h
diff --git a/hw/fig/v2/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h
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rename from hw/fig/v2/tx_raw_or_native_frame_setup.h
rename to drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h
diff --git a/hw/fig/v2/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h
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rename from hw/fig/v2/txpcu_buffer_basics.h
rename to drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h
diff --git a/hw/fig/v2/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h
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rename from hw/fig/v2/txpcu_buffer_status.h
rename to drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h
diff --git a/hw/fig/v2/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h
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rename from hw/fig/v2/txpcu_user_buffer_status.h
rename to drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h
diff --git a/hw/fig/v2/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h
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rename from hw/fig/v2/u_sig_eht_su_mu_info.h
rename to drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h
diff --git a/hw/fig/v2/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h
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rename from hw/fig/v2/u_sig_eht_tb_info.h
rename to drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h
diff --git a/hw/fig/v2/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h
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rename from hw/fig/v2/unallocated_ru_160_info.h
rename to drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h
diff --git a/hw/fig/v2/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h
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rename from hw/fig/v2/uniform_descriptor_header.h
rename to drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h
diff --git a/hw/fig/v2/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h
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rename from hw/fig/v2/vht_sig_a_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h
diff --git a/hw/fig/v2/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h
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rename from hw/fig/v2/vht_sig_b_mu160_info.h
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diff --git a/hw/fig/v2/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h
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rename from hw/fig/v2/vht_sig_b_mu20_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h
diff --git a/hw/fig/v2/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h
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rename from hw/fig/v2/vht_sig_b_mu40_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h
diff --git a/hw/fig/v2/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h
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rename from hw/fig/v2/vht_sig_b_mu80_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h
diff --git a/hw/fig/v2/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h
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rename from hw/fig/v2/vht_sig_b_su160_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h
diff --git a/hw/fig/v2/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h
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rename from hw/fig/v2/vht_sig_b_su20_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h
diff --git a/hw/fig/v2/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h
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rename from hw/fig/v2/vht_sig_b_su40_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h
diff --git a/hw/fig/v2/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h
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rename from hw/fig/v2/vht_sig_b_su80_info.h
rename to drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h
diff --git a/hw/fig/v2/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h
similarity index 100%
rename from hw/fig/v2/wbm2sw_completion_ring_rx.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h
diff --git a/hw/fig/v2/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h
similarity index 100%
rename from hw/fig/v2/wbm_buffer_ring.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h
diff --git a/hw/fig/v2/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h
similarity index 100%
rename from hw/fig/v2/wbm_link_descriptor_ring.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h
diff --git a/hw/fig/v2/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h
similarity index 100%
rename from hw/fig/v2/wbm_release_ring.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h
diff --git a/hw/fig/v2/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h
similarity index 100%
rename from hw/fig/v2/wbm_release_ring_rx.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h
diff --git a/hw/fig/v2/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h
similarity index 100%
rename from hw/fig/v2/wbm_release_ring_tx.h
rename to drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h
diff --git a/hw/fig/v2/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h
similarity index 100%
rename from hw/fig/v2/wcss_seq_hwiobase.h
rename to drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h
diff --git a/hw/fig/v2/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h
similarity index 100%
rename from hw/fig/v2/wcss_seq_hwioreg_umac.h
rename to drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h
diff --git a/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h
similarity index 100%
rename from hw/fig/v2/wcss_seq_hwioreg_wifi_top.h
rename to drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h
diff --git a/hw/fig/v2/wcss_version.h b/drivers/staging/fw-api/hw/fig/v2/wcss_version.h
similarity index 100%
rename from hw/fig/v2/wcss_version.h
rename to drivers/staging/fw-api/hw/fig/v2/wcss_version.h
diff --git a/hw/wcn8750/v1/HALcomdef.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h
similarity index 100%
rename from hw/wcn8750/v1/HALcomdef.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h
diff --git a/hw/wcn8750/v1/HALhwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h
similarity index 100%
rename from hw/wcn8750/v1/HALhwio.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h
diff --git a/hw/wcn8750/v1/ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h
similarity index 100%
rename from hw/wcn8750/v1/ack_report.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h
diff --git a/hw/wcn8750/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h
similarity index 100%
rename from hw/wcn8750/v1/boron_top_reg.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h
diff --git a/hw/wcn8750/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h
similarity index 100%
rename from hw/wcn8750/v1/buffer_addr_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h
diff --git a/hw/wcn8750/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h
similarity index 100%
rename from hw/wcn8750/v1/ce_src_desc.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h
diff --git a/hw/wcn8750/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h
similarity index 100%
rename from hw/wcn8750/v1/ce_stat_desc.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h
diff --git a/hw/wcn8750/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h
similarity index 100%
rename from hw/wcn8750/v1/coex_rx_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h
diff --git a/hw/wcn8750/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h
similarity index 100%
rename from hw/wcn8750/v1/coex_tx_req.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h
diff --git a/hw/wcn8750/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h
similarity index 100%
rename from hw/wcn8750/v1/coex_tx_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h
diff --git a/hw/wcn8750/v1/com_dtypes.h b/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h
similarity index 100%
rename from hw/wcn8750/v1/com_dtypes.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h
diff --git a/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
similarity index 100%
rename from hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h
diff --git a/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
similarity index 100%
rename from hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h
diff --git a/hw/wcn8750/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h
similarity index 100%
rename from hw/wcn8750/v1/eht_sig_usr_su_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h
diff --git a/hw/wcn8750/v1/expected_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h
similarity index 100%
rename from hw/wcn8750/v1/expected_response.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h
diff --git a/hw/wcn8750/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_a_mu_dl_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h
diff --git a/hw/wcn8750/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_a_mu_ul_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h
diff --git a/hw/wcn8750/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_a_su_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h
diff --git a/hw/wcn8750/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_b1_mu_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h
diff --git a/hw/wcn8750/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_b2_mu_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h
diff --git a/hw/wcn8750/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h
similarity index 100%
rename from hw/wcn8750/v1/he_sig_b2_ofdma_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h
diff --git a/hw/wcn8750/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h
similarity index 100%
rename from hw/wcn8750/v1/ht_sig_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h
diff --git a/hw/wcn8750/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h
similarity index 100%
rename from hw/wcn8750/v1/l_sig_a_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h
diff --git a/hw/wcn8750/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h
similarity index 100%
rename from hw/wcn8750/v1/l_sig_b_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h
diff --git a/hw/wcn8750/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h
similarity index 100%
rename from hw/wcn8750/v1/macrx_abort_request_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h
diff --git a/hw/wcn8750/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_eht_sig_usr_su.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_a_su.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_b1_mu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_b2_mu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h
diff --git a/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h
diff --git a/hw/wcn8750/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_ht_sig.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h
diff --git a/hw/wcn8750/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_l_sig_a.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h
diff --git a/hw/wcn8750/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_l_sig_b.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h
diff --git a/hw/wcn8750/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_phy_desc.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h
diff --git a/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h
diff --git a/hw/wcn8750/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_u_sig_eht_tb.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h
diff --git a/hw/wcn8750/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_user_desc_common.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h
diff --git a/hw/wcn8750/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_user_desc_per_user.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_a.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_su160.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_su20.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_su40.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h
diff --git a/hw/wcn8750/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h
similarity index 100%
rename from hw/wcn8750/v1/mactx_vht_sig_b_su80.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h
diff --git a/hw/wcn8750/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h
similarity index 100%
rename from hw/wcn8750/v1/mlo_sta_id_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h
diff --git a/hw/wcn8750/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h
similarity index 100%
rename from hw/wcn8750/v1/mon_buffer_addr.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h
diff --git a/hw/wcn8750/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h
similarity index 100%
rename from hw/wcn8750/v1/mon_destination_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h
diff --git a/hw/wcn8750/v1/mon_drop.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h
similarity index 100%
rename from hw/wcn8750/v1/mon_drop.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h
diff --git a/hw/wcn8750/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h
similarity index 100%
rename from hw/wcn8750/v1/mon_ingress_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h
diff --git a/hw/wcn8750/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h
similarity index 100%
rename from hw/wcn8750/v1/msmhwiobase.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h
diff --git a/hw/wcn8750/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h
similarity index 100%
rename from hw/wcn8750/v1/msmhwioreg.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h
diff --git a/hw/wcn8750/v1/no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h
similarity index 100%
rename from hw/wcn8750/v1/no_ack_report.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h
diff --git a/hw/wcn8750/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h
similarity index 100%
rename from hw/wcn8750/v1/ofdma_trigger_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h
diff --git a/hw/wcn8750/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h
similarity index 100%
rename from hw/wcn8750/v1/pcu_ppdu_setup_init.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h
diff --git a/hw/wcn8750/v1/pdg_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h
similarity index 100%
rename from hw/wcn8750/v1/pdg_response.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h
diff --git a/hw/wcn8750/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h
similarity index 100%
rename from hw/wcn8750/v1/pdg_response_rate_setting.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h
diff --git a/hw/wcn8750/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h
similarity index 100%
rename from hw/wcn8750/v1/pdg_tx_req.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h
diff --git a/hw/wcn8750/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_abort_request_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h
diff --git a/hw/wcn8750/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_common_user_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_a_su.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h
diff --git a/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h
diff --git a/hw/wcn8750/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_ht_sig.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h
diff --git a/hw/wcn8750/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_l_sig_a.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h
diff --git a/hw/wcn8750/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_l_sig_b.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h
diff --git a/hw/wcn8750/v1/phyrx_location.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_location.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h
diff --git a/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h
diff --git a/hw/wcn8750/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_pkt_end.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h
diff --git a/hw/wcn8750/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_pkt_end_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h
diff --git a/hw/wcn8750/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_rssi_legacy.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h
diff --git a/hw/wcn8750/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_user_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h
diff --git a/hw/wcn8750/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h
similarity index 100%
rename from hw/wcn8750/v1/phyrx_vht_sig_a.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h
diff --git a/hw/wcn8750/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h
similarity index 100%
rename from hw/wcn8750/v1/phytx_abort_request_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h
diff --git a/hw/wcn8750/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h
similarity index 100%
rename from hw/wcn8750/v1/phytx_pkt_end.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h
diff --git a/hw/wcn8750/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h
similarity index 100%
rename from hw/wcn8750/v1/phytx_ppdu_header_info_request.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h
diff --git a/hw/wcn8750/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h
similarity index 100%
rename from hw/wcn8750/v1/receive_pkt_start_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h
diff --git a/hw/wcn8750/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h
similarity index 100%
rename from hw/wcn8750/v1/receive_rssi_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h
diff --git a/hw/wcn8750/v1/receive_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h
similarity index 100%
rename from hw/wcn8750/v1/receive_user_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h
diff --git a/hw/wcn8750/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_15_8.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h
diff --git a/hw/wcn8750/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_23_16.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h
diff --git a/hw/wcn8750/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_31_24.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h
diff --git a/hw/wcn8750/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_36_32.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h
diff --git a/hw/wcn8750/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_7_0.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h
diff --git a/hw/wcn8750/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h
similarity index 100%
rename from hw/wcn8750/v1/received_response_user_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h
diff --git a/hw/wcn8750/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h
similarity index 100%
rename from hw/wcn8750/v1/received_trigger_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h
diff --git a/hw/wcn8750/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h
similarity index 100%
rename from hw/wcn8750/v1/received_trigger_info_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h
diff --git a/hw/wcn8750/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h
similarity index 100%
rename from hw/wcn8750/v1/reo_destination_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h
diff --git a/hw/wcn8750/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h
similarity index 100%
rename from hw/wcn8750/v1/reo_destination_ring_with_pn.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h
diff --git a/hw/wcn8750/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h
similarity index 100%
rename from hw/wcn8750/v1/reo_entrance_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h
diff --git a/hw/wcn8750/v1/response_end_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h
similarity index 100%
rename from hw/wcn8750/v1/response_end_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h
diff --git a/hw/wcn8750/v1/response_start_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h
similarity index 100%
rename from hw/wcn8750/v1/response_start_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h
diff --git a/hw/wcn8750/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h
similarity index 100%
rename from hw/wcn8750/v1/ru_allocation_160_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h
diff --git a/hw/wcn8750/v1/rx_attention.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h
similarity index 100%
rename from hw/wcn8750/v1/rx_attention.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h
diff --git a/hw/wcn8750/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h
similarity index 100%
rename from hw/wcn8750/v1/rx_flow_search_entry.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h
diff --git a/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
similarity index 100%
rename from hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h
diff --git a/hw/wcn8750/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h
similarity index 100%
rename from hw/wcn8750/v1/rx_frame_bitmap_ack.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h
diff --git a/hw/wcn8750/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h
similarity index 100%
rename from hw/wcn8750/v1/rx_frame_bitmap_req.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h
diff --git a/hw/wcn8750/v1/rx_location_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_location_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h
diff --git a/hw/wcn8750/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_desc_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h
diff --git a/hw/wcn8750/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h
diff --git a/hw/wcn8750/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_end.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h
diff --git a/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h
diff --git a/hw/wcn8750/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h
diff --git a/hw/wcn8750/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_link_ptr.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h
diff --git a/hw/wcn8750/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h
similarity index 100%
rename from hw/wcn8750/v1/rx_mpdu_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h
diff --git a/hw/wcn8750/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_desc_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h
diff --git a/hw/wcn8750/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_details.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h
diff --git a/hw/wcn8750/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_end.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h
diff --git a/hw/wcn8750/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_ext_desc_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h
diff --git a/hw/wcn8750/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_link.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h
diff --git a/hw/wcn8750/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h
similarity index 100%
rename from hw/wcn8750/v1/rx_msdu_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h
diff --git a/hw/wcn8750/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_ack_report.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h
diff --git a/hw/wcn8750/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_end_user_stats.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h
diff --git a/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h
diff --git a/hw/wcn8750/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_no_ack_report.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h
diff --git a/hw/wcn8750/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h
diff --git a/hw/wcn8750/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_ppdu_start_user_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h
diff --git a/hw/wcn8750/v1/rx_preamble.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h
similarity index 100%
rename from hw/wcn8750/v1/rx_preamble.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h
diff --git a/hw/wcn8750/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_response_required_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h
diff --git a/hw/wcn8750/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h
similarity index 100%
rename from hw/wcn8750/v1/rx_rxpcu_classification_overview.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h
diff --git a/hw/wcn8750/v1/rx_start_param.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h
similarity index 100%
rename from hw/wcn8750/v1/rx_start_param.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h
diff --git a/hw/wcn8750/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_timing_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h
diff --git a/hw/wcn8750/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h
similarity index 100%
rename from hw/wcn8750/v1/rx_trig_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h
diff --git a/hw/wcn8750/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h
similarity index 100%
rename from hw/wcn8750/v1/rxpcu_early_rx_indication.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h
diff --git a/hw/wcn8750/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h
similarity index 100%
rename from hw/wcn8750/v1/rxpcu_ppdu_end_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h
diff --git a/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
similarity index 100%
rename from hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h
diff --git a/hw/wcn8750/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h
similarity index 100%
rename from hw/wcn8750/v1/rxpt_classify_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h
diff --git a/hw/wcn8750/v1/seq_hwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h
similarity index 100%
rename from hw/wcn8750/v1/seq_hwio.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h
diff --git a/hw/wcn8750/v1/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h
similarity index 100%
rename from hw/wcn8750/v1/tcl_assist_cmd.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h
diff --git a/hw/wcn8750/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h
similarity index 100%
rename from hw/wcn8750/v1/tcl_status_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h
diff --git a/hw/wcn8750/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h
similarity index 100%
rename from hw/wcn8750/v1/tlv_hdr.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h
diff --git a/hw/wcn8750/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h
similarity index 100%
rename from hw/wcn8750/v1/tlv_tag_def.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h
diff --git a/hw/wcn8750/v1/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h
similarity index 100%
rename from hw/wcn8750/v1/tqm2sw_completion_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h
diff --git a/hw/wcn8750/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h
similarity index 100%
rename from hw/wcn8750/v1/tx_cbf_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h
diff --git a/hw/wcn8750/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_setup.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h
diff --git a/hw/wcn8750/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_1k_ba.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h
diff --git a/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h
diff --git a/hw/wcn8750/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_end.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h
diff --git a/hw/wcn8750/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_prot.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h
diff --git a/hw/wcn8750/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h
diff --git a/hw/wcn8750/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_start_ppdu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h
diff --git a/hw/wcn8750/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_start_prot.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h
diff --git a/hw/wcn8750/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_user_ppdu.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h
diff --git a/hw/wcn8750/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h
similarity index 100%
rename from hw/wcn8750/v1/tx_fes_status_user_response.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h
diff --git a/hw/wcn8750/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h
similarity index 100%
rename from hw/wcn8750/v1/tx_flush_req.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h
diff --git a/hw/wcn8750/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h
similarity index 100%
rename from hw/wcn8750/v1/tx_mpdu_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h
diff --git a/hw/wcn8750/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h
similarity index 100%
rename from hw/wcn8750/v1/tx_msdu_extension.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h
diff --git a/hw/wcn8750/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h
similarity index 100%
rename from hw/wcn8750/v1/tx_msdu_start.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h
diff --git a/hw/wcn8750/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h
similarity index 100%
rename from hw/wcn8750/v1/tx_peer_entry.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h
diff --git a/hw/wcn8750/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h
similarity index 100%
rename from hw/wcn8750/v1/tx_queue_extension.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h
diff --git a/hw/wcn8750/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h
similarity index 100%
rename from hw/wcn8750/v1/tx_rate_stats_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h
diff --git a/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
similarity index 100%
rename from hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h
diff --git a/hw/wcn8750/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h
similarity index 100%
rename from hw/wcn8750/v1/txpcu_buffer_basics.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h
diff --git a/hw/wcn8750/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h
similarity index 100%
rename from hw/wcn8750/v1/txpcu_buffer_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h
diff --git a/hw/wcn8750/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h
similarity index 100%
rename from hw/wcn8750/v1/txpcu_user_buffer_status.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h
diff --git a/hw/wcn8750/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h
similarity index 100%
rename from hw/wcn8750/v1/u_sig_eht_su_mu_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h
diff --git a/hw/wcn8750/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h
similarity index 100%
rename from hw/wcn8750/v1/u_sig_eht_tb_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h
diff --git a/hw/wcn8750/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h
similarity index 100%
rename from hw/wcn8750/v1/unallocated_ru_160_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h
diff --git a/hw/wcn8750/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h
similarity index 100%
rename from hw/wcn8750/v1/uniform_descriptor_header.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h
diff --git a/hw/wcn8750/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_a_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_mu160_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_mu20_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_mu40_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_mu80_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_su160_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_su20_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_su40_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h
diff --git a/hw/wcn8750/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h
similarity index 100%
rename from hw/wcn8750/v1/vht_sig_b_su80_info.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h
diff --git a/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
similarity index 100%
rename from hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h
diff --git a/hw/wcn8750/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h
similarity index 100%
rename from hw/wcn8750/v1/wbm_buffer_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h
diff --git a/hw/wcn8750/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h
similarity index 100%
rename from hw/wcn8750/v1/wbm_link_descriptor_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h
diff --git a/hw/wcn8750/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h
similarity index 100%
rename from hw/wcn8750/v1/wbm_release_ring.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h
diff --git a/hw/wcn8750/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h
similarity index 100%
rename from hw/wcn8750/v1/wbm_release_ring_rx.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h
diff --git a/hw/wcn8750/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h
similarity index 100%
rename from hw/wcn8750/v1/wbm_release_ring_tx.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h
diff --git a/hw/wcn8750/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h
similarity index 100%
rename from hw/wcn8750/v1/wcss_seq_hwiobase.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h
diff --git a/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
similarity index 100%
rename from hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h
diff --git a/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
similarity index 100%
rename from hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h
diff --git a/hw/wcn8750/v1/wcss_version.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h
similarity index 100%
rename from hw/wcn8750/v1/wcss_version.h
rename to drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h